Achronix Speedster22i User Manual Memory PHY
1
Speedster22i Memory PHY
User Guide
UG043 – April 26, 2014
UG043, April 26, 2014
Copyright Info
Copyright © 2013 Achronix Semiconductor Corporation. All rights reserved. Achronix is a
trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation.
All other trademarks are the property of their prospective owners. All specifications subject
to change without notice.
NOTICE of DISCLAIMER: The information given in this document is believed to be accurate
and reliable. However, Achronix Semiconductor Corporation does not give any
representations or warranties as to the completeness or accuracy of such information and
shall have no liability for the use of the information contained herein. Achronix
Semiconductor Corporation reserves the right to make changes to this document and the
information contained herein at any time and without notice. All Achronix trademarks,
registered trademarks, and disclaimers are listed at http://www.achronix.com and use of this
document and the Information contained therein is subject to such terms.
2 UG043, April 26, 2014
3
Table of Contents
Copyright Info .................................................................................................... 2
Table of Contents .............................................................................................. 3
Overview ............................................................................................................ 4
DDR PHY ............................................................................................................ 7
Organization and Interfaces ................................................................................................... 7
PHY Structure and Operation .............................................................................................. 10
PHY – Controller Interfacing through Widebus .................................................................... 11
Byte Lane Building Blocks.................................................................................................... 12
TX, RX and OE paths in Data Bits ....................................................................................... 14
DQS Clocking and Circuitry ................................................................................................. 16
DLL Specs and Operation ............................................................................... 17
Revision History .............................................................................................. 20
UG043, April 26, 2014
Overview
Core Fabric
SerDes
SerDes
Protocol Hard IP
Protocol Hard IP
General Purpose IO Buffer
IO Register PHY and DLL
Hard DDR Controllers
General Purpose IO Buffer
IO Register PHY and DLL
Hard DDR Controllers
PLLs
PLLs PLLs
PLLs
Soft DDR3
Controller
Application
Interface
QDRII+
Controller
RLDRAM3
Controller
Speedster22i HD devices have a flexible and feature rich PHY with building blocks to
implement a PHY capable of interfacing with the hard DDR3 memory controller or soft
memory controller interfaces in the FPGA fabric.
This User Guide will review these building blocks and how they are assembled to build the
PHY circuitry needed for commonly used memory interfaces.
Before diving into the details, it is worthwhile understanding how the FPGA is organized to
put the PHY into context. Figure 1 below shows a top-level view of a Speedster22iHD FPGA,
how the SerDes, IO and hard IP are organized, and how a memory interface would be built
using the hardened PHY and a soft controller.
Figure 1: Speedster22iHD Architecture for Memory Interface Design using Soft Controller
The IO in the Speedster22iHD devices is organized into 12 IO byte-lanes. Within this 12, there
are 10 DQ, 1 DQS and 1 DQSn IOs. The PHY implementation for all bits are the same, but
there are differences in top-level connectivity between the IOs implementing these different
functions. More importantly, there are differences in connectivity even for the same
DQS/DQSn bit across byte-lanes. This means that even for soft memory controller
implementations, there are IO placement restrictions, and it is important that Achronix
guidelines be followed to ensure that the particular memory interface PHY can be legally and
4 UG043, April 26, 2014
successfully implemented, and optimized to be able to timing close in the fabric.
5
As stated above, there are 12 IOs in a byte-lane. A group of byte-lanes make up an IO bank
Byte-Lanes
0-3
(48 IOs)
Byte Lanes
4-7
(48 IOs)
Byte Lanes
8-12
(60 IOs)
Core Fabric
West-North (WN) IO Cluster
Clock Region West 1
Clock Region West 2
Clock Region West 3
and 3 IO banks build an IO cluster (denoted using the initials EN, EC, ES, WN, WC, WS for
location). There are a total of 13 byte-lanes (or 156 IOs) per IO cluster, with the IO banks
being organized as 2 groups of 4 byte lanes and 1 group of 5 byte lanes.
Every IO cluster is powered by a separate set of power balls and so the power profile and
chacteristics of the respective rails will depend on the activity of those specific IOs.
An IO cluster is able to provide no more than 2 clocks (a half-rate and a quarter-rate) to the
corresponding triplet of clock regions. For source-synchronous operations where the clock
needs to be transmitted from the PHY to the FPGA fabric, the amount of logic that can be
clocked using this source-synchronous implementation will be limited by this architecture
(unless additional FIFOs/sync logic is used to transfer to a global clock domain in the
memory interface PHY). This concept is illustrated in Figure 2 below. Figure 3 shows a blovk
level diagram of the IO layout across the FPGA.
Figure 2: Speedster22iHD IO Bank and Clock Region Organization for West North Cluster
UG043, April 26, 2014
Core Fabric
WN IO
Cluster
WN Hard DDR3
Controller
WC IO
Cluster
WC Hard DDR3
Controller
WS IO
Cluster
WS Hard DDR3
Controller
EN Hard DDR3
Controller
EC Hard DDR3
Controller
ES Hard DDR3
Controller
EN IO
Cluster
EC IO
Cluster
ES IO
Cluster
Figure 3: Speedster22iHD IO Cluster Organization
The next sections will discuss the actual PHY implementation for the different memory
interfaces in more detail.
6 UG043, April 26, 2014
Loading...