Achronix Speedster22i User Manual DDR

Speedster22i DDR3 Controller

User Guid e

UG031 – Nov 18, 2014

UG031, Nov 18, 2014

1

Copyright Info

Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a
trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation.
All other trademarks are the property of their prospective owners. All specifications subject
to change without notice.

NOTICE of DISCLAIMER: The information given in this document is believed to be accurate
and reliable. However, Achronix Semiconductor Corporation does not give any
representations or warranties as to the completeness or accuracy of such information and
shall have no liability for the use of the information contained herein. Achronix
Semiconductor Corporation reserves the right to make changes to this document and the
information contained herein at any time and without notice. All Achronix trademarks,
registered trademarks, and disclaimers are listed at
document and the Information contained therein is subject to such terms.

http://www.achronix.com and use of this

2 UG031, Nov 18, 2014

Table of Contents

Table of Figures ................................................................................................. 4

Features ............................................................................................................. 6

Introduction ....................................................................................................... 7

Interfaces ........................................................................................................... 9

Internal (core) Interface .......................................................................................................... 9

External (off-chip) Interface .................................................................................................. 11

Parameters .......................................................................................................................... 11

Address Mapping ............................................................................................ 14

Write Interface Details ..................................................................................... 15

Back-to-Back Write Protocol 2X Cloc k Mode ....................................................................... 19

Write Protocol with Wide Bus Interface Enabled .................................................................. 21

Read Interface Details ..................................................................................... 23

Back-to-Back Read Protocol 2X Clock Mode ....................................................................... 25

Read Protocol with Wide Bus Interface Enabled .................................................................. 27

Memory Interface Latency .............................................................................. 30

Customization using ACE ............................................................................... 31

Revision Histor y .............................................................................................. 32

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Tabl e of Fig ur es

Figure 1: Location of Speedster22i DDR Controllers and PHYs ............................................................... 5

Figure 2: Top-level Overview of Embedded DDR Control Logic ............................................................... 7

Figure 3: Address mapping of ‘ddr_int_addr’ Signal ............................................................................... 14

Figure 4: Write Interface 2X Clock Mode ................................................................................................. 15

Figure 5: Internal Interface Write Protocol Timing Diagram .................................................................. 16

Figure 6: Internal Interface Write Protocol Timing Diagram with default value ‘addrcmd_delay’ to 8 . 17

Figure 7: Write Protocol Timing Diagram (SDRAM Interface) ............................................................... 18

Figure 8: Write Protocol Timing Diagram (Write requests with valid writes highlighted)...................... 19

Figure 9: Write Protocol Timing Diagram (ddr_int_wrdata_req corresponding to respective writes

highlighted) ............................................................................................................................................... 20

Figure 10: Write Interface with Wide Bus Interface Enabled ................................................................... 22

Figure 11: Internal Interface Write Protocol Timing Diagram with Wide Bus Interface Enabled .......... 22

Figure 12: Read Interface 2X Clock Mode ............................................................................................... 24

Figure 13: Internal Interface Read Protocol Timing Diagram ................................................................. 24

Figure 14: External Interface Read Protocol Timing Diagram ................................................................ 25

Figure 15: Read Protocol Timing Diagram (with valid read request highlighted) .................................. 26

Figure 16: Read Protocol Timing Diagram (with ddr_int_rddata_valid highlighted) ............................. 26

Figure 17: Read Interface with Wide Bus Interface Enabled ................................................................... 28

Figure 18: Internal Interface Read Protocol Timing Diagram with Wide Bus Interface Enabled ........... 28

Figure 19: DDR3 Customization using ACE ............................................................................................ 31

4 UG031, Nov 18, 2014

Overview

Speedster22i FPGA

DDR PHY

DDR Controller

DDR Memory

(off-chip)

Speedster22i Core

WN

WS

EN

ES

EC

WC

Achronix’s Speedster22i FPGAs contain up to six embedded DDR controllers which can be
used to interface with and control off-chip DDR2 or DDR3 memory devices, including
DIMMs. Each of the DDR controllers supports up to 72 bits of data and speeds of up to 1866
Mbps. The embedded DDR controllers and PHYs are implemented as Hard-IP blocks in the
frame of the Speedster22i FPGAs as illustrated in Figure 1 below.

UG031, Nov 18, 2014

Figure 1: Location of Speedster22i DDR Controllers and PHYs

Speedster22i DDR controllers support both “auto” and “custom” modes. Under the “auto”
mode functions such as (but not limited to) activating/precharging banks/rows, calibration
algorithms, and initialization sequences are handled by the embedded DDR Controller and
are transparent to the user. The mapping of byte-lanes to pins is also handled transparently
as the IOs are included in embedded DDR PHY Macro.

Under “custom” mode the user has the option to manually override functions such as
automated refresh and initialization engines/sequences.

5

Features

The features supported by the embedded DDR controllers are highlighted below:

• 1866 Mbps data rate

• The controller and PHY can run at 1066 MHz to achieve 1866 Mbps rate at the

memory interface. A 2X Clock setting enables the core to run at half the speed ­533MHz. There is an additional feature to enable a wide bus interface, which
effectively enables the core to run at one quarter the speed - 266MHz. The 2X
clock setting and wide bus interfaces can be enabled at any data rate, thereby
reducing the core frequency by half, or a quarter, respectively.

• 4 Chip Selects per controller

• The external memory connected to each controller can comprise of up to 4 ranks

(either two dual-rank DIMMs or one quad rank DIMM)

• Registered DIMM and Unbuffered DIMM support

• Each controller can independently support either rDIMMs or uDIMMs

• Address mirroring is supported.

• Multi-Burst Mode

• Each controller supports multi-burst mode, up to a burst length of 252 (DDR2) /

254 (DDR) / 248(DDR3). This allows the embedded controller to automatically
issue up to 252 cascaded read or write commands to automatically increment
addresses based on a single command from the Core Fabric

• Backwards Compatible

• The embedded DDR controllers can support DDR3 (up to 1866 Mbps), DDR2 (up

to 800 Mbps) and DDR protocols

• Bypassable

• If the user does not require all six DDR controllers, any (or all) can be bypassed

to leverage use of the designated I/Os for other purposes

• If the user does not require all 72-bits of the data bus, unused byte lanes can be

bypassed to leverage use of the designated I/Os for other purposes

• Minimal LUT use

• The DDR controllers are embedded (hardened), and therefore do not use any of

the LUTs in the core fabric

• LUTs are only required to interface the DDR Controllers

• Zero License fees

6 UG031, Nov 18, 2014

Introduction

Speedster22i

DDR Control Macro

ACX_PLL

DDR

Controller

clk

sd_dummy[8:0]

sd_dm[8:0]

sd_dqsn[8:0]

sd_dqsp[8:0]

sd_dq[71:0]

sd_cke[3:0]

sd_clk_out_p[3:0]
sd_clk_out_n[3:0]

sd_reset_n

sd_cas_n
sd_ras_n

sd_we_n
sd_a[15:0]
sd_ba[2:0]

sd_cs_n[3:0]

sd_odt[3:0]

Read/Write

Shared Interface

Write Interface

Read Interface

General Memory
Control Interface

Manual refresh

control Interface

Control

Interface

DDR Internal Interface

(User Logic)

ddr_int_clk_div2

ddr_int_zq_cal_ack

ddr_int_ref_ack

ddr_int_busy_align

ddr_int_busy

ddr_int_wrdata_valid

ddr_int_wrdata_req[8:0]
ddr_int_wrdata_req_early[8:0]
ddr_int_wrdata_req_align[8:0]

ddr_int_wrdata_req_early_align[8:0]

ddr_int_rddata[287:0]

ddr_int_rddata_valid [8:0]

ddr_int_rddata_valid_align[8:0]

ddr_int_rddata_valid_early[8:0]

ddr_int_rddata_valid_early_align[8:0]

ddr_int_init_ack

ddr_int_init_wlvl_done

ddr_int_cmd_auto_pch

ddr_int_cmd_self_refresh[1:0]

ddr_int_addr[33:0]

ddr_int_burst_size[7:0]

ddr_int_wr_request

ddr_int_wrdata[287:0]

ddr_int_wrdata_mask[17:0]

ddr_int_rd_request

reset_ddr_ctrlr_n
reset_ddr_phy_n

ddr_int_phy_ci_slave_dqsn_en

ddr_int_cmd_power_down[1:0]

ddr_int_cmd_ref_req

ddr_int_cmd_zq_cal_req[1:0]

ddr_int_phy_ci_slave_adj

DDR
PHY

External

DDR Memory

UG031, Nov 18, 2014

Speedster22i devices contain up to six embedded (Hardened) DDR Controllers. The
instantiatable macros for these are called ‘ddr3_xSIZE
configured as 72,64,32,16 or 8 and location can be EN,EC,ES,WN,WC,WS for a device with
six controllers, such as the Speedster22i HD1000. Each Macro is comprised of a DDR
Controller and a DDR PHY, and is controlled by the user by means of the DDR driver logic.

The DDR3 controller macros manage the interface between the DDR driving logic (housed
within the Core Fabric) and the off-chip DDR memory itself. A more detailed description of
these interfaces is illustrated in Figure 2 below.

Figure 2: Top-level Overview of Embedded DDR Control Logic

1

_LOCATION2’ where size can be

7

The embedded DDR controller macro function performs:

• All required initialization sequences such as the programming of AL and CL values

based on user-defined parameters

• All required calibration algorithms. This includes

 Write levelization
 DQS Enable (to control read-write turnaround of DQ/DQS bi-directional

busses)

 DQS Delay (to skew the DQS by 90 degrees relative to the corresponding

DQ, such that the latter can be sampled in the middle of the bit transition)

• Translation of READ and WRITE requests received from the DDR driver into DDR

protocol i.e. RAS, CAS and WE

• Translation of data to and from SDR to DDR

• Maintaining integrity of memory contents by issuing periodic auto-refresh and zqcal

commands

• Managing the activating and pre-charging of memory banks and rows, as required

• Managing the driving of the memory address pins (with column or row information,

as well as A10 function (precharge-all, auto-precharge, etc)

• Providing a data request signal (‘ddr_int_wrdata_req’) to the DDR driver logic, some

number of cycles after a corresponding write transaction request is received. The
customer logic should be capable of reacting to ddr_int_wrdata_req correctly”. This
ensures that CAS latency, additive latency and burst length are all managed
internally to the Speedster22i DDR controller. It also provides early data request
signal (‘ddr_int_wrdata_req_early’) which can be used if more time is required to
generate data.

• Provides data request signal (‘ddr_int_wrdata_req_align’) and early data request

signal (‘ddr_int_wrdata_req_early_align’) because the wide bus interface or 2X Clock
mode should always be selected for 1866Mpbs.

• Providing a read data valid signal (‘ddr_int_rddata_valid’) to accompany read data

provided in response to a read request. This ensures that the round-trip latency to
(and through) the memory is managed internally to the Speedster22i DDR controller.
It also provides early data valid signal (‘ddr_int_rddata_valid_early’) which can be
used to latch read data.

• Provides data request signal (‘ddr_int_rddata_valid_align’) and early data valid

signal (‘ddr_int_rddata_valid_early_align’) if the wide bus interface or 2X Clock
mode is selected for 1866 Mbps.

• Provide signal (‘ddr_int_busy’) to DDR Driver logic to indicate that the DDR3

Controller is busy and is not accepting new requests.

8 UG031, Nov 18, 2014

Interfaces

Bus

Width

Driven by user. Clock signal. This is the reference clock

In 2X Clock mode the clock from PHY will be at half the

from core to controller

When the wide bus interface is enabled, the clock from PHY

used to send and receive data from core to controller

reset_ddr_phy_n

1

Input

Driven by user. Reset to PHY. Asserted active low.

reset_ddr_ctrlr_n

1

Input

Driven by user. Reset to DDR controller. Asserted active low.

Indicates that the DDR3 Controller is busy and is not accepting

When the wide bus interface is enabled and in 2X clock mode,
indicates that the DDR3 Controller is busy and is not accepting
new requests.

ddr_int_addr

34

Input

Address bus containing row, column, and bank information.

Indicates burst size of given read/write request.

8’d4  8’d252 (multiples of 4) for DDR3

ddr_int_wr_request

1

Input

Write request.

Request by DDR Controller for data to be written to the DDR

length per write request.

Early request by DDR controller for data to be written to the

‘ddr_int_wrdata_req’ which can be used.

When the wide bus interface is enabled and in 2X Clock mode,

timing purposes.

When the wide bus interface is enabled and in 2X Clock mode,

provided as a multi-bit signal for timing purposes.

Data to be written to the DDR Memory. This data is provided

parameters and consequently the bus width, are doubled.

Data mask corresponding to “ddr_int_wrdata”. When any

Memory. SIZE: 72, 64, 32, 16, 8. When the wide bus interface is

Internal (core) Interface

The internal interface to the PHY/DDR controller, which is implemented in the core fabric, contains the
following interface signals as listed below in table 1.

Signal Name

clk 1 Input

ddr_int_clk_div2 1 Output

ddr_int_clk_div4 1 Output

ddr_int_busy 1 Output

ddr_int_busy_align 1 Output

ddr_int_burst_size 8 Input

ddr_int_wrdata_req 9 Output

Direction

Description

coming in from the board.

controller clock which should be used to send and receive data

will be at one quarter the controller clock which should be

new requests.

Valid ranges of this value are:

Memory. This is asserted some number of clock cycles after a
write request, and is burst length number of clock cycles in

ddr_int_wrdata_req_early 9 Output

ddr_int_wrdata_req_align 9 Output

ddr_int_wrdata_req_early_align 9 Output

ddr_int_wrdata

ddr_int_wrdata_mask

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[SIZE*4-

1:0]

[SIZE/2-

1:0]

Input

Input

DDR memory. Signal will be asserted earlier then

request by DDR Controller for data to be written to the DDR
Memory. This signal bus essentially performs a single
alignment function but is provided as a multi-bit signal for

early request by DDR Controller for data to be written to the
DDR Memory. Signal will be asserted earlier then
‘ddr_int_wrdata_req_align’ which can be used. This signal bus
essentially performs a single alignment function but is

two cycles after ddr_int_wrdata_req is asserted. SIZE: 72, 64,
32, 16, 8. When the wide bus interface is enabled, the SIZE

data mask bit is asserted, the data contained in the
corresponding ‘ddr_int_wrdata’ byte will not be written to

9

enabled, the SIZE parameters and consequently the bus width,
are doubled.

ddr_int_rd_request

1

Input

Read request.

ddr_int_rddata

Data read back from the DDR Memory in response to a read

abled, the SIZE parameters and consequently the bus width,

are doubled.

ddr_int_rddata_valid

9

Output

Valid signal corresponding to read data (‘ddr_int_rddata’).

Early valid signal corresponding to read data
(‘ddr_int_rddata’)

When the wide bus interface is enabled and in 2X clock mode,
valid signal corresponding to read data (‘ddr_int_rddata’)

When the wide bus interface is enabled and in 2X clock mode,

(‘ddr_int_rddata’)

ddr_int_cmd_auto_pch

1

Input

Core can send a Auto pre charge request to controller

Core can send a power down request to controller. Each signal
[1:0] controls each SDRAM on its chip select.

User-initiated refresh control. Core can send a refresh request
to controller (manual control).

ddr_int_ref_ack

1

Output

Refresh acknowledgement from controller to core

Self refresh control. Causes the DDR3 SDRAM Controller Core

select.

User initialized ZQ calibration. User can initiate ZQ calibration

SDRAM on its chip select.

ZQ calibrations acknowledge. Asserted for one clock when ZQ
calibration command is issued to memory devices.

Frames the active data being written to SDRAM. Mimics
‘ddr_int_wrdata_req’ except it is delayed by one clock.

ddr_int_phy_ci_slave_adj

8

input

ddr_int_phy_ci_slave_dqsn_en

9

Input

*based on data width

ddr_int_phy_co_wr_lvl_out

9

Output

*based on data width

Asserts for one clock to acknowledge init_refresh,

ddr_int_init_wlvl_done

1

Output

Indicates completion of write leveling

Delay line value determined by write leveling calibration

the DQS lane selected by ‘**’ parameter **

Indicates that controller-driven automatic write leveling is in
progress.

ddr_int_rddata_valid_early 9 Output

ddr_int_rddata_valid_align 9 Output

[SIZE*4-

1:0]

Output

request. SIZE: 72, 64, 32, 16, 8. When the wide bus interface is
en

ddr_int_rddata_valid_early_align 9 Output

ddr_int_cmd_power_down 2 Input

ddr_int_cmd_ref_req 1 Input

ddr_int_cmd_self_referesh 2 Input

ddr_int_cmd_zq_cal_req 2 Input

ddr_int_zq_cal_ack 1 Output

ddr_int_wrdata_valid 1 Output

ddr_int_init_ack 1 Output

early valid signal corresponding to read data

to put the SDRAM into self refresh mode at the next refresh
event. Each signal [1:0] controls each SDRAM on its chip

at next available opportunity. Each signal [1:0] controls each

init_precharge_all, init_mr, init_zq_cal, and
init_wlvl_mrX_req. **

status_wlvl_tap_value 9 Output

wlvl_active 1 Output

10 UG031, Nov 18, 2014

inside DDR3 controller. The value on this port corresponds to

Table-1: Internal interface signals