LaneLinx
TM
User Guide
UG035 (v1.0) – March 19, 2012
UG035 (v1.0), March 19, 2012
1
Table of Contents
Introduction ....................................................................................................... 3
LaneLinx Overview ............................................................................................ 3
XG_Lanelinx Details .......................................................................................... 5
LaneLinx2p5g: ....................................................................................................................... 5
Link_FSM: .............................................................................................................................. 5
The Link_Training block ................................................................................................................. 7
TX_data_module .................................................................................................................... 7
RX_data_module: .................................................................................................................. 7
XG_Lanelinx Pin Description ............................................................................ 8
Reference Design .............................................................................................. 9
Revision History ................................................................................................ 9
2 UG035 (v1.0), March 19, 2012
Introduction
LaneLinxTM is a lightweight, multi-gigabit per second serial protocol. It enables high bandwidth, serial
connectivity with minimal programmable resource requirements, enabling lightweight, high performance data
links between Speedster22i devices. This communication protocol goes through a number of steps to establish a
reliable link. Once the link is established, data is transmitted and received. Each packet of data is preceded with
SOP (Start-Of-Packet) and ends with EOP (End-Of-Packet) identifiers. LaneLinx is a single channel protocol, i.e. it
uses only a single SerDes Tx/Rx lane. By leveraging the Speedster22i embedded PCS resources, the minimum
amount of programmable (LUT based) Resources.
This User Guide covers the 2.5Gbps version of LaneLinx. Other speeds are available and have near identical
construction.
LaneLinx Overview
The LaneLinx Macro has 4 main sub-components contained within the top level RTL (XG_Lanelinx)
1. LaneLinx2p5G – the HardIP SerDes instantiation
2. TX_data_module
3. RX_data_module
4. Link_FSM block
The LaneLinx Macro is delivered with a reference design which provides a sample instantiation of XG_Lanelinx
connected to data generation and data compare blocks. When a SerDes loopback is used, (in simulation or in real
hardware), the data generation and compare blocks are self-checking. The data generation and data compare
blocks also include data packetization (start of packet and end of packet), and important part of the protocol
Figure 1 below shows the blocks within the XG_Lanelinx macro and how the reference design components are
connected to the Macro.
UG035 (v1.0), March 19, 2012
3
Figure 1 – LaneLinx Block diagram
4 UG035 (v1.0), March 19, 2012
XG_Lanelinx Details
LaneLinx2p5g:
This block is the instantiation of the Hard SerDes IP contained within the Speedster22i Frame. For the
included example implementation we have already created a 2.5 Gbps SerDes Macro. To change the
data rate, a new SerDes Macro can be generated using the ACE IP Generator GUI. If a new macro is
generated, it can simply be used as a drop in replacement for the existing one.
The Key internal signals from the SerDes macros are
• lane0_o_pma_sig_detect
• lane0_o_pma_txready
• lane0_o_pma_rxready
• lane0_o_pma_synthready
• lane0_o_rx_data_clk
• laneo_o_tx_data_clk
• lane0_o_rx_syma_locked
Figure 2 below shows how the Speedster22i SerDes pins should be asserted during correct start up
The “Link_FSM” block will respond based on the value of these signals
Link_FSM:
This is the main control block for implementing the LaneLinx protocol. This controls data flow based
on incoming data (in both the TX and RX directions) as well as based on the status of the Key SerDes
signals:
• lane0_o_pma_sig_detect
• lane0_o_pma_txready
• lane0_o_pma_rxready
• lane0_o_pma_synthready
• lane0_o_rx_data_clk
• lane0_o_tx_data_clk
• lane0_o_rx_syma_locked
UG035 (v1.0), March 19, 2012
Figure 2 – Correct operation of SerDes pins
5
The signals
• lane0_o_pma_txready and
• lane0_o_pma_rxready
are OR’ed together to create a signal called “lane_ok”
The FSM diagram for Link_FSM is shown below in Figure 3.
Figure 3 – Link_FSM block state diagrams
In this state machine, the LINK_INITIALIZED state will ensure that both ends of the link are
properly initialized.
• During link training, IDLE (//I//) ordered set will be transmitted.
• The receiver will constantly hunt for //I// ordered set.
• The embedded PCS block will recognize the IDLE ordered set and automatically align to the
sync (//K//) and skip (//R//) characters.
• Link initialization failure will be set if no IDLE is detected by the receiver.
• The user will have the option to reinitialize link training in the event of link failure.
• The IDLE ordered set will be transmitted continuously on the lane whenever the link is idle
i.e. no data is present for transmission.
• The Sync (//K//) character is used for comma-detection by the receiver. It maps to K28.5.
• Skip (//R//) character is used for rate matching between the receiver and transmitter. The skip
character maps to K28.0.
• The receiver must flag to the far-end device that it has detected and locked on to the IDLE
ordered sequence. This can be achieved by sending the sequence ordered set once the initial
10 µsecs counter inside LaneLinx has expired.
• The sequence ordered set is - Sync (//K//) K28.5 and Skip (//R//) K28.0 always transmitted first
and after initialized then the D10.2 will be transmitted.
• The sequence ordered set will be recognized by the LaneLinx state machine.
• After the LINK_INITIALIZED signal gets asserted, then this block send the 16-bit parallel
data to the “rx_data_module” block.
6 UG035 (v1.0), March 19, 2012
The Link_Training block
This block generates the training signal for linking up the channel at the required data-rate. This
block generates the transmit data and control signals, which depend on the SKIP, SYNC and
SEQUENTIAL-PATTERN values. This block is also a multiplexor between the link training pattern
and link initialization pattern controlled by the Link_FSM block.
The signal from the SerDes macro “lane0_o_rx_syma_locked” (which is called “serdes_aligned” in
this block) is used to generate the training order pattern. The training pattern is “9C4A”.
TX_data_module
Upon receiving the data, Start-Of-Packet, End-Of-Packet and transmit data valid signals from the
external interface (e.g. TX_data_gen block or custom user interface) the transmit-ready signal is
generated, as well as the transmit control signal and the 16-bit parallel data values will be generated
to transmit to the SerDes block. The generated transmit ready signal will be propagated to the
external interface in this reference design “tx_data_gen” block.
RX_data_module:
This block receives the aligned 16-bit parallel data, control signal and link initialized signal value
from the Link_FSM block. Upon receiving these signals this block will generate Start-Of-Packet, End-
Of-Packet, the properly aligned 16-bit data, receive data valid signal for the external interface (in this
reference design it is “RX_data_compare” block).
UG035 (v1.0), March 19, 2012
7
XG_Lanelinx Pin Description
ref_clk_p
Input.
Reference clock p
-
side
(Differential clock
-
pin)
ref_clk_n
Input.
Reference clock n
-
side (Differential clock
-
pin)
resetn
Input.
Active Low reset line
Input.
Serial Data to SerDes p
-
side
Input.
Serial Data to SerDes n
-
side
Input
. Indicates
that the input data is valid
Input.
Indicates start
-of-
packet
Input.
Indicates end
-of-
packet
Input
. Error character must be inserted. At this moment we don’t support
tx_data_in_ch0[15:0]
Input.
Parallel data. Width is 16 bits wide.
tx_valid_bytes_ch0
Input.
Number of valid bytes in the data values
tx_ch0_p
Output.
Serial Data from SerDes p
-
side
Output.
Serial Data from SerDes n
-
side
Output.
Parallel data from rx_data_module block. Width is 16 bits wide.
Output.
Number of valid bytes in data out
Output.
Indicates that the output data is valid
Output.
Indicates start
-of-
packet
Output.
Indicates end
-of-
packet
rx_err_ch0
Output.
Indicates detection of 8b/10b decode or disparity error
tx_ready_ch0
Output.
Indicates that bus is ready for data transmission
serdes_tx_clk_ch0
Output.
SerDes Transmit clock from the SerDes macro.
Output.
SerDes Receive clock from the SerDes macro.
Output.
Will be used for Chip
-
Tap debugging tool.
Output.
Will be used for Chip
-
Tap debugging tool.
Output.
ACX SerDes pin which indicates the signal detection. Will be used
Output.
Link initialization signal from FSM block. Will be used in Chip
-
Tap
rx_data_is_good_ch0
Output.
Indicates that the 16
-
bit data out values are good (no corruption or
rx_switch_data_ch0
Output.
Indicates that depending on the SKIP & SYNC character, the 16
-
bit
rx_skip_ch0
Output.
This is to detect SKIP character values of 1C1C pattern. Will be
Output.
This is to detect SYNC character values of BCBC pattern.
Will be
Output.
This is to detect if there is any combination of 1CBC pattern. Will
Output.
This is to detect if there is any combination of BC1C pattern. Will
Output.
This is receiving side aligned data. 16
-
bit wide. Will be used in
Signal Description
rx_ch0_p
rx_ch0_n
tx_data_valid_ch0
tx_sop_ch0
tx_eop_ch0
tx_err_ch0
it. It is tied to 1’b0
tx_ch0_n
rx_data_out_ch0 [15:0]
rx_valid_out_bytes_ch0
rx_data_valid_ch0
rx_sop_ch0
rx_eop_ch0
serdes_rx_clk_ch0
MISCELLENEOUS PINS WILL BE USED FOR ACX Chip-Tap Block for Debugging
debug_bus0[4:0]
debug_bus1[17:0]
sig_detect_ch0
in chip-Tap debugging tool.
link_initialized_ch0_tx
debugging tool.
error). Will be used in Chip-Tap debugging tool.
will be switched as [{7:0,15:9}]. Will be used in Chip-Tap debugging tool.
used in Chip-Tap debugging tool.
rx_sync_ch0
used in Chip-Tap debugging tool.
rx_skip_sync_ch0
be used in Chip-Tap debugging tool.
rx_sync_skip_ch0
be used in Chip-Tap debugging tool.
rx_aligned_data_ch0[15:0]
Chip-Tap debugging tool.
8 UG035 (v1.0), March 19, 2012
Reference Design
The Reference Design consists of two blocks, TX_data_gen and RX_data_comp.
1. TX_data_gen:
This block generates data which is transmitted through a parallel interface to the
LaneLinx Macro. The block also generates Start-of-Packet and End-of-Packet signals
depending on whether the signal “tx_ready” is asserted by XG_LaneLinx block.
2. RX_data_comp:
After transmission has completed the LaneLinx protocol does the RX-data comparison to
see that the RX side packet reception is OK or not. If the RX data is validated this block
asserts “compare_ok” signal saying that the data is good, otherwise it asserts bad-data
indicator.
Revision History
The following table shows the revision history for this document.
Date Version Revisions
3/19/2012 1.0 Initial Achronix release.
UG035 (v1.0), March 19, 2012
9
Loading...