Achronix Speedster22i User Guide
1
ACX-KIT-HD1000-100G
Development Kit
User Guide
UG034, July 1, 2014
UG034, July 1, 2014
Copyright Info
Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a
trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation.
All other trademarks are the property of their prospective owners. All specifications subject
to change without notice.
NOTICE of DISCLAIMER: The information given in this document is believed to be accurate
and reliable. However, Achronix Semiconductor Corporation does not give any
representations or warranties as to the completeness or accuracy of such information and
shall have no liability for the use of the information contained herein. Achronix
Semiconductor Corporation reserves the right to make changes to this document and the
information contained herein at any time and without notice. All Achronix trademarks,
registered trademarks, and disclaimers are listed at http://www.achronix.com and use of this
document and the Information contained therein is subject to such terms.
2 UG034, July 1, 2014
3
Table of Contents
Copyright Info ......................................................................................................................... 2
List of Figures ........................................................................................................................ 6
List of Tables .......................................................................................................................... 7
Preface ............................................................................................................... 8
About this Guide .................................................................................................................... 8
Target Readership (or Audience) ........................................................................................... 8
Reference Documents ........................................................................................................... 9
Conventions used in this Guide ............................................................................................. 9
Terminologies used in this Guide ........................................................................................... 9
Chapter 1 – ACX-KIT-HD1000-100G Overview ............................................... 10
ACX-KIT-HD1000-100G Kit Contents .................................................................................. 10
ACX-KIT-HD1000-100G Kit Uses ........................................................................................ 10
ACX-BRD-HD1000-100G Development Board Features ..................................................... 11
FPGA ........................................................................................................................................... 11
Functional blocks ......................................................................................................................... 11
Networking and Communications ................................................................................................. 11
System ......................................................................................................................................... 11
Board ........................................................................................................................................... 11
Interfaces ..................................................................................................................................... 11
Networking and Communications ................................................................................................. 11
System ......................................................................................................................................... 12
Controller ..................................................................................................................................... 12
Additional memories ..................................................................................................................... 12
Achronix CAD Environment (ACE) Software........................................................................ 12
Chapter 2 – General Description .................................................................... 13
ACX-BRD-HD1000-100G Development Board Picture ........................................................ 13
Use Modes ........................................................................................................................... 14
Standalone Mode ......................................................................................................................... 14
In-system (Plug-in) Mode ............................................................................................................. 14
On-Board Memory ............................................................................................................... 15
On-Board Controller ............................................................................................................. 15
Board-Specific Design Issues .............................................................................................. 16
UG034, July 1, 2014
Chapter 3 – Development Environment Setup .............................................. 17
Installing the ACE and Synopsys software and their licenses .............................................. 17
Running the software ................................................................................................................... 18
Setting up the ACX-BRD-HD1000-100G Development Board ............................................. 18
Standalone Mode ......................................................................................................................... 18
Connecting the Development PC ................................................................................................ . 18
Connecting the Power Supply ...................................................................................................... 18
In-system Mode ........................................................................................................................... 19
Connecting the Power Supply ...................................................................................................... 19
Getting started ..................................................................................................................... 20
Power Sequencing ....................................................................................................................... 20
Initialization .................................................................................................................................. 20
Downloading a Design ......................................................................................................... 20
Configuring the Board for the Appropriate Bitstream Source ........................................................ 21
Connecting the Development PC ................................................................................................ . 21
Configuring the HD1000 and Running the Application .................................................................. 21
JTAG............................................................................................................................................ 24
Serial............................................................................................................................................ 24
CPU ............................................................................................................................................. 24
FLASH Programming ................................................................................................................... 24
Chapter 4 – Interfaces ..................................................................................... 25
ACX-BRD-HD1000-100G Development Board Interfaces ................................................... 27
Networking and Communications Interfaces ................................................................................ 28
CFP Cage for 100GE Line Interface ............................................................................................. 28
Interlaken Interface (AirMax Connector Pair)................................................................................ 30
FMC Expansion Port (HPC, J3).................................................................................................... 32
System Interfaces ........................................................................................................................ 37
PCI Express ................................................................................................................................. 37
USB (U54, U41) ........................................................................................................................... 38
JTAG (J11) .................................................................................................................................. 39
Controller Interfaces ..................................................................................................................... 40
Memory Interfaces ....................................................................................................................... 40
SO-DIMM Socket (J41) ................................................................................................................ 40
One DDR3 Device (U21) .............................................................................................................. 41
RLDRAM3 Devices (U31, U36) .................................................................................................... 42
QDR2+ Device (72 Mb) ................................................................................................................ 45
User Interfaces ............................................................................................................................. 48
Bitporter CLI ................................................................................................................................. 48
ACE GUI ...................................................................................................................................... 48
SMA Connectors .......................................................................................................................... 49
Digilent connector (J29) ............................................................................................................... 50
Jumpers ....................................................................................................................................... 50
LEDs ............................................................................................................................................ 50
Switches ...................................................................................................................................... 50
Chapter 5 – Clocking ....................................................................................... 52
4 UG034, July 1, 2014
5
Chapter 6 – Atmel Microcontroller ................................................................. 55
Temperature Sensing and Reporting ................................................................................... 55
Power Measurement and Reporting .................................................................................... 55
Embedded Control ............................................................................................................... 55
Appendix A – HD1000 Pins and their connections to the SO-DIMM Socket 57
Appendix B – LEDs, Buttons, Jumpers, and Switches ................................. 62
LEDs .................................................................................................................................... 62
Buttons ................................................................................................................................. 62
Jumpers ............................................................................................................................... 63
Switches............................................................................................................................... 66
Appendix C – Troubleshooting ...................................................................... 68
Appendix D – Revision History ...................................................................... 69
UG034, July 1, 2014
List of Figures
Figure 1: ACE Development Environment............................................................................................... 12
Figure 2: ACX-BRD-HD1000-100G Development Board Picture .......................................................... 13
Figure 3: Standalone Use Mode ................................................................................................................ 14
Figure 4: In-System Use Mode ................................................................................................................. 15
Figure 5: Software Development Environment ........................................................................................ 18
Figure 6: Standalone Board Connections ................................................................................................. 19
Figure 7: In-System Board Connections ................................................................................................... 20
Figure 8: ACX-BRD-HD1000-100G Board Configuration Modes ......................................................... 22
Figure 9: HD1000 FPGA Interfaces ......................................................................................................... 26
Figure 10: ACX-BRD-HD1000-100G Development Board Interface Overview .................................... 27
Figure 11: ACX-BRD-HD1000-100G Development Board Interface Locations .................................... 28
Figure 12: ACX-BRD-HD1000-100G JTAG Daisy Chain ...................................................................... 39
Figure 13: ACE GUI for the Bitporter Pod ............................................................................................... 49
6 UG034, July 1, 2014
7
List of Tables
Table 1: ACX-BRD-HD1000-100G Board Configuration Mode (J31) ................................................... 22
Table 2: HD1000 Configuration Mode Pins and their Connections ........................................................ 22
Table 3: HD1000 Pins and their Descriptions for Configuration ............................................................. 23
Table 4: ACX-BRD-HD1000-100G CFP Interface Pins .......................................................................... 29
Table 5: ACX-BRD-HD1000-100G Interlaken Transmitter Interface Pins ............................................. 30
Table 6: ACX-BRD-HD1000-100G Interlaken Receiver Interface Pins ................................................. 31
Table 7: ACX-BRD-HD1000-100G FMC Interface Pins ........................................................................ 32
Table 8: ACX-BRD-HD1000-100G PCIe Interface Pins ......................................................................... 37
Table 9: ACX-BRD-HD1000-100G USB Interface Connections (HD1000) ........................................... 38
Table 10: ACX-BRD-HD1000-100G USB Interface Connections (MCU) ............................................. 38
Table 11: ACX-BRD-HD1000-100G JTAG Header (J11) Pins............................................................... 39
Table 12: ACX-BRD-HD1000-100G Microcontroller Interfaces and their Connections ........................ 40
Table 13: ACX-BRD-HD1000-100G Memory Interfaces – DDR3 ......................................................... 41
Table 14: ACX-BRD-HD1000-100G Memory Interfaces – RLDRAM3 ................................................ 42
Table 15: ACX-BRD-HD1000-100G Memory Interfaces – CY7C2565XV18 ....................................... 45
Table 16: SMA Connectors and Connection to HD1000 Pins ................................................................. 49
Table 17: Digilent Connector and Connection to HD1000 Pins............................................................... 50
Table 18: Configuration Signal Pins for the HD1000 and their Connections .......................................... 50
Table 19: Crystals/Oscillators on the Board ............................................................................................. 52
Table 20: Sample DIP Switch Settings to Generate Desired Synthesizer Output Clocks ........................ 53
Table 21: Interlaken SerDes Clocks and their Connections ..................................................................... 53
Table 22: PLL Pins and their Connections ............................................................................................... 54
Table 23: Over-temperature Alert Circuitry Pin Connections .................................................................. 55
Table 24: ACX-BRD-HD1000-100G MCU Pins and their Connections ................................................. 56
Table 25: ACX-BRD-HD1000-100G SO-DIMM Socket Pins and their Connections ............................ 57
Table 26: LEDs and their Functions ......................................................................................................... 62
Table 27: Push Buttons and their Functions ............................................................................................. 62
Table 28: Jumpers and their Functions ..................................................................................................... 63
Table 29: Switches and their Functions .................................................................................................... 66
Table 30: DIP switches and their Functions ............................................................................................. 66
UG034, July 1, 2014
Preface
About this Guide
The Achronix ACX-KIT-HD1000-100G Development Kit for the AC22IHD1000-F53C3 FPGA,
delivers a practical platform for you to evaluate the Speedster22i FPGA family using the
HD1000. This guide provides details on the capabilities and use of the
ACX-KIT-HD1000-100G Kit. You will learn about the features that may be customized, the
features that are fixed, and the tools and environment required to implement your own
system designs.
This guide consists of the following chapters:
Chapter 1 – ACX-KIT-HD1000-100G Kit Overview provides an overview of the
ACX-KIT-HD1000-100G Development Kit.
Chapter 2 – General Description covers more details of the ACX-KIT-HD1000-100G Kit.
Chapter 3 – Development Environment Setup takes you through the software tools
installation and getting started.
Chapter 4 – Interfaces provides information about the interfaces that are available on the
ACX-BRD-HD1000-100G board.
Chapter 5 – SDK1000 Clocking provides details of the clocks and on-board clock
references.
Chapter 6 – Controller provides information about the on-board Atmel controller for
control, monitoring and other functions.
Appendix A – HD1000 pin connections to the SO-DIMM Socket details the signal pin
allocation on the HD1000 and their connections to the SO-DIMM socket.
Appendix B – LEDs, Buttons, Switches and Jumpers explains the functions of these
elements on the ACX-BRD-HD1000-100G board.
Appendix C – Frequently Asked Questions (FAQs) addresses potential questions that
you may have during the use of the ACX-KIT-HD1000-100G Kit.
Appendix D – Revision History highlights the revisions to this document.
Target Readership (or Audience)
This guide is intended for embedded systems and sub-systems designers working with the
Achronix HD1000, 22-nm FPGA and application developers for the Networking and
Communications markets. You should have knowledge of FPGAs, Controllers, Development
environments and other relevant technologies.
This guide does not include board design and layout information. If you want assistance with
board design and layout, please contact Achronix.
8 UG034, July 1, 2014
9
Reference Documents
Item
Format
Examples
Command-line entries
Courier bold font face
$ Open top_level_name.log
File Names
Courier font face
filename.ext
GUI buttons, menus and
radio buttons
Helvetica bold font face
Click OK to continue.
File → Open
Variables
Italic emphasis
design_dir/output.log
Window and dialog box
headings and sub-headings
Heading in quotation
marks
Under “Output Files,” select ...
Window and dialog box
names
Initial caps
From the Add Files dialog box, ...
Terminology
Synonyms
Examples
ACX-KIT-HD1000-100G
Kit, Development Board
Kit
Refers to the set of Development
Board, ACE Software tools, and
other accessories shipped with
the Board
ACX-BRD-HD1000-100G
Development Board or
Board
Refers to the Development Board
using the 22nm,
AC22IHD1000-F53C3 FPGA
AC22IHD1000–F53C3
HD1000
Refers to the Achronix FPGA
Speedster22i FPGA Family Datasheet (DS004)
ACE User Guide (UG001)
Achronix Software & License User Guide (UG002)
Bitporter User Guide (UG004)
Conventions used in this Guide
This document uses the conventions shown in the following table.
Terminologies used in this Guide
This document uses the terminologies and synonyms shown in the following table.
UG034, July 1, 2014
Chapter 1 – ACX-KIT-HD1000-100G
Components
Sub-Components
ACX-BRD-HD1000-100G Development Board
Described below
BitPorter Programming Pod
Power Supply with power cord
USB cable
7ft Ethernet cable
14-pin JTAG ribbon cable
Power Supply
ACX-KIT-HD1000-100G Kit Quickstart Guide
Achronix CAD Environment (ACE) License
Overview
In this chapter, you will learn the following about the ACX-KIT-HD1000-100G kit:
ACX-KIT-HD1000-100G Kit Contents
ACX-KIT-HD1000-100G Kit Uses
ACX-BRD-HD1000-100G Development Board Features
Achronix CAD Environment (ACE) Software
ACX-KIT-HD1000-100G Kit Contents
The Achronix ACX-KIT-HD1000-100G kit contents are as follows:
ACX-KIT-HD1000-100G Kit Uses
The Achronix ACX-KIT-HD1000-100G kit allows you to evaluate the AC22IHD1000-F53C3
FPGA. The ACX-KIT-HD1000-100G kit includes the ACX-BRD-HD1000-100G development
board, which is optimized for networking and communications applications. Ports, controls,
memories, and interfaces on the board allow you to evaluate and debug the programmable
functionality and the hardened IP in the AC22IHD1000-F53C3 device.
The kit comes with instructions to easily set up the development environment, and configure
the HD1000 device with your designs.
You can use the board as a stand-alone target or as a PCI Express card plugged into a PCIe
Gen3 x8 slot.
10 UG034, July 1, 2014
11
ACX-BRD-HD1000-100G Development Board Features
FPGA
Achronix 22-nm, AC22IHD1000-F53C3
Functional blocks
1 million equivalent LUTs (700k programmable LUTs + hardened IP)
86 Mbit on-chip memory (82 Mb BRAM, 4 Mb LRAM)
756 28x28 multiply/accumulate blocks
960 programmable user IOs
Networking and Communications
Hardened Ethernet MACs: 100GE, 40GE, 10GE
64 SerDes lanes (1 to 12.75 Gb/s)
Hardened Interlaken ports, each running up to 11.3Gbps
System
Hardened PCI Express Gen1/2/3 x1, x4, x8
Hardened DDR3 controllers: six x72 at 2.133 Gb/s
Board
PCI Express pluggable form factor
Six SMAs (Tx, Rx, Clk) for single lane SerDes access
DDR3 SO-DIMM socket
One DDR3 device
Power supply modules
Power on reset circuitry
Oscillators/ crystals/ clock modules & synthesizers
Power and temperature measurement sensors
SPI header for FLASH access
FLASH for device configuration
LEDs, switches, headers
Interfaces
Networking and Communications
CFP cage for 100GE line interface
Adaptable to 2x40GE or 10x10GE
Interlaken interface (AirMax connector pair)
135Gb/s to companion board/system
FMC expansion port (HPC)
Ten SerDes lane at 10 Gb/s
Up to 160 signals (or 80 diff) at 1.6 Gb/s
UG034, July 1, 2014
System
PCI Express Gen 3 x8, for 128 Gb/s (2 x64 Gb/s - Rx, Tx) throughput
USB
JTAG
Controller
Atmel ATmega2560
Additional memories
One DDR3 device
QDR2+ (72Mb @ 633 MHz)
Two RLDRAM3 (each 16 Mb x 36 for a total of 576 Mb @ 1066 MHz)
Achronix CAD Environment (ACE) Software
Achronix provides the ACE Software together with an Achronix-optimized version of
Synplify-Pro from Synopsys. You will need a node-locked or floating version of the license to
use the ACE Software for development. You will find more details about installation and use
in the “Development Environment Setup” chapter.
Figure 1 shows the ACE Development Environment.
Figure 1: ACE Development Environment
12 UG034, July 1, 2014
13
Chapter 2 – General Description
12 V Main and Auxiliary
Power Supply Connectors
JTAG Header for
Bitporter Pod
Connectivity
Board Power
On/Off Switch
FPGA Soft
Reset Switch
Micro SD
Card Slot
SPI Flash
Memory on flip
side of board
(Not shown)
Programming
Header
Microcontroller
Speedster22i
HD1000 FPGA
USB
Connectors
Power
Regulators
Configuration related
LEDs
Configuration related
DIP switches
FPGA Configuration
Hard Reset Switch
In this chapter, you will learn the following about the ACX-BRD-HD1000-100G Development
Board:
ACX-BRD-HD1000-100G Development Board
Use Modes
On-board Memory
On-Board Controller
Board-specific Design Issues
ACX-BRD-HD1000-100G Development Board Picture
The development board has a PCIe form-factor with an 8” (203.2mm) width. It also has
dedicated power connectors. Figure 2 shows the ACX-BRD-HD1000-100G development
board with many of the key components annotated.
UG034, July 1, 2014
Figure 2: ACX-BRD-HD1000-100G Development Board Picture
Use Modes
This section describes the standalone and in-system (or “plug-in”) use modes for the
development board. In both modes, you must provide power to the board through the
dedicated power connectors using an external power supply.
Standalone Mode
In this mode, the development board is placed on a bench, with control and data signals
coming from the surrounding interfaces, which may include the Atmel microcontroller, DIP
switches, SMAs etc. This mode is shown in Figure 3.
Figure 3: Standalone Use Mode
In-system (Plug-in) Mode
The development board is inserted into a PCIe Gen3 x8 slot of a PC. In addition to the
capabilities highlighted in the standalone mode, you may provide data traffic over the PCIe
interface in this mode, assuming you configure the PCIe interface of the FPGA appropriately.
This mode is shown in Figure 4.
Note: You will still need to provide power using an external power supply, rather than the PCIe
connector, and the dedicated power connectors on the board. Additional connectors on the PC power
supply will be sufficient.
14 UG034, July 1, 2014
15
PCIe Plug In Card
Power Supply
On-Board Memory
The development board has the following memories available for system design.
A 204-pin SO-DIMM DDR3 module with 2.133 Gb/s performance.
To use as the primary off-chip memory for all applications. This supplements the
on-chip BRAM.
To serve as a demonstration of the embedded DDR3 controller capability.
A DDR3 device (2 Gb @ 1066 MHz) soldered on the board which you can use at 2.133
Gb/s performance.
Two RLDRAM3 (each 16 Mb x 36 for a total of 576 Mb @ 1066 MHz)
A QDR2+ device (2 Mb x 36 = 72 Mb @ 633 MHz) which you can use for high-
bandwidth, low-latency, random-access requirements such as classification and policy
lookup in networking applications.
An SPI Flash device which you can use to store configuration bitstreams on board.
On-Board Controller
Figure 4: In-System Use Mode
The development board comes equipped with an on‐board, Atmel ATmega2560 AVR
microcontroller. You can use this microcontroller to perform the following tasks:
Control power sequencing of the board and any connected peripherals.
Measure the temperature captured via the on‐chip temp diode of the HD1000 FPGA.
Monitor power consumption of some of the key functional blocks.
SerDes
UG034, July 1, 2014
IOs
BRAM
Fabric
Take appropriate corrective action by the embedded control software.
Board-Specific Design Issues
The development board is optimized for Networking applications. As such, Achronix has
configured the SerDes and the IOs at specific pins on the HD1000 device. You must maintain
these in any changes that you make to the device as you work on your system development.
Achronix has made this easy for you through a template for ACE that you can use as a tool to
avoid inadvertent changes to the configuration.
You must also maintain the clocking structure implemented on the board for any changes
that you make while using the board as a development platform. For your new designs, you
may use the flexibility provided by the HD1000 to implement your own clocking schemes.
16 UG034, July 1, 2014
17
Chapter 3 – Development Environment
Setup
In this chapter, you will learn how to perform the following tasks:
Installing the ACE and Synopsys software and their licenses
Setting up the ACX-BRD-HD1000-100G Development Board
Getting started
Downloading a design
Installing the ACE and Synopsys software and their licenses
You need to perform the following steps to use the ACE Software development environment:
1. Download the required files. Typically, you will choose only ONE of the following
environments:
a. Windows Client, Windows Node-locked license
b. Windows Client, Windows Floating license server
c. Windows Client, Linux Floating license server
d. Linux Client, Linux Node-locked license
e. Linux Client, Linux Floating license server
f. Linux Client, Windows Floating license server
2. Install your licenses e-mailed to you by Achronix on the license server
3. Modify the license servers for Floating licenses only (cases b, c, e, and f)
4. Run the license servers (Not needed for case ’a’ – Windows Node-locked)
5. Set the Client machine environment variables
6. Run the software
Figure 5 shows the Software development environment. You will need to network the Client
machine(s) and the license server.
UG034, July 1, 2014
Figure 5: Software Development Environment
For more details on Steps 1 through 6 refer to the Achronix Software & License User Guide
(UG002).
Running the software
You are now ready to run the software on your client machine. Run the executable file to
start using ACE.
For more information, please refer to the Achronix Software & License User Guide (UG002).
Setting up the ACX-BRD-HD1000-100G Development Board
Depending on your requirements, choose either the standalone mode or the in-system (plugin) mode of operation for the board. This guide will discuss both modes.
Standalone Mode
You need to connect the development PC and supply power to the board using an external
power source. The connections are shown in Figure 6.
Connecting the Development PC
The development PC is connected to the board using a JTAG ribbon cable that connects to the
USB port on the PC and the JTAG header on the board. The cable (bitporter cable) is
provided with the kit.
Connecting the Power Supply
Although the individual components on the board use different voltage levels, each of these
is generated on the board using a single 12V power supply input.
18 UG034, July 1, 2014
19
Standalone Board Connections
USB Cable
JTAG Ribbon Cable
Development PC (Client)
Bitporter Pod
Power Supply
Development Board
Figure 6: Standalone Board Connections
In-system Mode
You need to plug the development board into an available PCIe x8 slot of the development
PC. You need to leave the adjacent slot vacant to accommodate the clearance requirements
for the component side of the board. Figure 7 shows the connections for this mode.
Connecting the Power Supply
Although the individual components on the board use different voltage levels, each of these
is generated on the board using a single 12V power supply input. You may use a spare 12V
supply connector from the development PC power supply.
UG034, July 1, 2014
In-System Board Connections
USB Cable
JTAG Ribbon Cable
Development PC (Client)
Bitporter Pod
PCIe Slot Connection
Power Supply
Getting started
Power Sequencing
The power sequencing on the board is preconfigured. After you connect the power supply
and the power good LED (D1) is a steady red, turn on the SW4 switch. The board will
automatically power up all the components in the right order.
Initialization
The devices on the board are controlled either by the ATmega2560 controller or by the
HD1000. Both of these devices can also serve as I2C masters. The HD1000 is the default
master.
The board comes pre-configured for you to get started. Once the power is in place on the
board, a set of LEDs will light up. Please refer to the Quickstart Guide for details on default
power-up behavior.
Note: This guide will assume that your initial efforts will be in the standalone mode and these LEDs
will be easily visible. If you are using the in-system mode, you may not be able to see some of the board
indicators as clearly as in the standalone mode.
Figure 7: In-System Board Connections
Downloading a Design
20 UG034, July 1, 2014
Typically, you need to perform the following steps to download a design to the board and
start debugging your application.
Configure the board for the appropriate bitstream source
21
Connect the development PC
Configure the HD1000 and Run the Application
There are three sources currently supported for the FPGA bitstream:
1. JTAG download through BitPorter Pod of bitstream on the development PC
2. SPI Flash
3. A Secure Digital (MicroSD) card
Configuring the Board for the Appropriate Bitstream Source
The board is preconfigured to accept the bitstream from the JTAG interface. Table 1 shows
the shunt positions for J31 to enable the other modes.
Connecting the Development PC
1. Connect the Bitporter pod using the ribbon cable to the development board (J11).
2. Power up the board.
3. Connect the Bitporter pod using the USB port to the development PC.
Configuring the HD1000 and Running the Application
You can configure the FPGA using one of three modes:
1. JTAG
2. Serial
3. CPU
Use jumper J31 and a shunt to select the mode as shown in Table 1. Figure 8 shows the
sources for the bitstream for these modes.
UG034, July 1, 2014
Loading...