Achronix Speedster22i User Manual Clock and Reset Networks
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Speedster22i Clock and
Reset Networks
User Guide
UG027 – May 21, 2014
UG027, May 21, 2014
Copyright Info
Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a
trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation.
All other trademarks are the property of their prospective owners. All specifications subject
to change without notice.
NOTICE of DISCLAIMER: The information given in this document is believed to be accurate
and reliable. However, Achronix Semiconductor Corporation does not give any
representations or warranties as to the completeness or accuracy of such information and
shall have no liability for the use of the information contained herein. Achronix
Semiconductor Corporation reserves the right to make changes to this document and the
information contained herein at any time and without notice. All Achronix trademarks,
registered trademarks, and disclaimers are listed at http://www.achronix.com and use of this
document and the Information contained therein is subject to such terms.
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Table of Contents
Copyright Info .................................................................................................... 2
Table of Contents .............................................................................................. 3
Introduction ................................ ................................................................ ....... 4
Clock and Reset Networks Overview ..................................................................................... 4
Clock Resource Counts ................................................................................................................. 4
Reset Resource Counts ................................................................................................................. 5
Clock Sources ........................................................................................................................ 6
Reset Sources ....................................................................................................................... 6
Core Clock Network .......................................................................................... 7
Global and Direct Core Clock Network .................................................................................. 7
Global Core Clock Network ............................................................................................................ 7
Direct Core Clock Network ............................................................................................................. 8
Core Clock Network Components ........................................................................................ 10
Clock Generator (CG) ................................................................................................ .................. 10
Phase Locked Loop (PLL) ............................................................................................................ 11
Clock Mux .................................................................................................................................... 14
Clock Hub .................................................................................................................................... 15
Clock Region ................................................................................................................................ 16
Clock Region Management Unit (CRMU) ..................................................................................... 17
Junctions .............................................................................................................................. 19
Data-to-Clock Junctions ............................................................................................................... 19
Clock-to-Data Junctions ............................................................................................................... 19
Byte-Lane Clocks ................................................................................................................. 20
Boundary Clock Network ................................................................................ 21
Clock Setting and Reporting .......................................................................... 23
Reset Network ................................................................................................. 24
Reset Sources and the Reset Input Block ........................................................................... 24
Reset Distribution ................................................................................................................. 26
Revision History .............................................................................................. 28
UG027, May 21, 2014
Introduction
Resource
Number of resources
Clock input pins
24 single ended (12 differential)
Global core clocks
48
Direct core clocks
32
Clocks per IP column in fabric
16
Boundary clocks
16
Global boundary clock hierarchy levels
4
Local boundary clock hierarchy levels
2
Clock generators (CGs)
4 (1 per device corner)
Phase Locked Loops (PLLs)
16 (4 in each CG)
Clock and Reset Networks Overview
Speedster22iHD FPGAs have two hierarchical clock networks: a core clock network and a
boundary clock network.
The core clock network is the hierarchical network that feeds resources in the FPGA fabric.
There are two types of core clock networks: a global and a direct. Both of them have common
input sources: Clock input pins and PLL outputs which make up the Clock Generator (CG)
and recovered SerDes input clocks. These input sources get channeled in from both the north
and south sides of the device, and are then fed into the FPGA core through a central trunk.
The boundary clock network is a fully programmable clock network in the IO ring, unique to
Speedster22iHD FPGAs, that provides for significant advantages when clocking IO ring
resources at high frequencies. The boundary clock network is comprised of a low skew global
boundary clock network and a lower jitter local boundary clock network. The inputs to the
boundary clock network are CGs.
Reset signals generated internally or coming from GPIOs are funneled through the Reset
Input Blocks in the device corners into the FPGA core and the IO ring. The IO ring contains a
dedicated reset network but for distribution to core logic, the clock network resources
described above are used.
Clock Resource Counts
The following table lists the clock resources available on Speedster22iHD FPGAs.
Table 1: Clock Resource Counts on Speedster22iHD FPGAs
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Reset Resource Counts
Resource
Number of resources
Reset input pins
32 - 40 (pkg dependent)
Reset input blocks
4
Reset signal groups in IO ring
2
Reset bus width in IO ring
16
The following table lists the reset resources available on Speedster22iHD FPGAs.
Table 2: Reset Resource Counts on Speedster22iHD FPGAs
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Clock Sources
As mentioned earlier, the clock sources are Clock Generators (CGs) and recovered SerDes
input clocks.
There are four CGs on a Speedster 22iHD FPGA, one in each corner of the device. Each CG
contains six clock I/O buffers (CBs) and four Phase Locked Loops (PLLs). The clock buffers
can be used differential I/Os or single‐ended I/Os. If these I/Os are not used as clock buffers,
they can be used as generic inputs or outputs.
The PLLs are low jitter, wide range, independent multi-phase outputs with glitch-free phase
rotators that can be used for PLL outputs of up to 2 GHz for core circuit applications. The
PLLs support both integer mode and fractional mode operation.
Each pair of SerDes lanes is provided one reference clock. Each SerDes lane has its own pair
of PLLs listed below to generate and forward clocks to the fabric:
Thus each SerDes lane provides two word-clocks (Tx and Rx) to the fabric.
a. A transmit PLL, which synthesizes the Tx clock directly from the reference clock,
and then a slower Tx word-clock for data-input from the fabric,
b. A receive PLL, which synthesizes a Rx bit-clock (and corresponding word-clock)
from the incoming data-stream.
For source synchronous transfers, there are additional clock networks known as byte-lane
clock networks that may be used especially when a small amount of logic in the fabric needs
clocking. In these cases, clocks can be routed directly into the fabric along with the data.
Reset Sources
Each corner of a Speedster22i FPGA has an individual Reset Input Block. This block receives
external reset inputs as well as inputs generated internally within the device. External reset
inputs can be driven by dedicated clock pads as well as a number of GPIOs located in the
East-North (EN), East- South (ES), West-North (WN) or West-South (WS) sides of the device.
Internal reset inputs are driven through data and clock paths in the logic fabric.
The inputs to the Reset Input Block generated either externally or internally are required to
be active‐low and glitch free. The input resets can be either asynchronous or synchronous. An
asynchronous reset is synchronized for de‐assertion to each and every clock domain where it
is utilized. A synchronous reset does not need to be synchronized to the same clock domain
but is synchronized when used in any other clock domain not synchronous with the current
clock domain.
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Core Clock Network
This chapter focuses solely on the core clock network, illustrating the global and direct core
clock network hierarchies and providing a more in-depth look at the different components
that make up these networks.
Global and Direct Core Clock Network
Global Core Clock Network
The global core clock network is a balanced and low-skew H-tree that enables clock
distribution to all parts of the Speedster 22iHD FPGA fabric. Clock signals coming in from
the top and bottom CGs and SerDes blocks are routed through a clock hub and aggregated at
the center of the device. These are then provided to all clock regions (see section on Clock
Region for details) on both the west and east sides.
As shown in Table 1, a total of 48 global clock signals are generated in the clock hub. These
are then distributed to all clock regions. Every clock region supports up to a maximum of 16
clocks, and it is able to select, amongst other sources, any of the 48 available global clocks.
Figure 1 below provides a high level illustration of the routing and connection paths for the
H-tree global core clock network.
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GPIO GPIO
SerDes
SerDes
GCG
GCG
GCG
GCG
Figure 1: Global Core Clock Network
Direct Core Clock Network
The direct core clock network is a distribution system that provides for much lower clock
insertion delay, which is particularly useful for more complex designs that utilize multiple
clocks and require clocks to be internally generated and re-distributed to certain parts of the
FPGA fabric. Each branch of the direct clock network is restricted to the clock region it
reaches. Furthermore, direct clocks in each of the clock regions have different insertion
delays, which may result in significant inter-region clock skew.
The clock sources for the direct core clock network are fundamentally the same as those for
the global core clock network. The main difference between the direct and global clocks is
that direct clocks get distributed to the clock regions directly out of the top and bottom clock
muxes, without going through the clock hub (H-tree) in the center of the device.
There are a total of 32 direct clocks coming in from the top clock mux, and 32 coming in from
the bottom clock mux. A pre-designated set of 12 clocks from this group of 32 is distributed
to every clock region. Once inside the clock region, these 12 clocks are then muxed with other
incoming clocks to provide for the set of 16 that ultimately goes into the LUTs, memories and
DSPs in that clock region.
Figure 2 below illustrates the direct core clock network hierarchy.
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GPIO GPIO
SerDes
SerDes
GCG
GCG
GCG
GCG
Figure 2: Direct Core Clock Network
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