Achronix Speedster22i User Manual Snapshot

Speedster22i Snapshot

User Guide

UG016 – September 22, 2014

UG016, September 22, 2014

1

Copyright Info

Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a
trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation.
All other trademarks are the property of their prospective owners. All specifications subject
to change without notice.

NOTICE of DISCLAIMER: The information given in this document is believed to be accurate
and reliable. However, Achronix Semiconductor Corporation does not give any
representations or warranties as to the completeness or accuracy of such information and
shall have no liability for the use of the information contained herein. Achronix
Semiconductor Corporation reserves the right to make changes to this document and the
information contained herein at any time and without notice. All Achronix trademarks,
registered trademarks, and disclaimers are listed at
document and the Information contained therein is subject to such terms.

http://www.achronix.com and use of this

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Table of Contents

Copyright Info .................................................................................................... 2

Table of Contents .............................................................................................. 3

Snapshot Overview ........................................................................................... 4

General Description and Archit e c t ure ............................................................. 5

JTAP Interfa c e ............................................................................................................................... 5

Trigger Detector ............................................................................................................................. 6

Read-Write Control Logic ............................................................................................................... 6

Counters and Registers ................................................................................................................. 6

BRAM ............................................................................................................................................ 6

Snapshot Interface ............................................................................................ 7

Implementation .................................................................................................. 8

Snapshot GUI in ACE ...................................................................................... 13

Revision Histor y .............................................................................................. 18

UG016, September 22, 2014

3

Snapshot Overview

`

BitPorter

TDI

TMS

TCK

TRSTN

TDO

Speedster22iHD

JTAP

Macro

JTAG

TAP

CNTRL

tck

capture

shift

update

trstn

usr1_sel

usr2_sel

usr1_tdr_in
usr2_tdr_in

S
N
A
P
S
H
O
T

C
O
R
E

User Logic

Snapshot is the real-time design debugging tool for Speedster22iHD FPGAs. Snapshot,
which is embedded in the ACE Software, delivers a practical platform to evaluate the signals
of a user’s design in real-time. To run the Snapshot debugger tool, the Snapshot macro needs
to be instantiated inside the RTL. After instantiating the macro and programming the device,
the user will be able to debug the design through the ACE Snapshot Debugger GUI.

The Snapshot macro, when instantiated in the design, can be used to interface with any logic
mapped to the FPGA core. The Snapshot macro provides a JTAG interface at the FPGA pins
to observe debug logic mapped in the core. Through the Snapshot macro and GUI, the user is
able to customize what, when and how much observation will be done by specifying the
nodes, trigger points and pre-store lengths.

Figure 1 shows a block diagram overview of the different components in the Snapshot
debugging tool and its connection to the Speedster22iHD FPGA device.

Figure 1: Snapshot Overview

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General Description and Architecture

JTAP Interface

Read-

Write

Control

Trigger

Detector

BRAM

Read/Write

Address

Counters

Registers

40

80-320

Trigger-Ch

User Clk

Monitor-Ch

The Snapshot macro samples user-signals in real time, and sends the captured data back
through the JTAG interface. The implementation supports the following features:

- Capture up to 144-bit wide data.

- Capture always 1024 samples of data at the user clock frequency

- Supports up to three separate 36-bit trigger conditions, each capable of operating on

any user signal. Each trigger condition supports “don’t care” feature (masking)

- All captured data will be read back serially with respect to TCK

Figure 2 shows the Snapshot architecture:

UG016, September 22, 2014

Figure 2: Snapshot Block Diagram

The blocks comprising the Snapshot module are described in more detail in the following
sections.

JTAP Interface

The JTAG based tap controller, or JTAP, is a module auto-generated when Snapshot is used
in the design. It provides handshaking and connectivity between the Snapshot core in the
user logic and the JTAG interface.

5

Trigger Detector

sel_in

pattern_in [35:0]

channel_in [35:0]

don’t_care [35:0]

usr_clk

match_out

Trigger Detector

As illustrated in Figure 3, the Trigger Detector receives one 36-bit each from the trigger
pattern (pattern_in), don’t care sequence (mask), and input data (channel_in). For every
channel_in sample, this block evaluates a corresponding match signal, called match_out. If
the corresponding mask bit is set high, match_out is asserted; otherwise, match_out remains
low, and is only asserted if the corresponding channel_in bit matches the pattern_in bit.
There is a sel_in pin which comes from a JTAG register for selecting between match_out
getting ORed or ANDed. If sel_in pin is asserted high match_out is ANDed or if sel_in pin is
asserted low match_out is ORed.

Figure 3: Trigger Detector

Note: The 36bit trigger signals must always be the lowest 36 bits of the monitor signals

Read-Write Control Logic

The read-write control logic is essentially a set of state machines to interface with the
counters, the BRAM and the trigger detect circuitry to generate the appropriate signals for
proper storage of user data in the BRAM and for retrieval of this data to be displayed for the
user. It is the main interface between the JTAG circuitry in the rest of the modules in the
Snapshot macro and operates in the same domain as the user clock.

Counters and Registers

The read/write address counters are controlled through the read-write control logic, and
essentially ensure that captured data is appropriately written to and read from the BRAM.
There are also additional registers to monitor triggering mechanisms as well as for
implementation of the read-write control logic.

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BRAM

The BRAM is the memory module used for storage of the captured data. It is a 80Kbit fully
featured true dual port (TDP) memory which acts as the buffering mechanism to supply the
captured data to the user through JTAG. More infotmation can be found on the BRAM in the
Speedster22iHD datasheet and the Speedster22iHD Macro Cell Library.