Achronix Speedster22i User Manual Pin Connections and Power Sequencing
1
Speedster22i Pin Connections and
Power Supply Sequencing
User Guide
UG042 – August 19, 2014
UG042, August 19, 2014
Copyright Info
Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademark and Speedster is a
registered trademark of Achronix Semiconductor Corporation. All other trademarks are the property of their prospective owners.
All specifications subject to change without notice.
NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable. However, Achronix
Semiconductor Corporation does not give any representations or warranties as to the completeness or accuracy of such
information and shall have no liability for the use of the information contained herein. Achronix Semiconductor Corporation
reserves the right to make changes to this document and the information contained herein at any time and without notice. All
Achronix trademarks, registered trademarks, and disclaimers are listed at http://www.achronix.com and use of this document
and the Information contained therein is subject to such terms.
2 UG042, August 19, 2014
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Pin Connection Guidelines
Pin Name
Pin
Group
Type
Description
Connection Guidelines
12.75 Gbps SerDes (64 lanes)
PAD_TE_I_BCK_REF_P/M_LNUM[31:0]
N12P75G
Clock
The 12.75 Gbps SerDes reference clock supplied from either a
single-ended or differential external source. There is 1
differential pair for each of 2, 12.75Gbps lane.
Connect these clocks for all SerDes lanes
used in the interface. Unused clocks should
be tied to their own individual GND via a
50Ω +/- 1% termination resistor.
Note: For PCIe Gen3 operation when using
the hard PCIe controller, reference clocks
for all 8 SerDes lanes need to be connected
regardless of the data width implemented.
PAD_TE_I_BA_RX_P/M_LNUM[31:0]
N12P75G
Input
Receive differential inputs to the 12.75 Gbps SerDes. One pair
for each lane.
Connect all unused receive pins directly to
GND via a 50Ω +/- 1% termination resistor.
PAD_TE_O_BA_APROBE_LNUM[31:0]
N12P75G
Output
The 12.75 Gbps SerDes Analog DC test pad used internally for
debug and testing, one for each lane.
Leave unconnected.
PAD_TE_O_BA_TX_P/M_LNUM[31:0]
N12P75G
Output
Transmit differential outputs from the 12.75 Gbps SerDes.
There is one differential pair per each 12.75Gbps lane.
These pins should be AC coupled. Leave all
unused transmit pins unconnected.
PAD_BE_I_BCK_REF_P/M_LNUM[31:0]
S12P75G
Clock
The 12.75 Gbps SerDes reference clock supplied from either a
single-ended or differential external source. There is 1
differential pair for each of 2, 12.75Gbps lane.
Connect these clocks for all SerDes lanes
used in the interface. Unused clocks should
be tied to their own individual GND via a
50Ω +/- 1% termination resistor.
Note: For PCIe Gen3 operation when using
the hard PCIe controller, reference clocks
for all 8 SerDes lanes need to be connected
regardless of the data width implemented.
PAD_BE_I_BA_RX_P/M_LNUM[31:0]
S12P75G
Input
Receive differential inputs to the 12.75 Gbps SerDes. One pair
for each lane.
Connect all unused receive pins directly to
GND via a 50Ω +/- 1% termination resistor.
PAD_BE_O_BA_APROBE_LNUM[31:0]
S12P75G
Output
The 12.75 Gbps SerDes Analog DC test pad used for ATE and
bench testing, one for each lane
Leave unconnected.
PAD_BE_O_BA_TX_P/M_LNUM[31:0]
S12P75G
Output
Transmit differential outputs from the 12.75 Gbps SerDes.
There is one differential pair per each 12.75Gbps lane.
These pins should be AC coupled. Leave all
unused transmit pins unconnected.
Please see the table below on guidelines for connecting all IOs on the Speedster22i HD FPGAs. For completeness, debug I/Os that
have no user functionality have also been included and are indicated by a grey background.
UG042, August 19, 2014
IEEE1149.1 JTAG Interface
Do not leave JTAG I/Os unconnected. The
JTAG interface should be brought out to a
JTAG header on the board.
TMS
JTAG
Input
Test Mode Select (TMS) input controlling the test access port
(TAP) controller state machine transitions. This input is
captured on the rising edge of the test logic clock (TCK).
This dedicated pin is equipped with an
internal pull-up resistor to place the test
logic in the Test-Logic-Reset state. Connect
this pin using a 10-kΩ +/- 5% pull-up
resistor to VDDO_JCFG (1.8V).
TCK
JTAG
Input
Dedicated test clock used to advance the TAP controller and
clock in data on TDI input and out on TDO output. The
maximum frequency for TCK is 100 MHz.
Connect this pin using a 1-kΩ +/- 1% pulldown resistor to GND.
TDI
JTAG
Input
Serial input for instruction and test data. Data is captured on
the rising edge of the test logic clock.
Dedicated pin with an internal pull-up
resistor. Connect this pin using a 10-kΩ +/5% pull-up resistor to VDDO_JCFG (1.8V).
TRSTN
JTAG
Input
Active-low reset input used to initialize the TAP controller.
Dedicated pin and an optional port on
some devices. Connect this pin using a 4.7kΩ +/- 5% pull-down resistor to GND.
TDO
JTAG
Output
Serial output for data from the test logic. TDO is set to an
inactive drive state (high impedance) when data scanning is
not in progress. TDO drives out valid data on the falling edge
of the TCK input.
Use a 10-kΩ +/- 5% pull-up resistor to
VDDO_JCFG (1.8V) to minimize leakage in
the TDI input buffer of interfacing devices.
Configuration Interface
CONFIG_STATUS
CFG
Open
drain
output
Signal from open-drain output pulled low by FCU until the
configuration memory is successfully cleared. After this, I/O is
tri-stated and the external pull-up should pull this signal high.
It is recommended to connect this signal to
an LED as an indicator on the board. In this
case, use an external 10-kΩ +/- 5% pull-up
resistor to 3.3V and drive a 1-kΩ resistor to
the input of a FET to turn on the LED. If LED
usage is not desired, this signal can be
pulled-up to 1.8V (VDDO_JCFG / PA_VDD2)
using the same 10-kΩ pull-up resistor.
CONFIG_RSTN
CFG
Input
Asynchronous active-low reset input clearing the
configuration memory in the device and the logic in the FPGA
configuration unit (FCU).
Connect directly to the configuration
controller and pull up to 1.8V (VDDO_JCFG
/ PA_VDD2) through a 10-kΩ +/- 5%
resistor.
CONFIG_MODESEL[2:0]
CFG
Input
Configuration mode selection inputs to define the FPGA
configuration unit (FCU) mode of operation.
Configuration Mode
CONFIG_MODESEL[2:0]
Serial x1 Flash
001
Serial x4 Flash
010
CPU
100
JTAG
Always active
Do not leave these pins unconnected. They
should be connected to configurable inputs
like DIP switches to toggle between modes
of operation for debug. If this is not
possible or desired, based on the config
scheme, these pins should be tied to 1.8V
(VDDO_JCFG / PA_VDD2) or GND.
4 UG042, August 19, 2014
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