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Conventions Used in this GuideChapter 1. Preface
Preface
About This Guide
This guide is a reference manual for the Achronix CAD Environment (ACE), used for placing, routing,
configuring, and debugging Achronix FPGAs. ACE works in conjunction with 3rdParty Synthesis and
Simulation tools to provide a complete design environment for Achronix FPGAs.
This guide consists of the following chapters:
Getting Started includes an Introduction to ACE and a quick Tutorial.
Concepts covers all the basic concepts of ACE, and can be considered a reference manual for the various
GUI elements.
Tasks details how to complete various tasks within the GUI, plus provides the related TCL commands.
TCL Command Reference provides a complete TCL command reference including syntax.
Related Documents
ACE Installation and Licensing Guide (UG002)
ACE Quick Start Guide (UG003)
Bitporter User Guide (UG004)
Using Verilog Libraries Available In ACE (found at <ace install dir>/libraries/README.pdf)
Conventions Used in this Guide
ItemFormat
Command-line entries
File Names
GUI buttons, menus, and
radio buttons
VariablesFormatted with italic emphasis.
Window and dialog box
headings and
sub-headings
Window and dialog box
names
Formatted with a bold
fixed-width font.
Formatted with a fixed-width
font.
Formatted with a
variable-width bold font.
Heading formatted in
quotation marks.
Name uses initial caps.
Examples
$ Open top level name.log
filename.ext
Select File→Open, select the desired
file, then click OK to continue.
design dir/output.log
Under ”Output Files”, select . . .
From the Add Files dialog box, . . .
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Chapter 2. Getting Started
Getting Started
Introduction
The Achronix implementation flow uses an industry standard RTL synthesis flow based on Synplify-Pro
from Synplicity and Precision Synthesis from Mentor Graphics. Working in conjunction with the synthesis
tool, Achronix CAD Environment (ACE) provides
• Placement
• Routing
• Timing Analysis
• Bitstream Generation
• FPGA Configuration
• On-chip Debugging
UG001 Rev. 5.0 - 5th December 2012http://www.achronix.com2
ACE Quickstart TutorialChapter 2. Getting Started
ACE Quickstart Tutorial
Start by copying all the files from <install dir>/Achronix/examples/quickstart into a new
empty directory (<test dir>). Now click the () icon in the upper right corner. Then follow these
simple steps to complete your first design in ACE.
1. Create your Project
In the Projects view, click the Create Project () toolbar button. In the Create a New Project dialog, enter
(or browse to) the path to <test dir> in the Project Directory field. Enter ”quickstart” in the ProjectName field and click OK. You should now see your new project show up in the Projects view.
See Creating Projects or Working with Projects for more details.
2. Add your Design Files
In the Projects view, click on the ”quickstart” project to select it. Now click on the Add Files () toolbar
button. In the Add Source Files dialog, select both quickstart.vma and quickstart.sdc by holding
down the CTRL key and clicking on them. Now click the Open button. You now have a project that is ready
to run through the flow!
See Adding Source Files or Working with Projects for more details.
3. Run the Flow
In the Flow view, click on the Run Flow () toolbar button. Output from the flow will be shown in the
TCL Console view. When the flow is finished running, you will see the flow steps in the Flow view updated
with a green check mark () to indicate success and all newly generated reports will be displayed in the
editor area.
See the Flow concept or Running the Flow for more details.
4. Analyze the Results
On the main toolbar, click the Floorplanner Perspective () toolbar button. Use the Critical Paths view to
analyze critical paths and highlight them in the Floorplanner view. Clicking the Zoom To Path () toolbar
button will zoom the Floorplanner view to the path currently selected in the Critical Paths view. Use the
Search view and Selection view to locate objects of interest. Clicking the Zoom To Selection () toolbar
button in the Selection view will zoom the Floorplanner view to the objects in the current selection set.
Congratulations!!!
You have successfully completed a design in ACE!
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PerspectivesChapter 3. Concepts
Concepts
Workbench
The term Workbench refers to the desktop development environment within ACE. The Workbench aims to
achieve seamless tool integration and controlled openness by providing a common platform for the creation,
management, and navigation of workspace resources.
Each Workbench window contains one or more perspectives. Perspectives contain views and editors and
control what appears in certain menus and tool bars. More than one Workbench window can exist on the
desktop at any given time.
Perspectives
There are many different kinds of information a user must view within ACE. Perspectives are used to filter
the information into usable logically consistent groupings. A perspective provides a set of functionality
aimed at accomplishing a specific type of task or works with specific types of resources. A perspective
defines the initial set and layout of views, editors, menus, and toolbars in the Workbench window.
For example, the Projects perspective combines views commonly used while managing project source
files, while the Floorplanner perspective contains the views that are used while viewing chip layout and
floorplanning information. Users often switch perspectives frequently while working inside the Workbench.
Note: Within the Workbench window, all perspectives share the same set of editors. All editors are
usable/visible from all perspectives1. Likewise, each of the views may optionally be used within any
perspective, but they’re most useful when grouped with the other views from their native perspective.
Projects Perspective
TheProjects Perspective allows the user to select an active project and implementation, manage the
contents and configuration of the active project/implementation, run the Flow, and view the reports
generated by the Flow.
By default, this perspective contains the ”Projects View”, ”Flow View”, ”Options View”, ”TCL Console
View”, and the Editor area, which can contain any ACE Editor or Report.
For more information, see Working with Projects, Running the Flow, and Using the Tcl Console.
Floorplanner Perspective
TheFloorplanner Perspective allows the user to view and edit the placement and routing of their active
project/implementation.
By default, this perspective contains the ”Floorplanner View”, ”Package View”, ”Search View”, ”Selection
For more information on using the views in this perspective, see Viewing the Floorplanner, Viewing the
Package Layout, Pre-Placing a Design, Analyzing Critical Paths, and Managing I/Os.
NOTE:
Unlike all other perspectives, the Floorplanner perspective hides the Editor area. To view
Editors and reports, a different perspective must be selected.
IP Configuration Perspective
TheIP Configuration Perspective is used to create and edit IP configuration files (.acxip) through the IP
Editors (like the ”SerDes IP Configuration Editor” and ”Basic PLL IP Configuration Editor”).
1
except the Floorplanner perspective, which disallows the display of editors
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PerspectivesChapter 3. Concepts
By default, this perspective contains the ”Projects View”, ”IP Libraries View”, ”IP Diagram View”, ”IP
Problems View”, ”Outline View”, ”TCL Console View”, and the Editor Area, which can contain any ACE
Editor or Report.
See Creating an IP Configuration for more details.
Bitporter Perspective
TheBitporter Perspective allows interaction with Achronix FPGAs via JTAG through a Bitporter pod.
Downloading the device configuration and debugging will typically happen from here.
By default, this perspective contains the ”SnapShot Debugger View”, ”Download View”, ”TCL Console
View”, and the Editor area, which can contain any ACE Editor or Report.
For more information on using this perspective, see Running the SnapShot Debugger and Playing a STAPL
File
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EditorsChapter 3. Concepts
Editors
Most perspectives in the Workbench are comprised of an editor area and one or more views. Different
editors are associated with different types of files. For example, when a file is opened by double-clicking for
editing in the Projects View, the associated editor opens in the Workbench. If there is no associated editor
for a resource, the Workbench attempts to launch an external editor outside the Workbench. Any number
of editors can be open at once, but only one can be active at a time. The main menu bar and toolbar for the
Workbench window contain operations that are applicable to the active editor.
Tabs in the editor area indicate the names of resources that are currently open for editing (usually the
filename, and the tab’s tooltip will provide the full path to the file). An asterisk (*) indicates that an editor
has unsaved changes. By default, editors are stacked in the editor area, but users may choose to tile them
in order to view multiple editors simultaneously. The gray border at the left margin of the editor area may
contain icons that flag errors, warnings, or problems detected by the system.
In ACE, the editor area is also used to view the Reports generated by ACE. By default, ACE will open HTML
versions of the reports in the HTML Report Browser as soon as the report data is generated/updated2.
Text Editor
Reports, source files, and scripts open in the text editor. The text editor supports typical editing functions,
such as insert, delete, copy, cut, and paste.
Figure 3.1: Text Editor Window
2
This is only true when running the Flow in single-process mode. In Multiprocess mode (via the Multiprocess View), only the
Multiprocess Summary Report is automatically opened in the editor area the other reports must be opened manually through the
Projects View.
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EditorsChapter 3. Concepts
HTML Report Browser
When HTML versions of generated Reports are opened within ACE, they are displayed within the Editor
area using the HTML Report Browser. This is a very limited form of a web browser - it only allows hyperlink
traversal, refresh, forward, and back operations.
Note:
The HTML Report Browser should typically not be used to browse the Internet - a
dedicated web browser like Firefox would be a much better choice for both security and
performance reasons.
IconAction
Refresh
Back
Forward
HTML Report Browser Toolbar Buttons
3
Description
Refreshes the displayed HTML report to show the current contents of the
report file on disk.
Returns to the last HTML location viewed.
Returns to the HTML location viewed before the Back button was
selected. (The Forward button remains disabled until the Back button has
been pressed.)
3
These buttons are displayed in the topmost button-bar of ACE, not within the Editor area itself.
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EditorsChapter 3. Concepts
Advanced PLL Configuration Editor
The Advanced PLL Configuration Editor provides a graphical wizard for creating a PLL configuration
file (.acxip). This editor allows the user to generate the required configuration files for design with the
embedded PLLs. See Creating an IP Configuration. Unlike the much simpler Basic PLL Configuration
Editor, the Advanced PLL Configuration Editor allows the user to access the complete functionality of the
PLL.
By default, the Advanced PLL Configuration Editor is included in the IP Configuration perspective
(Window → Open Perspective → IP Configuration) (). The Advanced PLL configuration information is
broken up into several pages, organized by concept. While some pages are always available, many pages of
configuration options may appear or disappear depending upon whether they are relevant, based upon the
users current choices for configuration options.
Once the user has configured the PLL to meet their requirements, and the Advanced PLL Editor has
determined that there are no errors in the configuration, the user may choose to generate their IP design
files (see Generating the IP Design Files).
IP Diagram
The IP Diagram View for the PLL shows live information about the current configuration in the Editor,
including which logic blocks are currently active, which inputs and outputs are currently active, and what
the various frequencies are within the PLL. Additionally, configuration errors will be shown with a red
background, and configuration warnings will be shown with a yellow background (these are the default IP
Diagram colors, and may be modified in the Preferences).
Figure 3.2: Example IP Diagram for Advanced PLL Editor with some errors in red
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EditorsChapter 3. Concepts
Overview Page
The Overview page contains the top-level, global properties that govern the structure and base
configuration of the PLL. Changes made on this page affect all the outputs for this PLL.
Figure 3.3: Advanced PLL IP Editor Overview Page
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EditorsChapter 3. Concepts
PLL Editor Overview Page Options
OptionEditable
Target DeviceY
Refclk Input
Frequency (MHz)
Number of Desired
Clock Outputs
Y
Y
clkout Output
Frequency
Reference Divider
”NR”
Y
Divided Reference
Frequency
Feedback ModeY
Description
The Speedster22i device this PLL is intended to target.
The frequency of the PLL reference clock input.
The number of desired clock output signals for this PLL.
Changing this will alter the number of active pages of
Clock Output configuration options.
The calculated output frequency of the named clock
output signal. The number of outputs listed will match
the ”Number of Desired Clock Outputs”.
The amount by which the reference clock frequency
should be divided before entering the PLLs Phase
Frequency Detector. As this value increases, the ”VCO
Frequency” decreases.
The calculated reference clock frequency after having
been divided by the ”Reference Divider ’NR’”.
Selects one of the three allowed feedback modes, and
enables/disables related options on this page according
to the selected mode. See Feedback Modes below for
more details.
Feedback Path Total
Divisor Product
VCO Frequency
Feedback Divider
”NF”
Closest NF Fractional
Numerator
Difference between
target and achieved
The calculated total product of all divisors in the present
feedback path.
The calculated VCO output frequency. The algorithm
used will vary depending upon the selected Feedback
Mode.
Y
The amount by which the feedback signal should be
divided before entering the PLLs Phase Frequency
Detector. As this value increases, the ”VCO Frequency”
increases. When in Pure Internal Feedback Mode, this
may be a floating-point value; in Mixed feedback mode
this must be an integer value. In Pure External Feedback
Mode, this option will be disabled.
This calculated values represents the fractional portion of
the entered ”Feedback Value ’NF’” used to configure the
PLL. When floating point values are entered for the
”Feedback Divider ’NF’”, they must be represented as
fractions of 65536 (a 16-bit representation of the fraction is
used). The value displayed provides the closest possible
fraction to that requested by the user.
This calculated value shows how close the PLL can come
to the requested ”Feedback Divider ’NF’” value. (Some
requested fractional values are impossible to exactly
represent within the 16 bits available in the PLL.)
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EditorsChapter 3. Concepts
Achieved NF
This calculated value shows the exact ”Feedback Divider
’NF’” value which will be used by the PLL. This may
differ slightly from the requested value; the closest
approximate value will be chosen if an exact match is not
possible.
Clkout Driving
External Feedback
Path
Y
Selects which of the currently-enabled clock outputs will
drive the external feedback path. Note that Phase
Adjustment is not allowed in the Feedback Path.
Enable sbus portsY
When selected, the sbus ports will be exposed in the
generated HDL file(s).
Feedback Modes There are three feedback modes available to the PLL. Some allow fractional feedback,
others allow deskew.
PLL Feedback Modes
ModeFractional Feedback?Deskew?
Pure InternalYN
Pure ExternalNY
MixedNY
Algorithm
F
=(NF/NR)*F
V CO
F
=(ODn*OSn/NR)*F
V CO
F
=(NF*ODn*OSn/NR)*F
V CO
ref
ref
ref
Pure Internal Feedback
When internal feedback mode is selected, the VCO clock is divided by the ”Feedback Divider ’NF’” only.
In this mode, the PLL can have both integer and fractional feedback divider values. The ”Clkout Driving
External Feedback Path” option becomes disabled in this mode, since it is irrelevant. Deskewing is not
possible in this mode.
Pure External Feedback
When external feedback mode is selected, the VCO clock is divided by the Output Divider (ODn) and
(optionally) the Output Synthesizer (OSn). The ”Clkout Driving External Feedback Path” option becomes
enabled in this mode, and the ”Feedback Divider ’NF’” option becomes disabled. In this mode, it is not
allowed to feedback a clock output that has Phase Adjustment enabled.
4
Mixed Feedback
Mixed feedback mode is a modified version of Pure External feedback mode, in that the Feedback Divider
integer value is also in the deskew feedback path. As with Pure External mode, Phase Adjustment is not
allowed in the feedback path. The ”Clkout Driving External Feedback Path” option becomes enabled in this
mode, as does ”Feedback Divider ’NF’”.
4
Phase rotation in the feedback path will cause the PLL to unlock. If Phase Adjustment is required on any output clocks, it must be
used on outputs which are not in the feedback path.
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EditorsChapter 3. Concepts
Placement Page
The Placement page contains configuration information relating to the PLLs placement in the Speedster
device. The site chosen will be exported in a placement constraints (.pdc) file when the user chooses to
generate their PLL design files.
OptionEditable
Site CornerY
Site IndexY
Figure 3.4: Advanced PLL IP Editor Placement Page
PLL Editor Placement Page Options
Description
The corner of the Speedster22i device where this PLL instance
should be placed. The four choices are NE, SE, SW, and NW.
The site index within the corner where this PLL instance should be
placed.
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EditorsChapter 3. Concepts
Clock Output [0,1,2,3] Pages
The Clock Output pages each contain general configuration information relating to a single PLL output
signal. Since there are one-to-four PLL output signals per PLL (as configured on the Overview Page),
between one and four Clock Output pages will be enabled.
Figure 3.5: IP Advanced PLL Editor Clock Output 0 Page
OptionEditable
clkout Output
Frequency
Bypass PLL and
Output Divider
(OD[0-3])
Enable Output
Synthesizer
(OS[0-3])
Y
Y
PLL Editor Clock Output Page Options
Description
The calculated frequency of this clock output signal as it
exits the PLL.
Enabling this will bypass the NR, PFD, VCO, and OD,
sending the reference clock input signal directly to the OS
input. Disabling this allows normal PLL behavior. Note that
when this is enabled, the IP Editor configuration page for
the Output Divider (OD) associated with this clock output is
disabled. In addition, when enabled, it becomes illegal to
use this output in an external feedback path, as the PLL will
lose lock.
Allows this clock output to use its Output Synthesizer (OS).
When enabled, this activates the IP Editor configuration
page for the OS associated with this clock output. When
disabled, the associated OS configuration page is hidden.
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EditorsChapter 3. Concepts
Output Divider [0,1,2,3] Pages
The Output Divider pages contain configuration information relating to the output divider (OD) of one of
the PLLs clock output signals. Since there are one-to-four PLL output signals per PLL, there are also up to
four of these pages. Because the PLL and OD logic may be bypassed on a per-output basis (as configured
on the Clock Output [0,1,2,3] Pages), this page may sometimes be hidden, even if the related clock output is
enabled.
Figure 3.6: IP Advanced PLL Editor Output Divider 0 Page
PLL Editor Output Divider Page Options
OptionEditable
OD[0-3] Input
Frequency
OD[0-3] DividerY
OD[0-3] Output
Frequency
Enable OD[0-3] Phase
Adjustment
Y
Description
The calculated frequency of the input signal as it enters
this OD logic block.
The factor by which the signal entering the OD should be
divided before it exits the OD. As this increases, the OD
output frequency decreases. (Unless this OD is in the
external feedback path, in which case increasing this
value does not affect the OD output frequency, but
increases the VCO output frequency.)
The calculated frequency of the output signal as it exits
this OD logic block.
Enabling this will allow this OD to perform phase
adjustments on the OD output signal. When enabled, this
activates the related OD [0,1,2,3] Phase Adjustment Pages.
When disabled, the phase adjustment configuration
options remain hidden.
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EditorsChapter 3. Concepts
OD [0,1,2,3] Phase Adjustment Pages
The Output Divider (OD) Phase Adjustment pages contain configuration information about the potential
phase adjustment performed in an OD for one of the PLLs clkout signals. This page will only be visible
when the associated Output Divider [0,1,2,3] Pages are enabled, and the setting ”Enable OD[0-3] Phase
Adjustment” is selected. There is potentially one of these pages associated with every OD, so there will be
between zero and four of these pages for a given IP configuration.
Figure 3.7: IP Advanced PLL Editor OD0 Phase Adjustment Page
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EditorsChapter 3. Concepts
PLL Editor OD Phase Adjustment Options
OptionEditable
OD[0-3] Phase Shift
Increment Unit
Static AdjustmentY
Phase Adjustment MultiplierY
OD[0-3] Static Phase
Adjustment
Dynamic Signal-Driven
Incremental Adjustment
Y
Description
The incremental step, always 45 degrees, by which
the OD output signal will be shifted relative to the
VCO output signal. This is a fixed value, displayed
for user convenience.
When selected, a single, unchanging phase
adjustment must be chosen for this OD. When this
is enabled, the ”Phase Adjustment Multiplier” field
will also be enabled.
This value is multiplied by the ”OD[0-3] Phase
Shift Increment Unit” to determine the total
”OD[0-3] Static Phase Adjustment”.
The calculated total phase shift, in degrees,
performed by this OD.
When selected, this enables dynamic phase
adjustment mode, where the phase of the OD
output signal will advance by ”OD[0-3] Phase Shift
Increment Unit” degrees each time a rising edge is
applied to the associated phase inc input signal.
When this mode is enabled, the ”Phase
Adjustment Multiplier” field will be disabled.
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EditorsChapter 3. Concepts
Output Synthesizer [0,1,2,3] Pages
The Output Synthesizer (OS) pages contain configuration information relating to the OS associated with
the PLLs selected clock output. Because the OS can be disabled for a PLL clock output, this page is only
visible when the ”Enable Output Synthesizer (OS[0-3])” field on the appropriate Clock Output [0,1,2,3] Page
is enabled.
Figure 3.8: IP Advanced PLL Editor Output Synthesizer 0 Page
PLL Editor Output Synthesizer Page Options
OptionEditable
OS[0-3] Input
Frequency
OS[0-3] DividerY
OS[0-3] Output
Frequency
Description
The calculated frequency of the OS input signal.
The factor by which the signal entering the OS should be
divided before it exits the OS. As this increases, the OS
output frequency decreases. (Unless this OS is in the
external feedback path, in which case increasing this value
does not affect the OS output frequency, but instead
increases the VCO output frequency.)
The calculated frequency of the OS output signal.
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EditorsChapter 3. Concepts
Port Names Page
The Port Names page contains all the input and output ports which will be used by the PLL in its current
configuration. (Changing options on other pages will show and hide port names on this page, as the need
for the ports changes.)
Figure 3.9: IP Advanced PLL Editor Port Names Page
NOTE:
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All port names entered on this page must adhere to Verilog and VHDL naming
standards. Illegal names will be caught as errors, and will prohibit RTL wrapper file
generation.
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