Acer TraveMate 8200, TraveMate 8472 Schematic

5

4

3

2

1

GPU CORE PWR

Calpella Switchable Graphic BLOCK DIAGRAM

D D

CLOCK GENERATOR

X'TAL

14.318MHz

SELGO: SLG8SP595V

DDR III

SO-DIMM 0
SO-DIMM 1

C C

Note:
HM55 does not support USB 6 & 7
HM55 does not support SATA 2 & 3

Card Reader
Connector
AU6437

P25USB_P12

MB USB

USB_P1 P39

P31

DB USB Port x 2

B B

USB_P3, 11

P31

Bluetooth

USB_P4 P39

MDC

P33

CCD

P23USB_P8

FingerPrint

P35USB_P2

RJ11

SIMM card

USB_P5 P28

P14, 15

HDD (SATA) *1

ODD (SATA)

Audio CODEC

CX20672

P3

P32

P32

BCLK: 133MHz
PEG_CLK: 100MHz
DPLL_REF_SSCLK: 120MHz

Dual Channel

800/ 1066 MHz

800 MT/s 1066 MT/s

SATA0

SATA1

USB 2.0

Azalia

P30

DDR SYSTEM MEMORY

[Arrandale Only]

*

SATA

3.0 GT/s

USB

HDA

SPI

SPI ROM

4MB x1 (Basic ME+Braidwood)

intel

<MCH Processor>

Arrandale (SG)

rPGA 989

(37.5mm X 37.5mm)

P4.5.6.7

FDI

DMI

X4 DMI interface

DMIFDI

intel

<PCH>

Ibex Peak_M

mBGA 676

(27mm X 25mm)

P8.9.10.11.12.13

LPC

P9

EC (NPCE781)

PCI-E
X16

PCI-E

RTC
P9

Graphics Interfaces

PCIE

2.5GT/s

INT_CRT
INT_LVDS

INT_HDMI

PCI-Express

2.5GT/s

X'TAL

32.768KHz

P34

Fan Driver

(PWM Type)

P37

Nvidia GPU

N11M 512MB
N11P 1GB

P16,17,18,19,20,21,22

[Arrandale Only]

*

[Arrandale Only]

*

[Arrandale Only]

*

TPM

P31

CRT
LVDS
HDMI

X'TAL

27.0MHz

DVI L/S
SN75DP139

PCIE-1

CLKOUT_PEG_B

Broadcom

Giga-LAN

BCM57760

Docking SW
PI3L500

Docking

Transformer

MAX8792ETD

3/5V SYS PWR

RT8206

DDR3 PWR

VT358

+1.8V

HPA00835RTER

CPU VGFX_AXG

ISL62881

THERMAL
PROTECTION

LVDS/CRT
Switch

(UMA only)

P24

PCIE-2

CLKOUT_PEG_4

PCIE-6

CLKOUT_PEG_1&3

P26

P27

P27

(Linear)

P23

Mini card
3G/GPS

USB_P10

Mini Card

WLAN

USB_P13

X'TAL
25MHz

CHARGER

P44

ISL88731

DISCHARGER

+3V,+ 5V,+1.5V,+1.05V,+1.1V_VTT

P39

CPU CORE PWR

P43

ISL62882

CPU VTT

P46

VT358

VTT 1.05V

P45

VT357

P47

MB CRT
Dock

LVDS

Docking DVI

P28

P28

ARD: 1.05V
CFD: 1.1V

P23

P27

P23

P33

SIM card

P38

P47

P42

P41

P42

P28

A A

Docking
S/PDIF

5

P33

Speaker

P30

Docking
Line in

P33

4

Int. D-MIC

P23

Docking
MIC

P33

MIC Jack

P30

Docking
HP

P33

HP Jack

SPI ROM

P30

T / P

P34

3

P35

K/B CON.

P35

P33

RJ45 Connector

2

P27

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

Block Diagram

Block Diagram

Block Diagram

ZQ3

ZQ3

ZQ3

1 47Monday, March 29, 2010

1 47Monday, March 29, 2010

1

1 47Monday, March 29, 2010

1A

1A

1A

1

GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+3.3V

2

VIN

VIN

3

+1.5V

4

+1.5V_SUS

5

+1.8V

6

7

8

+5V

P22

+3V_D

+VGPU_CORE (20A)

VDDC

ISL6264

dGPU_VRON

A A

VDDR3

MOS (AO3413)

+3_D (0.5A)

P44

PG_GPUIO_EN

VDDCI

ISL62872

P45

+VGPU_IO (4.5A)

PG_1V_EN

(DP PLL PWR)

+1V

G9334ADJ & MOS

+1V (3A)

P47

PG_1.5V_EN

VDDR1

MOS (AO4710)

P43

+1.5V_GPU (10A)

PG_1.5V_EN

VDDR4

MOS (AO6402)

P43

+1.8V_GPU (3A)

PG_1.5V_EN

BJT

P22

dGPU_PWROK

dGPU_PWR_EN#

MOS

AO3413

+5_GPU

P22

GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

VIN

dGPU_VRON

VDDC

ISL6264

PG_GPUIO_EN

P44

+VGPU_CORE (20A)

B B

VIN

VDDCI

ISL62872

P45

+VGPU_IO (4.5A)

PG_1V_EN

Power States

POWER PLANE

VIN
+RTC_CELL
+3VPCU
+5VPCU
+15V
3V_LAN_S5

C C

D D

+5VSUS
+3VSUS
+1.5VSUS
+0.75V_DDR_VTT
+5V
+3V
+1.8V
+1.5V
+1.1V_VTT +1.05V~+1.1V
+1.05V +1.05V
+VCC_CORE
LCDVCC
MBAT+
+5V_S5
+3V_S5 +3.3V S5D

1

+10V~+19V
+3V~+3.3V
+3.3V
+5V
+15V
+3.3V
+5V
+3.3V
+1.5V
+0.9V
+5V
+3.3V
+1.8V
+1.5V

0V~+1.5V
+3.3V

+5V S5_ON

DESCRIPTION

MAIN POWER
RTC
8051 POWER
CHARGE POWER
LARGE POWER
LAN POWER

SODIMM POWER
SODIMM POWER

PCH POWER

CPU CORE POWER
LCD Power
MAIN BATTERY+10V~+17V

2

+1.5V

(DP PLL PWR)

+1V

G9334ADJ & MOS

+1V (3A)

CONTROL
SIGNAL

ALWON
ALWON
+15V_ALWP
AUX_ON
SUSD
SUSD
SUSON
MAINON
MAIND
MAIND
MAINON
MAIND
MAINONCPU POWER
MAINONPCH POWER
VRON
LVDS_VDDEN

3

P47

PG_1.5V_EN

ACTIVE INVOLTAGE

S0~S5
S0~S5
S0~S5
S0~S5
S0~S5

+1.5V_SUS

VDDR1

MOS (AO4710)

P43

+1.5V_GPU (10A)

4

+3.3V

+1.5V_GPU

VDDR3

MOS (AO3413)

P22

+3_D (0.5A)

Thermal Follow Chart

CPU
CORE PWR

+3V_D

H_ORICHOT#

5

+1.8V

VDDR4

MOS (AO6402)

+1.8V_GPU (3A)

H/W Throttling

SM-Bus

PG_1.5V_EN

P43

NTC
Thermal
Protection

CPU

PCH

EC

PM_THRMTRIP#

SML1ALERT#

CPUFAN#

6

BJT

P22

dGPU_PWROK

SYS_SHDN#

WIRE-AND

+5V

dGPU_PWR_EN#

MOS

AO3413

P22

+5_GPU

3V/5 V
SYS PWR

FANFAN Driver

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

PWR Status & GPU PWR CRL & THRM

PWR Status & GPU PWR CRL & THRM

PWR Status & GPU PWR CRL & THRM

Date: Sheet of

Date: Sheet of

Date: Sheet of

7

PROJECT :

ZQ3

ZQ3

ZQ3

2 47Monday, March 29, 2010

2 47Monday, March 29, 2010

2 47Monday, March 29, 2010

8

1A

1A

1A

5

+1.5V

L51 BKP1608HS181T/1.5A/180ohm_6L51 BKP1608HS181T/1.5A/180ohm_6

C763

C763

D D

C C

+3V

L44 BKP1608HS181T/1.5A/180ohm_6L44 BKP1608HS181T/1.5A/180ohm_6

4.7u/10V_8

4.7u/10V_8

C700

C700

4.7u/10V_8

4.7u/10V_8

0.1u/16V_4

0.1u/16V_4

C717

C717

0.1u/16V_4

0.1u/16V_4

C718

C718

150mA(20mil)

C758

C758

0.1u/16V_4

0.1u/16V_4

C749

C749

0.1u/16V_4

0.1u/16V_4

CLK_ICH_14M(10)

+1.5V_CLK

C762

C762

0.1u/16V_4

0.1u/16V_4

+3V_CLK

C752 33p/50V_4C752 33p/50V_4

C757

C757

R588 33_4R588 33_4

2 1

33p/50V_4

33p/50V_4

4

R556

R556

*585@0_6

*585@0_6

Y8

Y8

14.318MHZ

14.318MHZ

CLK_SDATA
CLK_SCLK

CPU_SEL

XTAL_IN
XTAL_OUT

U44

U44

1

VDD_DOT

5

VDD_27

17

VDD_SRC

24

VDD_CPU

29

VDD_REF

31

SDA

32

SCL

30

REF_0/CPU_SEL

28

XTAL_IN

27

XTAL_OUT

2

VSS_DOT

8

VSS_27

9

VSS_SATA

12

VSS_SRC

21

VSS_CPU

26

VSS_REF

33

GND

SLG8SP595V

SLG8SP595V

3

VDD_SRC_I/O
VDD_CPU_I/O

DOT_96

DOT_96#

27M

27M_SS

SRC_1/SATA

SRC_1#/SATA#

SRC_2

SRC_2#

*CPU_STOP#

CPU_1

CPU_1#

CPU_0

CPU_0#

CKPWRGD/PD#

CLK Gen(CLK)

15
18

3
4

6
7

10
11
13
14

16
20

19
23
22

25

CLK_BUF_DREFCLKP (10)
CLK_BUF_DREFCLKN (10)

TP91TP91
TP90TP90

CLK_BUF_PCIE_3GPLLP (10)
CLK_BUF_PCIE_3GPLLN (10)
CLK_BUF_DREFSSCLKP (10)
CLK_BUF_DREFSSCLKN (10)

R603 10K_4R603 10K_4

TP83TP83

TP84TP84

CLK_BUF_BCLKP (10)
CLK_BUF_BCLKN (10)

CK_PWRGD_R

+VDDIO_CLK

2/5 modified

+3V

2

80mA(20mil)

C747

C747

C761

C761

0.1u/16V_4

0.1u/16V_4

0.1u/16V_4

0.1u/16V_4

L50 BKP1608HS181T/1.5A/180ohm_6L50 BKP1608HS181T/1.5A/180ohm_6

C753

C759

C759

10u/10V_8

10u/10V_8

C753

C308 may be can save

10u/10V_8

10u/10V_8

Place each 0.1uF cap as close as
possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.

1

+1.05V

CPU_CLK select(CLK)

+1.05V

B B

A A

CPU_SEL

0 1

CPU0/1=133MHz
(default)

5

R587

R587
*10K_4

*10K_4

CPU_SEL

R576

R576

*10p/50V_4

*10p/50V_4

10K_4

10K_4

CPU0/1=100MHz

C733

C733

SMBus(CLK) CLK Enable(CLK)

ICH_SMBDATA(10,26,28)

ICH_SMBCLK(10,26,28)

4

+3V

R554

2

3

Q41

Q41
2N7002D

2N7002D

+3V

2

3

Q42

Q42
2N7002D

2N7002D

R554

2.2K_4

2.2K_4

CLK_SDATA

1

R555

R555

2.2K_4

2.2K_4

1

CLK_SCLK

3

CLK_SDATA (14,15,28)

CLK_SCLK (14,15,28)

VR_PWRGD_CK505#(40)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

+3V

R620

R620
1K/F_4

1K/F_4

CK_PWRGD_R

3

Q43

Q43
2N7002D

2N7002D

2

1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Clock Generator

Clock Generator

Clock Generator

R621

R621
100K/F_4

100K/F_4

ZQ3

ZQ3

ZQ3

1

1A

1A

1A

3 47Monday, March 29, 2010

3 47Monday, March 29, 2010

3 47Monday, March 29, 2010

Arrandale_1(CPU)

5

4

AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI)

3

2

1

AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

U36A

U36A

DMI_TXN0(8)
DMI_TXN1(8)
DMI_TXN2(8)
DMI_TXN3(8)

D D

DMI_TXP0(8)
DMI_TXP1(8)
DMI_TXP2(8)
DMI_TXP3(8)

DMI_RXN0(8)
DMI_RXN1(8)
DMI_RXN2(8)
DMI_RXN3(8)

DMI_RXP0(8)
DMI_RXP1(8)
DMI_RXP2(8)
DMI_RXP3(8)

FDI_TXN0(8)
FDI_TXN1(8)
FDI_TXN2(8)
FDI_TXN3(8)
FDI_TXN4(8)
FDI_TXN5(8)
FDI_TXN6(8)
FDI_TXN7(8)

FDI_TXP0(8)
FDI_TXP1(8)
FDI_TXP2(8)
FDI_TXP3(8)
FDI_TXP4(8)

C C

FDI_TXP5(8)
FDI_TXP6(8)
FDI_TXP7(8)

FDI_FSYNC0(8 )
FDI_FSYNC1(8 )

FDI_INT(8)

FDI_LSYNC0(8)
FDI_LSYNC1(8)

B B

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

Clarksfield/Auburn dale

Clarksfield/Auburn dale

DMI Intel(R) FDI

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS
PEG_RX#[0]

PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN1 0
PEG_RXN1 1
PEG_RXN1 2
PEG_RXN1 3
PEG_RXN1 4
PEG_RXN1 5

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0_ C
PEG_TXN1_ C
PEG_TXN2_ C
PEG_TXN3_ C
PEG_TXN4_ C
PEG_TXN5_ C
PEG_TXN6_ C
PEG_TXN7_ C
PEG_TXN8_ C
PEG_TXN9_ C
PEG_TXN10 _C
PEG_TXN11 _C
PEG_TXN12 _C
PEG_TXN13 _C
PEG_TXN14 _C
PEG_TXN15 _C

PEG_TXP0_C
PEG_TXP1_C
PEG_TXP2_C
PEG_TXP3_C
PEG_TXP4_C
PEG_TXP5_C
PEG_TXP6_C
PEG_TXP7_C
PEG_TXP8_C
PEG_TXP9_C
PEG_TXP10_C
PEG_TXP11_C
PEG_TXP12_C
PEG_TXP13_C
PEG_TXP14_C
PEG_TXP15_C

R440 49.9/F_4R440 49.9/F_4

R441 750/F_ 4R441 750/F_4

C573 0.1 u/10V_4C573 0. 1u/10V_ 4
C575 0.1 u/10V_4C575 0. 1u/10V_ 4
C601 0.1 u/10V_4C601 0. 1u/10V_ 4
C577 0.1 u/10V_4C577 0. 1u/10V_ 4
C590 0.1 u/10V_4C590 0. 1u/10V_ 4
C579 0.1 u/10V_4C579 0. 1u/10V_ 4
C592 0.1 u/10V_4C592 0. 1u/10V_ 4
C581 0.1 u/10V_4C581 0. 1u/10V_ 4
C595 0.1 u/10V_4C595 0. 1u/10V_ 4
C568 0.1 u/10V_4C568 0. 1u/10V_ 4
C583 0.1 u/10V_4C583 0. 1u/10V_ 4
C598 0.1 u/10V_4C598 0. 1u/10V_ 4
C604 0.1 u/10V_4C604 0. 1u/10V_ 4
C570 0.1 u/10V_4C570 0. 1u/10V_ 4
C588 0.1 u/10V_4C588 0. 1u/10V_ 4
C586 0.1 u/10V_4C586 0. 1u/10V_ 4

C574 0.1 u/10V_4C574 0. 1u/10V_ 4
C576 0.1 u/10V_4C576 0. 1u/10V_ 4
C602 0.1 u/10V_4C602 0. 1u/10V_ 4
C578 0.1 u/10V_4C578 0. 1u/10V_ 4
C591 0.1 u/10V_4C591 0. 1u/10V_ 4
C580 0.1 u/10V_4C580 0. 1u/10V_ 4
C593 0.1 u/10V_4C593 0. 1u/10V_ 4
C582 0.1 u/10V_4C582 0. 1u/10V_ 4
C596 0.1 u/10V_4C596 0. 1u/10V_ 4
C569 0.1 u/10V_4C569 0. 1u/10V_ 4
C584 0.1 u/10V_4C584 0. 1u/10V_ 4
C599 0.1 u/10V_4C599 0. 1u/10V_ 4
C600 0.1 u/10V_4C600 0. 1u/10V_ 4
C571 0.1 u/10V_4C571 0. 1u/10V_ 4
C589 0.1 u/10V_4C589 0. 1u/10V_ 4
C587 0.1 u/10V_4C587 0. 1u/10V_ 4

PEG_RXN[0..15] (16)

Use reverse type
(at GPU side)

PEG_RXP[0..15] (16)

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

PEG_TXN[0..15] (16)

PM_DRAM_P WRGD(8,31)

PEG_TXP[0 ..15] (16)

Processor Compensation Signals

R497 20/F_4R497 20/F_4
R494 20/F_4R494 20/F_4
R145 49.9 /F_4R145 49.9/F_4
R483 49.9 /F_4R483 49.9/F_4

TP5TP5

TP10TP10

H_PECI(11)

H_PROCHOT#(40)

PM_THRMTRIP#(11)

PM_SYNC(8)

H_PWRGOOD(11)

PLTRST#(10,11,16 ,25,26,28,31,34 )

R215 1.5K/F_4R215 1.5K/F_4

SI 2/5 Modified

TP_SKT0CC#

H_CATERR#

H_PECI_IS O

H_PROCHOT#

H_CPURST#

H_PM_SYNC

VDDPWRG OOD

H_VTTPWRGD

CPU_PLTRST#

H_COMP3
H_COMP2
H_COMP1
H_COMP0

R201

R201
750/F_4

750/F_4

U36B

U36B

AT23
AT24

G16

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

Clarksfield/Auburn dale

Clarksfield/Auburn dale

COMP3
COMP2
COMP1
COMP0

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

MISC THERMAL

MISC THERMAL

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

CLOCKS

SM_DRAMRST#

PM_EXT_TS#[0]
PM_EXT_TS#[1]

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

PWR MANAGEMENT

JTAG & BPM

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#

PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

TCK
TMS

TDI

TDO

A16
B16

AR30
AT30

E16
D16

A18
A17

CPU_DDR3_D RAMRST#

F6

SM_RCOMP_ 0

AL1

SM_RCOMP_ 1

AM1

SM_RCOMP_ 2

AN1
AN15

AP15

AT28

XDP_PREQ #

AP27

XDP_TCLK

AN28

XDP_TMS

AP28

XDP_TRST#

AT27

XDP_TDI_R

AT29

XDP_TDO_R

AR27

XDP_TDI_M

AR29

XDP_TDO_M

AP29

H_DBR#_R

AN25

XDP_OBS0_R

AJ22

XDP_OBS1_R

AK22

XDP_OBS2_R

AK24

XDP_OBS3_R

AJ24

XDP_OBS4_R

AJ25

XDP_OBS5_R

AH22

XDP_OBS6_R

AK23

XDP_OBS7_R

AH23

CLK_CPU_BCLKP (11)
CLK_CPU_BCLKN (11)

TP70TP70
TP63TP63

CLK_PCIE_3GPLLP (10 )
CLK_PCIE_3GPLLN (10)

DPLL_REF_SSCLKP (10)
DPLL_REF_SSCLKN (10)

R176 100/F_4R176 100/F_4
R183 24.9/F_4R183 24.9/F_4
R188 130/F_4R188 130/F_4

R223 10K_4R223 10K_4
R221 10K_4R221 10K_4

TP67TP67
TP69TP69

TP61TP61
TP68TP68
TP71TP71

TP65TP65
TP66TP66
TP64TP64
TP62TP62

R229 0_4R2 29 0_4

TP14TP14
TP15TP15
TP13TP13
TP12TP12
TP7TP7
TP11TP11
TP8TP8
TP6TP6TP9TP9

CPU_DDR3_D RAMRST# (3 1)

PM_EXTTS#0 (14)

+1.1V_VTT

PM_EXTTS#1 (15)

Layout Note: Place
these resistors
near Processor

XDP_DBRST# (8)

Thermaltrip protect

+1.1V_VTT

3

Q23

Q23

PM_THRMTRIP#

2

1 3

FDV301N

FDV301N

1

R237

R237
1K_4

1K_4

2

Q24

Q24
MMBT3904

MMBT3904

SYS_SHDN# (39,47 )

DELAY_VR_ PWRGOOD(8,40)

A A

PM_THRMTRIP#(11)

VTT PWR_Good

MPWROK(34)

+3V

C374

C374

0.1u/16V _4

0.1u/16V _4

R224

3 5

4

U18

U18
TC7SH08FU

TC7SH08FU

R224

2K/F_4

2K/F_4

H_VTTPWRGD

R200

R200
1K_4

1K_4

2
1

pull-up 56ohm close to PCH

5

4

3

Processor pull-up

4/9 REV:B MODIFY BY DG1.52

+1.5V_CPUVDDQ

R213

R213

1.1K/F_4

1.1K/F_4

R195

R195
3K/F_4

3K/F_4

XDP_TDO

R225 51/F_4R225 51/F_4

H_CATERR#

R216 49.9/F_4R2 16 49.9/F_4

H_PROCHOT#

R226 68_4R226 68_4

H_CPURST#

R472 *68_4R472 *68_4

XDP_TMS

R481 *51_4R481 *51_4

XDP_TDI_R

R475 *51_4R475 *51_4

XDP_PREQ #

R470 *51_4R470 *51_4

XDP_TCLK
XDP_TRST#

R482 51/F_4R482 51/F_4

PM_DRAM_P WRGD

Use a voltage divider with VDDQ
(1.5V) rail (ON in S3) and
resistor combination of 4.75K (to
VDDQ)/12K(to GND) to generate the
required voltage.
Note: CRB uses a 3.3V (always ON)
rail with 2K and 1K combination.

2

+1.1V_VTT

JTAG MAPPING

XDP_TDI_R XDP_TDI

R468 *SHORT_4R468 *SHORT_4

XDP_TDO_M

R467 *0_4R467 *0_4

R476

R476

*SHORT_4

*SHORT_4

XDP_TDI_M

R469 *0_4R469 *0_4R479 *51_4R479 *51_4

XDP_TDO_R

R471 *SHORT_4R471 *SHORT_4

Scan Chain
(Default)

CPU Only

GMCH Only

STUFF -> R469, R491, R507
NO STUFF -> R489, R490

STUFF -> R490, R491
NO STUFF -> R469, R489, R507

STUFF -> R489, R507
NO STUFF -> R491, R490, R469

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev

AUBURNDA 1/4

AUBURNDA 1/4

AUBURNDA 1/4

Date: Sheet of

Date: Sheet of

Date: Sheet of

XDP_TDO

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZQ3

ZQ3

ZQ3

4 47Monday, March 29 , 2010

4 47Monday, March 29 , 2010

1

4 47Monday, March 29 , 2010

1A

1A

1A

5

Arrandale_2(CPU)

M_A_DQ[63:0](14)

D D

C C

B B

M_A_BS#0(14)
M_A_BS#1(14)
M_A_BS#2(14)

M_A_CAS#(14)
M_A_RAS#(14)
M_A_WE#(14)

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

C10

D10

H10

G10

AH5
AF5
AK6
AK7
AF6
AG5

AJ10
AL10

AK12

AK8

AK11

AN8
AM10
AR11

AL11

AM9

AN9

AT11
AP12
AM12
AN12
AM13

AT14

AT12

AL13
AR14
AP14

AC3
AB2

AE1
AB3
AE9

A10

C7
A7

B10
E10

A8
D8

F10

E6
F7
E9
B7
E7
C6

G8
K7

J8

G7

J7

J10

L7
M6
M8

L9

L6
K8
N8
P9

AJ7
AJ6

AJ9

AL7
AL8

U7

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)

U36C

U36C

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

4

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]

SA_DM[1]

SA_DM[2]

SA_DM[3]

SA_DM[4]

SA_DM[5]

SA_DM[6]

SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]

SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7

M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_CLKP0 (14)
M_A_CLKN0 (14)
M_A_CKE0 (14)

M_A_CLKP1 (14)
M_A_CLKN1 (14)
M_A_CKE1 (14)

M_A_CS#0 (14)
M_A_CS#1 (14)

M_A_ODT0 (14)
M_A_ODT1 (14)

M_A_DM[7:0] (14)

M_A_DQSN[7:0] (14)

M_A_DQSP[7:0] (14)

M_A_A[15:0] (14)

3

M_B_DQ[63:0](15)

M_B_BS#0(15)
M_B_BS#1(15)
M_B_BS#2(15)

M_B_CAS#(15)
M_B_RAS#(15)
M_B_WE#(15)

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AR10

AT10

AF3
AG1

AK1
AG4
AG3

AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9

AB1

AC5
AC6

AJ3

AJ4

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3

G4

H6

G2

G1
G5

K2

M1

K5
K4

M4

N5

W5

R7

Y7

J6
J3

J2
J1
J5

L3

U36D

U36D

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

2

W8

SB_CK[0]

W9

SB_CK#[0]

M3

SB_CKE[0]

V7

SB_CK[1]

V6

SB_CK#[1]

M2

SB_CKE[1]

AB8

SB_CS#[0]

AD6

SB_CS#[1]

AC7

SB_ODT[0]

AD1

SB_ODT[1]

M_B_DM0

D4

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7

M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

1

M_B_CLKP0 (15)
M_B_CLKN0 (15)
M_B_CKE0 (15)

M_B_CLKP1 (15)
M_B_CLKN1 (15)
M_B_CKE1 (15)

M_B_CS#0 (15)
M_B_CS#1 (15)

M_B_ODT0 (15)
M_B_ODT1 (15)

M_B_DM[7:0] (15)

M_B_DQSN[7:0] (15)

M_B_DQSP[7:0] (15)

M_B_A[15:0] (15)

Clarksfield/Auburndale

Clarksfield/Auburndale

Clarksfield/Auburndale

Channel A DQ[15,32,48,54], DM[5]
Requires minimum 12mils spacing
with all other signals, including data signals.

A A

5

4

3

Channel B DQ[16,18,36,42,56,57,60,61,62]
Requires minimum 12mils spacing
with all other signals, including data signals.

Clarksfield/Auburndale

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

AUBURNDA 2/4

AUBURNDA 2/4

AUBURNDA 2/4

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

ZQ3

ZQ3

ZQ3

5 47Monday, March 29, 2010

5 47Monday, March 29, 2010

5 47Monday, March 29, 2010

1

1A

1A

1A

5

Arrandale_3(CPU)

CPU Core Power

ARD:48A
CFD:52A

C281

C330

C330
22u/6.3V_8

22u/6.3V_8

C311

C311

22u/6.3V_8

22u/6.3V_8

C626

C626

10u/6.3V_6

10u/6.3V_6

C277

C277

10u/6.3V_6

10u/6.3V_6

C281

+

+

*330u/2V_7343

*330u/2V_7343

C334

C334

22u/6.3V_8

22u/6.3V_8

C331

C331

22u/6.3V_8

22u/6.3V_8

C285

C285

10u/6.3V_6

10u/6.3V_6

C328

C328

10u/6.3V_6

10u/6.3V_6

C295

C274

C274
22u/6.3V_8

22u/6.3V_8

C632

C632

22u/6.3V_8

22u/6.3V_8

C325

C325

10u/6.3V_6

10u/6.3V_6

C276

C276

10u/6.3V_6

10u/6.3V_6

+

+

330u/2V_7343

330u/2V_7343

C304

C304

22u/6.3V_8

22u/6.3V_8

C310

C310

22u/6.3V_8

22u/6.3V_8

C320

C320

10u/6.3V_6

10u/6.3V_6

C323

C323

10u/6.3V_6

10u/6.3V_6

C295

C264

C264

+

D D

C621

C621
22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

C C

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

B B

A A

+

*330u/2V_7343

*330u/2V_7343

C633

C633

22u/6.3V_8

22u/6.3V_8

C332

C332

C627

C627

22u/6.3V_8

22u/6.3V_8

C625

C625

C327

C327

10u/6.3V_6

10u/6.3V_6

C324

C324

C329

C329

10u/6.3V_6

10u/6.3V_6

C333

C333
22u/6.3V_8

22u/6.3V_8

C635

C635

22u/6.3V_8

22u/6.3V_8

C278

C278

10u/6.3V_6

10u/6.3V_6

C275

C275

10u/6.3V_6

10u/6.3V_6

C296

C296

+

+

330u/2V_7343

330u/2V_7343

+VCC_CORE

C628

C628

22u/6.3V_8

22u/6.3V_8

C634

C634

22u/6.3V_8

22u/6.3V_8

C623

C623

10u/6.3V_6

10u/6.3V_6

C631

C631

10u/6.3V_6

10u/6.3V_6

U36F

U36F

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Clarksfield/Auburndale

Clarksfield/Auburndale

AUBURNDALE/CLARKSFIELD PROCESSOR (POWER)

5

4

VTT Rail Values are
Auburndal VTT=1.05V
Clarksfield VTT=1.1V

AH14

VTT0_1

AH12

VTT0_2

AH11

VTT0_3

AH10

VTT0_4

J14

VTT0_5

J13

VTT0_6

H14

VTT0_7

H12

VTT0_8

G14

VTT0_9

G13

VTT0_10

G12

VTT0_11

G11

VTT0_12

F14

VTT0_13

F13

VTT0_14

F12

VTT0_15

F11

VTT0_16

E14

VTT0_17

E12

VTT0_18

D14

VTT0_19

D13

VTT0_20

D12

VTT0_21

D11

VTT0_22

C14

VTT0_23

C13

VTT0_24

C12

VTT0_25

C11

VTT0_26

B14

VTT0_27

B12

VTT0_28

A14

VTT0_29

A13

VTT0_30

A12

VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VTT_SELECT

ISENSE

VCC_SENSE
VSS_SENSE

VTT_SENSE

A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

PSI#

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

AN35

AJ34
AJ35

B15
A15

1.1V RAIL POWER

1.1V RAIL POWER

CPU CORE SUPPLY

CPU CORE SUPPLY

POWER

POWER

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

VSS_SENSE_VTT

SENSE LINES

SENSE LINES

4

C309

C309

22u/6.3V_8

22u/6.3V_8

C271

C271

10u/6.3V_8

10u/6.3V_8

C630

C630

10u/6.3V_8

10u/6.3V_8

C282

C282
22u/6.3V_8

22u/6.3V_8

+VTT_43

R143 0_4R143 0_4

+VTT_44

R144 0_4R144 0_4

C251

C251
1u/10V_4

1u/10V_4

H_PSI#

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_DPRSLPVR

H_VTTVID1

H_VTTVID1=Low, 1.1V
H_VTTVID1=High, 1.05V

R162 100_4R162 100_4

R167 100_4R167 100_4

VTT_SENSE
VSS_SENSE_VTT

18A

C303

C303

C618

C618
22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

C629

C629

C622

C622
10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

C615

C615

C272

C272
10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

+1.1V_VTT

C611

C611

22u/6.3V_8

22u/6.3V_8

(15mils)

H_PSI# (40)

H_VID0 (40)
H_VID1 (40)
H_VID2 (40)
H_VID3 (40)
H_VID4 (40)
H_VID5 (40)
H_VID6 (40)
H_DPRSLPVR (40)

TP1TP1

+VCC_CORE

TP56TP56
TP57TP57

I_MON (40)

VCCSENSE (40)
VSSSENSE (40)

+

+

C284

C284
330u/2V_7343

330u/2V_7343

C636

C636
10u/6.3V_8

10u/6.3V_8

+1.1V_VTT

3

2

1

AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

U36G

R194

R194
1K_4

1K_4

R193

R193
*1K_4

*1K_4

U36G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

Clarksfield/Auburndale

Clarksfield/Auburndale

+1.1V_VTT

R197

R197

R203

R203
*1K_4

*1K_4

*1K_4

*1K_4

R196

R196

R202

R202
1K_4

1K_4

1K_4

1K_4

HFM_VID : Max 1.4V
LFM_VID : Min 0.65V

AR22

VAXG_SENSE

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GRAPHICS

GRAPHICS

GFX_DPRSLPVR

GRAPHICS VIDs

GRAPHICS VIDs

FDI PEG & DMI

FDI PEG & DMI

POWER

POWER

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

1.1V1.8V

1.1V1.8V

R218

R218

R228

R228

*1K_4

*1K_4

1K_4

1K_4

R217

R217

R227

R227

1K_4

1K_4

*1K_4

*1K_4

2

R181

R181
1K_4

1K_4

R180

R180
*1K_4

*1K_4

R174

R174
*1K_4

*1K_4

R173

R173
1K_4

1K_4

VCC_AXG_SENSE (45)
VSS_AXG_SENSE (45)

GFX_VID0 (45)
GFX_VID1 (45)
GFX_VID2 (45)
GFX_VID3 (45)
GFX_VID4 (45)
GFX_VID5 (45)
GFX_VID6 (45)

R496 4.7K_4R496 4.7K_4
R492 *10K_4R492 *10K_4

GFX_ON (45)
GFX_DPRSLPVR (45)

GFX_IMON (45)

+1.5V_CPUVDDQ

C292

C292

C353

C353

1u/10V_4

1u/10V_4

C266

C266

22u/6.3V_8

22u/6.3V_8

C616

C616

10u/6.3V_6

10u/6.3V_6

C614

C614
22u/6.3V_8

22u/6.3V_8

C273

C273
1u/10V_4

1u/10V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

AUBURNDA 3/4 (PWR)

AUBURNDA 3/4 (PWR)

AUBURNDA 3/4 (PWR)

Date: Sheet of

Date: Sheet of

Date: Sheet of

C315

C315

1u/10V_4

1u/10V_4

1u/10V_4

1u/10V_4

+

+

C261

C261

C265

C265

330u/2V_7343

330u/2V_7343

22u/6.3V_8

22u/6.3V_8

C610

C610

10u/6.3V_6

10u/6.3V_6

C613

C613
22u/6.3V_8

22u/6.3V_8

C619

C619

C280

C280

2.2u/10V_6

2.2u/10V_6

1u/10V_4

1u/10V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

C286

C286

1u/10V_4

1u/10V_4

+1.1V_VTT

4.7u/10V_6

4.7u/10V_6

C617

C617

ZQ3

ZQ3

ZQ3

C308

C308
1u/10V_4

1u/10V_4

0.6A

C270

C270
22u/6.3V_8

22u/6.3V_8

6 47Monday, March 29, 2010

6 47Monday, March 29, 2010

6 47Monday, March 29, 2010

+1.8V

1A

1A

1A

22A

+VGFX_AXG

+1.1V_VTT

3

+

+

C653

C653
330u/2V_7343

330u/2V_7343

C385

C385
22u/6.3V_8

22u/6.3V_8

C637

C637
10u/6.3V_8

10u/6.3V_8

C375

C375
22u/6.3V_8

22u/6.3V_8

C535 and C1005 may be can save

C381

C381
10u/6.3V_8

10u/6.3V_8

+1.1V_VTT

22u/6.3V_8

22u/6.3V_8

C294

C294

C620

C620
22u/6.3V_8

22u/6.3V_8

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_DPRSLPVR
H_PSI#

C288

C288

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

Note:
For Validating IMVP VR R6451 should be STUFF
and R2N1 NO_STUFF

C268

C268

R191

R191
1K_4

1K_4

R190

R190
*1K_4

*1K_4

+

+

C650

C650
330u/2V_7343

330u/2V_7343

C639

C639
22u/6.3V_8

22u/6.3V_8

C384

C384
10u/6.3V_8

10u/6.3V_8

C335

C335

22u/6.3V_8

22u/6.3V_8

R186

R186
1K_4

1K_4

R185

R185
*1K_4

*1K_4

C612

C612
22u/6.3V_8

22u/6.3V_8

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

5

VSS

VSS

AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

AE34

VSS81

AE33

VSS82

AE32

VSS83

AE31

VSS84

AE30

VSS85

AE29

VSS86

AE28

VSS87

AE27

VSS88

AE26

VSS89

AE6

VSS90

AD10

VSS91

AC8

VSS92

AC4

VSS93

AC2

VSS94

AB35

VSS95

AB34

VSS96

AB33

VSS97

AB32

VSS98

AB31

VSS99

AB30

VSS100

AB29

VSS101

AB28

VSS102

AB27

VSS103

AB26

VSS104

AB6

VSS105

AA10

VSS106

Y8

VSS107

Y4

VSS108

Y2

VSS109

W35

VSS110

W34

VSS111

W33

VSS112

W32

VSS113

W31

VSS114

W30

VSS115

W29

VSS116

W28

VSS117

W27

VSS118

W26

VSS119

W6

VSS120

V10

VSS121

U8

VSS122

U4

VSS123

U2

VSS124

T35

VSS125

T34

VSS126

T33

VSS127

T32

VSS128

T31

VSS129

T30

VSS130

T29

VSS131

T28

VSS132

T27

VSS133

T26

VSS134

T6

VSS135

R10

VSS136

P8

VSS137

P4

VSS138

P2

VSS139

N35

VSS140

N34

VSS141

N33

VSS142

N32

VSS143

N31

VSS144

N30

VSS145

N29

VSS146

N28

VSS147

N27

VSS148

N26

VSS149

N6

VSS150

M10

VSS151

L35

VSS152

L32

VSS153

L29

VSS154

L8

VSS155

L5

VSS156

L2

VSS157

K34

VSS158

K33

VSS159

K30

VSS160

Arrandale_4(CPU)

U36H

U36H

AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20

D D

C C

B B

AR17
AR15
AR12

AR9
AR6

AR3
AP20
AP17
AP13
AP10

AP7

AP4

AP2
AN34
AN31
AN23
AN20
AN17

AM29
AM27
AM25
AM20
AM17
AM14
AM11

AM8

AM5

AM2
AL34
AL31
AL23
AL20
AL17
AL12

AL9
AL6

AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11

AJ8

AJ5

AJ2

AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13

AH9
AH6
AH3

AG10

AF8
AF4
AF2

AE35

Clarksfield/Auburndale

Clarksfield/Auburndale

U36I

U36I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

Clarksfield/Auburndale

Clarksfield/Auburndale

4

VSS

VSS

AT35

VSS_NCTF1

AT1

VSS_NCTF2

AR34

VSS_NCTF3

B34

VSS_NCTF4

B2

VSS_NCTF5

B1

VSS_NCTF6

A35

VSS_NCTF7

NCTF

NCTF

TP60TP60
TP58TP58
TP3TP3

3

AP25
AL25
AL24
AL22
AJ33

VREF_DQ_DIMM0(14,31)
VREF_DQ_DIMM1(15,31)

CFG0

AM30
AM28

AP31

CFG3

AL32

CFG4

AL30
AM31
AN29

CFG7

AM32

AK32

AK31

AK28

AJ28
AN30
AN32

AJ32

AJ29

AJ30

TP54TP54
TP55TP55

AK30

CHECKLIST 2.0 CONNECT TO GND

TP2TP2

U36E

U36E

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

Clarksfield/Auburndale

Clarksfield/Auburndale

2

AJ13

RSVD32

AJ12

RSVD33

AH25

RSVD34

AK26

RSVD35

AL26

RSVD36

AR2
AJ26

RSVD38

AJ27

RSVD39

AP1
AT2

AT3
AR1

AL28

RSVD45

AL29

RSVD46

AP30

RSVD47

AP32

RSVD48

AL27

RSVD49

AT31

RSVD50

AT32

RSVD51

AP33

RSVD52

AR33

RSVD53

AT33
AT34
AP35
AR35
AR32

RSVD58

E15
F15
A2

KEY

D15

RSVD62

C15

RSVD63

AJ15

RSVD64
RSVD65

VSS

TP16TP16

AH15

TP17TP17

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

TP59TP59

AP34 can be NC on CRB; EDS/DG suggestion to GND

RESERVED

RESERVED

RSVD_NCTF_37

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD_TP_59
RSVD_TP_60

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

1

Processor Strapping

A A

CFG4
(Display Port
Presence)

CFG0
(PCI-Epress
Configuration Select)

CFG3
(PCI-Epress Static
Lane Reversal)

Disabled; No Physical Display Port
attached to Embedded Diplay Port

Single PEG

Normal Operation Lane Numbers Reversed

5

1 0

Enabled; An external Display port
device is connected to the Embedded
Display port

Bifurcation enabled

4

CFG[ 1:0 ] - PCI_Epress Configuration Select

Use reverse type

* 11= 1 x 16 PEG
* 10= 2 x 8 PEG

+1.1V_VTT

R204 3.01K/F_4R204 3.01K/F_4
R219 3.01K/F_4R219 3.01K/F_4
R198 *3.01K/F_4R198 *3.01K/F_4

3

CFG4

R214 *3.01K/F_4R214 *3.01K/F_4

CFG0

R222 *3.01K/F_4R222 *3.01K/F_4

CFG3

R199 3.01K/F_4R199 3.01K/F_4

CFG7

R474 *3.01K/F_4R474 *3.01K/F_4

The Clarkfield processor's PCI Express interface may not meet
PCI Express 2.0 jitter specifications. Intel recommends
placing a 3.01K +/- 5% pull down resistor to VSS on CFG[7] pin
for both rPGA and BGA components. This pull down resistor
should be removed when this issue is fixed.(ES1 only)

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

AUBURNDA 4/4

AUBURNDA 4/4

AUBURNDA 4/4

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

ZQ3

ZQ3

ZQ3

7 47Monday, March 29, 2010

7 47Monday, March 29, 2010

1

7 47Monday, March 29, 2010

1A

1A

1A

PCH1(CLG)

5

4

3

2

1

IBEX PEAK-M (DMI,FDI,GPIO)

U43C

U43C

ACIN_R

PM_BATLOW#

PM_RI#

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IbexPeak-M_R1P0

IbexPeak-M_R1P0

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

System Power Management

SLP_LAN# / GPIO29

DMI_RXN0(4)

D D

C C

XDP_DBRST#(4)

B B

DMI_RXN1(4)
DMI_RXN2(4)
DMI_RXN3(4)

DMI_RXP0(4)
DMI_RXP1(4)
DMI_RXP2(4)
DMI_RXP3(4)

DMI_TXN0(4)
DMI_TXN1(4)
DMI_TXN2(4)
DMI_TXN3(4)

DMI_TXP0(4)
DMI_TXP1(4)
DMI_TXP2(4)
DMI_TXP3(4)

R600 49.9/F_4R600 49.9/F_4

+1.05V

XDP_DBRST#

SYS_PWROK

RSV_ICH_LAN_RST#

PM_DRAM_PWRGD(4,31)

ICH_RSMRST#(34)

DNBSWON#(34)

PCH_ACIN(34)

ICH_RSMRST#

SUS_PWR_ACK_R

R360 *0_4R360 *0_4

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14
BF13
BH13
BJ12
BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

For LAN PU @ LAN site

PCIE_WAKE#

CLKRUN#

SUS_STAT#

SLP_S5#_R

R352 *0_4R352 *0_4

SLP_M#

PM_SLP_LAN#

TP46TP46

TP52TP52

TP85TP85

TP49TP49

FDI_TXN0 (4)
FDI_TXN1 (4)
FDI_TXN2 (4)
FDI_TXN3 (4)
FDI_TXN4 (4)
FDI_TXN5 (4)
FDI_TXN6 (4)
FDI_TXN7 (4)

FDI_TXP0 (4)
FDI_TXP1 (4)
FDI_TXP2 (4)
FDI_TXP3 (4)
FDI_TXP4 (4)
FDI_TXP5 (4)
FDI_TXP6 (4)
FDI_TXP7 (4)

FDI_INT (4)
FDI_FSYNC0 (4)
FDI_FSYNC1 (4)
FDI_LSYNC0 (4)
FDI_LSYNC1 (4)

PCIE_WAKE# (26)

CLKRUN# (31,34)

ICH_SUSCLK (34)

SUSC# (34)

SUSB# (34)

PM_SYNC (4)

LAN

TPM & EC

PD @ LVDS page

INT_LVDS_BLON(23)

INT_LVDS_DIGON(23)

INT_LVDS_BRIGHT(23)

INT_LVDS_EDIDCLK(23)
INT_LVDS_EDIDDATA(23)

INT_TXLCLKOUTN(23)

INT_TXLCLKOUTP(23)

INT_TXLOUTN0(23)

INT_TXLOUTN1(23)

INT_TXLOUTN2(23)

INT_TXLOUTP0(23)

INT_TXLOUTP1(23)

INT_TXLOUTP2(23)

INT_CRT_BLU(23)
INT_CRT_GRE(23)
INT_CRT_RED(23)

INT_CRT_DDCCLK(23)
INT_CRT_DDCDAT(23)

INT_HSYNC(23)
INT_VSYNC(23)

+3V

R295 10K/F_4R295 10K/F_4
R280 10K/F_4R280 10K/F_4

R304 2.37K/F_4R304 2.37K/F_4

INT_TXLCLKOUTN
INT_TXLCLKOUTP

INT_TXLOUTN0
INT_TXLOUTN1
INT_TXLOUTN2

INT_TXLOUTP0
INT_TXLOUTP1
INT_TXLOUTP2

INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED

DAC_IREF

R285

R285
1K/F_4

1K/F_4

IBEX PEAK-M (LVDS,DDI)

U43D

U43D

AB48

AB46

AP39
AP41

AT43
AT42

AV53
AV51

BB47
BA52
AY48
AV47

BB48
BA50
AY49
AV48

AP48
AP47

AY53
AT49
AU52
AT53

AY51
AT48
AU50
AT51

AA52
AB53
AD53

AD48
AB51

T48
T47

Y48

Y45

V48

V51
V53

Y53
Y51

L_BKLTEN
L_VDD_EN

L_BKLTCTL
L_DDC_CLK

L_DDC_DATA
L_CTRL_CLK

L_CTRL_DATA
LVD_IBG

LVD_VBG
LVD_VREFH

LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

IbexPeak-M_R1P0

IbexPeak-M_R1P0

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

CRT

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

PU @ DVI page

INT_HDMI_TXN2_C
INT_HDMI_TXP2_C
INT_HDMI_TXN1_C
INT_HDMI_TXP1_C
INT_HDMI_TXN0_C
INT_HDMI_TXP0_C
INT_HDMI_TXCN_C
INT_HDMI_TXCP_C

SDVO_CTRLCLK (24)
SDVO_CTRLDAT (24)

C444 IV@0.1u/10V_4C444 IV@0.1u/10V_4
C439 IV@0.1u/10V_4C439 IV@0.1u/10V_4
C434 IV@0.1u/10V_4C434 IV@0.1u/10V_4
C432 IV@0.1u/10V_4C432 IV@0.1u/10V_4
C459 IV@0.1u/10V_4C459 IV@0.1u/10V_4
C449 IV@0.1u/10V_4C449 IV@0.1u/10V_4
C429 IV@0.1u/10V_4C429 IV@0.1u/10V_4
C426 IV@0.1u/10V_4C426 IV@0.1u/10V_4

Add IV@ (1/11)

R place close to PCH

R514 150/F_4R514 150/F_4
R513 150/F_4R513 150/F_4
R512 150/F_4R512 150/F_4

INT_HDMI_HPD (24)

INT_HDMI_TXN2 (24)
INT_HDMI_TXP2 (24)
INT_HDMI_TXN1 (24)
INT_HDMI_TXP1 (24)
INT_HDMI_TXN0 (24)
INT_HDMI_TXP0 (24)
INT_HDMI_TXCN (24)
INT_HDMI_TXCP (24)

INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED

PCH Pull-high/low(CLG)

+3V

CLKRUN#

A A

XDP_DBRST#

ICH_RSMRST#
RSV_ICH_LAN_RST#

SYS_PWROK ACIN_R

R647 8.2K_4R647 8.2K_4
R354 1K_4R354 1K_4

R608 10K_4R608 10K_4
R602 10K_4R602 10K_4

5

PM_RI#
PM_BATLOW#

PM_SLP_LAN#
SUS_PWR_ACK_R

R320 10K_4R320 10K_4
R351 8.2K_4R351 8.2K_4

R343 *10K_4R343 *10K_4R327 10K_4R327 10K_4
R626 10K_4R626 10K_4
R349 10K_4R349 10K_4

+3V_S5

4

System PWR_OK(CLG)

C750 *0.1u/10V_4C750 *0.1u/10V_4

SYS_PWROK

3

U45

U45
TC7SH08FU

TC7SH08FU

+3V_S5

DELAY_VR_PWRGOOD need PU 2K to +3V.
PU at power side

53

1

4

2

R601 100K_4R601 100K_4

DELAY_VR_PWRGOOD (4,40)
PWROK_EC (34)

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

IBEX PEAK-M 1/6

IBEX PEAK-M 1/6

IBEX PEAK-M 1/6

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

ZQ3

ZQ3

ZQ3

8 47Monday, March 29, 2010

8 47Monday, March 29, 2010

1

8 47Monday, March 29, 2010

1A

1A

1A

5

RTC Circuitry(RTC)

+VCCRTC

D35

PCH_AZ_MDC_SYNC(33)
PCH_AZ_CODEC_SYNC(30)
PCH_AZ_MDC_RST#(33)
PCH_AZ_CODEC_RST#(30)
PCH_AZ_MDC_SDOUT(33)
PCH_AZ_CODEC_SDOUT(30)

PCH_AZ_MDC_BITCLK(33)
PCH_AZ_CODEC_BITCLK(30)

20mils

D35

BAT54C

BAT54C

1 3

2

20MIL

RTC_N01

Q46

Q46

MMBT3904

MMBT3904

RTC_N03

C731

C731

*27p/50V_4

*27p/50V_4

R611 20K/F_4R611 20K/F_4

30mils

R610 20K/F_4R610 20K/F_4

C769

C769
1u/10V_4

1u/10V_4

R633 22K/F_6R633 22K/F_6

R564 33_4R564 33_4
R574 33_4R574 33_4
R559 33_4R559 33_4
R563 33_4R563 33_4
R586 33_4R586 33_4
R585 33_4R585 33_4

R575 33_4R575 33_4
R582 33_4R582 33_4

C732

C732
*27p/50V_4

*27p/50V_4

C764

C764
1u/10V_4

1u/10V_4

C755

C755
1u/10V_4

1u/10V_4

Tony:0831

R645

R645

68.1K/F_4

68.1K/F_4

R646

R646
150K/F_6

150K/F_6

RTC_RST#

12

J1

J1

*SHORT_ PAD1

*SHORT_ PAD1

SRTC_RST#

12

J2

J2

*SHORT_ PAD1

*SHORT_ PAD1

+5V_S5

ACZ_SYNCACZ_SYNC

ACZ_SYNCACZ_SYNC

ACZ_RST#

ACZ_SDOUTACZ_SDOUT

ACZ_SDOUTACZ_SDOUT

ACZ_BIT_CLKACZ_BIT_CLK

ACZ_BIT_CLKACZ_BIT_CLK

+3VPCU

VCCRTC_1

20MIL

D D

R632

R632
1K_4

1K_4

VCCRTC_2

20MIL

12

CN23

CN23
RTC_ML2032

RTC_ML2032

HDA Bus(CLG)

C C

Place all series terms close to PCH except for SDIN input
lines,which should be close to source.Placement of R773, R775,
R776 & R777 should equal distance to the T split trace point.
Basically, keep the same distance from T for all series
termination resistors.

PCH SPI(CLG)

B B

SPI_CS0#_R
SPI_CLK_R
SPI_SI_R
SPI_SO_R

C768

C768
*22p/50V_4

*22p/50V_4

R619 3.3K/F_4R619 3.3K/F_4

+3V

A A

U47

U47

1
6
5
2

3

5

CE#

VDD
SCK
SI
SO

HOLD#

WP#

VSS

MX25L1605DM2I-12G

MX25L1605DM2I-12G

8

R618 3.3K/F_4R618 3.3K/F_4

7
4

2/10 modify for fac. request.

+3V

C488

C488

0.1u/10V_4

0.1u/10V_4

4

PCH2(CLG)

PCH Strap Table

SPKR

INIT3_3V

GNT3# / GPIO55

INTVRMEN

GNT1# / GPIO51

GNT0#

GNT2# / GPIO53

NV_ALE

NV_CLE

HDA_DOCK_EN#/GPIO33

SPI_MOSI

HDA_SDO
GPIO8
GPIO27
HDA_SYNC

GPIO15

4

C484

C484

15p/50V_4

15p/50V_4

C492

C492

15p/50V_4

15p/50V_4

+VCCRTC

HDA_SYNC (PCH strap pin)

Internal weak pull-down
VCCVRM=>+1.8V (default)
external pull-up
VCCVRM=>+1.5V

PCH_AZ_CODEC_SDIN0(30)
PCH_AZ_MDC_SDIN1(33)

+3V_S5

+3VPCU

Pin Name Strap description

No reboot mode setting PWROK

Reserved

Integrated 1.05V VRM enable ALWAYS

Boot BIOS Selection 1 [bit-1]

Boot BIOS Selection 0 [bit-0]

ESI strap (Server only)

Intel Anti-Theft HDD protection PWROK 0 = Disable (Internal pull-down 32ohm)

DMI Termination voltage

Flash Descriptor Security

iTPM function Disable MEPWROK 0 = Default (weak pull-down 20K)

Reserved
Reserved
On-die PLL Voltage Regulator

On-die PLL PWR supply select RSMRST#

Reserved RSMRST#

3

14

23

Y6

32.768KHzY632.768KHz

R604 1M_4R604 1M_4

ACZ_BIT_CLK
ACZ_SYNC

SPKR(30)

ACZ_RST#

ACZ_SDOUT

R313 *10K_4R313 *10K_4

TP86TP86
TP88TP88
TP89TP89
TP87TP87
TP53TP53

PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#

R625 *10K_4R625 *10K_4

Sampled

PWROK

PWROKTop-Block Swap Override

PWROK

PWROK

PWROK

PWROK

PWROK

RSMRST#
RSMRST#
RSMRST# 0 = Disable

3

IBEX PEAK-M (HDA,JTAG,SATA)

R328

R328
10M_4

10M_4

RTC_X1
RTC_X2

RTC_RST#
SRTC_RST#

SM_INTRUDER#

PCH_INVRMEN

TP32TP32
TP33TP33

HDA_DOCK_EN#

PCH_GPIO13

SPI_CLK_R
SPI_CS0#_R
SPI_CS1#

SPI_SI_R
SPI_SO_R

0 = Default (weak pull-down 20K)
1 = Setting to No-Reboot mode

1 = Default (weak pull-up 20K)
Should not be pull-down

0 = "top-block swap" mode
1 = Default (weak pull-up 20K)

Should be always pull-up

Should not be pull-down
(weak pull-up 20K)

weak pull-down 32ohm

0 = Override
1 = Default (weak pull-up 20K)

1 = Enable

Should not be pull-up
(weak pull-down 20K)
Should not be pull-down
(weak pull-up 20K)

1 = Enable (weak pull-up 20K)
0 = 1.8V supply (weak pull-down 20K)

1 = 1.5V supply
0 = TLS no Confidentiality

(weak pull-down 20K)
1 = TLS Confidentiality

U43A

U43A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IbexPeak-M_R1P0

IbexPeak-M_R1P0

Configuration

GNT0#GNT1#

11

01

00

Boot Location

SPI

PCI

LPC

2

D33

FWH0 / LAD0

B33

FWH1 / LAD1

C32

FWH2 / LAD2

A32

FWH3 / LAD3

RTCIHDA

RTCIHDA

SPI JTAG

SPI JTAG

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

LPC

SATA

SATA

SATA0GP / GPIO21
SATA1GP / GPIO19

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

C34

PCH_DRQ#0

A34

PCH_DRQ#1

F34
AB9

AK7
AK6

SATA_TXN0_C

AK11

SATA_TXP0_C

AK9

AH6
AH5

SATA_TXN1_C

AH9

SATA_TXP1_C

AH8
AF11

AF9
AF7
AF6

Note:
SATA port2/3 may not be available on all PCH sku

AH3
AH1

(HM55 support 4port only)

AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16

R323 37.4/F_4R323 37.4/F_4

AF15

T3

R368 10K_4R368 10K_4

Y9

R639 10K_4R639 10K_4

V1

ZY9B note

R642 *10K_4R642 *10K_4

+3V

R519 *4.7K_4R519 *4.7K_4

R606 330K_4R606 330K_4

+VCCRTC

Default weak pull-up on GNT0/1#
[Need external pull-down for LPC BIOS]

+3V

R284 *1K_4R284 *1K_4
R269 *1K_4R269 *1K_4

R292 1K_4R292 1K_4
R268 1K_4R268 1K_4

R303 *4.7K_4R303 *4.7K_4

+1.8V

+1.8V

+3V_S5

R624 *1K_4R624 *1K_4

R341 *1K_4R341 *1K_4

R592 *1K_4R592 *1K_4
R594 *10K_4R594 *10K_4

+3V

+3V

R336 10K_4R336 10K_4

R324 *10K_4R324 *10K_4

NV_ALE

NV_CLE

R623 *8.2K_4R623 *8.2K_4

use defaul (0 = 1.8V supply)

R346 1K_4R346 1K_4

+3V_S5

2

TP80TP80
TP30TP30

R366 10K_4R366 10K_4

C710 0.01u/25V_4C710 0.01u/25V_4
C711 0.01u/25V_4C711 0.01u/25V_4

C283 0.01u/25V_4C283 0.01u/25V_4
C287 0.01u/25V_4C287 0.01u/25V_4

+3V

+3V

SPKR

PCI_GNT3# (10)

PCH_INVRMEN

1/11 modified

PCI_GNT0# (10)
PCI_GNT1# (10)

PWM_SELECT# (10,23)

NV_ALE (10)

NV_CLE (10)

HDA_DOCK_EN#

SPI_SI_R

RSV_GPIO8 (11)

RSV_GPIO27 (11)

CR_WAKE# (11)

1

LPC_LAD0 (28,31,34)
LPC_LAD1 (28,31,34)
LPC_LAD2 (28,31,34)
LPC_LAD3 (28,31,34)

LPC_LFRAME# (28,31,34)

+3V

IRQ_SERIRQ (31,34)

SATA_RXN0 (29)
SATA_RXP0 (29)
SATA_TXN0 (29)
SATA_TXP0 (29)

SATA_RXN1 (29)
SATA_RXP1 (29)
SATA_TXN1 (29)
SATA_TXP1 (29)

+1.05V

SATA_ACT# (36)

PCH_ODD_EN (29)

from PCH and to control SW (EC or PCH control
Brightness switch)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

IBEX PEAK-M 2/6

IBEX PEAK-M 2/6

IBEX PEAK-M 2/6

Date: Sheet of

Date: Sheet of

Date: Sheet of

SATA HDD

CAP. Close connect side

SATA ODD

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZQ3

ZQ3

ZQ3

1

1A

1A

9 47Monday, March 29, 2010

9 47Monday, March 29, 2010

9 47Monday, March 29, 2010

1A

5

PCH3(CLG)

IBEX PEAK-M (PCI,USB,NVRAM)

U43E

U43E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

D D

PCI_PIRQA#

TP29TP29

PCI_PIRQB#

C C

S

e

l

e

c

S

t

e

l

L

e

V

c

D

t

S

b

&

r

i

C

g

R

h

T

t

n

i

e

s

s

i

B B

CLK_LPC_DEBUG(28)
CLK_LPC_TPM(31)

CLK_PCI_775(34)

dGPU_SELECT#(23)

PCI_GNT0#(9)
PCI_GNT1#(9)

PWM_SELECT#(9,23)

PCI_GNT3#(9)

PCI_RST#(28)

CLK_PCI_FB CLK_PCI_FB_C

C411

C411

C660

C660

*10p/50V_4

*10p/50V_4

*10p/50V_4

*10p/50V_4

*10p/50V_4

*10p/50V_4

TP76TP76

TP77TP77

TP78TP78
TP72TP72
TP79TP79
TP73TP73

TP21TP21
TP18TP18

TP22TP22
TP25TP25
TP24TP24
TP75TP75

TP20TP20
TP28TP28

TP74TP74
TP51TP51

R267 22_4R 267 22_4
R515 22_4R 515 22_4
R260 22_4R 260 22_4
R273 22_4R 273 22_4

C421

C421

PCI_PIRQC#
PCI_PIRQD#

PCI_REQ0#
PCI_REQ1#
dGPU_SELECT#
PCI_REQ3#

PCI_GNT0#
PCI_GNT1#

PCI_GNT3#
PCI_PIRQE#

PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_RST#
PCI_SERR#

PCI_PERR#

PCI_IRDY#
PCI_PAR
PCI_DEVSEL#
PCI_FRAME#

PCI_PLOCK#
PCI_STOP#

PCI_TRDY#
ICH_PME#
PCI_PLTRST#

CLK_PCI_TPM_C

CLK_PCI_775_CCLK_PCI_775_C

EMI addition

PLTRST#(CLG)

Add Buffers as needed for

+3V_S5

Loading and fanout concerns.

T

C495

C495

o

0.1u/10V_4

0.1u/10V_4 R288 10K_4R288 10K_4

PCI_PLTRST#

2

A A

1

U24

U24

3 5

TC7SH08FU

TC7SH08FU

r

e

T

a

P

d

M

e

r

/

/
E

C

L

C

P

A

4

U

PLTRST# (4,11,16,25,26,28,31,34)

N

/

R364

R364

/

100K_4

100K_4

G

M

P

i

U

n

i

/
c

C

a

a

r

r

d

d
/

5

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50
G42
H47
G34

G38
H51
B37
A44

F51
A46
B45

M53

F48
K45
F36
H53

B41
K53
A36
A48

K6

E44
E50

A42
H44
F46
C46

D49
D41

C48

M7
D5

N52
P53
P46
P51
P48

IbexPeak-M_R1P0

IbexPeak-M_R1P0

C/BE0#
C/BE1#
C/BE2#
C/BE3#

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PCIRST#
SERR#

PERR#

IRDY#
PAR
DEVSEL#
FRAME#

PLOCK#
STOP#

TRDY#
PME#
PLTRST#
CLKOUT_PCI0

CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

PCI

PCI

PCI/USBOC# Pull-up(CLG)

USB_OC7#
USB_OC6#
USB_OC5#
USB_OC4#

+3V_S5

PCI_REQ0#
PCI_PIRQB#
PCI_REQ3#
PCI_PIRQD#

+3V

PCI_PLOCK#
PCI_SERR#
PCI_DEVSEL#
PCI_STOP#

+3V

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USB

USB

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

6
7
8
9

10

6
7
8
9

10

6
7
8
9

10

4

RP3

RP3

8.2K_10P8R

8.2K_10P8R

RP4

RP4

8.2K_10P8R

8.2K_10P8R

RP2

RP2

8.2K_10P8R

8.2K_10P8R

4

3

2

1

IBEX PEAK-M (PCI-E,SMBUS,CLK)

U43B

U43B

PCIE_RXN1(26)
PCIE_RXP1(26)

LAN

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

NV_ALE

BD3

NV_CLE

AY6

NV_RCOMP

AU2
AV7
AY8

AY5
AV11

BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20

USBP6-

M22

USBP6+

N22

USBP7-

B21

USBP7+

D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

USB_BIAS

B25
D25

USB_OC0#

N16

USB_OC1#

J16

USB_OC2#

F16

USB_OC3#CLK_LPC_DEBUG_C

L16

USB_OC4#

E14

USB_OC5#

G16

USB_OC6#

F12

USB_OC7#

T15

NV_ALE (9)
NV_CLE (9)

R342 *32.4/F_4R342 *32.4/F_4

Port1 and port9 can be used on debug mode

USBP0- (33)
USBP0+ (33)
USBP1- (32)
USBP1+ (32)
USBP2- (32)
USBP2+ (32)
USBP3- (32)

USBP3+ (32)

TP38TP38
TP36TP36

USBP5- (28)

USBP5+ (28)

TP35TP35
TP34TP34
TP43TP43
TP41TP41

USBP8- (23)
USBP8+ (23)

USBP4- (32)

USBP4+ (32)

USBP10- (28)

USBP10+ (28)

USBP11- (35)

USBP11+ (35)

USBP12- (25)

USBP12+ (25)

USBP13- (28)

USBP13+ (28)

R317

R317

Docking
M/B USB
EXT-USB1-1
EXT-USB2

15" USB PORT

SIMM card

USB port6/7 may not be available on all PCH sku
(HM55 support 12port only)

Camera
BLUETOOTH
Mini Card (WWAN)
Finger Printer
Card reader
Mini Card (WLAN)

22.6/F_4

22.6/F_4

TP45TP45
TP40TP40

TP92TP92
TP39TP39
TP37TP37

EHCI1

EHCI2

USB_OC0# (32)
USB_OC1# (32)

Mini 3G

MiniWLAN

Mini 3G

MiniWLAN

PCIE_TXN1(26)
PCIE_TXP1(26)

PCIE_RXN2(28)
PCIE_RXP2(28)
PCIE_TXN2(28)
PCIE_TXP2(28)

PCIE_RXN6(28)
PCIE_RXP6(28)
PCIE_TXN6(28)
PCIE_TXP6(28)

Note:
PCIE port7/8 may not be available on all PCH sku
(HM55 support 6port only)

CLK_PCH_SRC1N(28)
CLK_PCH_SRC1P(28)

CLK_PCIE_REQ1#_R(28)

CLK_PCH_SRC2N(28)
CLK_PCH_SRC2P(28)

CLK_PCIE_WLAN#(28)

CLK_PCIE_LOMN(26)

LAN

CLK_PCIE_LOMP(26)

CLK_PCIE_LAN_REQ#(26)

CLK_REQ/Strap Pin(CLG)

+3V_S5

R348 10K_4R348 10K_4
R340 10K_4R340 10K_4
R355 10K_4R355 10K_4
R350 10K_4R350 10K_4

R628 IV@10K_4R628 IV@10K_4

+3V

R640 10K_4R640 10K_4
R644 10K_4R644 10K_4

R536 8.2K_4R536 8.2K_4
R510 8.2K_4R510 8.2K_4
R549 8.2K_4R549 8.2K_4

R634 *10K_4R634 *10K_4

CLK_PCIE_REQ0#
CLK_PCIE_REQ3#
CLK_PCIE_REQ4#
CLK_PCIE_REQ5#

PEG_CLKREQ#_R

CLK_PCIE_REQ1#_R
CLK_PCIE_WLAN#
dGPU_SELECT#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#

PEG_CLKREQ#_R

3

N

s

i

t

e

5
4
3
2
1

5
4
3
2
1

5
4
3
2
1

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

PCI_PIRQH#
PCI_TRDY#
PCI_FRAME#
PCI_REQ1#

PCI_PERR#
PCI_PIRQC#
PCI_IRDY#
PCI_PIRQA#

+3V_S5

+3V

+3V

C736 0.1u/10V_4C736 0.1u/10V_4

C730 0.1u/10V_4C 730 0.1u/10V_4

C465 0.1u/10V_4C465 0.1u/10V_4

C462 0.1u/10V_4C 462 0.1u/10V_4

C445 0.1u/10V_4C 445 0.1u/10V_4
C451 0.1u/10V_4C 451 0.1u/10V_4

R275 *0/short_4R275 *0/short_4
R274 *0/short_4R274 *0/short_4

R258 *0/short_4R258 *0/short_4
R257 *0/short_4R257 *0/short_4

R506 *0/short_4R506 *0/short_4
R505 *0/short_4R505 *0/short_4

F

o

r

L

A

N

PEG_A_CLKRQ# PD for FreeRun, due GPU not support.

P

A16 swap override Strap/Top-Block

U

Swap Override jumper

@

PCI_GNT3#

L

A

Boot BIOS Strap

GNT0# GNT1#

0
0
1
1

Danbury Technology Enabled

NV_ALE

DMI Termination Voltage

NV_CLE

CLK_PCH_SRC1N_R
CLK_PCH_SRC1P_R

CLK_PCIE_REQ1#_R

CLK_PCH_SRC2N_R
CLK_PCH_SRC2P_R

CLK_PCIE_WLAN#

CLK_PCIE_REQ3#

CLK_PCIE_REQ4#

CLK_PCIE_REQ5#

CLK_PCH_SRC6N_R
CLK_PCH_SRC6P_R

CLK_PCIE_LAN_REQ#

Low = A16 swap
override/Top-Block
Swap Override enabled
High = Default

Boot BIOS Location
LPC

0

Reserved (NAND)

1

PCI

0

SPI

1

High = Enable
Low = Disable

Set to Vcc when LOW
Set to Vcc/2 when HIGH

T24T24
T22T22
T19T19
T21T21

CLK_PCIE_REQ0#

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN6_C
PCIE_TXP6_C

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IbexPeak-M_R1P0

IbexPeak-M_R1P0

SMBus

SMBus

PCI-E*

PCI-E*

Link

Link

Controller

Controller

PEG

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N

CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

From CLK BUFFER

Clock Flex

Clock Flex

SMBus/Pull-up(CLG)

+3V_S5

R612 10K_4R612 10K_4
R319 10K_4R319 10K_4
R358 10K_4R358 10K_4
R617 2.2K_4R617 2.2K_4
R615 2.2K_4R615 2.2K_4

R85 4.7K_4R85 4.7K_4
R84 4.7K_4R84 4.7K_4

1/21 modified

+3V

2

BOARD ID

R262 OPTIM@10K_4R262 OPTIM@10K_4
R270 *10K_4R270 *10K_4
R277 10K_4R277 10K_4

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1
CL_DATA1
CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

RSV_SMBALERT#

RSV_SML0ALERT#
RSV_SML1ALERT#
ICH_SMBCLK
ICH_SMBDATA

SMB_CLK_ME0
SMB_DATA_ME0

t

BOARD_ID1

s

o

BOARD_ID2

u

BOARD_ID3

r

c

e

RSV_SMBALERT#

B9

ICH_SMBCLK

H14

ICH_SMBDATA

C8

RSV_SML0ALERT#

J14

SMB_CLK_ME0

C6

SMB_DATA_ME0

G8

RSV_SML1ALERT#

M14

2ND_MBCLK

E10

2ND_MBDATA

G12

CL_CLK1

T13

CL_DATA1

T11

CL_RST1#

T9

PEG_CLKREQ#_R

H1

AD43
AD45

AN4
AN2

AT1
AT3

AW24
BA24

AP3
AP1

F18
E18

&

AH13
AH12

F

A

P41

N

J42

&

AH51

E

AH53

C

XCLK_RCOMP

AF38

BOARD_ID1

T45

BOARD_ID2

P43

BOARD_ID3

T42

N50

&

C

R

T

E

D

I

D

i

n

p

u

R276 MUX@10K_4R276 MUX@10K_4
R271 10K_4R271 10K_4
R289 *10K_4R289 *10K_4

ICH_SMBCLK (3,26,28)
ICH_SMBDATA (3,26,28)

SMB_CLK_ME0
SMB_DATA_ME0

R649 *0_4R649 *0_4

F

o

F

r

o

r

a

CL_CLK1 (28)

n

E

CL_DATA1 (28)

o

C

CL_RST1# (28)

t

n

h

i

R635 SW@0_4R635 SW@0_4

e

r

PEG_A_CLKRQ# PD for FreeRun, due GPU not support.

c

CLK_PCIE_VGAN (16)
CLK_PCIE_VGAP (16)

a

P

r

CLK_PCIE_3GPLLN (4)

C

s

CLK_PCIE_3GPLLP (4)

d

H

p

i

n

A

A

4

CLK_PCI_FB

XTAL25_IN
XTAL25_OUT

e

R509 10K_4R509 10K_4

c

t

L

V

D

S

R318

R318

2.2K_4

2.2K_4

2ND_MBDATA 2ND_MBCLK

BID3

BID2

BID1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

i

t

DPLL_REF_SSCLKN (4)
DPLL_REF_SSCLKP (4)

e

CLK_BUF_PCIE_3GPLLN (3)

W

CLK_BUF_PCIE_3GPLLP (3)

M

A

CLK_BUF_BCLKN (3)
CLK_BUF_BCLKP (3)

X

CLK_BUF_DREFCLKN (3)
CLK_BUF_DREFCLKP (3)

CLK_BUF_DREFSSCLKN (3)
CLK_BUF_DREFSSCLKP (3)

CLK_ICH_14M (3)

R306 90.9/F_4R306 90.9/F_4

No stuff XTAL25_IN and XTAL25_OUT circuitry
until integrated CG becomes PCH POR.

S

e

l

dGPU_EDIDSEL# (23,24)

+3V

May be remove is OK

2ND_MBCLK(34)2ND_MBDATA(34)

0



PCI

1



LPC

0



ZQ3

1



ZR9

0



Mux

1



Optimas

IBEX PEAK-M 3/6

IBEX PEAK-M 3/6

IBEX PEAK-M 3/6

F

o

r

C

F

l

o

k

r

SML1ALERT# (11,34,37)

g

L

e

A

n

N

&

P

F

U

o

M

r

i

@

M

PEG_CLKREQ# (16)

L

i

A

n

N

i

c

a

r

d

2/10 modified

C664 27p/50V_4C664 27p/50V_4

21

R518

R518
1M_4

1M_4

+1.05V

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

C663 33p/50V_4C663 33p/50V_4

+3V_S5+3V_S5

ZQ3

ZQ3

ZQ3

10 47Monday, March 29, 2010

10 47Monday, March 29, 2010

10 47Monday, March 29, 2010

Y3
25MHzY325MHz

R322

R322

2.2K_4

2.2K_4

1A

1A

1A

5

PCH4(CLG)

BMBUSY#

SIO_EXT_SMI#(34)

D D

T

o

dGPU_PWR_EN# should be stable

G

before dGPU_VRON enable

w
E

P

e
n

U

r
a

b

o
l

C C

k
e

F

o

r

a

n

o

B B

change board_id0 to GPIO7 at 6/1

F

r

o

m

GPIO24 NC for Intel suggestion at 6/1

G

P

U

p

o

SML1ALERT#(10,34,37)

EC suggestion use GPIO49 for FAN control

SATA5GP / GPIO49 / TEMP_ALERT# is used to
alert for EC when CPU or Graph/Memory
controllers' temperature go out of limit.
So connecting GPIO49 to EC and avoid this
pin to be used for other purpose

SIO_EXT_SCI#(34)

RSV_GPIO8(9)

TP48TP48

CR_WAKE#(9)

dGPU_PWROK(18)

TP47TP47

RSV_GPIO27(9)

dGPU_VRON(44)

dGPU_PWR_EN(46)

RST_GATE#(31)

R636 *0/short_4R636 *0/short_4

SIO_EXT_SMI#
SIO_EXT_SCI#
BOARD_ID0
RSV_GPIO8
LAN_DISABLE#
CR_WAKE#
dGPU_HOLD_RST#
dGPU_PWROK
GPIO22

GPIO27
TP_PCH_GPIO28
STP_PCI#

dGPU_PWR_EN
dGPU_PRSNT#
GPIO38
SAVE_LED#
GPIO45
RST_GATE#
SV_SET_UP

SATA5GP

GPIO57

4

IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)

U43F

U43F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IbexPeak-M_R1P0

IbexPeak-M_R1P0

MISC

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

GPIO

GPIO

CPU

CPU

NCTF

NCTF

RSVD

RSVD

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8

TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19

NC_1
NC_2
NC_3
NC_4
NC_5

INIT3_3V#

TP24

3

AH45
AH46

AF48
AF47

U2

AM3
AM1
BG10
T1
BE10

PCH_THRMTRIP#_R

BD10

BA22
AW22
BB22
AY45
AY46
AV43
AV45
AF13
M18
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39

P6
C10

TP_PCH_PCIE6N
TP_PCH_PCIE6P

TP_PCH_PCIE7N
TP_PCH_PCIE7P

TP1_PCH
TP2_PCH

TP_INT3_3V

TP26TP26
TP27TP27

TP19TP19
TP23TP23

R338 56/F_4R338 56/F_4

TP42TP42
TP44TP44

TP50TP50

SIO_A20GATE (34)

CLK_CPU_BCLKN (4)
CLK_CPU_BCLKP (4)
H_PECI (4)
SIO_RCIN# (34)
H_PWRGOOD (4)

56/F_4

56/F_4

R337

R337

2

PM_THRMTRIP# (4)

+1.1V_VTT

GPU RST#(CLG)

+3V

C496 *0.1u/10V_4C496 *0.1u/10V_4

53

1

GPU_RST#(16)

4

U23

U23

SW@TC7SH08FU

SW@TC7SH08FU

dGPU_HOLD_RST#

2

GPIO Pull-up/Pull-down(CLG)

TP_PCH_GPIO28
GPIO45
RST_GATE#
GPIO57
LAN_DISABLE#

SIO_EXT_SMI#
SIO_EXT_SCI#

dGPU_PWR_EN

SIO_RCIN#
SIO_A20GATE
dGPU_HOLD_RST#
SATA5GP
GPIO22
dGPU_PRSNT#
SAVE_LED#
STP_PCI#

GPIO38
BMBUSY#
SV_SET_UP

dGPU_PWROK

SV_SET_UP 1-X High = Strong (Default)

GPIO57 stuff PD and not stuff PU for Intel suggestion at 6/1

GPIO57

R314 SW@10K_4R314 SW@10K_4

+3V_S5

R641 10K_4R641 10K_4
R627 10K_4R627 10K_4
R630 10K_4R630 10K_4
R637 10K_4R637 10K_4
R353 10K_4R353 10K_4
R356 IV@10K_4R356 IV@10K_4
R643 10K_4R643 10K_4
R347 10K_4R347 10K_4

R648 10K_4R648 10K_4
R638 8.2K_4R638 8.2K_4
R357 10K_4R357 10K_4

R542 IV@10K_4R542 IV@10K_4

UMA only

BOARD_ID0
dGPU_PRSNT#

dGPU always exist

1

PLTRST# (4,10,16,25,26,28,31,34)

R363

R363
SW@100K_4

SW@100K_4

1/11 modified

+3V_S5

R345 10K_4R345 10K_4
R629 10K_4R629 10K_4
R631 10K_4R631 10K_4
R333 *10K_4R333 *10K_4
R332 10K_4R332 10K_4

R537 10K_4R537 10K_4
R541 10K_4R541 10K_4

R367 *10K_4R367 *10K_4

remove GPIO7 PU at 6/1

R335 10K_4R335 10K_4

R307 IV@10K_4R307 IV@10K_4
R344 SW@10K_4R344 SW@10K_4

+3V

+3V

Integrated Clock Chip Enable

BOARD_ID0

A A

RSV_GPIO8

High = SG
Low = UMA
High = Disable
Low = Enable

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

IBEX PEAK-M 4/6

IBEX PEAK-M 4/6

IBEX PEAK-M 4/6

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

ZQ3

ZQ3

ZQ3

1A

1A

11 47Monday, March 29, 2010

11 47Monday, March 29, 2010

11 47Monday, March 29, 2010

1

1A

5

U43G

PCH5(CLG)

VCCCORE(+1.05V) = 1.432A(80mils)

+1.05V

R560 *0/short_8R560 *0/short_8
R551 *0/short_8R551 *0/short_8

+1.05V_VCCCORE_ICH

C461 1u/10V_4C461 1u/10V_4
C471 10u/6.3V_6C471 10u/6.3V_6

IBEX PEAK-M (POWER)

D D

+1.05V

40mA(15mils)

C C

VRM enable by strap pin GPIO27
which supply clean 1.05V for
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL]

37mA(15mils)

B B

L36 *1uH/25mA_6L36 *1uH/25mA_6

+1.05V

L37 *1uH/25mA_6L37 *1uH/25mA_6

C470 *10u/6.3V_6C470 *10u/6.3V_6

VCCVRM=196mA(15mils)

+1.8V

L42 10uH/100mA_8L42 10uH/100mA_8

+1.05V

L45 10uH/100mA_8L45 10uH/100mA_8

A A

C659

C659

220u/2.5V_3528

220u/2.5V_3528

C698

C698

220u/2.5V_3528

220u/2.5V_3528

+V1.1LAN_VCCAPLL_EXP

VCCIO = 3.062A(150mils)

+1.05V

C472 1u/10V_4C472 1u/10V_4
C458 1u/10V_4C458 1u/10V_4
C457 1u/10V_4C457 1u/10V_4
C466 1u/10V_4C466 1u/10V_4
C751 10u/6.3V_6C751 10u/6.3V_6

+3V_VCC_GIO

+V1.5S_1.8S

+V1.1LAN_VCCAPLL_FDI

+1.05V

C476

C476
*10u/6.3V_6

*10u/6.3V_6

R325 *0/short_6R325 *0/short_6

C474

C474

0.1u/16V_4

0.1u/16V_4

+V1.1LAN_VCCA_A_DPL

+

+

C667

C667
1u/10V_4

1u/10V_4

+V1.1LAN_VCCA_B_DPL

+

+

C701

C701

B test move 1u cap at check list

1u/10V_4

1u/10V_4

U43G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

VCCIO[27]

AN24

VCCIO[28]

AN26

VCCIO[29]

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

VCCIO[41]

BA28

VCCIO[42]

BB26

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

VCCIO[52]

BH27

VCCIO[53]

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

+V1.5S_1.8S

C479

C479

0.1u/16V_4

0.1u/16V_4

B test move 1u cap at check list

4

POWER

POWER

VCC CORE

VCC CORE

PCI E*

PCI E*

FDI

FDI

HDA_SYNC (PCH strap pin)

Internal weak pull-down
VCCVRM=>+1.8V (default)
external pull-up
VCCVRM=>+1.5V

DMI

DMI

NAND / SPI

NAND / SPI

CRTLVDS

CRTLVDS

HVCMOS

HVCMOS

VCCADAC[1]

VCCADAC[2]
VSSA_DAC[1]
VSSA_DAC[2]

VCCALVDS

VSSA_LVDS

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

VCC3_3[2]
VCC3_3[3]
VCC3_3[4]

VCCVRM[2]

VCCDMI[1]
VCCDMI[2]

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

+VCCA_DAC_1_2

AE50
AE52
AF53
AF51

AH38
AH39

VCCTX_LVDS

AP43
AP45
AT46
AT45

0.01u/25V_4

0.01u/25V_4

AB34
AB35

+3V_VCC_GIO

AD35

VCCVRM= 196mA(15mils)

AT24

+VCCDM

AT16
AU16

AM16
AK16
AK20

VCCPNAND

AK19
AK15
AK13
AM12
AM13
AM15

AM8

+3V_VCCME_SPI

AM9
AP11
AP9

VCCADAC= 69mA(15mils)

C417

C417

C415

C415

10u/6.3V_6

10u/6.3V_6

22U/6.3V_8

22U/6.3V_8

VCCALVDS= 1mA

C446

C446

0.1u/16V_4

0.1u/16V_4

C427

C427

C425

C425

0.1u/16V_4

0.1u/16V_4

VCC3_3 = 357mA(30mils)

R294 *0/short_4R294 *0/short_4

C438

C438

0.1u/16V_4

0.1u/16V_4

R331 *0/short_4R331 *0/short_4

C487

C487
1u/10V_4

1u/10V_4

VCCPNAND= 156mA(15mils)

C482

C482

0.1u/16V_4

0.1u/16V_4

C490

C490

0.1u/16V_4

0.1u/16V_4

R613 *0/short_8R613 *0/short_8

VCCME3_3= 85mA(15mils)

R339 *0/short_6R339 *0/short_6

L26

L26

BKP1608HS181T/1.5A/180ohm_6

BKP1608HS181T/1.5A/180ohm_6

C419

C419

0.1u/16V_4

0.1u/16V_4

R302 *0/short_4R302 *0/short_4

L27

L27

0.1uH/250mA_8

0.1uH/250mA_8

C422

C422

10u/6.3V_6

10u/6.3V_6

+3V

+V1.5S_1.8S

+1.1V_VTT

+1.8V

+3V

3

+3V

+3V

VCCTX_LVDS= 59mA(15mils)

+1.05V

VCCLAN = 320mA(30mils)

+1.8V

VCCME(+1.05V) = 1.849A(100mils)

+1.05V

VCCDMI= 61mA(15mils)

VCC3_3 = 0.357A(30mils)

V_CPU_IO >1mA(15mils)

VCCRTC= 2mA(15mils)

VCCACLK= 52mA(15mils)

L41 *10uH/100mA_8L41 *10uH/100mA_8

R316 *0_6R316 *0_6

+1.05V

R272 *0/short_8R272 *0/short_8
R266 *0/short_8R266 *0/short_8

+V1.5S_1.8S

68mA(15mils)

69mA(15mils)

VCCIO = 3.062A(150mils)

C491 0.1u/16V_4C491 0.1u/16V_4

C477 0.1u/16V_4C477 0.1u/16V_4

VCCSUS3_3 = 163mA(20mils)

R359 *0/short_6R359 *0/short_6

+3V

R334 *0/short_6R334 *0/short_6

+1.1V_VTT

+VCCRTC

+V1.1LAN_VCCA_CLK

C662 *10u/6.3V_6C662 *10u/6.3V_6
C666 *1u/6.3V_4C666 *1u/6.3V_4

R321

R321
0_4

0_4

TP_PCH_VCCDSW

C473

C473

0.1u/16V_4

0.1u/16V_4

+1.05V_VCCEPW

C416 22u/6.3V_8C416 22u/6.3V_8
C441 22u/6.3V_8C441 22u/6.3V_8
C447 1u/10V_4C447 1u/10V_4
C455 1u/10V_4C455 1u/10V_4

C494 0.1u/16V_4C494 0.1u/16V_4

+V1.1LAN_VCCA_A_DPL

+V1.1LAN_VCCA_B_DPL

+1.05V

C467 1u/10V_4C467 1u/10V_4
C454 1u/10V_4C454 1u/10V_4
C478 1u/10V_4C478 1u/10V_4

+V1.1LAN_INT_VCCSUS

+3V_S5_VCCPSUS

+3V_VCCPCORE

+VTT_VCCPCPU

C493 4.7u/10V_8C493 4.7u/10V_8
C486 0.1u/16V_4C486 0.1u/16V_4
C485 0.1u/16V_4C485 0.1u/16V_4

+VCCRTCEXT

+VCCSST

0.1u/16V_4C464 0.1u/16V_4C464

C481

C481

0.1u/16V_4

0.1u/16V_4

C760

C760

0.1u/16V_4

0.1u/16V_4

2

AP51
AP53

AF23
AF24

Y20

AD38
AD39
AD41
AF43
AF41
AF42

V39
V41
V42
Y39
Y41
Y42

V9

AU24

BB51
BB53

BD51
BD53

AH23
AJ35
AH35

AF34
AH34
AF32

V12

Y22

P18
U19
U20
U22

V15
V16
Y16

AT18

AU18

A12

C766

C766

0.1u/16V_4

0.1u/16V_4

U43J

U43J

VCCACLK[1]
VCCACLK[2]

VCCLAN[1]
VCCLAN[2]

DCPSUSBYP

VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
VCCME[7]
VCCME[8]
VCCME[9]
VCCME[10]
VCCME[11]
VCCME[12]

DCPRTC

VCCVRM[3]

VCCADPLLA[1]
VCCADPLLA[2]

VCCADPLLB[1]
VCCADPLLB[2]

VCCIO[21]
VCCIO[22]
VCCIO[23]

VCCIO[2]
VCCIO[3]
VCCIO[4]
DCPSST

DCPSUS

VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSUS3_3[31]
VCCSUS3_3[32]

VCC3_3[5]
VCC3_3[6]
VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

VCCRTC

IbexPeak-M_R1P0

IbexPeak-M_R1P0

POWER

POWER

Clock and Miscellaneous

Clock and Miscellaneous

CPU

CPU

RTC PCI/GPIO/LPC

RTC PCI/GPIO/LPC

USB

USB

PCI/GPIO/LPC

PCI/GPIO/LPC

SATA

SATA

HDA

HDA

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

VCCIO[56]

V5REF_SUS

V5REF

VCC3_3[8]

VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]

VCCSATAPLL[1]
VCCSATAPLL[2]

VCCIO[9]

VCCVRM[4]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13]

VCCIO[14]

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23
V23
F24

K49

J38
L38
M36
N36
P36
U35

AD13

AK3
AK1

C770

C770

*1u/6.3V_4

*1u/6.3V_4

AH22

AT20

AH19
AD20
AF22
AD19

AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

+V3.3A_1.5A_HDA_IO

L30

C469 1u/10V_4C469 1u/10V_4

+3V_VCCPPCI

+1.05V_VCCEPW

1

VCCIO = 3.062A(150mils)

+3V_S5_VCCPSUS+1.05V_VCCAUX

C497

C497

0.022u/16V_4

0.022u/16V_4

C414

C414
1u/16V_6

1u/16V_6

C412

C412
1u/16V_6

1u/16V_6

C452

C452

0.1u/16V_4

0.1u/16V_4

C428

C428

0.1u/16V_4

0.1u/16V_4

+V1.1LAN_VCCAPLL

+V1.5S_1.8S

VCCSUS3_3 = 0.163A(20mils)

C468

C468

0.1u/16V_4

0.1u/16V_4

0.1u/16V_4

0.1u/16V_4

+1.05V

R265 100/F_4R265 100/F_4
D9 RB500V-40D9 RB500V-40

R259 100/F_4R259 100/F_4
D8 RB500V-40D8 RB500V-40

R300 *0/short_4R300 *0/short_4

VCC3_3 = 0.357A(30mils)

+3V+1.05V

31mA(15mils)

L56 *10uH/100mA_8L56 *10uH/100mA_8

C771

C771
*10u/6.3V_6

*10u/6.3V_6

VCCIO = 3.062A(150mils)

C475

C475
1u/10V_4

1u/10V_4

VCCME = 1.849A(100mils)

R253 *0/short_4R253 *0/short_4

VCCSUSHDA= 6mA(15mils)

C460

C460
1u/10V_4

1u/10V_4

+1.05V

R365 *0/short_6R365 *0/short_6

C463

C463

+1.05V

V5REF_SUS< 1mA

+5V_S5
+3V_S5

V5REF< 1mA

+5V
+3V

+3V

+3V_S5

+3V_S5

+1.05V

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

IBEX PEAK-M 5/6

IBEX PEAK-M 5/6

IBEX PEAK-M 5/6

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

ZQ3

ZQ3

ZQ3

12 47Monday, March 29, 2010

12 47Monday, March 29, 2010

1

12 47Monday, March 29, 2010

1A

1A

1A

5

4

3

2

1

PCH6(CLG)

U43I

U43I

AY7

VSS[159]

BG12

BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49

BC10
BC14
BC18

BC2
BC22
BC32
BC36
BC40
BC44
BC52

BH9
BD48
BD49

BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50

BF49
BF51

BG18
BG24

BG4

BG50

BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47

BH7

AF39

B11
B15
B19
B23
B31
B35
B39
B43
B47

BB5

BE6
BE8
BF3

C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48

F49
G10

G14
G18

G22
G32
G36
G40
G44
G52

H16
H20
H30
H34
H38
H42

VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]

B7

VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]

E6

VSS[238]

E8

VSS[239]
VSS[240]

F5

VSS[241]
VSS[242]
VSS[243]
VSS[244]

G2

VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

IBEX PEAK-M (GND)

D D

U43H

U43H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49

AF12
AH49
AF35

AP13
AN34
AF45
AF46
AF49

AG52

AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47

AJ19
AJ20

AJ22
AJ23
AJ26
AJ28
AJ32
AJ34

AK12

AM41

AN19
AK26
AK22
AK23
AK28

AB5
AB8
AC2

AD7
AE2
AE4

Y13
AU4

AF5
AF8
AG2

AH7
AJ2

AT5
AJ4

VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

C C

B B

A A

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

IbexPeak-M_R1P0

IbexPeak-M_R1P0

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

IBEX PEAK-M 6/6

IBEX PEAK-M 6/6

IBEX PEAK-M 6/6

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

ZQ3

ZQ3

ZQ3

13 47Monday, March 29, 2010

13 47Monday, March 29, 2010

13 47Monday, March 29, 2010

1A

1A

1A

5

DDR_STD(DDR)

M_A_A[15:0](5)

D D

M_A_BS#0(5)
M_A_BS#1(5)
M_A_BS#2(5)
M_A_CS#0(5)
M_A_CS#1(5)
M_A_CLKP0(5)
M_A_CLKN0(5)
M_A_CLKP1(5)
M_A_CLKN1(5)
M_A_CKE0(5)
M_A_CKE1(5)
M_A_CAS#(5)
M_A_RAS#(5)

R241 10K_4R241 10K_4

10K_4

10K_4

R244

R244

C C

B B

M_A_WE#(5)

CLK_SCLK(3,15,28)

CLK_SDATA(3,15,28)

M_A_ODT0(5)
M_A_ODT1(5)

M_A_DM[7:0](5)

M_A_DQSP[7:0](5)

M_A_DQSN[7:0](5)

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

DIMM0_SA0
DIMM0_SA1
CLK_SCLK
CLK_SDATA

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7

107

119

109
108

114
121
101
103
102
104

115
110
113
197
201
202
200

116
120

136
153
170
187

137
154
171
188

135
152
169
186

98

97

96

95

92

91

90

86

89

85

84

83

80

78

79

73

74

11

28

46

63

12

29

47

64

10

27

45

62

JDIM1A

JDIM1A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

4

M_A_DQ5
M_A_DQ4
M_A_DQ2
M_A_DQ3
M_A_DQ0
M_A_DQ1
M_A_DQ7
M_A_DQ6
M_A_DQ8
M_A_DQ9
M_A_DQ11
M_A_DQ14
M_A_DQ13
M_A_DQ12
M_A_DQ15
M_A_DQ10
M_A_DQ20
M_A_DQ21
M_A_DQ19
M_A_DQ23
M_A_DQ17
M_A_DQ16
M_A_DQ22
M_A_DQ18
M_A_DQ28
M_A_DQ25
M_A_DQ31
M_A_DQ27
M_A_DQ29
M_A_DQ24
M_A_DQ26
M_A_DQ30
M_A_DQ32
M_A_DQ33
M_A_DQ35
M_A_DQ39
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ34
M_A_DQ41
M_A_DQ40
M_A_DQ46
M_A_DQ47
M_A_DQ45
M_A_DQ44
M_A_DQ43
M_A_DQ42
M_A_DQ53
M_A_DQ48
M_A_DQ50
M_A_DQ51
M_A_DQ49
M_A_DQ52
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ63
M_A_DQ62

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

(204P)

(204P)

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

3

M_A_DQ[63:0] (5)

0831:Remove M2 CKT.

+SMDDR_VREF_DQ0(31)

+SMDDR_VREF

VREF_DQ_DIMM0(7,31)

+SMDDR_VREF

R138 *M1@0/short_6R138 *M1@0/short_6
R139 *M3@0_6R139 *M3@0_6

R182 *0/short_6R182 *0/short_6

+3V

PM_EXTTS#0(4)

DDR3_DRAMRST#(15,31)

+1.5V_SUS

R172

R172
*10K_4

*10K_4

+SMDDR_VREF_DIMM

R187

R187
*10K_4

*10K_4

+1.5V_SUS

2.48A

+3V

R245 *10K_4R245 *10K_4

+SMDDR_VREF_DQ0

+SMDDR_VREF_DIMM

C362

C362
470p/50V_4

470p/50V_4

2

JDIM1B

JDIM1B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM0_H=4_Standard

DDR3-DIMM0_H=4_Standard

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

(204P)

(204P)

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

GND
GND

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203
204

205
206

1

+0.75V_DDR_VTT

DDR3-DIMM0_H=4_Standard

DDR3-DIMM0_H=4_Standard

Place these Caps near So-Dimm0.

+1.5V_SUS

C306

C305

C305
10u/6.3V_6

10u/6.3V_6

C397

C397

0.1u/16V_4

0.1u/16V_4

5

C306
10u/6.3V_6

10u/6.3V_6

C317

C317

0.1u/16V_4

0.1u/16V_4

+0.75V_DDR_VTT

C399

C399
1u/6.3V_4

1u/6.3V_4

C314

C314

0.1u/16V_4

0.1u/16V_4

C321

C321

0.1u/16V_4

0.1u/16V_4

C301

C301

0.1u/16V_4

0.1u/16V_4

C404

C404
1u/6.3V_4

1u/6.3V_4

C300

C300

0.1u/16V_4

0.1u/16V_4

C403

C403
1u/6.3V_4

1u/6.3V_4

+

+

C298

C298
330u/2V_7343

330u/2V_7343

C344

C344
10u/6.3V_6

10u/6.3V_6

C326

C326

10u/6.3V_6

10u/6.3V_6

A A

+3V

C293

C293
10u/6.3V_6

10u/6.3V_6

C387

C387

2.2u/6.3V_6

2.2u/6.3V_6

C341

C341
10u/6.3V_6

10u/6.3V_6

+SMDDR_VREF_DIMM

0.1u/16V_4

0.1u/16V_4
C359

C359

C400

C400
1u/6.3V_4

1u/6.3V_4

4

C358

C358

2.2u/6.3V_6

2.2u/6.3V_6

C396

C396

10u/6.3V_6

10u/6.3V_6

maybe can save

+SMDDR_VREF_DQ0

C248

C248

0.1u/16V_4

0.1u/16V_4

C405

C405

10u/6.3V_6

10u/6.3V_6

2.2u/6.3V_6

2.2u/6.3V_6

C407

C407

10u/6.3V_6

10u/6.3V_6

C246

C246

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDRIII SO-DIMM-0

DDRIII SO-DIMM-0

DDRIII SO-DIMM-0

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

PROJECT :

ZQ3

ZQ3

ZQ3

1

1A

1A

1A

14 47Monday, March 29, 2010

14 47Monday, March 29, 2010

14 47Monday, March 29, 2010

5

4

3

2

1

DDR_STD(DDR)

M_B_A[15:0](5)

D D

M_B_BS#0(5)
M_B_BS#1(5)
M_B_BS#2(5)
M_B_CS#0(5)
M_B_CS#1(5)
M_B_CLKP0(5)
M_B_CLKN0(5)
M_B_CLKP1(5)
M_B_CLKN1(5)
M_B_CKE0(5)
M_B_CKE1(5)
M_B_CAS#(5)
M_B_RAS#(5)

R240 10K_4R240 10K_4
R243 10K_4R243 10K_4

C C

B B

M_B_WE#(5)

CLK_SCLK(3,14,28)

CLK_SDATA(3,14,28)

M_B_ODT0(5)
M_B_ODT1(5)

M_B_DM[7:0](5)

M_B_DQSP[7:0](5)

M_B_DQSN[7:0](5)

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

DIMM1_SA0
DIMM1_SA1

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7

JDIM2A

JDIM2A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

PC2100 DDR3 SDRAM SO-DIMM

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

PC2100 DDR3 SDRAM SO-DIMM

12
29
47

64
137
154
171
188

10

27

45

62
135
152
169
186

DDR3-DIMM1_H=8_Standard

DDR3-DIMM1_H=8_Standard

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

(204P)

(204P)

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

M_B_DQ5
M_B_DQ4
M_B_DQ7
M_B_DQ3
M_B_DQ1
M_B_DQ0
M_B_DQ2
M_B_DQ6
M_B_DQ12
M_B_DQ13
M_B_DQ11
M_B_DQ14
M_B_DQ8
M_B_DQ9
M_B_DQ15
M_B_DQ10
M_B_DQ17
M_B_DQ20
M_B_DQ19
M_B_DQ23
M_B_DQ21
M_B_DQ16
M_B_DQ22
M_B_DQ18
M_B_DQ29
M_B_DQ28
M_B_DQ30
M_B_DQ31
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ37
M_B_DQ36
M_B_DQ38
M_B_DQ39
M_B_DQ33
M_B_DQ32
M_B_DQ34
M_B_DQ35
M_B_DQ41
M_B_DQ40
M_B_DQ46
M_B_DQ47
M_B_DQ44
M_B_DQ45
M_B_DQ43
M_B_DQ42
M_B_DQ52
M_B_DQ53
M_B_DQ55
M_B_DQ54
M_B_DQ49
M_B_DQ48
M_B_DQ51
M_B_DQ50
M_B_DQ56
M_B_DQ57
M_B_DQ62
M_B_DQ63
M_B_DQ60
M_B_DQ61
M_B_DQ59
M_B_DQ58

M_B_DQ[63:0] (5)

0831:Remove M2 CKT.

+SMDDR_VREF_DQ1(31)

+SMDDR_VREF

VREF_DQ_DIMM1(7,31)

+3V

PM_EXTTS#1(4)

DDR3_DRAMRST#(14,31)

R120 *M1@0/short_6R120 *M1@0/short_6
R119 *M3@0_6R119 *M3@0_6

+SMDDR_VREF_DIMM+3V

2.48A

R242 *10K_4R242 *10K_4

+1.5V_SUS

+3V

+SMDDR_VREF_DQ1

JDIM2B

JDIM2B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM1_H=8_Standard

DDR3-DIMM1_H=8_Standard

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

(204P)

(204P)

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

GND
GND

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203
204

205
206

+0.75V_DDR_VTT

+1.5V_SUS

C291

C291
10u/6.3V_6

10u/6.3V_6

+3V

A A

Place these Caps near So-Dimm1.

C307

C307
10u/6.3V_6

10u/6.3V_6

C423

C423

2.2u/6.3V_6

2.2u/6.3V_6

C299

C299
10u/6.3V_6

10u/6.3V_6

C316

C316
10u/6.3V_6

10u/6.3V_6

C398

C398

0.1u/16V_4

0.1u/16V_4

C336

C336
10u/6.3V_6

10u/6.3V_6

+0.75V_DDR_VTT

5

C350

C350
10u/6.3V_6

10u/6.3V_6

C340

C340

0.1u/16V_4

0.1u/16V_4

C402

C402
1u/6.3V_4

1u/6.3V_4

C297

C297

0.1u/16V_4

0.1u/16V_4

C290

C290

0.1u/16V_4

0.1u/16V_4

C393

C393
1u/6.3V_4

1u/6.3V_4

C289

C289

0.1u/16V_4

0.1u/16V_4

C349

C349

0.1u/16V_4

0.1u/16V_4

C401

C401
1u/6.3V_4

1u/6.3V_4

+SMDDR_VREF_DIMM

+

+

0.1u/16V_4

0.1u/16V_4

C263

C263

330u/2V_7343

330u/2V_7343

C392

C392
1u/6.3V_4

1u/6.3V_4

C361

C361

10u/6.3V_6

10u/6.3V_6

4

C406

C406

+SMDDR_VREF_DQ1

0.1u/16V_4

0.1u/16V_4
C233

C233

C360

C360

2.2u/6.3V_6

2.2u/6.3V_6

C394

C394

10u/6.3V_6

10u/6.3V_6

maybe can save

2.2u/6.3V_6

2.2u/6.3V_6
C235

C235

C395

C395
10u/6.3V_6

10u/6.3V_6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDRIII SO-DIMM-1

DDRIII SO-DIMM-1

DDRIII SO-DIMM-1

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

PROJECT :

ZQ3

ZQ3

ZQ3

1

1A

1A

1A

15 47Monday, March 29, 2010

15 47Monday, March 29, 2010

15 47Monday, March 29, 2010