Acer SWIFT SF314-51 Schematic

SYSTEM PAGE REF.

5

4

3

2

1

01. Block Diagram

02. GPIO Setting

03. CPU(1)_DDI/eDP

04. CPU(2)_DDR4

05. CPU(3)_+VCCCORE

06. CPU(4)_+VCCGT

D D

07. CPU(5)_+VDDQ/IO/SA

08. CPU(6)_CPU GND

09. CPU(7)_CFG/RSVD

15. DDR4(0)_Termination

16. DDR4(1)_CH0

17. DDR4(2)_CH1

19. DDR4(4)_CA/DQ Voltage

20. PCH(1)_SPI/LPC

21. PCH(2)_ISH

22. PCH(3)_HDA/SDIO

23. PCH(4)_USB/PCIE/SATA

24. PCH(5)_CLK/RTC

25. PCH(6)_POWER MANAGEMENT

26. PCH(7)_POWER

28. PCH(9)_SPI/SMB

30. EC_IT8587/FX

31. EC_IT8587E/FX_KB/TP/KBBL

32. RST_Reset Circuit

36. AUD_ALC255

37. AUD(2)_SPK/DMIC

C C

41. USB_Type-C ANX7428

42. USB Type-C Receptacle

43. USB Type-C Dead Battery

44. Debug CONN

45. CRT(1)_eDP,CAMERA,TSN

47. HDMI Repeater PS8201A

48. HDMI OUT

50. THERMAL / FAN

51. NGFF PCIE*4/SATA SSD

52. USB 3.0/Sleep Charge IC

53. NGFF PCIE WLAN/BT

56. LED

57. Discharge

60. DC_DC/BAT CONN
62 TPM NPCT650

64. IO Board

65. ME_CONN / Skew Hole

68. BYPASS EC SEQUENCE
80_POWER_VCORE for U22

B B

81_POWER_SYSTEM
82_POWER_+1.0VSUS
83_POWER_ DDR & VTT_UMA
84_POWER_ 1.8VSUS
85_POWER_ 1.5VS
86_POWER_XXX
87_POWER_XXX
88_POWER_CHARGER
89_POWER_AC_PD_WC Input
90_POWER_DETECT
91_POWER_LOAD SWITCH
92_POWER_PROTECT
93_POWER_SIGNAL
94_POWER_FLOWCHART
A02. AUD(2)_JACK
A03. USB20
A04. CB_RTS5170_GR

14" Cassiopeia (X3) for Skylake U Platform Block Diagram

PANEL

HDMI

page48

SPEAKER X 2

page37

COMBO JACK

pageA02

DMIC X 1

page37

NGFF SSD

page51

D

EBUG CONN.

page44

TPM

NUVOTON/NPCT650

page62

KB

page31

Click Pad

page31

Thermal

page50

HDMI Repeater
PS8201A

Audio Codec
REALTEK/ ALC255

EC

IT8987E/BX

SPI ROM (16M)

page28

SPI ROM (8M)

page28

page36

page30

eDP

D

DI 1/2

HDA

PCIE

SATA

SPI

INTEL

Skylake U

TDP 15W

LPC

DDR4 2133MHz
Channel A

Channel B

USB 3.0 3/4

DDI 2

PCI-E 6/10

USB 2.0 5/10

USB 3.0 1/4

USB 2.0 1/10

USB 2.0 7/10

USB 2.0 2/10

USB 2.0 6/10

USB 2.0 3/10

USB 2.0 4/10

Analogix

ANX7428

MUX

page41

USB2.0 8/10

USB2.0 9/10

DDR4

M

emory Down x4

Memory Down x4

page16

DDR4DDR4 2133MHz

page17

N

GFF

WLAN / BT

USB 3.0 Conn x1

/charger

W

Front Camera /0.3M

USB2.0 Conn x1

Fingerprinter

Type C

page42

Card Reader

Realtek/RTS5170

Touch Panel

pageA03

pageA05

PageA04

page45

page52

page45

page53

System (5V & 3.3V)

+1.0VSUS

VCCPRIM_CORE

DDR & VTT

BATTERY CHARGER

Power

+VCORE
+VCCGT

+VCCSA

+1.5VS
+1.8VSUS

DETECT

LOAD SWITCH

Power Protect

Page 80

PMIC

Page 81

Page 84

Page 88

Page 90

Page 91

Page 92

A A

Discharge Circuit

Reset Circuit

5

4

3

Page 57

Page 32

DC & BATT. Conn.

Page 60

Skew Holes

2

Page 65

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Block Diagram

Block Diagram

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

X3

X3

X3

Engineer:

Engineer:

Engineer:

1

Block Diagram

Andy Kao

Andy Kao

Andy Kao

1 97Monday, July 11, 2016

1 97Monday, July 11, 2016

1 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

Use As Signal NameEC GPIO EC GPIO Use As Signal NameUse As Signal NameEC GPIO Use As Signal NameEC GPIO

D D

C C

B B

A A

Title :

Title :

Title :

GPIO Setting

GPIO Setting

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

X3

X3

X3

Engineer:

Engineer:

Engineer:

1

GPIO Setting

Andy Kao

Andy Kao

Andy Kao

2 97Monday, July 11, 2016

2 97Monday, July 11, 2016

2 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

DDI Port 1: HDMI eDP x 4

DDI Port 2: TYPE-C DP

+VCCIO

C C

DDI1_TXN247
DDI1_TXP247
DDI1_TXN147
DDI1_TXP147
DDI1_TXN047
DDI1_TXP047
DDI1_CLKN47
DDI1_CLKP47

DDI2_TXN041
DDI2_TXP041
DDI2_TXN141
DDI2_TXP141
DDI2_TXN241
DDI2_TXP241
DDI2_TXN341
DDI2_TXP341

DDPB_CTRLCLK47

DDPB_CTRLDATA47

R0301 24.9Ohm1%

12

DDPC_CTRLCLK
DDPC_CTRLDATA

DP_COMP

4

SKYLAKE-U symbol ReV0.53 #545316 / Ballout_Rev0_71 #543787 / PEGA local PN is 4201-0062000

U0301A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

eDP_RCOMP

940432

01V010000015

DDI

DISPLAY SIDEBANDS

EDP

EDP_DISP_UTIL

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP

RSVD_1
RSVD_2

eDP_BKLTEN

eDP_BKLTCTL

eDP_VDDEN

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

G50
F50
E48
F48
G46
F46

L9
L7
L6
N9
L10

R12
R11
U13

3

+VCCIO

+VCCST_CPU

+VCCSTG

+3VS

EXT_SMI#_R EXT_SMI#
EXT_SCI#_R EXT_SCI#
eDP_HPD

1 2

R0302 0Ohm

1 2

R0303 0Ohm

2

+VCCIO 7,9,57,91

+VCCST_CPU 5,7,9,25,32

+VCCSTG 5,7

+3VS 4,21,22,23,24,30,31,32,36,37,44,45,47,50,51,53,57,62,64,91,92

EDP_TXN0 45
EDP_TXP0 45
EDP_TXN1 45
EDP_TXP1 45
EDP_TXN2 45
EDP_TXP2 45
EDP_TXN3 45
EDP_TXP3 45

EDP_AUXN 45

EDP_AUXP 45

DDI2_AUXN 41

DDI2_AUXP 41

DDI1_HPD 47
DDI2_HPD 41
EXT_SMI# 30,44
EXT_SCI# 30
eDP_HPD 45

LCD_BKLTEN_PCH 21,45

LCD_BL_PWM_PCH 45

EDP_VDD_EN 45

-- WQHD 4 Lane

-- FHD 2 Lane

Pull down at connector side

DDPB_CTRLDATA
DDPC_CTRLDATA
DDPD_CTRLDATA

- Internal weak pull down 20k ohm

- 0 : port is not detected
1 : port is deteccted

DDPB_CTRLDATA

DDPB_CTRLCLK

EXT_SCI#

EXT_SMI#

DDPC_HPD
DP: 100Kohm pull down on PCH Side
HDMI: 20Kohm pull down

DDI2_HPD

DDPC_CTRLDATA

DDPC_CTRLCLK

R0304 2.2KOhm@

R0338 2.2KOhm@

R0307 10KOhm

R0308 10KOhm

R0337 100KOhm

R0342 2.2KOhm

R0343 2.2KOhm

R1.0_10L ---Enable DP port

1

1 2

1 2

1 2

1 2

1 2

1 2

1 2

+3VS

+3VS

+3VS

141024 follow PDG V1.0 Table 10-4
Rpu = 1K ohm 5%
Rs = 500 ohm 5%

12

R0311
1KOhm

H_THRMTRIP#32

B B

THRO_CPU30

PROCHOT#88

A A

VR_HOT#80

1

G

2

S

Q0301
2N7002

5

12

R0312
1KOhm

5%

H_PECI_EC30

H_PROCHOT# PROCHOT#_R

1

3

32

R0341 0Ohm

D

SP0325 0Ohm

R0320 0Ohm@

1 2

R0314 499Ohm1%

R0341

由

EC control

(depends on under-shoot measurement result),預預0ohm

觸觸觸觸觸觸觸觸觸觸觸觸觸

12

H_PROCHOT#

12

12

Closeer EC

R0315 43Ohm5%

SP0301

1 2

R0316 49.9Ohm1%

1 2

R0317 49.9Ohm1%

1 2

R0318 49.9Ohm1%

1 2

R0319 49.9Ohm1%

1 2

1 2

70-200 ohm

4

+VCCST_CPU+VCCSTG+VCCST_CPU

T0306

觸是是是是

12

R0313

49.9Ohm

1%
@

TP_CATERR#_R
H_PECI

H_THRMTRIP#_R

1

SKTOCC#

CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP

AT16
AU16

D63
A54
C65
C63
A65

C55
D55
B54
C56

BA5
AY5

H66
H65

A6
A7

01V010000015

U0301D

CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#

CPU MISC

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

940432

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

3

B61

XDP_TCLK

D60

XDP_TDI_CPU

A61

XDP_TDO_CPU

C60

XDP_TMS_CPU

B59

XDP_TRST_CPU_N

B56

PCH_JTAG_TCLK

D59

PCH_JTAG_TDI

A56

PCH_JTAG_TDO

C59

PCH_JTAG_TMS

C61

PCH_TRST_CPU_N XDP_TCLKXDP_TCLK_JTAGX

A59

XDP_TCLK_JTAGX

JTAGX

1

T0315

PCH_JTAG_TMS XDP_TMS_CPU

XDP_TDO_CPUPCH_JTAG_TDO

XDP_TRST_CPU_NPCH_TRST_CPU_N

XDP_TDI_CPUPCH_JTAG_TDI

2

R0323 51Ohm

R0324 51Ohm

12

12

+VCCSTG

1

T0316

1

T0317

1

T0318

Modify to XDP less

<Variant Name>

<Variant Name>

<Variant Name>

CPU(1)_DDI/eDP

CPU(1)_DDI/eDP

CPU(1)_DDI/eDP

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

X3

X3

Date: Sheet of

Date: Sheet of

Date: Sheet

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

3 97Monday, July 11, 2016

3 97Monday, July 11, 2016

3 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

of

5

4

3

2

1

U0301B

M_A_D[15 ..0]16

D D

M_A_D[47 ..32]16

M_B_D[15 ..0]17

C C

M_B_D[47 ..32]17

B B

M_A_D0
M_A_D1
M_A_D2
M_A_D3
M_A_D4
M_A_D5
M_A_D6
M_A_D7
M_A_D8
M_A_D9
M_A_D10
M_A_D11
M_A_D12
M_A_D13
M_A_D14
M_A_D15
M_A_D32
M_A_D33
M_A_D34
M_A_D35
M_A_D36
M_A_D37
M_A_D38
M_A_D39
M_A_D40
M_A_D41
M_A_D42
M_A_D43
M_A_D44
M_A_D45
M_A_D46
M_A_D47
M_B_D0
M_B_D1
M_B_D2
M_B_D3
M_B_D4
M_B_D5
M_B_D6
M_B_D7
M_B_D8
M_B_D9
M_B_D10
M_B_D11
M_B_D12
M_B_D13
M_B_D14
M_B_D15
M_B_D32
M_B_D33
M_B_D34
M_B_D35
M_B_D36
M_B_D37
M_B_D38
M_B_D39
M_B_D40
M_B_D41
M_B_D42
M_B_D43
M_B_D44
M_B_D45
M_B_D46
M_B_D47

AW65
AW63

AW61

AW59

AW39

AW37

AW35

AW33

AW31

AW29

AW27

AW25

AL71

DDR0_DQ[0 ]

AL68

DDR0_DQ[1 ]

AN68

DDR0_DQ[2 ]

AN69

DDR0_DQ[3 ]

AL70

DDR0_DQ[4 ]

AL69

DDR0_DQ[5 ]

AN70

DDR0_DQ[6 ]

AN71

DDR0_DQ[7 ]

AR70

DDR0_DQ[8 ]

AR68

DDR0_DQ[9 ]

AU71

DDR0_DQ[1 0]

AU68

DDR0_DQ[1 1]

AR71

DDR0_DQ[1 2]

AR69

DDR0_DQ[1 3]

AU70

DDR0_DQ[1 4]

AU69

DDR0_DQ[1 5]

BB65

DDR0_DQ[1 6]/DDR0_DQ[32 ]
DDR0_DQ[1 7]/DDR0_DQ[33 ]
DDR0_DQ[1 8]/DDR0_DQ[34 ]

AY63

DDR0_DQ[1 9]/DDR0_DQ[35 ]

BA65

DDR0_DQ[2 0]/DDR0_DQ[36 ]

AY65

DDR0_DQ[2 1]/DDR0_DQ[37 ]

BA63

DDR0_DQ[2 2]/DDR0_DQ[38 ]

BB63

DDR0_DQ[2 3]/DDR0_DQ[39 ]

BA61

DDR0_DQ[2 4]/DDR0_DQ[40 ]
DDR0_DQ[2 5]/DDR0_DQ[41 ]

BB59

DDR0_DQ[2 6]/DDR0_DQ[42 ]
DDR0_DQ[2 7]/DDR0_DQ[43 ]

BB61

DDR0_DQ[2 8]/DDR0_DQ[44 ]

AY61

DDR0_DQ[2 9]/DDR0_DQ[45 ]

BA59

DDR0_DQ[3 0]/DDR0_DQ[46 ]

AY59

DDR0_DQ[3 1]/DDR0_DQ[47 ]

AY39

DDR0_DQ[3 2]/DDR1_DQ[0]
DDR0_DQ[3 3]/DDR1_DQ[1]

AY37

DDR0_DQ[3 4]/DDR1_DQ[2]
DDR0_DQ[3 5]/DDR1_DQ[3]

BB39

DDR0_DQ[3 6]/DDR1_DQ[4]

BA39

DDR0_DQ[3 7]/DDR1_DQ[5]

BA37

DDR0_DQ[3 8]/DDR1_DQ[6]

BB37

DDR0_DQ[3 9]/DDR1_DQ[7]

AY35

DDR0_DQ[4 0]/DDR1_DQ[8]
DDR0_DQ[4 1]/DDR1_DQ[9]

AY33

DDR0_DQ[4 2]/DDR1_DQ[10 ]
DDR0_DQ[4 3]/DDR1_DQ[11 ]

BB35

DDR0_DQ[4 4]/DDR1_DQ[12 ]

BA35

DDR0_DQ[4 5]/DDR1_DQ[13 ]

BA33

DDR0_DQ[4 6]/DDR1_DQ[14 ]

BB33

DDR0_DQ[4 7]/DDR1_DQ[15 ]

AY31

DDR0_DQ[4 8]/DDR1_DQ[32 ]
DDR0_DQ[4 9]/DDR1_DQ[33 ]

AY29

DDR0_DQ[5 0]/DDR1_DQ[34 ]
DDR0_DQ[5 1]/DDR1_DQ[35 ]

BB31

DDR0_DQ[5 2]/DDR1_DQ[36 ]

BA31

DDR0_DQ[5 3]/DDR1_DQ[37 ]

BA29

DDR0_DQ[5 4]/DDR1_DQ[38 ]

BB29

DDR0_DQ[5 5]/DDR1_DQ[39 ]

AY27

DDR0_DQ[5 6]/DDR1_DQ[40 ]
DDR0_DQ[5 7]/DDR1_DQ[41 ]

AY25

DDR0_DQ[5 8]/DDR1_DQ[42 ]
DDR0_DQ[5 9]/DDR1_DQ[43 ]

BB27

DDR0_DQ[6 0]/DDR1_DQ[44 ]

BA27

DDR0_DQ[6 1]/DDR1_DQ[45 ]

BA25

DDR0_DQ[6 2]/DDR1_DQ[46 ]

BB25

DDR0_DQ[6 3]/DDR1_DQ[47 ]

940432

01V0100 00015

IL Channel A[0..63]

NIL Channel A[0..15]
NIL Channel A[32..47]

NIL Channel B[0..15]
NIL Channel B[32..47]

IL Channel A DQS[0..7]

NIL Channel A
DQS[0,1,4,5]

NIL Channel B
DQS[0,1,4,5]

DDR CH - A

DDR0_MA[5 ]/DDR0_CAA[0] /DDR0_MA[5]
DDR0_MA[9 ]/DDR0_CAA[1] /DDR0_MA[9]
DDR0_MA[6 ]/DDR0_CAA[2] /DDR0_MA[6]
DDR0_MA[8 ]/DDR0_CAA[3] /DDR0_MA[8]
DDR0_MA[7 ]/DDR0_CAA[4] /DDR0_MA[7]

DDR0_BA[2 ]/DDR0_CAA[5 ]/DDR0_BG[0]
DDR0_MA[1 2]/DDR0_CAA[6 ]/DDR0_MA[12 ]
DDR0_MA[1 1]/DDR0_CAA[7 ]/DDR0_MA[11 ]

DDR0_MA[1 5]/DDR0_CAA[8 ]/DDR0_ACT#

DDR0_MA[1 4]/DDR0_CAA[9 ]/DDR0_BG[1]

DDR0_MA[1 3]/DDR0_CAB[0 ]/DDR0_MA[13 ]

DDR0_CAS# /DDR0_CAB[1] /DDR0_MA[15]

DDR0_WE #/DDR0_CAB[ 2]/DDR0_MA[14 ]

DDR0_RAS# /DDR0_CAB[3] /DDR0_MA[16]

DDR0_BA[0 ]/DDR0_CAB[4 ]/DDR0_BA[0]

DDR0_MA[2 ]/DDR0_CAB[5] /DDR0_MA[2]

DDR0_BA[1 ]/DDR0_CAB[6 ]/DDR0_BA[1]
DDR0_MA[1 0]/DDR0_CAB[7 ]/DDR0_MA[10 ]

DDR0_MA[1 ]/DDR0_CAB[8] /DDR0_MA[1]
DDR0_MA[0 ]/DDR0_CAB[9] /DDR0_MA[0]

DDR0_DQSN [2]/DDR0_DQSN [4]
DDR0_DQSP [2]/DDR0_DQS P[4]
DDR0_DQSN [3]/DDR0_DQSN [5]
DDR0_DQSP [3]/DDR0_DQS P[5]
DDR0_DQSN [4]/DDR1_DQSN [0]
DDR0_DQSP [4]/DDR1_DQS P[0]
DDR0_DQSN [5]/DDR1_DQSN [1]
DDR0_DQSP [5]/DDR1_DQS P[1]
DDR0_DQSN [6]/DDR1_DQSN [4]
DDR0_DQSP [6]/DDR1_DQS P[4]
DDR0_DQSN [7]/DDR1_DQSN [5]
DDR0_DQSP [7]/DDR1_DQS P[5]

DDR0_VREF _DQ
DDR1_VREF _DQ

DDR_VTT_CNTL

DDR0_CKN[0 ]
DDR0_CKP[ 0]
DDR0_CKN[1 ]
DDR0_CKP[ 1]

DDR0_CKE[ 0]
DDR0_CKE[ 1]
DDR0_CKE[ 2]
DDR0_CKE[ 3]

DDR0_CS#[ 0]
DDR0_CS#[ 1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3 ]
DDR0_MA[4 ]

DDR0_DQSN [0]
DDR0_DQSP [0]
DDR0_DQSN [1]
DDR0_DQSP [1]

DDR0_ALE RT#

DDR0_PAR

DDR_VREF_ CA

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26

AW50
AT52

AY67
AY68
BA67

AW67

M_A_A5
M_A_A9
M_A_A6
M_A_A8
M_A_A7

M_A_A12
M_A_A11

M_A_A13

M_A_A2

M_A_A10
M_A_A1
M_A_A0
M_A_A3
M_A_A4

M_A_DQS# 0
M_A_DQS0
M_A_DQS# 1
M_A_DQS1
M_A_DQS# 4
M_A_DQS4
M_A_DQS# 5
M_A_DQS5
M_B_DQS# 0
M_B_DQS0
M_B_DQS# 1
M_B_DQS1
M_B_DQS# 4
M_B_DQS4
M_B_DQS# 5
M_B_DQS5

DDR_VTT_CTRL

M_A_DIM0_ CK_DDR0_DN 15,16
M_A_DIM0_ CK_DDR0_DP 15,16

M_A_DIM0_ CKE0 15,16

M_A_DIM0_ CS0_N 15,16

M_A_DIM0_ ODT0 15,16

M_A_BG0 15,16

M_A_ACT_N 15,1 6

M_A_A15 _CAS_N 15,16
M_A_A14 _WE_N 15,16
M_A_A16 _RAS_N 15,16
M_A_BA0 15,16

M_A_BA1 15,16

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_DQS[ 7:0] 16

M_A_DQS# [7:0] 16

M_A_DQS7
M_A_DQS6
M_A_DQS5
M_A_DQS4
M_A_DQS3
M_A_DQS2
M_A_DQS1
M_A_DQS0
M_A_DQS# 7
M_A_DQS# 6
M_A_DQS# 5
M_A_DQS# 4
M_A_DQS# 3
M_A_DQS# 2
M_A_DQS# 1
M_A_DQS# 0

DDR0_A_A LERT_N 15, 16
DDR0_A_P ARITY 1 5,16

DDR_VREF_ CA 19

DDR_VREF_ DQ 19

M_A_D[31 ..16]16

M_A_D[63 ..48]16

M_B_D[31 ..16]17

M_B_D[63 ..48]17

M_A_A[13 :0] 15,16

+1.2V +3VSUS+3VS

M_A_D16
M_A_D17
M_A_D18
M_A_D19
M_A_D20
M_A_D21
M_A_D22
M_A_D23
M_A_D24
M_A_D25
M_A_D26
M_A_D27
M_A_D28
M_A_D29
M_A_D30
M_A_D31
M_A_D48
M_A_D49
M_A_D50
M_A_D51
M_A_D52
M_A_D53
M_A_D54
M_A_D55
M_A_D56
M_A_D57
M_A_D58
M_A_D59
M_A_D60
M_A_D61
M_A_D62
M_A_D63
M_B_D16
M_B_D17
M_B_D18
M_B_D19
M_B_D20
M_B_D21
M_B_D22
M_B_D23
M_B_D24
M_B_D25
M_B_D26
M_B_D27
M_B_D28
M_B_D29
M_B_D30
M_B_D31
M_B_D48
M_B_D49
M_B_D50
M_B_D51
M_B_D52
M_B_D53
M_B_D54
M_B_D55
M_B_D56
M_B_D57
M_B_D58
M_B_D59
M_B_D60
M_B_D61
M_B_D62
M_B_D63

U0301C

AF65

DDR1_DQ[0 ]/DDR0_DQ[16]

AF64

DDR1_DQ[1 ]/DDR0_DQ[17]

AK65

DDR1_DQ[2 ]/DDR0_DQ[18]

AK64

DDR1_DQ[3 ]/DDR0_DQ[19]

AF66

DDR1_DQ[4 ]/DDR0_DQ[20]

AF67

DDR1_DQ[5 ]/DDR0_DQ[21]

AK67

DDR1_DQ[6 ]/DDR0_DQ[22]

AK66

DDR1_DQ[7 ]/DDR0_DQ[23]

AF70

DDR1_DQ[8 ]/DDR0_DQ[24]

AF68

DDR1_DQ[9 ]/DDR0_DQ[25]

AH71

DDR1_DQ[1 0]/DDR0_DQ[26 ]

AH68

DDR1_DQ[1 1]/DDR0_DQ[27 ]

AF71

DDR1_DQ[1 2]/DDR0_DQ[28 ]

AF69

DDR1_DQ[1 3]/DDR0_DQ[29 ]

AH70

DDR1_DQ[1 4]/DDR0_DQ[30 ]

AH69

DDR1_DQ[1 5]/DDR0_DQ[31 ]

AT66

DDR1_DQ[1 6]/DDR0_DQ[48 ]

AU66

DDR1_DQ[1 7]/DDR0_DQ[49 ]

AP65

DDR1_DQ[1 8]/DDR0_DQ[50 ]

AN65

DDR1_DQ[1 9]/DDR0_DQ[51 ]

AN66

DDR1_DQ[2 0]/DDR0_DQ[52 ]

AP66

DDR1_DQ[2 1]/DDR0_DQ[53 ]

AT65

DDR1_DQ[2 2]/DDR0_DQ[54 ]

AU65

DDR1_DQ[2 3]/DDR0_DQ[55 ]

AT61

DDR1_DQ[2 4]/DDR0_DQ[56 ]

AU61

DDR1_DQ[2 5]/DDR0_DQ[57 ]

AP60

DDR1_DQ[2 6]/DDR0_DQ[58 ]

AN60

DDR1_DQ[2 7]/DDR0_DQ[59 ]

AN61

DDR1_DQ[2 8]/DDR0_DQ[60 ]

AP61

DDR1_DQ[2 9]/DDR0_DQ[61 ]

AT60

DDR1_DQ[3 0]/DDR0_DQ[62 ]

AU60

DDR1_DQ[3 1]/DDR0_DQ[63 ]

AU40

DDR1_DQ[3 2]/DDR1_DQ[16 ]

AT40

DDR1_DQ[3 3]/DDR1_DQ[17 ]

AT37

DDR1_DQ[3 4]/DDR1_DQ[18 ]

AU37

DDR1_DQ[3 5]/DDR1_DQ[19 ]

AR40

DDR1_DQ[3 6]/DDR1_DQ[20 ]

AP40

DDR1_DQ[3 7]/DDR1_DQ[21 ]

AP37

DDR1_DQ[3 8]/DDR1_DQ[22 ]

AR37

DDR1_DQ[3 9]/DDR1_DQ[23 ]

AT33

DDR1_DQ[4 0]/DDR1_DQ[24 ]

AU33

DDR1_DQ[4 1]/DDR1_DQ[25 ]

AU30

DDR1_DQ[4 2]/DDR1_DQ[26 ]

AT30

DDR1_DQ[4 3]/DDR1_DQ[27 ]

AR33

DDR1_DQ[4 4]/DDR1_DQ[28 ]

AP33

DDR1_DQ[4 5]/DDR1_DQ[29 ]

AR30

DDR1_DQ[4 6]/DDR1_DQ[30 ]

AP30

DDR1_DQ[4 7]/DDR1_DQ[31 ]

AU27

DDR1_DQ[4 8]

AT27

DDR1_DQ[4 9]

AT25

DDR1_DQ[5 0]

AU25

DDR1_DQ[5 1]

AP27

DDR1_DQ[5 2]

AN27

DDR1_DQ[5 3]

AN25

DDR1_DQ[5 4]

AP25

DDR1_DQ[5 5]

AT22

DDR1_DQ[5 6]

AU22

DDR1_DQ[5 7]

AU21

DDR1_DQ[5 8]

AT21

DDR1_DQ[5 9]

AN22

DDR1_DQ[6 0]

AP22

DDR1_DQ[6 1]

AP21

DDR1_DQ[6 2]

AN21

DDR1_DQ[6 3]

940432

01V0100 00015

IL Channel B[0..63]

SKL_ULT

NIL Channel A[16..31]
NIL Channel A[48..63]

DDR1_MA[5 ]/DDR1_CAA[0] /DDR1_MA[5]
DDR1_MA[9 ]/DDR1_CAA[1] /DDR1_MA[9]
DDR1_MA[6 ]/DDR1_CAA[2] /DDR1_MA[6]
DDR1_MA[8 ]/DDR1_CAA[3] /DDR1_MA[8]
DDR1_MA[7 ]/DDR1_CAA[4] /DDR1_MA[7]

DDR1_BA[2 ]/DDR1_CAA[5 ]/DDR1_BG[0]
DDR1_MA[1 2]/DDR1_CAA[6 ]/DDR1_MA[12 ]
DDR1_MA[1 1]/DDR1_CAA[7 ]/DDR1_MA[11 ]

DDR1_MA[1 5]/DDR1_CAA[8 ]/DDR1_ACT#
DDR1_MA[1 4]/DDR1_CAA[9 ]/DDR1_BG[1]

DDR1_MA[1 3]/DDR1_CAB[0 ]/DDR1_MA[13 ]

DDR1_CAS# /DDR1_CAB[1] /DDR1_MA[15]

DDR1_WE #/DDR1_CAB[ 2]/DDR1_MA[14 ]

DDR1_RAS# /DDR1_CAB[3] /DDR1_MA[16]

DDR1_BA[0 ]/DDR1_CAB[4 ]/DDR1_BA[0]

DDR1_MA[2 ]/DDR1_CAB[5] /DDR1_MA[2]

DDR1_BA[1 ]/DDR1_CAB[6 ]/DDR1_BA[1]
DDR1_MA[1 0]/DDR1_CAB[7 ]/DDR1_MA[10 ]

DDR1_MA[1 ]/DDR1_CAB[8] /DDR1_MA[1]
DDR1_MA[0 ]/DDR1_CAB[9] /DDR1_MA[0]

NIL Channel B[16..31]
NIL Channel B[48..63]

IL Channel B DQS[0..7]

NIL Channel A
DQS[2,3,6,7]

NIL Channel B
DQS[2,3,6,7]

DDR CH - B

DDR1_DQSN [0]/DDR0_DQSN [2]

DDR1_DQSP [0]/DDR0_DQS P[2]

DDR1_DQSN [1]/DDR0_DQSN [3]

DDR1_DQSP [1]/DDR0_DQS P[3]

DDR1_DQSN [2]/DDR0_DQSN [6]

DDR1_DQSP [2]/DDR0_DQS P[6]

DDR1_DQSN [3]/DDR0_DQSN [7]

DDR1_DQSP [3]/DDR0_DQS P[7]

DDR1_DQSN [4]/DDR1_DQSN [2]

DDR1_DQSP [4]/DDR1_DQS P[2]

DDR1_DQSN [5]/DDR1_DQSN [3]

DDR1_DQSP [5]/DDR1_DQS P[3]

DDR1_CKN[0 ]
DDR1_CKN[1 ]
DDR1_CKP[ 0]
DDR1_CKP[ 1]

DDR1_CKE[ 0]
DDR1_CKE[ 1]
DDR1_CKE[ 2]
DDR1_CKE[ 3]

DDR1_CS#[ 0]
DDR1_CS#[ 1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3 ]
DDR1_MA[4 ]

DDR1_DQSN [6]
DDR1_DQSP [6]
DDR1_DQSN [7]
DDR1_DQSP [7]

DDR1_ALE RT#

DDR1_PAR
DRAM_RESE T#
DDR_RCOMP[0 ]
DDR_RCOMP[1 ]
DDR_RCOMP[2 ]

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13

CPUDRAMRST#

AR18

SM_RCOMP_ 0

AT18

SM_RCOMP_ 1

AU18

SM_RCOMP_ 2

M_A_DQS# 2
M_A_DQS2
M_A_DQS# 3
M_A_DQS3
M_A_DQS# 6
M_A_DQS6
M_A_DQS# 7
M_A_DQS7
M_B_DQS# 2
M_B_DQS2
M_B_DQS# 3
M_B_DQS3
M_B_DQS# 6
M_B_DQS6
M_B_DQS# 7
M_B_DQS7

M_B_DIM0_ CK_DDR0_DN 15,17

M_B_DIM0_ CK_DDR0_DP 15,17

M_B_DIM0_ CKE0 15,17

M_B_DIM0_ CS0_N 15,17

M_B_DIM0_ ODT0 15,17

M_B_A5
M_B_A9
M_B_A6
M_B_A8
M_B_A7

M_B_A12
M_B_A11

M_B_A13

M_B_A2

M_B_A10
M_B_A1
M_B_A0
M_B_A3
M_B_A4

+1.2V

12

DDR0_B_A LERT_N 15, 17

1 2

R0402 200Ohm1%

1 2

R0403 80.6Ohm1%

1 2

R0404 100Ohm1%

DDR0_B_P ARITY 1 5,17

M_B_BG0 15,17

M_B_ACT_N 15,1 7

M_B_A15 _CAS_N 15,17
M_B_A14 _WE_N 15,17
M_B_A16 _RAS_N 15,17
M_B_BA0 15,17

M_B_BA1 15,17

M_B_DQS7
M_B_DQS6
M_B_DQS5
M_B_DQS4
M_B_DQS3
M_B_DQS2
M_B_DQS1
M_B_DQS0
M_B_DQS# 7
M_B_DQS# 6
M_B_DQS# 5
M_B_DQS# 4
M_B_DQS# 3
M_B_DQS# 2
M_B_DQS# 1

M_B_DQS# 0

R0405
470Ohm

R0401

0Ohm

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

M_B_DQS[ 7:0] 17

M_B_DQS# [7:0] 17

12

12

C0402

@

0.1UF/25V

Controls reset to the memory
subsystems, and is used on
DDR3L, DDR4

546765_SKL_MOW
DDR4/3L Reset signal - DRAMRST
It is recommended not to install any capacitor
on DDR Reset signal (DRAMRST).

(not applicable to LPDDR3).

M_B_A[13 :0] 15,17

DDR4_DRAMRS T_R_N 16,17

12

C0401

U0401

1

NC

2

A

3 4

12

R0406
10KOhm@

Symbol U0301 B

A A

BYTE 0
BYTE 1
BYTE 2
BYTE 3

ChannelA DQ[0..63]
DQS/DQS#[0..7]

BYTE 4
BYTE 5
BYTE 6
BYTE 7

Non-interleavedinterleaved(Symbol default)

ChannelA DQ[0..15]
DQS/DQS#[0,1]
ChannelADQ[32..47]
DQS/DQS#[4,5]

ChannelB DQ[0..15]
DQS/DQS#[0,1]
ChannelB DQ[32..47]
DQS/DQS#[4,5]

5

Symbol U0301 C

BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7

ChannelB DQ[0..63]
DQS/DQS#[0..7]

Non-interleavedinterleaved(Symbol default)

ChannelA DQ[16..31]
DQS/DQS#[2,3]
ChannelADQ[48..63]
DQS/DQS#[6,7]

ChannelB DQ[16..31]
DQS/DQS#[2,3]
ChannelB DQ[48..63]
DQS/DQS#[6,7]

4

GND

74AUP1G 07GW

5

VCC

Y

0.1UF/16V

3

12

R0412
220KOhm

12

12

R0407
220KOhm

@

R0411
2MOHM

@

DDR_PG_CTRL 83

DDR_VTT_CNTL to VTT
power ready < 35us (tCPU18)

<Variant Name>

<Variant Name>

<Variant Name>

CPU(2)_DDR4

CPU(2)_DDR4

CPU(2)_DDR4

Title :

Title :

1

Title :

Engineer:

Engineer:

Engineer:

Andy Kao

Andy Kao

Andy Kao

4 97Monday, July 11, 2016

4 97Monday, July 11, 2016

4 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW 3

BG1/HW 3

BG1/HW 3

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

X3

X3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

X3

5

4

3

2

1

D D

+VCORE

+VCCSTG

+VCCST_CPU

+VCORE 80

+VCCSTG 3,7

+VCCST_CPU 3,7,9,25,32

29A

+VCORE +VCORE

C C

SKL 2+2, +V1.8VS_EDRAM / +V_EDRAM_VR / +V_EOPIO_VR

From Intel, SKL-U 2+2 reserve these pins PD to GND Pull H/L at EE side

1 2

R0528 0Ohm@

1 2

R0529 0Ohm@

1 2

R0530 0Ohm@

B B

R0535 0Ohm@

R0531 0Ohm@
R0532 0Ohm@

R0533 0Ohm@
R0534 0Ohm@

1 2

1 2
1 2

1 2
1 2

RSVD NC

AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38

G30

AK32

AB62

G61

AC63
AE63

AE62
AG62

AL63
AJ62

A30
A34
A39
A44

K32

P62
V62

H63

01V01000001 5

U0301L

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18

RSVD_3

RSVD_4

VCCOPC_1
VCCOPC_2
VCCOPC_3

VCC_OPC_1P8_1

VCC_OPC_1P8_2

VCCOPC_SENSE
VSSOPC_SENSE

VCCEOPIO_1
VCCEOPIO_2

VCCEOPIO_SENSE
VSSEOPIO_SENSE

940432

CPU POWER 1 OF 4

VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63

VIDALERT#

A63

VIDSCK

D64

VIDSOUT

G20

+VCCFUSEPRG

+VCORE

12

R0536
100Ohm 1%

12

R0537
100Ohm

R0518 0Ohm
R0519 0Ohm

SP0505

NB_R0402_ 20MIL_SMALL

VCORE_VCCSENSE 8 0
VCORE_VSSSENSE 80

1 2

R0517 220Oh m 1%

12
12

+VCCSTG

1 2

CPU side VR side

+VCCST_CPU

12

R0520
56Ohm

1%

VIDALERT#_R

1%

+VCCST_CPU

VIDSCK_R

12

R0521
100Ohm1%

VIDSOUT_R

+VCCST_CPU

12

+VCCST_CPU

12

R0522

45.3Ohm

1%

R0523
100Ohm

1%

R0524 0Ohm

12

C0505

0.1UF/16V

@

1 2

R0525 51Ohm1%

1 2

R0526 10Ohm1%

12

VR_SVID_ALERT# 8 0

VR_SVID_CLK 80

VR_SVID_DATA 80

A A

CPU(3)_+VCCCORE

CPU(3)_+VCCCORE

CPU(3)_+VCCCORE

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

X3

X3

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

5 97Monday, July 11, 2016

5 97Monday, July 11, 2016

5 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

+VCCGT

+VCCGT 80

31A

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

+VCCGT

1 2

R0601 0Ohm@

1 2

R0608 0Ohm@

1 2

R0604 0Ohm@

1 2

R0605 0Ohm@

1 2

R0606 0Ohm@

1 2

R0607 0Ohm@

1 2

R0602 0Ohm@

1 2

R0603 0Ohm@

From Intel, SKL-U 2+2 reserve these pins PD to GND

VccGTx power rail is unconnected for Processors without GT3/4.

+VCCGT

D D

C C

+VCCGT

R0609
100Ohm 1%

R0610
100Ohm 1%

12

12

VCCGT_VCCSENSE80

VCCGT_VSSSENSE80

AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

A48
A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70

L71
M62
N63
N64
N66
N67
N69

J70

J69

U0301M

CPU POWER 2 OF 4

VCCGT_1
VCCGT_2
VCCGT_3
VCCGT_4
VCCGT_5
VCCGT_6
VCCGT_7
VCCGT_8
VCCGT_9
VCCGT_10
VCCGT_11
VCCGT_12
VCCGT_13
VCCGT_14
VCCGT_15
VCCGT_16
VCCGT_17
VCCGT_18
VCCGT_19
VCCGT_20
VCCGT_21
VCCGT_22
VCCGT_23
VCCGT_24
VCCGT_25
VCCGT_26
VCCGT_27
VCCGT_28
VCCGT_29
VCCGT_30
VCCGT_31
VCCGT_32
VCCGT_33
VCCGT_34
VCCGT_35
VCCGT_36
VCCGT_37
VCCGT_38
VCCGT_39
VCCGT_40
VCCGT_41
VCCGT_42
VCCGT_43
VCCGT_44
VCCGT_45
VCCGT_46
VCCGT_47
VCCGT_48
VCCGT_49
VCCGT_50
VCCGT_51
VCCGT_52
VCCGT_53
VCCGT_54
VCCGT_55

VCCGT_SENSE
VSSGT_SENSE

940432

01V010000015

VCCGT_56
VCCGT_57
VCCGT_58
VCCGT_59
VCCGT_60
VCCGT_61
VCCGT_62
VCCGT_63
VCCGT_64
VCCGT_65
VCCGT_66
VCCGT_67
VCCGT_68
VCCGT_69
VCCGT_70
VCCGT_71
VCCGT_72
VCCGT_73
VCCGT_74
VCCGT_75
VCCGT_76
VCCGT_77
VCCGT_78
VCCGT_79
VCCGT_80

VccGTx_1
VccGTx_2
VccGTx_3
VccGTx_4
VccGTx_5
VccGTx_6
VccGTx_7
VccGTx_8

VccGTx_9
VccGTx_10
VccGTx_11
VccGTx_12
VccGTx_13
VccGTx_14
VccGTx_15
VccGTx_16
VccGTx_17
VccGTx_18
VccGTx_19
VccGTx_20
VccGTx_21
VccGTx_22
VccGTx_23
VccGTx_24
VccGTx_25
VccGTx_26
VccGTx_27
VccGTx_28
VccGTx_29

VCCGTx_SENSE

VSSGTx_SENSE

B B

A A

CPU(4)_+VCCGT

CPU(4)_+VCCGT

CPU(4)_+VCCGT

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

X3

X3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

6 97Monday, July 11, 2016

6 97Monday, July 11, 2016

6 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

of

5

D D

4

3

+1.2V

+VCCST_CPU

+VCCSTG

+VCCIO

+VCCSA

+5VSUS

+12VSUS

+1.0VSUS

+1.0V

2

+1.2V 4,15,16,17,19,57 ,83

+VCCST_CPU 3,5,9,25,32

+VCCSTG 3,5

+VCCIO 3 ,9,57,91

+VCCSA 80

+5VSUS 41,42,52,5 6,64,81

+12VSUS 28,81,91

+1.0VSUS 26 ,82

+1.0V 57,91

1

+1.2V

12

C0702
10UF/6.3V

12

C0703
10UF/6.3V

12

C0701
10UF/6.3V

C C

B B

12

12

+1.2V

C0705

C0704

10UF/6.3V

10UF/6.3V

1 2

R0701 NB_R0402_2 0MIL_SMALL

C0701 - C0704 : Near by package
C0705 - C0710 : Underneath the package

12

12

+VCCST_CPU

+VCCSTG

+VCCSFR_OC

+VCCSFR

C0706
10UF/6.3V

12

C0712
1UF/6.3V

12

C0713
1UF/6.3V

12

C0714

0.1UF/16V

12

C0715

0.1UF/16V

C0707
1UF/6.3V

+VDDQ_CPU_C LK

12

C0711

0.1UF/16V

12

C0716

0.1UF/16V

12

C0708
1UF/6.3V

12

C0709
1UF/6.3V

12

C0710

1UF/6.3V

60mA

20mA

100mA

130mA

U0301N

CPU POWER 3 OF 4

AU23

VDDQ_1

AU28

VDDQ_2

AU35

VDDQ_3

AU42

VDDQ_4

BB23

VDDQ_5

BB32

VDDQ_6

BB41

VDDQ_7

BB47

VDDQ_8

BB51

VDDQ_9

AM40

VDDQC

A18

VCCST

A22

VCCSTG

AL23

VCCPLL_OC

K20

VccPLL_1

K21

VccPLL_2

940432

01V01000001 5

+1.0V

R0710

nb_r0603_sh ort_32mil_small

1 2

+1.0V +VCCSFR

R0711

nb_r0603_sh ort_32mil_small

1 2

+VCCIO

R0713

nb_r0603_sh ort_32mil_small

1 2

VCCIO_1
VCCIO_2
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7

VCCSA_1
VCCSA_2
VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6
VCCSA_7
VCCSA_8

VCCSA_9
VCCSA_10
VCCSA_11
VCCSA_12
VCCSA_13
VCCSA_14

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

+VCCST_CPU

+VCCSTG

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

3.1A2.8A

+VCCSA

4.5A

VCCIO_VR_FB
VSSIO_VR_FB

1 2

R0702

100Ohm1%

1 2

R0703

1%

100Ohm

141127 65u sec full load ready

141030 Merge Power PDDG0.91 Table5-1

141127 65u sec full load ready

12

C0718
1UF/6.3V

12

+VCCIO

C0719
1UF/6.3V

12

12

12

C0717
1UF/6.3V

VCCSA_VSSSENSE 8 0

VCCSA_VCCSENSE 80

+VCCSA

1 2

R0709 NB_R0402_2 0MIL_SMALL

R1.1_10L

R0714
100Ohm

1%
@

R0715
100Ohm

1%
@

+VCCSFR_OC+1.2V

+VCCIO

12

C0720
1UF/6.3V

Reserved PH/PD

A A

CPU(5)_+VDDQ/IO/SA

CPU(5)_+VDDQ/IO/SA

CPU(5)_+VDDQ/IO/SA

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

X3

X3

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

7 97Monday, July 11, 2016

7 97Monday, July 11, 2016

7 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

reference 543977_543977_SKL_PDDG_Rev0_91

5

4

3

2

1

F8
G10
G22
G43
G45
G48

G5
G52
G55
G58

G6
G60
G63
G66
H15
H18
H71

J11

J13

J25

J28

J32

J35

J38

J42

J8
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71

L11
L16
L17

U0301R

GND 3 OF 3

VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318

940432

01V010000015

VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

U0301P

GND 1 OF 3

A5

VSS_1

A67

VSS_2

A70

VSS_3

AA2

VSS_4

AA4

VSS_5

AA65

VSS_6

AA68

VSS_7

AB15

VSS_8

AB16

VSS_9

AG16
AG17
AG18
AG19
AG20
AG21
AG71

AB18
AB21

AD13
AD16
AD19
AD20
AD21
AD62

AE64
AE65
AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63

AH13

AH63
AH64
AH67
AJ15
AJ18
AJ20

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AL28
AL32
AL35
AL38

AL45
AL48
AL52
AL55
AL58
AL64

AB8

AD8

AF1

AF2
AF4

AH6

AJ4

AK8
AL2

AL4

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70

940432

01V010000015

D D

C C

VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70

AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW60
AW62
AW64
AW66

AY66

BA10

BA14

BA18

BA23

BA28

BA32

BA36

BA45

AV1

AW6

AW8

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1

BA2

F68

U0301Q

GND 2 OF 3

VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208

940432

01V010000015

VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

B B

A A

CPU(6)_CPU GND

CPU(6)_CPU GND

CPU(6)_CPU GND

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

X3

X3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

8 97Monday, July 11, 2016

8 97Monday, July 11, 2016

8 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

5

CFG0

T0901

1

CFG2
CFG3
CFG4

CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

CFG18
CFG19

CFG_RCOMP

ITP_PMODE

1

T0923

1

T0924

1

T0925

1

T0926

1

D D

T0927
T0928
T0929
T0930
T0931

T0919
T0920

T0921
T0922

1
1
1
1

1
1

1
1

1 2

R0901 49.9Ohm1%

Reserve TP for XDP

Remove SNN

AL25
AL27

BA70

C C

Intel confirm NC

T0917
T0918

1
1

RSVD_VSS_F65
RSVD_VSS_G65

BA68

Remove SNN

+VCCIO

12

R0905
0Ohm

@

R0906

+VCCIO_OUT_CFG_PU

1 2

@
1%

10KOhm

E68

B67
D65
D67

E70
C68
D68
C67

F71
G69

F70
G68
H70
G71
H69
G70

E63

F63

E66

F66

E60

E8

AY2
AY1

D1
D3

K46

K45

C71

B70

F60

A52

J71

J68

F65
G65

F61

E61

U0301S

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_5
RSVD_6

RSVD_7
RSVD_8

RSVD_9
RSVD_10

RSVD_11
RSVD_12

RSVD_13
RSVD_14

RSVD_15

RSVD_16

RSVD_TP_1
RSVD_TP_2

RSVD_17
RSVD_18

VSS_360
VSS_361

RSVD_19
RSVD_20

940432

01V010000015

4

RESERVED SIGNALS-1

CFG0

1 2

R0922 1KOhm@

RSVD_TP_3
RSVD_TP_4

RSVD_TP_5
RSVD_TP_6

RSVD_21
RSVD_22

RSVD_23
RSVD_24
RSVD_25
RSVD_26

RSVD_27
RSVD_28

RSVD_29

RSVD_30
RSVD_31

RSVD_32
RSVD_33

RSVD_34
RSVD_35

RSVD_36
RSVD_37

RSVD_38

RSVD_39
RSVD_40

RSVD_41
RSVD_42

VSS_362

ZVM#

RSVD_TP_7
RSVD_TP_8

MSM#

PROC_SELECT#

3

BB68
BB69

Remove SNN

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

TP4

A69
B69

AY3

D71
C70

C54
D54

AY4

TP1

BB3

TP2

AY71
AR56

AW71
AW70

AP56
C64

RSVD_AY3

Remove SNN

VSS_AY71

Remove SNN

SKL_CNL#

1 2

R0902 0Ohm

1 2

R0903 0Ohm

From Intel, SKL-U 2+2 remove these pins.

1 2

R0904 100KOhm@

MOW WW48

1. Ball C64 which is PROC_SELECT# needs to be pulled to VCCST for
Cannonlake support via 100K ohm resistor and with no resistor populated
(floating pin) for Skylake.

2

C0902

0.1UF/25V

+VCCIO 3,7,57,91

+VCCST_CPU 3,5,7,25,32

+1.8VSUS 21,22,26,84

AW69
AW68

AU56

AW48

C7
U12
U11
H11

+VCCIO

+VCCST_CPU

+1.8VSUS

+1.8VSUS

PDG 1.2
Placeholder only. Does not need to be stuffed.
Placement are required for future platform compatibility purpose only.

+VCCST_CPU

1 2

R0930 0Ohm@

1 2

R0931 0Ohm@

VCC_1P8_U12
VCC_1P8_U11

12

C0901

@

0.1UF/25V

12

@

U0301T

RSVD_43
RSVD_44
RSVD_45
RSVD_46
RSVD_47
RSVD_48
RSVD_49
RSVD_50

940432

01V010000015

SPARE

1

F6

RSVD_51

E3

RSVD_52

C11

RSVD_53

B11

RSVD_54

A11

RSVD_55

D12

RSVD_56

C12

RSVD_57

F52

RSVD_58

B B

A A

5

1 2

R0908 10KOhm

@
1%

1 2

R0910 10KOhm

@
1%

1 2

R0913 10KOhm

@
1%

CFG2

CFG4

CFG7

4

1 2

R0924 1KOhm@

1 2

R0926 1KOhm

1 2

R0929 1KOhm@

CPU(7)_CFG/RSVD

CPU(7)_CFG/RSVD

CPU(7)_CFG/RSVD

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

X3

X3

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

9 97Monday, July 11, 2016

9 97Monday, July 11, 2016

9 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

C C

4

3

2

1

B B

A A

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

A

A

A

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

X3

X3

X3

2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

<Title>

<Title>

<Title>

Andy Kao

Andy Kao

Andy Kao

10 97Monday, July 11, 2016

10 97Monday, July 11, 2016

10 97Monday, July 11, 2016

1

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

C C

4

3

2

1

B B

A A

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

A

A

A

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

X3

X3

X3

2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

<Title>

<Title>

<Title>

Andy Kao

Andy Kao

Andy Kao

11 97Monday, July 11, 2016

11 97Monday, July 11, 2016

11 97Monday, July 11, 2016

1

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

C C

4

3

2

1

B B

A A

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

A

A

A

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

X3

X3

X3

2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

<Title>

<Title>

<Title>

Andy Kao

Andy Kao

Andy Kao

12 97Monday, July 11, 2016

12 97Monday, July 11, 2016

12 97Monday, July 11, 2016

1

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

C C

4

3

2

1

B B

A A

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

A

A

A

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

X3

X3

X3

2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

<Title>

<Title>

<Title>

Andy Kao

Andy Kao

Andy Kao

13 97Monday, July 11, 2016

13 97Monday, July 11, 2016

13 97Monday, July 11, 2016

1

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

C C

4

3

2

1

B B

A A

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

A

A

A

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

X3

X3

X3

2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

<Title>

<Title>

<Title>

Andy Kao

Andy Kao

Andy Kao

14 97Monday, July 11, 2016

14 97Monday, July 11, 2016

14 97Monday, July 11, 2016

1

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

15

D D

+0.6VS

1 2

1 2

1 2

1 2

1 2

1 2

1 2

C C

B B

A A

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

+0.6VS

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

5

R150134.8Ohm 1%

R150234.8Ohm 1%

R150334.8Ohm 1%

R150434.8Ohm 1%

R150534.8Ohm 1%

R150634.8Ohm 1%

R150734.8Ohm 1%

R150834.8Ohm 1%

R150934.8Ohm 1%

R151034.8Ohm 1%

R151134.8Ohm 1%

R151234.8Ohm 1%

R151334.8Ohm 1%

R151434.8Ohm 1%

R151534.8Ohm 1%

R151634.8Ohm 1%

R152934.8Ohm 1%

R155534.8Ohm 1%

R156034.8Ohm 1%

R156334.8Ohm 1%

R154034.8Ohm 1%

R154334.8Ohm 1%

R154434.8Ohm 1%

R154534.8Ohm 1%

R154734.8Ohm 1%

R155234.8Ohm 1%

R155834.8Ohm 1%

R155934.8Ohm 1%

R156234.8Ohm 1%

R156534.8Ohm 1%

R155134.8Ohm 1%

R155634.8Ohm 1%

R155034.8Ohm 1%

R156434.8Ohm 1%

M0_MA0

M0_MA1

M0_MA2

M0_MA3

M0_MA4

M0_MA5

M0_MA6

M0_MA7

M0_MA8

M0_MA9

M_A_A10

M0_MA11

M0_MA12

M0_MA13

M_A_A14_WE_N

M_A_A15_CAS_N

M_A_A16_RAS_N

M_B_A0

M_B_A1

M_B_A2

M_B_A3

M_B_A4

M_B_A5

M_B_A6

M_B_A7

M_B_A8

M_B_A9

M_B_A10

M_B_A11

M_B_A12

M_B_A13

M_B_A14_WE_N

M_B_A15_CAS_N

M_B_A16_RAS_N

M_A_A0 4,16

M_A_A1 4,16

M_A_A2 4,16

M_A_A3 4,16

M_A_A4 4,16

M_A_A5 4,16

M_A_A6 4,16

M_A_A7 4,16

M_A_A8 4,16

M_A_A9 4,16

M_A_A10 4,16

M_A_A11 4,16

M_A_A12 4,16

M_A_A13 4,16

M_A_A14_WE_N 4, 16

M_A_A15_CAS_N 4,16

M_A_A16_RAS_N 4,16

M_B_A0 4,17

M_B_A1 4,17

M_B_A2 4,17

M_B_A3 4,17

M_B_A4 4,17

M_B_A5 4,17

M_B_A6 4,17

M_B_A7 4,17

M_B_A8 4,17

M_B_A9 4,17

M_B_A10 4,17

M_B_A11 4,17

M_B_A12 4,17

M_B_A13 4,17

M_B_A14_WE_N 4, 17

M_B_A15_CAS_N 4,17

M_B_A16_RAS_N 4,17

4

DDR4(0)_Termination

M_A_DIM0_CS0_N4,16

M_A_DIM0_CKE04,16

M_A_BG04,16

M_A_BA04,16

M_A_BA14,16

M_A_DIM0_ODT04,16

M_A_ACT_N4,16

DDR0_A_PARITY4,16

M_A_DIM0_CK_DDR0_DN4,16

M_A_DIM0_CK_DDR0_DP4,16

DDR0_A_ALERT_N4,16

M_B_DIM0_CS0_N4,17

M_B_DIM0_CKE04,17

M_B_BG04,17

M_B_BA04,17

M_B_BA14,17

M_B_DIM0_ODT04,17

M_B_ACT_N4,17

DDR0_B_PARITY4,17

M_B_DIM0_CK_DDR0_DN4,17

M_B_DIM0_CK_DDR0_DP4,17

DDR0_B_ALERT_N4,17

R1521 34.8Ohm1%

R1522 34.8Ohm1%

R1523 34.8Ohm1%

R1524 34.8Ohm1%

R1525 34.8Ohm1%

R1530 34.8Ohm1%

R1532 34.8Ohm1%

R1534 34.8Ohm1%

R1536 36Ohm5%

R1537 36Ohm5%

R1535 49.9Ohm1%

R1554 34.8Ohm1%

R1542 34.8Ohm1%

R1546 34.8Ohm1%

R1549 34.8Ohm1%

R1553 34.8Ohm1%

R1561 34.8Ohm1%

R1557 34.8Ohm1%

R1548 34.8Ohm1%

R1538 36Ohm5%

R1541 36Ohm5%

R1539 49.9Ohm1%

3

vx_r0402_small

1 2

1 2

vx_r0402_small

vx_r0402_small

vx_r0402_small

vx_r0402_small

vx_r0402_small

vx_r0402_small

vx_r0402_small

vx_r0402_small
1 2

vx_r0402_small
1 2

vx_r0402_small
1 2

vx_r0402_small

1 2

1 2

vx_r0402_small

vx_r0402_small

vx_r0402_small

vx_r0402_small

vx_r0402_small

vx_r0402_small

vx_r0402_small

vx_r0402_small
1 2

vx_r0402_small
1 2

vx_r0402_small
1 2

+0.6VS

+1.2V_DDR4

+0.6VS

+0.6VS

12

12

12

12

12

12

+0.6VS

+1.2V_DDR4

+0.6VS

+0.6VS

12

12

12

12

12

12

+0.6VS

+1.2V_DDR4

Average placed close to +VDDQ_VTT power plane

+0.6VS

12

C1501
1UF/6.3V

X5R/10%

vx_c0402_small

+0.6VS

12

C1513
1UF/6.3V

X5R/10%

vx_c0402_small

+0.6VS

12

C1509
10UF/6.3V

X5R/20%

vx_c0603_small

+0.6VS

12

C1541
1UF/6.3V

X5R/10%

vx_c0402_small

+0.6VS

12

C1524
1UF/6.3V

X5R/10%

vx_c0402_small

+0.6VS

12

C1522
10UF/6.3V

X5R/20%

vx_c0603_small

12

vx_c0402_small

12

vx_c0402_small

12

vx_c0603_small

12

vx_c0402_small

12

vx_c0402_small

12

vx_c0603_small

C1502
1UF/6.3V

X5R/10%

C1514
1UF/6.3V

X5R/10%

C1510
10UF/6.3V

X5R/20%

C1540
1UF/6.3V

X5R/10%

C1525
1UF/6.3V

X5R/10%

C1534
10UF/6.3V

X5R/20%

2

12

C1521
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1515
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1511
10UF/6.3V

X5R/20%

vx_c0603_small

12

C1539
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1526
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1523
10UF/6.3V

X5R/20%

vx_c0603_small

12

C1504
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1516
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1512
10UF/6.3V

X5R/20%

vx_c0603_small

12

C1538
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1528
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1536
10UF/6.3V

X5R/20%

vx_c0603_small

12

12

C1505
1UF/6.3V

X5R/10%

vx_c0402_small

vx_c0402_small

12

12

C1517
1UF/6.3V

X5R/10%

vx_c0402_small

vx_c0402_small

12

12

C1537
1UF/6.3V

X5R/10%

vx_c0402_small

vx_c0402_small

12

12

C1535
1UF/6.3V

X5R/10%

vx_c0402_small

vx_c0402_small

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

+0.6VS 57,83

+1.2V_DDR4 4,7,16,17,19,57,83

12

C1506

C1507

1UF/6.3V

1UF/6.3V

X5R/10%

X5R/10%

vx_c0402_small

12

C1518

C1519

1UF/6.3V

1UF/6.3V

X5R/10%

X5R/10%

vx_c0402_small

12

C1531

C1533

1UF/6.3V

1UF/6.3V

X5R/10%

X5R/10%

vx_c0402_small

12

C1532

C1530

1UF/6.3V

1UF/6.3V

X5R/10%

X5R/10%

vx_c0402_small

X3

X3

X3

12

C1508
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1520
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1529
1UF/6.3V

X5R/10%

vx_c0402_small

12

C1527
1UF/6.3V

X5R/10%

vx_c0402_small

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

DDR4(0)_Termination

DDR4(0)_Termination

DDR4(0)_Termination

Andy Kao

Andy Kao

Andy Kao

15 97Monday, July 11, 2016

15 97Monday, July 11, 2016

15 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

16

M_A_D[0:6 3] 4

5

DDR4(1)_CH0

4

3

4.4A

+1.2V_DD R4+1.2V

2

1

+1.2V_DD R4

+V_DDR_ VREFC A_CHA_D IMM

+2P5VPP

+1.2V_DD R4 4,7,1 5,17,19,5 7,83

+V_DDR_ VREFC A_CHA_D IMM 19

+2P5VPP 17,57 ,82

U1601

DDR4

256M x 16 (4Gbit)

P3

12

12

Byte_0

Byte_1

12

C1614
1UF/6.3V

C1629
1UF/6.3V

C1605

0.1UF/25V

@

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14 _WE_N
M_A_A15 _CAS_N
M_A_A16 _RAS_N
M_A_ACT _N

M_A_BA0
M_A_BA1

M_A_BG0

DDR0_A _PARIT Y

M_A_DIM0 _CS0_N

M_A_DIM0 _ODT0

M_A_DIM0 _CKE0

M_A_DIM0 _CK_DD R0_DP
M_A_DIM0 _CK_DD R0_DN

DDR0_A _ALERT _N

M_A_D4
M_A_D7
M_A_D5
M_A_D2
M_A_D0
M_A_D6
M_A_D1
M_A_D3

M_A_DQS 0
M_A_DQS #0

M_A_D11
M_A_D8
M_A_D10
M_A_D13
M_A_D14
M_A_D9
M_A_D15
M_A_D12

M_A_DQS 1
M_A_DQS #1

DDR4_D RAMRST_ R_N

12

C1615
1UF/6.3V

12

C1630
1UF/6.3V

12

C1616
1UF/6.3V

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_n

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

L3

ACT_n

N2

BA0

N8

BA1

M2

BG0

T3

PAR

L7

CS_n

K3

ODT

K2

CKE

K7

CK_t

K8

CK_c

P9

ALERT_n

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

E7

DML_N/DBIL_N

G3

DQSL_t

F3

DQSL_c

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

E2

DMU_N/DBIU_N

B7

DQSU_t

A7

DQSU_c

P1

RESET_n

K4A8G1 65WB-B CPB

12

C1624
1UF/6.3V

M_A_A04,15

D D

R1.0_10L ---Route 2
adjacent bytes to same

+1.2V_DD R4

12

+1.2V_DD R4

12

C1611
1UF/6.3V

+2P5VPP

12

C1607
10UF/6.3V

C1626
10UF/6.3V

DRAM device

DDR4_D RAMRST_ R_N4,1 7

12

12

12

C C

B B

M_A_A14,15
M_A_A24,15
M_A_A34,15
M_A_A44,15
M_A_A54,15
M_A_A64,15
M_A_A74,15
M_A_A84,15

M_A_A94,15
M_A_A104,15
M_A_A114,15
M_A_A124,15
M_A_A134,15

M_A_A14 _WE_N4,1 5
M_A_A15 _CAS_N4,15
M_A_A16 _RAS_N4,15

M_A_ACT _N4,15

M_A_BA04,15
M_A_BA14,15

M_A_BG04,15

DDR0_A _PARIT Y4,1 5

M_A_DIM0 _CS0_N4,15

M_A_DIM0 _ODT04,15

M_A_DIM0 _CKE04,15

M_A_DIM0 _CK_DD R0_DP4,15
M_A_DIM0 _CK_DD R0_DN4,15

DDR0_A _ALERT _N4,15

+1.2V_DD R4

M_A_DQS 04
M_A_DQS #04 M_A_DQS 64

+1.2V_DD R4

M_A_DQS 14
M_A_DQS #14

C1608
10UF/6.3V

12

C1612

C1613

1UF/6.3V

1UF/6.3V

12

C1628

C1627

1UF/6.3V

1UF/6.3V

VDD_10

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VDDQ_10

VREFCA

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VSSQ_10

12

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VPP_1
VPP_2

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

TEN

C1625
1UF/6.3V

+1.2V_DD R4

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9

+2P5VPP +2P5VPP

J2
J8

B1
R9

M1

F9

ZQ

N9

T7

NC

B2
E1
E9
G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

DDR4_Z Q_01

+V_DDR_ VREFC A_CHA_D IMM

12

R1686
240Ohm

+1.2V_DD R4

12

+1.2V_DD R4

12

C1634
1UF/6.3V

+2P5VPP

12

12

C1631
10UF/6.3V

C1642
10UF/6.3V

C1647

0.047UF/1 6V

M_A_DIM0 _CK_DD R0_DP
M_A_DIM0 _CK_DD R0_DN

+1.2V_DD R4

M_A_DQS 24
M_A_DQS #24

Byte_3

+1.2V_DD R4

M_A_DQS 34
M_A_DQS #34

DDR4_D RAMRST_ R_N

12

C1604

0.1UF/25V

@

12

12

C1633

C1632

10UF/6.3V

10UF/6.3V

12

12

C1635
1UF/6.3V

12

C1649
10UF/6.3V

12

C1636

C1637

1UF/6.3V

1UF/6.3V

12

12

C1644

C1643

1UF/6.3V

1UF/6.3V

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14 _WE_N
M_A_A15 _CAS_N
M_A_A16 _RAS_N
M_A_ACT _N

M_A_BA0
M_A_BA1

M_A_BG0

DDR0_A _PARIT Y

M_A_DIM0 _CS0_N

M_A_DIM0 _ODT0

M_A_DIM0 _CKE0

DDR0_A _ALERT _N

M_A_D16
M_A_D22
M_A_D20
M_A_D18
M_A_D21
M_A_D23
M_A_D17
M_A_D19

M_A_DQS 2
M_A_DQS #2

M_A_D28
M_A_D26
M_A_D25
M_A_D30
M_A_D24
M_A_D29
M_A_D31
M_A_D27

M_A_DQS 3
M_A_DQS #3

12

12

C1645
1UF/6.3V

C1638
1UF/6.3V

U1602

256M x 16 (4Gbit)

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_n

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

L3

ACT_n

N2

BA0

N8

BA1

M2

BG0

T3

PAR

L7

CS_n

K3

ODT

K2

CKE

K7

CK_t

K8

CK_c

P9

ALERT_n

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

E7

DML_N/DBIL_N

G3

DQSL_t

F3

DQSL_c

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

E2

DMU_N/DBIU_N

B7

DQSU_t

A7

DQSU_c

P1

RESET_n

K4A8G1 65WB-B CPB

12

12

C1646
1UF/6.3V

C1639
1UF/6.3V

DDR4

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDD_10

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VDDQ_10

VREFCA

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VSSQ_10

12

VPP_1
VPP_2

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

C1640
1UF/6.3V

+1.2V_DD R4

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B1
R9

M1

F9

DDR4_Z Q_23

ZQ

N9

TEN

12

R1687
240Ohm

+V_DDR_ VREFC A_CHA_D IMM

12

C1648

0.047UF/1 6V

M_A_DIM0 _CK_DD R0_DP
M_A_DIM0 _CK_DD R0_DN

Byte_4Byte_2 Byte_6

T7

NC

B2
E1
E9
G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

12

C1641
1UF/6.3V

+1.2V_DD R4

M_A_DQS 44
M_A_DQS #44

Byte_5

+1.2V_DD R4

M_A_DQS 54
M_A_DQS #54 M_A_DQS 74

DDR4_D RAMRST_ R_N

12

C1650

0.1UF/25V

@

+1.2V_DD R4

12

12

C1652

C1653

10UF/6.3V

10UF/6.3V

12

12

C1656
1UF/6.3V

+2P5VPP +2P5VPP

12

C1674
10UF/6.3V

12

C1657

C1658

1UF/6.3V

1UF/6.3V

12

12

C1675

C1676

1UF/6.3V

1UF/6.3V

U1603

DDR4

256M x 16 (4Gbit)

P3

M_A_A0

A0

P7

M_A_A1

A1

R3

M_A_A2

A2

N7

M_A_A3

A3

N3

M_A_A4

A4

P8

M_A_A5

A5

P2

M_A_A6

A6

R8

M_A_A7

A7

R2

M_A_A8

A8

R7

M_A_A9

A9

M3

M_A_A10

A10/AP

T2

M_A_A11

A11

M7

M_A_A12

A12/BC_n

T8

M_A_A13

A13

L2

M_A_A14 _WE_N

WE_n/A14

M8

M_A_A15 _CAS_N

CAS_n/A15

L8

M_A_A16 _RAS_N

RAS_n/A16

L3

M_A_ACT _N

ACT_n

N2

M_A_BA0

BA0

N8

M_A_BA1

BA1

M2

M_A_BG0

BG0

T3

DDR0_A _PARIT Y

PAR

L7

M_A_DIM0 _CS0_N

CS_n

K3

M_A_DIM0 _ODT0

ODT

K2

M_A_DIM0 _CKE0

CKE

K7

CK_t

K8

CK_c

P9

DDR0_A _ALERT _N

ALERT_n

G2

M_A_D39

DQL0

F7

M_A_D32

DQL1

H3

M_A_D38

DQL2

H7

M_A_D36

DQL3

H2

M_A_D35

DQL4

H8

M_A_D37

DQL5

J3

M_A_D33

DQL6

J7

M_A_D34

DQL7

E7

DML_N/DBIL_N

G3

M_A_DQS 4

DQSL_t

F3

M_A_DQS #4

DQSL_c

A3

M_A_D43

DQU0

B8

M_A_D44

DQU1

C3

M_A_D46

DQU2

C7

M_A_D45

DQU3

C2

M_A_D47

DQU4

C8

M_A_D40

DQU5

D3

M_A_D42

DQU6

D7

M_A_D41

DQU7

E2

DMU_N/DBIU_N

B7

M_A_DQS 5

DQSU_t

A7

M_A_DQS #5 M_A_DQS 7

DQSU_c

P1

RESET_n

K4A8G1 65WB-B CPB

12

12

12

C1660

C1659

1UF/6.3V

1UF/6.3V

12

12

C1678

C1677

1UF/6.3V

1UF/6.3V

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VDDQ_10

VREFCA

VSSQ_10

C1661
1UF/6.3V

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDD_10

VPP_1
VPP_2

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

+1.2V_DD R4

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9

+2P5VPP

J2
J8

B1
R9

M1

F9

ZQ

N9

TEN

T7

NC

B2
E1
E9
G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

12

C1668
1UF/6.3V

DDR4_Z Q_67

+V_DDR_ VREFC A_CHA_D IMM

12

R1688
240Ohm

12

C1669
1UF/6.3V

12

C1684

0.047UF/1 6V

+1.2V_DD R4

M_A_DQS #64

+1.2V_DD R4

M_A_DQS #74

+1.2V_DD R4

12

+1.2V_DD R4+1.2V_DD R4

12

C1662
1UF/6.3V

12

C1654
10UF/6.3V

Byte_7

C1679
10UF/6.3V

M_A_DIM0 _CK_DD R0_DP
M_A_DIM0 _CK_DD R0_DN

DDR4_D RAMRST_ R_N

12

C1651

0.1UF/25V

@

12

C1655
10UF/6.3V

12

C1663
1UF/6.3V

12

C1680
1UF/6.3V

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14 _WE_N
M_A_A15 _CAS_N
M_A_A16 _RAS_N
M_A_ACT _N

M_A_BA0
M_A_BA1

M_A_BG0

DDR0_A _PARIT Y

M_A_DIM0 _CS0_N

M_A_DIM0 _ODT0

M_A_DIM0 _CKE0

DDR0_A _ALERT _N

M_A_D48
M_A_D50
M_A_D49
M_A_D55
M_A_D52
M_A_D51
M_A_D53
M_A_D54

M_A_DQS 6
M_A_DQS #6

M_A_D56
M_A_D62
M_A_D57
M_A_D63
M_A_D60
M_A_D59
M_A_D61
M_A_D58

M_A_DQS #7

12

12

12

C1664

0.1UF/25V

C1681
1UF/6.3V

C1673
10UF/6.3V

U1604

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_n

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

L3

ACT_n

N2

BA0

N8

BA1

M2

BG0

T3

PAR

L7

CS_n

K3

ODT

K2

CKE

K7

CK_t

K8

CK_c

P9

ALERT_n

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

E7

DML_N/DBIL_N

G3

DQSL_t

F3

DQSL_c

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

E2

DMU_N/DBIU_N

B7

DQSU_t

A7

DQSU_c

P1

RESET_n

K4A8G1 65WB-B CPB

12

C1665

0.1UF/25V

12

C1682
1UF/6.3V

DDR4

256M x 16 (4Gbit)

12

C1666

0.1UF/25V

12

C1683
1UF/6.3V

VDD_10

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VDDQ_10

VREFCA

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VSSQ_10

+1.2V_DD R4

B3

VDD_1

B9

VDD_2

D1

VDD_3

G7

VDD_4

J1

VDD_5

J9

VDD_6

L1

VDD_7

L9

VDD_8

R1

VDD_9

T9

A1
A9
C1
D9
F2
F8
G1
G9

+2P5VPP

J2
J8

B1

VPP_1

R9

VPP_2

M1

F9

DDR4_Z Q_54

ZQ

N9

TEN

T7

NC

B2

VSS_1

E1

VSS_2

E9

VSS_3

G8

VSS_4

K1

VSS_5

K9

VSS_6

M9

VSS_7

N1

VSS_8

T1

VSS_9

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

12

C1667

0.1UF/25V

+V_DDR_ VREFC A_CHA_D IMM

12

C1685

0.047UF/1 6V

R1689
240ohm

1 2

12

12

C1671

C1670

1UF/6.3V

1UF/6.3V

A A

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Title :

Title :

Title :

DDR4(0)_CH0

DDR4(0)_CH0

DDR4(0)_CH0

Engineer:

Andy Kao

Engineer:

Andy Kao

Engineer:

Andy Kao

Rev

Rev

Re

1.0

1.0

X3

X3

X3

1.0

16 97Monday, July 11, 20 16

16 97Monday, July 11, 20 16

16 97Monday, July 11, 20 16

v

5

17

U1701

DDR4

256M x 16 (4Gbit)

P3

M_B_A04,15

D D

R1.0_10L ---Route 2

C C

adjacent bytes to same
DRAM device

DDR4_D RAMRST_ R_N4,1 6

M_B_A14,15

M_B_A24,15

M_B_A34,15

M_B_A44,15

M_B_A54,15

M_B_A64,15

M_B_A74,15

M_B_A84,15

M_B_A94,15
M_B_A104,15
M_B_A114,15
M_B_A124,15
M_B_A134,15

M_B_A14 _WE_N4,1 5
M_B_A15 _CAS_N4,15
M_B_A16 _RAS_N4,15

M_B_ACT _N4,15

M_B_BA04,15
M_B_BA14,15

M_B_BG04,15

DDR0_B _PARIT Y4 ,15

M_B_DIM0 _CS0_N4,15

M_B_DIM0 _ODT04,15

M_B_DIM0 _CKE04,15

M_B_DIM0 _CK_DD R0_DP4,15
M_B_DIM0 _CK_DD R0_DN4,15

DDR0_B _ALERT _N4,15

+1.2V_DD R4

M_B_DQS 04
M_B_DQS #04

+1.2V_DD R4

M_B_DQS 14
M_B_DQS #14

M_B_A0

A0

P7

M_B_A1

A1

R3

M_B_A2

A2

N7

M_B_A3

A3

N3

M_B_A4

A4

P8

M_B_A5

A5

P2

M_B_A6

A6

R8

M_B_A7

A7

R2

M_B_A8

A8

R7

M_B_A9

A9

M3

M_B_A10

A10/AP

T2

M_B_A11

A11

M7

M_B_A12

A12/BC_n

T8

M_B_A13

A13

L2

M_B_A14 _WE_N

WE_n/A14

M8

M_B_A15 _CAS_N

CAS_n/A15

L8

M_B_A16 _RAS_N

RAS_n/A16

L3

M_B_ACT _N

ACT_n

N2

M_B_BA0

BA0

N8

M_B_BA1

BA1

M2

M_B_BG0

BG0

T3

DDR0_B _PARIT Y

PAR

L7

M_B_DIM0 _CS0_N

CS_n

K3

M_B_DIM0 _ODT0

ODT

K2

M_B_DIM0 _CKE0

CKE

K7

M_B_DIM0 _CK_DD R0_DP
M_B_DIM0 _CK_DD R0_DN

Byte_0 Byte_2

Byte_1

DDR4_D RAMRST_ R_N

12

C1705

0.1UF/25V

@

DDR0_B _ALERT _N

M_B_D4
M_B_D6
M_B_D1
M_B_D7
M_B_D5
M_B_D3
M_B_D0
M_B_D2

M_B_DQS 0
M_B_DQS #0

M_B_D13
M_B_D14
M_B_D12
M_B_D10
M_B_D9
M_B_D11
M_B_D8
M_B_D15

M_B_DQS 1
M_B_DQS #1

CK_t

K8

CK_c

P9

ALERT_n

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

E7

DML_N/DBIL_N

G3

DQSL_t

F3

DQSL_c

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

E2

DMU_N/DBIU_N

B7

DQSU_t

A7

DQSU_c

P1

RESET_n

K4A8G1 65WB-B CPB

VDD_10

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VDDQ_10

VREFCA

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VSSQ_10

B3

VDD_1

B9

VDD_2

D1

VDD_3

G7

VDD_4

J1

VDD_5

J9

VDD_6

L1

VDD_7

L9

VDD_8

R1

VDD_9

T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B1

VPP_1

R9

VPP_2

M1

F9

ZQ

N9

TEN

T7

NC

B2

VSS_1

E1

VSS_2

E9

VSS_3

G8

VSS_4

K1

VSS_5

K9

VSS_6

M9

VSS_7

N1

VSS_8

T1

VSS_9

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

DDR4(2)_CH1

+1.2V_DD R4

+2P5VPP +2P5VPP

+V_DDR_ VREFC A_CHB_D IMM

12

C1747

DDR4_Z Q_01_B

0.047UF/1 6V

12

R1786
240Ohm

+1.2V_DD R4

M_B_DQS 24
M_B_DQS #24

+1.2V_DD R4

M_B_DQS 34
M_B_DQS #34

4

Byte_3

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14 _WE_N
M_B_A15 _CAS_N
M_B_A16 _RAS_N
M_B_ACT _N

M_B_BA0
M_B_BA1

M_B_BG0

DDR0_B _PARIT Y

M_B_DIM0 _CS0_N

M_B_DIM0 _ODT0

M_B_DIM0 _CKE0

M_B_DIM0 _CK_DD R0_DP
M_B_DIM0 _CK_DD R0_DN

DDR0_B _ALERT _N

M_B_DQS 2
M_B_DQS #2

M_B_DQS 3
M_B_DQS #3

DDR4_D RAMRST_ R_N

12

C1704

0.1UF/25V

@

M_B_D23
M_B_D21
M_B_D19
M_B_D16
M_B_D22
M_B_D20
M_B_D18
M_B_D17

M_B_D31
M_B_D29
M_B_D30
M_B_D28
M_B_D27
M_B_D24
M_B_D26
M_B_D25

U1702

256M x 16 (4Gbit)

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_n

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

L3

ACT_n

N2

BA0

N8

BA1

M2

BG0

T3

PAR

L7

CS_n

K3

ODT

K2

CKE

K7

CK_t

K8

CK_c

P9

ALERT_n

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

E7

DML_N/DBIL_N

G3

DQSL_t

F3

DQSL_c

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

E2

DMU_N/DBIU_N

B7

DQSU_t

A7

DQSU_c

P1

RESET_n

K4A8G1 65WB-B CPB

DDR4

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDD_10

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VDDQ_10

VREFCA

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VSSQ_10

3

U1703

+1.2V_DD R4

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B1

VPP_1

R9

VPP_2

M1

F9

DDR4_Z Q_23_B

ZQ

N9

TEN

T7

NC

B2

VSS_1

E1

VSS_2

E9

VSS_3

G8

VSS_4

K1

VSS_5

K9

VSS_6

M9

VSS_7

N1

VSS_8

T1

VSS_9

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

12

R1787
240Ohm

+V_DDR_ VREFC A_CHB_D IMM

12

C1748

0.047UF/1 6V

+1.2V_DD R4

M_B_DQS 44
M_B_DQS #44

+1.2V_DD R4

M_B_DQS 54
M_B_DQS #54 M_B_DQS 74

12

C1750

0.1UF/25V

@

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14 _WE_N
M_B_A15 _CAS_N
M_B_A16 _RAS_N
M_B_ACT _N

M_B_BA0
M_B_BA1

M_B_BG0

DDR0_B _PARIT Y

M_B_DIM0 _CS0_N

M_B_DIM0 _ODT0

M_B_DIM0 _CKE0

M_B_DIM0 _CK_DD R0_DP
M_B_DIM0 _CK_DD R0_DN

DDR0_B _ALERT _N

M_B_D38
M_B_D32
M_B_D34
M_B_D37

Byte_4

M_B_D35
M_B_D33
M_B_D39
M_B_D36

M_B_DQS 4
M_B_DQS #4

M_B_D46
M_B_D44
M_B_D47
M_B_D40

Byte_5

M_B_D43
M_B_D45
M_B_D42
M_B_D41

M_B_DQS 5
M_B_DQS #5 M_B_DQS 7

DDR4_D RAMRST_ R_N

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_n

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

L3

ACT_n

N2

BA0

N8

BA1

M2

BG0

T3

PAR

L7

CS_n

K3

ODT

K2

CKE

K7

CK_t

K8

CK_c

P9

ALERT_n

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

E7

DML_N/DBIL_N

G3

DQSL_t

F3

DQSL_c

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

E2

DMU_N/DBIU_N

B7

DQSU_t

A7

DQSU_c

P1

RESET_n

K4A8G1 65WB-B CPB

DDR4

256M x 16 (4Gbit)

VDD_10

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VDDQ_10

VREFCA

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VSSQ_10

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VPP_1
VPP_2

TEN

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

2

+V_DDR_ VREFC A_CHB_D IMM

+1.2V_DD R4

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9

+2P5VPP

J2
J8

B1
R9

M1

F9

ZQ

N9

T7

NC

B2
E1
E9
G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

DDR4_Z Q_67_B

+V_DDR_ VREFC A_CHB_D IMM

12

R1788
240Ohm

12

C1784

0.047UF/1 6V

M_B_DQS 64
M_B_DQS #64

M_B_DQS #74

Byte_6

+1.2V_DD R4

Byte_7

+1.2V_DD R4

M_B_DIM0 _CK_DD R0_DP
M_B_DIM0 _CK_DD R0_DN

DDR4_D RAMRST_ R_N

12

C1751

0.1UF/25V

@

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14 _WE_N
M_B_A15 _CAS_N
M_B_A16 _RAS_N
M_B_ACT _N

M_B_BA0
M_B_BA1

M_B_BG0

DDR0_B _PARIT Y

M_B_DIM0 _CS0_N

M_B_DIM0 _ODT0

M_B_DIM0 _CKE0

DDR0_B _ALERT _N

M_B_D52
M_B_D51
M_B_D49
M_B_D50
M_B_D53
M_B_D55
M_B_D48
M_B_D54

M_B_DQS 6
M_B_DQS #6

M_B_D56
M_B_D59
M_B_D61
M_B_D58
M_B_D60
M_B_D63
M_B_D57
M_B_D62

M_B_DQS #7

U1704

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_n

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

L3

ACT_n

N2

BA0

N8

BA1

M2

BG0

T3

PAR

L7

CS_n

K3

ODT

K2

CKE

K7

CK_t

K8

CK_c

P9

ALERT_n

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

E7

DML_N/DBIL_N

G3

DQSL_t

F3

DQSL_c

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

E2

DMU_N/DBIU_N

B7

DQSU_t

A7

DQSU_c

P1

RESET_n

K4A8G1 65WB-B CPB

+1.2V_DD R4

+2P5VPP

DDR4

256M x 16 (4Gbit)

VDD_10

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VDDQ_10

VREFCA

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VSSQ_10

1

B3

VDD_1

B9

VDD_2

D1

VDD_3

G7

VDD_4

J1

VDD_5

J9

VDD_6

L1

VDD_7

L9

VDD_8

R1

VDD_9

T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B1

VPP_1

R9

VPP_2

M1

F9

ZQ

N9

TEN

T7

NC

B2

VSS_1

E1

VSS_2

E9

VSS_3

G8

VSS_4

K1

VSS_5

K9

VSS_6

M9

VSS_7

N1

VSS_8

T1

VSS_9

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

+1.2V_DD R4 4,7,1 5,16,19,5 7,83M_B_D[0:6 3] 4

+V_DDR_ VREFC A_CHB_D IMM 19

+2P5VPP 16,57,8 2

+1.2V_DD R4

+2P5VPP

+V_DDR_ VREFC A_CHB_D IMM

DDR4_Z Q_54_B

R1789
240ohm

1 2

12

C1785

0.047UF/1 6V

+1.2V_DD R4

B B

A A

12

+1.2V_DD R4

12

C1711
1UF/6.3V

+2P5VPP

12

C1707
10UF/6.3V

C1726
10UF/6.3V

12

C1708
10UF/6.3V

12

12

C1712

C1713

1UF/6.3V

1UF/6.3V

12

12

C1728

C1727

1UF/6.3V

1UF/6.3V

12

12

C1714
1UF/6.3V

12

C1729
1UF/6.3V

5

12

C1715

C1716

1UF/6.3V

1UF/6.3V

12

C1730
1UF/6.3V

12

12

C1725

C1724

1UF/6.3V

1UF/6.3V

+1.2V_DD R4

12

+1.2V_DD R4

12

C1734
1UF/6.3V

+2P5VPP

12

C1731
10UF/6.3V

C1742
10UF/6.3V

12

12

C1733

C1732

10UF/6.3V

10UF/6.3V

12

12

C1736

C1735

1UF/6.3V

1UF/6.3V

12

12

C1743
1UF/6.3V

C1749
10UF/6.3V

4

12

12

C1737
1UF/6.3V

12

C1744
1UF/6.3V

12

C1738

C1739

1UF/6.3V

1UF/6.3V

12

12

C1745

C1746

1UF/6.3V

1UF/6.3V

12

12

C1741

C1740

1UF/6.3V

1UF/6.3V

3

+1.2V_DD R4

12

12

C1752

C1753

10UF/6.3V

10UF/6.3V

12

12

C1756
1UF/6.3V

+2P5VPP +2P5VPP

12

C1774
10UF/6.3V

C1758

C1757

1UF/6.3V

1UF/6.3V

12

12

C1776

C1775

1UF/6.3V

1UF/6.3V

12

12

12

12

C1760

C1759

1UF/6.3V

1UF/6.3V

12

12

C1778

C1777

1UF/6.3V

1UF/6.3V

12

12

C1761
1UF/6.3V

C1768
1UF/6.3V

C1769
1UF/6.3V

2

+1.2V_DD R4

12

C1754
10UF/6.3V

+1.2V_DD R4+1.2V_DD R4

12

C1762
1UF/6.3V

12

C1779
10UF/6.3V

12

12

12

C1755
10UF/6.3V

C1763
1UF/6.3V

C1780
1UF/6.3V

12

C1773
10UF/6.3V

12

12

12

12

C1766

C1765

0.1UF/25V

C1782
1UF/6.3V

C1767

0.1UF/25V

0.1UF/25V

12

C1783
1UF/6.3V

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

12

12

C1771

C1770

1UF/6.3V

1UF/6.3V

DDR4(2)_CH1

DDR4(2)_CH1

DDR4(2)_CH1

Title :

Title :

Title :

Engineer:

Andy Kao

Engineer:

Andy Kao

Engineer:

Andy Kao

Rev

Rev

R

1.0

1.0

X3

X3

X3

1.0

17 97Monday, July 11, 20 16

17 97Monday, July 11, 20 16

17 97Monday, July 11, 20 16

12

C1764

0.1UF/25V

12

C1781
1UF/6.3V

ev

5

D D

C C

4

3

2

1

B B

A A

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

A

A

A

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

X3

X3

X3

2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

<Title>

<Title>

<Title>

Andy Kao

Andy Kao

Andy Kao

18 97Monday, July 11, 2016

18 97Monday, July 11, 2016

18 97Monday, July 11, 2016

1

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

19

D D

DDR4(3)_CA/DQ Voltage

+1.2V

+V_DDR_VREFCA_CHB_DIMM

+V_DDR_VREFCA_CHA_DIMM

+1.2V 4,7,15,16,17,57,83

+V_DDR_VREFCA_CHB_DIMM 17

+V_DDR_VREFCA_CHA_DIMM 16

DDR4 Vref (Intel Schematic Review)

C C

+1.2V

R1912

1.8KOhm

1%

R1910

12

12

R1909

24.9Ohm

1%

1 2

C1903

0.022UF/16V

2Ohm

1%

DDR_VREF_CA4

B B

1 2

12

R1911

1.8KOhm

1%

+V_DDR_VREFCA_CHA_DIMM

DDR_VREF_DQ4

12

12

R1915

24.9Ohm

1%

1 2

C1904

0.022UF/16V

R1916

2Ohm

1%

+1.2V

R1914

1.8KOhm

1%

1 2

12

R1913

1.8KOhm

1%

+V_DDR_VREFCA_CHB_DIMM

A A

5

4

3

2

<Variant Name>

<Variant Name>

<Variant Name>

DDR3(3)_CA/DQ Voltage

DDR3(3)_CA/DQ Voltage

Title :

Title :

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Nam e

Size Project Nam e

Size Project Nam e

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

X3

X3

X3

Title :

Engineer:

Engineer:

Engineer:

DDR3(3)_CA/DQ Voltage

Andy Kao

Andy Kao

Andy Kao

19 97Monday, July 11, 2016

19 97Monday, July 11, 2016

19 97Monday, July 11, 2016

1

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

+3VSUS_ORG

+3VS

U0301E

D D

ME

BIOS+EC_PBA

WLAN/BT

C C

B B

SPI_WP#_IO228
SPI_HOLD#_IO328,44
SPI_CS#028,44
SPI_CS#12 8

INT_SERIRQ3 0,44,62

GND

GND

GND

SPI_CLK28,44
SPI_SO28,44
SPI_SI28,44

CL_CLK53
CL_DATA53
CL_RST#53

RCIN#30

R2004 20KOhm@

R2006 20KOhm@

R2008 20KOhm@

1 2

1 2

1 2

T2001

1

T2013
T2014
T2015
T2016
T2017
T2018

1
1
1
1
1
1

SMBALERT#

SML0ALERT#

SPI_CS2#

GPP_D1
GPP_D2
GPP_D3
GPP_D21
GPP_D22
GPP_D0

AW13

AY11

R2003 2.2KOhm

CRB 0.53 reserve 150k ohm

R2005 4.7KOhm@

CRB 0.53 reserve 150k ohm

R2007 4.7KOhm@

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

01V01000001 5

1 2

1 2

1 2

940432

SPI - FLASH

SPI - TOUCH

C LINK

+3VSUS_ORG

+3VSUS_ORG

+3VSUS_ORG

BBS 21

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

LPC

SMBALERT# - Internal weak pull down 20k ohm
TLS Confidentiality
0 : Disable (default)
1 : Enable

SML0ALERT# - Internal weak pull down 20 kohm
0 : LPC EC (default)
1 : eSPI EC

BBS - Internal weak pull down 20k ohm
Boot BIOS Strap
0 : SPI destination (default)
1 : LPC destination

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

R7
R8
R10

R9
W2
W1

W3
V3
AM7

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

SMB_CLK
SMB_DAT
SMBALERT#

SML0_CLK_N FC
SML0_DAT_NFC
SML0ALERT#

SML1_CLK
SML1_DAT
SML1ALERT#

CLK_KBCPCI_PCH _R

CLK_LPC1

SMB_CLK

SMB_DAT

SML1_DAT

SML1_CLK

SML1ALERT#

1

T2011

1

T2012

1

T2003

1

T2004

SML1_CLK 28

T2010

3 4

1 2

3 4

1 2

1 2

R2012 150KOhm1%

SML1_DAT 28

R2001 22Ohm
R2002 22Ohm/D ebug
R2014 22Ohm/T PM

PM_CLKRUN# 30,62

@

2.2KOhm

@

2.2KOhm

2.2KOhm

2.2KOhm

1

RN2001B

RN2001A

RN2002B

RN2002A

MOW WW52
To enable Direct Connect Interface (DCI),
a 150K pull up resistor will need to be added to PCHHOT#
pin. This pin must be low during the rising edge of RSMRST#.

To EC

1 2
1 2
1 2

+3VSUS_ORG

+3VSUS_ORG 21,22,23,25,2 6

+3VS 3,4,21,22,23,24,30,3 1,32,36,37,44,45,47,50 ,51,53,57,62,64,91,92

LPC_AD0 30,44,62
LPC_AD1 30,44,62
LPC_AD2 30,44,62
LPC_AD3 30,44,62

LPC_FRAME# 30,44,62

PM_SUS_STAT# 62

CLK_KBCPCI_PCH 3 0

CLK_DEBUG 44

C2001

10PF/50V

12

12

@

GNDGND

C2002
10PF/50V

@

LPCCLK_TPM 62

TPM

A A

<Variant Name>

<Variant Name>

<Variant Name>

PCH(1)_SPI/LPC

PCH(1)_SPI/LPC

PCH(1)_SPI/LPC

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

X3

X3

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

20 97Monday, July 11, 2016

20 97Monday, July 11, 2016

20 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

of

5

Microsoft* Windows* 7 System WHCK Requirement – OEM platforms are
required to include a supported OS debug interface, accessible by an enduser.
This allows developers to help in driver debug. The supported
Windows 7 debug interfaces are EHCI, 1394 port and COM port.

With skylake EHCI Removal, Potential Gap with Windows* 7 Kernel Debug
and OS Installation – Mitigation Required

4

3

+3VS

2

+3VS 3,4,22,23,24,30,31,32,36,37,44,45,47,50,51,53,57,62,64,91,92

1

R1.0_10L

D D

+3VSUS_ORG

12

R2153
10KOhm

PBA_ID

GPP_D14

PBA_ID D

12

R2154
10KOhm

@

T2151
T2152

T2148
T2147

1
1

PCB_ID3

2

GND

T2153
T2154

12

12

12

R2159

R2162

10KOhm

10KOhm

@

12

R2160

R2161

10KOhm

10KOhm

@

2016.6.27
R1.4_10L ---Change PCB_ID to R1.4

GND

R1.1_10L R1.1_10L

SKL

KBL

GPP_F7(0)

GPP_F7(1)

I2C0_MUX_SEL 30
TP_SENSOR_OFF# 31

TP_IRQ# 30,31

OP_SD# 36

2016.6.2
R1.2_10L ---GPP_F is used by 1.8V

PCB_ID3
PCB_ID4
PCB_ID5

PCB_ID5

2133

2400

U0301F

LPSS ISH

GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

940432

01V010000015

MEM_ID0
MEM_ID1
MEM_ID2

C 3.3V GPIO

F 1.8V GPIO

+3VSUS_ORG

12

12

GND

GPP_B19(0)

PP_B19(1)

G

GPP_B20(0)

GPP_B20(1)

R2151
10KOhm

R2152
10KOhm

@

+3VSUS_ORG

12

12

GND

C

Disable

Enable

R2149
10KOhm

R2150
10KOhm

@

HA CHB

GPP_D9
GPP_D10
GPP_D11

D 3.3V GPIO

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

Sx_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6

3

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

MEM_CHA
MEM_CHB

Disable

Enable

GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

+1.8VSUS

12

12

GND GNDGND

GPP_F4(0)

PP_F4(1)M3X3

G

R2156
10KOhm

R2157
10KOhm

@

P2
P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

PRJ

GPP_D11
GPP_D12

ISH_I2C0_SDA
ISH_I2C0_SCL

GPP_F10
GPP_F11

PBA_ID
IOBD_ID_PCH

PCB_ID0
PCB_ID1
PCB_ID2

PRJ

1
1

1
1

+1.8VSUS +1.8VSUS +1.8VSUS

12

R2163
10KOhm

@

12

R2158
10KOhm

N/A

GPP_F5(0)

GPP_F5(1)

AH10

AH11
AH12

AF11
AF12

AN8

AP7
AP8

AR7

AM5
AN7

AP5

AN5

AB1
AB2

W4

AB3

AD1
AD2
AD3
AD4

U7
U6

U8
U9

AH9

MEM_ID0
MEM_ID1
MEM_ID2

C C

Boot BIOS Strap Bit (BBS)

BBS20

To implement UART for WIN7 WHCK requirement if need

Please refer to Intel document #548689 - RVP5

2016.6.29
R1.4_10L ---For IOAC

Type C MUX

Click PAD

VDB_PD_EN_PCH#

B B

R1.0_10L ---Follow HAWAII type-c design

+3VSUS_ORG +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG

12

R2104
10KOhm

12

R2105
10KOhm

@

R1.1_10L ---Change PCB_ID to R1.1

A A

GND GND GND

2016.6.2
R1.2_10L ---Change PCB_ID to R1.2

2016.6.14
R1.3_10L ---Change PCB_ID to R1.3

MB Version ID

PCB_ID4 PCB_ID1 PCB_ID0
(GPP_F6) (GPP_C14) (GPP_C13)
R1.0 0 0 0
R1.1 0 0 1
R1.2 0 1 0
R1.3 0 1 1
R1.4 1 0 0
R2.0 1 0 1

PCH_I2C0_SDA30
PCH_I2C0_SCL30

PCH_I2C1_SDA31
PCH_I2C1_SCL31

61

Q2101A
UM6K1N

2

R2155

GND

100KOhm

1 2

GND

+3VSUS_ORG

12

12

R2106

R2117

10KOhm

10KOhm

@

12

12

R2107
10KOhm

R2118
10KOhm

@

R1.0_10L

2016.6.27

GND

R1.4_10L ---Change PCB_ID to R1.4

PCB_ID2
(GPP_C15)
8L 0
10L 1

5

1 2

R2102 0Ohm

WLAN_ON_PCH53
BT_ON/OFF#_PCH53

LCD_BKLTEN_PCH3,45

IOAC_EN53

VDB_PD_EN_PCH 43

34

Q2101B
UM6K1N

5

2016.7.4
R2.0_10L ---Change PCB_ID to R2.0

PCB_ID0

PCB_ID1

PCB_ID2

USB_UART_SEL64

UART_RX64
UART_TX64

MEM_ID1
(GPP_B16)
4Gb 0
8Gb 1

T2144

T2115
T2116

12

R2108
10KOhm

@

12

R2109
10KOhm

N/A

GND

Memory ID

GPP_B18

MEM_CHA
MEM_CHB
VDB_PD_EN_PCH#
BBS_R

1

GPP_C11

WLAN_ON_PCH
BT_ON/OFF#_PCH

PCH_I2C0_SDA
PCH_I2C0_SCL

PCH_I2C1_SDA
PCH_I2C1_SCL

PRJ
PCB_ID3

PCB_ID4
PCB_ID5

1

GPP_F8

1

GPP_F9

12

12

R2115

R2119

10KOhm

10KOhm

N/A

@

12

12

R2116

R2120

10KOhm

10KOhm

@

GND

MEM_ID2 MEM_ID0
(GPP_B17) (GPP_B15)
SAMSUNG 0 0
HYNIX 0 1
MICRON 1 0
RSV 1 1

4

1 0

isableEnable

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

+3VS

+3VS

+3VS

+3VSUS_ORG

Andy Kao

Andy Kao

Andy Kao

PCH(2)_ISH

PCH(2)_ISH

PCH(2)_ISH

21 97Monday, July 11, 2016

21 97Monday, July 11, 2016

21 97Monday, July 11, 2016

ISH_I2C0_SDA
ISH_I2C0_SCL

PCH_I2C0_SDA
PCH_I2C0_SCL
PCH_I2C1_SCL
PCH_I2C1_SDA

GPP_B18

GSPI0_MOSI / GPP_B18 - Internal weak pull down 20k ohm
0 : Disable No Reboot mode(default)
1 : Enable NO Reboot Enable mode

1 2

R2110 10KOhm@

1 2

R2111 10KOhm@

1 2

R2113 2.2KOhm

1 2

R2114 2.2KOhm

1 2

R2146 10KOhm@

1 2

R2145 10KOhm@

1 2

R2112 4.7KOhm@

1 2

R2122 4.7KOhm@

Default is GPO, to reserve pull high to +3VSUS_ORG

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

X3

X3

X3

1

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

+VCCPAZIO

+3VS

D D

U0301G

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

GPP_B14/SPKR

940432

01V01000001 5

R2209 4.7KOhm@

R2210 2.2KOhm@

AUDIO

1 2

1 2

+3VS

+3VSUS_ORG

SDIO/SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_A17/SD_PWR_EN#/ISH_GP7

SPKR - Internal weak pull down
0 : Disable TOP Swap mode (default)
1 : Enable Top Swap Enable

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

GPP_G3

SKL_SD_RCOM P

RTC_IN#

Default is GPO, to reserve pull high to +3VSUS_ORG

12

D2201RB7 51V-40

PCH_FLASH_DES CRIPTOR 30

AU_I2S0_SDO_R - Internal weak pull down
FLASH DESCRIPTOR SECURITY OVERRRIDE
0 : Enable security measure defined in the Flash Descriptor
1 : Disable Flash Descriptor Security

1 2

HDA_SYNC36
HDA_BCLK36
HDA_SDO36
HDA_SDI036

HDA_RST#36

C C

HDA_SPKR36

B B

R2211 33Ohm

1 2

R2212 33Ohm

1 2

R2213 33Ohm

1 2

R2214 33Ohm

1 2

R2217 33Ohm

T2227
T2228

GND

+VCCPAZIO

AU_I2S0_SYNC_R
AU_I2S0_BCLK_R
AU_I2S0_SDO_R
AU_I2S0_SDI0_R

1

HDA_SDI1

T2201

HDA_RST#_R

1

AU_I2S_MCLK_R

T2229

1

DMIC_CLK0_PCH _R

1

DMIC_DATA0_PCH_ R

1

GPP_D17

T2202

1

GPP_D18

T2203

1 2

R2202 20KOhm@

CRB 0.53 reserve 150k ohm

1 2

R2203 4.7KOhm@

BA22
AY22
BB22
BA21
AY21

AW22

AY20

AW20

AK7
AK6
AK9

AK10

AW5

HDA_SPKR

AU_I2S0_SDO_R

+3VSUS_ORG

1

T2226

R2201 200Ohm1%

+VCCPAZIO 26

+3VS 3,4,21,23,24,30,31,3 2,36,37,44,45,47,50,51 ,53,57,62,64,91,92

+3VSUS_ORG 20,21,23,25,26

1 2

GND

+RTCBAT

1 2

R2.0_10L ---+RTCBAT will low when R2218
change to 47Kohm

GND

2016.5.11
R1.2_10L ---RTC detect circuit

R2218
47KOhm

/RTC

Q2201
2N7002

/RTC

+1.8VSUS

1

1

G

2016.7.6

R2219
100KOhm

/RTC

1 2

RTC_IN#

32

3

D

S

2

GND

A A

<Variant Name>

<Variant Name>

<Variant Name>

PCH(3)_HDA/SDIO

PCH(3)_HDA/SDIO

PCH(3)_HDA/SDIO

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

X3

X3

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

22 97Monday, July 11, 2016

22 97Monday, July 11, 2016

22 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

of

5

D D

PCIE_RXN4_WLAN53

WLAN

SSD

C C

PCIE_RCOMP PDG 0.9 need 100 ohm 0.1% / CRB 0.53 use 100 ohm +-1%

PCIE_RXP4_WLAN53

PCIE_TXN4_WLAN53
PCIE_TXP4_WLAN53

PCIE_RXN5_SSD51
PCIE_RXP5_SSD51

PCIE_TXN5_SSD51
PCIE_TXP5_SSD51

PCIE_RXN6_SSD51
PCIE_RXP6_SSD51

PCIE_TXN6_SSD51
PCIE_TXP6_SSD51

PCIE_RXN7_SSD51
PCIE_RXP7_SSD51

PCIE_TXN7_SSD51
PCIE_TXP7_SSD51

PCIE_SATA_RXN8_SSD51
PCIE_SATA_RXP8_SSD51
PCIE_SATA_TXN8_SSD51

PCIE_SATA_TXP8_SSD51

+3VS

R2318 10KOhm

12

4

C2309 0.1UF/16V
C2310 0.1UF/16V

1 2

R2301 100Ohm1%

T2323
T2324

1 2
1 2

1

PROC_PRDY#

1

PROV_PREQ#
PIRQA#

PCIE_TXN4_WLAN_C
PCIE_TXP4_WLAN_C

PCIE_RCOMPN
PCIE_RCOMPP

U0301H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

940432

01V010000015

3

SSIC / USB3

USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN

USB3_2_TXP/SSIC_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

(OD)

GPP_E4/DEVSLP0

(OD)

GPP_E5/DEVSLP1

(OD)

GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3
AG4

A9
C9
D9
B9

J1
J2
J3

H2
H3
G4

H1

2

USBCOMP
USB2_ID_OTG
USB2_VBUSSENSE_OTG

OC0#
OC1#
OC2#
NFC_IRQ_R

+3VSUS_ORG

+3VS

USB3_RXN1 52

USB3_RXP1 52
USB3_TXN1 52
USB3_TXP1 52

USB3_RXN3 41

USB3_RXP3 41

USB3_TXN3 41

USB3_TXP3 41

USB_PN1_30 52
USB_PP1_30 52

USB_PN2_20 64
USB_PP2_20 64

USB_PN3_PD 42
USB_PP3_PD 42

USB_PN4_PD 42
USB_PP4_PD 42

USB_PN5_BT 53
USB_PP5_BT 53

USB_PN6_FP 31
USB_PP6_FP 31

USB_PN7_CCD 45
USB_PP7_CCD 45

USB_PN8_CR 64
USB_PP8_CR 64

USB_PN9_TS 45
USB_PP9_TS 45

USB2_COMP PDG 1.0 R=113 +-1%

1 2

R2302 113Ohm1%

1 2

R2319 1KOhm

1 2

R2320 1KOhm

5 6
1 2
7 8
3 4

SSD_DEVSLP 51

SATA_SSD_PEDET 51

1

+3VSUS_ORG 20,21, 22,25,26

+3VS 3,4,21,22,24,30,31,32,36,37,44,45,47,50,51,53,57,62,64,91,92

USB30 w/charger

USB3 Type C

USB30

USB20

Type C_Power Delivery

Type C_Power Delivery

Bluetooth

Fingerprinter

Camera

Card reader

Touch

MOW 5.1.3 If the platform does not

GND
GND

support Dual Role, then USB2_ID pin

GND

shall be connected directly to GND.

RN2301C

10KOhm

RN2301A

10KOhm

RN2301D

10KOhm

RN2301B

10KOhm

1

1 2

R2321 0Ohm

1 2

R2322 0Ohm

1 2

R2310 0Ohm

T2325

+3VSUS_ORG

USB_OC0#_PCH 52
USB_OC1#_PCH 64
USB_OC2#_PCH 42

USB30
USB20

B B

Capture from 545659_545659_SKL_PCH_LP_EDS_Rev1_0_pub
Please refer the latest Doc.

A A

<Variant Name>

<Variant Name>

<Variant Name>

PCH(4)_USB/PCIE/SATA

PCH(4)_USB/PCIE/SATA

PCH(4)_USB/PCIE/SATA

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

X3

X3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

23 97Monday, July 11, 2016

23 97Monday, July 11, 2016

23 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

of

5

D D

C C

CLK_REQ1#

B B

CLK_PCIE_SSD#51
CLK_PCIE_SSD51

CLK_SSD_REQ#51

CLK_PCIE_WLAN#_PCH53
CLK_PCIE_WLAN_PCH53
CLK_REQ4_WLAN#53

CLK_REQ4_WLAN#_R

SRCCLKREQ#[5:0] (PDG v1.3 Page 835)

SRCCLKREQ#[5:0] (PDG v1.3 Page 835)

SRCCLKREQ#[5:0] (PDG v1.3 Page 835)SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
Any un-used, disabled, must be left as no connects at the PCH side on the platform.

Any un-used, disabled, must be left as no connects at the PCH side on the platform.

Any un-used, disabled, must be left as no connects at the PCH side on the platform.Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.

Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.

Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.

CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)

CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)

CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
Any differential clock pair not being used must be left as no connect

Any differential clock pair not being used must be left as no connect

Any differential clock pair not being used must be left as no connectAny differential clock pair not being used must be left as no connect

1 2

R2426 10KOhm

SP2419
SP2420
SP2421

1 2

SP2412

1 2

SP2413

1 2

SP2414

1 2

R2427 10KOhm

1 2

R2408 10KOhm@

1 2

R2411 10KOhm

12
12
12

T2401

T2403

@

+3VS

1

SNN_CLKOUT_PCIE_N0

1

SNN_CLKOUT_PCIE_N2

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
CLK_REQ1#

CLK_PCIE_WLAN#_PCH_R
CLK_PCIE_WLAN_PCH_R
CLK_REQ4_WLAN#_R

+3VSUS

+3VS

GND

AR10

AT10

U0301I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

940432

01V010000015

U0301J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

940432

01V010000015

4

C37

CSI2_CLKN0

D37

CSI2_CLKP0

C32

CSI2_CLKN1

D32

CSI2_CLKP1

C29

CSI2_CLKN2

D29

CSI2_CLKP2

B26

CSI2_CLKN3

A26

CSI2_CLKP3

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

CSI2_COMP
GPP_D4

EMMC_RCOMP

F43
E43

BA17

E37
E35

E42

AM18
AM20

AN18
AM16

CLOCK SIGNALS

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

R2418 100Ohm1%

R2419 200Ohm1%

SUSCLK_PCH

XTAL_24M_IN
XTAL_24M_OUT

XCLK_BIASREF

XTAL_32K_X1
XTAL_32K_X2

SRTC_RST#
RTC_RST#

3

1 2

1

1 2

1

T2404

1 2

R2417 2.7KOhm

1 2

R2422 60.4Ohm@

T2417

PDG 0.9 - 2.7k +-1%

GND

GND

+VCCF24NS_1P0

+VCCF24NS_1P0

+VCC_RTC

+3VSUS

GND

+3VA

+3VS

12

R2401
1MOhm

SP2401

1 2

NB_R0402_5MIL_SMALL

SP2402

1 2

NB_R0402_5MIL_SMALL

12

R2402
10MOhm

SW_RTCRST30

2

+VCCF24NS_1P0 26

+VCC_RTC 25,26,36,60

+3VA 30,31,36,41,43,53,57,64,81,88,93

+3VS 3,4,21,22,23,30,31,32,36,37,44,45,47,50,51,53,57,62,64,91,92

+3VSUS 4,25,26,28, 30,31,41,42,51,53,62,64,68,81,92

R2425
0Ohm@

+RTC_AC

+VCC_RTC

R2420
1KOhm

1 2

@

D2401

1

3

2

+RTC_BAT

12

Q2401
2N7002

GND

GND

1

1

R2405 1KOhm

GND

GND

GND

32

3

D

G

S

2

GND

X2401
24MHZ

XTAL_24M_OUT_R

XTAL_32K_X1_R

C2407
1UF/6.3V

13

2

4

X2402

32.768KHZ

1 2

07V080000064
2p_3.3*1.6*0.9_ESR 50K

R2406

12

0.8V/0.2mA

Use two in one package diode for cost reduction
Make sure +RTC BAT Voltage lower than +RTC AC

GND

1 2

C2401 10PF/50V

5%

1 2

C2402 10PF/50V

5%

1 2

C2403 15PF/50V

1 2

C2404 15PF/50V

1 2

R2407

10KOhm

1

+3VA

R2423

1.5KOhm

1%

3.19V~3.18V VCCRTC is sourced from Vbatt in G3 or VCCDSW_3p3
in Non-G3 state, platform designers must ensure the
effective voltage at VCCRTC does not exceed 3.2V.

R2424

45.3KOhm

1%

JRST2402

SGL_JUMP

JRST2401

SGL_JUMP

+RTCBAT

GND

1

1

2

@

2

1

1

2

@

2

GND GND

J2401

22SIDE1

1

1

SIDE2

WTOB_CON_2P

P/N: 12V17AISM001

1 2

R2403 20KOhm

12

C2405

1UF/6.3V

GNDGND

1 2

R2404 20KOhm

12

C2406

1UF/6.3V

GND

1 2

3

4

GND

+VCC_RTC

2015.04.06 YenPin
Add CLOCK Buffer Schematic (CRB Page123)

A A

R2426~R2428 Close To U2401 SUSCLK is on the DSW well and is available

Remove SUSCLK

5

earlier in the boot sequence.

<Variant Name>

<Variant Name>

<Variant Name>

PCH(5)_CLK

PCH(5)_CLK

PCH(5)_CLK

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

X3

X3

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

24 97Monday, July 11, 2016

24 97Monday, July 11, 2016

24 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

+3VSUS_ORG

+VCC_RTC

+VCCDSW

+VCCST_CPU

+3VSUS

D D

+3VSUS_ORG

12

R2501
10KOhm

PLT_RST#

1 2

PM_RSMRST#30

ALL_SYS_PWRGD delay 99 ms from EC

DSW function / non-AMT

C C

U2501

@

1

5

A

VCC

R2515

GND

2

B
GND3Y

SN74LVC1G08DCKR

1 2

4

PLT_RST#

12

C2502
100PF/50V

B B

@

SYS_PWROK30,68

SUSWARN#/SUSPWRDNACK30

WAKE_PCIE#53

+3V

12

SUSACK#30

C2503
100PF/50V

@

1

H_CPUPWRGD_TP H_CPUPWRGD

T2501

BUF_PLT_RST# 30, 32,51,53,62

12

R2516
10KOhm

GNDGNDGND

R2535

1 2

R2503 1KOhm

1 2

R2504

1 2

R2505

1 2

R2506

1 2

R2508 0Ohm/SBA

1 2

R2509 0Ohm/SBA

1 2

R2510 0Ohm@

1

T2502

1

T2508

PM_SYS_RESET#_R

PM_RSMRST_R

H_VCCST_PWRGD_MCP

SYS_PWROK_R
PM_PCH_PWROK_RPM_PWROK
PCH_DPWROKPM_RSMRST_R

SUS_PWR_ACK_R
SUSACK#_RSUS_PWR_ACK_R

LAN_WAKE#
GPD11
GPD7

ALL_SYSTEM_PWRGD30,92

DELAY_ALL_SYSTEM_PWRGD30

VRM_PWRGD80,92

R1.0_10L ---Shutdown possible solution

U0301K

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

940432

01V010000015

SP2506

D2501 RB751V-40

PLT_RST#

D2502 RB751V-40

1 2

R2531 0Ohm@

1 2

1 2

1 2

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#
SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

ALL_SYSTEM_PWRGD_PMOK

VR_READY_PMOK

AT11

SLP_S0#

AP15

SLP_S3#_R

BA16

SLP_S4#_R

AY16

GPD10

AN15

SLP_SUS#

AW15

SLP_LAN#

BB17

SLP_WLAN#

AN16

ME_SLP_A#

BA15
AY15

AC_PRESENT_R

AU13

BATLOW#

AU11

PME#

AP16

SM_INTRUDER#

AM10

MPHY_EXT_PWR_GATEB_R

AM11

VR_ALERT#

U2502

A

1

B

2

3 4

GND

Vcc=2~5.5

1 2

R2517 0Ohm@

5

VCC

Y

1 2

R2533

1 2

R2534

1 2

R2538 0Ohm/SBA

1 2

R2532 0Ohm/SBA

1 2

R2513 1MOhm

1 2

+3VSUS

GND

12

R2519
10KOhm

1

1

1
1
1

SP2505

PM_PWROK

T2503

T2504

T2510
T2505
T2511

+VCC_RTC

+3VSUS_ORG 20,21,22,23,26

+VCC_RTC 24,26,36,60

+VCCDSW 26,30

+VCCST_CPU 3,5,7,9,32

+3V 31,57,82,91

+3V

+3VSUS 4,24,26,28,30,31,41,42,51, 53,62,64,68,81,92

PM_SUSB# 30,68
PM_SUSC# 30,68

ME_PM_SLP_A# 30

PM_PWRBTN# 30

ME_AC_PRESENT 30

BATLOW#

LAN_WAKE#

GPD7

WAKE_PCIE#

AC_PRESENT_R

PM_PWRBTN#

Set to GPI

PME#

VR_ALERT#

internal pull high

+3VSUS_ORG

12

R2514
10KOhm

internal pull high

1 2

R2522 10KOhm

1 2

R2523 10KOhm

1 2

R2524 10KOhm

1 2

R2525 1KOhm

1 2

R2526 10KOhm

@

1 2

R2537 10KOhm

1 2

R2527 10KOhm@

1 2

R2528 10KOhm@

MPHY_EXT_PWR_GATEB 26

+VCCDSW

+3VSUS_ORG

+3VSUS

+VCCST_CPU

12

U2503

1

NC
A

GND

74AUP1G07GW

06V030000021

VCC

Y

EC delay ALL_SYSTEM_PWRGD 2ms

A A

5

DELAY_ALL_SYSTEM_PWRGD
ALL_SYSTEM_PWRGD

4

1 2

R2529

1 2

R2530 0Ohm@

H_VCCST_PWRGD_L

2
3 4

3

12

5

H_VCCST_PWRGD_R H_VCCST_PWRGD_MCP

C2504

0.1UF/16V

R2520
1KOhm

R2521 60.4Ohm1%

12

C2505

0.1UF/16V

@

+VDDQ/+VCCST_CPU/+VCCSTG to VCCST_PWRGD must > 1ms

1 2

2

PCH(6)_POWER MANAGE

PCH(6)_POWER MANAGE

PCH(6)_POWER MANAGE

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

X3

X3

Date: Sheet of

Date: Sheet of

Date: Sheet

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

25 97Monday, July 11, 2016

25 97Monday, July 11, 2016

25 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

of

5

D D

2016.6.3
R1.2_10L ---Current rating

+1.0VSUS

+VCCPRIM_CORE

+1.0VSUS

+1.0VSUS

+VCCDSW

+1.8VSUS

+VCCPAZIO

+VCC_RTC

+VCCF24NS_1P0

+3VSUS_ORG

R2601

1 2

R2603

1 2

+3VSUS

near K17

+VCCMPHYGTAON_1P0_LS_SIP

G

12

12

C2605

near N15

47uF/6.3V

C C

B B

+1.0VSUS

+3VSUS_ORG

B2607 600Ohm/100MHZ

+3VSUS_ORG

R2611

1 2

w/o DSW

MPHY_EXT_PWR_GATEB25

MPHY_EXT_PWR_GATEB should pull high at A0 chip

A A

@

21

B2604 600Ohm/100MHZ

C2608

47uF/6.3V

21

12

12

2016.6.13

R1.2_10L ---Follow megatron_KBL

+3VSUS_ORG/+1.8VSUS to +1.0VSUS >200us (tPCH06)

+3VSUS_ORG +VCCDSW

R2633 0Ohm

12

+1.0VSUS

+VCCDSW

+3VSUS_ORG

C2609
1UF/10V

+1.0VSUS

C2611
1UF/10V

+VCCAPLLEBB_1P0

JP2601

2

2MM_OPEN_5MIL

1 2

R2644

C2606
1UF/10V

near N15

1 2

G

112

R2612

1 2

+1.0VSUS 82

+VCCDSW 25,30

+1.8VSUS 9,21,22,84

+VCCPAZIO 22

+VCC_RTC 24,25,36,60

+VCCF24NS_1P0 24

+3VSUS_ORG 20,21,22,23,25

+3VSUS 4,24,25,28, 30,31,41,42,51,53,62,64,68,81,92

2016.6.13
R1.2_10L ---Follow megatron_KBL

12

C2601

near AB19

1UF/10V

12

C2602

near AF18

1UF/10V

2016.6.13

R1.2_10L ---Follow megatron_KBL

12

C2603
1UF/10V

Decoupling cap for internal power

+VCCDSW_1P0

+VCCMPHYAON_1P0

+VCCAMPHYPLL_1P0

G

+VCCPDSW_3P3

1 2
1 2

+VCCPRIM_3P3

near N18

12

C2629

0.033UF/16V

@

+V1.00A_SIP

+VCCSRAM_1P0

G

+VCCMPHYGTAON_1P0_LS_P

R2605

1 2

R2606

1 2

+1.8VSUS

12

+3VSUS_ORG+3VSUS

R2609 0Ohm@

R2610

+VCCFHV

C2612
1UF/10V

C2604 1UF/10V

+VCCAPLL_1P0

+VCCPSPI

C2610 1UF/10V

2016.6.13
R1.2_10L ---Follow megatron_KBL

+1.0VSUS +VCCMPHYGTAON_1P0_LS

+5VO +1.0VSUS

12

C2632
1UF/10V

4

+VCCPRIM_1P0

1 2

near AL1

12

C2607
1UF/10V

near K15

2016.6.13

R1.2_10L ---Follow megatron_KBL

+VCCPAZIO

1 2

near AF20

1 2

R2635 0Ohm

vx_r1206_h28

@

1 2

R2645 0Ohm

vx_r1206_h28

U2601

1

VIN1_1

2

VIN1_2

3

ON1

4

VBIAS

5

ON2

6

VIN2_1
VIN2_27VOUT2_1

SN10548

12

12

C2630
1UF/10V

C2633
1UF/10V

SATA Gen3 Port X 2
PCIe Gen2 Lane X 1
USB3 Port X 2
All HSIO disabled (basic comsunption)
=0.132x2+0.102+0.132x2+0.064 = 0.694A

U0301O

0.696A

2.574A

0.022A

0.694A

0.088A

0.026A

0.696A

0.118A

0.068A

0.011A

0.642A

0.075A

0.696A

0.033A

R2636 0Ohm

R2637 0Ohm

R2638

R2639

AB19
AB20

AF18
AF19

AB17

AD17
AD18
AJ17

AJ19

AJ16

AF20
AF21

AJ21

AK20

P18

V20
V21

AL1

K17

L1

N15
N16
N17
P15
P16

K15
L15

V15

Y18

T19
T20

N18

VCCPRIM_1P0_1
VCCPRIM_1P0_2
VCCPRIM_1P0_3

VCCPRIM_CORE_1
VCCPRIM_CORE_2
VCCPRIM_CORE_3
VCCPRIM_CORE_4

DCPDSW_1p0

VCCMPHYAON_1P0_1
VCCMPHYAON_1P0_2

VCCMPHYGT_1P0_1
VCCMPHYGT_1P0_2
VCCMPHYGT_1P0_3
VCCMPHYGT_1P0_4
VCCMPHYGT_1P0_5

VCCAMPHYPLL_1P0_1
VCCAMPHYPLL_1P0_2

VCCAPLL_1P0

VCCPRIM_1P0_4
VCCPRIM_1P0_5

VCCDSW_3p3_1
VCCDSW_3p3_2
VCCDSW_3p3_3

VCCHDA

VCCSPI

VCCSRAM_1P0_1
VCCSRAM_1P0_2
VCCSRAM_1P0_3
VCCSRAM_1P0_4

VCCPRIM_3p3_1

VCCPRIM_1P0_6

VCCAPLLEBB_1P0

940432

01V010000015

1 2

1 2

1 2

1 2

CPU POWER 4 OF 4

+VCCMPHYGTAON_1P0_LS_SIP

if need choke, gate power should be disabled

15

GND2

14

VOUT1_2

13

VOUT1_1

12

CT1

11

GND1

10

CT2

9

VOUT2_2

8

12

C2627
220PF/25V

+VCCSRAM_1P0

12

C2628
220PF/25V

3

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG

VCCPRIM_3p3_2

VCCPRIM_1P0_7

VCCATS_1p8

VCCRTCPRIM_3p3

VCCRTC_1
VCCRTC_2

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

G

G

+VCCAMPHYPLL_1P0

+VCCAPLLEBB_1P0

12

C2631

0.1UF/6.3V

12

C2626

0.1UF/6.3V

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19

T1

AA1

AK17

AK19
BB14

BB10

A14

K19

L21

N20

L19

A10

AN11
AN13

T2601

TPC26T

12

near AG15

C2635

1UF/10V

2016.6.13
R1.2_10L ---Follow megatron_KBL

0.02A

0.004A

+VCCPGPPA

0.075A

0.696A

0.006A

0.001A

VCCRTCEXT

0.035A

0.029A

0.024A

0.033A

0.004A

0.039A

GPP_B0
GPP_B1

0.006A

+VCCPGPPB

+VCCPGPPC

1 2

C2634 0.1UF/16V

GND

C2620 0.1UF/16V

12

R2646
1KOhm

12

0.008A

+VCCPGPPD

12

near BB10

R2647
1KOhm

0.006A

+VCCPGPPE

near AK19

0.001A

Intel confirm pull down 1k

G

G

Iout =2.12A / ICC_Max 2.12A _CRB 0.53/TPCH17 TR<200us

+VCCMPHYGTAON_1P0_LS_P

1

2

C2613

near Y16

1UF/10V

2016.6.13
R1.2_10L ---Follow megatron_KBL

C2614

1UF/10V

2016.6.13
R1.2_10L ---Follow megatron_KBL

0.161A

0.041A

+VCCPGPPF

+VCCPGPPG

+VCCPRTC_3P3

GND

1 2

1 2

C2619 1UF/10V

R2626

12

12

near T16

+VCCPRIM_3P3

+VCC_RTC

+VCCF24NS_1P0

+VCC24TBT_1P0

+VCCDSW

R2613

1 2

1 2

R2616

1 2

R2617

1 2

R2619

1 2

R2620

1 2

R2621

1 2

+VCCDTS_1P0

near AK19

GND

+VCCF100OC_1P0

+3VSUS_ORG

R2615

+3VSUS_ORG

+1.8VSUS

+3VSUS_ORG

R2623

1 2

+V1.8A_SIP

+VCC19P2_1P0

+VCCF100_1P0

+VCCF135_1P0

C2624

near A10

1UF/10V

R1.2_10L ---Follow megatron_KBL

1 2

R2641 0Ohm

Q2601

D

3

G

1

2

3

1

E1

B1

C2

C1

B2

E24

5

6

12

R2634
100KOhm

@

2016.01.07
R1.2
Armani 2016 project for USB D+/D- short lesson learn solution (EC)

+3VSUS_ORG

+3VSUS_ORG

+3VSUS_ORG

+1.0VSUS

1 2

12

C2615
1UF/10V

+VCCPRTCPRIM_3P3

12

2016.6.13

@

S

23

2

1

SI2301CDS-T1-GE3

Q2602
BC856BS

@

1

+1.8VSUS

R2624

near AA1

12

12

C2617

near AK17 near AK17

0.1UF/16V

R2627

1 2

R2628

1 2

R2629

1 2

R2630

1 2

R2631

1 2

R2632

1 2

12

R2640
100KOhm

@

+1.0VSUS

+1.0VSUS

+1.0VSUS

+1.0VSUS

+1.0VSUS

+1.0VSUS

+VCCPDSW_3P3+VCCDSW

1 2

C2618
1UF/10V

R2625

+3VSUS_ORG

PCH(7)_POWER

PCH(7)_POWER

PCH(7)_POWER

Title :

Title :

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

X3

X3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

X3

Engineer:

Engineer:

Engineer:

1

Title :

Andy Kao

Andy Kao

Andy Kao

26 97Monday, July 11, 2016

26 97Monday, July 11, 2016

26 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

C C

4

3

2

1

B B

A A

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

A

A

A

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

X3

X3

X3

2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

<Title>

<Title>

<Title>

Andy Kao

Andy Kao

Andy Kao

27 97Monday, July 11, 2016

27 97Monday, July 11, 2016

27 97Monday, July 11, 2016

1

Rev

Rev

Rev

1.0

1.0

1.0

5

R2802

+3VSUS +3VS

R2822 0Ohm@

+3VA_EC

D D

1 2

1 2

4

+3VM_SPI

55mA

D2801

1

3

2

@

0.8V/0.2mA

1 2

R2804

3

+3VM_SPI

2

+12VS

+3VSUS

+3VA_EC

+12VSUS

+3VS 3,4,21,22,23,24,30,31,32,36,37,44,45,47,50,51,53,57,62,64,91,92

+12VS 31,48,57,91

+3VSUS 4,24,25,26, 30,31,41,42,51,53,62,64,68,81,92

+3VA_EC 30, 32,44

+12VSUS 81, 91

1

R2811
1KOhm @

R2832
1KOhm @

12

+3VM_SPI

12

+3VM_SPI

12

@

12

R2812

3.3KOhm

R2826

3.3KOhm

@

U2801

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q128FVSIQ

U2802

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q64FVSSIQ

/8M_ROM

HOLD#/RESET#(IO3)

DI(IO0)

8

VCC

7

HOLD#(IO3)

6

CLK

5

DI(IO0)

VCC

CLK

C2801

0.1UF/16V

8
7

SPI0_HOLD#_R

6

SPI0_CLK_R

5

C2802

0.1UF/16V

/8M_ROM

SPI1_HOLD#_R
SPI1_CLK_R

SPI1_SI_R

15WW06 MOW Pull-up Resistors on SPI_IO2 and SPI_IO3 are no longer needed

1 2

SPI_WP#_IO220,28

SPI_SO20,28,44

R1.1_10L ---BIOS request

C C

SPI_CS#120

F_CS#_EC30
F_SDIO_EC30

SPI_CS#0

15WW06 MOW Pull-up Resistors on SPI_IO2 and SPI_IO3 are no longer needed

SPI_WP#_IO220,28
SPI_SO20,28,44
SPI_CS#020,44

R2805 33Ohm

1 2

R2806 33Ohm

1 2

R2807 0Ohm

/16M_CS1#

1 2

R2808 33Ohm

1 2

R2809 33Ohm

1 2

R2834 0Ohm

/16M_CS0#

R1.1_10L---Option with SPI_CS#1

1 2

R2825 33Ohm/8M_ROM

1 2

R2828 33Ohm/8M_ROM

1 2

R2833 0Ohm/8M_CS0#

SPI0_CS#1_R
SPI0_SO_R
SPI0_WP#_R

SPI1_CS#0_R
SPI1_SO_R
SPI11_WP#_R

12

SPI0_SI_R

+3VM_SPI

12

12

R2813

@

1KOhm

WW36MOW (for ES Pre-ES Sample)
SPI0_IO# Should be pull-down 1K

1 2

R2820 1KOhm

12

R2829

@

1KOhm

WW36MOW (for ES Pre-ES Sample)
SPI0_IO# Should be pull-down 1K

1 2

R2830 1KOhm

/8M_ROM

1 2

R2814 33Ohm

1 2

R2815 33Ohm

1 2

R2816 33Ohm

1 2

R2818 33Ohm

1 2

R2819 33Ohm

1 2

R2821 3KOhm

1 2

R2824 33Ohm/8M_ROM

1 2

R2827 33Ohm/8M_ROM

1 2

R2831 33Ohm/8M_ROM

1 2

R2823 3KOhm

/8M_ROM

+3VM_SPI

+3VM_SPI

SPI_HOLD#_IO3 20,28,44
SPI_CLK 20,28,44
SPI_SI 20,28,44

F_SCK_EC 30
F_SDI_EC 30

SPI_HOLD#_IO3 20, 28,44
SPI_CLK 20,28,44
SPI_SI 20,28,44

R1.1_10L ---BIOS request

PCH SMBus

B B

PCH

LPC

EC

SPI0

CS0

CS1

FSPI

U2801

16M

BIOS+EC+PBA

U2802

+12VSUS

8M

2

A A

ME(SBA)

SMB1_CLK30

EC PCH

SMB1_DAT30

5

4

3

Q2802A

UM6K1N

6 1

@

Q2802B

UM6K1N

3 4

@

SML1_CLK 20

5

SML1_DAT 20

2

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

PCH(9)_SPI,SMB

PCH(9)_SPI,SMB

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

PEGATRON PROPRIETARY AND CONFIDENTI AL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

X3

X3

X3

Engineer:

Engineer:

Engineer:

1

PCH(9)_SPI,SMB

Andy Kao

Andy Kao

Andy Kao

28 97Monday, July 11, 2016

28 97Monday, July 11, 2016

28 97Monday, July 11, 2016

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

C C

4

3

2

1

B B

A A

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

PEGATRON PROPRIETARY AND CONFIDENTIAL

BG1/HW3

BG1/HW3

BG1/HW3

Size Project Name

Size Project Name

Size Project Name

A

A

A

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

X3

X3

X3

2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

<Title>

<Title>

<Title>

Andy Kao

Andy Kao

Andy Kao

29 97Monday, July 11, 2016

29 97Monday, July 11, 2016

29 97Monday, July 11, 2016

1

Rev

Rev

Rev

1.0

1.0

1.0