Acer SWIFT 5 SF514-52T Schematic
5
D D
4
3
2
1
17809 -1m Carlsberg_KL
Schematics Document
C C
B B
A A
DY : None Installed
UMA: UMA only installed
DIS: DISCRTE OPTIMUS installed
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
Cover Page
Cover Page
Cover Page
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
1 106
1 106
1 106
-1M
-1M
-1M
5
4
Project Code: 4PD0D7010001
PCB No : 17809
Re
vision : -1m
3
2
1
D D
CCD/DMIC
55
LCD FHD:1920*1080
WXGA:1366*768
Touch Panel
55
DMIC
USB2.0x1
eDPx2
I2C x1
USB2.0x1
LCD CONN.
USB2.0x1
I2C x1 DY
USB2.0x1
DMIC
eDPx2
DY
LPDDR3 Channel A
LPDDR3 Channel B
24MHz
U22:X1601
U42:X2301
LPDDR3 MD x2 pcs
LPDDR3 MD x2 pcs
16
23
12
13
Intel CPU
X1
602
RTS5450
Charger
BQ24780S
16
TYPEC
73
57
Mini-Card
WLAN & BT
comb module
2
M2
SSD
74
M2
SSD
61
62
63
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Custom
Custom
Custom
Wednesday, N ovember 01, 20 17
Wednesday, N ovember 01, 20 17
Wednesday, N ovember 01, 20 17
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Block Diagram
Block Diagram
Block Diagram
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
2 106
2 106
2 106
-1M
-1M
-1M
73
92
57
25
HDMI 1.4b
44
55
Kabylake R U
32.768KHz
15W
USB3.0 *1
USB2.0 x1
USB3.0 x 1
C C
35
USB Charger
USB3.0 *1
I2C for Precision Touchpad
Small Board :17A38-SA
Combo Jack
B B
A A
DMIC
SPK 2W 8 ohm
Hall sensor
5
27
0R
SPK-OUT_R_+/SPK-OUT_L_+/-
29
66
66
Connector
HD Audio Codec
ALC255
I2C for Precision Touchpad
Thermal
VD_IN1
FAN
4
USB2.0 x1
36
10 USB 2.0/1.1 ports
USB2.0 x1
USB3.0 x1
35
HD Audio
27
6 USB 3.0 ports
High Definition Audio
3 SATA ports
6 PCIE ports
LPC I/F
ACPI 5.0
ITPM
DDIx 1
USB3.0 x 1
USB2.0 x 1
USB2.0
DDI1
PCIe x 1
USB2.0 x 1
PCIe x 4(SATA*1)
PCIe x 4(SATA*1)
SPI
Finger print
Redriver
PS8201
SPI Flash
MX25U6473FM2I
-10G-GP
8MB
5,7,8,9,10,
11,12,15,16,18,19,21
TPM
VID
26
PWM
26
LPC BUS
91NPCT650
KB9028QA
PS2
Touch PAD
KBC
LPC debug port
24
Int.
KB
6565
3
68
SMBus
5
4
3
2
1
Main Func = CPU
CPU1A
SKYLAKE_ULT
DDI
DISPLAY SIDEBANDS
Strap
Strap
Strap
3D3V_S0
EDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
1 2
HDMI_DATA_CPU_N2
HDMI_DATA_CPU_P2
HDMI_DATA_CPU_N1
HDMI_DATA_CPU_P1
HDMI_DATA_CPU_N0
HDMI_DATA_CPU_P0
HDMI_DATA_CPU_N3
HDMI_DATA_CPU_P3
DP_DDI_TX_N0
DP_DDI_TX_P0
DP_DDI_TX_N1
DP_DDI_TX_P1
DP_DDI_TX_N2
DP_DDI_TX_P2
DP_DDI_TX_N3
DP_DDI_TX_P3
HDMI_CLK_CPU
HDMI_DATA_CPU
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CDA
EDP_RCOMP
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22
N12
GPP_E23
E52
EDP_RCOMP
SKYLAKE-U-GP
CPU
eDP_TX_CPU_N055
eDP_TX_CPU_P055
D D
eDP_TX_CPU_N155
eDP_TX_CPU_P155
eDP_AUX_CPU_N55
eDP_AUX_CPU_P55
eDP_HPD_CPU55
eDP_BLEN_CPU24
eDP_BLCTRL_CPU55
eDP_VDDEN_CPU55
HDMI
TYPEC
HDMI
eDP
HDMI_DATA_CPU_N257
HDMI_DATA_CPU_P257
C C
HDMI_DATA_CPU_N157
HDMI_DATA_CPU_P157
HDMI_DATA_CPU_N057
HDMI_DATA_CPU_P057
HDMI_DATA_CPU_N357
HDMI_DATA_CPU_P357
HDMI_CLK_CPU14,57
HDMI_DATA_CPU14,57
HDMI_DET_CPU57
1V_VCCIO
HDMI
R301 24D9R2F-L-GP
1 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
RSVD#G46
RSVD#F46
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
eDP_TX_CPU_N0
eDP_TX_CPU_P0
eDP_TX_CPU_N1
eDP_TX_CPU_P1
eDP_AUX_CPU_N
eDP_AUX_CPU_P
DP_AUX_CPU_N
DP_AUX_CPU_P
HDMI_DET_CPU
DP_HPD_CON
EC_SCI#
eDP_HPD_CPU
eDP_BLEN_CPU
eDP_BLCTRL_CPU
eDP_VDDEN_CPU
eDP
eDP
DP_DDI_TX_N073
B B
A A
DP_DDI_TX_P073
DP_DDI_TX_N173
DP_DDI_TX_P173
DP_DDI_TX_N273
DP_DDI_TX_P273
DP_DDI_TX_N373
DP_DDI_TX_P373
DP_AUX_CPU_N73
DP_AUX_CPU_P73
DDPC_CTRLDATA14
DP_HPD_CON73
DDPD_CDA14
EC_SCI#24
5
TYPEC
OTHER
3D3V_S0
EC_SCI#
R307
12
2K2R2J-L1-GP
(#543016) eDP_RCOMP Guideline
Signal Trace
eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%
sign Guideline:
De
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.
Width
4
eDP_BLEN_CPU
DP_HPD_CON
20170302 Change
Isolation
Spacing
R304
1 2
100KR2F-L3-GP
R320
1 2
100KR2F-L3-GP
Resistor
Value
Max = 100 mils
Length
3
12
R310
2K2R2J-2-GP
DY
DDPC_CTRLCLK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU_(DISPLAY)
CPU_(DISPLAY)
CPU_(DISPLAY)
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
3 106
3 106
3 106
-1M
-1M
-1M
5
Main Func = CPU
DATA
M_A_DQ[63:0]12
D D
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_CA_A[9:0]12
M_A_CA_B[9:0]12
M_A_CLK012
M_A_CLK#012
M_A_CLK112
M_A_CLK#112
M_A_CKE012
M_A_CKE112
M_A_CKE212
M_A_CKE312
M_A_CS#012
M_A_CS#112
M_A_ODT012
V_DDR_CA_VREF12
DDR_VREFDQ01_CHA12
DDR_VREFDQ02_CHB13
DDR_VTT_CTRL_Q51
CMD
CLK
CKE
CTRL
VREF
VT
4
M_A_CA_A0
M_A_CA_A1
M_A_CA_A2
M_A_CA_A3
M_A_CA_A4
M_A_CA_A5
M_A_CA_A6
M_A_CA_A7
M_A_CA_A8
M_A_CA_A9
M_A_CA_B0
M_A_CA_B1
M_A_CA_B2
M_A_CA_B3
M_A_CA_B4
M_A_CA_B5
M_A_CA_B6
M_A_CA_B7
M_A_CA_B8
M_A_CA_B9
T CTRL
M_A_DQ[0:7]
M_A_DQ[8:15]
M_A_DQ[16:23]
M_A_DQ[24:31]
M_A_DQ[32:39]
M_A_DQ[40:47]
M_A_DQ[48:55]
M_A_DQ[56:63]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
CPU1B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
SKYLAKE-U-GP
3
SKYLAKE_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
CPU
071.SKYLA.000U
DDR CH - A
2 OF 20
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
2
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60
AW50
AT52
V_DDR_CA_VREF
AY67
DDR_VREFDQ01_CHA
AY68
DDR_VREFDQ02_CHB
BA67
AW67
M_A_CLK#0
M_A_CLK0
M_A_CLK#1
M_A_CLK1
M_A_CKE0
M_A_CKE1
M_A_CKE2
M_A_CKE3
M_A_CS#0
M_A_CS#1
M_A_ODT0
M_A_CA_A0
M_A_CA_A1
M_A_CA_A2
M_A_CA_A3
M_A_CA_A4
M_A_CA_A5
M_A_CA_A6
M_A_CA_A7
M_A_CA_A8
M_A_CA_A9
M_A_CA_B0
M_A_CA_B1
M_A_CA_B2
M_A_CA_B3
M_A_CA_B4
M_A_CA_B5
M_A_CA_B6
M_A_CA_B7
M_A_CA_B8
M_A_CA_B9
M_A_DQS_DN0
M_A_DQS_DP0
M_A_DQS_DN1
M_A_DQS_DP1
M_A_DQS_DN2
M_A_DQS_DP2
M_A_DQS_DN3
M_A_DQS_DP3
M_A_DQS_DN4
M_A_DQS_DP4
M_A_DQS_DN5
M_A_DQS_DP5
M_A_DQS_DN6
M_A_DQS_DP6
M_A_DQS_DN7
M_A_DQS_DP7
DDR_VTT_CTRL
1
A-CLK
A-CKE
A-CTRL
A
A-CMD
B
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS_DP[7:0]12
A A
M_A_DQS_DN[7:0]12
DQS
5
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
3D3V_S01D2V_S3
12
R401
G
DDR_VTT_CTRL DDR_VTT_CTRL_Q
2nd = 084.00138.0A31
4
3
DS
Q401
DMN5L06K-7-GP
84.05067.031
220KR2F-GP
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(DDR)
CPU_(DDR)
CPU_(DDR)
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
4 106
4 106
4 106
1
-1M
-1M
-1M
5
Main Func = CPU
DATA
M_B_DQ[63:0]13
D D
C C
B B
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_CA_A[9:0]13
M_B_CA_B[9:0]13
M_B_CLK013
M_B_CLK#013
M_B_CLK113
M_B_CLK#113
M_B_CKE013
M_B_CKE113
M_B_CKE213
M_B_CKE313
M_B_CS#013
M_B_CS#113
M_B_ODT013
CMD
M_B_CA_A0
M_B_CA_A1
M_B_CA_A2
M_B_CA_A3
M_B_CA_A4
M_B_CA_A5
M_B_CA_A6
M_B_CA_A7
M_B_CA_A8
M_B_CA_A9
M_B_CA_B0
M_B_CA_B1
M_B_CA_B2
M_B_CA_B3
M_B_CA_B4
M_B_CA_B5
M_B_CA_B6
M_B_CA_B7
M_B_CA_B8
M_B_CA_B9
CLK
CKE
CTRL
4
M_B_DQ[0:7]
M_B_DQ[8:15]
M_B_DQ[16:23]
M_B_DQ[24:31]
M_B_DQ[32:39]
M_B_DQ[40:47]
M_B_DQ[48:55]
M_B_DQ[56:63]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
3
CPU1C
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKYLAKE-U-GP
SKYLAKE_ULT
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
CPU
071.SKYLA.000U
DDR CH - B
2
3 OF 20
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
M_B_CLK#0
M_B_CLK#1
M_B_CLK0M_B_DQ0
M_B_CLK1
M_B_CKE0
M_B_CKE1
M_B_CKE2
M_B_CKE3
M_B_CS#0
M_B_CS#1
M_B_ODT0
M_B_CA_A0
M_B_CA_A1
M_B_CA_A2
M_B_CA_A3
M_B_CA_A4
M_B_CA_A5
M_B_CA_A6
M_B_CA_A7
M_B_CA_A8
M_B_CA_A9
M_B_CA_B0
M_B_CA_B1
M_B_CA_B2
M_B_CA_B3
M_B_CA_B4
M_B_CA_B5
M_B_CA_B6
M_B_CA_B7
M_B_CA_B8
M_B_CA_B9
M_B_DQS_DN0
M_B_DQS_DP0
M_B_DQS_DN1
M_B_DQS_DP1
M_B_DQS_DN2
M_B_DQS_DP2
M_B_DQS_DN3
M_B_DQS_DP3
M_B_DQS_DN4
M_B_DQS_DP4
M_B_DQS_DN5
M_B_DQS_DP5
M_B_DQS_DN6
M_B_DQS_DP6
M_B_DQS_DN7
M_B_DQS_DP7
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
B-CLK
B-CKE
B-CTRL
A
B-CMD
B
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
1 2
R501 200R2F-L-GP
1 2
R502 80D6R2F-L-GP
1 2
R503 162R2F-GP
1
5
DQS
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(DDR)
CPU_(DDR)
CPU_(DDR)
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
-1M
-1M
-1M
106
106
5
5
5
106
M_B_DQS_DP[7:0]13
A A
M_B_DQS_DN[7:0]13
5
Main Func = PCH
DETECT&RESET
TOUCH_DET#55
RTC_DET#25
D D
DEBUG PORT
Touch Panel
LPSS_UART2_RXD68
LPSS_UART2_T XD68
Touch Pad
I2C
PM_TP_DATA65
PM_TP_CLK65
TOUCH_DET#
GPP_B18/GSPI0_MOSI
RTC_DET#
PSW_CLR#
GPP_B22/GSPI1_MOSI
LPSS_UART2_RXD
LPSS_UART2_T XD
-1m
PM_TP_DATA
PM_TP_CLK
CPU1F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
SKYLAKE-U-GP
CPU
4
LPSS ISH
SKYLAKE_ULT
Strap
Strap
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
1.8V Only
SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6
3
6 OF 20
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D15/ISH_UART0_RTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
TPM_ID
-1m
1.8V Only
MEM_CHA_EN
MEM_CHB_EN
MEM_CONFIG1
MEM_CONFIG2
2
12
R604
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
MEM_CONFIG1 MEM_CONFIG2
10KR2J-3-GP
DY
12
R605
DY
3D3V_S5 3D3V_S5
12
R608
DY
12
R609
DY
10KR2J-3-GP
MEM_CHB_ENMEM_CHA_EN
10KR2J-3-GP
R606
R607
R610
10KR2J-3-GP
R611
10KR2J-3-GP
1
3D3V_S53D3V_S5
12
DY
12
DY
12
DY
12
DY
[#545659 Rev0.7]
C C
OTHER
GPP_B18/GSPI0_MOSI14
GPP_B22/GSPI1_MOSI14
PSW_CLR#
TOUCH_DET#
4
3D3V_S0 3D3V_S0
RN611
SRN2K2J-5-GP
23
1
PM_TP_CLK
PM_TP_DATA
RTC_DET#
8
7
6
R603
1 2
10KR2J-3-GP
RN609
SRN2K2J-4-GP
3D3V_S5
1
2
3
45
PSW_CLR#
21
Pass Word Clear
G601
B B
A A
5
GAP-OPEN
TPM_ID
4
R602
12
TPM
10KR2F-L1-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(LPSS/ISH)
CPU_(LPSS/ISH)
CPU_(LPSS/ISH)
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
6 106
6 106
6 106
-1M
-1M
-1M
5
Main Func = CPU
SVID
SVID_ALERT#_CPU46
SVID_CLK_CPU46
D D
SVID_DATA_CPU46
VCCCORE_SENSE46
VSSCORE_SENSE46
C C
B B
1V_CPU_CORE
A30
A34
A39
A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
CPU1L
SKYLAKE-U-GP
CPU POWER 1 OF 4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD#K32
RSVD#AK32
VCCOPC3
VCCOPC2
VCCOPC1
VCC_OPC_1P82
VCC_OPC_1P81
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO2
VCCEOPIO1
VCCEOPIO_SENSE
VSSEOPIO_SENSE
SKYLAKE_ULT
CPU
4
12 OF 20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG
1V_CPU_CORE
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
VCCCORE_SENSE
E32
VSSCORE_SENSE
E33
VIDALERT#_CPU
B63
VIDSCK_CPU
A63
VIDSOUT_CPU
D64
G20
VCCSTG(ICCMAX.=0.04A)
1V_VCCST
VIDSCK_CPU
VIDSOUT_CPU
1V_VCCSTG
1V_VCCSTG1V_VCCIO
R709
1 2
0R0402-PAD-1-GP
Layout Note:
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil
3
R727
1 2
56R2J-4-GP
54D9R2F-L1-GP
1 2
R731
DY
12
R726 100R2F-L3-GP
1 2
R728 220R2J-L2-GP
1 2
R729 0R0402-PAD-1-GP
1 2
R730 0R0402-PAD-1-GP
CLOSE CPU
VCCCORE_SENSE
VSSCORE_SENSE
1. Place close to CPU
VCC_SENSE/ VSS_SENSE impedance=50 ohm
2.
3. Length match<25mil
SVID_ALERT#_CPU
SVID_CLK_CPU
SVID_DATA_CPU
SVID_ALERT#_CPUVIDALERT#_CPU
SVID_CLK_CPU
SVID_DATA_CPU
1V_CPU_CORE
12
R732 100R2F-L3-GP
12
R733 100R2F-L3-GP
2
1
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU_POWER1
CPU_POWER1
CPU_POWER1
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
7 106
7 106
7 106
-1M
-1M
-1M
Main Func = CPU
5
VSSSA_SENSE46
VCCSA_SENSE46
VCCGT_SENSE46
VSSGT_SENSE46
D D
4
DY
FC800
SCD1U25V2KX-L-GP
DY
FC801
SCD1U25V2KX-L-GP
1 2
1 2
20170221 Change 1D2V_S3
12
C802 SC1U10V2KX-1GP
12
C803 SCD1U25V2KX-L-GP
1V_VCCST
C804
12
SCD1U25V2KX-L-GP
1D2V_S3
1D2V_S3
12
1D2V_S3
1V_VCCST
1V_VCCSTG
VDDQ 2A
C801
SC1U10V2KX-1GP
VD
DQC 0D2A
VccST 0D06A
0D02A 10mils
VCCPLL_OC 0D12A
VccPLL 0D12A
C805
12
SCD1U25V2KX-L-GP
DY
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
AL23
A18
A22
K20
K21
3
CPU1N
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQC
VCCST
VCCSTG
VCCPLL_OC
VCCPLL
VCCPLL
SKYLAKE-U-GP
CPU
CPU POWER 3 OF 4
SKYLAKE_ULT
14 OF 20
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
1V_VCCIO
1V_VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
VccIO 1D0V 3D1A
VccSA 0-1.15V 5A
2
1V_VCCSA
RN805
VCCSA_SENSE
1
4
1V_VCCIO
SRN100J-3-GP
RN806
4
SRN100J-3-GP
23
1
23
VSSSA_SENSE
VCCIO_SENSE
VSSIO_SENSE
1
20170223 Delete
C C
DY
FC803
SCD1U25V2KX-L-GP
B B
1V_VCCGT
A A
5
1 2
1V_VCCGT
U42:DY
U22:Stuff
R814
12
R815
12
DY
FC802
SCD1U25V2KX-L-GP
1 2
R813
1 2
0R2J-2-GP
U22
100R2F-L3-GP
100R2F-L3-GP
1V_VCCGT_C
VCCGT_SENSE
VSSGT_SENSE
4
1V_VCCGT
CPU_POWER_K52
VCCGT_SENSE
VSSGT_SENSE
CPU1M
CPU POWER 2 OF 4
A48
VCCGT
SKYLAKE_ULT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
SKYLAKE-U-GP
42 and U22 power co-lay
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
U
13 OF 20
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX1
VCCGTX2
VCCGTX3
VCCGTX4
VCCGTX5
VCCGTX6
VCCGTX7
VCCGTX8
VCCGTX9
VCCGTX10
VCCGTX11
VCCGTX12
VCCGTX13
VCCGTX14
VCCGTX15
VCCGTX16
VCCGTX17
VCCGTX18
VCCGTX19
VCCGTX20
VCCGTX21
VCCGTX22
VCCGTX23
VCCGTX24
VCCGTX25
VCCGTX26
VCCGTX27
VCCGTX28
VCCGTX29
VCCGTX_SENSE
VSSGTX_SENSE
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
1V_VCCGT
CPU
3
1V_CPU_CORE
If no plan to use U
e in the same
2+3
platform. These balls
can be connected to
VccCore. No shunting
resistor needed.
20170208 ENG R811 Change to 063.R0007.0161
1V_VCCGT_C 1V_VCCGT
R3
R811
1 2
D0002R5J-GP-U
063.R0007.0161
U22
1V_VCCGT_C 1V_CPU_CORE
R4
R812
1 2
D0002R5J-GP-U
063.R0007.0161
U42
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_POWER1
CPU_POWER1
CPU_POWER1
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
8 106
8 106
8 106
-1M
-1M
-1M
5
D D
C C
4
3
2
1
Blanking
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A A
Title
Title
Title
Reserved
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
9 106
9 106
9 106
1
-1M
-1M
-1M
12
PC1002
SC22U6D3V3MX-L1-GP
12
PC1034
SC22U6D3V3MX-L1-GP
PC10A2
12
SC22U6D3V3MX-L1-GP
PC1039
12
SC10U6D3V2MX-GP-U
DY
PC1017
12
SC10U6D3V2MX-GP-U
PC1033
12
SC10U6D3V2MX-GP-U
DY
20170118 DY
5
12
PC1018
DY
SC22U6D3V3MX-L1-GP
12
PC1035
SC22U6D3V3MX-L1-GP
PC10A3
12
SC22U6D3V3MX-L1-GP
DY
PC1040
12
SC10U6D3V2MX-GP-U
DY
20170308 DY
PC1031
12
SC10U6D3V2MX-GP-U
DY
PC1036
12
SC10U6D3V2MX-GP-U
DY
20170308 DY
20170308 DY
12
PC1019
SC22U6D3V3MX-L1-GP
12
PC1041
SC22U6D3V3MX-L1-GP
PC10A4
12
SC22U6D3V3MX-L1-GP
DY
PC1003
12
SC10U6D3V2MX-GP-U
DY
20170118 DY
PC10A5
12
SC10U6D3V2MX-GP-U
DY
PC1037
12
SC10U6D3V2MX-GP-U
12
PC1021
SC22U6D3V3MX-L1-GP
12
PC1042
SC22U6D3V3MX-L1-GP
PC10A9
12
SC22U6D3V3MX-L1-GP
DY
PC1004
12
SC10U6D3V2MX-GP-U
DY
PC10A6
12
SC10U6D3V2MX-GP-U
Main Func = CPU
1V_CPU_CORE
12
PC1001
SC22U6D3V3MX-L1-GP
1V_CPU_CORE
12
D D
PC1030
SC22U6D3V3MX-L1-GP
1V_CPU_CORE
PC10A1
12
SC22U6D3V3MX-L1-GP
DY
1V_CPU_CORE
PC1038
12
SC10U6D3V2MX-GP-U
DY
20170124 DY
1V_CPU_CORE
PC1008
12
SC10U6D3V2MX-GP-U
DY
20170118 DY
1V_CPU_CORE
PC1032
12
SC10U6D3V2MX-GP-U
DY
C C
20170124 DY
12
PC1022
SC22U6D3V3MX-L1-GP
12
PC1043
SC22U6D3V3MX-L1-GP
PC10B1
12
SC22U6D3V3MX-L1-GP
DY
PC1005
12
SC10U6D3V2MX-GP-U
DY
PC1020
12
SC10U6D3V2MX-GP-U
1V_CPU_CORE
4
PC1047
12
SC1U10V2KX-L1-GP
12
PC1023
SC22U6D3V3MX-L1-GP
12
PC1044
SC22U6D3V3MX-L1-GP
PC1006
12
SC10U6D3V2MX-GP-U
DY
20170308 DY
12
20170118 DY
0603 22u
PC1046
SC18P50V2JN-1-GP
DY
12
PC1024
SC22U6D3V3MX-L1-GP
12
PC1045
SC22U6D3V3MX-L1-GP
PC1007
12
SC10U6D3V2MX-GP-U
DY
3
1V_CPU_CORE
U22 0603 22uF *22 , 0402 10uF*11 , 1uF*1
U42 0603 22uF *4 , 0402 10uF*15
1D2V_S3
PC1009
12
SC10U6D3V2MX-GP-U
DY
20170118 DY
1D2V_S3
PC1025
12
SC10U6D3V2MX-GP-U
1V_CPU_CORE
12
1V_CPU_CORE
12
U42
1V_CPU_CORE
12
DY
PC10C1
SC10U6D3V2MX-GP-U
DY
20170124 DY
PC10D2
SC10U6D3V2MX-GP-U
PC10E4
SC22U6D3V3MX-L1-GP
PC1010
12
SC10U6D3V2MX-GP-U
PC1026
12
SC10U6D3V2MX-GP-U
12
12
U42
12
DY
PC10C2
SC10U6D3V2MX-GP-U
DY
PC10D3
SC10U6D3V2MX-GP-U
PC10E5
SC22U6D3V3MX-L1-GP
12
12
12
U42
12
U42
12
U42
PC1011
SC10U6D3V2MX-GP-U
PC1027
SC10U6D3V2MX-GP-U
PC10C3
SC10U6D3V2MX-GP-U
PC10D4
SC10U6D3V2MX-GP-U
PC10E6
SC22U6D3V3MX-L1-GP
PC1012
12
SC10U6D3V2MX-GP-U
PC1028
12
SC10U6D3V2MX-GP-U
For U42 power
PC10C4
12
SC10U6D3V2MX-GP-U
U42
PC10D5
12
SC10U6D3V2MX-GP-U
U42
PC10E7
12
SC22U6D3V3MX-L1-GP
U42
2
12
DY
20170118 DY
12
U42
U42
U42
PC1013
SC10U6D3V2MX-GP-U
PC1029
SC10U6D3V2MX-GP-U
PC10C5
12
SC10U6D3V2MX-GP-U
PC10D6
12
SC10U6D3V2MX-GP-U
PC10E8
12
SC10U6D3V2MX-GP-U
PC1014
12
SC10U6D3V2MX-GP-U
PC10E1
12
SC10U6D3V2MX-GP-U
12
U42
12
U42
12
U42
PC10C6
SC10U6D3V2MX-GP-U
PC10D7
SC10U6D3V2MX-GP-U
PC10E9
SC10U6D3V2MX-GP-U
PC1015
12
SC10U6D3V2MX-GP-U
PC10E2
12
SC10U6D3V2MX-GP-U
12
U42
20170118
12
DY
12
U42
PC10C7
SC10U6D3V2MX-GP-U
PC10D8
SC10U6D3V2MX-GP-U
PC10F1
SC10U6D3V2MX-GP-U
1D2V_S3
0402 10uF*13
PC1016
12
SC10U6D3V2MX-GP-U
PC10E3
12
SC10U6D3V2MX-GP-U
DY
20170118 DY
PC10D1
12
SC10U6D3V2MX-GP-U
DY
20170124 DY
PC10D9
12
SC10U6D3V2MX-GP-U
DY
20170124 DY
PC10F2
12
SC10U6D3V2MX-GP-U
U42
1
0603 22u
1V_VCCIO
10uF * 2 1uF *4
1V_VCCIO
PC1048
12
SC10U6D3V2MX-GP-U
2017/07/06 -1
PC1049
12
SC10U6D3V2MX-GP-U
PC1050
12
SC10U6D3V2MX-GP-U
PC1051
12
SC1U10V2KX-L1-GP
PC1052
12
SC1U10V2KX-L1-GP
PC1055
12
SC1U10V2KX-L1-GP
PC1056
12
SC1U10V2KX-L1-GP
20170118 DY
1V_VCCGT_C
PC10A7
12
SC10U6D3V2MX-GP-U
B B
A A
PC10A8
12
SC10U6D3V2MX-GP-U
5
PC10B2
12
SC22U6D3V3MX-L1-GP
20170118
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(Power CAP1)
CPU_(Power CAP1)
CPU_(Power CAP1)
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
10 106
10 106
10 106
-1M
-1M
-1M
of
Main Func = CPU
5
4
3
2
1
LICED GT
S
1V_VCCGT
12
D D
C C
1V_VCCGT
12
1V_VCCGT
12
1V_VCCGT
12
DY
1V_VCCGT
12
DY
1V_VCCGT
12
CLOSE CPU AB19 CLOSE CPU AF20CLOSE CPU K17
SC1U10V2KX-L1-GP
U-line 23e 28W
IccMax current-10ms max[A] = 67 A
PC1101
SC22U6D3V3MX-L1-GP
PC1167
SC22U6D3V3MX-L1-GP
PC1121
SC10U6D3V2MX-GP-U
PC1133
SC10U6D3V2MX-GP-U
PC1109
SC10U6D3V2MX-GP-U
PC1165
SC10U6D3V2MX-GP-U
1D0V_S5 1D0V_S5 1D0V_S5
12
PC1142
SC1U10V2KX-L1-GP
12
PC1102
SC22U6D3V3MX-L1-GP
12
PC10B3
SC22U6D3V3MX-L1-GP
12
PC1122
SC10U6D3V2MX-GP-U
12
PC1107
SC10U6D3V2MX-GP-U
12
PC1110
SC10U6D3V2MX-GP-U
DY
12
PC1166
SC10U6D3V2MX-GP-U
DY
SC1U10V2KX-L1-GP
12
PC1112
SC22U6D3V3MX-L1-GP
12
PC10B4
SC22U6D3V3MX-L1-GP
12
PC1123
SC10U6D3V2MX-GP-U
12
PC1108
SC10U6D3V2MX-GP-U
12
PC1111
SC10U6D3V2MX-GP-U
DY
12
PC1143
DY
SC1U10V2KX-L1-GP
CLOSE CPU AF18 CLOSE CPU N18
3D3V_S5
12
PC1153
SC1U10V2KX-L1-GP
3D3V_S5
3D3V_S5 3D3V_S5 3D3V_S5
12
PC1154
DY
SC1U10V2KX-L1-GP
0603 22u
12
PC1116
SC22U6D3V3MX-L1-GP
12
PC10B5
SC22U6D3V3MX-L1-GP
12
PC1124
SC10U6D3V2MX-GP-U
12
PC1136
SC10U6D3V2MX-GP-U
DY
12
PC1141
SC10U6D3V2MX-GP-U
DY
2017/07/06 -1
1D0V_S5 1D0V_S5
12
PC1144
SC1U10V2KX-L1-GP
CLOSE CPU N15
12
PC1155
SC1U10V2KX-L1-GP
DY
12
PC1134
SC22U6D3V3MX-L1-GP
12
PC10B6
SC22U6D3V3MX-L1-GP
12
PC1125
SC10U6D3V2MX-GP-U
12
PC1103
SC10U6D3V2MX-GP-U
12
PC1113
SC10U6D3V2MX-GP-U
12
12
SC22U6D3V5MX-L3-GP
PC1145
PC1146
12
PC1135
SC22U6D3V3MX-L1-GP
12
PC10B7
SC22U6D3V3MX-L1-GP
12
PC1126
SC10U6D3V2MX-GP-U
12
PC1104
SC10U6D3V2MX-GP-U
12
PC1114
SC10U6D3V2MX-GP-U
SC1U10V2KX-L1-GP
12
PC1147
CLOSE CPU K15
12
PC1156
DY
12
PC1157
SC1U10V2KX-L1-GP
DY
12
PC1137
SC22U6D3V3MX-L1-GP
12
PC1127
SC10U6D3V2MX-GP-U
DY
12
PC1105
SC10U6D3V2MX-GP-U
12
PC1115
SC10U6D3V2MX-GP-U
1D0V_S5
12
SC1U10V2KX-L1-GP
PC1148
3D3V_S5 3D3V_RTC_AUX
12
12
PC1159
PC1158
SCD1U25V2KX-L-GP
SC1U10V2KX-L1-GP
12
PC1138
SC22U6D3V3MX-L1-GP
12
PC1128
SC10U6D3V2MX-GP-U
DY
12
PC1168
SC10U6D3V2MX-GP-U
DY
12
PC1171
SC10U6D3V2MX-GP-U
1D0V_S5
SC1U10V2KX-L1-GP
12
PC1149
1D0V_S5
SC1U10V2KX-L1-GP
12
PC1150
DY
CLOSE CPU A10
12
12
PC1160
SC1U10V2KX-L1-GP
PC1161
SCD1U25V2KX-L-GP
1V_VCCGT
0603 22uF *14 , 0402 10uF*28
1V_VCCSA
2017/05/16 - SB
2017/05/19 - SB
1V_VCCSA
12
PC1172
SC10U6D3V2MX-GP-U
1V_VCCSA
12
1V_VCCSA
12
PC1139
SC10U6D3V2MX-GP-U
1D0V_VCCDSW
12
SC1U10V2KX-L1-GP
PC1129
SC22U6D3V3MX-L1-GP
PC1163
12
PC1173
SC10U6D3V2MX-GP-U
12
PC1130
SC22U6D3V3MX-L1-GP
12
VCCRTCEXT
12
SCD1U25V2KX-L-GP
CLOSE CPU AL1 CLOSE CPU BB10
1D8V_S5
12
PC1162
SC1U10V2KX-L1-GP
PC1170
SC10U6D3V2MX-GP-U
PC1164
12
12
PC1119
SC22U6D3V3MX-L1-GP
PC1131
SC22U6D3V3MX-L1-GP
12
PC1152
SC10U6D3V2MX-GP-U
0402 10uF*4
0603 22uF*6
12
PC1120
SC22U6D3V3MX-L1-GP
12
PC1132
SC22U6D3V3MX-L1-GP
20170118
12
PC1140
SC10U6D3V2MX-GP-U
B B
CLOSE CPU V19
CLOSE CPU AG15CLOSE CPU AJ19
CLOSE CPU Y16
CLOSE CPU AK17CLOSE CPU T16
CLOSE CPU AK19
CLOSE CPU AA1
2017/06/30 -1
1V_VCCGT
12
PC1183
SC10U6D3V2MX-GP-U
1V_VCCGT
12
PC1187
SC10U6D3V2MX-GP-U
1V_VCCSA
12
PC1198
SC10U6D3V2MX-GP-U
A A
1V_VCCSA
12
PC1117
SC10U6D3V2MX-GP-U
5
12
PC1174
SC10U6D3V2MX-GP-U
12
PC1177
SC10U6D3V2MX-GP-U
12
PC1197
SC10U6D3V2MX-GP-U
12
PC1118
SC10U6D3V2MX-GP-U
12
PC1182
SC10U6D3V2MX-GP-U
12
PC1180
SC10U6D3V2MX-GP-U
12
PC1199
SC10U6D3V2MX-GP-U
12
PC1151
SC10U6D3V2MX-GP-U
12
PC1179
SC10U6D3V2MX-GP-U
12
PC1188
SC10U6D3V2MX-GP-U
12
PC1106
SC10U6D3V2MX-GP-U
Modify by power Jason
2017/0630
4
12
PC1184
SC10U6D3V2MX-GP-U
12
PC1181
SC10U6D3V2MX-GP-U
12
PC1185
SC10U6D3V2MX-GP-U
12
PC1186
SC10U6D3V2MX-GP-U
12
PC1189
SC10U6D3V2MX-GP-U
12
PC1178
SC10U6D3V2MX-GP-U
12
PC1175
SC10U6D3V2MX-GP-U
12
PC1176
SC10U6D3V2MX-GP-U
Modify by power Jason
2017/0630
3
12
PC1190
SC10U6D3V2MX-GP-U
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(Power CAP2)
CPU_(Power CAP2)
CPU_(Power CAP2)
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
11 106
11 106
11 106
-1M
-1M
-1M
5
4
3
2
1
1D2V_S3
1D2V_S3
DY
FC1200
1 2
1D8V_DDR
1 2
DY
FC1201
SCD1U25V2KX-L-GP
U1201A
A3
VDD1
U3
VDD1
A4
VDD1
U4
VDD1
A5
VDD1
U5
VDD1
A6
VDD1
U6
VDD1
A10
VDD1
U10
VDD1
D4
VDD2
P4
VDD2
D5
VDD2
G5
VDD2
H5
VDD2
J5
VDD2
K5
VDD2
L5
VDD2
P5
VDD2
D6
VDD2
H6
VDD2
J6
VDD2
K6
VDD2
P6
VDD2
A8
VDD2
U8
VDD2
A9
VDD2
U9
VDD2
H12
VDD2
K12
VDD2
F2
VDDCA
G2
VDDCA
L2
VDDCA
M2
VDDCA
H3
VDDCA
E8
VDDQ
H8
VDDQ
K8
VDDQ
N8
VDDQ
H9
VDDQ
J9
VDDQ
J10
VDDQ
A11
VDDQ
H11
VDDQ
K11
VDDQ
U11
VDDQ
C12
VDDQ
E12
VDDQ
G12
VDDQ
L12
VDDQ
N12
VDDQ
R12
VDDQ
K4E6E304EE-EGCF-GP
1 OF 2
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Layout Note:Place Close U1201 between U1301
CHA/CHB_LPDDR3_VREFCA
V_DDR_CA_VREF4
1D2V_S3
12
R1210
1 2
R1212
10R2F-L-GP
2
8K2R2F-1-GP
12
R1211
8K2R2F-1-GP
M_VREF_DQ_SA
B2
H2
K2
T2
T3
E4
N4
R4
T4
B5
C5
E5
F5
M5
N5
R5
T5
L6
J12
C3
D3
G3
P3
F4
G4
J4
M4
B6
C6
E6
F6
G6
M6
N6
R6
T6
G9
L9
H10
K10
B12
D12
F12
M12
P12
T12
SCD1U25V2KX-L-GP
R1206
1 2
5D11R2F-GP
12
C1239
+V_VREF_RC3
SCD022U25V2KX-GP
12
R1207
24D9R2F-L-GP
Channel A
2 OF 2
M_A_CLK0
M_A_DQ[63:0]4
D D
C C
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_VREF_CA_DIMMA
M_VREF_DQ_SA
DQS
DATA
M_A_DQS_DP[7:0]4
M_A_DQS_DN[7:0]4
B B
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
CMD
M_A_CA_A[9:0]4
M_A_CA_B[9:0]4
M_A_CLK04
M_A_CLK#04
M_A_CLK14
M_A_CLK#14
A A
M_A_CKE04
M_A_CKE14
M_A_CKE24
M_A_CKE34
M_A_CS#04
M_A_CS#14
M_A_ODT04
CLK
CKE
CTRL
M_A_CA_A0
M_A_CA_A1
M_A_CA_A2
M_A_CA_A3
M_A_CA_A4
M_A_CA_A5
M_A_CA_A6
M_A_CA_A7
M_A_CA_A8
M_A_CA_A9
M_A_CA_B0
M_A_CA_B1
M_A_CA_B2
M_A_CA_B3
M_A_CA_B4
M_A_CA_B5
M_A_CA_B6
M_A_CA_B7
M_A_CA_B8
M_A_CA_B9
5
M_A_CLK#0
M_A_CKE0
M_A_CKE1
M_A_CS#0
M_A_CS#1
M_A_CA_A0
M_A_CA_A1
M_A_CA_A2
M_A_CA_A3
M_A_CA_A4
M_A_CA_A5
M_A_CA_A6
M_A_CA_A7
M_A_CA_A8
M_A_CA_A9
C1237
12
C1238
SCD047U16V2KX-1-GP
LPDDR3 DECAPS follow SkyLake U/Y PDG Table 4-58
Layout Note: Place these Caps near U1201
1D2V_S3
Q DECAPS VDD1 DECAPS VDD2 DECAPS
12
12
C1202
C1203
SC10U6D3V2MX-GP-U
SC10U6D3V2MX-GP-U
Layout Note: Place these Caps near U1202
VDDQ DECAPS
12
12
C1208
C1209
SC10U6D3V2MX-GP-U
SC10U6D3V2MX-GP-U
CHA TERMINATIONS
0D6V_VTT 0D6V_VTT
1 2
R1214 68R1J -GP
R1215 68R1J -GP
1 2
1 2
R1216 68R1J -GP
R1217 68R1J -GP
1 2
1 2
R1218 68R1J -GP
1 2
R1219 68R1J -GP
R1220 68R1J -GP
1 2
1 2
R1221 68R1J -GP
R1222 68R1J -GP
1 2
1 2
R1223 68R1J -GP
1 2
R1236 80D6R 1F-GP
R1237 80D6R 1F-GP
1 2
R1242 37D4R 2F-GP
1 2
1 2
R1243 37D4R 2F-GP
U1201B
J3
CK_T
J2
CK_C
K3
CKE0
K4
CKE1
L3
CS0#
L4
CS1#
R2
CA0
P2
CA1
N2
CA2
N3
CA3
M3
CA4
F3
CA5
E3
CA6
E2
CA7
D2
CA8
C2
CA9
L8
DM0
G8
DM1
P8
DM2
D8
DM3
H4
VREF_CA
J11
VREF_DQ
A1
DNU#A1
A2
12
DNU#A2
A12
DNU#A12
A13
DNU#A13
B1
DNU#B1
B13
DNU#B13
T1
DNU#T1
T13
DNU#T13
U1
SCD047U16V2KX-1-GP
DNU#U1
U2
DNU#U2
U12
DNU#U12
U13
DNU#U13
C4
NC#C4
K9
NC#K9
R3
NC#R3
K4E6E304EE-EGCF-GP
12
SCD1U10V1KX-GP
SCD1U10V1KX-GP
M_A_CA_A0
M_A_CA_A1
M_A_CA_A2
M_A_CA_A3
M_A_CA_A4
M_A_CA_A5
M_A_CA_A6
M_A_CA_A7
M_A_CA_A8
M_A_CA_A9
C1214
12
C1215
M_A_CKE0
M_A_CKE1
M_A_CLK0
M_A_CLK#0
12
SCD1U10V1KX-GP
SCD1U10V1KX-GP
12
C1223
SC1U10V2KX-L1-GP
12
C1224
SC1U10V2KX-L1-GP
M_A_DQ3
P9
DQ0
M_A_DQ7
N9
DQ1
M_A_DQ0
N10
DQ2
M_A_DQ5
N11
DQ3
M_A_DQ2
M8
DQ4
M_A_DQ6
M9
DQ5
M_A_DQ4
M10
DQ6
M_A_DQ1
M11
DQ7
M_A_DQ15
F11
DQ8
M_A_DQ10
F10
DQ9
M_A_DQ12
F9
DQ10
M_A_DQ9
F8
DQ11
M_A_DQ13
E11
DQ12
M_A_DQ14
E10
DQ13
M_A_DQ8
E9
DQ14
M_A_DQ11
D9
DQ15
M_A_DQ30
T8
DQ16
M_A_DQ26
T9
DQ17
M_A_DQ24
T10
DQ18
M_A_DQ28
T11
DQ19
M_A_DQ31
R8
DQ20
M_A_DQ27
R9
DQ21
M_A_DQ25
R10
DQ22
M_A_DQ29
R11
DQ23
M_A_DQ17
C11
DQ24
M_A_DQ16
C10
DQ25
M_A_DQ22
C9
DQ26
M_A_DQ18
C8
DQ27
M_A_DQ20
B11
DQ28
M_A_DQ21
B10
DQ29
M_A_DQ23
B9
DQ30
M_A_DQ19
B8
DQ31
M_A_DQS_DP0
L10
DQS0_T
M_A_DQS_DN0
L11
DQS0_C
M_A_DQS_DP1
G10
DQS1_T
M_A_DQS_DN1
G11
DQS1_C
M_A_DQS_DP3
P10
DQS2_T
M_A_DQS_DN3
P11
DQS2_C
M_A_DQS_DP2
D10
DQS3_T
M_A_DQS_DN2
D11
DQS3_C
CH_A_DRAM0_ZQ0
B3
ZQ0
CH_A_DRAM0_ZQ1
B4
ZQ1
M_A_ODT0
J8
ODT
1D8V_DDR 1D2V_S3
12
C1226
C1216
SC10U6D3V2MX-GP-U
1D8V_DDR 1D2V_S31D2V_S3
12
12
C1217
C1230
SC10U6D3V2MX-GP-U
R1224 68R1J -GP
R1225 68R1J -GP
R1227 68R1J -GP
R1226 68R1J -GP
R1229 68R1J -GP
R1228 68R1J -GP
R1231 68R1J -GP
R1230 68R1J -GP
R1233 68R1J -GP
R1232 68R1J -GP
R1238 80D6R 1F-GP
R1240 80D6R 1F-GP
R1244 37D4R 2F-GP
R1245 37D4R 2F-GP
4
DQ0
M_A_DQ[0:7]
DQ1
M_
DQ3
M_A_DQ[24:31]
DQ2
M_A_DQ[16:23]
M_A_DQS0
M_A_DQS1
M_A
M_A_DQS2
12
12
C1204
C1225
SC10U6D3V2MX-GP-U
SC10U6D3V2MX-GP-U
VDD1 DECAPS VDD2 DECAPS
12
12
C1210
C1231
SC10U6D3V2MX-GP-U
SC10U6D3V2MX-GP-U
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
A_DQ[8:15]
_DQS3
1 2
1 2
12
C1205
SC10U6D3V2MX-GP-U
12
SC10U6D3V2MX-GP-U
M_A_CA_B0
M_A_CA_B1
M_A_CA_B2
M_A_CA_B3
M_A_CA_B4
M_A_CA_B5
M_A_CA_B6
M_A_CA_B7
M_A_CA_B8
M_A_CA_B9
M_A_CKE2
M_A_CKE3
M_A_CLK1
M_A_CLK#1
C1211
M_VREF_CA_DIMMA
M_VREF_DQ_SA
R1202243R2F-2-GP
R1203243R2F-2-GP
12
12
C1227
C1228
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
12
12
C1233
C1234
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
M_A_CLK1
M_A_CLK#1
M_A_CKE2
M_A_CKE3
M_A_CS#0
M_A_CS#1
M_A_CA_B0
M_A_CA_B1
M_A_CA_B2
M_A_CA_B3
M_A_CA_B4
M_A_CA_B5
M_A_CA_B6
M_A_CA_B7
M_A_CA_B8
M_A_CA_B9
12
C1236
SCD047U16V2KX-1-GP
1D2V_S3
12
12
C1229
SC10U6D3V2MX-GP-U
SC1U10V2KX-L1-GP
1D2V_S3
12
12
C1232
SC10U6D3V2MX-GP-U
SC1U10V2KX-L1-GP
0D6V_VTT
R1234 80D6R 1F-GP
1 2
1 2
R1235 80D6R 1F-GP
1 2
R1241 80D6R 1F-GP
C1235
12
SCD047U16V2KX-1-GP
VDDCA DECAPSVDD
12
C1206
SC10U6D3V2MX-GP-U
VDDCA DECAPS
12
C1212
SC10U6D3V2MX-GP-U
3
C1207
C1213
M_A_CS#0
M_A_CS#1
M_A_ODT0
J3
J2
K3
K4
L3
L4
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
L8
G8
P8
D8
H4
J11
A1
A2
A12
A13
B1
B13
T1
T13
U1
U2
U12
U13
C4
K9
R3
U1202B
CK_T
CK_C
CKE0
CKE1
CS0#
CS1#
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
DM0
DM1
DM2
DM3
VREF_CA
VREF_DQ
DNU#A1
DNU#A2
DNU#A12
DNU#A13
DQS0_T
DNU#B1
DQS0_C
DNU#B13
DQS1_T
DNU#T1
DQS1_C
DNU#T13
DQS2_T
DQS2_C
DNU#U1
DQS3_T
DNU#U2
DQS3_C
DNU#U12
DNU#U13
NC#C4
NC#K9
NC#R3
K4E6E304EE-EGCF-GP
2 OF 2
M_A_DQ34
P9
DQ0
M_A_DQ38
N9
DQ1
M_A_DQ36
N10
DQ2
M_A_DQ33
N11
DQ3
M_A_DQ35
M8
DQ4
M_A_DQ39
M9
DQ5
M_A_DQ32
M10
DQ6
M_A_DQ37
M11
DQ7
M_A_DQ46
F11
DQ8
M_A_DQ43
F10
DQ9
M_A_DQ44
F9
DQ10
M_A_DQ41
F8
DQ11
M_A_DQ47
E11
DQ12
M_A_DQ42
E10
DQ13
M_A_DQ45
E9
DQ14
M_A_DQ40
D9
DQ15
M_A_DQ52
T8
DQ16
M_A_DQ48
T9
DQ17
M_A_DQ55
T10
DQ18
M_A_DQ54
T11
DQ19
M_A_DQ53
R8
DQ20
M_A_DQ49
R9
DQ21
M_A_DQ51
R10
DQ22
M_A_DQ50
R11
DQ23
M_A_DQ60
C11
DQ24
M_A_DQ57
C10
DQ25
M_A_DQ63
C9
DQ26
M_A_DQ58
C8
DQ27
M_A_DQ61
B11
DQ28
M_A_DQ56
B10
DQ29
M_A_DQ62
B9
DQ30
M_A_DQ59
B8
DQ31
M_A_DQS_DP4
L10
M_A_DQS_DN4
L11
M_A_DQS_DP5
G10
M_A_DQS_DN5
G11
M_A_DQS_DP6
P10
M_A_DQS_DN6
P11
M_A_DQS_DP7
D10
M_A_DQS_DN7
D11
CH_A_DRAM1_ZQ0
B3
ZQ0
CH_A_DRAM1_ZQ1
B4
ZQ1
M_A_ODT0
J8
ODT
Layout Note: Place these Caps
nea
r CHA Terminations
0D6V_VTT 0D6V_VTT 0D6V_VTT
12
12
C1243
C1242
C1241
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VTT
SC1U6D3V2KX-GP
DECAPS
12
C1244
DQ4
M_A_DQ[32:39]
DQ5
M_A_DQ[40:47]
DQ6
M_A_DQ[48:55]
DQ7
M_A_DQ[56:63]
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
12
SC1U6D3V2KX-GP
C1246
1 2
1 2
SC22U6D3V3MX-1-GP
Layout Note:Place Close U1201
CHA_LPDDR3_VREFDQ
DDR_VREFDQ01_C HA4
R1204243R2F-2-GP
R1205243R2F-2-GP
SCD1U25V2KX-L-GP
12
12
C1245
SC1U6D3V2KX-GP
12
C1240
+V_VREF_RC1
SCD022U25V2KX-GP
12
R1213
24D9R2F-L-GP
1D8V_DDR
1D2V_S3
1D2V_S3
1D2V_S31D2V_S3
DY
DY
FC1202
FC1203
SCD1U25V2KX-L-GP
1 2
1 2
1D2V_S3
12
R1209
8K2R2F-1-GP
12
R1208
8K2R2F-1-GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LPDDR3_CHA
LPDDR3_CHA
LPDDR3_CHA
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
1 OF 2
U1202A
A3
VDD1
VSS
U3
VDD1
VSS
A4
VDD1
VSS
U4
VDD1
VSS
A5
VDD1
VSS
U5
VDD1
VSS
A6
VDD1
VSS
U6
VDD1
A10
U10
H12
K12
J10
A11
H11
K11
U11
C12
E12
G12
L12
N12
R12
VSS
VDD1
VSS
VDD1
VSS
VSS
D4
VDD2
VSS
P4
VDD2
VSS
D5
VDD2
VSS
G5
VDD2
VSS
H5
VDD2
VSS
J5
VDD2
VSS
K5
VDD2
VSS
L5
VDD2
VSS
P5
VDD2
D6
VDD2
H6
VDD2
VSSCA
J6
VDD2
VSSCA
K6
VDD2
VSSCA
P6
VDD2
VSSCA
A8
VDD2
VSSCA
U8
VDD2
VSSCA
A9
VDD2
VSSCA
U9
VDD2
VSSCA
VDD2
VDD2
VSSQ
F2
VDDCA
VSSQ
G2
VDDCA
VSSQ
L2
VDDCA
VSSQ
M2
VDDCA
VSSQ
H3
VDDCA
VSSQ
VSSQ
E8
VDDQ
VSSQ
H8
VDDQ
VSSQ
K8
VDDQ
VSSQ
N8
VDDQ
VSSQ
H9
VDDQ
VSSQ
J9
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
K4E6E304EE-EGCF-GP
M_VREF_CA_DIMMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
12 106Wednesday, November 01, 2017
12 106Wednesday, November 01, 2017
12 106Wednesday, November 01, 2017
B2
H2
K2
T2
T3
E4
N4
R4
T4
B5
C5
E5
F5
M5
N5
R5
T5
L6
J12
C3
D3
G3
P3
F4
G4
J4
M4
B6
C6
E6
F6
G6
M6
N6
R6
T6
G9
L9
H10
K10
B12
D12
F12
M12
P12
T12
-1M
-1M
-1M
5
4
3
2
1
Channel B
M_B_DQ[63:0]5
D D
C C
M_B_DQS_DP[7:0]5
M_B_DQS_DN[7:0]5
M_B_CA_A[9:0]5
B B
M_B_CA_B[9:0]5
A A
DATA
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
DQS
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
CMD
M_B_CA_A0
M_B_CA_A1
M_B_CA_A2
M_B_CA_A3
M_B_CA_A4
M_B_CA_A5
M_B_CA_A6
M_B_CA_A7
M_B_CA_A8
M_B_CA_A9
M_B_CA_B0
M_B_CA_B1
M_B_CA_B2
M_B_CA_B3
M_B_CA_B4
M_B_CA_B5
M_B_CA_B6
M_B_CA_B7
M_B_CA_B8
M_B_CA_B9
CLK
M_B_CLK05
M_B_CLK#05
M_B_CLK15
M_B_CLK#15
CKE
M_B_CKE05
M_B_CKE15
M_B_CKE25
M_B_CKE35
CTRL
M_B_CS#05
M_B_CS#15
M_B_ODT05
5
M_VREF_CA_DIMMA
M_VREF_DQ_SB
C1335
12
M_B_CLK0
M_B_CLK#0
M_B_CKE0
M_B_CKE1
M_B_CS#0
M_B_CS#1
M_B_CA_A0
M_B_CA_A1
M_B_CA_A2
M_B_CA_A3
M_B_CA_A4
M_B_CA_A5
M_B_CA_A6
M_B_CA_A7
M_B_CA_A8
M_B_CA_A9
SCD047U16V2KX-1-GP
C1336
J3
J2
K3
K4
L3
L4
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
L8
G8
P8
D8
H4
J11
A1
A2
A12
A13
12
B1
B13
T1
T13
U1
U2
U12
SCD047U16V2KX-1-GP
U13
C4
K9
R3
LPDDR3 DECAPS follow SkyLake U/Y PDG Table 4-58
Layout Note: Place these Caps near U1301
12
12
C1302
C1303
SC10U6D3V2MX-GP-U
SC10U6D3V2MX-GP-U
Layout Note: Place these Caps near U1302
1D2V_S3
VDDQ DECAPS
12
12
C1308
C1309
SC10U6D3V2MX-GP-U
CHB TERMINATIONS
0D6V_VTT
R1313 68R1J -GP
R1314 68R1J -GP
R1315 68R1J -GP
R1316 68R1J -GP
R1317 68R1J -GP
R1318 68R1J -GP
R1319 68R1J -GP
R1320 68R1J -GP
R1321 68R1J -GP
R1322 68R1J -GP
R1333 80D6R 1F-GP
R1334 80D6R 1F-GP
R1340 37D4R 2F-GP
R1341 37D4R 2F-GP
SC10U6D3V2MX-GP-U
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
SC1U10V2KX-L1-GP
U1301B
CK_T
CK_C
CKE0
CKE1
CS0#
CS1#
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
DM0
DM1
DM2
DM3
VREF_CA
VREF_DQ
DNU#A1
DNU#A2
DNU#A12
DNU#A13
DNU#B1
DNU#B13
DNU#T1
DNU#T13
DNU#U1
DNU#U2
DNU#U12
DNU#U13
NC#C4
NC#K9
NC#R3
K4E6E304EE-EGCF-GP
12
C1328
SC1U10V2KX-L1-GP
12
C1334
SCD1U10V1KX-GP
M_B_CA_A0
M_B_CA_A1
M_B_CA_A2
M_B_CA_A3
M_B_CA_A4
M_B_CA_A5
M_B_CA_A6
M_B_CA_A7
M_B_CA_A8
M_B_CA_A9
M_B_CKE0
M_B_CKE1
M_B_CLK0
M_B_CLK#0
2 OF 2
M_B_DQ14
P9
DQ0
M_B_DQ15
N9
DQ1
M_B_DQ8
N10
DQ2
M_B_DQ13
N11
DQ3
M_B_DQ11
M8
DQ4
M_B_DQ10
M9
DQ5
M_B_DQ9
M10
DQ6
M_B_DQ12
M11
DQ7
M_B_DQ3
F11
DQ8
M_B_DQ4
F10
DQ9
M_B_DQ1
F9
DQ10
M_B_DQ0
F8
DQ11
M_B_DQ7
E11
DQ12
M_B_DQ6
E10
DQ13
M_B_DQ2
E9
DQ14
M_B_DQ5
D9
DQ15
M_B_DQ21
T8
DQ16
M_B_DQ17
T9
DQ17
M_B_DQ23
T10
DQ18
M_B_DQ19
T11
DQ19
M_B_DQ20
R8
DQ20
M_B_DQ16
R9
DQ21
M_B_DQ22
R10
DQ22
M_B_DQ18
R11
DQ23
M_B_DQ29
C11
DQ24
M_B_DQ25
C10
DQ25
M_B_DQ31
C9
DQ26
M_B_DQ27
C8
DQ27
M_B_DQ28
B11
DQ28
M_B_DQ24
B10
DQ29
M_B_DQ26
B9
DQ30
M_B_DQ30
B8
DQ31
M_B_DQS_DP1
L10
DQS0_T
DQS0_C
DQS1_T
DQS1_C
DQS2_T
DQS2_C
DQS3_T
DQS3_C
12
C1314
SCD1U10V1KX-GP
12
C1315
M_B_DQS_DN1
L11
M_B_DQS_DP0
G10
M_B_DQS_DN0
G11
M_B_DQS_DP2
P10
M_B_DQS_DN2
P11
M_B_DQS_DP3
D10
M_B_DQS_DN3
D11
CH_B_DRAM0_ZQ0
B3
ZQ0
CH_B_DRAM0_ZQ1
B4
ZQ1
M_B_ODT0
J8
ODT
12
C1316
SCD1U10V1KX-GP
12
C1317
SCD1U10V1KX-GP
4
DQ1
M
_B_DQ[8:15]
DQ0
M_B_DQ[0:7]
DQ2
M_B_DQ[16:23]
DQ3
M_B_DQ[24:31]
M_B_DQS1
M_B_DQS0
M_B_DQS2
B_DQS3
M_
1 2
1 2
1D8V_DDR 1D2V_S31D2V_S3
12
C1323
SC10U6D3V2MX-GP-U
1D8V_DDR 1D2V_S3
12
C1329
SC10U6D3V2MX-GP-U
0D6V_VTT
R1323 68R1J -GP
R1324 68R1J -GP
R1325 68R1J -GP
R1326 68R1J -GP
R1327 68R1J -GP
R1328 68R1J -GP
R1330 68R1J -GP
R1329 68R1J -GP
R1331 68R1J -GP
R1332 68R1J -GP
R1335 80D6R 1F-GP
R1336 80D6R 1F-GP
R1342 37D4R 2F-GP
R1343 37D4R 2F-GP
12
12
C1304
C1324
SC10U6D3V2MX-GP-U
SC10U6D3V2MX-GP-U
VDD1 DECAPS VDD2 DECAPS
12
12
C1310
C1330
SC10U6D3V2MX-GP-U
SC10U6D3V2MX-GP-U
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R1301243R2F-2-GP
R1302243R2F-2-GP
12
SC10U6D3V2MX-GP-U
12
SC10U6D3V2MX-GP-U
M_B_CA_B0
M_B_CA_B1
M_B_CA_B2
M_B_CA_B3
M_B_CA_B4
M_B_CA_B5
M_B_CA_B6
M_B_CA_B7
M_B_CA_B8
M_B_CA_B9
M_B_CKE2
M_B_CKE3
M_B_CLK1
M_B_CLK#1
C1305
C1311
M_VREF_CA_DIMMA
M_VREF_DQ_SB
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
12
C1326
12
C1332
M_B_CLK1
M_B_CLK#1
M_B_CKE2
M_B_CKE3
M_B_CS#0
M_B_CS#1
M_B_CA_B0
M_B_CA_B1
M_B_CA_B2
M_B_CA_B3
M_B_CA_B4
M_B_CA_B5
M_B_CA_B6
M_B_CA_B7
M_B_CA_B8
M_B_CA_B9
C1338
12
12
C1337
SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
12
12
C1325
C1327
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
12
12
C1331
C1333
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
0D6V_VTT
1 2
R1337 80D6R 1F-GP
1 2
R1338 80D6R 1F-GP
R1339 80D6R 1F-GP
1 2
J11
A12
A13
B13
T13
U12
U13
1D2V_S3
SC10U6D3V2MX-GP-U
1D2V_S3
SC10U6D3V2MX-GP-U
J3
J2
K3
K4
L3
L4
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
L8
G8
P8
D8
H4
A1
A2
B1
T1
U1
U2
C4
K9
R3
U1302B
CK_T
CK_C
CKE0
CKE1
CS0#
CS1#
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
DM0
DM1
DM2
DM3
VREF_CA
VREF_DQ
DNU#A1
DNU#A2
DNU#A12
DNU#A13
DNU#B1
DNU#B13
DNU#T1
DNU#T13
DNU#U1
DNU#U2
DNU#U12
DNU#U13
NC#C4
NC#K9
NC#R3
K4E6E304EE-EGCF-GP
VDDCA DECAPSVDDQ DECAPS VDD1 DECAPS VDD2 DECAPS
12
C1306
SC10U6D3V2MX-GP-U
VDDCA DECAPS
12
C1312
SC10U6D3V2MX-GP-U
M_B_CS#0
M_B_CS#1
M_B_ODT0
3
2 OF 2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS0_T
DQS0_C
DQS1_T
DQS1_C
DQS2_T
DQS2_C
DQS3_T
DQS3_C
ZQ0
ZQ1
ODT
12
C1307
12
C1313
M_B_DQ51
P9
M_B_DQ50
N9
M_B_DQ49
N10
M_B_DQ53
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
L10
L11
G10
G11
P10
P11
D10
D11
B3
B4
J8
M_B_DQ54
M_B_DQ55
M_B_DQ48
M_B_DQ52
M_B_DQ42
M_B_DQ43
M_B_DQ41
M_B_DQ45
M_B_DQ47
M_B_DQ46
M_B_DQ40
M_B_DQ44
M_B_DQ33
M_B_DQ36
M_B_DQ32
M_B_DQ38
M_B_DQ34
M_B_DQ37
M_B_DQ35
M_B_DQ39
M_B_DQ61
M_B_DQ60
M_B_DQ58
M_B_DQ63
M_B_DQ56
M_B_DQ57
M_B_DQ59
M_B_DQ62
M_B_DQS_DP6
M_B_DQS_DN6
M_B_DQS_DP5
M_B_DQS_DN5
M_B_DQS_DP4
M_B_DQS_DN4
M_B_DQS_DP7
M_B_DQS_DN7
CH_B_DRAM1_ZQ0
CH_B_DRAM1_ZQ1
M_B_ODT0
DQ6
M_B_DQ[48:55]
DQ
M_B_DQ[40:47]
DQ4
M_B_DQ[32:39]
DQ7
M_B_DQ[56:63]
M_B_DQS6
M_B_DQS5
M_B_DQS4
M_B_DQS7
Layout Note: Place these Caps
ne
ar CHB Terminations
0D6V_VTT 0D6V_VTT 0D6V_VTT
12
12
C1342
C1341
C1340
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
5
1 2
1 2
T DECAPS
VT
12
C1343
SC1U6D3V2KX-GP
DY
R1303243R2F-2-GP
R1304243R2F-2-GP
12
C1345
SC1U6D3V2KX-GP
FC1300
12
C1344
SC22U6D3V3MX-1-GP
SC1U6D3V2KX-GP
1D8V_DDR
1D2V_S3
1D2V_S3
DY
FC1301
SCD1U25V2KX-L-GP
1 2
1 2
SCD1U25V2KX-L-GP
U1301A
A3
VDD1
U3
VDD1
A4
VDD1
U4
VDD1
A5
VDD1
U5
VDD1
A6
VDD1
U6
VDD1
A10
VDD1
U10
VDD1
D4
VDD2
P4
VDD2
D5
VDD2
G5
VDD2
H5
VDD2
J5
VDD2
K5
VDD2
L5
VDD2
P5
VDD2
D6
VDD2
H6
VDD2
J6
VDD2
K6
VDD2
P6
VDD2
A8
VDD2
U8
VDD2
A9
VDD2
U9
VDD2
H12
VDD2
K12
VDD2
F2
VDDCA
G2
VDDCA
L2
VDDCA
M2
VDDCA
H3
VDDCA
E8
VDDQ
H8
VDDQ
K8
VDDQ
N8
VDDQ
H9
VDDQ
J9
VDDQ
J10
VDDQ
A11
VDDQ
H11
VDDQ
K11
VDDQ
U11
VDDQ
C12
VDDQ
E12
VDDQ
G12
VDDQ
L12
VDDQ
N12
VDDQ
R12
VDDQ
K4E6E304EE-EGCF-GP
1 OF 2
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
VSS
H2
VSS
K2
VSS
T2
VSS
T3
VSS
E4
VSS
N4
VSS
R4
VSS
T4
VSS
B5
VSS
C5
VSS
E5
VSS
F5
VSS
M5
VSS
N5
VSS
R5
VSS
T5
VSS
L6
VSS
J12
VSS
C3
D3
G3
P3
F4
G4
J4
M4
B6
C6
E6
F6
G6
M6
N6
R6
T6
G9
L9
H10
K10
B12
D12
F12
M12
P12
T12
FC1303
1D2V_S31D2V_S3
DY
SCD1U25V2KX-L-GP
1D2V_S3
1 2
1 2
1D2V_S3
DY
FC1302
SCD1U25V2KX-L-GP
1D8V_DDR
U1302A
A3
VDD1
U3
VDD1
A4
VDD1
U4
VDD1
A5
VDD1
U5
VDD1
A6
VDD1
U6
VDD1
A10
VDD1
U10
VDD1
D4
VDD2
P4
VDD2
D5
VDD2
G5
VDD2
H5
VDD2
J5
VDD2
K5
VDD2
L5
VDD2
P5
VDD2
D6
VDD2
H6
VDD2
J6
VDD2
K6
VDD2
P6
VDD2
A8
VDD2
U8
VDD2
A9
VDD2
U9
VDD2
H12
VDD2
K12
VDD2
F2
VDDCA
G2
VDDCA
L2
VDDCA
M2
VDDCA
H3
VDDCA
E8
VDDQ
H8
VDDQ
K8
VDDQ
N8
VDDQ
H9
VDDQ
J9
VDDQ
J10
VDDQ
A11
VDDQ
H11
VDDQ
K11
VDDQ
U11
VDDQ
C12
VDDQ
E12
VDDQ
G12
VDDQ
L12
VDDQ
N12
VDDQ
R12
VDDQ
K4E6E304EE-EGCF-GP
1 OF 2
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSCA
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
VSS
H2
VSS
K2
VSS
T2
VSS
T3
VSS
E4
VSS
N4
VSS
R4
VSS
T4
VSS
B5
VSS
C5
VSS
E5
VSS
F5
VSS
M5
VSS
N5
VSS
R5
VSS
T5
VSS
L6
VSS
J12
VSS
C3
D3
G3
P3
F4
G4
J4
M4
B6
C6
E6
F6
G6
M6
N6
R6
T6
G9
L9
H10
K10
B12
D12
F12
M12
P12
T12
Layout Note:Place Close U1301
12
2
CHB_LPDDR3_VREFDQ
DDR_VREFDQ02_C HB4
12
+V_VREF_RC2
SCD022U25V2KX-GP
12
24D9R2F-L-GP
1D2V_S3
12
R1309
8K2R2F-1-GP
R1311
1 2
10R2F-L-GP
12
C1339
R1312
R1310
8K2R2F-1-GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
M_VREF_DQ_SB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LPDDR3_CHB
LPDDR3_CHB
LPDDR3_CHB
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
-1M
-1M
13 106Wednesday, November 01, 2017
13 106Wednesday, November 01, 2017
13 106Wednesday, November 01, 2017
-1M
SSID = STRAP
5
STRAP RESISTORS SHOULD BE PLACED CLOSE TO SOC
SHOULD BE PLACED OUTSIDE KOZ AREA
4
3
2
1
D D
Description
GPIO
Schematic
High
Low
Display Port
B Detected
GPP_E19
3D3V_S0
4
RN1401
SRN2K2J-5-GP
1
2 3
Detected
t Detected
No
HDMI_DATA_CPU 3,57
HDMI_CLK_CPU 3,57
internal pull-down internal pull-down internal pull-down internal pull-down internal pull-down
C C
Description
Top Swap
rride
Ove
GPIO GPP_B14
3D3V_S0 3D3V_S5
12
R1415
1KR2J-L2-GP
Schematic
High
Low
DY
HDA_SPKR 17,27 SPI_SI_CPU 18 GPP_C5/SML0ALERT# 18 GPP_B23/SML1ALERT# 18
Enable
Disable
internal pull-down internal pull-down
Display Port
C
Detected
GPP_E21
3D3V_S0
12
R1401
2K2R2J-2-GP
Detected
t Detected
No
DDPC_CTRLDATA 3
3D3V_S5
R1441
10KR2J-3-GP
DY
1 2
Not Detected
Reserved
SPI0_MISO
SPI_SO_CPU 18
Detected
No reboot
GPP_B18
3D3V_S0 3D3V_S0
12
R1407
1KR2J-L2-GP
DY
GPP_B18/GSPI0_MOSI 6 GPP_B22/GSPI1_MOSI 6
Enable
Disable
internal pull-up
Reserved Reserved Reserved
SPI0_MOSI
R1435
10KR2J-3-GP
DY
1 2
internal pull-up internal pull-up internal pull-up internal pull-down
SPI0_IO2 SPI0_IO3
3D3V_S5
1
23
20170302 change
RN1402
SRN1KJ-7-GP
4
SPI_WP_ROM_R 25
SPI_HOLD_ROM_R 25
Bo
ot BIOS
strap bit BBS
GPP_B22
12
R1408
1KR2J-L2-GP
DY
LPC
SPI
TLS Confidentiality
GPP_C2
3D3V_S5
R1438
10KR2J-3-GP
DY
1 2
GPP_C2/SMBALERT# 18
Enable
Disable
internal pull-down
Fl
ash descriptor
security override
HDA_SDO
sable
Di
Enable
internal pull-down
eSPI or LPC
GPP_C5
3D3V_S5 3D3V_S5
R1439
10KR2J-3-GP
DY
1 2
eSPI
LPC
Display Port
D
Detected
GPP_E23
3D3V_S0
R1443
10KR2J-3-GP
DY
1 2
Not Detected
Reserved
GPP_B23
R1440
150KR2J-GP
DY
1 2
De
DDPD_CDA 3
tected
B B
A A
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
(Reserved)_SODIMM _SODIMM4
(Reserved)_SODIMM _SODIMM4
(Reserved)_SODIMM _SODIMM4
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
A1
A1
A1
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
14 106
14 106
14 106
-1M
-1M
-1M
Main Func = PCH
5
USB1_USB30_RX_N35
USB1_USB30_RX_P35
USB1_USB30_TX_N35
USB1_USB30_TX_P35
USB1_USB20_N35
USB1_USB20_P35
USB2_USB30_RX_N35
D D
USB2_USB30_RX_P35
USB2_USB30_TX_N35
USB2_USB30_TX_P35
USB2_USB20_N36
USB2_USB20_P36
USB30_RX_CPU_N373
USB30_RX_CPU_P373
USB30_TX_CPU_N373
USB30_TX_CPU_P373
TYPEC_USB20_N73
TYPEC_USB20_P73
C C
PCIE_RX_CPU_N962
PCIE_RX_CPU_P962
PCIE_TX_CON_N962
PCIE_TX_CON_P962
PCIE_RX_CPU_N1062
PCIE_RX_CPU_P1062
PCIE_TX_CON_N1062
PCIE_TX_CON_P1062
PCIE_RX_CPU_N1162
PCIE_RX_CPU_P1162
PCIE_TX_CON_N1162
PCIE_TX_CON_P1162
PCIE_RX_CPU_N1262
PCIE_RX_CPU_P1262
PCIE_TX_CON_N1262
PCIE_TX_CON_P1262
USB3 port1
USB3 port2
WLAN_PCIE_RX_N
WLAN_PCIE_RX_P
WLAN_PCIE_TX_N
WLAN
WLAN_PCIE_TX_P
USB Type-C
USB2.0
BT_USB20_N61,89
BT_USB20_P61,89
TS_USB20_N55
TS_USB20_P55
CCD_USB20_N55
CCD_USB20_P55
FP_USB20_N92
FP_USB20_P92
M.2 SSD1
DEVSLP163
SSD1_PEDET62
Layout Note:
1. Trace Width : 4 mils min
breakout) 12-1 5 mils
(
(trace)
Note: Must mai ntain low DC
resistance rou ting (<0.1
ohm).
2. Isolation S pacing: At
least 12 mils to any
adjacent
high speed I/O .
4
1 2
C1520 SCD22U10V2KX-L1-GP
1 2
C1519 SCD22U10V2KX-L1-GP
M.2 SSD2
M.2 SSD1
1 2
R1504 100R2F-L3-GP
TPAD14-OP-GP
TPAD14-OP-GP
TP1511
TP1501
M.2 SSD1
1
1
WLAN_PCIE_TX_N_C
WLAN_PCIE_TX_P_C
PCIE_RX_CPU_N5
PCIE_RX_CPU_P5
PCIE_TX_CON_N5
PCIE_TX_CON_P5
PCIE_RX_CPU_N6
PCIE_RX_CPU_P6
PCIE_TX_CON_N6
PCIE_TX_CON_P6
PCIE_RX_CPU_N7
PCIE_RX_CPU_P7
PCIE_TX_CON_N7
PCIE_TX_CON_P7
PCIE_RX_CPU_N8
PCIE_RX_CPU_P8
PCIE_TX_CON_N8
PCIE_TX_CON_P8
PCIE_RX_CPU_N9
PCIE_RX_CPU_P9
PCIE_TX_CON_N9
PCIE_TX_CON_P9
PCIE_RX_CPU_N10
PCIE_RX_CPU_P10
PCIE_TX_CON_N10
PCIE_TX_CON_P10
PEG_RCOMPN_CPU
PEG_RCOMPP_CPU
XDP_PRDY#
XDP_PREQ#
PIRQA#
PCIE_RX_CPU_N11
PCIE_RX_CPU_P11
PCIE_TX_CON_N11
PCIE_TX_CON_P11
PCIE_RX_CPU_N12
PCIE_RX_CPU_P12
PCIE_TX_CON_N12
PCIE_TX_CON_P12
CPU1H
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKYLAKE-U-GP
071.SKYLA.000U
CPU
SKYLAKE_ULT
3
SSIC / USB3
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2
USB2_COMP
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
8 OF 20
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_ID
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USB1_USB30_RX_N
USB1_USB30_RX_P
USB1_USB30_TX_N
USB1_USB30_TX_P
USB2_USB30_RX_N
USB2_USB30_RX_P
USB2_USB30_TX_N
USB2_USB30_TX_P
USB30_RX_CPU_N3
USB30_RX_CPU_P3
USB30_TX_CPU_N3
USB30_TX_CPU_P3
USB1_USB20_N
USB1_USB20_P
USB2_USB20_N
USB2_USB20_P
TYPEC_USB20_N
TYPEC_USB20_P
BT_USB20_N
BT_USB20_P
TS_USB20_N
TS_USB20_P
CCD_USB20_N
CCD_USB20_P
FP_USB20_N
FP_USB20_P
USBCOMP
USBID
USBVSEN
DEVSLP1
DEVSLP2
SATAGP0
SATAGP1
SATAGP2
2
USB1(USB 3.0)
USB2(USB 3.0)
USB3(Type-C)
USB1(USB 2.0) --FOR USB 3.0
USB2(USB 2.0- CHARGE) --FOR USB 3.0
USB2(Type-C)
BT
Touch Panel
CCD
FP
R1503
1 2
113R2F-GP
USB_OC#
R1502
10KR2F-L1-GP
1 2
C1525
DY
SCD1U25V2KX-L-GP
1 2
3D3V_S5
SSD1 Auto Detection
SATAGP2
SSD2 Auto Detection
SATAGP1
1
USBID
USBVSEN
SATAGP0
PIRQA#
SATAGP1
SATAGP2
Q1501
D
2N7002K-2-GP
84.2N702.J31
2ND = 084.27002.0L31
Q1502
D
2N7002K-2-GP
84.2N702.J31
2ND = 084.27002.0L31
G
S
G
S
RN1506
1
2 3
SRN1KJ-7-GP
RN1505
1
2
3
4 5
SRN10KJ-12-GP
SSD1_PEDET
SSD2_PEDET
4
3D3V_S0
8
7
6
M
.2 SSD2
PCIE_RX_CPU_N563
PCIE_RX_CPU_P563
PCIE_TX_CON_N563
PCIE_TX_CON_P563
B B
PCIE_RX_CPU_N663
PCIE_RX_CPU_P663
PCIE_TX_CON_N663
PCIE_TX_CON_P663
PCIE_RX_CPU_N763
PCIE_RX_CPU_P763
PCIE_TX_CON_N763
PCIE_TX_CON_P763
PCIE_RX_CPU_N863
PCIE_RX_CPU_P863
PCIE_TX_CON_N863
PCIE_TX_CON_P863
DEVSLP262
SSD2_PEDET63
WLAN
WLAN_PCIE_RX_N61,89
WLAN_PCIE_RX_P61,89
WLAN_PCIE_TX_N61,89
WLAN_PCIE_TX_P61,89
A A
5
4
3
CPU1I
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
SKYLAKE-U-GP
SKYLAKE_ULT
CSI-2
1.8V Only
CPU
2
9 OF 20
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
C37
D37
C32
D32
C29
D29
B26
A26
CSI2_COMP
E13
B7
AP2
AP1
AP3
AN3
G
AN1
AN2
AM4
AM1
AM2
AM3
AP4
EMMC_RCOMP
AT1
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 2
R1501 100R2F-L1-GP-U
PP_F: VCCPGPPF = 1.8V Only
1 2
R1510 200R2F-L-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(PCIE/SATA/USB)
CPU_(PCIE/SATA/USB)
CPU_(PCIE/SATA/USB)
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
15 106
15 106
15 106
-1M
-1M
-1M
5
Main Func = PCH
WLAN_CLK_CPU#61,89
D D
C C
B B
WLAN_CLK_CPU61,89
WLAN_CLKREQ_CPU#61,89
SSD1_CLK_CPU_N62
SSD1_CLK_CPU_P62
SSD1_CLKREQ_CPU_N62
SSD2_CLK_CPU_N63
SSD2_CLK_CPU_P63
SSD2_CLKREQ_CPU_N63
RTCRST_ON24
SUS_CLK_CPU61
WLAN
SSD1
SSD2
KBC
WLAN
WLAN
SSD1
SSD2
RTCRST_ON
100KR2F-L3-GP
4
PEG_CLKREQ_CPU#
LAN_CLKREQ_CPU#
WLAN_CLK_CPU#
WLAN_CLK_CPU
WLAN_CLKREQ_CPU#
SSD1_CLK_CPU_N
SSD1_CLK_CPU_P
SSD1_CLKREQ_CPU_N
SSD2_CLK_CPU_N
SSD2_CLK_CPU_P
SSD2_CLKREQ_CPU_N
SRCCLKREQ5#
CPU
For AFR
12
R1618
CPU1J
D42
C42
AR10
B42
A42
AT7
D41
C41
AT8
D40
C40
AT10
B40
A40
AU8
E40
E38
AU7
SKYLAKE-U-GP
RTC_RST#_R
12
R1621
2K2R2J-L1-GP
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1#
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2#
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3#
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4#
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#
Q1603
G
S
2N7002K-2-GP
84.2N702.J31
2ND = 084.27002.0L31
D
CLOCK SIGNALS
SKYLAKE_ULT
RTC_RST#
3
10 OF 20
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
XTL_32K_X1_CPU
XTL_32K_X2_CPU
C1603
SC15P50V2JN-L-GP
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
RTC Reset
12
SUS_CLK_CPU
XTL_24M_X1_CPU
XTL_24M_X2_CPU
XCLK_BIASREF
XTL_32K_X1_CPU
XTL_32K_X2_CPU
SRTC_RST#
RTC_RST#
12
R1615
10MR2J-L-GP
20170210 change
X1602
1 2
XTAL-32D768KHZ-91-GP
082.30003.0221
2ND = 082.30003.0301
2
1 2
R1603
2K7R2F-GP
12
C1604
SC15P50V2JN-L-GP
1D0V_S5
12
C1607
SC1U50V3KX-GP
G1601
GAP-OPEN
1
3D3V_RTC_AUX
4
1
2 3
12
21
SRN20KJ-1-GP
RN1601
C1606
SC1U50V3KX-GP
C1601
XTL_24M_X1_CPU
1MR2F-L-GP
A A
XTL_24M_X2_CPU
U22
12
R1602
1
INPUT/OUTPUT#1
2
NC#2
3
INPUT/OUTPUT#3
U22
U22
1 2
SC15P50V2JN-L-GP
X1601
XTAL-24MHZ-135-GP
082.30006.0041
2nd = 82.30004.A01
1 2
C1602
SC15P50V2JN-L-GP
U22
X1601 P/N:082.30006.0041
5
4
3
close to CPU
2017/05/18 - SB
SSD1_CLKREQ_CPU_N
SSD2_CLKREQ_CPU_N
WLAN_CLKREQ_CPU#
PEG_CLKREQ_CPU#
LAN_CLKREQ_CPU#
SRCCLKREQ5#
RN1608
8
7
6
SRN10KJ-12-GP
RN1609
8
7
6
SRN10KJ-12-GP
3D3V_S0
1
2
3
45
1
2
3
45
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
MCP_CLOCK
MCP_CLOCK
MCP_CLOCK
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
16 106
16 106
16 106
1
-1M
-1M
-1M
5
Main Func = PCH
Audio Code
HDA_SYNC_CODEC27
D D
HDA_BITCLK_CODEC27
HDA_SDOUT_CODEC27
HDA_SDIN0_CPU27
HDA_SPKR14,27
HDA_RST#_CODEC27
ME_UNLOCK24
DMIC
DMIC_DATA_CON27,55
C C
DMIC_CLK_CON27,55
DMIC_DATA1_CON55
DMIC_CLK1_CON55
3D3V_S5
R1702
150KR2J-GP
DY
1 2
HDA_SDOUT_CPU
DMIC_CLK_CON
DMIC_CLK1_CON
2017/08/30 -1m
4
HDA_BITCLK_CODEC
HDA_RST#_CODEC
R1709
EC1701
DY
HDA_SYNC_CPU
HDA_BITCLK_CPU
HDA_SDIN0_CPU
HDA_RST#_CPU
DMIC_CLK0_CPU
DMIC_DATA0_CPUDMIC_DATA_CON
DMIC_CLK1_CPU
DMIC_DATA1_CPUDMIC_DATA1_CON
1 2
HDA_SPKR
1 2
SC22P50V2JN-L-GP
ME_UNLOCK HDA_SDOUT_CPU
R1703 0R2J-2-GP
R1704 0R2J-2-GP
R1705 0R2J-2-GP
R1706 0R2J-2-GP
1 2
1KR2F-L1-GP
1 2
1 2
1 2
DY
1 2
DY
3
HDA_SYNC_CODEC
HDA_SDOUT_CODEC
EC1700
SC22P50V2JN-L-GP
DY
CPU1G
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
AUDIO
RN1701
1
2
3
4 5
SRN33J-7-GP-U
Strap
1.8V Only
Strap
HDA_BITCLK_CPU
8
HDA_SYNC_CPU
7
HDA_SDOUT_CPU
6
HDA_RST#_CPU
SKYLAKE_ULT
2
SDIO/SDXC
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
1.8V Only
SD_RCOMP
GPP_F23
7 OF 20
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
SD_RCOMP
1
200R2F-L-GP
R1701
1 2
DY
SKYLAKE-U-GP
CPU
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
CPU_(AUDIO/SDIO/SDXC)
CPU_(AUDIO/SDIO/SDXC)
CPU_(AUDIO/SDIO/SDXC)
Carlsberg_KL
Carlsberg_KL
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Carlsberg_KL
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
-1M
-1M
17 106
17 106
17 106
1
-1M
5
4
3
2
1
Main Func = PCH
LPC_AD_CPU_P024,68,91
LPC_AD_CPU_P124,68,91
LPC_AD_CPU_P224,68,91
LPC_AD_CPU_P324,68,91
LPC_FRAME#_CPU24,68,91
D D
LPC_CLK_KBC18,24
LPC_CLK_DBG18,68
SPI_CS_CPU_N024,25
SPI_CLK_ROM24,25
SPI_WP_ROM25
SPI_HOLD_ROM25
SPI_SO_ROM24,25
SPI_SI_ROM24,25
SPI_SO_CPU14
SPI_SI_CPU14
LPC
SPI
SPI_CLK_ROM
SPI_SO_ROM
SPI_SI_ROM
SPI_WP_ROM
SPI_HOLD_ROM
SPI_CS_CPU_N0
SMBUS
C C
SML1_CLK24,73
SML1_DATA24,73
SPI_SO_CPU
SPI_SI_CPU
R1806 0R0402-PAD
R1807 0R0402-PAD
R1808 0R0402-PAD
R1809 0R0402-PAD
R1810 0R0402-PAD
SPI_CLK_ROM
EC1804
SC22P50V2JN-L-GP
DY
1 2
1 2
1 2
1 2
1 2
1 2
SPI_CLK_CPU
SPI_WP_CPU
SPI_HOLD_CPU
H_RCIN#
INT_SERIRQ
AW3
AW2
AW13
AY11
AV2
AV3
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
CPU1E
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
SKYLAKE-U-GP
Strap
CPU
SKYLAKE_ULT
3V3
LPC
SMBUS, SMLINK
GPP_C1/SMBDATA
Strap
GPP_C2/SMBALERT#
GPP_C4/SML0DATA
Strap
GPP_C5/SML0ALERT#
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
Strap
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
5 OF 20
GPP_C0/SMBCLK
GPP_C3/SML0CLK
GPP_C6/SML1CLK
GPP_A8/CLKRUN#
R7
R8
GPP_C2/SMBALERT#
R10
R9
W2
GPP_C5/SML0ALERT#
W1
SML1_CLK
W3
SML1_DATA
V3
GPP_B23/SML1ALERT#
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
LPC_AD_CPU_P0
LPC_AD_CPU_P1
LPC_AD_CPU_P2
LPC_AD_CPU_P3
LPC_FRAME#_CPU
SUS_STAT
LPC_CLK_CPU_P0
LPC_CLK_TPM_R
PM_CLKRUN#_EC
KBC /TYPE-C
R1830
TPM
SC22P50V2JN-L-GP
LPC_CLK_TPM
EC1803
DY
1 2
22R2J-L1-GP
3D3V_S0
PM_CLKRUN#_EC
1 2
1 2
R1818 8K2R2F-1-GP
SPI_HOLD_CPU
1 2
R1824
DY
1KR2J-L2-GP
OTHER
5
KBC
TPM
SERIRQ PH:
PDG: 8.2k
CRB: 10k
LPC_CLK_CPU_P0
4
3
2
H_RCIN#
INT_SERIRQ
SML1_DATA
SML1_CLK
R1811 22R2J-L1-GP
R1804 22R2J-L1-GP
0129 TM Larry
SC22P50V2JN-4GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
LPC,SPI,SMBUS,CLINK
LPC,SPI,SMBUS,CLINK
LPC,SPI,SMBUS,CLINK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
RN1801
4
SRN10KJ-L-GP
RN1807
SRN2K2J-4-GP
8
7
6
1 2
1 2
LAB
EC1801
DY
1 2
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
23
1
2
3
45
EC1802
SC22P50V2JN-4GP
DY
1 2
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
3D3V_S0
3D3V_S5
LPC_CLK_KBC 18,24
LPC_CLK_DBG 18,68
18 106
18 106
18 106
-1M
-1M
-1M
H_RCIN#24
INT_SERIRQ24,68,91
LPC_CLK_TPM91
SUS_STAT91
PM_CLKRUN#_EC24,91
B B
GPP_C2/SMBALERT#14
GPP_C5/SML0ALERT#14
GPP_B23/SML1ALERT#14
A A
5
4
3
2
1
1D0V_S5
1D0V_S5
D D
1D0V_S5
1D0V_S5
1D0V_S5
1D0V_S5
1D0V_S5
3D3V_S5
3D3V_S5
3D3V_S5
C C
1D0V_S5
3D3V_S5
1D0V_S5
1D0V_S5
1D0V_VCCDSW
1 2
R1901
0R0402-PAD-1-GP
VCCPRIM_1P0 0.696A
VccPRIM_CORE 2D57A
Follow LT41S 10mils
VCCMPHYAON 0D022A
VCCMPHYGT 0D154A
VCCAMPHYPLL 0D154A
1D0V_VCCAMPHYPLL
0D026A
VCCAPLL_1P0
1 2
R1902
0R0402-PAD-1-GP
VCCPRIM_1P0 0.696A
VCCDSW_3P3 0D311A
VCCHDA 0.068A
1 2
VCCHDA_10
R1903
0R0402-PAD-1-GP
VCCSPI 0D011A
VCCSRAM 1D714A
VCCPRIM_3P3 0D075A 10mils
VCCPRIM_1P0 0.696A 10mils
VCCAPLLEBB_1P0 0D088A 10mils
Close N18
10mils
10mils
10mils
25mils
25mils
25mils
25mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
20mils
20mils
20mils
20mils
12
C1906
SC100P50V2JN-L-GP
CPU1O
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0
N16
VCCMPHYGT_1P0
N17
VCCMPHYGT_1P0
P15
VCCMPHYGT_1P0
P16
VCCMPHYGT_1P0
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0
Y18
VCCPRIM_1P0
AD17
VCCDSW_3P3
AD18
VCCDSW_3P3
AJ17
VCCDSW_3P3
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3
AK20
VCCPRIM_1P0
N18
VCCAPLLEBB_1P0
SKYLAKE-U-GP
CPU
CPU POWER 4 OF 4
SKYLAKE_ULT
Primary supply for
PCIe/DMI/USB3/SATA/MIPI
MPHY
logic.
15 OF 20
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3
VCCPRIM_1P0
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC
VCCRTC
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
AK15
0D02A 10mils
AG15
0D004A 10mils
Y16
0D006A 10mils
Y15
0D008A 10mils
T16
0D006A 10mils
AF16
0D161A 10mils
AD15
0D041A 10mils
V19
10mils
T1
10mils
AA1
VCCATS 0D006A 10mils
AK17
VCCRTCPRIM_3P3 0D7mA 10mils
AK19
VCCRTC 0D1A 10mils
BB14
BB10
A14
0D035A 10mils
K19
0D029A 10mils
L21
0D024A 10mils
N20
0D033A 10mils
L19
0D004A 10mils
A10
0D01A 10mils
V0D85A_VID0
AN11
V0D85A_VID1
AN13
VCCGPPX 0D246A
1D0V_VCCCLK
1
TP1901
1
TP1902
3D3V_S5
1D8V_S5
R1904
1 2
0R0603-PAD
3D3V_S5
3D3V_S5
1D0V_S5
1D8V_S5
3D3V_S5
3D3V_RTC_AUX
VCCRTCEXT
1D0V_S5
Sensitive trace cap
VCCAPLL_1P0
B B
12
C1926
SC100P50V2JN-L-GP
Close V15
Sensitive trace cap
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(CS-2/EMMC)
CPU_(CS-2/EMMC)
CPU_(CS-2/EMMC)
Carlsberg_KL
Carlsberg_KL
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Carlsberg_KL
19 106
19 106
19 106
1
-1M
-1M
-1M
5
4
3
2
1
Main Func = PCH
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
GPP_B2/VRALERT#
R2004
100KR2F-L3-GP
75.27002.F7C
11 OF 20
SLP_SUS#
SLP_LAN#
INTRUDER#
DY
Q2001
34
2
5
1
6
Note:ZZ.27002.F7C01
2N7002KDW-1-GP
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
PM_SLP_S0#
PM_SLP_S3#
PM_SLP_S4#
PM_PWRBTN#
AC_PRESENT
BATLOW#
SM_INTRUDER#
EXT_PWR_GATE#
RSMRST#_KBC
3V_5V_POK
PM_RSMRST#
3V_5V_POK_C
BATLOW#:
Pull-up required even if not implemented.
-SB 20170316
U2001
R2001
1KR2F-L1-GP
12
R2002
1 2
0R0402-PAD
2017/05/11-SB
ED2000
AZ5725-01FDR7G-GP
1
2
DY
5
A
VCC
B
GND3Y
U74LVC1G08G-AL5-R-GP-U
73.01G08.EHG
2nd = 73.7SZ08.DAH
12
PM_RSMRST#
4
RSMRST#_KBC
3V_5V_POK
12
ED2001
AZ5725-01FDR7G-GP
DY
3D3V_S5
BATLOW#
PM_PWRBTN#
PCIE_WAKE#
AC_PRESENT
PM_SUSWARN#
C2002
SCD1U25V2KX-L-GP
12
DY
EXT_PWR_GATE#
SM_INTRUDER#
PM_RSMRST#
PM_PCH_PWROK
XDP_DBRESET#
PLT_RST# PM_PCH_PWROK
SRN10KJ-L-GP
SRN10KJ-L-GP
DY
1 2
R2030 10KR2F-L1-GP
1 2
DY
R2031 20KR2F-L3-GP
20170217 Chang e 20k
R2019 1MR2F-L-GP
1 2
R2010 10KR2F-L1-GP
1 2
DY
R2011 10KR2J-L-GP
10KR2F-L1-GP
DY
12
SYS_PWROK24
PCH_PWROK40
PCIE_WAKE#24,61,62,63
ALL_SYS_PWRGD24,40
D D
C C
#543016 Rev0.7
VCCST_PWRGD is only 1.0 V tolerant.
1.
2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST
PLT_RST#24,61,62,63,68,89,91
RSMRST#_KBC24
3V_5V_POK45,53,73
PM_SLP_S0#24,40
PM_SLP_S3#24,40,45,53
PM_SLP_S4#24,40,51
PM_PWRBTN#24
AC_PRESENT24
1KR2F-L1-GP
ALL_SYS_PWRGD
R2024
3D3V_S0
12
10KR2F-L1-GP
1 2
R2020
R2021
4K7R2J-L-GP
1 2
17/05/11-SB
20
1 2
R2008 0R0402-PAD
R2006 0R0402-PAD
1 2
1 2
0R2J-2-GP
VCCST_PWRGD
12
C2001
SC100P50V2JN-L-GP
R2017
PLT_RST#
XDP_DBRESET#
PM_RSMRST#
VCCST_PWRGD
SYS_PWROK
PM_PCH_PWROKPCH_PWROK
PCH_DPWROKPM_RSMRST#
PM_SUSWARN#
PM_SUSACK#
PCIE_WAKE#
PM_SUSWARN#PM_SUSACK#
DY
Sensitive trace
VCCST_PWRGD / HWM201:
B B
CPU1K
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD#AT15
SKYLAKE-U-GP
CPU
SKYLAKE_ULT
3D3V_AUX_S5
R2005
DY
10KR2F-L1-GP
1 2
3V_5V_POK_#
GPP_B11/EXT_PWR_GATE#
1 2
DY
2nd = 075.67002.007C
3rd = 075.063D1.007C
GPP_A13-15 pin(LPC/eSPI):
RN2005
1
4
2 3
RN2006
1
4
2 3
12
R2014
12
EC2020
SC22P50V2JN-L-GP
3D3V_S5
3D3V_S5
3D3V_RTC_AUX
3D3V_S0
DY
12
EC2002
SC10P50V2JN-L1-GP
<Core Design>
<Core Design>
A A
5
4
3
2
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(POWER MANAGEMENT)
CPU_(POWER MANAGEMENT)
CPU_(POWER MANAGEMENT)
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
20 106
20 106
20 106
-1M
-1M
-1M
5
Main Func = PCH
4
3
2
1
CPU1P
GND 1 OF 3
D D
C C
B B
A A
A67
A70
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL2
AL28
AL32
AL35
AL38
AL4
AL45
AL48
AL52
AL55
AL58
AL64
A5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKYLAKE-U-GP
SKYLAKE_ULT
16 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
CPU
5
4
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
CPU1Q
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKYLAKE-U-GP
CPU
SKYLAKE_ULT
17 OF 20
3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
CPU1R
GND 3 OF 3
F8
VSS
G10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKYLAKE-U-GP
SKYLAKE_ULT
G22
G43
G45
G48
G52
G55
G58
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
G5
G6
J8
CPU
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
18 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CPU_(VSS)
CPU_(VSS)
CPU_(VSS)
2
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
21 106
21 106
21 106
1
-1M
-1M
-1M
5
4
3
2
1
Main Func = CPU
CPU1D
D63
PECI_EC
1 2
D D
C C
PECI_EC24
PROCHOT#_CPU24,44,46
TP_IN#65
R2203
499R2F-2-GP
20170302 Change
1
2 3
SRN49D9F-GP
1
2 3
SRN49D9F-GP
RN2201
RN2202
4
4
PROCHOT#_CPU_RPROCHOT#_CPU
THERMTRIP#_CPU
TP_IN#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
-1m
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
SKYLAKE-U-GP
071.SKYLA.000U
SKYLAKE_ULT
CPU MISC
CPU
B B
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
4 OF 20
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
B61
D60
A61
C60
B59
B56
D59
A56
C59
C61
A59
+VCCSTG = 1.0 V
1V_VCCSTG
1215 Simon
Larry sugess to dummy r418`, r417
1 2
R2207 51R2J-2-GP
DY
1 2
R2210 51R2J-2-GP
DY
1 2
R2208 51R2J-2-GP
DY
XDP_TCK_JTAGX
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
XDP_TRST#
PCH_JTAG_TCK
TP_IN#
1 2
THERMTRIP#_CPU
PROCHOT#_CPU
R2213
10KR2J-L-GP
20170302 Change
R2219
1 2
1KR2F-L1-GP
R2201
1KR2F-L1-GP
3D3V_S0
1V_VCCST
1V_VCCSTG
12
XDP_TCK_JTAGX
XDP_TRST#
PCH_JTAG_TCK
A A
5
4
3
1 2
R2209 51R2J-2-GP
DY
1 2
R2205
1 2
R2206 51R2J-2-GP
51R2J-2-GP
DY
DY
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Siz
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU_(JTAG/CPU SIDE BAND)
CPU_(JTAG/CPU SIDE BAND)
CPU_(JTAG/CPU SIDE BAND)
e Document Number Rev
Carlsberg_KL
Carlsberg_KL
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Carlsberg_KL
22 106
22 106
22 106
1
-1M
-1M
-1M
5
Main Func = CPU
4
3
2
1
CPU1S
E68
CFG[0]
B67
CFG[1]
D65
CFG[2]
CFG3
D D
1 2
R2301 49D9R2F-L1-GP
C C
TP601
TP602
CFG4
CFG_RCOMP
RSVD_TP_BA70
1
RSVD_TP_BA68
1
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
AY2
AY1
K46
K45
AL25
AL27
C71
B70
F60
A52
BA70
BA68
F65
G65
F61
E61
E8
D1
D3
J71
J68
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD#AY2
RSVD#AY1
RSVD#D1
RSVD#D3
RSVD#K46
RSVD#K45
RSVD#AL25
RSVD#AL27
RSVD#C71
RSVD#B70
RSVD#F60
RSVD#A52
RSVD_TP#BA70
RSVD_TP#BA68
RSVD#J71
RSVD#J68
VSS
VSS
RSVD#F61
RSVD#E61
SKYLAKE-U-GP
RESERVED SIGNALS-1
SKYLAKE_ULT
19 OF 20
RSVD_TP#BB68
RSVD_TP#BB69
RSVD_TP#AK13
RSVD_TP#AK12
RSVD#BB2
RSVD#BA3
RSVD#D5
RSVD#D4
RSVD#B2
RSVD#C2
RSVD#B3
RSVD#A3
RSVD#AW1
RSVD#E1
RSVD#E2
RSVD#BA4
RSVD#BB4
RSVD#A4
RSVD#C4
RSVD#A69
RSVD#B69
RSVD#AY3
RSVD#D71
RSVD#C70
RSVD#C54
RSVD#D54
VSS
ZVM#
RSVD_TP#AW71
RSVD_TP#AW70
MSM#
PROC_SELECT#
PCH strap pin:
CFG3
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
AR56
AW71
AW70
AP56
C64
PROC_SELECT#
R2303 100KR2F-L3-GP
DY
1 2
1V_VCCST
12
R2305
1KR2J-1-GP
DY
PCH strap pin:
CFG4
12
R2304
1KR2J-1-GP
[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
0 : ENABLED
CFG[3]
SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
1 : DISABLED
DISPLAY PORT PRESENCE STRAP
0 : ENABLED
CFG[4]
An external Display Port device is connected to the Embedded Display Port.
1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.
CPU
B B
CPU1T
SKYLAKE_ULT
RSVD#AW69
RSVD#AW68
RSVD#AU56
RSVD#AW48
RSVD#C7
RSVD#U12
RSVD#U11
RSVD#H11
SPARE
AW69
AW68
AU56
XTAL24_RU42_OUT
A A
AW48
U12
U11
H11
C7
SKYLAKE-U-GP
CPU
5
20 OF 20
RSVD#F6
RSVD#E3
RSVD#C11
RSVD#B11
RSVD#A11
RSVD#D12
RSVD#C12
RSVD#F52
F6
E3
C11
B11
A11
D12
C12
F52
XTAL24_RU42_IN
XTAL24_RU42_IN
XTAL24_RU42_OUT
12
R2308
1MR2J-1-GP
U42
need to choose ESR < 50ohm
1
INPUT/OUTPUT#1
2
NC#2
3
INPUT/OUTPUT#3
U42
P/N: 082.30006.0041
4
U42
C2310 SC15P50V2JN-L-GP
C2312 SC15P50V2JN-L-GP
12
X2301
XTAL-24MHZ-135-GP
082.30006.0041
2nd = 82.30004.A01
U42
12
3
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_RESERVED,CFG
CPU_RESERVED,CFG
CPU_RESERVED,CFG
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
23 106
23 106
23 106
-1M
-1M
-1M
SSID = KBC
5
Power
3D3V_AUX_S5
3D3V_S0
3D3V_RTC_AUX
AC_PRESENT 20
eDP_BLEN_CPU 3
PM_PWRBTN# 20
PCIE_WAKE# 20,61,62,63
Signal
H_RCIN# 18
FUN_OFF# 65,89
D D
LPC_FRAME#_CPU 18,68,91
LPC_AD_CPU_P3 18,68,91
LPC_AD_CPU_P2 18,68,91
LPC_AD_CPU_P1 18,68,91
LPC_AD_CPU_P0 18,68,91
LPC_CLK_KBC 18
PLT_RST# 20,61,62,63,68,89,91
WLAN_PCIE_WAKE# 24,61
LID_CLOSE# 66
PTP_PWR_EN# 65
PURE_HW_SHUTDOWN# 26,40
PM_CLKRUN#_EC 18,91
E51_TXD 61,68
EC_TP_IN# 24,65
KBC_BEEP 27
KB_BL_DET 65
FAN1_PWM 26,89
FAN_TACH1 26,89
3.3V
LPC BUS=>3.3V
SPI BUS=>3.3V/1.8V (VCC_IO2 PIN:124 OPTION)
C C
KSI0 65,89
KSI1 65,89
KSI2 65,89
KSI3 65,89
KSI4 65,89
KSI5 65,89
KSI6 65,89
KSI7 65,89
KSO0 65,89
KSO1 65,89
KSO2 65,89
KSO3 65,89
KSO4 65,89
KSO5 65,89
KSO6 65,89
KSO7 65,89
KSO8 65,89
KSO9 65,89
KSO10 65,89
KSO11 65,89
KSO12 65,89
KSO13 65,89
KSO14 65,89
KSO15 65,89
KSO16 65,89
KSO17 65,89
AC_IN# 44,74
DC_Protect_EC 44
KBC_PWRBTN# 65,89
BAT_IN# 43,44
DC_IN_OK 44,73,74
AD_IA 44
BT_IA 44
2017 05/22 -SB
ALL_SYS_PWRGD 20,40
STDBY_LED 66,89
POWER_LED 66,89
CHARGE_LED 66,89
DC_BATFULL 66,89
SML1_CLK 18,73
SML1_DATA 18,73
BAT_SCL 43,44
BAT_SDA 43,44
SPI_WP_ROM 18,25
EC_TPCLK 65
EC_TPDATA 65
ME_UNLOCK 17
EC_TP_IN# 24,65
RTCRST_ON 16
BLON_OUT 55
AD_OFF 43
VD_IN1 26
VD_OUT1 26
PROCHOT#_CPU 22,44,46
RSMRST#_KBC 20
AMP_MUTE# 27
5V_EN 40,45
KB_BL_PWM 65
TOUCH_EN 55
3V_S5_ENABLE 24,40
3V_S5_ENABLE 24,40
TYPEC_ILIM 74
PM_SLP_S0# 20,40
VCCSTG_EN_EC 40
PURE_HW_SHUTDOWN#
100KR2F-L3-GP
B B
A A
INT_SERIRQ 18,68,91
EC_SCI# 3
PM_SLP_S3# 20,40,45,53
PM_SLP_S4# 20,40,51
PD_INT# 73
USB_CHAR_SEL 36
USB_CHARGER_EN 36
USB_CHAR_CT1 36
WIFI_RF_EN 61
BLUETOOTH_EN 61,89
USB_PWR_EN# 35
WLAN_PCIE_WAKE# 24,61
CHG_ON# 44
PECI_EC 22
WLAN_PERST# 61
WLAN_PWR_EN# 61
SYS_PWROK 20
SPI_SO_ROM 18,25
SPI_SI_ROM 18,25
SPI_CLK_ROM 18,25
SPI_CS_CPU_N0 18,25
RN2407
1
2 3
SRN10KJ-L-GP
GPIO0 High Active
PROCHOT_EC
12
12
R2408
C2430
SC100P50V2JN-L-GP
Sensitive trac e cap
330KR2J-L-GP
G2402
GAP-OPEN
4
3D3V_AUX_S5
R2441
1 2
21
ECRST#_Q
3D3V_AUX_S5
Q2404
G
S
2N7002K-2-GP
84.2N702.J31
2ND = 084.27002.0L31
Type_C
Cha
D
5
4
1KR2F-L1-GP
R2453
AD_OFF
1 2
Close to the EC
PLT_RST#
12
R2460
47KR2J-L2-GP
RN2412
1
4
2 3
SRN10KJ-L-GP
3D3V_S0
RN2410
2 3
1
4
SRN10KJ-L-GP
3D3V_AUX_KBC
RN2413
rger
3D3V_AUX_S5
3D3V_S0
3D3V_AUX_KBC
2017 05/22 -SB
3D3V_S5
KBC_PWRBTN#_RKBC_PWRBTN# EC_SCI# ECSCI#_KBC
12
R2444
470R2F-GP
Q2403
PMBS3906-GP
2
1
84.03906.F11
3
2nd = 84.T3906.E11
PROCHOT#_CPU
SRN100KJ-6-GP
1
2 3
10KR2J-3-GP
10KR2J-3-GP
ECRST#
RN2414
SRN10KJ-L-GP
R2401
DY
10KR2J-L-GP
R2451
DY
R2454
DY
R2402
10KR2J-3-GP
12
C2428
SC1U10V2KX-L1-GP
1234
4
12
12
12
5V_EN
3V_S5_ENABLE
FAN_TACH1
FUN_OFF#
12
BAT_IN#
CHG_ON#
LID_CLOSE#
TOUCH_EN
ECRST#
USB_PWR_EN#
TYPEC_ILIM
VC
C_LPC(Pin9)
3D3V_AUX_KBC
1 2
R2465
0R0402-PAD-1-GP
4
R2435
0R0402-PAD-1-GP
1 2
VCC_LPC
2017 05/22 -SB
CPU/Type C --->
BATTER /CHARGER --->
Touch Pad--->
3
For EC power c onsumption rese rver
1 2
R2406
0R0603-PAD-1-GP-U
BLM15AG121SN-1GP
68.00084.921
2nd = 68.00217.401
LPC_CLK_KBC
LPC_FRAME#_CPU
LPC_AD_CPU_P0
LPC_AD_CPU_P1
LPC_AD_CPU_P2
LPC_AD_CPU_P3
INT_SERIRQ
TYPEC_ILIM
H_RCIN#
PLT_RST#
ECSCI#_KBC
PM_CLKRUN#_EC
ECRST#
KBC_BEEP
KB_BL_PWM
DC_BATFULL
FAN1_PWM
FAN_TACH1
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
SML1_DATA
SML1_CLK
BAT_SDA
BAT_SCL
DC_IN_OK
EC_TPCLK
EC_TPDATA
5V_EN
CHG_ON#
LID_CLOSE#
WLAN_PERST#
STDBY_LED
E51_TXD
PM_SLP_S0#
ME_UNLOCK
CHARGE_LED SPI_SI_KBC SPI_SI_ROM
WIFI_RF_EN
3D3V_AUX_KBC
12
R2429
20KR2F-L3-GP
EC_AGND
3D3V_AUX_KBC
EC_AGND
3D3V_AUX_KBC
12
R2425
100KR2F-L3-GP
Adapter
12
EC_AGND
Module_ID
12
R2431
100KR2F-L3-GP
Module_ID
12
R2428
64K9R2F-1-GP
PCB_VER
2017/10/17 -1m
12
R2427
100KR2F-L3-GP
PCB_VER
R2430
20KR2F-L3-GP
Adapter
MODEL_ID_AD
PCB_VER_AD
ADT_TYPE_AD
3D3V_AUX_S53D3V_AUX_KBC
L2401
12
EC_AGND
U2401
12
PCICLK
4
LFRAME#
10
LAD0
8
LAD1
7
3.3V
LAD2
5
LAD3
3
SERIRQ
1
GA20
2
1.8V
KBRST#
13
PCIRST#
20
SCI#
38
CLKRUN#
37
ECRST#
21
PWM0
23
PWM1
25
PWM2
26
FANPWM0
27
FANPWM1
28
FANFB0
29
FANFB1
39
KSO0
40
KSO1
41
KSO2
42
KSO3
43
KSO4
44
KSO5
45
KSO6
46
KSO7
47
KSO8
48
KSO9
49
KSO10
50
KSO11
51
KSO12
52
KSO13
53
KSO14
54
KSO15
81
KSO16
82
KSO17
55
KSI0
56
KSI1
57
KSI2
58
KSI3
59
KSI4
60
KSI5
61
KSI6
62
KSI7
78
SDA0
77
SCL0
80
SDA1
79
SCL1
83
PSCLK1
84
PSDAT1
85
PSCLK2
86
PSDAT2
87
PSCLK3
88
PSDAT3
17
GPIO0B
18
GPIO0C
16
GPIO0A
19
GPIO0D
34
GPIO19
30
GPIO16
31
GPIO17
90
GPIO52
92
GPIO54
95
GPIO56
071.09028.000G
KB9028Q-C-GP
3
3.3V
1.8V
1.8V
3.3V
3.3V
2
3D3V_RTC_AUX3D3V_AUX_KBC
EC_AGND
H_PECI_KBC
PCIE_WAKE#_R
R2415
SPI_CS_KBC_N0 SPI_CS_CPU_N0
1 2
1 2
SPI_SO_KBC SPI_SO_ROM
1 2
1 2
VCC_LPC
VCC_IO2
GPXIOA00
GPXIOA01
GPXIOA02
GPXIOA03
GPXIOA04
GPXIOA05
GPXIOA06
GPXIOA07
GPXIOA08
GPXIOA09
GPXIOA10
GPXIOA11
GPXIOD00
AC_IN#
EC_EN#
PWRBTN#
GPXIOD04
GPXIOD05
GPIOD06
GPIO1A
GPIO53
GPIO55
GPIO5D
GPIO5E
GPIO59
GPIO57
GPIO50
GPIO18
GPIO08
GPIO07
GPIO04
SPICS#
SPICLK
125
VCC
22
VCC
33
VCC
111
VCC0
96
VCC
9
67
AVCC
11
GND
24
GND
35
GND
94
GND
113
GND
69
AGND
124
68
DA0
70
DA1
71
DA2
72
DA3
63
AD0
64
AD1
65
AD2
66
AD3
75
AD4
76
AD5
73
AD6
74
AD7
97
98
99
100
101
102
103
104
105
106
107
108
109
110
112
114
115
116
117
118
PECI
36
91
93
122
123
127
121
89
32
15
14
6
128
120
MOSI
119
MISO
126
2
3D3V_AUX_KBC
1 2
R244843R2F-2-GP
DY
12
0R2J-L-GP
R2412 0R0402-PAD-1-GP
R2407 0R0402-PAD-1-GP
R2418 0R0402-PAD-1-GP
R2411 0R0402-PAD-1-GP
VCC_LPC
12
C2429
SCD1U25V2KX-L-GP
AMP_MUTE#
PM_SLP_S4#
WLAN_PCIE_WAKE#
AD_IA
PCB_VER_AD
ADT_TYPE_AD
EC_TP_IN#
MODEL_ID_AD
BT_IA
USB_CHARGER_EN
KB_BL_DET
BLON_OUT
AD_OFF
3V_S5_ENABLE
FUN_OFF#
TOUCH_EN
RSMRST#_KBC
VD_OUT1
USB_PWR_EN#
SYS_PWROK
RTCRST_ON
PD_INT#
VD_IN1
AC_IN#
USB_CHAR_SEL
KBC_PWRBTN#_R
ALL_SYS_PWRGD
USB_CHAR_CT1
DC_Protect_EC
PECI_EC
WLAN_PWR_EN#
BAT_IN#
POWER_LED
eDP_BLEN_CPU
PM_PWRBTN#
PCIE_WAKE#
AC_PRESENT
VCCSTG_EN_EC
PTP_PWR_EN#
PROCHOT_EC
BLUETOOTH_EN
PM_SLP_S3#
SPI_CLK_ROMSPI_CLK_KBC
PM_PWRBTN#
ALL_SYS_PWRGD
SYS_PWROK
AMP_MUTE#
PURE_HW_SHUTDOWN#
1
3D3V_AUX_KBC
12
EC_AGND
12
C2421
SCD1U25V2KX-L-GP
12
C2422
SCD1U25V2KX-L-GP
12
C2424
SCD1U25V2KX-L-GP
3D3V_AUX_KBC_AVCC 3D3V_AUX_KBC
12
C2427
SCD1U25V2KX-L-GP
C2425
12
SCD1U25V2KX-L-GP
BLM15AG121SN-1GP
12
C2420
C2426
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
L2407
12
SYS_PWROK(S0_P WR_GOOD) ==DELA Y 99ms
12
12
12
ED2401
AZ5725-01FDR7G-GP
ED2402
AZ5725-01FDR7G-GP
DY
DY
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
KBC_KB9028
KBC_KB9028
KBC_KB9028
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
12
ED2403
AZ5725-01FDR7G-GP
ED2404
AZ5725-01FDR7G-GP
DY
DY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
24 106
24 106
24 106
1
12
C2416
SCD1U25V2KX-L-GP
12
ED2405
AZ5725-01FDR7G-GP
DY
-1M
-1M
-1M
5
4
3
2
1
Main Func = SPI Flash
SPI FLASH ROM (8M byte) for PCH
SPI ROM Equal length need to less than 500mil
SCLK
LAB
VCC
SIO3
8
7
5
3D3V_S5
8
7
6
5
20170308 Change
3D3V_S5
SPI_HOLD_ROM_R
SPI_CLK_ROM
SPI_SI_ROM
1 2
R2507
0R0402-PAD-1-GP
SPI_HOLD_ROM_R
SPI_HOLD_ROM
SPI_CLK_ROMSPI_WP_ROM
SPI_SI_ROM
SPI_CS_CPU_N0SPI_CS_CPU_N0
12
DY
3K3R2F-2-GP
C2501
SC10U6D3V3MX-L-GP
R2508
3D3V_S5
12
3D3V_S5
12
C2502
SCD1U25V2KX-L-GP
SPI_CS_CPU_N018,24
D D
C C
SPI_SO_ROM18,24
SPI_WP_ROM18
SPI_WP_ROM_R14
SPI_HOLD_ROM_R14
SPI_HOLD_ROM18
SPI_CLK_ROM18,24
SPI_SI_ROM18,24
RTC_DET#6
SPI_CS_CPU_N0
SPI_SO_ROM
SPI_WP_ROM_R
1 2
R2506
0R0402-PAD-1-GP
SPI_SO_ROM
SPI_WP_ROM_R
U2501
1
CS#
2
SO/SIO1
3
SIO2
GND4SI/SIO0
MX25L6473FM2I-08G-GP
072.25647.000D
2nd = 072.25Q64.0H01
0
72.25647.000D_MX25L6473FM2I-08G_MXIC
2.25Q64.0H01_W25Q64FVSSIQ_WINBOND
07
U2504
1
2
3 6
4
SKT-G6179-GP-U
62.10076.011
Main Func = RTC
3D3V_AUX_S5
R2503
1 2
1K5R2F-2-GP
R2505
1 2
45K3R2F-L-GP
3D3V_AUX_S5_R
B B
RTC1
3
1
2
4
ACES-CON2-40-GP-U
20.F1633.002
2nd = 020.F0245.0002
A A
RTC BATTERY
1st= 023.21220.1101
5
4
3D3V_RTC_VCC
2017/05/12 - SB
R2502
1KR2F-L1-GP
Width=20mils
12
R2504
10MR2J-L-GP
2017/04/25 -SB
075.00054.0B7D
2ND = 075.00054.0N7D
12
3D3V_RTC_PWR
G
3
12
RTC_DET#
DS
Q2505
PJA7002H-R1-00001-1-GP
084.07002.M002
2nd = 084.27002.M009
3D3V_RTC_AUX
D2501
LBAT54CLT1G-1-GP
3
C2503
SC1U10V2KX-L1-GP
12
DY
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Si
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
Flash(KBC+PCH)/RTC
Flash(KBC+PCH)/RTC
Flash(KBC+PCH)/RTC
ze Document Number Rev
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
25 106
25 106
25 106
1
-1M
-1M
-1M
5
4
3
2
1
VD_IN124
FAN1_PW M24,26,89
D D
C C
FAN_TACH124,89
PURE_HW _SHUTDOWN#24,40
VD_OUT124
VR_RDY40,46
FAN_TACH1_C89
FAN1_PW M24,26,89
RT2601 close CPU and Vcore chock
SSID = Thermal
3D3V_AUX_S5
12
R2611
16KR2F-GP
12
T8
RT2601
NTC-100K-11-GP-U
12
C2607
3D3V_S0
VD_IN1
12
SCD1U25V2KX-L-GP
C2608
SC100P50V2JN-L-GP
PURE_HW _SHUTDOWN#
Q2603
D
2N7002K-2-GP
84.2N702.J31
2ND = 084.27002.0L31
S
G
12
R2606
2KR2F-L1-GP
VD_OUT1
VR_RDY
VD_IN1 trace 10 mli
*Layout* 15 mil
B B
KA
D2601
RB551V30-GP
83.R5003.H8H
2ND = 83.R5003.T8F
5V_S0
FAN1_PW M
12
C2603
12
C2602
SC4D7U25V5KX-L2-GP
SCD1U25V2KX-L-GP
DY
D2602
FAN_TACH1_CFAN_TACH1
KA
RB551V30-GP
83.R5003.H8H
2ND = 83.R5003.T8F
5V_S0
FAN1
ACES-CON4-67-GP
6
4
3
2
1
5
020.F0220.0004
2nd = 020.F000P.0004
2017/05/12 - SB
<Core Design>
<Core Design>
<Core Design>
A A
Title
Title
Title
Thermal 7718/Fan Controllor P2793
Thermal 7718/Fan Controllor P2793
Thermal 7718/Fan Controllor P2793
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
26 106
26 106
26 106
1
-1M
-1M
-1M
5
4
3
2
1
From CPU
HDA_SDOUT_CODEC17
HDA_BITCLK_CODEC17
HDA_SDIN0_CPU17
D D
HDA_SYNC_CODEC17
HDA_RST#_CODEC17
DMIC to eDP Con.
DMIC_DATA_CON17,55
DMIC_CLK_CON17,55
C C
Speaker to audio box
AUD_SPK1_L+29
AUD_SPK1_L-29
AUD_SPK1_R-29
AUD_SPK1_R+29
Universal Jack via IO Board
SELEEVE66,89
AUD_HP1_JACK_L266,89
AUD_HP1_JACK_R266,89
RING266,89
AUD_HP1_JD#66,89
B B
AMP_MUTE#24
KBC_BEEP24
HDA_SPKR14,17
SSID = AUDIO
5V_S0
1 2
R2719
0R0603-PAD-1-GP-U
5V_PVDD
Close to Pin46
Close to Pin41
12
C2709
12
C2707
12
SCD1U16V2KX-L-GP
2017/06/07 -SB
12
SCD1U16V2KX-L-GP
2017/06/07 -SB
C2708
SC10U25V5KX-L-GP
C2706
SC10U25V5KX-L-GP
1D5V_S0
1 2
R2766
0R0402-PAD-1-GP
TO Audio BOX
AUD_AGND
2017/07/05 -1
3D3V_AUDIO_S0
12
C2701
SC4D7U6D3V3KX-L-GP
Close pin36
1D5V_AVDD_S0
12
C2715
SC4D7U6D3V3KX-L-GP
AUD_AGND
C2712 SC10U6D3V3MX-L-GP
AUD_SPK1_L+
AUD_SPK1_LAUD_SPK1_RAUD_SPK1_R+
AMP_MUTE#
AUD_HP1_JACK_L2
AUD_HP1_JACK_R2
2017/07/05 -1
3D3V_AUDIO_S0
12
C2703
CBP
LDO2_CAP
EAPD#
1 2
R2720
0R0603-PAD-1-GP-U
SC10U6D3V3MX-L-GP
SC2D2U10V3KX-L-GP
C2717
C
lose pin40
1 2
1D5V_AVDD_S0
5V_PVDD
5V_PVDD
1 2
R2754
0R0402-PAD
2017/05/11-SB
2017/07/05 -1 2017/07/05 -1
1 2
R2748
0R0402-PAD-1-GP
C2714
SC10U6D3V3MX-L-GP
U2701
37
CBP
38
AVSS2
39
LDO2-CAP
40
AVDD2
41
PVDD1
42
SPK-OUT-L+
43
SPK-OUT-L-
44
SPK-OUT-R-
45
SPK-OUT-R+
46
PVDD2
47
PDB
48
SPDIF-OUT/GPIO2
49
GND
ALC255-CG-GP-U
3D3V_AUDIO_DVDD
12
SCD1U16V2KX-L-GP
C2704
1 2
SC2D2U10V3KX-L-GP
12
071.00255.0003
C2716
Close to Pin1
G2703
1 2
GAP-CLOSE
G2701
1 2
GAP-CLOSE
G2702
1 2
GAP-CLOSE
AUD_AGND close to codec IC
3V_MIC2V
12
SC2D2U10V3KX-L-GP
SC10U6D3V3MX-L-GP
C2705
12
C2702
LINE1_VREFO_R
LINE1_VREFO_L
CBN
AUD_VREF
LDO1_CAP
CPVDD
CPVEE
28
25
26
27
34
35
36
29
32
30
33
CBN
VREF
AVDD1
CPVEE
CPVDD
LDO1-CAP
LINE2-L_PORT-E-L
MIC2-VREFO
LINE2-R_PORT-E-R
LINE1-VREFO-L31LINE1-L_PORT-C-L
LINE1-VREFO-R
LINE1-R_PORT-C-R
HPOUT-L_PORT-I-L
HPOUT-R_PORT-I-R
MIC2-R_PORT-F-R/SLEEVE
MIC2-L_PORT-F-L/RING
SPDIFO/FRONT_JD_JD3/GPIO3
MIC2/LINE2_JD_JD2
HP/LINE1_JD_JD1
DVDD
DVDD-IO
GPIO0/DMIC-DATA2GPIO1/DMIC-CLK
LDO3-CAP7BCLK6DC_DET4RESET#
SYNC
SDATA-IN8SDATA-OUT
1
9
3
5
11
12
10
LDO3_CAP
C2719S CD1U16V2KX-L-GP
12
12
C2718S C10U6D3V3MX-L-GP
1 2
AVSS1
PCBEEP
AUD_AGND
12
R2711
100KR2F-L3-GP
5V_PVDD2
VD33_STB
MIC_CAP
MONO-OUT
12
AUD_AGND
1 2
0R0603-PAD-1-GP-U
AUD_AGND
24
23
22
21
20
19
18
17
16
15
14
13
DVDD_IO
C2720
SC10U6D3V3MX-L-GP
R2755
LINE1_L
C2723 SC4D7U6D3V3KX- L-GP
LINE1_R
C2724 SC4D7U6D3V3KX- L-GP
V3D3_STB
MIC_CAP
C2713 SC10U6D3V3MX-L-GP
AUD_SENSE_A
1 2
R2714
0R0402-PAD-1-GP
1 2
1 2
1 2
1 2
R2713
200KR2F-L-3-GP
3D3V_AUDIO_S03D3V_AUDIO_S0
5V_S0
R2722
1 2
100KR2F-L3-GP
5V_PVDD2
C2710
SCD1U16V2KX-L-GP
AUD_HP1_JACK_L2
AUD_HP1_JACK_R2
2017/07/05 -1
C2711
12
12
SC10U6D3V3MX-L-GP
1 2
R2712 0R0402-PAD-1-GP
AUD_AGND
AUD_HP1_JD#
3D3V_AUDIO_S0
Layout Note:
Place close to Pin 26
RN2703
2 3
1
SRN4K7J-8-GP
3D3V_S5
4
LINE1_VREFO_L
LINE1_VREFO_R
2017/07/05 -1
3D3V_S0 3D3V_AUDIO_S0
1 2
R2703
0R0603-PAD
3V_MIC2V
4
RN2702
SRN2K2J-5-GP
1
2 3
SELEEVE
RING2
Width>40mil, to improve Headpohone Crosstalk noise
Change it to sharp will be better.
Add 2 vias (>0.5A) when trace layer change.
Layout Note:
2017/08/30 -1m
DMIC_DATA_CON
TO DB
A A
5
4
TO CPU
DMIC_CLK_CON
HDA_SDOUT_CODEC
HDA_BITCLK_CODEC
HDA_SDIN0_CPU
HDA_SYNC_CODEC
HDA_RST#_CODEC
1 2
R2756 0R2J-2-GP
1 2
R2757 0R2J-2-GP
DY
DY
1 2
R2718 33R2J-L1-GP
3
DMIC_DATA_CODEC
DMIC_CLK_CODEC
HDA_SDIN0_CODEC
AUDIO_PC_BEEP
C2725
1 2
SCD1U16V2KX-L-GP
KBC_BEEP_C
12
R2730
10KR2F-L1-GP
1 2
R2701 47KR2J-L2-GP
1 2
R2702 47KR2J-L2-GP
2017/06/07 - SB
placed nearby codec PIN12
2
KBC_BEEP
HDA_SPKR
2017/05/12 - SB
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
1
Taipei Hsien 221, Taiwan, R.O.C.
27 106
27 106
27 106
Title
Title
Title
Audio Codec ALC255
Audio Codec ALC255
Audio Codec ALC255
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
-1M
-1M
-1M
5
D D
C C
4
3
2
1
Blanking
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
AUDIO AMP_ALC1001
AUDIO AMP_ALC1001
AUDIO AMP_ALC1001
Carlsberg_KL
Carlsberg_KL
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Carlsberg_KL
28 106
28 106
28 106
1
-1M
-1M
-1M
5
4
3
2
1
SSID = AUDIO
Speaker
D D
2017/05/16 - SB
5
AUD_SPK1_L-27
AUD_SPK1_L+27
AUD_SPK1_R-27
AUD_SPK1_R+27
C C
AUD_SPK1_LAUD_SPK1_L+
AUD_SPK1_RAUD_SPK1_R+ AUD_SPK1_R+_CON
1 2
R2914 0R0603-PAD
1 2
R2915 0R0603-PAD
1 2
R2916 0R0603-PAD
1 2
R2917 0R0603-PAD
1 2
EC2901 SC22P50V2JN-L-GP
1 2
EC2902 SC22P50V2JN-L-GP
1 2
EC2915 SC22P50V2JN-L-GP
1 2
EC2920 SC22P50V2JN-L-GP
AUD_SPK1_L-_CON
AUD_SPK1_L+_CON
AUD_SPK1_R-_CON
DY
DY
DY
DY
1
2
3
4
6
SPK1
ACES-CON4-17-GP-U1
20.F1621.004
2nd = 20.F1937.004
Layout Note:
Trace width=40mil
B B
AFTP TESTPOINT
AUD_SPK1_L-_CON
AUD_SPK1_L+_CON
AUD_SPK1_R-_CON
AUD_SPK1_R+_CON
2
2
1
AUD_SPK1_L-_CON89
AUD_SPK1_L+_CON89
AUD_SPK1_R-_CON89
AUD_SPK1_R+_CON89
A A
5
4
3
ED2901
AZ5125-02S-R7G-GP
DY
1
ED2902
AZ5125-02S-R7G-GP
DY
3
3
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Speaker/ALC255
Speaker/ALC255
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
A4
A4
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
Speaker/ALC255
Carlsberg_KL
Carlsberg_KL
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
2
Carlsberg_KL
29 106
29 106
29 106
1
-1M
-1M
-1M
5
D D
C C
4
3
2
1
Blanking
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Wednesday, November 01, 2017
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Carlsberg_KL
Carlsberg_KL
Carlsberg_KL
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
-1M
-1M
30 106
30 106
30 106
1
-1M
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