Acer Swift 3 SF314-52G Schematic
5
4
3
2
1
SU4EA Block Diagram
D D
eDP CONN.
14" Panel
HDMI 1.4
HDMI CONN
TMDS
HDMI LS
TPM
NUVOTON/NPCT650AA0WX
Debug Conn.
C C
Keyboard / ClickPad
EC
Thermal/Fan
Universal Jack
Speaker
B B
DMIC
IT8987E/BX
SPI ROM
Audio Codec
REALTEK/ALC255-CGT
EMMC
eDP
DDI1
LPC
SPI
HDA
EMMC
KabyLake-U
CPU
U22
U42
PCH
PCIe X1 (9)
PCIe X4 (5, 6, 7, 8)
SATA1
PCIe X2 (11, 12)
SATA2
DDR4_CHB
DDR4_CHA
USB 3.0
USB 2.0
1
2
3, 4
DDR4 Memory Down
DDR4 Memory Down
1
2
3
4
5
7
8
CR CONTROLLER
REALTEK/RTS5170-GR
9
6
M.2 2230
WLAN & BT
M.2 2240/2260/2280
SSD1
USB3.0 Port S/C
USB3.0 Port
USB Type-C
USB2.0 Port
Camera
SD Card
Finger Printer
Power
+VCORE
+VCCGT
+VCCSA
System (5V & 3.3V)
+1.0VSUS
DDR & VTT
+1.8VSUS
DDR(2.5V)
Battery Charger
Load Switch
Power Protect
Page 80
Page 81
Page 82
Page 83
Page 84
Page 85
Page 88
Page 91
Page 92
M.2 2240/2260/2280
SSD2
A A
Title :
Title :
Title :
Block Diagram
Block Diagram
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
1
Engineer:
Engineer:
Engineer:
Block Diagram
James_Liao
James_Liao
James_Liao
1 94Monday, February 20, 2017
1 94Monday, February 20, 2017
1 94Monday, February 20, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
Option
Optional
N/A
/@
/Debug
D D
Remark
Mount
Ummount
Debug only
Reserved EMI part/EMI
4
3
2
1
/SSD1 Support M.2 SSD1
Support M.2 SSD2/SSD2
/EMMC Support EMMC
/UMA Support UMA
/VGA Support VGA
/SDP Support SDP DRAM
/DDP Support DDP DRAM
/U22
/U42
/14inch
/15inch
Support 2+2 CPU
Support 4+2 CPU
Support 14"
Support 15"
C C
/TPM
/IOAC
/NON-IOAC
/PTP
/NON-PTP
B B
Support TPM function
Support IOAC
Not support IOAC
Support PTP
Not support PTP
A A
Title :
Title :
Title :
Option
Option
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Option
James_Liao
James_Liao
James_Liao
2 94Monday, February 20, 2017
2 94Monday, February 20, 2017
2 94Monday, February 20, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
03
D D
HDMI_TXN248
HDMI_TXP248
+VCCIO
HDMI_TXN148
HDMI_TXP148
HDMI_TXN048
HDMI_TXP048
HDMI_CLKN48
HDMI_CLKP48
HDMI_SCL_PCH48
HDMI_SDA_PCH48
R0301 24.9Ohm1%
DDI Port 1: HDMI
C C
4
CPU(1)_DDI_eDP
SKYLAKE-U symbol ReV0.53 #545316 / Ballout_Rev0_71 #543787 / PEGA local PN is 4201-0062000
U0301A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK EXT_SMI#_R EXT_SMI#
DDPC_CTRLDATA
12
DP_COMP
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22
N12
GPP_E23
E52
eDP_RCOMP
947859
0101-03860PB
DDI
DISPLAY SIDEBANDS
EDP
3
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
RSVD_1
RSVD_2
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
eDP_BKLTEN
eDP_BKLTCTL
eDP_VDDEN
EDP_TXN0
C47
EDP_TXP0
C46
EDP_TXN1
D46
EDP_TXP1
C45
A45
B45
A47
B47
EDP_AUXN
E45
EDP_AUXP
F45
B52
G50
F50
E48
F48
G46
F46
DPB_HPD
L9
L7
L6
EXT_SCI#_R EXT_SCI#
N9
eDP_HPD
L10
LCD_BKLTEN_PCH
R12
LCD_BL_PWM_PCH
R11
EDP_VDD_EN
U13
R0302 0Ohm
R0303 0Ohm
1 2
1 2
EDP_TXN0 45
EDP_TXP0 45
EDP_TXN1 45
EDP_AUXN 45
EDP_AUXP 45
EDP_TXP1 45
2
DPB_HPD 48
EXT_SMI# 30,44
EXT_SCI# 30
eDP_HPD 45
LCD_BKLTEN_PCH 21,45
LCD_BL_PWM_PCH 45
EDP_VDD_EN 45
+VCCIO
+VCCST_CPU
+VCCSTG
+3VS
1
+VCCIO 5,7,9,57,91
+VCCST_CPU 7
+VCCSTG 7
+3VS 4,20,21, 22,23,24,30,31,32,36,41,44,45,48,49,50,51,53,56,57,62,64,65,91,92
DDI#1 DDPB_CTRLDATA
DDI#2 DDPC_CTRLDATA
DDPD_CTRLDATA
- Internal weak pull down 20k ohm
- 0 : port is not detected
1 : port is deteccted
DDPB_CTRLDATA
DDPB_CTRLCLK
both pull-up deleted, HDMI side pull-up
DDPC_CTRLDATA
DDPC_CTRLCLK
EXT_SCI#
EXT_SMI#
1 2
R0305 2.2KOhm@
1 2
R0340 2.2KOhm@
1 2
R0307 10KOhm
1 2
R0308 10KOhm
HDMI HPD
eDP HPD
+3VS
+3VS
141024 follow PDG V1.0 Table 10-4
Rpu = 1K ohm 5%
12
R0311
1KOhm
H_THRMTRIP#32
B B
H_PROCHOT# H_PROCHOT#_R
Rs = 500 ohm 5%
12
R0312
1KOhm
5%
1 2
R0314 499Ohm
H_PECI_EC30
Closeer EC
1 2
R0315 43Ohm
1 2
SP0301 0Ohm
1 2
R0316 49.9Ohm
1 2
R0317 49.9Ohm
1 2
R0318 49.9Ohm
1 2
R0319 49.9Ohm
+1.0V+VCCIO+1.0V
@
T0306
12
R0313
49.9Ohm
1%
TP_CATERR#_R
H_PECI
H_THRMTRIP#_R
1
SKTOCC#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
AT16
AU16
D63
A54
C65
C63
A65
C55
D55
B54
C56
BA5
AY5
H66
H65
A6
A7
0101-03860PB
U0301D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
CPU MISC
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
947859
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
XDP_TCLK
B61
XDP_TDI_CPU
D60
XDP_TDO_CPU
A61
XDP_TMS_CPU
C60
XDP_TRST_CPU_N
B59
PCH_JTAG_TCLK
B56
XDP_TDI_CPU
D59
XDP_TDO_CPU
A56
XDP_TMS_CPU
C59
XDP_TRST_CPU_N XDP_TCLK
C61
XDP_TCLK
A59
JTAGX
1
T0315
XDP_TDO_CPU
XDP_TMS_CPU
XDP_TDI_CPU
XDP_TRST_CPU_N
R0323 51Ohm
R0324 51Ohm
12
12
+VCCIO
1
T0319
1
T0318
1
T0317
R1.2 MB_Lesson learnt template
THRO_CPU30
A A
PROCHOT#88
VR_HOT#80
1
1
G
2
S
Q0301
2N7002
5
R0341由EC control
(depends on under-shoot measurement result),預預0ohm
3
32
R0341 0Ohm
D
R0325 0Ohm
R0320 0Ohm@
觸觸觸觸觸觸觸觸觸觸觸觸觸
12
R0326 0Ohm
12
12
70-200 ohm
觸是是是是
GND
12
C0301
0.1UF/16V
4
H_PROCHOT#
CPU(1)_DDI_eDP
CPU(1)_DDI_eDP
CPU(1)_DDI_eDP
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Title :
James_Liao
James_Liao
James_Liao
3 94Thursday, February 23, 2017
3 94Thursday, February 23, 2017
3 94Thursday, February 23, 2017
Rev
Rev
Rev
1.0
1.0
1.0
12
@
5
4
3
2
1
04
M_A_D[63:0]16 M_B_D[63:0]17
D D
A_Byte_0
A_Byte_1
A_Byte_4
A_Byte_5
B_Byte_0
C C
B_Byte_1
B_Byte_5
B_Byte_6
B B
M_A_D0
M_A_D1
M_A_D2
M_A_D3
M_A_D4
M_A_D5
M_A_D6
M_A_D7
M_A_D8
M_A_D9
M_A_D10
M_A_D11
M_A_D12
M_A_D13
M_A_D14
M_A_D15
M_A_D32
M_A_D33
M_A_D34
M_A_D35
M_A_D36
M_A_D37
M_A_D38
M_A_D39
M_A_D40
M_A_D41
M_A_D42
M_A_D43
M_A_D44
M_A_D45
M_A_D46
M_A_D47
M_B_D0
M_B_D1
M_B_D2
M_B_D3
M_B_D4
M_B_D5
M_B_D6
M_B_D7
M_B_D8
M_B_D9
M_B_D10
M_B_D11
M_B_D12
M_B_D13
M_B_D14
M_B_D15
M_B_D32
M_B_D33
M_B_D34
M_B_D35
M_B_D36
M_B_D37
M_B_D38
M_B_D39
M_B_D40
M_B_D41
M_B_D42
M_B_D43
M_B_D44
M_B_D45
M_B_D46
M_B_D47
DDR_VTT_CTRL
U0301B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
947859
12
R0401
10KOhm
@
Used NIL
DDR CH - A
U0401
1
NC
A
GND
74AUP1G07GW
VCC
2
3 4
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
+1.2V
5
Y
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
12
12
C0401
0.1UF/16V
R0405
1KOhm
R1.1
M_A_DIM0_CK_DDR0_DN
AU53
M_A_DIM0_CK_DDR0_DP
AT53
AU55
AT55
M_A_DIM0_CKE0
BA56
BB56
AW56
AY56
M_A_DIM0_CS0_N
AU45
AU43
M_A_DIM0_ODT0
AT45
AT43
M_A_A5
BA51
M_A_A9 M_B_A5
BB54
M_A_A6
BA52
M_A_A8
AY52
M_A_A7
AW52
M_A_BG0
AY55
M_A_A12
AW54
M_A_A11
BA54
M_A_ACT_N
BA55
AY54
M_A_A13
AU46
M_A_A15_CAS_N
AU48
M_A_A14_WE_N
AT46
M_A_A16_RAS_N
AU50
M_A_BA0
AU52
M_A_A2
AY51
M_A_BA1
AT48
M_A_A10_AP
AT50
M_A_A1
BB50
M_A_A0
AY50
M_A_A3
BA50
M_A_A4
BB52
M_A_DQS_DN0
AM70
M_A_DQS_DP0
AM69
M_A_DQS_DN1
AT69
M_A_DQS_DP1
AT70
M_A_DQS_DN4
BA64
M_A_DQS_DP4
AY64
M_A_DQS_DN5
AY60
M_A_DQS_DP5
BA60
M_B_DQS_DN0
BA38
M_B_DQS_DP0
AY38
M_B_DQS_DN1
AY34
M_B_DQS_DP1
BA34
M_B_DQS_DN4
BA30
M_B_DQS_DP4
AY30
M_B_DQS_DN5
AY26
M_B_DQS_DP5
BA26
DDR0_A_ALERT_N
AW50
AT52
+V_DDR_CA_VREF
AY67
AY68
+V_DDR_VREFDQ02_CHB
BA67
DDR_VTT_CTRL
AW67
+3VSUS+3VS
12
R0406
220KOhm
@
DDR_PG_CTRL 83
DDR_VTT_CNTL to VTT
power ready < 35us (tCPU18)
12
R0407
2MOHM
@
Memory bus_DDR4
M_A_DIM0_CK_DDR0_DN 15,16
1 2
R0412
0Ohm /DDP
M_B_DQS_DN0 17
M_B_DQS_DP0 17
M_B_DQS_DN1 17
M_B_DQS_DP1 17
M_B_DQS_DN4 17
M_B_DQS_DP4 17
M_B_DQS_DN5 17
M_B_DQS_DP5 17
M_A_DIM0_CK_DDR0_DP 15,16
M_A_DIM0_CKE0 15,16
M_A_DIM0_CS0_N 15,16
M_A_DIM0_ODT0 15,16
M_A_A5 15,16
M_A_A9 15,16
M_A_A6 15,16
M_A_A8 15,16
M_A_A7 15,16
M_A_BG0 15,16
M_A_A12 15,16
M_A_A11 15,16
M_A_ACT_N 15,16
M_A_A13 15,16
M_A_A15_CAS_N 15,16
M_A_A14_WE_N 15,16
M_A_A16_RAS_N 15,16
M_A_BA0 15,16
M_A_A2 15,16
M_A_BA1 15,16
M_A_A10_AP 15,16
M_A_A1 15,16
M_A_A0 15,16
M_A_A3 15,16
M_A_A4 15,16
M_A_DQS_DN0 16
M_A_DQS_DP0 16
M_A_DQS_DN1 16
M_A_DQS_DP1 16
M_A_DQS_DN4 16
M_A_DQS_DP4 16
M_A_DQS_DN5 16
M_A_DQS_DP5 16
DDR0_A_ALERT_N 15,16
+V_DDR_CA_VREF 19
+V_DDR_VREFDQ02_CHB 19
M_A_BG1M_A_BG1_CPU
A_Byte_2
A_Byte_3
A_Byte_6
12
M_A_BG1 15,16
A_Byte_7
R0411
0Ohm
/SDP
B_Byte_2
B_Byte_3
B_Byte_6
B_Byte_7
M_A_D16
M_A_D17
M_A_D18
M_A_D19
M_A_D20
M_A_D21
M_A_D22
M_A_D23
M_A_D24
M_A_D25
M_A_D26
M_A_D27
M_A_D28
M_A_D29
M_A_D30
M_A_D31
M_A_D48
M_A_D49
M_A_D50
M_A_D51
M_A_D52
M_A_D53
M_A_D54
M_A_D55
M_A_D56
M_A_D57
M_A_D58
M_A_D59
M_A_D60
M_A_D61
M_A_D62
M_A_D63
M_B_D16
M_B_D17
M_B_D18
M_B_D19
M_B_D20
M_B_D21
M_B_D22
M_B_D23
M_B_D24
M_B_D25
M_B_D26
M_B_D27
M_B_D28
M_B_D29
M_B_D30
M_B_D31
M_B_D48
M_B_D49
M_B_D50
M_B_D51
M_B_D52
M_B_D53
M_B_D54
M_B_D55
M_B_D56
M_B_D57
M_B_D58
M_B_D59
M_B_D60
M_B_D61
M_B_D62
M_B_D63
DDR4_DRAMRST_N
U0301C
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
947859
+1.2V
12
R0408
470Ohm
R0409 0Ohm
Used NIL
SKL_ULT
DDR CH - B
1 2
12
C0402
0.1UF/16V
@
546765_SKL_MOW
DDR4/3L Reset signal - DRAMRST
It is recommended not to install any capacitor
on DDR Reset signal (DRAMRST).
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
R0402 and R0410 overlap
DDR4_DRAMRST_R_N 16,17
Controls reset to the memory subsystems,
and is used on DDR3L, DDR4
(not applicable to LPDDR3).
M_B_DIM0_CK_DDR0_DN
AN45
AN46
M_B_DIM0_CK_DDR0_DP
AP45
AP46
M_B_DIM0_CKE0
AN56
AP55
AN55
AP53
M_B_DIM0_CS0_N
BB42
AY42
M_B_DIM0_ODT0
BA42
AW42
AY48
M_B_A9
AP50
M_B_A6
BA48
M_B_A8
BB48
M_B_A7
AP48
M_B_BG0
AP52
M_B_A12
AN50
M_B_A11
AN48
M_B_ACT_N
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
1 2
R0413
0Ohm /DDP
M_B_A13
M_B_A15_CAS_N
M_B_A14_WE_N
M_B_A16_RAS_N
M_B_BA0
M_B_A2
M_B_BA1
M_B_A10_AP
M_B_A1
M_B_A0
M_B_A3
M_B_A4
M_A_DQS_DN2
M_A_DQS_DP2
M_A_DQS_DN3
M_A_DQS_DP3
M_A_DQS_DN6
M_A_DQS_DP6
M_A_DQS_DN7
M_A_DQS_DP7
M_B_DQS_DN2
M_B_DQS_DP2
M_B_DQS_DN3
M_B_DQS_DP3
M_B_DQS_DN6
M_B_DQS_DP6
M_B_DQS_DN7
M_B_DQS_DP7
DDR1_B_ALERT_NDDR0_A_PARITY
DDR1_B_PARITY
DDR4_DRAMRST_N
SM_RCOMP_0
R0402 121OHM1% /DDP
SM_RCOMP_1
R0403 80.6Ohm1%
SM_RCOMP_2
R0404 100Ohm1%
SM_RCOMP_0
RCOMP[0] value for SDP is 200+/-1% ohm, and for DDP is 121+/- 1% ohm
+1.2V
M_B_DIM0_CK_DDR0_DN 15,17
M_B_DIM0_CK_DDR0_DP 15,17
M_B_DIM0_CKE0 15,17
M_B_DIM0_CS0_N 15,17
M_B_DIM0_ODT0 15,17
M_B_A5 15,17
M_B_A9 15,17
M_B_A6 15,17
M_B_A8 15,17
M_B_A7 15,17
M_B_BG0 15,17
M_B_A12 15,17
M_B_A11 15,17
M_B_ACT_N 15,17
M_B_BG1M_B_BG1_CPU
M_B_A13 15,17
M_B_A15_CAS_N 15,17
M_B_A14_WE_N 15,17
M_B_A16_RAS_N 15,17
M_B_BA0 15,17
M_B_A2 15,17
M_B_BA1 15,17
M_B_A10_AP 15,17
M_B_A1 15,17
M_B_A0 15,17
M_B_A3 15,17
M_B_A4 15,17
M_A_DQS_DN2 16
M_A_DQS_DP2 16
M_A_DQS_DN3 16
M_A_DQS_DP3 16
M_A_DQS_DN6 16
M_A_DQS_DP6 16
M_A_DQS_DN7 16
M_A_DQS_DP7 16
M_B_DQS_DN2 17
M_B_DQS_DP2 17
M_B_DQS_DN3 17
M_B_DQS_DP3 17
M_B_DQS_DN6 17
M_B_DQS_DP6 17
M_B_DQS_DN7 17
M_B_DQS_DP7 17
DDR1_B_ALERT_N 15,17DDR0_A_PARITY 15,16
DDR1_B_PARITY 15,17
1 2
1 2
1 2
1 2
R0410 200Ohm 10V220000034
/SDP
EMI
@
1 2
C0403 0.1UF/16V
M_B_BG1 15,17
12
R0414
0Ohm
/SDP
Symbol U0301 B
A A
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
ChannelA DQ[0..63]
DQS/DQS#[0..7]
5
Non-interleavedinterleaved(Symbol default)
ChannelA DQ[0..15]
DQS/DQS#[0,1]
ChannelADQ[32..47]
DQS/DQS#[4,5]
ChannelB DQ[0..15]
DQS/DQS#[0,1]
ChannelB DQ[32..47]
DQS/DQS#[4,5]
Symbol U0301 C
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
ChannelB DQ[0..63]
DQS/DQS#[0..7]
4
Non-interleavedinterleaved(Symbol default)
ChannelA DQ[16..31]
DQS/DQS#[2,3]
ChannelADQ[48..63]
DQS/DQS#[6,7]
ChannelB DQ[16..31]
DQS/DQS#[2,3]
ChannelB DQ[48..63]
DQS/DQS#[6,7]
Title :
Title :
Title :
Memory bus_DDR4
Memory bus_DDR4
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Memory bus_DDR4
James_Liao
James_Liao
James_Liao
4 94Thursday, February 23, 2017
4 94Thursday, February 23, 2017
4 94Thursday, February 23, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
05
D D
C C
R1.1 follow int el PDG_James
+VCORE
12
C0511
1UF/6.3V@
12
12
C0518
C0519
1UF/6.3V@
1UF/6.3V@
12
12
C0525
C0526
1UF/6.3V@
1UF/6.3V@
12
12
C0544
@
47UF/6.3V
@
C0545
47UF/6.3V
12
C0509
1UF/6.3V@
12
C0523
1UF/6.3V@
12
C0547
47UF/6.3V
@
12
C0510
1UF/6.3V@
12
C0524
1UF/6.3V@
12
C0548
47UF/6.3V
12
12
C0514
C0515
1UF/6.3V@
1UF/6.3V@
12
12
C0543
C0522
1UF/6.3V@
1UF/6.3V@
12
12
C0528
C0529
1UF/6.3V@
1UF/6.3V@
12
C0513
1UF/6.3V@
12
C0530
1UF/6.3V@
12
C0527
1UF/6.3V@
12
C0542
@
1UF/6.3V@
CPU(3)_+VCCCORE
+VCORE +VCORE
AK33
AK35
AK37
AK38
AK40
AM32
AM33
AM35
AM37
AM38
AK32
AB62
AC63
AE63
AE62
AG62
AL33
AL37
AL40
AL63
AJ62
A30
A34
A39
A44
G30
K32
P62
V62
H63
G61
U0301L
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
RSVD_3
RSVD_4
VCCOPC_1
VCCOPC_2
VCCOPC_3
VCC_OPC_1P8_1
VCC_OPC_1P8_2
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO_1
VCCEOPIO_2
VCCEOPIO_SENSE
VSSEOPIO_SENSE
947859
0101-03860PB
CPU POWER 1 OF 4
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
Pull H/L near CPU side
1 2
R0536 100Ohm1%
1 2
R0537 100Ohm1%
VIDALERT#
VIDSCK
VIDSOUT
+VCCIO
+VCORE
VCORE_VCCSENSE 80
VCORE_VSSSENSE 80
1 2
R0517 220Ohm1%
1 2
R0518 0Ohm
1 2
R0519 0Ohm
CPU side VR side
+1.0V
12
R0520
56Ohm
1%
VIDALERT#_R
VIDSCK_R
+1.0V
12
R0521
100Ohm
1%
VIDSOUT_R
2016.03.18
R0524,R0522,R0525,R0523,R0526 and C0505 close to U8000
1 2
R0524 0Ohm
+1.0V
12
12
R0522
C0505
0.1UF/16V
45.3Ohm
+1.0V
1%
12
R0523
100Ohm
1%
1 2
R0525 51Ohm1%
1 2
R0526 10Ohm1%
VR_SVID_ALERT# 80
VR_SVID_CLK 80
VR_SVID_DATA 80
B B
A A
CPU(3)_+VCCCORE
CPU(3)_+VCCCORE
CPU(3)_+VCCCORE
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Title :
James_Liao
James_Liao
James_Liao
5 94Thursday, February 23, 2017
5 94Thursday, February 23, 2017
5 94Thursday, February 23, 2017
Rev
Rev
Rev
1.0
1.0
1.0
06
5
CPU(4)_+VCCGT
4
3
2
1
R1.1 follow int el PDG
+VCORE_U42_+VCCGT_U22+VCORE
1 2
R0601 0ohm/U42
D D
1 2
R0602 0ohm/U22
R0601~R0606
20161212 R1.1 Kai
change to VX
20161223 R1.1 James
change package size from 0805 to 0603
20161223 R1.1 Kai
change VX to P/N, for layout
U22
R1.2
+VCORE_U42_+VCCGT_U22
12
C0630
1UF/6.3V
/U42
12
C0633
1UF/6.3V
/U42
C C
VCCGT_VCCSENSE80
VCCGT_VSSSENSE80
12
12
C0631
1UF/6.3V
/U42
C0634
1UF/6.3V
/U42
12
C0632
1UF/6.3V
/U42
12
C0635
1UF/6.3V
/U42
VCCGT_VCCSENSE
VCCGT_VSSSENSE
R1.1 short pin
to 0 ohm
+VCCGT
R0609
100Ohm
1%
1 2
Pull H/L near CPU side
12
R0610
100Ohm
1%
Pull H/L near CPU side
+VCCGT
R0607 0Ohm/U22
1 2
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
U0301M
CPU POWER 2 OF 4
VCCGT_1
VCCGT_2
VCCGT_3
VCCGT_4
VCCGT_5
VCCGT_6
VCCGT_7
VCCGT_8
VCCGT_9
VCCGT_10
VCCGT_11
VCCGT_12
VCCGT_13
VCCGT_14
VCCGT_15
VCCGT_16
VCCGT_17
VCCGT_18
VCCGT_19
VCCGT_20
VCCGT_21
VCCGT_22
VCCGT_23
VCCGT_24
VCCGT_25
VCCGT_26
VCCGT_27
VCCGT_28
VCCGT_29
VCCGT_30
VCCGT_31
VCCGT_32
VCCGT_33
VCCGT_34
VCCGT_35
VCCGT_36
VCCGT_37
VCCGT_38
VCCGT_39
VCCGT_40
VCCGT_41
VCCGT_42
VCCGT_43
VCCGT_44
VCCGT_45
VCCGT_46
VCCGT_47
VCCGT_48
VCCGT_49
VCCGT_50
VCCGT_51
VCCGT_52
VCCGT_53
VCCGT_54
VCCGT_55
VCCGT_SENSE
VSSGT_SENSE
947859
0101-03860PB
VCCGT_56
VCCGT_57
VCCGT_58
VCCGT_59
VCCGT_60
VCCGT_61
VCCGT_62
VCCGT_63
VCCGT_64
VCCGT_65
VCCGT_66
VCCGT_67
VCCGT_68
VCCGT_69
VCCGT_70
VCCGT_71
VCCGT_72
VCCGT_73
VCCGT_74
VCCGT_75
VCCGT_76
VCCGT_77
VCCGT_78
VCCGT_79
VCCGT_80
VccGTx_1
VccGTx_2
VccGTx_3
VccGTx_4
VccGTx_5
VccGTx_6
VccGTx_7
VccGTx_8
VccGTx_9
VccGTx_10
VccGTx_11
VccGTx_12
VccGTx_13
VccGTx_14
VccGTx_15
VccGTx_16
VccGTx_17
VccGTx_18
VccGTx_19
VccGTx_20
VccGTx_21
VccGTx_22
VccGTx_23
VccGTx_24
VccGTx_25
VccGTx_26
VccGTx_27
VccGTx_28
VccGTx_29
VCCGTx_SENSE
VSSGTx_SENSE
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCCGT
U42U42
+VCORE_U42_+VCCGTx_U23
R0603 0ohm/U42
1 2
+VCORE
+VCCGT
12
12
12
12
C0602
10UF/6.3V
@
C0628
47UF/6.3V
@
C0616
1UF/6.3V
@
C0623
1UF/6.3V
@
12
12
12
C0603
10UF/6.3V
@
C0629
47UF/6.3V
@
C0618
1UF/6.3V
@
12
12
12
12
C0605
10UF/6.3V
@
C0610
10UF/6.3V
@
C0617
1UF/6.3V
@
C0624
1UF/6.3V
@
12
12
12
12
C0604
10UF/6.3V
@
C0609
10UF/6.3V
@
C0614
1UF/6.3V
@
C0621
1UF/6.3V
@
12
12
12
12
C0606
10UF/6.3V
@
C0611
10UF/6.3V
@
C0615
1UF/6.3V
@
C0622
1UF/6.3V
@
12
12
12
C0607
10UF/6.3V
@
C0612
10UF/6.3V
@
C0619
1UF/6.3V
@
12
12
12
C0608
10UF/6.3V
@
C0613
10UF/6.3V
@
C0620
1UF/6.3V
@
12
C0627
1UF/6.3V
@
B B
A A
CPU(4)_+VCCGT
CPU(4)_+VCCGT
CPU(4)_+VCCGT
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Title :
James_Liao
James_Liao
James_Liao
6 94Friday, March 10, 2017
6 94Friday, March 10, 2017
6 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
07
D D
12
12
C0734
10UF/6.3V
@
C0738
10UF/6.3V
@
+VDDQ_CPU
12
C0701
10UF/6.3V
12
C0733
10UF/6.3V
@
12
C0739
10UF/6.3V
@
12
C0702
10UF/6.3V
12
C0735
10UF/6.3V
@
12
C0740
10UF/6.3V
@
12
C0703
10UF/6.3V
12
C0736
10UF/6.3V
@
12
C0741
10UF/6.3V
@
12
C0704
10UF/6.3V
+VDDQ_CPU
12
C0737
10UF/6.3V
@
12
C0742
10UF/6.3V
@
12
12
C0705
C0706
10UF/6.3V
10UF/6.3V
1 2
R0701 0Ohm
R2.0_0816
+VCCST_CPU
12
+VCCSTG
12
+VCCSFR_OC
12
+VCCSFR
12
C0712
1UF/6.3V
C0713
1UF/6.3V
+1.2V
R1.1
JP0701
2
112
3MM_OPEN_5MIL
JP0702
2
112
3MM_OPEN_5MIL
R1.1 follow int el PDG
+VCCSA
12
12
C0731
C C
12
B B
10UF/6.3V
@
C0743
47UF/6.3V
@
12
C0732
10UF/6.3V
@
C0744
47UF/6.3V
@
CPU(5)_+VDDQ/IO/SA
C0701 - C0704 : Near by package
C0705 - C0710 : Underneath the package
12
+VDDQ_CPU_CLK
C0714
0.1UF/16V
C0715
0.1UF/16V
C0707
1UF/6.3V
12
C0711
10UF/6.3V
1AV200000074
vx_c0402_h28_small
12
C0716
0.1UF/16V
12
12
C0708
1UF/6.3V
Decoupling cap for internal power
C0709
1UF/6.3V
12
2.8A
C0710
1UF/6.3V
0.1A
+1.0V
R0710 0Ohm
+1.0V +VCCSFR
R0711 0Ohm
R0709 0Ohm
RES 0 OHM 1/10W (0603) JUMP
+VCCIO
R0713 0Ohm
U0301N
CPU POWER 3 OF 4
AU23
VDDQ_1
AU28
VDDQ_2
AU35
VDDQ_3
AU42
VDDQ_4
BB23
VDDQ_5
BB32
VDDQ_6
BB41
VDDQ_7
BB47
VDDQ_8
BB51
VDDQ_9
AM40
VDDQC
A18
VCCST
A22
VCCSTG
AL23
VCCPLL_OC
K20
VccPLL_1
K21
VccPLL_2
947859
0101-03860PB
1 2
RES 0 OHM 1/10W (0603) JUMP
1 2
RES 0 OHM 1/10W (0603) JUMP
1 2
1 2
RES 0 OHM 1/10W (0603) JUMP
+VCCST_CPU
0.24A0.24A
0.24A0.24A
+VCCSFR_OC+1.2V
+VCCSTG
0.12A0.12A
VCCIO_1
VCCIO_2
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCSA_1
VCCSA_2
VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6
VCCSA_7
VCCSA_8
VCCSA_9
VCCSA_10
VCCSA_11
VCCSA_12
VCCSA_13
VCCSA_14
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
Refer to CRB 0.53
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
VCCIO_VR_FB
VSSIO_VR_FB
4.5A
12
12
C0718
C0717
1UF/6.3V
1UF/6.3V
VCCSA_VSSSENSE 80
VCCSA_VCCSENSE 80
VCCSA_VCCSENSE
VCCSA_VSSSENSE
12
C0719
1UF/6.3V
+VCCIO
+VCCSA
12
C0720
1UF/6.3V
R0720
100Ohm
1%
1 2
R0721
100Ohm
1%
1 2
+VCCSA
+VCCIO
12
12
R0714
1KOhm
@
R0715
1KOhm
@
Reserved PH/PD
A A
CPU(5)_+VDDQ/IO/SA
CPU(5)_+VDDQ/IO/SA
CPU(5)_+VDDQ/IO/SA
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Title :
James_Liao
James_Liao
James_Liao
7 94Thursday, February 23, 2017
7 94Thursday, February 23, 2017
7 94Thursday, February 23, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
08
AA65
AA68
AB15
AB16
AB18
AB21
AD13
AD16
AD19
AD20
AD21
AD62
AE64
AE65
AE66
AE67
AE68
AE69
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH63
AH64
AH67
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AF10
AF15
AF17
AF63
AJ15
AJ18
AJ20
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
A5
A67
A70
AA2
AA4
AB8
AD8
AF1
AF2
AF4
AH6
AJ4
AK8
AL2
AL4
U0301P
GND 1 OF 3
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
947859
0101-03860PB
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
D D
C C
B B
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
BA10
BA14
BA18
BA23
BA28
BA32
BA36
BA45
AV1
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA2
F68
U0301Q
GND 2 OF 3
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
947859
0101-03860PB
CPU(6)_CPU GND
BA49
VSS_209
BA53
VSS_210
BA57
VSS_211
BA6
VSS_212
BA62
VSS_213
BA66
VSS_214
BA71
VSS_215
BB18
VSS_216
BB26
VSS_217
BB30
VSS_218
BB34
VSS_219
BB38
VSS_220
BB43
VSS_221
BB55
VSS_222
BB6
VSS_223
BB60
VSS_224
BB64
VSS_225
BB67
VSS_226
BB70
VSS_227
C1
VSS_228
C25
VSS_229
C5
VSS_230
D10
VSS_231
D11
VSS_232
D14
VSS_233
D18
VSS_234
D22
VSS_235
D25
VSS_236
D26
VSS_237
D30
VSS_238
D34
VSS_239
D39
VSS_240
D44
VSS_241
D45
VSS_242
D47
VSS_243
D48
VSS_244
D53
VSS_245
D58
VSS_246
D6
VSS_247
D62
VSS_248
D66
VSS_249
D69
VSS_250
E11
VSS_251
E15
VSS_252
E18
VSS_253
E21
VSS_254
E46
VSS_255
E50
VSS_256
E53
VSS_257
E56
VSS_258
E6
VSS_259
E65
VSS_260
E71
VSS_261
F1
VSS_262
F13
VSS_263
F2
VSS_264
F22
VSS_265
F23
VSS_266
F27
VSS_267
F28
VSS_268
F32
VSS_269
F33
VSS_270
F35
VSS_271
F37
VSS_272
F38
VSS_273
F4
VSS_274
F40
VSS_275
F42
VSS_276
BA41
VSS_277
F8
G10
G22
G43
G45
G48
G5
G52
G55
G58
G6
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42
J8
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
U0301R
GND 3 OF 3
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
947859
0101-03860PB
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
A A
CPU(6)_CPU GND
CPU(6)_CPU GND
CPU(6)_CPU GND
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Title :
James_Liao
James_Liao
James_Liao
8 94Monday, February 20, 2017
8 94Monday, February 20, 2017
8 94Monday, February 20, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
CPU(7)_CFG/RSVD
09
U0301S
CFG0
T0901
CFG16
CFG17
CFG18
CFG19
1
CFG2
CFG3
CFG4
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG_RCOMP
ITP_PMODE
RSVD_VSS_F65
RSVD_VSS_G65
1
D D
T0923
T0924
T0925
T0926
T0927
T0928
T0929
T0930
T0931
T0919
T0920
T0921
T0922
1
1
1
1
1
1
1
1
1
1
1
1
1 2
R0901 49.9Ohm1%
Reserve TP for XDP
C C
1
T0917
1
T0918
Remove SNN
+VCCIO
R0906
1 2
10KOhm
@
1%
1 2
R0908 10KOhm
@
B B
1%
1 2
R0910 10KOhm
@
1%
CFG0
CFG2
CFG4
E68
CFG[0]
B67
CFG[1]
D65
CFG[2]
D67
CFG[3]
E70
CFG[4]
C68
CFG[5]
D68
CFG[6]
C67
CFG[7]
F71
CFG[8]
G69
CFG[9]
F70
CFG[10]
G68
CFG[11]
H70
CFG[12]
G71
CFG[13]
H69
CFG[14]
G70
CFG[15]
E63
CFG[16]
F63
CFG[17]
E66
CFG[18]
F66
CFG[19]
E60
CFG_RCOMP
E8
ITP_PMODE
AY2
RSVD_5
AY1
RSVD_6
D1
RSVD_7
D3
RSVD_8
K46
RSVD_9
K45
RSVD_10
AL25
RSVD_11
AL27
RSVD_12
C71
RSVD_13
B70
RSVD_14
F60
RSVD_15
A52
RSVD_16
BA70
RSVD_TP_1
BA68
RSVD_TP_2
J71
RSVD_17
J68
RSVD_18
F65
VSS_360
G65
VSS_361
F61
RSVD_19
E61
RSVD_20
947859
0101-03860PB
1 2
R0922 1KOhm@
1 2
R0924 1KOhm@
1 2
R0926 1KOhm
4
RESERVED SIGNALS-1
PROC_SELECT#
PDG 1.2
Placeholder only. Does not need to be stuffed.
Placement are required for future platform compatibility purpose only.
RSVD_TP_3
RSVD_TP_4
RSVD_TP_5
RSVD_TP_6
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
RSVD_28
RSVD_29
RSVD_30
RSVD_31
RSVD_32
RSVD_33
RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38
RSVD_39
RSVD_40
RSVD_41
RSVD_42
VSS_362
RSVD_TP_7
RSVD_TP_8
+1.8VSUS
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
AR56
ZVM#
AW71
AW70
AP56
MSM#
C64
1 2
R0930 0Ohm@
1 2
R0931 0Ohm@
RSVD_AY3
VSS_AY71
SKL_CNL#
VCC_1P8_U12
VCC_1P8_U11
12
C0901
0.1UF/16V
@
12
3
C0902
0.1UF/16V
@
1 2
R0902 0Ohm
1 2
R0903 0Ohm
U0301T
AW69
RSVD_43
AW68
RSVD_44
AU56
RSVD_45
AW48
RSVD_46
C7
RSVD_47
U12
RSVD_48
U11
RSVD_49
H11
RSVD_50
947859
0101-03860PB
R0904 100KOhm@
SPARE
1 2
RSVD_51
RSVD_52
RSVD_53
RSVD_54
RSVD_55
RSVD_56
RSVD_57
RSVD_58
2
MOW WW48
+1.0V
1. Ball C64 which is PROC_SELECT# needs to be pulled to VCCST for
Cannonlake support via 100K ohm resistor and with no resistor populated
(floating pin) for Skylake.
F6
U42_XTAL24_IN
E3
C11
B11
A11
D12
C12
F52
U42_XTAL24_OUT U42_XTAL24_OUT_R_R
1 2
R0940 0Ohm
/U42
10V240000001
U42_XTAL24_OUT_R
1 2
R0941 0Ohm
/U42
10V240000001
U42_XTAL24_IN_R
12
R0932
1MOhm
/U42
10V240000006
SP0910 0Ohm
07V080000024
X0901
24MHZ
/U42
1 2
13
2
4
1
1 2
C0903 10PF/50V
1AV200000001/U42
C0904
1 2
10PF/50V
1AV200000001/U42
GND
GND
GND
1 2
R0913 10KOhm
@
1%
A A
The CFG signals have a default value of '1' if not terminated on the board.
*All processor lines.
CFG[2], CFG[6:5] and CFG[7] are relevant for H and S-processor line only
and test point may be placed on the board for them
5
CFG7
1 2
R0929 1KOhm@
Name
P5HCJ_KBL
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG[19:8] Reserved configuration lane
1 = (Default) Normal Operation; No stall
1
0 = Stall
Reserved configuration lane
1
PCI Express* Static x16 Lane Numbering Reversal
1
1 = Normal operation
0 = Lane numbers reversed
Reserved configuration lane
1
CFG[4]: eDP* enable:
0
1 = Disabled.
0 = Enabled
CFG[6:5]: PCI Express* Bifurcation
00 = 1 x8, 2 x4 PCI Express*
1
01 = reserved
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
1 = (default) PEG Train immediately following
1
RESET# de assertion
0 = PEG Wait for BIOS for training.
1
Description
From EDS_Intel_CPU(Kabylake.UY)_Vol1_559100_Rev0p91 Page.123
4
CPU(7)_CFG/RSVD
CPU(7)_CFG/RSVD
CPU(7)_CFG/RSVD
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Title :
James_Liao
James_Liao
James_Liao
9 94Friday, March 10, 2017
9 94Friday, March 10, 2017
9 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
D D
C C
4
3
2
1
B B
Title :
Title :
A A
5
4
3
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
SU4EA
SU4EA
A
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
SU4EA
Title :
Engineer:
Engineer:
Engineer:
Block Diagram
Block Diagram
Block Diagram
James_Liao
James_Liao
James_Liao
10 94Friday, March 10, 2017
10 94Friday, March 10, 2017
10 94Friday, March 10, 2017
1
Rev
Rev
Rev
1.0
1.0
1.0
5
D D
C C
4
3
2
1
B B
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
<Title>
<Title>
<Title>
SU4EA <RevCode>
A
SU4EA <RevCode>
A
SU4EA <RevCode>
A
11 94Friday, March 10, 2017
11 94Friday, March 10, 2017
2
11 94Friday, March 10, 2017
1
5
D D
C C
4
3
2
1
B B
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
<Title>
<Title>
<Title>
SU4EA <RevCode>
A
SU4EA <RevCode>
A
SU4EA <RevCode>
A
12 94Friday, March 10, 2017
12 94Friday, March 10, 2017
2
12 94Friday, March 10, 2017
1
5
D D
C C
4
3
2
1
B B
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
<Title>
<Title>
<Title>
SU4EA <RevCode>
A
SU4EA <RevCode>
A
SU4EA <RevCode>
A
13 94Friday, March 10, 2017
13 94Friday, March 10, 2017
2
13 94Friday, March 10, 2017
1
5
D D
C C
4
3
2
1
B B
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
<Title>
<Title>
<Title>
SU4EA <RevCode>
A
SU4EA <RevCode>
A
SU4EA <RevCode>
A
14 94Friday, March 10, 2017
14 94Friday, March 10, 2017
2
14 94Friday, March 10, 2017
1
5
DDR4(0)_Termination
15
+0.6VS
36OHM1%N/A
1 2
R1501
D D
CHA
C C
R1502
R1503
R1504
R1505
R1506
R1507
R1508
R1509
R1510
R1511
R1512
R1513
R1514
R1515
R1516
R1529
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
36OHM1%N/A
1 2
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10_AP
M_A_A11
M_A_A12
M_A_A13
M_A_A14_WE_N
M_A_A15_CAS_N
M_A_A16_RAS_N
4
M_A_A0 4,16
M_A_A1 4,16
M_A_A2 4,16
M_A_A3 4,16
M_A_A4 4,16
M_A_A5 4,16
M_A_A6 4,16
M_A_A7 4,16
M_A_A8 4,16
M_A_A9 4,16
M_A_A10_AP 4,16
M_A_A11 4,16
M_A_A12 4,16
M_A_A13 4,16
M_A_A14_WE_N 4,16
M_A_A15_CAS_N 4,16
M_A_A16_RAS_N 4,16
3
+0.6VS
36OHM1%N/A
1 2
M_A_DIM0_CS0_N4,16
M_A_DIM0_CKE04,16
M_A_BG14,16
M_A_BG04,16
M_A_BA04,16
M_A_BA14,16
M_A_DIM0_ODT04,16
M_A_ACT_N4,16
DDR0_A_PARITY4,16
M_A_DIM0_CK_DDR0_DN4,16
M_A_DIM0_CK_DDR0_DP4,16
12
C1521
3300PF/25V
@
DDR0_A_ALERT_N4,16
R1521
36OHM1%N/A
1 2
R1522
+0.6VS
36OHM
N/A
1%
N/A
1%
N/A
1%
N/A
1%
N/A
1%
N/A
1%
N/A
1%
N/A
R1536
R1537
R1535 49.9Ohm1%
36OHM
36OHM
36OHM
36OHM
36OHM
36OHM
36OHM1%N/A
1 2
36OHM1%N/A
1 2
1 2
12
R1517
12
R1523
12
R1524
12
R1525
12
R1530
12
R1532
12
R1534
+0.6VS
+1.2V
2
Average placed close to +VDDQ_VTT power plane
+0.6VS
12
X5R/10%
vx_c0402_small
N/A
+0.6VS
X5R/10%
vx_c0402_small
N/A
C1501
1UF/6.3V
12
C1532
1UF/6.3V
+0.6VS
12
N/A
C1511
10UF/6.3V
X5R/20%
vx_c0603_small
12
C1502
1UF/6.3V
X5R/10%
vx_c0402_small
N/A
12
C1535
1UF/6.3V
X5R/10%
vx_c0402_small
N/A
12
vx_c0603_small
N/A
C1515
10UF/6.3V
X5R/20%
12
C1503
1UF/6.3V
X5R/10%
vx_c0402_small
N/A
12
C1538
1UF/6.3V
X5R/10%
vx_c0402_small
N/A
+0.6VS
12
N/A
C1539
10UF/6.3V
X5R/20%
vx_c0603_small
12
C1504
1UF/6.3V
X5R/10%
vx_c0402_small
N/A
12
C1531
1UF/6.3V
X5R/10%
vx_c0402_small
N/A
vx_c0603_small
12
C1540
10UF/6.3V
X5R/20%
1
R1.1 follow int el PDG
12
12
N/A
X5R/10%
vx_c0402_small
12
N/A
X5R/10%
vx_c0402_small
N/A
C1505
1UF/6.3V
C1537
1UF/6.3V
C1506
1UF/6.3V
N/A
X5R/10%
vx_c0402_small
12
C1536
1UF/6.3V
N/A
X5R/10%
vx_c0402_small
+0.6VS
12
C1524
10UF/6.3V
X5R/20%
vx_c0603_small
@
12
C1507
1UF/6.3V
N/A
X5R/10%
vx_c0402_small
12
C1533
1UF/6.3V
N/A
X5R/10%
vx_c0402_small
12
N/A
X5R/10%
vx_c0402_small
12
N/A
X5R/10%
vx_c0402_small
12
@
C1525
10UF/6.3V
X5R/20%
vx_c0603_small
C1508
1UF/6.3V
C1534
1UF/6.3V
+0.6VS
36OHM1%/CHB
1 2
/CHB
/CHB
/CHB
/CHB
/CHB
/CHB
/CHB
/CHB
1%
1%
1%
1%
1%
1%
1%
R1538
R1541
R1539 49.9Ohm1%
R1554
1 2
R1542
36OHM
36OHM
36OHM
36OHM
36OHM
36OHM
36OHM
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
1 2
36OHM1%/CHB
12
R1518
12
R1546
12
R1549
12
R1553
12
R1560
12
R1558
12
R1547
+0.6VS
+0.6VS
+1.2V
+0.6VS
12
C1520
1UF/6.3V
X5R/10%
vx_c0402_small
/CHB
+0.6VS
12
/CHB
C1509
10UF/6.3V
X5R/20%
vx_c0603_small
+0.6VS
12
vx_c0402_small
/CHB
C1543
1UF/6.3V
X5R/10%
2
12
C1518
1UF/6.3V
X5R/10%
vx_c0402_small
/CHB
12
/CHB
C1510
10UF/6.3V
X5R/20%
vx_c0603_small
12
C1541
1UF/6.3V
X5R/10%
vx_c0402_small
/CHB
12
C1519
1UF/6.3V
X5R/10%
vx_c0402_small
/CHB
+0.6VS
12
C1549
10UF/6.3V
X5R/20%
vx_c0603_small
12
C1547
1UF/6.3V
X5R/10%
vx_c0402_small
/CHB
/CHB
12
C1517
1UF/6.3V
X5R/10%
vx_c0402_small
vx_c0402_small
/CHB
12
/CHB
C1550
10UF/6.3V
X5R/20%
vx_c0603_small
12
C1548
1UF/6.3V
X5R/10%
vx_c0402_small
/CHB
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
+0.6VS
36OHM1%/CHB
1 2
R1555
36OHM1%/CHB
1 2
R1561
B B
CHB
A A
5
R1563
R1540
R1543
R1544
R1545
R1548
R1552
R1557
R1559
R1562
R1565
R1551
R1556
R1550
R1564
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
36OHM1%/CHB
1 2
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10_AP
M_B_A11
M_B_A12
M_B_A13
M_B_A14_WE_N
M_B_A15_CAS_N
M_B_A16_RAS_N
M_B_A0 4,17
M_B_A1 4,17
M_B_A2 4,17
M_B_A3 4,17
M_B_A4 4,17
M_B_A5 4,17
M_B_A6 4,17
M_B_A7 4,17
M_B_A8 4,17
M_B_A9 4,17
M_B_A10_AP 4,17
M_B_A11 4,17
M_B_A12 4,17
M_B_A13 4,17
M_B_A14_WE_N 4,17
M_B_A15_CAS_N 4,17
M_B_A16_RAS_N 4,17
4
M_B_DIM0_CK_DDR0_DN4,17
M_B_DIM0_CK_DDR0_DP4,17
M_B_DIM0_CS0_N4,17
M_B_DIM0_CKE04,17
M_B_BG14,17
M_B_BG04,17
M_B_BA04,17
M_B_BA14,17
M_B_DIM0_ODT04,17
M_B_ACT_N4,17
DDR1_B_PARITY4,17
12
C1523
3300PF/25V
@
DDR1_B_ALERT_N4,17
3
R1.1 follow int el PDG
12
12
X5R/10%
C1516
1UF/6.3V
/CHB
+0.6VS
vx_c0603_small
12
X5R/10%
C1545
1UF/6.3V
/CHB
vx_c0402_small
X5R/10%
C1514
1UF/6.3V
/CHB
vx_c0402_small
12
@
C1526
10UF/6.3V
X5R/20%
12
vx_c0402_small
SU4EA
SU4EA
SU4EA
X5R/10%
C1544
1UF/6.3V
/CHB
12
X5R/10%
C1513
1UF/6.3V
/CHB
vx_c0402_small
12
@
C1527
10UF/6.3V
X5R/20%
vx_c0603_small
12
X5R/10%
C1546
1UF/6.3V
/CHB
vx_c0402_small
Engineer:
Engineer:
Engineer:
1
12
vx_c0402_small
Title :
Title :
Title :
X5R/10%
C1512
1UF/6.3V
/CHB
12
X5R/10%
C1542
1UF/6.3V
/CHB
vx_c0402_small
DDR4(0)_Termination
DDR4(0)_Termination
DDR4(0)_Termination
15 94Friday, March 10, 2017
15 94Friday, March 10, 2017
15 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
DDR4(1)_CH0
16
M_A_D[0:6 3] 4
D D
M_A_A04,15
M_A_A14,15
M_A_A24,15
M_A_A34,15
M_A_A44,15
M_A_A54,15
M_A_A64,15
M_A_A74,15
M_A_A84,15
M_A_A94,15
M_A_A10 _AP4,15
M_A_A114,15
M_A_A124,15
M_A_A134,15
M_A_A14 _WE_N4,15
M_A_A15 _CAS_N4,15
M_A_A16 _RAS_N4,15
M_A_ACT _N4,15
M_A_BA04,15
M_A_BA14,15
M_A_BG04,15
DDR0_A _PARIT Y4,15
M_A_DIM0 _CS0_N4,15
M_A_DIM0 _ODT04,15
M_A_DIM0 _CKE04,15
M_A_DIM0 _CK_DD R0_DP4,15
M_A_DIM0 _CK_DD R0_DN4,15
DDR0_A _ALERT _N4,15
M_A_DIM0 _CK_DD R0_DP
M_A_DIM0 _CK_DD R0_DN
20161101 SWAP
+1.2V
M_A_DQS _DP04
M_A_DQS _DN04
20161101 SWAP
C C
DDR4_D RAMRST_ R_N4 ,17
+1.2V
M_A_DQS _DP14
M_A_DQS _DN14
DDR4_D RAMRST_ R_N
12
C1605
0.1UF/16V
@
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10 _AP
M_A_A11
M_A_A12
M_A_A13
M_A_A14 _WE_N
M_A_A15 _CAS_N
M_A_A16 _RAS_N
M_A_ACT _N
M_A_BA0
M_A_BA1
M_A_BG0
DDR0_A _PARIT Y
M_A_DIM0 _CS0_N
M_A_DIM0 _ODT0
M_A_DIM0 _CKE0
DDR0_A _ALERT _N
M_A_D6
M_A_D1
M_A_D2
M_A_D5
M_A_D7
M_A_D4
M_A_D3
M_A_D0
M_A_DQS _DP0
M_A_DQS _DN0
M_A_D11
M_A_D13
M_A_D15
M_A_D12
M_A_D14
M_A_D8
M_A_D10
M_A_D9
M_A_DQS _DP1
M_A_DQS _DN1
U1601
256M x 16 (4Gbit)
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC_n
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
E7
NF/LDM_n/LDBI_n
G3
LDQS_t
F3
LDQS_c
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
E2
NF/UDM_n/UDBI_n
B7
UDQS_t
A7
UDQS_c
P1
RESET_n
MT40A25 6M16GE-0 83E
DDR4
VDD_10
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VREFCA
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VPP_1
VPP_2
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
+1.2V
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
+2P5VPP +2P5VPP
J2
J8
B1
R9
M1
F9
ZQ
N9
TEN
DDR4_A _ZQ_01
R1.4 0.1uf change 0.047uf
follow intel PDG
+V_DDR_ VREFC A_CHA_D IMM
12
C1647
0.047UF/1 6V
12
R1602
240Ohm
RES 240 OHM 1/16W (0402) 1%
20161101 SWAP
/DDP
T7
NC
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
12
R1624 0Ohm
A_MEM1_E 9
R1608 240Ohm
R1616 0Ohm
/DDP
1 2
/SDP
1 2
Colay
M_A_BG1 4,15
+1.2V
M_A_DQS _DP24
M_A_DQS _DN24
20161101 SWAP
+1.2V
M_A_DQS _DP34
M_A_DQS _DN34
4
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10 _AP
M_A_A11
M_A_A12
M_A_A13
M_A_A14 _WE_N
M_A_A15 _CAS_N
M_A_A16 _RAS_N
M_A_ACT _N
M_A_BA0
M_A_BA1
M_A_BG0
DDR0_A _PARIT Y
M_A_DIM0 _CS0_N
M_A_DIM0 _ODT0
M_A_DIM0 _CKE0
M_A_DIM0 _CK_DD R0_DP
M_A_DIM0 _CK_DD R0_DN
DDR0_A _ALERT _N
M_A_DQS _DP2
M_A_DQS _DN2
M_A_DQS _DP3
M_A_DQS _DN3
DDR4_D RAMRST_ R_N
12
C1604
0.1UF/16V
@
M_A_D18
M_A_D16
M_A_D23
M_A_D20
M_A_D19
M_A_D17
M_A_D22
M_A_D21
M_A_D26
M_A_D24
M_A_D31
M_A_D28
M_A_D30
M_A_D29
M_A_D27
M_A_D25
U1602
256M x 16 (4Gbit)
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC_n
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
E7
NF/LDM_n/LDBI_n
G3
LDQS_t
F3
LDQS_c
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
E2
NF/UDM_n/UDBI_n
B7
UDQS_t
A7
UDQS_c
P1
RESET_n
MT40A25 6M16GE-0 83E
DDR4
VDD_10
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VREFCA
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VPP_1
VPP_2
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
ZQ
TEN
NC
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B1
R9
M1
DDR4_A _ZQ_23
F9
N9
T7
R1625 0Ohm
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
+1.2V
R1603
240Ohm
RES 240 OHM 1/16W (0402) 1%
1 2
/DDP
A_MEM2_E 9
R1.4 0.1uf change 0.047uf
follow intel PDG
+V_DDR_ VREFC A_CHA_D IMM
12
C1648
0.047UF/1 6V
12
/DDP
1 2
R1610 240Ohm
1 2
R1618 0Ohm/SDP
M_A_BG1
3
20161101 SWAP
+1.2V
M_A_DQS _DP54
M_A_DQS _DN54
20161101 SWAP
+1.2V
M_A_DQS _DP44
M_A_DQS _DN44
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10 _AP
M_A_A11
M_A_A12
M_A_A13
M_A_A14 _WE_N
M_A_A15 _CAS_N
M_A_A16 _RAS_N
M_A_ACT _N
M_A_BA0
M_A_BA1
M_A_BG0
DDR0_A _PARIT Y
M_A_DIM0 _CS0_N
M_A_DIM0 _ODT0
M_A_DIM0 _CKE0
M_A_DIM0 _CK_DD R0_DP
M_A_DIM0 _CK_DD R0_DN
DDR0_A _ALERT _N
M_A_D46
M_A_D44
M_A_D43
M_A_D41
M_A_D47
M_A_D40
M_A_D42
M_A_D45
M_A_DQS _DP5
M_A_DQS _DN5
M_A_D34
M_A_D32
M_A_D38
M_A_D36
M_A_D39
M_A_D37
M_A_D35
M_A_D33
M_A_DQS _DP4
M_A_DQS _DN4
DDR4_D RAMRST_ R_N
12
C1655
0.1UF/16V
@
U1603
256M x 16 (4Gbit)
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC_n
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
E7
NF/LDM_n/LDBI_n
G3
LDQS_t
F3
LDQS_c
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
E2
NF/UDM_n/UDBI_n
B7
UDQS_t
A7
UDQS_c
P1
RESET_n
MT40A25 6M16GE-0 83E
DDR4
VDD_10
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VREFCA
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VPP_1
VPP_2
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
ZQ
TEN
NC
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B1
R9
M1
DDR4_A _ZQ_54
F9
N9
T7
R1626 0Ohm
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
+1.2V
+2P5VPP
R1605
240Ohm
RES 240 OHM 1/16W (0402) 1%
1 2
/DDP
A_MEM3_E 9
M_A_BG1
12
2
R1.4 0.1uf change 0.047uf
follow intel PDG
+V_DDR_ VREFC A_CHA_D IMM
12
C1676
0.047UF/1 6V
20161101 SWAP
/DDP
1 2
R1612 240Ohm
1 2
R1622 0Ohm/SDP
20161101 SWAP
ColayColay
1
U1604
DDR4
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10 _AP
M_A_A11
M_A_A12
M_A_A13
M_A_A14 _WE_N
M_A_A15 _CAS_N
M_A_A16 _RAS_N
M_A_ACT _N
M_A_BA0
M_A_BA1
M_A_BG0
DDR0_A _PARIT Y
M_A_DIM0 _CS0_N
M_A_DIM0 _ODT0
M_A_DIM0 _CKE0
M_A_DIM0 _CK_DD R0_DP
M_A_DIM0 _CK_DD R0_DN
DDR0_A _ALERT _N
M_A_D54
M_A_D53
M_A_D49
M_A_D51
M_A_D55
M_A_D52
M_A_D48
C1651
0.1UF/16V
@
M_A_D50
M_A_DQS _DP6
M_A_DQS _DN6
M_A_D59
M_A_D57
M_A_D62
M_A_D61
M_A_D58
M_A_D56
M_A_D63
M_A_D60
M_A_DQS _DP7
M_A_DQS _DN7
DDR4_D RAMRST_ R_N
+1.2V
M_A_DQS _DP64
M_A_DQS _DN64
+1.2V
M_A_DQS _DP74
M_A_DQS _DN74
12
256M x 16 (4Gbit)
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC_n
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
E7
NF/LDM_n/LDBI_n
G3
LDQS_t
F3
LDQS_c
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
E2
NF/UDM_n/UDBI_n
B7
UDQS_t
A7
UDQS_c
P1
RESET_n
MT40A25 6M16GE-0 83E
VDD_10
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VREFCA
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VPP_1
VPP_2
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
ZQ
TEN
NC
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B1
R9
M1
DDR4_A _ZQ_67
F9
N9
T7
R1627 0Ohm
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
+1.2V
+2P5VPP
R1.4 0.1uf change 0.047uf
follow intel PDG
+V_DDR_ VREFC A_CHA_D IMM
12
R1604
240Ohm
/DDP
12
A_MEM4_E 9
R1614 240Ohm
R1620 0Ohm
M_A_BG1
12
C1666
0.047UF/1 6V
/DDP
1 2
/SDP
1 2
Colay
R1.1 follow intel PDG
+1.2V
12
12
C1607
10UF/6.3V
N/A
12
C1611
1UF/6.3V
N/A
+2P5VPP
12
C1628
0.1UF/16V
B B
N/A
12
C1608
C1601
10UF/6.3V
10UF/6.3V
N/A
N/A
12
12
C1615
C1613
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1627
C1626
10UF/6.3V
0.1UF/16V
N/A
N/A
12
12
C1616
1UF/6.3V
N/A
12
C1691
1UF/6.3V
N/A
12
C1612
C1614
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1689
C1690
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1698
C1699
1UF/6.3V
1UF/6.3V
N/A
N/A
12
C1688
1UF/6.3V
N/A
12
12
C1618
C1617
10UF/6.3V
10UF/6.3V
N/A
N/A
+1.2V
+2P5VPP
12
C1631
10UF/6.3V
N/A
12
C1635
1UF/6.3V
N/A
12
C1643
0.1UF/16V
N/A
12
12
C1602
C1632
10UF/6.3V
10UF/6.3V
N/A
N/A
12
12
C1636
C1638
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1644
C1642
0.1UF/16V
10UF/6.3V
N/A
N/A
12
12
C1640
C1641
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1687
C1686
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1637
1UF/6.3V
N/A
12
C1684
1UF/6.3V
N/A
12
C1697
C1696
1UF/6.3V
1UF/6.3V
N/A
N/A
12
C1685
1UF/6.3V
N/A
12
12
C1620
C1619
10UF/6.3V
10UF/6.3V
N/A
N/A
+1.2V
+2P5VPP
12
12
12
C1660
0.1UF/16V
N/A
C1675
10UF/6.3V
N/A
C1663
1UF/6.3V
N/A
12
12
12
C1667
0.1UF/16V
N/A
C1671
10UF/6.3V
N/A
C1672
1UF/6.3V
N/A
12
12
12
C1657
10UF/6.3V
N/A
C1652
10UF/6.3V
N/A
C1658
1UF/6.3V
N/A
12
12
C1665
C1649
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1683
C1682
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1670
1UF/6.3V
N/A
12
C1680
1UF/6.3V
N/A
12
C1695
C1694
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1681
1UF/6.3V
N/A
C1621
10UF/6.3V
N/A
12
C1622
10UF/6.3V
N/A
+1.2V
+2P5VPP
N/A
12
12
12
N/A
C1656
0.1UF/16V
C1674
10UF/6.3V
N/A
C1659
1UF/6.3V
12
12
C1668
C1650
10UF/6.3V
10UF/6.3V
N/A
N/A
12
12
12
12
C1653
C1669
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1662
C1654
10UF/6.3V
0.1UF/16V
N/A
N/A
12
12
C1664
1UF/6.3V
N/A
12
C1679
1UF/6.3V
N/A
C1661
C1673
1UF/6.3V
1UF/6.3V
N/A
N/A
12
12
C1625
C1678
1UF/6.3V
1UF/6.3V
N/A
N/A
12
C1693
C1692
1UF/6.3V
1UF/6.3V
N/A
N/A
12
C1677
1UF/6.3V
N/A
12
12
C1623
C1624
10UF/6.3V
10UF/6.3V
N/A
N/A
A A
Title :
Title :
Title :
DDR4(1)_CH0
DDR4(1)_CH0
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
D
D
D
SU4EA
SU4EA
SU4EA
Date: Sheet o f
Date: Sheet o f
5
4
3
2
Date: Sheet o f
1
Engineer:
Engineer:
Engineer:
DDR4(1)_CH0
16 94Friday, March 10, 20 17
16 94Friday, March 10, 20 17
16 94Friday, March 10, 20 17
Rev
Rev
Rev
1.0
1.0
1.0
5
DDR4(2)_CH1
17
M_B_D[63 :0] 4
M_B_A04,15
M_B_A14,15
M_B_A24,15
M_B_A34,15
M_B_A44,15
M_B_A54,15
M_B_A64,15
M_B_A74,15
M_B_A84,15
M_B_A94,15
M_B_A10 _AP4,15
M_B_A114,15
D D
M_B_A124,15
M_B_A134,15
M_B_A14 _WE_N4,15
M_B_A15 _CAS_N4,15
M_B_A16 _RAS_N4,15
M_B_ACT _N4,15
M_B_BA04,15
M_B_BA14,15
M_B_BG04,15
DDR1_B _PARIT Y4 ,15
M_B_DIM0 _CS0_N4,15
M_B_DIM0 _ODT04,15
M_B_DIM0 _CKE04,15
M_B_DIM0 _CK_DD R0_DP4,15
M_B_DIM0 _CK_DD R0_DN4,15
DDR1_B _ALERT _N4,15
Byte_0
Byte_1 Byte_3
C C
DDR4_D RAMRST_ R_N4 ,16
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10 _AP
M_B_A11
M_B_A12
M_B_A13
M_B_A14 _WE_N
M_B_A15 _CAS_N
M_B_A16 _RAS_N
M_B_ACT _N M_B_ACT _N
M_B_BA0
M_B_BA1
M_B_BG0 M_B_BG0
M_B_DIM0 _CS0_N M_B_DIM0 _CS0_N
M_B_DIM0 _ODT0
M_B_DIM0 _CKE0
M_B_DIM0 _CK_DD R0_DP M_B_DIM0 _CK_DD R0_DP
M_B_DIM0 _CK_DD R0_DN
DDR1_B _ALERT _N DDR1_B _ALERT _N
20161101 SWAP
+1.2V
M_B_DQS _DP04 M_B_DQS _DP24
M_B_DQS _DN04
M_B_DQS _DP0 M_B_DQS _DP2
M_B_DQS _DN0
20161101 SWAP
+1.2V
12
C1718
0.1UF/16V
@
M_B_DQS _DP1
M_B_DQS _DN1
DDR4_D RAMRST_ R_N
M_B_DQS _DP14
M_B_DQS _DN14
U1701
DDR4
256M x 16 (4Gbit)
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC_n
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
DDR1_B _PARIT Y DDR1_B _PARIT Y
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
M_B_D2
G2
DQ0
M_B_D0
F7
DQ1
M_B_D6
H3
DQ2
M_B_D5
H7
DQ3
M_B_D7
H2
DQ4
M_B_D3
H8
DQ5
M_B_D4
J3
DQ6
M_B_D1
J7
DQ7
E7
NF/LDM_n/LDBI_n
G3
LDQS_t
F3
LDQS_c
M_B_D15
A3
DQ8
M_B_D13 M_B_D29
B8
DQ9
M_B_D10
C3
DQ10
M_B_D12
C7
DQ11
M_B_D14
C2
DQ12
M_B_D8
C8
DQ13
M_B_D11
D3
DQ14
M_B_D9
D7
DQ15
E2
NF/UDM_n/UDBI_n
B7
UDQS_t
A7
UDQS_c
P1
RESET_n
MT40A25 6M16GE-0 83E
/CHB
+1.2V
B3
VDD_1
B9
VDD_2
D1
VDD_3
G7
VDD_4
J1
VDD_5
J9
VDD_6
L1
VDD_7
L9
VDD_8
R1
VDD_9
T9
VDD_10
A1
VDDQ_1
A9
VDDQ_2
C1
VDDQ_3
D9
VDDQ_4
F2
VDDQ_5
F8
VDDQ_6
G1
VDDQ_7
G9
VDDQ_8
VDDQ_9
VDDQ_10
VREFCA
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VPP_1
VPP_2
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
+2P5VPP +2P5VP P
J2
J8
B1
R9
M1
F9
ZQ
N9
TEN
T7
NC
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
R1.4 0.1uf change 0.047uf
follow intel PDG
+V_DDR_ VREFC A_CHB_D IMM
12
C1711
/CHB
12
R1701
240Ohm
RES 240 OHM 1/16W (0402) 1%
/DDP
12
R1706 240Ohm
R1708 0Ohm
/DDP
1 2
/SDP
1 2
0.047UF/1 6V
DDR4_B _ZQ_01 DDR4_B _ZQ_23
/CHB
R1705 0Ohm
B_MEM1_E 9
Colay
M_B_BG1 4,15
20161101 SWAP
+1.2V
M_B_DQS _DN24
20161101 SWAP
+1.2V
M_B_DQS _DP34
M_B_DQS _DN34
4
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10 _AP
M_B_A11
M_B_A12
M_B_A13
M_B_A14 _WE_N
M_B_A15 _CAS_N
M_B_A16 _RAS_N
M_B_BA0
M_B_BA1
M_B_DIM0 _ODT0
M_B_DIM0 _CKE0
M_B_DIM0 _CK_DD R0_DN
M_B_D19
M_B_D21
M_B_D18
M_B_D17
M_B_D23
M_B_D20
M_B_D22
M_B_D16
M_B_DQS _DN2
M_B_D26
M_B_D30
M_B_D24
M_B_D27
M_B_D28
M_B_D31
M_B_D25
M_B_DQS _DP3
M_B_DQS _DN3
DDR4_D RAMRST_ R_N
12
C1722
0.1UF/16V
@
U1702
256M x 16 (4Gbit)
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC_n
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
E7
NF/LDM_n/LDBI_n
G3
LDQS_t
F3
LDQS_c
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
E2
NF/UDM_n/UDBI_n
B7
UDQS_t
A7
UDQS_c
P1
RESET_n
MT40A25 6M16GE-0 83E
/CHB
DDR4
VDD_10
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VREFCA
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VPP_1
VPP_2
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
ZQ
TEN
NC
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B1
R9
M1
F9
N9
T7
R1714 0Ohm
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
+1.2V
R1702
240Ohm
RES 240 OHM 1/16W (0402) 1%/CHB
1 2
/DDP
12
B_MEM2_E 9
R1.4 0.1uf change 0.047uf
follow intel PDG
+V_DDR_ VREFC A_CHB_D IMM
12
C1705
/CHB
0.047UF/1 6V
/DDP
1 2
R1711 240Ohm
1 2
R1712 0Ohm/SDP
Colay
M_B_BG1
3
U1703
DDR4
Byte_4Byte_2
Byte_5
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10 _AP
M_B_A11
M_B_A12
M_B_A13
M_B_A14 _WE_N
M_B_A15 _CAS_N
M_B_A16 _RAS_N
M_B_ACT _N M_B_ACT _N
M_B_BA0
M_B_BA1
M_B_BG0 M_B_BG0
DDR1_B _PARIT Y DDR1 _B_PAR ITY
M_B_DIM0 _CS0_N M_B_DI M0_CS0_ N
M_B_DIM0 _ODT0
M_B_DIM0 _CKE0
M_B_DIM0 _CK_DD R0_DP
M_B_DIM0 _CK_DD R0_DN
DDR1_B _ALERT _N DDR1_B _ALERT _N
20161101 SWAP
+1.2V
20161101 SWAP
+1.2V
12
C1731
0.1UF/16V
@
M_B_DQS _DP4
M_B_DQS _DN4
M_B_D46
M_B_D45
M_B_D47
M_B_D44
M_B_D43
M_B_D40
M_B_D42
M_B_D41
M_B_DQS _DP5
M_B_DQS _DN5
DDR4_D RAMRST_ R_N
M_B_DQS _DP44
M_B_DQS _DN44
M_B_DQS _DP54
M_B_DQS _DN54
M_B_D38
M_B_D32
M_B_D34
M_B_D33
M_B_D39
M_B_D37
M_B_D35
M_B_D36
256M x 16 (4Gbit)
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC_n
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
E7
NF/LDM_n/LDBI_n
G3
LDQS_t
F3
LDQS_c
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
E2
NF/UDM_n/UDBI_n
B7
UDQS_t
A7
UDQS_c
P1
RESET_n
MT40A25 6M16GE-0 83E
/CHB
B3
VDD_1
B9
VDD_2
D1
VDD_3
G7
VDD_4
J1
VDD_5
J9
VDD_6
L1
VDD_7
L9
VDD_8
R1
VDD_9
T9
VDD_10
A1
VDDQ_1
A9
VDDQ_2
C1
VDDQ_3
D9
VDDQ_4
F2
VDDQ_5
F8
VDDQ_6
G1
VDDQ_7
G9
VDDQ_8
J2
VDDQ_9
J8
VDDQ_10
B1
VPP_1
R9
VPP_2
M1
VREFCA
DDR4_B _ZQ_45
F9
ZQ
N9
TEN
T7
R1719 0Ohm
NC
B2
VSS_1
E1
VSS_2
B_MEM3_E 9 B_MEM4_E 9
E9
VSS_3
G8
VSS_4
K1
VSS_5
K9
VSS_6
M9
VSS_7
N1
VSS_8
T1
VSS_9
A2
VSSQ_1
A8
VSSQ_2
C9
VSSQ_3
D2
VSSQ_4
D8
VSSQ_5
E3
VSSQ_6
E8
VSSQ_7
F1
VSSQ_8
H1
VSSQ_9
H9
VSSQ_10
2
+1.2V
+2P5VPP
R1.4 0.1uf change 0.047uf
follow intel PDG
+V_DDR_ VREFC A_CHB_D IMM
12
C1745
/CHB
0.047UF/1 6V
12
R1703
240Ohm/CHB
Byte_6
/DDP
12
/DDP
1 2
R1717 240Ohm
/SDP
1 2
R1720 0Ohm
Byte_7
Colay Colay
M_B_BG1
20161101 SWAP
+1.2V
M_B_DQS _DP64
M_B_DQS _DN64
20161101 SWAP
+1.2V
M_B_DQS _DP74
M_B_DQS _DN74
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10 _AP
M_B_A11
M_B_A12
M_B_A13
M_B_A14 _WE_N
M_B_A15 _CAS_N
M_B_A16 _RAS_N
M_B_BA0
M_B_BA1
M_B_DIM0 _ODT0
M_B_DIM0 _CKE0
M_B_DIM0 _CK_DD R0_DP
M_B_DIM0 _CK_DD R0_DN
M_B_D55
M_B_D48
M_B_D50
M_B_D49
M_B_D54
M_B_D52
M_B_D51
M_B_D53
M_B_DQS _DP6
M_B_DQS _DN6
M_B_D62
M_B_D56
M_B_D63
M_B_D57
M_B_D59
M_B_D61
M_B_D58
M_B_D60
M_B_DQS _DP7
M_B_DQS _DN7
DDR4_D RAMRST_ R_N
12
C1736
0.1UF/16V
@
+V_DDR_ VREFC A_CHB_D IMM19
U1704
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC_n
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
E7
NF/LDM_n/LDBI_n
G3
LDQS_t
F3
LDQS_c
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
E2
NF/UDM_n/UDBI_n
B7
UDQS_t
A7
UDQS_c
P1
RESET_n
MT40A25 6M16GE-0 83E
/CHB
DDR4
256M x 16 (4Gbit)
VDD_10
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VREFCA
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VPP_1
VPP_2
ZQ
TEN
NC
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
1
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B1
R9
M1
F9
N9
T7
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
DDR4_B _ZQ_67
R1721 0Ohm
+V_DDR_ VREFC A_CHB_D IMM
+1.2V
+2P5VPP
R1.4 0.1uf change 0.047uf
follow intel PDG
+V_DDR_ VREFC A_CHB_D IMM
/CHB
R1704
240Ohm
RES 240 OHM 1/16W (0402) 1%/CHB
1 2
/DDP
12
1 2
R1724 240Ohm
1 2
R1725 0Ohm/SDP
M_B_BG1
/DDP
12
C1756
0.047UF/1 6V
R1.1 follow intel PDG
+1.2V
12
12
C1712
0.1UF/16V
/CHB
12
C1717
10UF/6.3V
/CHB
C1707
1UF/6.3V
/CHB
12
12
12
C1723
10UF/6.3V
/CHB
C1703
10UF/6.3V
/CHB
C1716
1UF/6.3V
/CHB
12
12
C1710
C1709
1UF/6.3V
1UF/6.3V
/CHB
/CHB
12
12
C1799
C1798
1UF/6.3V
1UF/6.3V
/CHB
/CHB
12
12
C1702
1UF/6.3V
/CHB
12
C1796
1UF/6.3V
/CHB
12
C1769
C1768
1UF/6.3V
1UF/6.3V
/CHB
/CHB
12
12
C1795
10UF/6.3V
/CHB
12
C1794
10UF/6.3V
/CHB
C1797
1UF/6.3V
/CHB
12
C1724
10UF/6.3V
/CHB
12
C1728
1UF/6.3V
/CHB
+2P5VPP +2P5VPP
12
C1719
0.1UF/16V
B B
/CHB
+1.2V
12
C1720
10UF/6.3V
/CHB
12
C1704
1UF/6.3V
/CHB
12
C1714
0.1UF/16V
/CHB
12
12
C1721
C1725
10UF/6.3V
10UF/6.3V
/CHB
/CHB
12
12
C1715
1UF/6.3V
/CHB
12
C1727
0.1UF/16V
/CHB
12
C1701
C1726
1UF/6.3V
1UF/6.3V
/CHB
/CHB
12
12
C1713
C1793
10UF/6.3V
1UF/6.3V
/CHB
/CHB
12
12
C1708
1UF/6.3V
/CHB
12
C1792
1UF/6.3V
/CHB
12
C1706
1UF/6.3V
/CHB
12
C1790
1UF/6.3V
/CHB
12
C1771
C1770
1UF/6.3V
1UF/6.3V
/CHB
/CHB
12
C1789
10UF/6.3V
/CHB
12
C1788
10UF/6.3V
/CHB
12
C1791
1UF/6.3V
/CHB
+1.2V
+2P5VPP
12
12
12
C1735
0.1UF/16V
/CHB
C1755
10UF/6.3V
/CHB
C1739
1UF/6.3V
/CHB
+1.2V
12
12
12
C1748
0.1UF/16V
/CHB
C1751
10UF/6.3V
/CHB
C1753
1UF/6.3V
/CHB
12
C1732
10UF/6.3V
/CHB
12
12
C1737
C1746
1UF/6.3V
1UF/6.3V
/CHB
/CHB
12
12
C1781
C1738
1UF/6.3V
10UF/6.3V
/CHB
/CHB
12
12
12
C1749
C1729
1UF/6.3V
1UF/6.3V
/CHB
/CHB
12
12
C1780
C1778
1UF/6.3V
1UF/6.3V
/CHB
/CHB
12
C1775
C1774
1UF/6.3V
1UF/6.3V
/CHB
/CHB
12
C1777
10UF/6.3V
/CHB
12
C1776
10UF/6.3V
/CHB
12
C1779
1UF/6.3V
/CHB
12
12
C1747
C1730
10UF/6.3V
10UF/6.3V
/CHB
/CHB
12
C1750
1UF/6.3V
/CHB
12
C1742
0.1UF/16V
/CHB
12
C1733
10UF/6.3V
/CHB
C1734
1UF/6.3V
/CHB
C1744
1UF/6.3V
/CHB
12
C1787
1UF/6.3V
/CHB
12
12
12
12
C1752
1UF/6.3V
/CHB
12
C1786
1UF/6.3V
/CHB
12
C1741
1UF/6.3V
/CHB
12
C1784
1UF/6.3V
/CHB
12
C1773
C1772
1UF/6.3V
1UF/6.3V
/CHB
/CHB
12
C1783
10UF/6.3V
/CHB
12
C1782
10UF/6.3V
/CHB
12
C1785
1UF/6.3V
/CHB
+2P5VPP
12
12
12
C1740
0.1UF/16V
/CHB
C1754
10UF/6.3V
/CHB
C1743
1UF/6.3V
/CHB
A A
Title :
Title :
Title :
DDR4(2)_CH0
DDR4(2)_CH0
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
D
D
D
SU4EA
SU4EA
SU4EA
Date: Sheet
Date: Sheet o f
5
4
3
2
Date: Sheet o f
1
Engineer:
Engineer:
Engineer:
DDR4(2)_CH0
of
17 94Friday, March 10, 20 17
17 94Friday, March 10, 20 17
17 94Friday, March 10, 20 17
Rev
Rev
Rev
1.0
1.0
1.0
5
D D
C C
4
3
2
1
B B
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
<Title>
<Title>
<Title>
SU4EA <RevCode>
A
SU4EA <RevCode>
A
SU4EA <RevCode>
A
18 94Friday, March 10, 2017
18 94Friday, March 10, 2017
2
18 94Friday, March 10, 2017
1
5
4
3
2
1
19
D D
C C
DDR4(3)_CA/DQ Voltage
+1.2V
R1910
C1903
0.022UF/16V
R1909
24.9Ohm
1%
C1902
0.022UF/16V
R1905
24.9Ohm
1%
1 2
2.7Ohm
10V220000434
R1906
1 2
2.7Ohm
10V220000434
+V_DDR_CA_VREF4
+V_DDR_VREFDQ02_CHB4
12
12
12
12
1 2
12
+1.2V
1 2
12
R1912
1.8KOhm
1%
R1911
1.8KOhm
1%
R1907
1.8KOhm
1%
R1908
1.8KOhm
1%
+V_DDR_VREFCA_CHA_DIMM
+V_DDR_VREFCA_CHB_DIMM
+1.2V
+V_DDR_VREFCA_CHB_DIMM
+V_DDR_VREFCA_CHA_DIMM
+1.2V 4,7,15,16,17,57,83
+V_DDR_VREFCA_CHB_DIMM 17
+V_DDR_VREFCA_CHA_DIMM 16
B B
A A
DDR4(3)_CA/DQ Voltage
DDR4(3)_CA/DQ Voltage
DDR4(3)_CA/DQ Voltage
Title :
Title :
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Title :
Engineer:
Engineer:
Engineer:
1
James_Liao
James_Liao
James_Liao
of
19 94Friday, March 10, 2017
19 94Friday, March 10, 2017
19 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
20
D D
RF requirement
SPI_CLK
12
C2003
0.1UF/16V
@
near AV2
20170126
Reserver GPIO for function ID
+3VSUS
Function ID
12
C C
B B
12
12
1 2
R2004 20KOhm@
1 2
R2006 20KOhm@
1 2
R2008 20KOhm@
R2015
10KOhm
@
R2016
10KOhm
12
R2017
10KOhm
@
R2018
10KOhm
FN_ID2
FN_ID1
SMBALERT#
SML0ALERT#
R1.1 Not support AMT
R2003 2.2KOhm@
CRB 0.53 reserve 150k ohm
R2005 4.7KOhm@
CRB 0.53 reserve 150k ohm
R2007 4.7KOhm@
1 2
1 2
1 2
SPI_CLK28
SPI_SO28
SPI_SI28
SPI_WP#_IO228
SPI_HOLD#_IO328
SPI_CS#028
BBS 21
T2011
T2001
T2002
T2007
CL_CLK53
CL_DATA53
CL_RST#53
RCIN#30
INT_SERIRQ30,44,62
+3VSUS
+3VSUS
+3VSUS
SMBALERT# - Internal weak pull down 20k ohm
TLS Confidentiality
0 : Disable (default)
1 : Enable
SML0ALERT# - Internal weak pull down 20 kohm
0 : LPC EC (default)
1 : eSPI EC
BBS - Internal weak pull down 20k ohm
Boot BIOS Strap
0 : SPI destination (default)
1 : LPC destination
SPI_CLK
SPI_SO
SPI_SI
SPI_WP#_IO2
SPI_HOLD#_IO3
SPI_CS#0
SPI_CS1#
1
SPI_CS2#
1
GPP_D1
1
FN_ID1
FN_ID2
GPP_D0
1
CL_CLK
CL_DATA
CL_RST#
RCIN#
INT_SERIRQ
Unmount R2013,R2009
Vendor Suggest Pull High Resistor Need To Close To TPM
PM_CLKRUN#, INT_SERIRQ Need To Pull 10Kohm To+3VS at Chipset Side
AW13
AY11
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
PCH(1)_SPI/LPC
U0301E
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
947859
0101-03860PB
PM_CLKRUN#
INT_SERIRQ
SMB_CLK
SMB_DAT
SML1_DAT
SML1_CLK
SML1ALERT#
MOW WW52
To enable Direct Connect Interface (DCI),
a 150K pull up resistor will need to be added to PCHHOT#
pin. This pin must be low during the rising edge of RSMRST#.
LPC
1 2
R2013 10KOhm
1 2
R2009 10KOhm
1 2
RN2001A
2.2KOhm
3 4
RN2001B
2.2KOhm
3 4
RN2002B
2.2KOhm
1 2
RN2002A
2.2KOhm
1 2
R2012 150KOhm
SMBUS, SMLINK
GPP_A14/SUS_STAT#/ESPI_RESET#
@
@
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
+3VS
+3VSUS
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
SMB_CLK
SMB_DAT
SMBALERT#
SML0_CLK_NFC
SML0_DAT_NFC
SML0ALERT#
SML1_CLK
SML1_DAT
SML1ALERT#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PM_SUS_STAT#
CLK_KBCPCI_PCH_R
CLK_LPC1
PM_CLKRUN#
RF requirement
SML1_CLK
1
T2008
1
T2003
1
T2004
SML1_CLK 28
T2010
SML1_DAT 28
LPC_AD0 30,44,62
LPC_AD1 30,44,62
LPC_AD2 30,44,62
LPC_AD3 30,44,62
LPC_FRAME# 30,44,62
PM_SUS_STAT# 62
R2001 22Ohm 1%
R2002 22Ohm 1%/Debug
R2014 22Ohm 1%/TPM
PM_CLKRUN# 30,62
1
1 2
1 2
1 2
To EC
TPM
EC
DEBUG
12
C2001
10PF/50V
@
12
C2002
10PF/50V
@
12
C2004
0.1UF/16V
@
near W3
CLK_KBCPCI_PCH 30
CLK_DEBUG 44
LPCCLK_TPM 62
A A
PCH(1)_SPI/LPC
PCH(1)_SPI/LPC
PCH(1)_SPI/LPC
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Title :
James_Liao
James_Liao
James_Liao
20 94Friday, March 10, 2017
20 94Friday, March 10, 2017
20 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
Microsoft* Windows* 7 System WHCK Requirement – OEM platforms are
required to include a supported OS debug interface, accessible by an enduser.
This allows developers to help in driver debug. The supported
21
D D
C C
+3VSUS
B B
R10
R11 0
R12
R20
A A
Windows 7 debug interfaces are EHCI, 1394 port and COM port.
With skylake EHCI Removal, Potential Gap with Windows* 7 Kernel Debug
and OS Installation – Mitigation Required
To implement UART for WIN7 WHCK requirement if need
Please refer to Intel document #548689 - RVP5
+3VSUS
PCB ID
R2104
10KOhm
N/A
R2105
10KOhm
@
12
PCB_ID1
PCB_ID0
12
PCB_ID1
(GPP_C14)
0 0
1
1
R2106
10KOhm
N/A
R2107
10KOhm
@
PCB_ID0
(GPP_C13)
HYNIX DDR4 2400 8Gb H5AN8G6NAFR-UHC
0315-01W60PB
MICRON DDR4 2400 4Gb MT40A256M16GE-083E:B
1
0315-01W80PB
MICRON DDR4 2400 8Gb MT40A512M16JY-083E:B
0
0315-01W90PB
SAMSUNG DDR4 2400 4Gb K4A4G165WE-BCRC
1
0315-01VV0PB
HYNIX DDR4 2400 4Gb H5AN4G6NAFR-UHC
0315-01WM0PB
SAMSUNG DDR4 2400 8Gb K4A8G165WB-BCRC
0315-01C80PB
HYNIX DDR4 2133 4Gb H5AN4G6NAFR-TF
0315-01EK0PB
MICRON/MT40A1G16WBU-083E:B
0315-01YC0PB
5
12
12
12
R2108
10KOhm
@
12
R2109
10KOhm
@
20161212 R1.1 Kai
P21 ~ P23 / P65
Add SHB & G-sensor in MB
20161222 R1.0 Kai
Add Touch panel
Memory ID
12
12
R2115
10KOhm
@
12
12
R2116
R2120
10KOhm
@
R2119
10KOhm
@
10KOhm
@
4
NO UART MUX
IOAC EC CTRL (X3 PCH CTRL)
Sensor Hub
Touch Pad
Touch Panel
I2C_SDA_SEN_S
R2110 10KOhm@
I2C_SCL_SEN_S
R2111 10KOhm@
I2C2_SDA_PCH
R2101 10KOhm@
I2C2_SCL_PCH
R2102 10KOhm@
12
R2117
10KOhm
@
12
R2118
10KOhm
@
MEM_ID3
MEM_ID2
(GPP_C15)
(GPP_B17)
0 0
0
0
0
0 1
0
0
0
4
BBS20
PCH_UATR0_DEBUG_RX28
PCH_UATR0_DEBUG_TX28
WLAN_ON_PCH53
BT_ON/OFF#_PCH53 TP_IRQ# 30,31
LCD_BKLTEN_PCH3,45
I2C_SDA_SEN_S65
I2C_SCL_SEN_S65
PCH_I2C1_SDA31
PCH_I2C1_SCL31
I2C2_SDA_PCH45
I2C2_SCL_PCH45
12
12
12
12
MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3
MEM_ID1
MEM_ID0
(GPP_B16)
(GPP_B15)
0 0
0
0
1
0
1 1
1
0
1
1
1 1 1
Reserve UART
For Debug Port
+3VS
+1.8VS
10
0
00
1
0
PCH(2)_ISH
MEM_ID0
MEM_ID1
MEM_ID2
GPP_B18
GPP_B21
1
T2117
T2111
T2144
T2112
R1.1 change set ting
UMA
DIS 1
BBS
PCH_UATR0_DEBUG_RX
PCH_UATR0_DEBUG_TX
GPP_C10
1
GPP_C11
1
WLAN_ON_PCH
BT_ON/OFF#_PCH
LCD_BKLTEN_PCH
GPP_C23
1
I2C_SDA_SEN_S
I2C_SCL_SEN_S
PCH_I2C1_SDA
PCH_I2C1_SCL
I2C2_SDA_PCH
I2C2_SCL_PCH
MB BD ID
+3VSUS +3VSUS
12
R2136
12
BID_GPU
0
100KOhm
/VGA
R2147
100KOhm
/UMA
DIS
UMA
3
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
W4
AB3
AD1
AD2
AD3
AD4
U7
U6
U8
U9
AH9
AH10
AH11
AH12
AF11
AF12
12
R2133
10KOhm
/U42
12
R2134
10KOhm
/U22
U22 0
U42 1
3
U0301F
LPSS ISH
GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
947859
0101-03860PB
BID_GPU
CPU_ID1
CPU_ID1
C 3.3V GPIO
F 1.8V GPIO
GPP_A18(0)
GPP_A18(1)
GPP_A19(0)
GPP_A19(1)
12
12
R2148
10KOhm
R2149
10KOhm
@
Disable
Enable
12
R2150
10KOhm
/CHB_EN
12
R2151
10KOhm
/CHB_DIS
CHA CHB
2
GPP_D9
GPP_D10
GPP_D11
D 3.3V GPIO
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
Sx_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
R1.2 change set ting
+3VSUS
12
R2152
10KOhm
/HDCP2.2
MEM_CHA
MEM_CHB
12
R2153
10KOhm
/HDCP1.4
disable 0
Disable
Enable
2
enable 1
1.4 0
2.2 1
R1.1 remove GPU
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
TOUCH_INT_CPU_R
AY7
TOUCH_RST#_CPU_R
AW7
AP13
12
R2132
10KOhm
@
12
R2135
10KOhm
N/A
eMMC_ID
HDCP_ID
1
TP_SENSOR_OFF#
CPU_ID1
eMMC_ID
TP_IRQ#
BID_GPU
OP_SD#
PCB_ID0
PCB_ID1
MEM_ID3
20161227 R1.1 Kai
Add for I2C Touch panel
MEM_CHA
MEM_CHB
HDCP_ID
PANEL_ID
R2103 0Ohm/ TPANEL
R2113 0Ohm/ TPANEL
TP_SENSOR_OFF# 31
R1.1 remove GPU
OP_SD# 36
12
12
+3VSUS
12
12
R1.1 remove GPU
eMMC_ID
HDCP_ID
PCH_I2C1_SCL
PCH_I2C1_SDA
GPP_B18
GSPI0_MOSI / GPP_B18 - Internal weak pull down 20k ohm
0 : Disable No Reboot mode(default)
1 : Enable NO Reboot Enable mode
Default is GPO, to reserve pull high to +3VSUS_ORG
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
SU4EA
SU4EA
SU4EA
R2146 2.2KOhm@
R2145 2.2KOhm@
Change To 2.2Kohm PU side
Default PU +3V For S3 Resume by TP side
1 2
R2112 4.7KOhm@
1 2
R2122 4.7KOhm@
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
Touch Pad
TOUCH_INT_CPU 45
TOUCH_RST#_CPU 45
PANEL ID
R2154
10KOhm
/14inch
PANEL_ID
R2155
10KOhm
/15inch
1 2
1 2
+3VS
+3VSUS
PCH(2)_ISH
PCH(2)_ISH
PCH(2)_ISH
James_Liao
James_Liao
James_Liao
21 94Monday, March 20, 2017
21 94Monday, March 20, 2017
21 94Monday, March 20, 2017
Touch Pad
+3VS
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
22
HDA_SDO_R
HDA_SDI0_R
HDA_SDI1
HDA_RST#_R
12
C2201
D D
2PF/25V
NPO/+/-0.25PF
vx_c0201
NPO/+/-0.25PF
EMI request for Kaby Lake
Recommended Routing : Stripline < 2"
Alternative Routing : Microstrip <1" (less noise-reduction)
C C
RF requirement
HDA_BCLK
12
C2205
22PF/50V
@
B B
A A
5
C2202
2PF/25V
vx_c0201
HDA_SPKR36
12
12
HDA_SYNC36
HDA_BCLK36
HDA_SDO36
HDA_SDI036
HDA_RST#36
C2203
2PF/25V
NPO/+/-0.25PF
vx_c0201
@
12
GND
HDA_SDO
HDA_SYNC
HDA_BCLK
HDA_SDO
HDA_SDI0
HDA_RST#
HDA_SPKR
C2204
2PF/25V
NPO/+/-0.25PF
vx_c0201
R2206 33Ohm@
R2207 33Ohm@
R2219 33Ohm
R2216 33Ohm
R2215 33OhmN/A
R2220 33OhmN/A
R2217 33Ohm
SP2208 0Ohm
1 2
GND
T2201
T2202
R2202 20KOhm@
* The signal has a weak internal Pull-down.
1 2
HDA_SDO_R
Name
GPP_B14
GPP_B18
GPP_B22
GPP_C5
HDA_SDO
GPP_C2
HDA_SDO_RHDA_SDI0
HDA_SDI0_R
HDA_SYNC_R
HDA_BCLK_R
HDA_SDO_R
HDA_SDI0_R
HDA_SDI1
1
HDA_RST#_R
GPP_D23
1
SPKR
P5HCJ_KBL
0
0
0
0
0
0
GPP_E19 0
GPP_E21 0
From EDS_Intel_PCH(Skylake.UY_Kabylake.UY)_Vol1_545659_Rev2p0 Page.55-57
4
PCH(3)_HDA_SDIO
U0301G
BA22
AY22
BB22
BA21
AY21
AW22
AY20
AW20
AK10
AUDIO
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
947859
0101-03860PB
SPKR
+3VSUS
HDA_SDO - Internal weak pull down
FLASH DESCRIPTOR SECURITY OVERRRIDE
0 : Enable security measure defined in the Flash Descriptor
1 : Disable Flash Descriptor Security
1 2
R2209 4.7KOhm@
1 2
R2210 4.7KOhm@
CRB 0.53 reserve 150k ohm
12
R2203
4.7KOhm
@
D2201 1.2V/0.1A
12
+3VS
+3VSUS
SDIO/SDXC
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
SPKR - Internal weak pull down
0 : Disable TOP Swap mode (default)
1 : Enable Top Swap Enable
Default is GPO, to reserve pull high to +3VSUS_ORG
PCH_FLASH_DESCRIPTOR 30
Description
0 = Disable “Top Swap” mode. (Default)
1 = Enable “Top Swap” mode.
0 = Disable “No Reboot” mode. (Default)
1 = Enable “No Reboot” mode
0 = SPI (Default)
1 = LPC
0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.
0 = Enable security measures defined in the Flash
Descriptor. (Default)
1 = Disable Flash Descriptor Security (override).
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality).
0 = Port B is not detected. (Default)
1 = Port B is detected.
0 = Port C is not detected. (Default)
1 = Port C is detected.
3
GPP_G0/SD_CMD
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
SD_RCOMP
GPP_F23
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
LID_STAT0_C
LID_STAT1_C
LID_STAT2_C
LID_INI#_C
SENSOR_INT_CPU
G_X
G_Y
SHB_RST#_CPU
TPanel_EN_R
SKL_SD_RCOMP
RTC_IN#
R2211 0Ohm/ TPANEL
R2201 200Ohm1%
2
12
1 2
RTC_IN# 24
LID_STAT0_C 65
LID_STAT1_C 65
LID_STAT2_C 65
LID_INI#_C 65
SENSOR_INT_CPU 65
G_X 65
G_Y 65
SHB_RST#_CPU 65
TPanel_EN 45
TPanel_ON 45
20161220 R1.0 Kai
P21 ~ P23 / P65
Add SHB & G-sensor in MB
20161222 R1.0 Kai
Add Touch panel (TPanel_ON)
20161228 R1.0 Kai
Add signale TPanel_EN
PCH(3)_HDA/SDIO
PCH(3)_HDA/SDIO
PCH(3)_HDA/SDIO
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Title :
James_Liao
James_Liao
James_Liao
22 94Friday, March 10, 2017
22 94Friday, March 10, 2017
22 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
23
PCH(4)_USB/PCIE/SATA
R1.1 remove GPU
D D
PCIE_RXN551
PCIE_RXP551
PCIE_TXN551
PCIE_TXP551
PCIE_RXN651
PCIE_RXP651
PCIE_TXN651
C C
M.2 SATA/PCIE x 4 -SSD
WLAN
PCIE_TXP651
PCIE_RXN751
PCIE_RXP751
PCIE_TXN751
PCIE_TXP751
SATA_RXN851
SATA_RXP851
SATA_TXN851
SATA_TXP851
PCIE_RXN_WLAN53
PCIE_RXP_WLAN53
PCIE_TXN_WLAN53
PCIE_TXP_WLAN53
PCIE_RCOMP PDG 0.9 need 100 ohm 0.1% / CRB 0.53 use 100 ohm +-1%
PCIE_RXN11_M2_SSD56
PCIE_RXP11_M2_SSD56
PCIE_TXN11_M2_SSD56
M.2 SATA/PCIE x 2 -SSD
If SATA driver need change port,
B B
Also must change reltaed "DEVSLP and SATAXPCIE" pin
PCIE_TXP11_M2_SSD56
SATA_RXN12_M2_SSD56
SATA_RXP12_M2_SSD56
SATA_TXN12_M2_SSD56
SATA_TXP12_M2_SSD56
PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5
PCIE_RXN6
PCIE_RXP6
PCIE_TXN6
PCIE_TXP6
PCIE_RXN7
PCIE_RXP7
PCIE_TXN7
PCIE_TXP7
SATA_RXN8
SATA_RXP8
SATA_TXN8
SATA_TXP8
R2301 100Ohm1%
Reserve TP for XDP
PCIE_RXN11_M2_SSD
PCIE_RXP11_M2_SSD
PCIE_TXN11_M2_SSD
PCIE_TXP11_M2_SSD
SATA_RXN12_M2_SSD
SATA_RXP12_M2_SSD
SATA_TXN12_M2_SSD
SATA_TXP12_M2_SSD
1 2
T2323
T2324
1 2
1 2
1
1
C23220.1UF/16V
C23230.1UF/16V
PCIE_TXN_WLAN_C
PCIE_TXP_WLAN_C
PCIE_RCOMPN
PCIE_RCOMPP
PROC_PRDY#
PROV_PREQ#
PIRQA#
U0301H
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
947859
0101-03860PB
SSIC / USB3
USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
(OD)
GPP_E5/DEVSLP1
(OD)
GPP_E6/DEVSLP2
(OD)
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
USB_PN10
USB_PP10
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
1
J2
J3
1
H2
H3
G4
H1
1 2
R2303 0Ohm@
1 2
R2324 0Ohm@
1 2
R2325 0Ohm@
1 2
R2326 0Ohm@
USB3_RXN1
USB3_RXP1
USB3_TXN1
USB3_TXP1
USB3_RXN2
USB3_RXP2
USB3_TXN2
USB3_TXP2
USB3_RXN3
USB3_RXP3
USB3_TXN3
USB3_TXP3
USB3_RXN4
USB3_RXP4
USB3_TXN4
USB3_TXP4
USB_PN10
USB_PP10
USBCOMP
USB2_ID_OTG
USB2_VBUSSENSE_OTG
OC0#
OC1#
OC2#
OC3#
T2326
SATA_DEVSLP1
SATA_DEVSLP2
T2325
SATA_SSD1_PEDET
SATA_SSD2_PEDET
SATA_LED#
20161227 R1.0 Kai
Add USB Hub connec to SHB / TPanel
Co-lay USB Hub / TPanel
1 2
R2302 113Ohm1%
1 2
R2319 1KOhm
1 2
R2320 1KOhm
1 2
R2308 0Ohm
1 2
R2309 0Ohm
1 2
R2310 0Ohm
1 2
R2311 0Ohm
USB3_RXN1 52
USB3_RXP1 52
USB3_TXN1 52
USB3_TXP1 52
USB3_RXN2 52
USB3_RXP2 52
USB3_TXN2 52
USB3_TXP2 52
USB3_RXN3 41
USB3_RXP3 41
USB3_TXN3 41
USB3_TXP3 41
USB3_RXN4 41
USB3_RXP4 41
USB3_TXN4 41
USB3_TXP4 41
USB_PN1_30 52
USB_PP1_30 52
USB_PN2_30 52
USB_PP2_30 52
USB_PN3_TYPEC 41
USB_PP3_TYPEC 41
USB_PN4_TYPEC 41
USB_PP4_TYPEC 41
USB_PN5_20 64
USB_PP5_20 64
USB_PN6_BT 53
USB_PP6_BT 53
USB_PN7_CCD 45
USB_PP7_CCD 45
USB_PN8_CR 64
USB_PP8_CR 64
USB_PN9_FP 69
USB_PP9_FP 69
USB_OC0#_PCH 52
USB_OC1#_PCH 52
USB_OC2#_PCH 64
USB_OC3#_PCH 41
SATA_DEVSLP1 51
SATA_DEVSLP2 51
SATA_SSD1_PEDET 51
SATA_SSD2_PEDET 51
USB_PN10_HUB 63
USB_PP10_HUB 63
USB_PN10_TP 45
USB_PP10_TP 45
USB3.0 S/C
USB3.0
USB3.0 Type C
USB3.0 Type C
USB3.0 S/C
USB3.0
USB3.0 Type C
USB3.0 Type C
USB20 (IO BD)
Bluetooth
Camera (EDP CONN)
Card reader (IO BD)
FingerPrinter
USB2_COMP PDG 1.0 R=113 +-1%
MOW 5.1.3 If the platform does not support Dual Role, then
USB2_ID pin shall be connected directly to GND.
20161220 R1.1 Kai
P21 ~ P23 / P65
Add SHB & G-sensor in MB
USB30 with USB Chager
USB30
USB20(IO BD)
Type C
SATA SSD1
SATA SSD2
OC3#
OC2#
OC1#
OC0#
SATA_LED#
PIRQA#
3 4
7 8
1 2
5 6
1 2
R2304 10KOhm
@
1 2
R2318 10KOhm
+3VSUS
RN2301B10KOhm
RN2301D10KOhm
RN2301A10KOhm
RN2301C10KOhm
+3VS
USB30
Capture from 545659_545659_SKL_PCH_LP_EDS_Rev1_0_pub
Please refer the latest Doc.
A A
PCH(4)_USB/PCIE/SATA
PCH(4)_USB/PCIE/SATA
PCH(4)_USB/PCIE/SATA
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Title :
James_Liao
James_Liao
James_Liao
23 94Friday, March 10, 2017
23 94Friday, March 10, 2017
23 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
24
D D
C C
R1.1 remove GPU
B B
R1.1 remove GPU
A A
U0301I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
947859
0101-03860PB
CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
Any differential clock pair not being used must be left as no connect
Any differential clock pair not being used must be left as no connect
Any differential clock pair not being used must be left as no connectAny differential clock pair not being used must be left as no connect
CLK_PCIE_SSD1#_PCH51
CLK_PCIE_SSD1_PCH51
CLK_REQ1_SSD1#51
CLK_PCIE_SSD2#_PCH51
CLK_PCIE_SSD2_PCH51
CLK_REQ2_SSD2#51
CLK_PCIE_WLAN#_PCH53
CLK_PCIE_WLAN_PCH53
CLK_REQ4_WLAN#53
CLK_PCIE_SSD1#_PCH
CLK_REQ1_SSD1# CLK_REQ1_SSD1#_R
CLK_PCIE_SSD2#_PCH
CLK_PCIE_SSD2_PCH
CLK_REQ2_SSD2#
CLK_PCIE_WLAN#_PCH
CLK_PCIE_WLAN_PCH
CLK_REQ4_WLAN#
SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
SRCCLKREQ#[5:0] (PDG v1.3 Page 835)SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any un-used, disabled, must be left as no connects at the PCH side on the platform.Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any used, enabled, should connect to a PCIe* connector pin or a device down ball
Any used, enabled, should connect to a PCIe* connector pin or a device down ball
Any used, enabled, should connect to a PCIe* connector pin or a device down ballAny used, enabled, should connect to a PCIe* connector pin or a device down ball
with a 10K Ohm ±10% external pull-up resistor to core rail.
with a 10K Ohm ±10% external pull-up resistor to core rail.
with a 10K Ohm ±10% external pull-up resistor to core rail.with a 10K Ohm ±10% external pull-up resistor to core rail.
CLK_REQ4_WLAN#_R
CLK_REQ2_SSD2#_R
CLK_REQ1_SSD1#_R
5
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
SP2405
SP2406
SP2407
SP2408
SP2409
SP2410
SP2412
SP2413
SP2414
1 2
R2429 10KOhm
1 2
R2408 10KOhm@
1 2
R2411 10KOhm
1 2
R2414 10KOhm
1 2
R2416 10KOhm
1 2
R2430 10KOhm
1 2
R2431 10KOhm
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@
@
@
CSI2_COMP
GPP_D4
1
EMMC_RCOMP
CLK_PCIE_SSD1#_PCH_R
CLK_PCIE_SSD1_PCH_RCLK_PCIE_SSD1_PCH
CLK_PCIE_SSD2#_PCH_R
CLK_PCIE_SSD2_PCH_R
CLK_REQ2_SSD2#_R
CLK_PCIE_WLAN#_PCH_R
CLK_PCIE_WLAN_PCH_R
CLK_REQ4_WLAN#_R
+3VSUS
+3VS
+3VS
+3VS
T2417
R2418
1 2
100Ohm
RES 100 OHM 1/16W (0402) 1%
12
R2419
200Ohm
RES 200 OHM 1/16W (0402) 1%
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
0101-03860PB
4
U0301J
947859
eMMC_D0 49
eMMC_D1 49
eMMC_D2 49
eMMC_D3 49
eMMC_D4 49
eMMC_D5 49
eMMC_D6 49
eMMC_D7 49
eMMC_RCLK 49
eMMC_CLK 49
eMMC_CMD 49
CLOCK SIGNALS
Ball E37
Ball E37
Ball E37Ball E37
XTAL_24M_IN
Ball E35
Ball E35
Ball E35Ball E35
XTAL_24M_OUT
PCH(5)_CLK
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
R2432 0Ohm/ U22
R2433 0Ohm/U22
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
需需需需需需需需
GND
R2401 1MOhm
SP2401
0Ohm
1 2
XTAL_24M_OUT_R
12
C2402
/U22
10PF/50V
3
SUSCLK_PCH
XTAL_24M_IN
XTAL_24M_OUT
XCLK_BIASREF
XTAL_32K_X1
XTAL_32K_X2
SRTC_RST#
RTC_RST#
SW_RTCRST30
/U22
X2401
24MHZ
4
/U22
2
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
24MHz signal
VCCRTC is sourced from Vbatt in G3 or VCCDSW_3p3 in Non-G3 state,
platform designers must ensure the effective voltage at VCCRTC does not
exceed 3.2V.
R2425
0Ohm@
D2401
RB751V-40
0.37V/30mA
D2402
RB751V-40
0.37V/30mA
1
1
G
X2402
1 2
32.768KHZ
07V080000075
+/-20ppm/9PF
+RTC_AC
+RTC_BAT
32
3
D
S
2
12
1 2
1 2
2
1UF/6.3V
1
T2418
1 2
R2417 2.71Kohm
R2406 0Ohm
12
13
12
C2401
/U22
10PF/50V
+VCC_RTC
C2407
0.5%
1 2
12
XTAL_32K_X1
XTAL_32K_X2
R2420
1KOhm
1 2
@
+VCCF24NS_1P0
R2407
10KOhm
12
12
Q2401
2N7002
12
R2402 10MOhm
C2404
7PF/50V
1 2
+3VA
R2423
1.5KOhm
1%
R2424
45.3KOhm
1%
R2405 1KOhm
1
JRST2402
1
SGL_JUMP
2
@
2
1
JRST2401
1
SGL_JUMP
2
@
2
SP2402
0Ohm
XTAL_32K_X1_R
C2403
7PF/50V
1 2
12
C2405
1UF/6.3V
R2455 0Ohm
12
C2406
1UF/6.3V
2015.11.23
R1.1
Vendor suggestion 7PF
+RTCBAT
Q2402
2N7002
1
1
12
R2409
10MOhm
CON2401
4
SIDE2
2
2
1
1
3
SIDE1
WtoB_CON_2P
12V17GISM030
P/N:1217-0105000
P/N:1217-0105000
P/N:1217-0105000 P/N:1217-0105000
1 2
R2403 20KOhm
R1.2 MB_Lesson learnt template
N/A
1 2
1 2
R2404 20KOhm
12
C2409
0.1UF/16V
@
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
SU4EA
SU4EA
SU4EA
+1.8VSUS
G
3
2
12
32
D
S
R2412
100KOhm
1%
+VCC_RTC
Engineer:
Engineer:
Engineer:
1
Title :
Title :
Title :
RTC_IN# 22
PCH(5)_CLK
PCH(5)_CLK
PCH(5)_CLK
James_Liao
James_Liao
James_Liao
24 94Friday, March 10, 2017
24 94Friday, March 10, 2017
24 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
25
In Table 42-1 of PDG (#561280, Rev1p0)
PROCPWRGD is PCH to CPU, but KBL-U don't has this pin at CPU side.
we assume it's conted in MCP package.
D D
ALL_SYS_PWRGD delay 99 ms from EC
DSW function / non-AMT
PCH_PWROK logic
C C
1 2
DE_ALL_SYS_PGD_EC30
R2544
SYS_PWROK logic
B B
1 2
SYS_PWROK_EC30
R2546
VCCST_PWRGD logic
DELAY_ALL_SYSTEM_PWRGD
ALL_SYSTEM_PWRGD
So follow CRB to reserve TP only.
PM_RSMRST#30
T2501
SYS_PWROK_PCH30
T2513
T2512
WAKE_PCIE#53
DE_ALL_SYS_PGD_EC_R
PM_SUSB#
PM_SUSB#
R2529
R2530 0Ohm@
PLT_RST#
1 2
H_CPUPWRGD_TP H_CPUPWRGD
1
SYS_PWROK_PCH
PCH_PWROK_PCH
PM_RSMRST_R
1
1
SUSACK#
1 2
1 2
SP2501
R2503 1KOhm@
R2506 0Ohm
R2509 0Ohm
R2510 0Ohm@
T2511
T2502
T2508
ALL_SYSTEM_PWRGD30,92
DELAY_ALL_SYSTEM_PWRGD30
U2504
A
1
VCC
B
2
3 4
GND
Vcc=2~5.5
For shut down Sequence
Tplt17 < 1us
U2505
A
1
5
VCC
B
2
3 4
GND
Vcc=2~5.5
Y
SYS_PWROK_AND
1 2
1 2
1 2
1 2
1
1
1
VRM_PWRGD80,92
5
Y
LAN_WAKE#
PLT_RST#
+3VSUS
For Intel power sequence requestment
ALL_SYS_PWRGD to Delay_ALL_SYS_PGD >2ms
Delay By EC(2ms+ EC processing time (3ms~33ms)
12
R2545
100KOhm
@
10V240000005
12
@
H_VCCST_PWRGD_L
PCH(6)_POWER MANAGE
U0301K
PM_SYS_RESET#_R
PM_RSMRST_R
VCCST_PWRGD_CPU
PCH_DPWROK
SUS_PWR_ACK_R
SUSACK#_RSUS_PWR_ACK_R
GPD11
GPD7
R2531 0Ohm@
SP2506
D2501 RB751V-40
D2502 RB751V-40
12
C2540
0.1UF/16V
@
1 2
R2548
R2547
100KOhm
10V240000005
U2503
1
NC
2
A
3 4
GND
74AUP1G07GW
06V030000021
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
947859
0101-03860PB
1 2
SYS_PWROK_PCH
5
VCC
Y
ALL_SYSTEM_PWRGD_PMOK
1 2
1 2
1 2
DE_ALL_SYS_PGD_HW 30
VR_READY_PMOK
PLT_RST#
+3VSUS
12
C2504
0.1UF/16V
12
GND
12
C2502
100PF/50V
@
R1.1 mount
R2553 0Ohm
GPP_B12/SLP_S0#
GPD10/SLP_S5#
GPD9/SLP_WLAN#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
U2502
A
1
B
2
3 4
GND
Vcc=2~5.5
1 2
R2517 0Ohm@
R2554
100KOhm
N/A
U2501
1
A
2
B
GND3Y
SN74LVC1G08DCKR
GND
1 2
R2515 0OhmN/A
1 2
GPD4/SLP_S3#
GPD5/SLP_S4#
SLP_SUS#
SLP_LAN#
GPD6/SLP_A#
GPP_A11/PME#
INTRUDER#
5
VCC
Y
@
5
VCC
4
+1.0V
SLP_S0#
AT11
PM_SUSB#
AP15
PM_SUSC#
BA16
AY16
GPD10
SLP_SUS#
AN15
SLP_LAN#
AW15
SLP_WLAN#
BB17
ME_PM_SLP_M#_PCH
AN16
BA15
AC_PRESENT_R
AY15
AU13
BATLOW#
AU11
PME#
SM_INTRUDER#
AP16
MPHY_EXT_PWR_GATEB_R
AM10
VR_ALERT#
AM11
+3VSUS
R1.2 MB_Lesson learnt template
PM_PWROK
+3V
12
R2520
1KOhm
R2521 60.4Ohm1%
12
C2505
0.1UF/16V
@
1 2
R2505 0OhmN/A
12
R2519
10KOhm
GND
R1.2 MB_Lesson learnt template
12
C2541
0.1UF/16V
@
GND
1 2
+VDDQ/+VCCST_CPU/+VCCSTG to VCCST_PWRGD must > 1ms
1 2
R2532 0Ohm
PCH_PWROK_PCH
12
C2516
@
0.1UF/16V
12
C2503
100PF/50V
@
GNDGNDGND
VCCST_PWRGD_CPUVCCST_PWRGD_C PU_R
12
R2516
10KOhm
1
T2503
1
T2504
If Deep Sx is not implemented on the platform, this signal may be left as no connect
1
T2510
1
T2505
1
T2506
1
T2507
1
PM_PWRBTN# 30
ME_AC_PRESENT 30
T2509
internal pull high
SLP_S3# and SLP_S4# logic
PM_SUSB#
1 2
R2502 0Ohm
SUSB_EC#30,57,91,92
PM_SUSC#
1 2
R2504 0Ohm
SUSC_EC#30,57, 91
BATLOW#
LAN_WAKE#
GPD7
WAKE_PCIE#
AC_PRESENT_R
BUF_PLT_RST# 30,32,49,51,53,62
SM_INTRUDER#
Set to GPI
PME#
VR_ALERT#
PM_SYS_RESET#_R
internal pull high
N/AN/A
PM_SUSB# 30
20161227 R1.1 Kai
Correct location
PM_SUSC# 30
1 2
R2522 10KOhm
1 2
R2523 10KOhm
1 2
R2524 10KOhm
1 2
R2525 1KOhm
1 2
R2526 10KOhm
1 2
R2513 1MOhm
1 2
R2527 10KOhm@
1 2
R2528 10KOhm@
1 2
R2501 10KOhmN/ A
+3VSUS
+VCC_RTC+3VSUS
+3VSUS
A A
PCH(6)_POWER MANAGE
PCH(6)_POWER MANAGE
PCH(6)_POWER MANAGE
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
Title :
James_Liao
James_Liao
James_Liao
25 94Friday, March 10, 2017
25 94Friday, March 10, 2017
25 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
PCH(7)_POWER
26
4
3
2
1
+1.0VSUS
4A
D D
+1.0VSUS_ORG
12
C2601
1UF/6.3V
near AB19
vx_c0402_small
+VCCPRIM_CORE
12
C2602
1UF/6.3V
near AF18
vx_c0402_small
+1.0VSUS_ORG
12
C2603
near K17
1UF/6.3V
C C
+VCCMPHYGTAON_1P0_LS_SIP
2A
12
12
+3VSUS_ORG
12
near V19
B B
A A
C2605
47UF/6.3V
@
C2611
1UF/6.3V
vx_c0402_small
+1.0VSUS
+3VSUS
C2606
1UF/6.3V
near N15near N15
R2604 0Ohm
R2602 0Ohm
vx_c0402_small
+VCCAMPHYPLL_1P0
12
near K15
R1.2 MB_Lesson learnt template
+VCCAPLLEBB_1P0
near N18
1 2
1 2
S1V040200001
+VCCAPLL_1P0
C2608
47uF/6.3V
C2609
1UF/10V
@
C2607
1UF/6.3V
vx_c0402_small
12
@
+VCCPAZIO
12
R2640 0Ohm
R2637 0Ohm
R2638 0Ohm
R2639 0Ohm
R1.2 MB_Lesson learnt template
+3VSUS_ORG
12
C2612
1UF/6.3V
12
C2636
0.1UF/16V
12
C2637
0.1UF/16V
EMI request for Kaby Lake
Recommended Routing : Stripline < 2"
Alternative Routing : Microstrip <1"
(less noise-reduction)
+VCCMPHYGTAON_1P0_LS_SIP
1 2
S1V080500001
1 2
S1V080500001
1 2
S1V040200001
1 2
+VCCPDSW_3P3
+1.0VSUS_ORG
B2601 75OHM
GND
B2602 75OHM
GND
2A
Decoupling cap for internal power
+VCCDSW_1P0
+1.0VSUS_ORG
R2648 0Ohm
+VCCSRAM_1P0
R2649 0Ohm
09V010000096
2 1
12
C2640
2PF/25V
NPO/+/-0.25PF
vx_c0201
09V010000096
2 1
12
C2642
2PF/25V
NPO/+/-0.25PF
vx_c0201
+VCCSRAM_1P0
0.642A
+VCCAMPHYPLL_1P0
0.088A
0.033A
12
@
R1.2 MB_Lesson learnt template
2.574A
1 2
C2604 1UF/6.3V
near AL1
1 2
C2610 1UF/6.3V
1 2
12
C2641
2PF/25V
NPO/+/-0.25PF
vx_c0201
12
C2643
2PF/25V
NPO/+/-0.25PF
vx_c0201
+VCCAPLL_1P0_SOC
C2644 0.1UF/16V
+VCCPAZIO_SOC
1 2
vx_c0402_small
near AF20
1 2
C2645 0.1UF/16V
@
+VCCAPLL_1P0_SOC
near V15
+VCCPAZIO_SOC
near AJ19
@
1 2
+VCCAPLLEBB_1P0
C2628
0.1UF/16V
0.696A
0.022A
0.088A
0.026A
0.696A
0.118A
0.068A
0.011A
0.642A
0.075A
0.696A
0.033A
PCIe Gen3 Lane X10
USB3 Port X3
All HSIO disabled (basic comsunption)
=0.154x10+0.132x3+0.064
=2 A
U0301O
AB19
AB20
AB17
AD17
AD18
AK20
AF18
AF19
AJ17
AJ19
AJ16
AF20
AF21
AJ21
P18
V20
V21
AL1
K17
L1
N15
N16
N17
P15
P16
K15
L15
V15
Y18
T19
T20
N18
CPU POWER 4 OF 4
VCCPRIM_1P0_1
VCCPRIM_1P0_2
VCCPRIM_1P0_3
VCCPRIM_CORE_1
VCCPRIM_CORE_2
VCCPRIM_CORE_3
VCCPRIM_CORE_4
DCPDSW_1p0
VCCMPHYAON_1P0_1
VCCMPHYAON_1P0_2
VCCMPHYGT_1P0_1
VCCMPHYGT_1P0_2
VCCMPHYGT_1P0_3
VCCMPHYGT_1P0_4
VCCMPHYGT_1P0_5
VCCAMPHYPLL_1P0_1
VCCAMPHYPLL_1P0_2
VCCAPLL_1P0
VCCPRIM_1P0_4
VCCPRIM_1P0_5
VCCDSW_3p3_1
VCCDSW_3p3_2
VCCDSW_3p3_3
VCCHDA
VCCSPI
VCCSRAM_1P0_1
VCCSRAM_1P0_2
VCCSRAM_1P0_3
VCCSRAM_1P0_4
VCCPRIM_3p3_1
VCCPRIM_1P0_6
VCCAPLLEBB_1P0
947859
0101-03860PB
+1.0VSUS +1.0VSUS_ORG
+1.8VSUS +1.8VSUS_ORG
R2601
1 2
0Ohm
R2603
1 2
0Ohm
R2605
1 2
0Ohm
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
S1V040200001
S1V060300001
S1V040200001
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3p3_2
VCCPRIM_1P0_7
VCCATS_1p8
VCCRTCPRIM_3p3
VCCRTC_1
VCCRTC_2
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
0.5A
1A
0.5A
AK15
0.02A
AG15
Y16
Y15
T16
AF16
AD15
V19
0.075A
T1
0.696A
AA1
0.006A
AK17
0.001A
AK19
BB14
BB10
VCCRTCEXT
A14
0.035A
K19
0.029A
L21
0.024A
N20
0.033A
L19
0.004A
A10
0.0039A
AN11
AN13
Intel confirm pull down 1k
+3VSUS_ORG+3VSUS
0.004A
0.006A
0.008A
1 2
C2634 1UF/6.3V
GND
1 2
C2620 1UF/6.3V
near BB10
12
12
R2646
1KOhm
R2647
1KOhm
R1.1 USB short mount
+3VSUS
0.006A
0.161A
near AK19
0.001A
GND
@
1 2
R2636 0Ohm
Q2601
PJA3411
D
3
G
1
1
2
3
1
E1
B1
C2
Q2602
BC856BS
N/A
C1
B2
E24
5
6
vx_c0402_small
1 2
C2613 1UF/6.3V
near Y16
vx_c0402_small
1 2
C2614 1UF/6.3V
near T16
R1.2 MB_Lesson learnt template
+3VSUS_ORG
R2650
0Ohm
12
R2635
100KOhm
N/A
1 2
0.0041A
1 2
C2619 1UF/6.3V
near AK19
S
23
2
+VCC_RTC
GND
1 2
C2646
0.1UF/16V
@
+VCCPDSW_3P3
+1.8VSUS_ORG
+V1.8A_SIP
12
near A10
C2615
1UF/6.3V
R2624
0Ohm
S1V040200001
near AA1
+VCC19P2_1P0
+VCCF100_1P0
+VCCF135_1P0
+VCCF100OC_1P0
+VCCF24NS_1P0
+VCC24TBT_1P0
+1.0VSUS_ORG
+1.8VSUS_ORG
12
12
12
vx_c0402_small
C2625
1UF/6.3V
near AK17
S1V040200001
S1V040200001
S1V040200001
S1V040200001
S1V040200001
S1V040200001
C2624
1UF/6.3V
R2627
R2628
R2629
R2630
R2631
R2632
0Ohm
0Ohm
0Ohm
0Ohm
0Ohm
0Ohm
12
12
12
12
12
12
+3VSUS_ORG
12
12
C2617
C2618
1UF/6.3V
1UF/6.3V
near AK17 near AK17
+1.0VSUS_ORG
+1.0VSUS_ORG
+1.0VSUS_ORG
+1.0VSUS_ORG
+1.0VSUS_ORG
+1.0VSUS_ORG
+3VSUS_ORG
12
R2634
100KOhm
N/A
5
4
3
2
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
SU4EA
SU4EA
SU4EA
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
PCH(7)_POWER
PCH(7)_POWER
PCH(7)_POWER
James_Liao
James_Liao
James_Liao
26 94Friday, March 10, 2017
26 94Friday, March 10, 2017
26 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
D D
C C
4
3
2
1
B B
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
<Title>
<Title>
<Title>
SU4EA <RevCode>
A
SU4EA <RevCode>
A
SU4EA <RevCode>
A
27 94Friday, March 10, 2017
27 94Friday, March 10, 2017
2
27 94Friday, March 10, 2017
1
5
4
3
2
1
28
D D
+3VSUS
+3VA
1 2
R2802 0Ohm
1 2
R2830 0Ohm
@
55mA
15WW06 MOW Pull-up Resistors on SPI_IO2 and SPI_IO3 are no longer needed
1 2
SPI_WP#_IO220
SPI_SO20
SPI_CS#020
F_CS#_EC30
F_SDIO_EC30
C C
PCH_UATR0_DEBUG_TX21
PCH_UATR0_DEBUG_RX21
R2805 33Ohm
1 2
R2806 33Ohm
1 2
R2807 33Ohm
1 2
R2808 33Ohm
1 2
R2809 33Ohm
+3VM_SPI
PCH_UATR0_DEBUG_TX
PCH_UATR0_DEBUG_RX
SPI_CS#0
R2850 0Ohm/ Debug
SPI_SO
R2851 0Ohm/ Debug
SPI_CLK
R2852 0Ohm/ Debug
SPI_SI
R2853 0Ohm/ Debug
SPI_HOLD#_IO3
SPI1_CS#0
SPI1_SO
SPI1_WP#
+3VM_SPI
+3VM_SPI
12
R2811
1KOhm @
1
2
3
4
5
12
6
12
12
7
8
12
9
10
11
12
12V18GWSM055
12
R2812
3.3KOhm
@
/Debug
CON2810
1
2
SIDE1
3
4
5
6
7
8
9
10
11
SIDE2
12
FPC_CON_12P
U2801
1
CS#
2
DO(IO1)
3
WP#(IO2)
4
GND
W25Q64FVSSIQ
05V000000025
13
14
8
VCC
SPI1_HOLD#
7
HOLD#(IO3)
DI(IO0)
SPI1_CLK
6
CLK
SPI1_SI
5
NON-POA 05V000000025 8M
POA 05V000000031 16M
PCH(9)_SPI_SMB
+3VM_SPI
12
C2801
0.1UF/16V
SPI ROM size
*
12
R2813
@
1KOhm
FAE: 2015/10/14
1 2
R2820 1KOhm
@
1 2
R2814 33Ohm
1 2
R2815 33Ohm
1 2
R2816 33Ohm
1 2
R2818 33Ohm
1 2
R2819 33Ohm
1 2
WW48MOW(ES Sample)
In Skylake Platform Design Guides (PDG) under “Platform Debug & Test Hooks”
chapter, HOOK[3] pin from XDP/CMC header needs to be routed to PCH SPI0_MOSI
pin. The termination resistor can be a value from 1K to 3K ohm pull up to Always rail
(not Core rail) with voltage value from 0.8V to 3.3V. This will ensure PCH hardware
straps are not overridden unintentionally and cause boot issues.
R2821 3KOhm
P/NT-pad function Size
+3VM_SPI
SPI_HOLD#_IO3 20
SPI_CLK 20
SPI_SI 20
F_SCK_EC 30
F_SDI_EC 30
PCH SMBus
B B
+12VSUS
2
G
A A
EC
SMB1_CLK30 SML1_CLK 20
GPU
5
4
6 1
S
D
Q2802A
UM6K1NG1DTN
Rdson=13Ohm/Vgs(th)=1.5V
N/A
UM6K1NG1DTN
5
3 4
D
Q2802B
N/A
PCH
G
S
3
SML1_DAT 20SMB1_DAT30
Title :
Title :
Title :
PCH(9)_SPI_SMB
PCH(9)_SPI_SMB
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
SU4EA
SU4EA
SU4EA
Engineer:
Engineer:
Engineer:
1
PCH(9)_SPI_SMB
James_Liao
James_Liao
James_Liao
28 94Friday, March 10, 2017
28 94Friday, March 10, 2017
28 94Friday, March 10, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
D D
C C
4
3
2
1
B B
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
<Title>
<Title>
<Title>
SU4EA <RevCode>
A
SU4EA <RevCode>
A
SU4EA <RevCode>
A
29 94Friday, March 10, 2017
29 94Friday, March 10, 2017
2
29 94Friday, March 10, 2017
1
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