Acer Swift 3 SF314-52G Schematic
5
4
3
2
1
HE4EA Block Diagram
D D
14" Panel
eDP CONN.
eDP
LPDDR3_CHB
LPDDR3 Memory Down
LPDDR3_CHA
HDMI 1.4
HDMI CONN
VRAM GDDR5
128Mbx32 bits x 2-pcs
TMDS
HDMI LS
dGPU TDP 25W
PCIe X4(1, 2, 3, 4)GDDR5
NVIDIA N17S-G1
TPM
NUVOTON/NPCT650AA0WX
Debug Conn.
DDI1
LPC
KabyLake-U
CPU
U22
RU42
USB 3.0
1
1
2
2
3, 4
3
4
LPDDR3 Memory Down
USB3.0 Port S/C
USB3.0 Port
USB Type-C
Power
+VCORE
+VCCGT
+VCCSA
Page 80
System (5V & 3.3V)
C C
Keyboard / ClickPad
EC
Thermal/Fan
IT8987E/BX
PCH
USB 2.0
SPI
SPI ROM
5
USB2.0 Port
Page 81
+1.0VSUS
7
Camera
8
CR CONTROLLER
REALTEK/RTS5170-GR
SD Card
DDR & VTT
+1.8VSUS
Page 82
Page 83
Page 84
PEX_VDD
9
Universal Jack
Speaker
B B
DMIC
Audio Codec
REALTEK/ALC255-CGT
HDA
10
Finger Printer
Touch Panel
FBVDDQ
NVVDD
Page 85
Page 86
Page 87
Battery Charger
EMMC
EMMC
PCIe X1 (9)
PCIe X4 (5, 6, 7, 8)
SATA1
PCIe X2 (11, 12)
SATA2
6
M.2 2230
WLAN & BT
M.2 2240/2260/2280
1V8_AON
Load Switch
SSD1
Power Protect
M.2 2240/2260/2280
Page 88
Page 90
Page 91
Page 92
SSD2
A A
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
Block Diagram
Block Diagram
Block Diagram
Kai_Shen
Kai_Shen
Kai_Shen
1 94Wednesday, March 29, 2017
1 94Wednesday, March 29, 2017
1 94Wednesday, March 29, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
Option
Optional
N/A
/@
/Debug
D D
Remark
Mount
Ummount
Debug only
/SSD1 Support M.2 SSD1
Support M.2 SSD2/SSD2
/EMMC Support EMMC
Reserved EMI part/EMI
/UMA Support UMA
/VGA Support VGA
/SDP Support SDP DRAM
/DDP Support DDP DRAM
/U22
/U42
/14inch
/15inch
C C
/TPM
Support 2+2 CPU
Support 4+2 CPU
Support 14"
Support 15"
Support TPM function
/IOAC
/NON-IOAC
/PTP
/NON-PTP
B B
Support IOAC
Not support IOAC
Support PTP
Not support PTP
A A
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
Option
Option
Option
Kai_Shen
Kai_Shen
Kai_Shen
2 94Wednesday, March 29, 2017
2 94Wednesday, March 29, 2017
2 94Wednesday, March 29, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
03
D D
HDMI_TXN248
HDMI_TXP248
DDI Port 1: HDMI
+VCCIO
C C
HDMI_TXN148
HDMI_TXP148
HDMI_TXN048
HDMI_TXP048
HDMI_CLKN48
HDMI_CLKP48
HDMI_SCL_PCH48
HDMI_SDA_PCH48
R0301 24.9Ohm1%
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK EXT_SMI#_R EXT_SMI#
DDPC_CTRLDAT A
12
DP_COMP
SKYLAKE-U symbol ReV0.53 #545316 / Ballout_Rev0_71 #543787 / PEGA local PN is 4201-0062000
U0301A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCL K
N8
GPP_E21/DDPC_CTRLDAT A
N11
GPP_E22
N12
GPP_E23
E52
eDP_RCOMP
947859
0101-03860PB
CPU(1)_DDI_eDP
EDP_TXN0
RSVD_1
RSVD_2
C47
EDP_TXP0
C46
EDP_TXN1
D46
EDP_TXP1
C45
A45
B45
A47
B47
EDP_AUXN
E45
EDP_AUXP
F45
B52
G50
F50
E48
F48
G46
F46
DPB_HPD
L9
L7
L6
EXT_SCI#_R EXT_ SCI#
N9
eDP_HPD
L10
LCD_BKLTEN_PCH
R12
LCD_BL_PWM_PCH
R11
EDP_VDD_EN
U13
DDI
DISPLAY SIDEBANDS
EDP
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
eDP_BKLTEN
eDP_BKLTCTL
eDP_VDDEN
1 2
SP0302 0Ohm
1 2
SP0303 0Ohm
+1.0V
+3VS
+VCCIO
EDP_TXN0 45
EDP_TXP0 45
EDP_TXN1 45
EDP_TXP1 45
EDP_AUXN 45
EDP_AUXP 45
+1.0V 5,7,9,25,32,57,91
+3VS 4 ,20,21,22,23,24,30,31,32,36,41,44,45,48,49,50,51,53,56 ,57,62,64,74,87,91,92
+VCCIO 5,7,9,57,91
DDI#1 DDPB_CTRLDATA
DDI#2 DDPC_CTRLDATA
DDPD_CTRLDATA
- Internal weak pull down 20k ohm
- 0 : port is not detected
1 : port is deteccted
DDPB_CTRLDATA
DDPB_CTRLCLK
both pull-up deleted, HDMI side pull-up
DPB_HPD 48
EXT_SMI# 30,44
EXT_SCI# 30
eDP_HPD 45
LCD_BKLTEN_PCH 21,45
LCD_BL_PWM_PCH 45
EDP_VDD_EN 45
DDPC_CTRLDAT A
DDPC_CTRLCLK
EXT_SCI#
EXT_SMI#
HDMI HPD
eDP HPD
R0305 2.2KOhm@
R0340 2.2KOhm@
R0307 10KOhm
R0308 10KOhm
+3VS
1 2
1 2
+3VS
1 2
1 2
141024 follow PDG V1.0 Table 10-4
Rpu = 1K ohm 5%
12
R0311
1KOhm
H_THRMTRIP#32
B B
THRO_CPU30
A A
PROCHOT#88
VR_HOT#80
H_PROCHOT# H_PROCHOT#_R
G
2
S
12
R0312
1KOhm
5%
R0314 499Ohm
1
1
3
32
R0341 0Ohm
D
Q0301
2N7002
SP0304 0Ohm
@/SP
R0320 0Ohm@
Rs = 500 ohm 5%
1 2
R0341由EC control
(depends on under-shoot measurement result),預預0ohm
12
12
12
H_PECI_EC30
觸觸觸觸觸觸觸觸觸觸觸觸觸
1 2
R0326 0Ohm
Closeer EC
T0301
1 2
R0315 43Ohm
1 2
SP0301 0Ohm
@/SP
1 2
R0316 49.9Ohm
1 2
R0317 49.9Ohm
1 2
R0318 49.9Ohm
1 2
R0319 49.9Ohm
H_PROCHOT#
12
C0301
0.1UF/16V
GND
+1.0V+VCCIO+1.0V
1
T0306
70-200 ohm
觸是是是是
12
R0313
49.9Ohm
1%
@
TP_CATERR#_R
H_PECI
H_THRMTRIP#_R
1
SKTOCC#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
0101-03860PB
U0301D
947859
CPU MISC
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
XDP_TCLK
B61
XDP_TDI_CPU
D60
XDP_TDO_CPU
A61
XDP_TMS_CPU
C60
XDP_TRST_CPU_N
B59
PCH_JTAG_TCLK
B56
XDP_TDI_CPU
D59
XDP_TDO_CPU
A56
XDP_TMS_CPU
C59
XDP_TRST_CPU_N XDP_TCLK
C61
XDP_TCLK
A59
1
T0315
XDP_TDO_CPU
XDP_TMS_CPU
XDP_TDI_CPU
XDP_TRST_CPU_N
R0323 51Ohm
R0324 51Ohm
12
12
+VCCIO
1
1
1
T0319
T0318
T0317
CPU(1)_DDI_eDP
CPU(1)_DDI_eDP
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
CPU(1)_DDI_eDP
Kai_Shen
Kai_Shen
Kai_Shen
3 94Friday, April 07, 2017
3 94Friday, April 07, 2017
3 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
of
5
4
3
2
1
+1.2V
+3VS
+3VSUS
M_A_D[63:0]16 M_B_D[63:0]17
M_A_DQS#[7:0] 16
Astrea used Non-Interleave
U0301B
D D
NIL Channel A[0..15]NIL Channel A[32..47]NIL Channel B[0..15]NIL Channel B[32..47]
C C
M_A_D0
M_A_D1
M_A_D2
M_A_D3
M_A_D4
M_A_D5
M_A_D6
M_A_D7
M_A_D8
M_A_D9
M_A_D10
M_A_D11
M_A_D12
M_A_D13
M_A_D14
M_A_D15
M_A_D32
M_A_D33
M_A_D34
M_A_D35
M_A_D36
M_A_D37
M_A_D38
M_A_D39
M_A_D40
M_A_D41
M_A_D42
M_A_D43
M_A_D44
M_A_D45
M_A_D46
M_A_D47
M_B_D0
M_B_D1
M_B_D2
M_B_D3
M_B_D4
M_B_D5
M_B_D6
M_B_D7
M_B_D8
M_B_D9
M_B_D10
M_B_D11
M_B_D12
M_B_D13
M_B_D14
M_B_D15
M_B_D32
M_B_D33
M_B_D34
M_B_D35
M_B_D36
M_B_D37
M_B_D38
M_B_D39
M_B_D40
M_B_D41
M_B_D42
M_B_D43
M_B_D44
M_B_D45
M_B_D46
M_B_D47
AL71
AL68
AN68
AN69
AL70
AL69
AN70
AN71
AR70
AR68
AU71
AU68
AR71
AR69
AU70
AU69
BB65
AW65
AW63
AY63
BA65
AY65
BA63
BB63
BA61
AW61
BB59
AW59
BB61
AY61
BA59
AY59
AY39
AW39
AY37
AW37
BB39
BA39
BA37
BB37
AY35
AW35
AY33
AW33
BB35
BA35
BA33
BB33
AY31
AW31
AY29
AW29
BB31
BA31
BA29
BB29
AY27
AW27
AY25
AW25
BB27
BA27
BA25
BB25
IL Channel A[0..63]
DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]
DDR0_DQ[16]/DDR0_D Q[32]
DDR0_DQ[17]/DDR0_D Q[33]
DDR0_DQ[18]/DDR0_D Q[34]
DDR0_DQ[19]/DDR0_D Q[35]
DDR0_DQ[20]/DDR0_D Q[36]
DDR0_DQ[21]/DDR0_D Q[37]
DDR0_DQ[22]/DDR0_D Q[38]
DDR0_DQ[23]/DDR0_D Q[39]
DDR0_DQ[24]/DDR0_D Q[40]
DDR0_DQ[25]/DDR0_D Q[41]
DDR0_DQ[26]/DDR0_D Q[42]
DDR0_DQ[27]/DDR0_D Q[43]
DDR0_DQ[28]/DDR0_D Q[44]
DDR0_DQ[29]/DDR0_D Q[45]
DDR0_DQ[30]/DDR0_D Q[46]
DDR0_DQ[31]/DDR0_D Q[47]
DDR0_DQ[32]/DDR1_D Q[0]
DDR0_DQ[33]/DDR1_D Q[1]
DDR0_DQ[34]/DDR1_D Q[2]
DDR0_DQ[35]/DDR1_D Q[3]
DDR0_DQ[36]/DDR1_D Q[4]
DDR0_DQ[37]/DDR1_D Q[5]
DDR0_DQ[38]/DDR1_D Q[6]
DDR0_DQ[39]/DDR1_D Q[7]
DDR0_DQ[40]/DDR1_D Q[8]
DDR0_DQ[41]/DDR1_D Q[9]
DDR0_DQ[42]/DDR1_D Q[10]
DDR0_DQ[43]/DDR1_D Q[11]
DDR0_DQ[44]/DDR1_D Q[12]
DDR0_DQ[45]/DDR1_D Q[13]
DDR0_DQ[46]/DDR1_D Q[14]
DDR0_DQ[47]/DDR1_D Q[15]
DDR0_DQ[48]/DDR1_D Q[32]
DDR0_DQ[49]/DDR1_D Q[33]
DDR0_DQ[50]/DDR1_D Q[34]
DDR0_DQ[51]/DDR1_D Q[35]
DDR0_DQ[52]/DDR1_D Q[36]
DDR0_DQ[53]/DDR1_D Q[37]
DDR0_DQ[54]/DDR1_D Q[38]
DDR0_DQ[55]/DDR1_D Q[39]
DDR0_DQ[56]/DDR1_D Q[40]
DDR0_DQ[57]/DDR1_D Q[41]
DDR0_DQ[58]/DDR1_D Q[42]
DDR0_DQ[59]/DDR1_D Q[43]
DDR0_DQ[60]/DDR1_D Q[44]
DDR0_DQ[61]/DDR1_D Q[45]
DDR0_DQ[62]/DDR1_D Q[46]
DDR0_DQ[63]/DDR1_D Q[47]
947859
NIL Channel A[0..15]
NIL Channel A[32..47]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT #
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR 0_MA[15]
DDR0_WE#/DDR0 _CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR 0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
NIL Channel B[0..15]
NIL Channel B[32..47]
IL Channel A DQS[0..7]
DDR0_DQSN[2]/DDR0_D QSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_D QSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_D QSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_D QSN[1]
NIL Channel A
DQS[0,1,4,5]
NIL Channel B
DQS[0,1,4,5]
DDR CH - A
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_D QSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_D QSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNT L
M_A_DQS[7:0] 16
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
M_A_DIM0_ODT0
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
M_A_DQS#0
AM70
M_A_DQS0
AM69
M_A_DQS#1
AT69
M_A_DQS1
AT70
M_A_DQS#4
BA64
M_A_DQS4
AY64
M_A_DQS#5
AY60
M_A_DQS5
BA60
M_B_DQS#0
BA38
M_B_DQS0
AY38
M_B_DQS#1
AY34
M_B_DQS1
BA34
M_B_DQS#4
BA30
M_B_DQS4
AY30
M_B_DQS#5
AY26
M_B_DQS5
BA26
AW50
AT52
AY67
AY68
BA67
DDR_PG_CTRL_S
AW67
M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9
M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9
M_A_DIM0_CLK#0 1 6
M_A_DIM0_CLK0 16
M_A_DIM0_CLK#1 1 6
M_A_DIM0_CLK1 16
M_A_DIM0_CKE0 16
M_A_DIM0_CKE1 16
M_A_DIM0_CKE2 16
M_A_DIM0_CKE3 16
M_A_DIM0_CS#0 16
M_A_DIM0_CS#1 16
M_A_DIM0_ODT0 16
M_A_CAA[9:0] 16
M_A_CAB[9:0] 16
RVP LPDDR3 floating. DDR3L GND
PDG short to GND.
DIMM_VREF_CA 18
DIMM0_VREF_DQ 18
DIMM1_VREF_DQ 18
U0301C
M_A_D16
M_A_D17
M_A_D18
M_A_D19
M_A_D20
M_A_D21
M_A_D22
M_A_D23
M_A_D24
M_A_D25
M_A_D26
M_A_D27
M_A_D28
M_A_D29
M_A_D30
NIL Channel A[16..31]NIL Channel A[48..63]NIL Channel B[16..31]NIL Channel B[48..63]
M_A_D31
M_A_D48
M_A_D49
M_A_D50
M_A_D51
M_A_D52
M_A_D53
M_A_D54
M_A_D55
M_A_D56
M_A_D57
M_A_D58
M_A_D59
M_A_D60
M_A_D61
M_A_D62
M_A_D63
M_B_D16
M_B_D17
M_B_D18
M_B_D19
M_B_D20
M_B_D21
M_B_D22
M_B_D23
M_B_D24
M_B_D25
M_B_D26
M_B_D27
M_B_D28
M_B_D29
M_B_D30
M_B_D31
M_B_D48
M_B_D49
M_B_D50
M_B_D51
M_B_D52
M_B_D53
M_B_D54
M_B_D55
M_B_D56
M_B_D57
M_B_D58
M_B_D59
M_B_D60
M_B_D61
M_B_D62
M_B_D63
AF65
AF64
AK65
AK64
AF66
AF67
AK67
AK66
AF70
AF68
AH71
AH68
AF71
AF69
AH70
AH69
AT66
AU66
AP65
AN65
AN66
AP66
AT65
AU65
AT61
AU61
AP60
AN60
AN61
AP61
AT60
AU60
AU40
AT40
AT37
AU37
AR40
AP40
AP37
AR37
AT33
AU33
AU30
AT30
AR33
AP33
AR30
AP30
AU27
AT27
AT25
AU25
AP27
AN27
AN25
AP25
AT22
AU22
AU21
AT21
AN22
AP22
AP21
AN21
IL Channel B[0..63]
DDR1_DQ[0]/DDR0_DQ [16]
DDR1_DQ[1]/DDR0_DQ [17]
DDR1_DQ[2]/DDR0_DQ [18]
DDR1_DQ[3]/DDR0_DQ [19]
DDR1_DQ[4]/DDR0_DQ [20]
DDR1_DQ[5]/DDR0_DQ [21]
DDR1_DQ[6]/DDR0_DQ [22]
DDR1_DQ[7]/DDR0_DQ [23]
DDR1_DQ[8]/DDR0_DQ [24]
DDR1_DQ[9]/DDR0_DQ [25]
DDR1_DQ[10]/DDR0_D Q[26]
DDR1_DQ[11]/DDR0_D Q[27]
DDR1_DQ[12]/DDR0_D Q[28]
DDR1_DQ[13]/DDR0_D Q[29]
DDR1_DQ[14]/DDR0_D Q[30]
DDR1_DQ[15]/DDR0_D Q[31]
DDR1_DQ[16]/DDR0_D Q[48]
DDR1_DQ[17]/DDR0_D Q[49]
DDR1_DQ[18]/DDR0_D Q[50]
DDR1_DQ[19]/DDR0_D Q[51]
DDR1_DQ[20]/DDR0_D Q[52]
DDR1_DQ[21]/DDR0_D Q[53]
DDR1_DQ[22]/DDR0_D Q[54]
DDR1_DQ[23]/DDR0_D Q[55]
DDR1_DQ[24]/DDR0_D Q[56]
DDR1_DQ[25]/DDR0_D Q[57]
DDR1_DQ[26]/DDR0_D Q[58]
DDR1_DQ[27]/DDR0_D Q[59]
DDR1_DQ[28]/DDR0_D Q[60]
DDR1_DQ[29]/DDR0_D Q[61]
DDR1_DQ[30]/DDR0_D Q[62]
DDR1_DQ[31]/DDR0_D Q[63]
DDR1_DQ[32]/DDR1_D Q[16]
DDR1_DQ[33]/DDR1_D Q[17]
DDR1_DQ[34]/DDR1_D Q[18]
DDR1_DQ[35]/DDR1_D Q[19]
DDR1_DQ[36]/DDR1_D Q[20]
DDR1_DQ[37]/DDR1_D Q[21]
DDR1_DQ[38]/DDR1_D Q[22]
DDR1_DQ[39]/DDR1_D Q[23]
DDR1_DQ[40]/DDR1_D Q[24]
DDR1_DQ[41]/DDR1_D Q[25]
DDR1_DQ[42]/DDR1_D Q[26]
DDR1_DQ[43]/DDR1_D Q[27]
DDR1_DQ[44]/DDR1_D Q[28]
DDR1_DQ[45]/DDR1_D Q[29]
DDR1_DQ[46]/DDR1_D Q[30]
DDR1_DQ[47]/DDR1_D Q[31]
DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]
DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]
DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]
DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]
947859
NIL Channel A[16..31]
NIL Channel A[48..63]
NIL Channel B[16..31]
NIL Channel B[48..63]
IL Channel B DQS[0..7]
NIL Channel A
DQS[2,3,6,7]
NIL Channel B
DQS[2,3,6,7]
M_B_DQS#[7:0] 17
M_B_DQS[7:0] 17
SKL_ULT
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT #
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR 1_MA[15]
DDR1_WE#/DDR1 _CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR 1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_D QSN[2]
DDR1_DQSN[1]/DDR0_D QSN[3]
DDR1_DQSN[2]/DDR0_D QSN[6]
DDR1_DQSN[3]/DDR0_D QSN[7]
DDR1_DQSN[4]/DDR1_D QSN[2]
DDR1_DQSN[5]/DDR1_D QSN[3]
DDR CH - B
+12V
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
+1.2V 7,16,17,18,57,83
+3VS 3,20,21,22,23,24,30,31,32,36,41,44,45,48,49 ,50,51,53,56,57,62,64,74,87,91,92
+3VSUS 20,21,22,23,24,25,26 ,28,30,31,41,51,53,62,74,81,92
+12V 57,91
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
M_B_DIM0_ODT0
M_A_DQS#2
M_A_DQS2
M_A_DQS#3
M_A_DQS3
M_A_DQS#6
M_A_DQS6
M_A_DQS#7
M_A_DQS7
M_B_DQS#2
M_B_DQS2
M_B_DQS#3
M_B_DQS3
M_B_DQS#6
M_B_DQS6
M_B_DQS#7
M_B_DQS7
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9
M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9
RVP LPDDR3 floating. DDR3L GND
PDG short to GND.
1 2
R0402 200Ohm1%
1 2
R0403 80.6Ohm1%
1 2
R0404 162Ohm1%
M_B_DIM0_CLK#0 1 7
M_B_DIM0_CLK#1 1 7
M_B_DIM0_CLK0 17
M_B_DIM0_CLK1 17
M_B_DIM0_CKE0 17
M_B_DIM0_CKE1 17
M_B_DIM0_CKE2 17
M_B_DIM0_CKE3 17
M_B_DIM0_CS#0 17
M_B_DIM0_CS#1 17
M_B_DIM0_ODT0 17
M_B_CAA[9:0] 17
M_B_CAB[9:0] 17
Controls reset to the memory subsystems,
and is used on DDR3L, DDR4
(not applicable to LPDDR3).
DRAM_RESET#
1
T0401
B B
+3VS+1.2V +3VSUS
Symbol U0301 B
Non-interleavedinterleaved(Symbol default)
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
ChannelA DQ[0..63]
DQS/DQS#[0..7]
BYTE 5
BYTE 6
BYTE 7
A A
5
ChannelA DQ[0..15]
DQS/DQS#[0,1]
ChannelADQ[32..47]
DQS/DQS#[4,5]
ChannelB DQ[0..15]
DQS/DQS#[0,1]
ChannelB DQ[32..47]
DQS/DQS#[4,5]
C0401
0.1UF/16V
U0401
1
NC
2
A
3 4
GND
74AUP1G07GW
R0431
100KOhm
@
R0430 330Ohm
For cost down!!
unmount:U0401, C0401
mount: R0430,Q0403,Q0405,R0431
4
12
5
VCC
Y
+12V
12
@
3
C
B
1
@
Q0403
E
PMBS3904
2
3
1 2
32
3
D
Q0405
2N7002
1
1
@
G
S
2
12
R0405
1KOhm
1%
12
R0407
220KOhm
12
@
DDR_VTT_CNTL to VTT
power ready < 35us (tCPU18)
R0411
2MOHM
@
DDR_PG_CTRL 83
2
Symbol U0301 C
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
ChannelB DQ[0..63]
DQS/DQS#[0..7]
BYTE 5
BYTE 6
BYTE 7
Date: Sheet
Date: Sheet of
Date: Sheet of
Non-interleavedinterleaved(Symbol default)
ChannelA DQ[16..31]
DQS/DQS#[2,3]
ChannelADQ[48..63]
DQS/DQS#[6,7]
ChannelB DQ[16..31]
DQS/DQS#[2,3]
ChannelB DQ[48..63]
DQS/DQS#[6,7]
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1/HW7
BG1/HW7
BG1/HW7
Size Project Name
Size Project Name
Size Project Name
C
C
C
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
CPU(2)_LPDDR3
CPU(2)_LPDDR3
CPU(2)_LPDDR3
Kai_Shen
Kai_Shen
Kai_Shen
4 94Friday, April 07, 2017
4 94Friday, April 07, 2017
4 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
of
5
4
3
2
1
05
D D
C C
+VCORE
12
12
12
C0518
1UF/6.3V
@
C0532
1UF/6.3V
@
C0539
1UF/6.3V
@
12
C0519
1UF/6.3V
@
12
C0533
1UF/6.3V
@
12
C0540
1UF/6.3V
@
12
C0545
47UF/6.3V
@
12
C0520
1UF/6.3V
@
12
C0534
1UF/6.3V
@
12
C0546
47UF/6.3V
@
12
12
12
C0509
1UF/6.3V
@
C0516
1UF/6.3V
@
C0537
1UF/6.3V
@
12
C0510
1UF/6.3V
@
12
C0517
1UF/6.3V
@
12
C0531
1UF/6.3V
@
12
C0538
1UF/6.3V
@
12
C0548
47UF/6.3V
@
12
C0514
1UF/6.3V
@
12
C0535
1UF/6.3V
@
12
C0542
1UF/6.3V
@
12
C0549
47UF/6.3V
@
12
12
12
C0515
1UF/6.3V
@
C0536
1UF/6.3V
@
C0543
1UF/6.3V
@
+VCORE +VCORE
CPU(3)_+VCCCORE
A30
A34
A39
A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
0101-03860PB
U0301L
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
RSVD_3
RSVD_4
VCCOPC_1
VCCOPC_2
VCCOPC_3
VCC_OPC_1P8_1
VCC_OPC_1P8_2
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO_1
VCCEOPIO_2
VCCEOPIO_SENSE
VSSEOPIO_SENSE
947859
CPU POWER 1 OF 4
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
Pull H/L near CPU side
1 2
R0536 100Ohm1%
1 2
R0537 100Ohm1%
VIDALERT#
VIDSCK
VIDSOUT
+VCCIO
+1.0V
+VCORE
+VCCIO
+VCORE
VCORE_VCCSENSE 80
VCORE_VSSSENSE 80
1 2
R0517 220Ohm1%
1 2
R0518 0Ohm
1 2
R0519 0Ohm
+1.0V 3,7,9,25,32,57,91
+VCORE 6,80
+VCCIO 3,7,9,57,91
CPU side VR side
+1.0V
12
R0520
56Ohm
1%
VIDALERT#_R
VIDSCK_R
+1.0V
12
R0521
100Ohm
1%
VIDSOUT_R
+1.0V
+1.0V
2016.03.18
R0524,R0522,R0525,R0523,R0526 and C0505 close to U8000
1 2
R0524 0Ohm
R0522
45.3Ohm
1%
R0523
100Ohm
1%
12
C0505
0.1UF/16V
R0525 51Ohm1%
R0526 10Ohm1%
1 2
1 2
12
12
VR_SVID_ALERT# 80
VR_SVID_CLK 80
VR_SVID_DATA 80
B B
A A
CPU(3)_+VCCCORE
CPU(3)_+VCCCORE
CPU(3)_+VCCCORE
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
Kai_Shen
Kai_Shen
Kai_Shen
of
5 94Friday, April 07, 2017
5 94Friday, April 07, 2017
5 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
+VCORE
VccGTx_1
VccGTx_2
VccGTx_3
VccGTx_4
VccGTx_5
VccGTx_6
VccGTx_7
VccGTx_8
VccGTx_9
+VCCGT
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCCGT
06
D D
C C
CPU(4)_+VCCGT
+VCORE_U42_+VCCGT_ U22+VCORE
1 2
R0601 0ohm/U42
+VCORE_U42_+VCCGT_ U22
12
12
C0630
1UF/6.3V
/U42
C0633
1UF/6.3V
/U42
VCCGT_VCCSENSE80
VCCGT_VSSSENSE80
12
12
C0631
1UF/6.3V
/U42
C0634
1UF/6.3V
/U42
12
12
C0632
1UF/6.3V
/U42
C0635
1UF/6.3V
/U42
+VCCGT
VCCGT_VCCSENSE
VCCGT_VSSSENSE
1 2
R0602 0ohm/U22
R0609
100Ohm
1%
1 2
Pull H/L near CPU side
12
R0610
100Ohm
1%
Pull H/L near CPU side
+VCCGT
R0607 0Ohm@
1 2
A48
A53
A58
A62
A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
J70
J69
U0301M
CPU POWER 2 OF 4
VCCGT_1
VCCGT_2
VCCGT_3
VCCGT_4
VCCGT_5
VCCGT_6
VCCGT_7
VCCGT_8
VCCGT_9
VCCGT_10
VCCGT_11
VCCGT_12
VCCGT_13
VCCGT_14
VCCGT_15
VCCGT_16
VCCGT_17
VCCGT_18
VCCGT_19
VCCGT_20
VCCGT_21
VCCGT_22
VCCGT_23
VCCGT_24
VCCGT_25
VCCGT_26
VCCGT_27
VCCGT_28
VCCGT_29
VCCGT_30
VCCGT_31
VCCGT_32
VCCGT_33
VCCGT_34
VCCGT_35
VCCGT_36
VCCGT_37
VCCGT_38
VCCGT_39
VCCGT_40
VCCGT_41
VCCGT_42
VCCGT_43
VCCGT_44
VCCGT_45
VCCGT_46
VCCGT_47
VCCGT_48
VCCGT_49
VCCGT_50
VCCGT_51
VCCGT_52
VCCGT_53
VCCGT_54
VCCGT_55
VCCGT_SENSE
VSSGT_SENSE
947859
0101-03860PB
VCCGT_56
VCCGT_57
VCCGT_58
VCCGT_59
VCCGT_60
VCCGT_61
VCCGT_62
VCCGT_63
VCCGT_64
VCCGT_65
VCCGT_66
VCCGT_67
VCCGT_68
VCCGT_69
VCCGT_70
VCCGT_71
VCCGT_72
VCCGT_73
VCCGT_74
VCCGT_75
VCCGT_76
VCCGT_77
VCCGT_78
VCCGT_79
VCCGT_80
VccGTx_10
VccGTx_11
VccGTx_12
VccGTx_13
VccGTx_14
VccGTx_15
VccGTx_16
VccGTx_17
VccGTx_18
VccGTx_19
VccGTx_20
VccGTx_21
VccGTx_22
VccGTx_23
VccGTx_24
VccGTx_25
VccGTx_26
VccGTx_27
VccGTx_28
VccGTx_29
VCCGTx_SENSE
VSSGTx_SENSE
+VCORE 5,80
+VCCGT 80
U42U42 U22
+VCORE_U42_+VCCGTx_U23
R0603 0ohm/U42
1 2
+VCORE
+VCCGT
12
C0602
10UF/6.3V
12
C0628
47UF/6.3V
12
12
@
@
C0616
1UF/6.3V
@
C0623
1UF/6.3V
@
12
C0603
10UF/6.3V
12
12
12
@
C0629
47UF/6.3V
@
C0618
1UF/6.3V
@
C0625
1UF/6.3V
@
12
C0605
10UF/6.3V
12
C0610
10UF/6.3V
12
12
@
@
C0617
1UF/6.3V
@
C0624
1UF/6.3V
@
12
C0604
10UF/6.3V
12
C0609
10UF/6.3V
12
12
@
@
C0614
1UF/6.3V
@
C0621
1UF/6.3V
@
12
C0606
10UF/6.3V
12
C0611
10UF/6.3V
12
12
@
@
C0615
1UF/6.3V
@
C0622
1UF/6.3V
@
12
C0607
10UF/6.3V
12
C0612
10UF/6.3V
12
12
@
@
C0619
1UF/6.3V
@
C0626
1UF/6.3V
@
12
C0608
10UF/6.3V
12
C0613
10UF/6.3V
@
@
12
12
C0620
1UF/6.3V
@
C0627
1UF/6.3V
@
B B
A A
CPU(4)_+VCCGT
CPU(4)_+VCCGT
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
CPU(4)_+VCCGT
Kai_Shen
Kai_Shen
Kai_Shen
6 94Friday, April 07, 2017
6 94Friday, April 07, 2017
6 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
of
5
4
3
2
1
07
D D
12
C0734
10UF/6.3V
@
12
C0738
10UF/6.3V
@
+VDDQ_CPU
12
C0701
10UF/6.3V
12
12
C0733
10UF/6.3V
@
C0739
10UF/6.3V
@
12
C0702
10UF/6.3V
12
12
C0735
10UF/6.3V
@
C0740
10UF/6.3V
@
12
C0703
10UF/6.3V
12
12
C0736
10UF/6.3V
@
C0741
10UF/6.3V
@
12
C0704
10UF/6.3V
12
12
12
+VDDQ_CPU
SP0701 0Ohm
@/SP
C0737
10UF/6.3V
@
C0742
10UF/6.3V
@
C0705
10UF/6.3V
1 2
12
C0706
10UF/6.3V
+VCCST_CPU
12
C0712
1UF/6.3V
+VCCSTG
12
C0713
1UF/6.3V
+VCCSFR_OC
12
C0714
1UF/6.3V
+VCCSFR
12
+VDDQ_CPU_CLK
C0715
0.1UF/16V
+1.2V
JP0701
@/SP
2
112
3MM_OPEN_5MIL
JP0702
@/SP
2
112
3MM_OPEN_5MIL
+VCCSA
12
C C
B B
C0731
10UF/6.3V
@
12
C0743
47UF/6.3V
@
12
C0732
10UF/6.3V
@
12
C0744
47UF/6.3V
@
CPU(5)_+VDDQ/IO/SA
C0701 - C0704 : Near by package
C0705 - C0710 : Underneath the package
12
C0707
1UF/6.3V
12
C0708
1UF/6.3V
12
C0709
1UF/6.3V
Decoupling cap for internal power
12
C0711
10UF/6.3V
1AV200000074
vx_c0402_h28_small
12
C0716
0.1UF/16V
12
2.8A
C0710
1UF/6.3V
0.1A
+1.0V
+1.0V +VCCSFR
U0301N
AU23
VDDQ_1
AU28
VDDQ_2
AU35
VDDQ_3
AU42
VDDQ_4
BB23
VDDQ_5
BB32
VDDQ_6
BB41
VDDQ_7
BB47
VDDQ_8
BB51
VDDQ_9
AM40
VDDQC
A18
VCCST
A22
VCCSTG
AL23
VCCPLL_OC
K20
VccPLL_1
K21
VccPLL_2
947859
0101-03860PB
1 2
R0710 0Ohm
RES 0 OHM 1/10W (0603) JUMP
1 2
R0711 0Ohm
RES 0 OHM 1/10W (0603) JUMP
CPU POWER 3 OF 4
0.24A0.24A
0.24A0.24A
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
+VCCST_CPU
+VCCSFR_OC+1.2V
VCCIO_1
VCCIO_2
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCSA_1
VCCSA_2
VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6
VCCSA_7
VCCSA_8
VCCSA_9
VCCSA_10
VCCSA_11
VCCSA_12
VCCSA_13
VCCSA_14
+1.0V
+1.2V
+VCCIO
+VCCSA
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
VCCIO_VR_FB
VSSIO_VR_FB
+1.0V 3,5,9,25,32,57,91
+1.2V 4,16,17,18,57,83
+VCCIO 3,5,9,57,91
+VCCSA 8 0
4.5A
VCCSA_VSSSENSE 80
VCCSA_VCCSENSE 80
12
C0717
1UF/6.3V
VCCSA_VCCSENSE
VCCSA_VSSSENSE
12
C0718
1UF/6.3V
12
C0719
1UF/6.3V
+VCCIO
12
+VCCSA
C0720
1UF/6.3V
R0720
100Ohm
1%
1 2
R0721
100Ohm
1%
1 2
+VCCSA
+VCCIO
12
R0714
1KOhm
@
Reserved PH/PD
12
R0715
1KOhm
@
Refer to CRB 0.53
1 2
R0709 0Ohm
RES 0 OHM 1/10W (0603) JUMP
+VCCIO
R0713 0Ohm
RES 0 OHM 1/10W (0603) JUMP
1 2
+VCCSTG
0.12A0.12A
A A
CPU(5)_+VDDQ/IO/SA
CPU(5)_+VDDQ/IO/SA
CPU(5)_+VDDQ/IO/SA
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW3 RD
BG1-HW3 RD
BG1-HW3 RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
Kai_Shen
Kai_Shen
Kai_Shen
of
7 94Friday, April 07, 2017
7 94Friday, April 07, 2017
7 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
08
A67
A70
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL2
AL28
AL32
AL35
AL38
AL4
AL45
AL48
AL52
AL55
AL58
AL64
A5
U0301P
GND 1 OF 3
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
947859
0101-03860PB
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
D D
C C
B B
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
U0301Q
GND 2 OF 3
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
947859
0101-03860PB
CPU(6)_CPU GND
BA49
VSS_209
BA53
VSS_210
BA57
VSS_211
BA6
VSS_212
BA62
VSS_213
BA66
VSS_214
BA71
VSS_215
BB18
VSS_216
BB26
VSS_217
BB30
VSS_218
BB34
VSS_219
BB38
VSS_220
BB43
VSS_221
BB55
VSS_222
BB6
VSS_223
BB60
VSS_224
BB64
VSS_225
BB67
VSS_226
BB70
VSS_227
C1
VSS_228
C25
VSS_229
C5
VSS_230
D10
VSS_231
D11
VSS_232
D14
VSS_233
D18
VSS_234
D22
VSS_235
D25
VSS_236
D26
VSS_237
D30
VSS_238
D34
VSS_239
D39
VSS_240
D44
VSS_241
D45
VSS_242
D47
VSS_243
D48
VSS_244
D53
VSS_245
D58
VSS_246
D6
VSS_247
D62
VSS_248
D66
VSS_249
D69
VSS_250
E11
VSS_251
E15
VSS_252
E18
VSS_253
E21
VSS_254
E46
VSS_255
E50
VSS_256
E53
VSS_257
E56
VSS_258
E6
VSS_259
E65
VSS_260
E71
VSS_261
F1
VSS_262
F13
VSS_263
F2
VSS_264
F22
VSS_265
F23
VSS_266
F27
VSS_267
F28
VSS_268
F32
VSS_269
F33
VSS_270
F35
VSS_271
F37
VSS_272
F38
VSS_273
F4
VSS_274
F40
VSS_275
F42
VSS_276
BA41
VSS_277
G10
G22
G43
G45
G48
G52
G55
G58
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
F8
G5
G6
J8
U0301R
GND 3 OF 3
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
947859
0101-03860PB
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
A A
CPU(6)_CPU GND
CPU(6)_CPU GND
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
CPU(6)_CPU GND
Kai_Shen
Kai_Shen
Kai_Shen
8 94Wednesday, March 29, 2017
8 94Wednesday, March 29, 2017
8 94Wednesday, March 29, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
CPU(7)_CFG/RSVD
09
4
3
2
1
+1.0V
+1.8VSUS
U0301S
RESERVED SIGNALS-1
RSVD_21
RSVD_22
TP5
TP6
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
RSVD_28
RSVD_29
RSVD_30
RSVD_31
RSVD_32
RSVD_33
RSVD_34
RSVD_35
TP4
RSVD_36
RSVD_37
RSVD_38
RSVD_39
RSVD_40
RSVD_41
RSVD_42
TP1
TP2
VSS_362
ZVM#
MSM#
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
RSVD_AY3
VSS_AY71
SKL_CNL#
1 2
SP0901 0Ohm
@/SP
1 2
SP0902 0Ohm
@/SP
R0904 100KOhm@
CFG0
1
D D
C C
T0923
1
T0924
1
T0925
1
T0926
1
T0927
1
T0928
1
T0929
1
T0930
1
T0931
1
T0919
1
T0920
1
T0921
1
T0922
1 2
R0901 49.9Ohm1%
Reserve TP for XDP
1
T0917
1
T0918
T0901
CFG2
CFG3
CFG4
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP
ITP_PMODE
1
RSVD_VSS_F65
RSVD_VSS_G65
Remove SNN
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
AY2
AY1
K46
K45
AL25
AL27
C71
B70
F60
A52
BA70
BA68
F65
G65
F61
E61
J71
J68
E8
D1
D3
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_TP_1
RSVD_TP_2
RSVD_17
RSVD_18
VSS_360
VSS_361
RSVD_19
RSVD_20
RSVD_TP_3
RSVD_TP_4
RSVD_TP_5
RSVD_TP_6
RSVD_TP_7
RSVD_TP_8
PROC_SELECT#
+VCCIO
1 2
+1.0V 3,5,7,25,32,57,91
+1.8VSUS 2 4,26,84
+VCCIO 3,5,7,57,91
+1.0V
MOW WW48
1. Ball C64 which is PROC_SELECT# needs to be pulled to VCCST for
Cannonlake support via 100K ohm resistor and with no resistor populated
(floating pin) for Skylake.
947859
0101-03860PB
+VCCIO
AW69
AW68
AU56
AW48
U12
U11
H11
RSVD_43
RSVD_44
RSVD_45
RSVD_46
C7
RSVD_47
RSVD_48
RSVD_49
RSVD_50
0101-03860PB
U0301T
947859
SPARE
RSVD_51
RSVD_52
RSVD_53
RSVD_54
RSVD_55
RSVD_56
RSVD_57
RSVD_58
F6
E3
C11
B11
A11
D12
C12
F52
U42_XTAL24_IN
U42_XTAL24_OUT U42_XTAL24_OUT_ R_R
1 2
R0940 0Ohm
/U42
10V240000001
1 2
R0941 0Ohm
10V240000001
U42_XTAL24_OUT_ R
/U42
U42_XTAL24_IN_R
12
R0932
1MOhm
/U42
10V240000006
SP0910 0Ohm
@/SP
07V080000024
X0901
24MHZ
/U42
1 2
13
2
4
1 2
1 2
C0903
10PF/50V
/U42
1AV200000001
C0904
10PF/50V
/U42
1AV200000001
GND
GND
GND
R0906
1 2
1 2
R0908 10KOhm
B B
1 2
R0910 10KOhm
1 2
R0913 10KOhm
10KOhm
@
1%
@
1%
@
1%
@
1%
CFG0
CFG2
CFG4
CFG7
1 2
R0922 1KOhm@
1 2
R0924 1KOhm@
1 2
R0926 1KOhm
1 2
R0929 1KOhm@
PDG 1.2
Placeholder only. Does not need to be stuffed.
Placement are required for future platform compatibility purpose only.
Name
CFG0
CFG1
CFG2
CFG3
CFG4
+1.8VSUS
R0930 0Ohm@
R0931 0Ohm@
P5HCJ_KBL
1
1
1
1
0
1 2
1 2
VCC_1P8_U12
VCC_1P8_U11
12
C0901
0.1UF/16V
@
12
C0902
0.1UF/16V
@
Description
1 = (Default) Normal Operation; No stall
0 = Stall
Reserved configuration lane
PCI Express* Static x16 Lane Numbering Reversal
1 = Normal operation
0 = Lane numbers reversed
Reserved configuration lane
CFG[4]: eDP* enable:
1 = Disabled.
0 = Enabled
A A
CFG5
CFG6
1
The CFG signals have a default value of '1' if not terminated on the board.
*All processor lines.
CFG[2], CFG[6:5] and CFG[7] are relevant for H and S-processor line only
and test point may be placed on the board for them
CFG7
CFG[19:8] Reserved configuration lane
1
1
From EDS_Intel_CPU(Kabylake.UY)_Vol1_559100_Rev0p91 Page.123
5
4
CFG[6:5]: PCI Express* Bifurcation
00 = 1 x8, 2 x4 PCI Express*
01 = reserved
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
1 = (default) PEG Train immediately following
RESET# de assertion
0 = PEG Wait for BIOS for training.
3
CPU(7)_CFG/RSVD
CPU(7)_CFG/RSVD
CPU(7)_CFG/RSVD
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
Kai_Shen
Kai_Shen
Kai_Shen
of
9 94Wednesday, March 29, 2017
9 94Wednesday, March 29, 2017
9 94Wednesday, March 29, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
D D
4
3
2
1
C C
B B
Title :
Title :
A A
5
4
3
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
HE4EA
HE4EA
A
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
HE4EA
Title :
Engineer:
Engineer:
Engineer:
Block Diagram
Block Diagram
Block Diagram
Kai_Shen
Kai_Shen
Kai_Shen
10 94Wednesday, March 29, 2017
10 94Wednesday, March 29, 2017
10 94Wednesday, March 29, 2017
1
Rev
Rev
Rev
1.0
1.0
1.0
5
D D
4
3
2
1
C C
B B
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
HE4EA 1.0
HE4EA 1.0
HE4EA 1.0
11 94Wednesday, March 29, 2017
11 94Wednesday, March 29, 2017
11 94Wednesday, March 29, 2017
2
1
5
D D
4
3
2
1
C C
B B
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
HE4EA 1.0
HE4EA 1.0
HE4EA 1.0
12 94Wednesday, March 29, 2017
12 94Wednesday, March 29, 2017
12 94Wednesday, March 29, 2017
2
1
5
D D
4
3
2
1
C C
B B
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
HE4EA 1.0
HE4EA 1.0
HE4EA 1.0
13 94Wednesday, March 29, 2017
13 94Wednesday, March 29, 2017
13 94Wednesday, March 29, 2017
2
1
5
D D
4
3
2
1
C C
B B
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
HE4EA 1.0
HE4EA 1.0
HE4EA 1.0
14 94Wednesday, March 29, 2017
14 94Wednesday, March 29, 2017
14 94Wednesday, March 29, 2017
2
1
5
D D
4
3
2
1
C C
B B
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
HE4EA 1.0
HE4EA 1.0
HE4EA 1.0
15 94Wednesday, March 29, 2017
15 94Wednesday, March 29, 2017
15 94Wednesday, March 29, 2017
2
1
5
4
3
2
1
LPDDR3 Channel A
M_A_CAA[9:0]4
M_A_DIM0_CLK04
D D
M_A_DIM0_CLK#04
M_A_DIM0_CKE04
M_A_DIM0_CKE14
M_A_DIM0_CS#04
M_A_DIM0_CS#14
B1
B0
B3
B2
M_A_DQS14
M_A_DQS#14
M_A_DQS04
M_A_DQS#04
M_A_DQS34
M_A_DQS#34
M_A_DQS24
M_A_DQS#24
M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9
LPDDR3 SOURCE
C C
0315-01M9000
0315-01MT000
0315-01E10DE
0315-01DP0DE
LPDDR3 8Gb
LPDDR3 16Gb
LPDDR3 8Gb
LPDDR3 16Gb
0315-01GR000 LPDDR3 8Gb SKHYNIX H9CCNNN8JTBLAR-NUD11.0x11.5x1.00mm
+1.2V
Samsung
Samsung
SKHYNIX
K4E8E324EB-EGCF
K4E6E304EB-EGCF
H9CCNNN8GTMLAR-NUD
SKHYNIX H9CCNNNBJTMLAR-NUD
12
12
C1645
1UF/6.3V
C1661
10UF/6.3V
12
12
C1658
1UF/6.3V
C1662
10UF/6.3V
GND
12
C1659
1UF/6.3V
12
12
C1644
1UF/6.3V
C1660
10UF/6.3V
11.0x11.5x0.90mm
11.0x11.5x0.9mm
11.0x11.5x1.00mm
11.0x11.5x1.00mm
U1601
R2
CA0
P2
CA1
N2
CA2
N3
CA3
M3
CA4
F3
CA5
E3
CA6
E2
CA7
D2
CA8
C2
CA9
J3
CK_t
J2
CK_c
K3
CKE0
K4
CKE1
L3
CS0_n
L4
CS1_n
L8
DM0
G8
DM1
P8
DM2
D8
DM3
A1
NU1
A2
NU4
A12
NU2
A13
NU3
B1
NU5
B13
NU6
T1
NU7
T13
NU8
U1
NU9
U2
NU12
U12
NU10
U13
NU11
L10
DQS0_t
L11
DQS0_c
G10
DQS1_t
G11
DQS1_c
P10
DQS2_t
P11
DQS2_c
D10
DQS3_t
D11
DQS3_c
B2
VSS1
B5
VSS2
C5
VSS3
E4
VSS4
E5
VSS5
F5
VSS6
H2
VSS7
J12
VSS8
K2
VSS9
L6
VSS10
M5
VSS11
N4
VSS12
N5
VSS13
R4
VSS14
R5
VSS15
T2
VSS16
T3
VSS17
T4
VSS18
T5
VSS19
C3
VSSCA1
D3
VSSCA2
F4
VSSCA3
G3
VSSCA4
G4
VSSCA5
J4
VSSCA6
M4
VSSCA7
P3
VSSCA8
B6
VSSQ2
B12
VSSQ1
C6
VSSQ3
D12
VSSQ4
E6
VSSQ5
F6
VSSQ7
F12
VSSQ6
G6
VSSQ8
G9
VSSQ9
H10
VSSQ10
K10
VSSQ11
L9
VSSQ12
M6
VSSQ14
M12
VSSQ13
N6
VSSQ15
P12
VSSQ16
R6
VSSQ17
T6
VSSQ19
T12
VSSQ18
MT52L1G32D 4PG
M_A_D8
P9
DQ0
M_A_D11
N9
DQ1
M_A_D13
N10
DQ2
M_A_D12
N11
DQ3
M_A_D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_1
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_6
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_8
VDD2_9
VDD2_7
VDD2_10
VDD2_11
VDD2_13
VDD2_14
VDD2_12
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDQ1
VDDQ2
VDDQ4
VDDQ3
VDDQ5
VDDQ7
VDDQ8
VDDQ6
VDDQ10
VDDQ9
VDDQ12
VDDQ11
VDDQ13
VDDQ15
VDDQ14
VDDQ16
VDDQ17
VREFCA
VREFDQ
M8
DQ4
M_A_D15
M9
DQ5
M_A_D9
M10
DQ6
M_A_D10
M11
DQ7
M_A_D4
F11
DQ8
M_A_D2
F10
DQ9
M_A_D5
F9
M_A_D6
F8
M_A_D7
E11
M_A_D0
E10
M_A_D3
E9
M_A_D1
D9
M_A_D28
T8
M_A_D25
T9
M_A_D27
T10
M_A_D30
T11
M_A_D24
R8
M_A_D29
R9
M_A_D26
R10
M_A_D31
R11
M_A_D22
C11
M_A_D16
C10
M_A_D17
C9
M_A_D18
C8
M_A_D21
B11
M_A_D20
B10
M_A_D23
B9
M_A_D19
B8
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
H4
J11
J8
ODT
ZQ0_A1
B3
ZQ0
ZQ1_A1
B4
ZQ1
C4
NC1
K9
NC2
R3
NC3
B1
B0
B3
B2
M_A_D[15:8] 4
M_A_D[7:0] 4
M_A_D[31:24] 4
M_A_D[23:16] 4
+1.8V_LPDDR3
M_A_DIM0_ODT0 4
1 2
R1601 243Ohm1%
1 2
R1602 243Ohm1%
+1.2V
B4
B5
B6
B7
+V_VREF_CA_DIMM0
+V_VREF_DQ_DIMM0
GND GND
M_A_CAB[9:0]4
M_A_DIM0_CLK14
M_A_DIM0_CLK#14
M_A_DIM0_CKE24
M_A_DIM0_CKE34
M_A_DQS44
M_A_DQS#44
M_A_DQS54
M_A_DQS#54
M_A_DQS64
M_A_DQS#64
M_A_DQS74
M_A_DQS#74
M_A_DIM0_CS#0
M_A_DIM0_CS#1
M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9
U1602
R2
CA0
P2
CA1
N2
CA2
N3
CA3
M3
CA4
F3
CA5
E3
CA6
E2
CA7
D2
CA8
C2
CA9
J3
CK_t
J2
CK_c
K3
CKE0
K4
CKE1
L3
CS0_n
L4
CS1_n
L8
DM0
G8
DM1
P8
DM2
D8
DM3
A1
NU1
A2
NU4
A12
NU2
A13
NU3
B1
NU5
B13
NU6
T1
NU7
T13
NU8
U1
NU9
U2
NU12
U12
NU10
U13
NU11
L10
DQS0_t
L11
DQS0_c
G10
DQS1_t
G11
DQS1_c
P10
DQS2_t
P11
DQS2_c
D10
DQS3_t
D11
DQS3_c
B2
VSS1
B5
VSS2
C5
VSS3
E4
VSS4
E5
VSS5
F5
VSS6
H2
VSS7
J12
VSS8
K2
VSS9
L6
VSS10
M5
VSS11
N4
VSS12
N5
VSS13
R4
VSS14
R5
VSS15
T2
VSS16
T3
VSS17
T4
VSS18
T5
VSS19
C3
VSSCA1
D3
VSSCA2
F4
VSSCA3
G3
VSSCA4
G4
VSSCA5
J4
VSSCA6
M4
VSSCA7
P3
VSSCA8
B6
VSSQ2
B12
VSSQ1
C6
VSSQ3
D12
VSSQ4
E6
VSSQ5
F6
VSSQ7
F12
VSSQ6
G6
VSSQ8
G9
VSSQ9
H10
VSSQ10
K10
VSSQ11
L9
VSSQ12
M6
VSSQ14
M12
VSSQ13
N6
VSSQ15
P12
VSSQ16
R6
VSSQ17
T6
VSSQ19
T12
VSSQ18
MT52L1G32D 4PG
1 2
R1603 243Ohm1%
1 2
R1604 243Ohm1%
M_A_D[39:32] 4
M_A_D[47:40] 4
M_A_D[55:48] 4
M_A_D[63:56] 4
+1.8V_LPDDR3
+1.2V
+V_VREF_CA_DIMM0
+V_VREF_DQ_DIMM0
M_A_D32
P9
DQ0
M_A_D36
N9
DQ1
M_A_D35
N10
DQ2
M_A_D38
N11
DQ3
M_A_D33
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_1
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_6
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_8
VDD2_9
VDD2_7
VDD2_10
VDD2_11
VDD2_13
VDD2_14
VDD2_12
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDQ1
VDDQ2
VDDQ4
VDDQ3
VDDQ5
VDDQ7
VDDQ8
VDDQ6
VDDQ10
VDDQ9
VDDQ12
VDDQ11
VDDQ13
VDDQ15
VDDQ14
VDDQ16
VDDQ17
VREFCA
VREFDQ
M8
DQ4
M_A_D37
M9
DQ5
M_A_D39
M10
DQ6
M_A_D34
M11
DQ7
M_A_D47
F11
DQ8
M_A_D43
F10
DQ9
M_A_D46
F9
M_A_D42
F8
M_A_D41
E11
M_A_D40
E10
M_A_D44
E9
M_A_D45
D9
M_A_D53
T8
M_A_D50
T9
M_A_D48
T10
M_A_D54
T11
M_A_D51
R8
M_A_D52
R9
M_A_D49
R10
M_A_D55
R11
M_A_D63
C11
M_A_D56
C10
M_A_D61
C9
M_A_D58
C8
M_A_D62
B11
M_A_D57
B10
M_A_D60
B9
M_A_D59
B8
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
H4
J11
M_A_DIM0_ODT0
J8
ODT
ZQ0_A2
B3
ZQ0
ZQ1_A2
B4
ZQ1
C4
NC1
K9
NC2
R3
NC3
B4
B5
B6
B7
C1602
0.047UF/16V
12
C1613
10UF/6.3V
GND
12
C1626
1UF/6.3V
12
GND
12
C1634
1UF/6.3V
12
C1603
0.047UF/16V
C1627
1UF/6.3V
12
12
C1635
1UF/6.3V
12
C1628
1UF/6.3V
C1604
0.047UF/16V
12
C1636
0.1UF/16V
+1.8V_LPDDR3
12
C1629
1UF/6.3V
12
12
C1608
1UF/6.3V
12
C1630
1UF/6.3V
C1637
0.1UF/16V
4
12
C1605
10UF/6.3V
12
C1609
1UF/6.3V
12
12
C1638
0.1UF/16V
12
C1631
1UF/6.3V
C1606
10UF/6.3V
12
C1610
1UF/6.3V
12
GND
12
GND
12
C1607
10UF/6.3V
GND
C1618
1UF/6.3V
C1639
0.1UF/16V
GND
12
C1611
1UF/6.3V
+1.2V
+0.6VS
+0.6VS
12
12
12
C1623
1UF/6.3V
C1640
1UF/6.3V
C1652
22UF/6.3V
12
12
12
C1614
10UF/6.3V
C1641
1UF/6.3V
C1653
22UF/6.3V
@
12
GND
12
12
C1615
10UF/6.3V
C1642
1UF/6.3V
C1654
22UF/6.3V
+1.2V
12
12
12
C1621
1UF/6.3V
C1643
1UF/6.3V
C1655
22UF/6.3V
@
12
GND
12
12
C1622
1UF/6.3V
C1646
1UF/6.3V
C1656
22UF/6.3V
@
3
12
12
GND
C1647
1UF/6.3V
C1657
22UF/6.3V
@
12
C1648
1UF/6.3V
12
C1649
1UF/6.3V
12
C1650
22UF/6.3V
@
GND
12
C1651
22UF/6.3V
@
M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9
M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9
M_A_DIM0_ODT0
M_A_DIM0_CS#0
M_A_DIM0_CS#1
M_A_DIM0_CKE0
M_A_DIM0_CKE1
M_A_DIM0_CKE2
M_A_DIM0_CKE3
M_A_DIM0_CLK0
M_A_DIM0_CLK#0
M_A_DIM0_CLK1
M_A_DIM0_CLK#1
1 2
R1605 68Ohm1%
1 2
R1606 68Ohm1%
1 2
R1607 68Ohm1%
1 2
R1608 68Ohm1%
1 2
R1609 68Ohm1%
1 2
R1610 68Ohm1%
1 2
R1611 68Ohm1%
1 2
R1612 68Ohm1%
1 2
R1613 68Ohm1%
1 2
R1614 68Ohm1%
1 2
R1615 68Ohm1%
1 2
R1616 68Ohm1%
1 2
R1617 68Ohm1%
1 2
R1618 68Ohm1%
1 2
R1619 68Ohm1%
1 2
R1620 68Ohm1%
1 2
R1621 68Ohm1%
1 2
R1622 68Ohm1%
1 2
R1623 68Ohm1%
1 2
R1624 68Ohm1%
1 2
R1629 80.6Ohm 1%
1 2
R1628 80.6Ohm 1%
1 2
R1627 80.6Ohm 1%
1 2
R1625 80.6Ohm 1%
1 2
R1626 80.6Ohm 1%
1 2
R1635 80.6Ohm 1%
1 2
R1634 80.6Ohm 1%
10V22000010 0
1 2
R1630 37.4Ohm 1%
1 2
R1631 37.4Ohm 1%
1 2
R1632 37.4Ohm 1%
1 2
R1633 37.4Ohm 1%
2
+0.6VS
LPDDR3 1600 32Gb
MICRON/EDFB232A1MA-GD-F-D
12.5mm x 11.5mm
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1/HW7
BG1/HW7
BG1/HW7
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sh eet of
Date: Sh eet of
Date: Sh eet of
1
Engineer:
Engineer:
Engineer:
HE4EA
HE4EA
HE4EA
DDR3L(1)_SO-DIMM0
DDR3L(1)_SO-DIMM0
DDR3L(1)_SO-DIMM0
Title :
Title :
Title :
Kai_Shen
Kai_Shen
Kai_Shen
Rev
Rev
Rev
1.0
1.0
16 94Friday, April 07, 2017
16 94Friday, April 07, 2017
16 94Friday, April 07, 2017
1.0
B B
+1.2V
12
12
C1624
1UF/6.3V
2
+0.6VS
+1.2V
+1.8V
+1.8V_LPDDR3
A A
+V_VREF_CA_DIMM0
+V_VREF_DQ_DIMM0
C1616
10UF/6.3V
JP1601
1MM_OPEN_M1 M2
112
12
GND
+1.2V +V_VREF_CA_DIMM0 +V_VREF_DQ_DIMM0
C1617
10UF/6.3V
12
C1619
1UF/6.3V
+1.8V_LPDDR3+1.8V
+0.6VS 17,57,83
+1.2V 4,7,17,18,57,83
+1.8V 57,91
+1.8V_LPDDR3 17
+V_VREF_CA_DIMM0 18
+V_VREF_DQ_DIMM0 18
5
GND
12
C1620
1UF/6.3V
12
C1601
0.047UF/16V
GND GND GND GND
+1.2V
12
C1612
10UF/6.3V
12
C1625
1UF/6.3V
12
12
C1632
1UF/6.3V
12
C1633
1UF/6.3V
5
4
3
2
1
LPDDR3 Channel B
U1701
M_B_CAA[9:0]4 M_B_D[7:0] 4
M_B_DIM0_CLK04
D D
C C
+1.2V
12
12
12
12
C1744
1UF/6.3V
/CHB
C1760
10UF/6.3V
/CHB
12
C1745
1UF/6.3V
/CHB
C1761
10UF/6.3V
/CHB
12
C1758
1UF/6.3V
/CHB
C1762
10UF/6.3V
/CHB
GND
12
C1759
1UF/6.3V
/CHB
M_B_DIM0_CLK# 04
M_B_DIM0_CKE04
M_B_DIM0_CKE14
M_B_DIM0_CS#04
M_B_DIM0_CS#14
B0
B1
B2
B3
M_B_DQS04
M_B_DQS#04
M_B_DQS14
M_B_DQS#14
M_B_DQS24
M_B_DQS#24
M_B_DQS34
M_B_DQS#34
M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9
R2
CA0
P2
CA1
N2
CA2
N3
CA3
M3
CA4
F3
CA5
E3
CA6
E2
CA7
D2
CA8
C2
CA9
J3
CK_t
J2
CK_c
K3
CKE0
K4
CKE1
L3
CS0_n
L4
CS1_n
L8
DM0
G8
DM1
P8
DM2
D8
DM3
A1
NU1
A2
NU4
A12
NU2
A13
NU3
B1
NU5
B13
NU6
T1
NU7
T13
NU8
U1
NU9
U2
NU12
U12
NU10
U13
NU11
L10
DQS0_t
L11
DQS0_c
G10
DQS1_t
G11
DQS1_c
P10
DQS2_t
P11
DQS2_c
D10
DQS3_t
D11
DQS3_c
B2
VSS1
B5
VSS2
C5
VSS3
E4
VSS4
E5
VSS5
F5
VSS6
H2
VSS7
J12
VSS8
K2
VSS9
L6
VSS10
M5
VSS11
N4
VSS12
N5
VSS13
R4
VSS14
R5
VSS15
T2
VSS16
T3
VSS17
T4
VSS18
T5
VSS19
C3
VSSCA1
D3
VSSCA2
F4
VSSCA3
G3
VSSCA4
G4
VSSCA5
J4
VSSCA6
M4
VSSCA7
P3
VSSCA8
B6
VSSQ2
B12
VSSQ1
C6
VSSQ3
D12
VSSQ4
E6
VSSQ5
F6
VSSQ7
F12
VSSQ6
G6
VSSQ8
G9
VSSQ9
H10
VSSQ10
K10
VSSQ11
L9
VSSQ12
M6
VSSQ14
M12
VSSQ13
N6
VSSQ15
P12
VSSQ16
R6
VSSQ17
T6
VSSQ19
T12
VSSQ18
MT52L1G32D 4PG
/CHB
M_B_D4
P9
DQ0
M_B_D5
N9
DQ1
M_B_D6
N10
DQ2
M_B_D7
N11
DQ3
M_B_D0
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_1
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_6
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_8
VDD2_9
VDD2_7
VDD2_10
VDD2_11
VDD2_13
VDD2_14
VDD2_12
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDQ1
VDDQ2
VDDQ4
VDDQ3
VDDQ5
VDDQ7
VDDQ8
VDDQ6
VDDQ10
VDDQ9
VDDQ12
VDDQ11
VDDQ13
VDDQ15
VDDQ14
VDDQ16
VDDQ17
VREFCA
VREFDQ
M8
DQ4
M_B_D1
M9
DQ5
M_B_D2
M10
DQ6
M_B_D3
M11
DQ7
M_B_D12
F11
DQ8
M_B_D9
F10
DQ9
M_B_D13
F9
M_B_D8
F8
M_B_D11
E11
M_B_D15
E10
M_B_D10
E9
M_B_D14
D9
M_B_D20
T8
M_B_D17
T9
M_B_D23
T10
M_B_D19
T11
M_B_D21
R8
M_B_D16
R9
M_B_D18
R10
M_B_D22
R11
M_B_D26
C11
M_B_D29
C10
M_B_D28
C9
M_B_D25
C8
M_B_D27
B11
M_B_D30
B10
M_B_D31
B9
M_B_D24
B8
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
H4
J11
J8
ODT
ZQ0_B1
B3
ZQ0
ZQ1_B1
B4
ZQ1
C4
NC1
K9
NC2
R3
NC3
M_B_D[15:8] 4
M_B_D[23:16] 4
M_B_D[31:24] 4
+1.8V_LPDDR3
+1.2V
+V_VREF_CA_DIMM1
M_B_DIM0_ODT0 4
1 2
R1701 243Ohm1% /CHB
1 2
R1702 243Ohm1% /CHB
+V_VREF_DQ_DIMM1
GND
B4
B5
B6
B7
B0
B1
B2
B3
M_B_CAB[9:0]4
M_B_DIM0_CLK14
M_B_DIM0_CLK# 14
M_B_DIM0_CKE24
M_B_DIM0_CKE34
M_B_DQS44
M_B_DQS#44
M_B_DQS54
M_B_DQS#54
M_B_DQS64
M_B_DQS#64
M_B_DQS74
M_B_DQS#74
M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9
M_B_DIM0_CS#0
M_B_DIM0_CS#1
U1702
R2
CA0
P2
CA1
N2
CA2
N3
CA3
M3
CA4
F3
CA5
E3
CA6
E2
CA7
D2
CA8
C2
CA9
J3
CK_t
J2
CK_c
K3
CKE0
K4
CKE1
L3
CS0_n
L4
CS1_n
L8
DM0
G8
DM1
P8
DM2
D8
DM3
A1
NU1
A2
NU4
A12
NU2
A13
NU3
B1
NU5
B13
NU6
T1
NU7
T13
NU8
U1
NU9
U2
NU12
U12
NU10
U13
NU11
L10
DQS0_t
L11
DQS0_c
G10
DQS1_t
G11
DQS1_c
P10
DQS2_t
P11
DQS2_c
D10
DQS3_t
D11
DQS3_c
B2
VSS1
B5
VSS2
C5
VSS3
E4
VSS4
E5
VSS5
F5
VSS6
H2
VSS7
J12
VSS8
K2
VSS9
L6
VSS10
M5
VSS11
N4
VSS12
N5
VSS13
R4
VSS14
R5
VSS15
T2
VSS16
T3
VSS17
T4
VSS18
T5
VSS19
C3
VSSCA1
D3
VSSCA2
F4
VSSCA3
G3
VSSCA4
G4
VSSCA5
J4
VSSCA6
M4
VSSCA7
P3
VSSCA8
B6
VSSQ2
B12
VSSQ1
C6
VSSQ3
D12
VSSQ4
E6
VSSQ5
F6
VSSQ7
F12
VSSQ6
G6
VSSQ8
G9
VSSQ9
H10
VSSQ10
K10
VSSQ11
L9
VSSQ12
M6
VSSQ14
M12
VSSQ13
N6
VSSQ15
P12
VSSQ16
R6
VSSQ17
T6
VSSQ19
T12
VSSQ18
MT52L1G32D 4PG
/CHB
M_B_D35
P9
DQ0
M_B_D36
N9
DQ1
M_B_D38
N10
DQ2
M_B_D34
N11
DQ3
M_B_D37
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_1
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_6
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_8
VDD2_9
VDD2_7
VDD2_10
VDD2_11
VDD2_13
VDD2_14
VDD2_12
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDQ1
VDDQ2
VDDQ4
VDDQ3
VDDQ5
VDDQ7
VDDQ8
VDDQ6
VDDQ10
VDDQ9
VDDQ12
VDDQ11
VDDQ13
VDDQ15
VDDQ14
VDDQ16
VDDQ17
VREFCA
VREFDQ
M8
DQ4
M_B_D32
M9
DQ5
M_B_D33
M10
DQ6
M_B_D39
M11
DQ7
M_B_D46
F11
DQ8
M_B_D47
F10
DQ9
M_B_D44
F9
M_B_D45
F8
M_B_D42
E11
M_B_D41
E10
M_B_D40
E9
M_B_D43
D9
M_B_D52
T8
M_B_D48
T9
M_B_D54
T10
M_B_D51
T11
M_B_D53
R8
M_B_D49
R9
M_B_D55
R10
M_B_D50
R11
M_B_D60
C11
M_B_D61
C10
M_B_D59
C9
M_B_D63
C8
M_B_D57
B11
M_B_D56
B10
M_B_D58
B9
M_B_D62
B8
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
H4
J11
M_B_DIM0_ODT0
J8
ODT
ZQ0_B2
B3
ZQ0
ZQ1_B2
B4
ZQ1
C4
NC1
K9
NC2
R3
NC3
B4
B5
B6
B7
M_B_D[39:32] 4
M_B_D[47:40] 4
M_B_D[55:48] 4
M_B_D[63:56] 4
+1.8V_LPDDR3
+1.2V
+V_VREF_CA_DIMM1
+V_VREF_DQ_DIMM1
1 2
R1703 243Ohm1% /CHB
1 2
R1704 243Ohm1% /CHB
GND
B B
GND
LPDDR3 1600 32Gb
MICRON/EDFB232A1MA-GD-F-D
12
C1704
0.047UF/16V
/CHB
12
12
C1736
0.1UF/16V
/CHB
+1.8V_LPDDR3
C1729
1UF/6.3V
/CHB
12
12
C1708
1UF/6.3V
/CHB
12
C1730
1UF/6.3V
/CHB
C1737
0.1UF/16V
/CHB
4
12
C1705
10UF/6.3V
/CHB
12
C1709
1UF/6.3V
/CHB
12
12
C1738
0.1UF/16V
/CHB
12
C1731
1UF/6.3V
/CHB
C1706
10UF/6.3V
/CHB
12
C1710
1UF/6.3V
/CHB
12
GND
12
GND
12
C1707
10UF/6.3V
/CHB
GND
C1718
1UF/6.3V
/CHB
C1739
0.1UF/16V
/CHB
GND
+1.2V
12
12
C1724
1UF/6.3V
/CHB
A A
+0.6VS
+1.2V
+1.8V_LPDDR3
+V_VREF_CA_DIMM1
+V_VREF_DQ_DIMM1
C1716
10UF/6.3V
/CHB
12
GND
+1.2V +V_VREF_CA_DIMM1 +V_VREF_DQ_DIMM1
12
C1717
10UF/6.3V
/CHB
+0.6VS 16,57,83
+1.2V 4,7,16,18,57,83
+1.8V_LPDDR3 16
+V_VREF_CA_DIMM1 18
+V_VREF_DQ_DIMM1 18
C1719
1UF/6.3V
/CHB
5
GND
12
C1720
1UF/6.3V
/CHB
12
C1701
0.047UF/16V
/CHB
GND GND GND GND
+1.2V
12
C1712
10UF/6.3V
/CHB
12
C1725
1UF/6.3V
/CHB
12
12
C1732
1UF/6.3V
/CHB
12
C1702
0.047UF/16V
/CHB
12
GND
12
C1733
1UF/6.3V
/CHB
C1713
10UF/6.3V
/CHB
C1726
1UF/6.3V
/CHB
12
12
C1734
1UF/6.3V
/CHB
12
C1703
0.047UF/16V
/CHB
C1727
1UF/6.3V
/CHB
12
12
C1735
1UF/6.3V
/CHB
C1728
1UF/6.3V
/CHB
12
C1711
1UF/6.3V
/CHB
+1.2V
+0.6VS
+0.6VS
12
12
12
C1723
1UF/6.3V
/CHB
C1740
1UF/6.3V
/CHB
C1752
22UF/6.3V
@
12
12
12
C1714
10UF/6.3V
/CHB
C1741
1UF/6.3V
/CHB
C1753
22UF/6.3V
@
12
GND
12
12
C1715
10UF/6.3V
/CHB
C1742
1UF/6.3V
/CHB
C1754
22UF/6.3V
@
+1.2V
12
12
12
C1721
1UF/6.3V
/CHB
C1743
1UF/6.3V
/CHB
C1755
22UF/6.3V
@
12
GND
12
12
C1722
1UF/6.3V
/CHB
C1746
1UF/6.3V
/CHB
C1756
22UF/6.3V
@
3
12
12
GND
C1747
1UF/6.3V
/CHB
C1757
22UF/6.3V
@
12
C1748
1UF/6.3V
/CHB
12
C1749
1UF/6.3V
/CHB
12
C1750
22UF/6.3V
@
GND
12
C1751
22UF/6.3V
@
M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9
M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9
M_B_DIM0_ODT0
M_B_DIM0_CS#0
M_B_DIM0_CS#1
M_B_DIM0_CKE0
M_B_DIM0_CKE1
M_B_DIM0_CKE2
M_B_DIM0_CKE3
M_B_DIM0_CLK0
M_B_DIM0_CLK# 0
M_B_DIM0_CLK1
M_B_DIM0_CLK# 1
R1705 68Ohm1% /CHB
R1706 68Ohm1% /CHB
R1707 68Ohm1% /CHB
R1708 68Ohm1% /CHB
R1709 68Ohm1% /CHB
R1710 68Ohm1% /CHB
R1711 68Ohm1% /CHB
R1712 68Ohm1% /CHB
R1713 68Ohm1% /CHB
R1714 68Ohm1% /CHB
R1715 68Ohm1% /CHB
R1716 68Ohm1% /CHB
R1717 68Ohm1% /CHB
R1718 68Ohm1% /CHB
R1719 68Ohm1% /CHB
R1720 68Ohm1% /CHB
R1721 68Ohm1% /CHB
R1722 68Ohm1% /CHB
R1723 68Ohm1% /CHB
R1724 68Ohm1% /CHB
R1729 80.6Ohm 1%/CHB
R1728 80.6Ohm 1%/CHB
R1727 80.6Ohm 1%/CHB
R1725 80.6Ohm 1%/CHB
R1726 80.6Ohm 1%/CHB
R1734 80.6Ohm 1%/CHB
R1735 80.6Ohm 1%/CHB
R1730 37.4Ohm 1%/CHB
R1731 37.4Ohm 1%/CHB
R1733 37.4Ohm 1%/CHB
R1732 37.4Ohm 1%/CHB
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+0.6VS
12.5mm x 11.5mm
<Variant Name>
<Variant Name>
<Variant Name>
DDR3(2)_SO-DIMM1
DDR3(2)_SO-DIMM1
DDR3(2)_SO-DIMM1
Title :
Title :
HE4EA
HE4EA
HE4EA
Title :
Engineer:
Engineer:
Engineer:
Kai_Shen
Kai_Shen
Kai_Shen
17 94Friday, April 07, 2017
17 94Friday, April 07, 2017
17 94Friday, April 07, 2017
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1/HW7
BG1/HW7
BG1/HW7
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sh eet of
Date: Sh eet of
Date: Sh eet of
1
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
18
D D
C C
LPDDR3(3)_CA/DQ Voltage
+1.2V
+V_VREF_CA_DIMM0
+V_VREF_DQ_DIMM0
+V_VREF_CA_DIMM1
+V_VREF_DQ_DIMM1
M3: CPU driven VREF path is stuffed be default.
M1: VREF_DQ driven by a Voltage Divider Network during Processor power-off
DIMM0_VREF_DQ4
DIMM1_VREF_DQ4
+1.2V 4,7,16,17,57,83
+V_VREF_CA_DIMM0 16
+V_VREF_DQ_DIMM0 16
+V_VREF_CA_DIMM1 17
+V_VREF_DQ_DIMM1 17
12
C1805
0.022UF/16V
12
R1819
24.9Ohm
1%
12
C1804
0.022UF/16V
12
R1818
24.9Ohm
1%
M3
R1821
1 2
10Ohm
10V220000009
1%
R1822
1 2
10Ohm
10V220000009
1%
C1803
0.1UF/25V
@
1 2
C1802
0.1UF/25V
@
1 2
+1.2V
1 2
1 2
+1.2V
1 2
1 2
R1815
8.2KOhm
1%
R1816
8.2KOhm
1%
R1810
8.2KOhm
1%
R1809
8.2KOhm
1%
+V_VREF_DQ_DIMM0
+V_VREF_DQ_DIMM1
561280_KBL UY PDG Rev1_0
47nF on Page 16&17
M1
B B
+1.2V
1 2
M3
R1823
DIMM_VREF_CA4
12
C1806
0.022UF/16V
12
R1820
24.9Ohm
1%
1 2
5.1OHM
10V220000087
1%
+V_VREF_CA
C1801
0.1UF/25V
@
1 2
R1807
8.2KOhm
1 2
1%
R1808
8.2KOhm
1 2
1%
R1801 0Ohm/0-ohm
1 2
R1802 0Ohm/0-ohm
+V_VREF_CA_DIMM0
+V_VREF_CA_DIMM1
M1
A A
<Variant Name>
<Variant Name>
<Variant Name>
DDR3(3)_CA/DQ Voltage
DDR3(3)_CA/DQ Voltage
DDR3(3)_CA/DQ Voltage
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1/HW7
BG1/HW7
BG1/HW7
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
Kai_Shen
Kai_Shen
Kai_Shen
18 94Friday, April 07, 2017
18 94Friday, April 07, 2017
18 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
D D
4
3
2
1
C C
B B
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
HE4EA 1.0
HE4EA 1.0
HE4EA 1.0
19 94Wednesday, March 29, 2017
19 94Wednesday, March 29, 2017
19 94Wednesday, March 29, 2017
2
1
5
4
3
2
1
20
D D
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
AW13
AY11
M2
M3
J4
V1
V2
M1
G3
G2
G1
U0301E
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
947859
0101-03860PB
RF requirement
SPI_CLK
12
C2003
0.1UF/16V
@
SPI_CLK28
SPI_SO28
SPI_SI28
SPI_WP#_IO228
SPI_HOLD#_IO328
SPI_CS#028
T2011
T2001
1
1
near AV2
1
T2002
1
T2007
CL_CLK53
CL_DATA53
CL_RST#53
RCIN#30
C C
INT_SERIRQ30,44,62
SPI_CLK
SPI_SO
SPI_SI
SPI_WP#_IO2
SPI_HOLD#_IO3
SPI_CS#0
SPI_CS1#
SPI_CS2#
GPP_D1
GPP_D0
CL_CLK
CL_DATA
CL_RST#
RCIN#
INT_SERIRQ
PCH(1)_SPI/LPC
SPI - FLASH
SPI - TOUCH
LPC
C LINK
SMBUS, SMLINK
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
+3VS
+3VSUS
SMB_CLK
SMB_DAT
SMBALERT#
SML0_CLK_NFC
SML0_DAT_NFC
SML0ALERT#
SML1_CLK
SML1_DAT
SML1ALERT#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PM_SUS_STAT#
CLK_KBCPCI_PCH_R
CLK_LPC1
PM_CLKRUN#
+3VS 3 ,4,21,22,23,24,30,31,32,36,41,44,45,48,49,50,51,53,56,57 ,62,64,74,87,91,92
+3VSUS 4,21,22,23,24,25,26,28 ,30,31,41,51,53,62,74,81,92
RF requirement
SML1_CLK
1
T2008
1
T2003
1
T2004
SML1_CLK 28
1
T2010
SML1_DAT 28
LPC_AD0 30,44,62
LPC_AD1 30,44,62
LPC_AD2 30,44,62
LPC_AD3 30,44,62
LPC_FRAME# 30,44,62
PM_SUS_STAT# 62
1 2
R2001 22Ohm 1%
1 2
R2002 22Ohm 1%/Debug
1 2
R2014 22Ohm 1%@/TPM
PM_CLKRUN# 30,62
To EC
TPM
EC
DEBUG
12
C2001
10PF/50V
@
12
C2002
10PF/50V
@
12
C2004
0.1UF/16V
@
near W3
CLK_KBCPCI_PCH 30
CLK_DEBUG 44
LPCCLK_TPM 62
Unmount R2013,R2009
Vendor Suggest Pull High Resistor Need To Close To TPM
PM_CLKRUN#, INT_SERIRQ Need To Pull 10Kohm To+3VS at Chipset Side
+3VS
+3VSUS
1 2
R2004 20KOhm@
B B
1 2
R2006 20KOhm@
SMBALERT#
CRB 0.53 reserve 150k ohm
SML0ALERT#
CRB 0.53 reserve 150k ohm
1 2
R2008 20KOhm@
1 2
R2003 2.2KOhm@
1 2
R2005 4.7KOhm@
1 2
R2007 4.7KOhm@
+3VSUS
+3VSUS
BBS 21
SMBALERT# - Internal weak pull down 20k ohm
TLS Confidentiality
0 : Disable (default)
1 : Enable
SML0ALERT# - Internal weak pull down 20 kohm
0 : LPC EC (default)
1 : eSPI EC
BBS - Internal weak pull down 20k ohm
Boot BIOS Strap
0 : SPI destination (default)
1 : LPC destination
PM_CLKRUN#
INT_SERIRQ
SMB_CLK
SMB_DAT
SML1_DAT
SML1_CLK
SML1ALERT#
RN2001A
RN2001B
RN2002B
RN2002A
MOW WW52
To enable Direct Connect Interface (DCI),
a 150K pull up resistor will need to be added to PCHHOT#
pin. This pin must be low during the rising edge of RSMRST#.
1 2
R2013 10KOhm
1 2
R2009 10KOhm
1 2
3 4
3 4
1 2
1 2
R2012 150KOhm
2.2KOhm
2.2KOhm
2.2KOhm
2.2KOhm
@
@
+3VSUS
A A
PCH(1)_SPI/LPC
PCH(1)_SPI/LPC
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
PCH(1)_SPI/LPC
Kai_Shen
Kai_Shen
Kai_Shen
of
20 94Friday, April 07, 2017
20 94Friday, April 07, 2017
20 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
Microsoft* Windows* 7 System WHCK Requirement – OEM platforms are
required to include a supported OS debug interface, accessible by an enduser.
This allows developers to help in driver debug. The supported
21
D D
C C
+3VSUS +3VSUS
PCB ID Memory ID
Windows 7 debug interfaces are EHCI, 1394 port and COM port.
With skylake EHCI Removal, Potential Gap with Windows* 7 Kernel Debug
and OS Installation – Mitigation Required
To implement UART for WIN7 WHCK requirement if need
Please refer to Intel document #548689 - RVP5
NO UART MUX
IOAC EC CTRL (X3 PCH CTRL)
Touch Panel
Touch Pad
I2C2_SDA_Touch
I2C2_SCL_Touch
R2103 10KOhm@
R2114 10KOhm@
BBS20
PCH_UATR0_DEBUG_R X28
PCH_UATR0_DEBUG_T X28
LCD_BKLTEN_PCH3,45
12
12
Reserve UART
For Debug Port
WLAN_ON_PCH53
BT_ON/OFF#_PCH53 TP_IRQ# 30,31
I2C2_SDA_Touch45
I2C2_SCL_Touch45
PCH_I2C1_SDA31
PCH_I2C1_SCL31
+3VS
+3VSUS +3VSUS +3VSUS
MB BD ID
PCH(2)_ISH
MEM_ID0
MEM_ID1
MEM_ID2
GPP_B18
GPP_B21
1
T2117
PCH_UATR0_DEBUG_R X
PCH_UATR0_DEBUG_T X
T2111
T2144
T2112
1
1
1
BBS
GPP_C10
GPP_C11
WLAN_ON_PCH
BT_ON/OFF#_PCH
LCD_BKLTEN_PCH
GPP_C23
I2C2_SDA_Touch
I2C2_SCL_Touch
PCH_I2C1_SDA
PCH_I2C1_SCL
Mem test ID eMMC / HDCP ID
U0301F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
947859
0101-03860PB
LPSS ISH
D 3.3V GPIO
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART 1_RXD
GPP_C13/UART1_TXD/ISH_UART 1_TXD
GPP_C14/UART1_RTS#/ISH_UART 1_RTS#
GPP_C15/UART1_CTS#/ISH_UART 1_CTS#
C 3.3V GPIO
F 1.8V GPIO
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
F 1.8V GPIO
Sx_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6
Function ID
+1.8VS
+3VS
+3VSUS
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_D15/ISH_UART0_RTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
+1.8VS 36,49,57,91
+3VS 3 ,4,20,22,23,24,30,31,32,36,41,44,45,48,49,50,51,53,56,57 ,62,64,74,87,91,92
+3VSUS 4,20,22,23,24,25,26,28,30,31,41 ,51,53,62,74,81,92
+3VSUS
GPU_EVENT#_PCH
THRO_GPU#
GC6_FB_GPU
DGPU_EN_PWR
P2
P3
GPU_EVENT#_PCH_R
P4
DGPU_HOLD_RST#
P1
DGPU_PWROK
M4
THRO_GPU#
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
TP_SENSOR_OFF#
CPU_ID1
eMMC_ID
TP_IRQ#
BID_GPU
GC6_FB_GPU
OP_SD#
PCB_ID0
PCB_ID1
MEM_ID3
TOUCH_INT_CPU_R
TOUCH_RST#_C PU_R
1 2
R2102 10KOhm
1 2
R2123 10KOhm
1 2
R2125 10KOhm
1 2
R2101 0Ohm
MEM_CHA
MEM_CHB
HDCP_ID
PANEL_ID
R2121 0Ohm@/TPANEL
R2113 0Ohm@/TPANEL
12
12
DGPU_EN_PWR 74
TP_SENSOR_OFF# 31
GPU_EVENT#_PCH 74
DGPU_HOLD_RST# 70
DGPU_PWROK 70,87
THRO_GPU# 74
GC6_FB_GPU 74
OP_SD# 36
PANEL ID
+3VSUS
12
R2154
10KOhm
/14inch
PANEL_ID
12
R2155
10KOhm
@/15inch
Touch Pad
Touch Pad
TOUCH_INT_CPU 45
TOUCH_RST#_C PU 45
12
R2104
10KOhm
B B
12
R2105
10KOhm
@
PCB_ID1
(GPP_C14)
R10
R11 0
R12 01
R20 1 1
A A
12
R2106
10KOhm
@
12
R2107
10KOhm
PCB_ID0
(GPP_C13)
0 0
R2108
10KOhm
@
R2109
10KOhm
12
12
12
PCB_ID1
12
MICRON / 8Gb / 0315-01NJ0PB
0
T52L256M32D1PF-107WT:B
1
1
MICRON / 16Gb / 0315-01N10PB
MT52L512M32D2PF-107WT:B
2
MICRON / 32Gb / 0315-01N20PB
MT52L1G32D4PG-107WT:B
3
KINGSTONE / 8Gb / 0315-025A0PB
KB26AAEL3E08G
4
KINGSTONE / 16Gb / 0315-025E0PB
KB26AAEL3E16G
5
SKHynix / 8Gb / 0315-01YQ0PB
H9CCNNN8GTALAR-NUD
6
SKHynix / 16Gb / 0315-01Y00PB
H9CCNNNBJTALAR-NUD
7
5
R2115
10KOhm
@
R2116
10KOhm
12
R2119
10KOhm
@
12
R2120
10KOhm
MEM_ID3
(GPP_C15)
0 0
0
0
0
0 1
0
0
0
12
R2117
10KOhm
@
MEM_ID0
MEM_ID1PCB_ID0
MEM_ID2
MEM_ID3
12
R2118
10KOhm
MEM_ID2
(GPP_B17)
MEM_ID1
(GPP_B16)
0 0
0
0
0
1
1
1
1 1
0
1
1 1 1
4
MEM_ID0
(GPP_B15)
10
0
00
1
0
12
R2136
100KOhm
/VGA
12
R2147
100KOhm
@/UMA
12
R2133
10KOhm
/U42
12
R2134
10KOhm
/U22
BID_GPU
UMA
DIS 1
CPU_ID1
U22 0
U42 1
BID_GPU
CPU_ID1
0
12
R2148
10KOhm
12
R2149
10KOhm
@
GPP_A18(0)
GPP_A18(1)
GPP_A19(0)
GPP_A19(1)
12
12
R2150
10KOhm
MEM_CHA
MEM_CHB eMMC_ID
R2151
10KOhm
@
12
R2152
10KOhm
/HDCP2.2
12
R2153
10KOhm
@/HDCP1.4
CHA CHB
Disable
Enable
Disable
Enable
3
12
12
R2132
10KOhm
@
R2135
10KOhm
HDCP_ID
+3VS
DGPU_PWROK
PCH_I2C1_SCL
PCH_I2C1_SDA
Change To 2.2Kohm PU side
Default PU +3V For S3 Resume by TP side
GPP_B18
GSPI0_MOSI / GPP_B18 - Internal weak pull down 20k ohm
0 : Disable No Reboot mode(default)
1 : Enable NO Reboot Enable mode
1 2
R2141 10KOhm@
1 2
R2146 2.2KOhm@
1 2
R2145 2.2KOhm@
1 2
R2112 4.7KOhm@
1 2
R2122 4.7KOhm@
+3VS
+3VS
+3VSUS
Default is GPO, to reserve pull high to +3VSUS_ORG
PCH(2)_ISH
PCH(2)_ISH
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
PCH(2)_ISH
Kai_Shen
Kai_Shen
Kai_Shen
of
21 94Friday, April 07, 2017
21 94Friday, April 07, 2017
21 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
22
HDA_SDO_R
HDA_SDI0_R
HDA_SDI1
HDA_RST#_R
D D
NPO/+/-0.25PF
C2201
2PF/25V
vx_c0201
12
2PF/25V
NPO/+/-0.25PF
vx_c0201
C2202
EMI request for Kaby Lake
Recommended Routing : Stripline < 2"
Alternative Routing : Microstrip <1" (less noise-reduction)
C C
GPU_OVERT#74
VGA_THERM#32,74,92
HDA_SPKR36
HDA_SYNC36
HDA_BCLK36
HDA_SDO3 6
HDA_SDI036
HDA_RST#3 6
+3VSUS
12
12
C2203
2PF/25V
NPO/+/-0.25PF
vx_c0201
@
12
C2204
2PF/25V
NPO/+/-0.25PF
vx_c0201
GND
HDA_SDO
HDA_SYNC
HDA_BCLK
HDA_SDO
HDA_SDI0
HDA_RST#
12
12
HDA_SPKR
1
1
FN_ID2
FN_ID1
HDA_SDO_RHDA_SDI0
HDA_SDI0_R
HDA_SYNC_R
HDA_BCLK_R
HDA_SDO_R
HDA_SDI0_R
HDA_SDI1
HDA_RST#_R
GPP_D23
SPKR
R2206 33Ohm@
R2207 33Ohm@
R2219 33Ohm
R2216 33Ohm
R2215 33Ohm
R2220 33Ohm
R2217 33Ohm
R220410KOhm
R220510KOhm
GPU_OVERT#
GPU_ALERT#
GPU_OVERT#
GPU_ALERT#
1 2
SP2208 0Ohm
@/SP
T2201
T2202
PCH(3)_HDA_SDIO
U0301G
AUDIO
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
SDIO/SDXC
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
+3VS
+3VSUS
TPanel_EN_R
SKL_SD_RCOMP
RTC_IN#
+3VS 3 ,4,20,21,23,24,30,31,32,36,41,44,45,48,49,50,51,53,56,57 ,62,64,74,87,91,92
+3VSUS 4,20,21,23,24,25,26,28 ,30,31,41,51,53,62,74,81,92
R2211 0Ohm@/TPANEL
12
1 2
R2201 200Ohm1%
RTC_IN# 24
TPanel_EN 45
TPanel_ON 45
947859
0101-03860PB
RF requirement
1 2
HDA_BCLK
12
C2205
22PF/50V
@
B B
+3VSUS
Function ID
12
12
R2212
10KOhm
@
R2213
10KOhm
12
12
R2214
10KOhm
@
R2218
10KOhm
FN_ID2
FN_ID1
R2202 20KOhm@
GND
HDA_SDO_R
* The signal has a weak internal Pull-down.
Name
P5HCJ_KBL
GPP_B14
GPP_B18
GPP_B22
GPP_C5
HDA_SDO
A A
GPP_C2
SPKR
+3VSUS
12
D2201 1.2V/0.1A
HDA_SDO - Internal weak pull down
FLASH DESCRIPTOR SECURITY OVERRRIDE
0 : Enable security measure defined in the Flash Descriptor
1 : Disable Flash Descriptor Security
0
0
0
0
0
0
0 = Disable “Top Swap” mode. (Default)
1 = Enable “Top Swap” mode.
0 = Disable “No Reboot” mode. (Default)
1 = Enable “No Reboot” mode
0 = SPI (Default)
1 = LPC
0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.
0 = Enable security measures defined in the Flash
Descriptor. (Default)
1 = Disable Flash Descriptor Security (override).
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality).
1 2
R2209 4.7KOhm@
1 2
R2210 4.7KOhm@
CRB 0.53 reserve 150k ohm
R2203
4.7KOhm
@
12
+3VS
+3VSUS
PCH_FLASH_DESCRIPTOR 30
Description
SPKR - Internal weak pull down
0 : Disable TOP Swap mode (default)
1 : Enable Top Swap Enable
Default is GPO, to reserve pull high to +3VSUS_ORG
GPP_E19 0
GPP_E21 0
From EDS_Intel_PCH(Skylake.UY_Kabylake.UY)_Vol1_545659_Rev2p0 Page.55-57
5
4
0 = Port B is not detected. (Default)
1 = Port B is detected.
0 = Port C is not detected. (Default)
1 = Port C is detected.
3
PCH(3)_HDA/SDIO
PCH(3)_HDA/SDIO
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
PCH(3)_HDA/SDIO
Kai_Shen
Kai_Shen
Kai_Shen
22 94Friday, April 07, 2017
22 94Friday, April 07, 2017
22 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
23
D D
PEX_TXX0*70
PEX_TXX070
PEX_RX0*70
PEX_RX070
PEX_TXX1*70
PEX_TXX170
PEX_RX1*70
PEX_RX170
PCIE x 4 -dGPU
M.2 SATA/PCIE x 4 -SSD
C C
WLAN
PEX_TXX2*70
PEX_TXX270
PEX_RX2*70
PEX_RX270
PEX_TXX3*70
PEX_TXX370
PEX_RX3*70
PEX_RX370
PCIE_RXN551
PCIE_RXP551
PCIE_TXN551
PCIE_TXP551
PCIE_RXN651
PCIE_RXP651
PCIE_TXN651
PCIE_TXP651
PCIE_RXN751
PCIE_RXP751
PCIE_TXN751
PCIE_TXP751
SATA_RXN851
SATA_RXP851
SATA_TXN851
SATA_TXP851
PCIE_RXN_WLAN53
PCIE_RXP_WLAN53
PCIE_TXN_WLAN53
PCIE_TXP_WLAN53
PCIE_RCOMP PDG 0.9 need 100 ohm 0.1% / CRB 0.53 use 100 ohm +-1%
Reserve TP for XDP
PCIE_RXN11_M2_SSD56
PCIE_RXP11_M2_SSD56
PCIE_TXN11_M2_SSD56
M.2 SATA/PCIE x 2 -SSD
If SATA driver need change port,
B B
Also must change reltaed "DEVSLP and SATAXPCIE" pin
PCIE_TXP11_M2_SSD56
SATA_RXN12_M2_SSD56
SATA_RXP12_M2_SSD56
SATA_TXN12_M2_SSD56
SATA_TXP12_M2_SSD56
PEX_TXX0*
PEX_TXX0
PEX_RX0*
PEX_RX0
PEX_TXX1*
PEX_TXX1
PEX_RX1*
PEX_RX1
PEX_TXX2*
PEX_TXX2
PEX_RX2*
PEX_RX2
PEX_TXX3*
PEX_TXX3
PEX_RX3*
PEX_RX3
PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5
PCIE_RXN6
PCIE_RXP6
PCIE_TXN6
PCIE_TXP6
PCIE_RXN7
PCIE_RXP7
PCIE_TXN7
PCIE_TXP7
SATA_RXN8
SATA_RXP8
SATA_TXN8
SATA_TXP8
R2301 100Ohm1%
PCIE_RXN11_M2_SSD
PCIE_RXP11_M2_SSD
PCIE_TXN11_M2_SSD
PCIE_TXP11_M2_SSD
SATA_RXN12_M2_SSD
SATA_RXP12_M2_SSD
SATA_TXN12_M2_SSD
SATA_TXP12_M2_SSD
C2304 0.22UF/10V/VGA
C2303 0.22UF/10V/VGA
C2310 0.22UF/10V/VGA
C2309 0.22UF/10V/VGA
C2308 0.22UF/10V/VGA
C2307 0.22UF/10V/VGA
C2306 0.22UF/10V/VGA
C2305 0.22UF/10V/VGA
1 2
T2323
T2324
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
1
C23220.1UF/16V
C23230.1UF/16V
PEX_RX0*_C
PEX_RX0_C
PEX_RX1*_C
PEX_RX1_C
PEX_RX2*_C
PEX_RX2_C
PEX_RX3*_C
PEX_RX3_C
PCIE_TXN_WLAN_C
PCIE_TXP_WLAN_C
PCIE_RCOMPN
PCIE_RCOMPP
PROC_PRDY#
PROV_PREQ#
PIRQA#
PCH(4)_USB/PCIE/SATA
U0301H
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
947859
0101-03860PB
SSIC / USB3
USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
(OD)
GPP_E5/DEVSLP1
(OD)
GPP_E6/DEVSLP2
(OD)
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
USB3_RXN1
H8
USB3_RXP1
G8
USB3_TXN1
C13
USB3_TXP1
D13
USB3_RXN2
J6
USB3_RXP2
H6
USB3_TXN2
B13
USB3_TXP2
A13
USB3_RXN3
J10
USB3_RXP3
H10
USB3_TXN3
B15
USB3_TXP3
A15
USB3_RXN4
E10
USB3_RXP4
F10
USB3_TXN4
C15
USB3_TXP4
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
USBCOMP
USB2_ID_OTG
AG3
USB2_VBUSSENSE_OTG
AG4
A9
OC0#
C9
OC1#
D9
OC2#
B9
OC3#
J1
1
T2326
SATA_DEVSLP1
J2
SATA_DEVSLP2
J3
H2
1
T2325
SATA_SSD1_PEDET
H3
SATA_SSD2_PEDET
G4
SATA_LED#
H1
+3VS
+3VSUS
R2302 113Ohm1%
R2319 1KOhm
R2320 1KOhm
1 2
SP2301 0Ohm@/SP
1 2
SP2302 0Ohm@/SP
1 2
SP2303 0Ohm@/SP
1 2
SP2304 0Ohm@/SP
USB3_RXN1 52
USB3_RXP1 52
USB3_TXN1 52
USB3_TXP1 52
USB3_RXN2 52
USB3_RXP2 52
USB3_TXN2 52
USB3_TXP2 52
USB3_RXN3 41
USB3_RXP3 41
USB3_TXN3 41
USB3_TXP3 41
USB3_RXN4 41
USB3_RXP4 41
USB3_TXN4 41
USB3_TXP4 41
USB_PN1_30 52
USB_PP1_30 52
USB_PN2_30 52
USB_PP2_30 52
USB_PN3_TYPEC 41
USB_PP3_TYPEC 41
USB_PN4_TYPEC 41
USB_PP4_TYPEC 41
USB_PN5_20 64
USB_PP5_20 64
USB_PN6_BT 53
USB_PP6_BT 53
USB_PN7_CCD 45
USB_PP7_CCD 45
USB_PN8_CR 64
USB_PP8_CR 64
USB_PN9_FP 69
USB_PP9_FP 69
USB_PN10_TP 4 5
USB_PP10_TP 45
1 2
1 2
1 2
+3VS 3 ,4,20,21,22,24,30,31,32,36,41,44,45,48,49,50,51,53,56,57 ,62,64,74,87,91,92
+3VSUS 4,20,21,22,24,25,26,28,30,31,41 ,51,53,62,74,81,92
USB3.0 S/C
USB3.0
USB3.0 Type C
USB3.0 Type C
USB3.0 S/C
USB3.0
USB3.0 Type C
USB3.0 Type C
USB20 (IO BD)
Bluetooth
Camera (EDP CONN)
Card reader (IO BD)
FingerPrinter
USB2_COMP PDG 1.0 R=113 +-1%
USB_OC0#_PCH 52
USB_OC1#_PCH 52
USB_OC2#_PCH 64
USB_OC3#_PCH 41
SATA_DEVSLP1 51
SATA_DEVSLP2 51
SATA_SSD1_PEDET 51
SATA_SSD2_PEDET 51
USB30 with USB Chager
USB30
USB20(IO BD)
Type C
SATA SSD1
SATA SSD2
+3VSUS
OC3#
OC2#
OC1#
OC0#
SATA_LED#
PIRQA#
Capture from 545659_545659_SKL_PCH_LP_EDS_Rev1_0_pub
Please refer the latest Doc.
A A
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
3 4
7 8
1 2
5 6
1 2
R2304 10KOhm
1 2
R2318 10KOhm
HE4EA
HE4EA
HE4EA
@
RN2301B10KOhm
RN2301D10KOhm
RN2301A10KOhm
RN2301C10KOhm
Engineer:
Engineer:
Engineer:
1
+3VS
PCH(4)_USB/PCIE/SATA
PCH(4)_USB/PCIE/SATA
PCH(4)_USB/PCIE/SATA
Title :
Title :
Title :
Kai_Shen
Kai_Shen
Kai_Shen
of
23 94Friday, April 07, 2017
23 94Friday, April 07, 2017
23 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
N/AN/AN/AN/AN/AN/A
4
3
2
1
+1.8VSUS
+3VS
24
A36
B36
C38
D38
C36
D36
A38
B38
C31
D31
C33
D33
A31
B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
U0301I
CSI-2
CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3
CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7
CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11
947859
0101-03860PB
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
CSI2_COMP
GPP_D4
1
EMMC_RCOMP
R2418
1 2
T2417
100Ohm
RES 100 OHM 1/16W (0402) 1%
12
R2419
200Ohm
RES 200 OHM 1/16W (0402) 1%
GND
GND
eMMC_D0 49
eMMC_D1 49
eMMC_D2 49
eMMC_D3 49
eMMC_D4 49
eMMC_D5 49
eMMC_D6 49
eMMC_D7 49
eMMC_RCLK 4 9
eMMC_CLK 49
eMMC_CMD 49
D D
C C
PCH(5)_CLK
VCCRTC is sourced from Vbatt in G3 or VCCDSW_3p3 in Non-G3 state,
platform designers must ensure the effective voltage at VCCRTC does not
exceed 3.2V.
+VCC_RTC
12
C2407
1UF/6.3V
GND GND
+3VSUS
+VCC_RTC
R2420
1KOhm
1 2
@
D2401
12
RB751V-40
0.37V/30mA
D2402
12
RB751V-40
0.37V/30mA
+1.8VSUS 9,26,84
+3VS 3,4,20,21,22,23,30,31,32,36,41,44,45,48,49,50 ,51,53,56,57,62,64,74,87,91,92
+3VSUS 4,20,21,22,23,25,26,28 ,30,31,41,51,53,62,74,81,92
+VCC_RTC 25,26,36,60
+RTCBAT
+3VA
R2425
0Ohm@
+RTC_AC
+RTC_BAT
R2423
1.5KOhm
1%
R2424
45.3KOhm
1%
GND
1 2
R2405 1KOhm
12
R2409
10MOhm
GND GND
CON2401
4
SIDE2
2
2
1
1
3
SIDE1
WtoB_CON_2P
12V17GISM030
P/N:1217-0105000
P/N:1217-0105000
P/N:1217-0105000 P/N:1217-0105000
@
Q2402
2N7002
@
1
1
+1.8VSUS
12
32
3
D
G
2
R2412
100KOhm
1% @
S
RTC_IN# 22
U0301J
CLOCK SIGNALS
CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
Any differential clock pair not being used must be left as no connect
Any differential clock pair not being used must be left as no connect
Any differential clock pair not being used must be left as no connectAny differential clock pair not being used must be left as no connect
CLK_PCIE_SSD1#_PCH51
CLK_PCIE_SSD1_PCH51
CLK_REQ1_SSD1#51
CLK_PCIE_SSD2#_PCH51
CLK_PCIE_SSD2_PCH51
CLK_REQ2_SSD2#51
PEX_REFCLK*7 0
PEX_REFCLK70
CLK_REQ3_PEG#70
CLK_PCIE_WLAN#_PCH53
B B
CLK_PCIE_WLAN_PCH53
CLK_REQ4_WLAN#53
CLK_PCIE_SSD1#_PCH
CLK_REQ1_SSD1# CLK_REQ1_SSD1#_R
CLK_PCIE_SSD2#_PCH
CLK_PCIE_SSD2_PCH
CLK_REQ2_SSD2#
PEX_REFCLK*
PEX_REFCLK
CLK_REQ3_PEG#
CLK_PCIE_WLAN#_PCH
CLK_PCIE_WLAN_PCH
CLK_REQ4_WLAN#
SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
SRCCLKREQ#[5:0] (PDG v1.3 Page 835)SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any un-used, disabled, must be left as no connects at the PCH side on the platform.Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any used, enabled, should connect to a PCIe* connector pin or a device down ball
Any used, enabled, should connect to a PCIe* connector pin or a device down ball
Any used, enabled, should connect to a PCIe* connector pin or a device down ballAny used, enabled, should connect to a PCIe* connector pin or a device down ball
with a 10K Ohm ±10% external pull-up resistor to core rail.
with a 10K Ohm ±10% external pull-up resistor to core rail.
with a 10K Ohm ±10% external pull-up resistor to core rail.with a 10K Ohm ±10% external pull-up resistor to core rail.
CLK_REQ4_WLAN#_R
CLK_REQ3_PEG#_R
R2429 10KOhm
R2408 10KOhm@
R2411 10KOhm
R2421 10KOhm@
R2410 10KOhm
R2413 10KOhm@
SP2405@/SP
SP2406@/SP
SP2407@/SP
SP2408@/SP
SP2409@/SP
SP2410@/SP
SP2415@/SP
SP2416@/SP
SP2417@/SP
SP2412@/SP
SP2413@/SP
SP2414@/SP
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@
CLK_PCIE_SSD1#_PCH_R
CLK_PCIE_SSD1_PCH_RCLK_PCIE_SSD1_PCH
CLK_PCIE_SSD2#_PCH_R
CLK_PCIE_SSD2_PCH_R
CLK_REQ2_SSD2#_R
PEX_REFCLK*_R
PEX_REFCLK_R
CLK_REQ3_PEG#_R
CLK_PCIE_WLAN#_PCH_R
CLK_PCIE_WLAN_PCH_R
CLK_REQ4_WLAN#_R
+3VSUS
+3VS
GND
+3VSUS
+3VS
GND
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
947859
0101-03860PB
Ball E37
Ball E37
Ball E37Ball E37
XTAL_24M_IN
Ball E35
Ball E35
Ball E35Ball E35
XTAL_24M_OUT
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
24MHz signal
R2432 0Ohm/U22
R2433 0Ohm/U22
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
需需需需需需需需
SUSCLK_PCH
XTAL_24M_IN
XTAL_24M_OUT
XCLK_BIASREF
XTAL_32K_X1
XTAL_32K_X2
SRTC_RST#
RTC_RST#
SW_RTCRST30
GND
XTAL_24M_OUT_R_R
R2401 1MOhm/U22
1
T2418
0.5%
1 2
R2417 2.71Kohm
1 2
SP2403 0Ohm
@/SP
12
10KOhm
XTAL_32K_X1
XTAL_32K_X2
+VCCF24NS_1P0
Q2401
2N7002
12
R2407
32
3
JRST2401
D
SGL_JUMP
@/SP
1
1
G
S
2
GND
R2402 10MOhm
12
JRST2402
SGL_JUMP
@/SP
1
2
1 2
R2403 20KOhm
1
2
12
1
2
GND
1
2
C2406
1UF/6.3V
GND
12
R2455
0Ohm
C2405
1UF/6.3V
1 2
GND
R2404 20KOhm
12
C2409
0.1UF/16V
@
GND
+VCC_RTC
1 2
CLK_REQ2_SSD2#_R
A A
CLK_REQ1_SSD1#_R
5
1 2
R2414 10KOhm
1 2
R2416 10KOhm
R2430 10KOhm
R2431 10KOhm
@
1 2
1 2
@
GND
GND
+3VS
+3VS
SP2401
0Ohm
@/SP
1 2
X2401
24MHZ
C2402
10PF/50V
/U22
/U22
13
2
4
12
C2401
10PF/50V
/U22
GND
XTAL_24M_OUT_R
12
4
3
1 2
C2404
7PF/50V
X2402
1 2
32.768KHZ
07V080000075
+/-20ppm/9PF
SP2402
0Ohm
@/SP
1 2
XTAL_32K_X1_R
PCH(5)_CLK
PCH(5)_CLK
PCH(5)_CLK
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
C2403
7PF/50V
1 2
GND
2
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
Kai_Shen
Kai_Shen
Kai_Shen
of
24 94Friday, April 07, 2017
24 94Friday, April 07, 2017
24 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
25
In Table 42-1 of PDG (#561280, Rev1p0)
PROCPWRGD is PCH to CPU, but KBL-U don't has this pin at CPU side.
we assume it's conted in MCP package.
D D
PM_RSMRST#30
ALL_SYS_PWRGD delay 99 ms from EC
SYS_PWROK_PCH30
DSW function / non-AMT
WAKE_PCIE#53
PCH_PWROK logic
C C
1 2
DE_ALL_SYS_PGD_EC30
SP2507
@/SP
SYS_PWROK logic
B B
1 2
SYS_PWROK_EC30
R2508 0Ohm/0-ohm
VCCST_PWRGD logic
DELAY_ALL_SYSTEM_PWRGD
ALL_SYSTEM_PWRGD
So follow CRB to reserve TP only.
H_CPUPWRGD_T P H_CPUPWRGD
1
T2501
SYS_PWROK_PCH
PM_RSMRST_R
1
T2513
1
T2512
DE_ALL_SYS_PGD_EC_R
PM_SUSB#
SUSACK#
PM_SUSB#
1 2
R2511 0Ohm/0-ohm
1 2
R2530 0Ohm@
For shut down Sequence
Tplt17 < 1us
U2505
A
1
B
2
3 4
GND
Vcc=2~5.5
PLT_RST#
SP2501
@/SP
R2503 1KOhm@
SP2502 0Ohm@/SP
R2506 0Ohm/0-ohm
R2510 0Ohm@
T2511
T2502
T2508
ALL_SYSTEM_PWRGD30,92
DELAY_ALL_SYSTEM_PWRGD30
U2504
A
1
VCC
B
2
3 4
GND
Vcc=2~5.5
5
VCC
Y
1 2
1 2
1 2
1 2
1 2
1
1
1
VRM_PWRGD74,80,92
PLT_RST#
+3VSUS
5
Y
12
R2545
100KOhm
@
10V240000005
SYS_PWROK_AND
H_VCCST_PWRGD _L
PM_SYS_RESET#_R
PM_RSMRST_R
VCCST_PWRGD_C PU
PCH_PWROK_PCH
PCH_DPWROK
SUS_PWR_ACK_R
SUSACK#_RSUS_PWR_ACK_R
LAN_WAKE#
GPD11
GPD7
For Intel power sequence requestment
ALL_SYS_PWRGD to Delay_ALL_SYS_PGD >2ms
Delay By EC(2ms+ EC processing time (3ms~33ms)
R2509 0Ohm/0-ohm
12
R2547
100KOhm
@
10V240000005
PCH(6)_POWER MANAGE
AN10
B5
AY17
A68
B65
B6
BA20
BB20
AR13
AP11
BB15
AM15
AW17
AT15
1 2
R2531 0Ohm@
1 2
R2507 0Ohm/0-ohm
1 2
D2501 RB751V-40
1 2
D2502 RB751V-40
DE_ALL_SYS_PGD_HW 30
12
C2540
0.1UF/16V
@
1 2
U2503
1
NC
2
A
3 4
GND
74AUP1G07GW
06V030000021
U0301K
GPP_B13/PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
VCCST_PWRGD
SYS_PWROK
PCH_PWROK
DSW_PWROK
GPP_A13/SUSWARN#/SUSPWRDN ACK
GPP_A15/SUSACK#
WAKE#
GPD2/LAN_WAKE#
GPD11/LANPHYPC
GPD7/RSVD
947859
0101-03860PB
VCC
Y
SYSTEM POWER MANAGEMENT
ALL_SYSTEM_PWRGD_PMOK
VR_READY_PMOK
PLT_RST#
SYS_PWROK_PCH
+3VSUS
12
5
C2504
0.1UF/16V
R2517 0Ohm@
12
R2554
100KOhm
N/A
GND
12
C2502
100PF/50V
@
GND
1 2
R2553 0Ohm
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
+3VSUS
U2502
A
1
B
2
3 4
GND
Vcc=2~5.5
1 2
1
2
R2515 0Ohm/0-ohm
5
VCC
Y
U2501
@
5
A
VCC
B
4
GND3Y
SN74LVC1G08DCKR
1 2
+1.0V
GND
12
12
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
PM_PWROK
12
R2519
10KOhm
+3V
12
GND
R2520
1KOhm
1 2
R2521 60.4Ohm1 %
@
C2505
0.1UF/16V
+1.0V
+3V
+3VSUS
+VCC_RTC
SLP_S0#
PM_SUSB#
PM_SUSC#
GPD10
SLP_SUS#
SLP_LAN#
SLP_WLAN#
ME_PM_SLP_M#_PCH
AC_PRESENT_R
BATLOW#
PME#
SM_INTRUDER#
MPHY_EXT_PWR_GATEB_R
VR_ALERT#
SP2505 0Ohm
@/SP
1 2
1
T2503
1
T2504
1
1
1
1
If Deep Sx is not implemented on the platform, this signal may be left as no connect
T2510
T2505
T2506
T2507
1
SLP_S3# and SLP_S4# logic
PM_SUSB#
12
GND
C2503
100PF/50V
@
VCCST_PWRGD_C PUVCCST_PWRGD_C PU_R
PCH_PWROK_PCH
C2516
0.1UF/16V
@
12
R2516
10KOhm
GNDGNDGND
PM_SUSC#
BUF_PLT_RST# 30,32,49,51,53,62,70
1 2
R2505 0Ohm
C2541
0.1UF/16V
@
12
+VDDQ/+VCCST_CPU/+VCCSTG to VCCST_PWRGD must > 1ms
+1.0V 3,5,7,9,32,57,91
+3V 31,45,57,91
+3VSUS 4,20,21,22,23,24,26,28 ,30,31,41,51,53,62,74,81,92
+VCC_RTC 24,26,36,60
PM_PWRBTN# 30
ME_AC_PRESENT 30
T2509
internal pull high
1 2
R2502 0Ohm
SUSB_EC#30,57,74,91,92
1 2
R2504 0Ohm
SUSC_EC#30,57,91
internal pull high
Set to GPI
BATLOW#
LAN_WAKE#
GPD7
WAKE_PCIE#
AC_PRESENT_R
SM_INTRUDER#
PME#
VR_ALERT#
PM_SYS_RESET#_R
PM_SUSB# 30
PM_SUSC# 30
1 2
R2522 10KOhm
1 2
R2523 10KOhm
1 2
R2524 10KOhm
1 2
R2525 1KOhm
1 2
R2526 10KOhm
1 2
R2513 1MOhm
+3VSUS
1 2
R2527 10KOhm@
1 2
R2528 10KOhm@
1 2
R2501 10KOhmN/A
+3VSUS
+VCC_RTC+3VSUS
A A
PCH(6)_POWER MANAGE
PCH(6)_POWER MANAGE
PCH(6)_POWER MANAGE
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
Kai_Shen
Kai_Shen
Kai_Shen
of
25 94Friday, April 07, 2017
25 94Friday, April 07, 2017
25 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
4
3
2
1
26
D D
C C
near V19
B B
PCH(7)_POWER
+1.0VSUS
4A
+1.0VSUS_ORG
12
C2601
1UF/6.3V
vx_c0402_small
+VCCPRIM_CORE
12
C2602
1UF/6.3V
vx_c0402_small
+1.0VSUS_ORG
12
C2603
1UF/6.3V
vx_c0402_small
+VCCAMPHYPLL_1P0
near K15
1 2
1 2
S1V040200001
12
C2607
1UF/6.3V
vx_c0402_small
+VCCAPLLEBB_1P0
+VCCAPLL_1P0
C2608
47uF/6.3V
@
+VCCPAZIO
C2609
1UF/10V
@
+VCCMPHYGTAON_1P0_LS_SIP
2A
C2605
@
C2611
1UF/6.3V
12
+1.0VSUS
+3VSUS
12
47UF/6.3V
+3VSUS_ORG
12
vx_c0402_small
near AB19
near AF18
near K17
C2606
1UF/6.3V
near N15near N15
R2604 0Ohm
SP2602 0Ohm
@/SP
@/SP
SP2614 0Ohm
@/SP
SP2612 0Ohm
@/SP
SP2613 0Ohm
12
12
12
12
12
+VCCMPHYGTAON_1P0_LS_SIP
1 2
S1V080500001
1 2
S1V080500001
1 2
S1V040200001
1 2
R2639 0Ohm
Decoupling cap for internal power
+VCCDSW_1P0
+1.0VSUS_ORG
+VCCPDSW_3P3
+3VSUS_ORG
+VCCSRAM_1P0
+1.0VSUS_ORG
C2612
near N18
1UF/6.3V
09V010000096
2 1
B2601 75OHM
12
C2636
0.1UF/16V
C2637
0.1UF/16V
C2640
2PF/25V
NPO/+/-0.25PF
vx_c0201
GND
09V010000096
2 1
B2602 75OHM
12
C2642
2PF/25V
NPO/+/-0.25PF
vx_c0201
2A
+VCCSRAM_1P0
0.642A
0.088A
0.033A
12
C2628
0.1UF/16V
GND
1 2
C2604 1UF/6.3V
near AL1
1 2
R2648 0Ohm
1 2
C2644 0.1UF/16V
1 2
C2610 1UF/6.3V
vx_c0402_small
near AF20
1 2
R2649 0Ohm
C2645 0.1UF/16V
12
C2641
2PF/25V
NPO/+/-0.25PF
vx_c0201
12
C2643
2PF/25V
NPO/+/-0.25PF
vx_c0201
+VCCAMPHYPLL_1P0
+VCCAPLLEBB_1P0
2.574A
+VCCAPLL_1P0_SOC
+VCCPAZIO_SOC
1 2
+VCCAPLL_1P0_SOC
near V15
+VCCPAZIO_SOC
near AJ19
0.696A
0.022A
0.088A
0.026A
0.696A
0.118A
0.068A
0.011A
0.642A
0.075A
0.696A
0.033A
U0301O
AB19
VCCPRIM_1P0_1
AB20
VCCPRIM_1P0_2
P18
VCCPRIM_1P0_3
AF18
VCCPRIM_CORE_1
AF19
VCCPRIM_CORE_2
V20
VCCPRIM_CORE_3
V21
VCCPRIM_CORE_4
AL1
DCPDSW_1p0
K17
VCCMPHYAON_1P0_1
L1
VCCMPHYAON_1P0_2
N15
VCCMPHYGT_1P0_1
N16
VCCMPHYGT_1P0_2
N17
VCCMPHYGT_1P0_3
P15
VCCMPHYGT_1P0_4
P16
VCCMPHYGT_1P0_5
K15
VCCAMPHYPLL_1P0_1
L15
VCCAMPHYPLL_1P0_2
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_4
Y18
VCCPRIM_1P0_5
AD17
VCCDSW_3p3_1
AD18
VCCDSW_3p3_2
AJ17
VCCDSW_3p3_3
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0_1
AF21
VCCSRAM_1P0_2
T19
VCCSRAM_1P0_3
T20
VCCSRAM_1P0_4
AJ21
VCCPRIM_3p3_1
AK20
VCCPRIM_1P0_6
N18
VCCAPLLEBB_1P0
947859
0101-03860PB
PCIe Gen3 Lane X10
USB3 Port X3
All HSIO disabled (basic comsunption)
=0.154x10+0.132x3+0.064
=2 A
CPU POWER 4 OF 4
AK15
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3p3_2
VCCPRIM_1P0_7
VCCATS_1p8
VCCRTCPRIM_3p3
VCCRTC_1
VCCRTC_2
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
0.02A
0.075A
0.696A
0.006A
0.001A
VCCRTCEXT
0.035A
0.029A
0.024A
0.033A
0.004A
0.0039A
Intel confirm pull down 1k
+3VSUS_ORG+3VSUS
1 2
SP2601 0Ohm
+1.0VSUS +1.0VSUS_ORG
1 2
SP2603 0Ohm
+1.8VSUS +1.8VSUS_ORG
1 2
SP2604 0Ohm
0.5A
S1V040200001@/SP
1A
S1V060300001@/SP
0.5A
S1V040200001@/SP
0.004A
C2634 1UF/6.3V
GND
C2620 1UF/6.3V
12
R2646
1KOhm
+3VSUS
+1.0VSUS
+1.8VSUS
+3VSUS
+VCCPRIM_CORE
0.006A
1 2
1 2
12
R2647
1KOhm
0.008A
near BB10
0.006A
near AK19
0.001A
R2636 0Ohm
+1.0VSUS 8 2
+1.8VSUS 9 ,24,84
+3VSUS 4,20,21,22,23,24,25,28 ,30,31,41,51,53,62,74,81,92
+VCCPRIM_CORE 82
vx_c0402_small
1 2
C2635 1UF/6.3V
C2613 1UF/6.3V
C2614 1UF/6.3V
0.161A
1 2
R2650 0Ohm
1 2
C2646 0.1UF/16V@
1 2
R2651 0Ohm
1 2
C2647 0.1UF/16V@
C2619 1UF/6.3V
GND
near AK19
@
1 2
Q2601
PJA3411
D
S
23
2
3
G
1
1
1 2
1 2
0.0041A
1 2
near AG15
vx_c0402_small
near Y16
vx_c0402_small
near T16
+3VSUS_ORG
+VCC_RTC
GND
+1.8VSUS_ORG
+V1.8A_SIP
+VCCPDSW_3P3
12
C2615
1UF/6.3V
near AA1
+VCCF100OC_1P0
near A10
SP2605
12
0Ohm
@/SP
S1V040200001
+VCC19P2_1P0
+VCCF100_1P0
+VCCF135_1P0
+VCCF24NS_1P0
+VCC24TBT_1P0
+1.0VSUS_ORG
+1.8VSUS_ORG
12
C2625
1UF/6.3V
near AK17
SP2606
S1V040200001
SP2607
S1V040200001
SP2608
S1V040200001
SP2609
S1V040200001
SP2610
S1V040200001
SP2611
12
S1V040200001
C2624
1UF/6.3V
vx_c0402_small
12
C2617
1UF/6.3V
near AK17 near AK17
+1.0VSUS_ORG
12
0Ohm
@/SP
+1.0VSUS_ORG
12
0Ohm
@/SP
+1.0VSUS_ORG
12
0Ohm
@/SP
+1.0VSUS_ORG
12
0Ohm
@/SP
+1.0VSUS_ORG
12
0Ohm
@/SP
+1.0VSUS_ORG
12
0Ohm
@/SP
+3VSUS_ORG
12
C2618
1UF/6.3V
+3VSUS_ORG
12
3
2
A A
5
GND
EMI request for Kaby Lake
Recommended Routing : Stripline < 2"
Alternative Routing : Microstrip <1"
(less noise-reduction)
4
3
1
E1
C1
6
12
B1
C2
B2
E24
5
R2634
100KOhm
Q2602
BC856BS
R2635
100KOhm
PCH(7)_POWER
PCH(7)_POWER
PCH(7)_POWER
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
Kai_Shen
Kai_Shen
Kai_Shen
26 94Friday, April 07, 2017
26 94Friday, April 07, 2017
26 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
5
D D
4
3
2
1
C C
B B
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
HE4EA 1.0
HE4EA 1.0
HE4EA 1.0
27 94Wednesday, March 29, 2017
27 94Wednesday, March 29, 2017
27 94Wednesday, March 29, 2017
2
1
5
4
3
2
1
+3VSUS
+3VA
28
D D
+3VSUS
+3VA
1 2
R2802 0Ohm
1 2
R2830 0Ohm
@
55mA
15WW06 MOW Pull-up Resistors on SPI_IO2 and SPI_IO3 are no longer needed
1 2
SPI_WP#_IO220
SPI_SO20
SPI_CS#020
F_CS#_EC30
F_SDIO_EC30
C C
PCH_UATR0_DEBUG_T X21
PCH_UATR0_DEBUG_R X21
R2805 33Ohm
1 2
R2806 33Ohm
1 2
R2807 33Ohm
1 2
R2808 33Ohm
1 2
R2809 33Ohm
+3VM_SPI
PCH_UATR0_DEBUG_T X
PCH_UATR0_DEBUG_R X
SPI_CS#0
R2850 0Ohm/Debug
SPI_SO
R2851 0Ohm/Debug
SPI_CLK
R2852 0Ohm/Debug
SPI_SI
R2853 0Ohm/Debug
SPI_HOLD#_IO3
SPI1_CS#0
SPI1_SO
SPI1_WP#
+3VM_SPI
+3VM_SPI
12
R2811
1KOhm @
/Debug
CON2810
1
2
3
12
12
12
12
4
5
6
7
8
9
10
11
12
FPC_CON_12P
12V18GWSM055
12
@
1
2
3
4
5
6
7
8
9
10
11
12
R2812
3.3KOhm
SIDE1
SIDE2
U2801
1
CS#
2
DO(IO1)
3
WP#(IO2)
4
GND
W25Q64FVSSIQ
05V000000025
13
14
VCC
HOLD#(IO3)
CLK
DI(IO0)
12
C2801
0.1UF/16V
8
SPI1_HOLD#
7
SPI1_CLK
6
SPI1_SI
5
SPI ROM size
NON-POA 05V000000025 8M
POA 05V000000031 16M
*
PCH(9)_SPI_SMB
+3VM_SPI
12
R2813
@
1KOhm
FAE: 2015/10/14
1 2
R2820 1KOhm
WW48MOW(ES Sample)
In Skylake Platform Design Guides (PDG) under “Platform Debug & Test Hooks”
chapter, HOOK[3] pin from XDP/CMC header needs to be routed to PCH SPI0_MOSI
pin. The termination resistor can be a value from 1K to 3K ohm pull up to Always rail
(not Core rail) with voltage value from 0.8V to 3.3V. This will ensure PCH hardware
straps are not overridden unintentionally and cause boot issues.
P/NT-pad function Size
@
1 2
R2814 33Ohm
1 2
R2815 33Ohm
1 2
R2816 33Ohm
1 2
R2818 33Ohm
1 2
R2819 33Ohm
1 2
R2821 3KOhm
+3VM_SPI
SPI_HOLD#_IO3 2 0
SPI_CLK 20
SPI_SI 20
F_SCK_EC 30
F_SDI_EC 3 0
+12VSUS
+3VSUS 4,20,21,22,23,24,25,26 ,30,31,41,51,53,62,74,81,92
+3VA 2 4,30,31,36,53,57,67,81,88,93
+12VSUS 49,81,91
PCH SMBus
B B
+12VSUS
2
G
SMB1_CLK30,74 SML1_CLK 20
A A
EC
GPU
5
4
6 1
S
D
Q2802A
UM6K1NG1DTN
Rdson=13Ohm/Vgs(th)=1.5V
N/A
3 4
UM6K1NG1DTN
5
D
Q2802B
N/A
PCH
G
S
3
SML1_DAT 20SMB1_DAT30,74
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1-HW RD
BG1-HW RD
BG1-HW RD
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
2
Date: Sheet of
HE4EA
HE4EA
HE4EA
Engineer:
Engineer:
Engineer:
1
Title :
PCH(9)_SPI_SMB
PCH(9)_SPI_SMB
PCH(9)_SPI_SMB
Kai_Shen
Kai_Shen
Kai_Shen
28 94Friday, April 07, 2017
28 94Friday, April 07, 2017
28 94Friday, April 07, 2017
Rev
Rev
Rev
1.0
1.0
1.0
of
5
D D
4
3
2
1
C C
B B
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
HE4EA 1.0
HE4EA 1.0
HE4EA 1.0
29 94Wednesday, March 29, 2017
29 94Wednesday, March 29, 2017
29 94Wednesday, March 29, 2017
2
1