Acer Spin 3 SP315-51 Schematic
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SYSTEM PAGE REF.
01. Block Diagram
02. GPIO Setting
03. CPU(1)_DDI/eDP
04. CPU(2)_DDR4
05. CPU(3)_+VCCCORE
06. CPU(4)_+VCCGT
07. CPU(5)_+VDDQ/IO/SA
08. CPU(6)_CPU GND
D D
09. CPU(7)_CFG/RSVD
13. TYPE-C (CC)
14. TYPE-C (MUX + Redriver)
16. LPDDR3(1)_MEMORY DOWN
17. LPDDR3(2)_MEMORY DOWN
18. LPDDR3(3)_CA/DQ Voltage
20. PCH(1)_SPI/LPC
21. PCH(2)_ISH
22. PCH(3)_HDA/SDIO
23. PCH(4)_USB/PCIE/SATA
24. PCH(5)_CLK/RTC
25. PCH(6)_POWER MANAGEMENT
26. PCH(7)_POWER
28. PCH(9)_SPI/SMB
30. EC_IT8587/FX
31. EC_IT8587E/FX_KB/TP/KBBL
32. RST_Reset Circuit
36. ALC255_Combo Jack,SPK,DMIC
37. xxx AUDIO HP/MIC JACK
40. xxx CB_RTS5170_GR
44. Debug CONN
45. CRT(1)_eDP,CAMERA,TSN
48. HDMI OUT
50. THERMAL / FAN
C C
51. NGFF PCIE/SATA SSD x2
52. USB 3.0/Sleep Charge IC
53. NGFF PCIE WLAN/BT
55. xxx CAMERA
56. xxx LED
57. Discharge
58. SHB_Sensor Hub
60. DC_DC/BAT CONN
62 TPM NPCT650
64. IO Board
65. ME_CONN / Skew Hole
68. BYPASS EC SEQUENCE
69. Power Switch
80_POWER_VCORE for U22
81_POWER_SYSTEM
82_POWER_+1.0VSUS
83_POWER_ DDR & VTT_UMA
84_POWER_ 1.8VSUS
85_POWER_XXX
86_POWER_XXX
87_POWER_XXX
88_POWER_CHARGER
89_POWER_AC_PD_WC Input
90_POWER_DETECT
B B
91_POWER_LOAD SWITCH
92_POWER_PROTECT
93_POWER_SIGNAL
94_POWER_FLOWCHART
97. System History
A01. Power On Sequence
A02. Power On Timing
B01. LED Board/LED, Hall Sensor
B02. IO Board/CB, USB2, Key
B03. Sensor Board/G-SEN,DMIC
ST5DB for Skylake U Platform Block Diagram
PANEL
Page 45
HDMI
Page 48 Page 48
SPEAKER X 2
Page 37
COMBO JACK
Page 37
DMIC X 1
Page 45
Card reader
RTS5229
Page 40
NGFF SSD
Page 51
HDD
Page 51
DEBUG CONN.
Page 44
TPM
NUVOTON/NPCT650
Page 62 Page 58
KB
Page 31
Click Pad
Page 31
FAN
Page 50
HDMI Repeater
PS8201
Audio Codec
REALTEK/ ALC255
EC
IT8987E/BX
SPI ROM
Page 36
Page 30
eDP
DDI
HDA
PCIE
PCIE
SATA
SATA
LPC
SPI
INTEL
Skylake U
TDP 15W
Page 3~9Page 28
Page 20~26
CHB
CHA
PCIE
USB 2.0
USB 3.0
USB 2.0
I2C
DDR4 SO-DIMM x1
DDR4 Memory Down x4
Power
+VCORE
+VCCGT
+VCCSA
Page 15~18
NGFF
WLAN / BT
Page 53
USB 3.0 Conn
W/charger
Page 52
Webcam
Page 45
USB2.0 Conn
Page_A02
USB2.0 Conn
Page_A02
Touch Screen
Page 61
Fingerprinter
Page 31
Sensor Hub G-sensor
System (5V & 3.3V)
+1.0VSUS & DDR(2.5V)
VCCPRIM_CORE
DDR & VTT
+1.8VSUS
+1.5VS
BATTERY CHARGER
POWER_DETECT
LOAD SWITCH
Power Protect
I2C
G-sensor
LED BRD
LED BRD
Page 80
Page 81
Page 82
Page 83
Page 84
Page 85
Page 88
Page 90
Page 91
Page 92
Page 59
Page_A04
Page A01
Page A03
A A
Discharge Circuit
Reset Circuit
5
4
3
Page 57
Page 32
DC & BATT. Conn.
Page 60
Skew Holes
2
Page 65
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
Title :
Block Diagram
Block Diagram
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Block Diagram
Jack_Lee
Jack_Lee
Jack_Lee
1 110Monday, July 18, 2016
1 110Monday, July 18, 2016
1 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
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D D
C C
4
3
2
1
B B
A A
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
<Title>
<Title>
<Title>
Size Project Name
ST5DB 1.0
C
Size Project Name
ST5DB 1.0
C
Size Project Name
ST5DB 1.0
C
5
4
3
2
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title :
Engineer:
Engineer:
Engineer:
1
Rev
Rev
Rev
2 110Monday, July 18, 2016
2 110Monday, July 18, 2016
2 110Monday, July 18, 2016
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D D
R1.0 0407B
DDI Port 1: HDMI
C C
12
H_THRMTRIP#32
B B
+VCCIO
12
R0311
1KOhm
H_PROCHOT# H_PROCHOT#_R
R0312
1KOhm
R0314 499Ohm1%
R0301 24.9Ohm1%
1 2
DDI1_TXN247
DDI1_TXP247
DDI1_TXN147
DDI1_TXP147
DDI1_TXN047
DDI1_TXP047
DDI1_CLKN47
DDI1_CLKP47
12
RF requirement
RF requirement
H_PECI_EC30
12
C0301
10PF/50V
@
DP_COMP
TP_CATERR#_R
12
C0302
10PF/50V
@
R0315 43Ohm
SP0301
1 2
R0316 49.9Ohm1%
1 2
R0317 49.9Ohm1%
1 2
R0318 49.9Ohm1%
1 2
R0319 49.9Ohm1%
DDPB_CTRLCLK47
DDPB_CTRLDATA47
4
SKYLAKE-U symbol ReV0.53 #545316 / Ballout_Rev0_71 #543787 / PEGA local PN is 4201-0062000
U0301A
E55
1 2
1 2
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22
N12
GPP_E23
E52
eDP_RCOMP
940432
01V010000015
+VCCST_CPU+VCCSTG+VCCST_CPU
12
R0313
49.9Ohm
1%
@
1
T0310
1
T0315
1
T0313
1
T0314
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
DDI
DISPLAY SIDEBANDS
TP_CATERR#_R
H_PECI
H_THRMTRIP#_R
SKTOCC#
PCB_ID28
CPU_GP2
CPU_GP3
AT16
AU16
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
H66
H65
EDP
U0301D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
940432
01V010000015
EDP_DISP_UTIL
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
eDP_BKLTEN
eDP_BKLTCTL
eDP_VDDEN
CPU MISC
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
RSVD_1
RSVD_2
JTAG
3
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
EDP_DISP_UTIL_S
G50
F50
E48
F48
G46
F46
L9
L7
VGA_HPD_PCH
L6
EXT_SMI#_R EXT_SMI#
N9
L10
R12
R11
U13
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
R0302 0Ohm
EXT_SCI#_R EXT_SCI#
R0303 0Ohm
eDP_HPD
B61
PROC_TCK
D60
PROC_TDI
A61
PROC_TDO
C60
PROC_TMS
B59
B56
D59
A56
C59
C61
A59
JTAGX
1 2
1 2
XDP_TCLK
XDP_TDI_CPU
XDP_TDO_CPU
XDP_TMS_CPU
XDP_TRST_CPU_N
PCH_JTAG_TCLK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST_CPU_N
XDP_TCLK_JTAGX
1
T0305
1
T0321
R1.0 0407B
1
R1.0 0406
T0319
2
EDP_TXN0 45
EDP_TXP0 45
EDP_TXN1 45
EDP_TXP1 45
EDP_AUXN 45
EDP_AUXP 45
DDI1_HPD 47
EXT_SMI# 30,44
EXT_SCI# 30
eDP_HPD 45
LCD_BKLTEN_PCH 21,45
LCD_BL_PWM_PCH 45
EDP_VDD_EN 45
PCH_JTAG_TMS XDP_TMS_CPU
eDP x 2
XDP_TDO_CPUPCH_JTAG_TDO
XDP_TRST_CPU_NPCH_TRST_CPU_N
XDP_TDI_CPUPCH_JTAG_TDI
XDP_TCLKXDP_TCLK_JTAGX
+VCCIO
+VCCST_CPU
+VCCSTG
DDPB_CTRLDATA has pull high at connector side
DDPB_CTRLDATA
DDPB_CTRLCLK
EXT_SCI#
EXT_SMI#
Pull down at connector side
R0323 51Ohm
R0324 51Ohm
+3VS
12
12
+VCCIO 7,57,65,91
+VCCST_CPU 5,7,9,25,32,65
+VCCSTG 5,7
+3VS 4,17,20,21,22,23,24,28,30,31,32,36,40,44,45,47,50,51,53,57,58,59,61,62,65,91,92
1 2
R0304 2.2KOhm@
1 2
R0338 2.2KOhm@
1 2
R0307 10KOhm
1 2
R0308 10KOhm
+VCCSTG
1
T0316
1
T0317
1
T0318
R1.0 0401A
Modify to XDP less
1
+3VS
DDPB_CTRLDATA
DDPC_CTRLDATA
DDPD_CTRLDATA
- Internal weak pull down 20k ohm
- 0 : port is not detected
1 : port is deteccted
+3VS
R1.0 0401A
THRO_CPU30
A A
PROCHOT#88
VR_HOT#80
1
1
G
2
S
Q0301
2N7002
5
R0341由EC control
(depends on under-shoot measurement result),預預0ohm
3
32
R0341 0Ohm
D
SP0325 0Ohm
R0320 0Ohm@
觸觸觸觸觸觸觸觸觸觸觸觸觸
12
H_PROCHOT#
12
12
70-200 ohm
觸是是是是
4
CPU(1)_DDI/eDP
CPU(1)_DDI/eDP
CPU(1)_DDI/eDP
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
3 110Monday, July 18, 2016
3 110Monday, July 18, 2016
3 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
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4
3
2
+1.2V
+3VSUS
+3VS
+1.2V 7,15,16,1 7,18,57,65 ,83
+3VSUS 24,25, 26,28,30,3 1,51,53,62 ,65,68,81,9 2
+3VS 3,17,20,21 ,22,23,24,2 8,30,31,32 ,36,40,44, 45,47,50,5 1,53,57,58 ,59,61,62,6 5,91,92
1
1
M_A_A[16 :0] 15,16
M_A_DQS# [7:0] 16
M_A_DQS[ 7:0] 16
M_A_DIM0_ CLK#0 15,16
M_A_DIM0_ CLK0 15,16
M_A_DIM0_ CKE0 15,16
M_A_DIM0_ CS#0 15,16
M_A_DIM0_ ODT0 15,16
M_A_BG0 15,16
M_A_BG1 15,16
M_A_BA0 15,16
M_A_BA1 15,16
M_A_ALE RT# 15,16
M_A_PAR 15,16
T0401
DIMM1_VRE F_DQ 1 8,65
DIMM0_VRE F_CA 18
M_A_ACT# 15,16
U0301C
IL Channel B[0..63]
AF65
M_B_D0
M_B_D1
M_B_D2
M_B_D3
M_B_D4
M_B_D5
M_B_D6
M_B_D7
M_B_D8
M_B_D9
M_B_D10
M_B_D11
M_B_D12
M_B_D13
M_B_D14
NIL Channel A[16..31]NIL Channel A[48..63]NIL Channel B[16..31]NIL Channel B[48..63]
M_B_D15
M_B_D16
M_B_D17
M_B_D18
M_B_D19
M_B_D20
M_B_D21
M_B_D22
M_B_D23
M_B_D24
M_B_D25
M_B_D26
M_B_D27
M_B_D28
M_B_D29
M_B_D30
M_B_D31
M_B_D32
M_B_D33
M_B_D34
M_B_D35
M_B_D36
M_B_D37
M_B_D38
M_B_D39
M_B_D40
M_B_D41
M_B_D42
M_B_D43
M_B_D44
M_B_D45
M_B_D46
M_B_D47
M_B_D48
M_B_D49
M_B_D50
M_B_D51
M_B_D52
M_B_D53
M_B_D54
M_B_D55
M_B_D56
M_B_D57
M_B_D58
M_B_D59
M_B_D60
M_B_D61
M_B_D62
M_B_D63
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
940432
SKL_ULT
NIL Channel A[16..31]
NIL Channel A[48..63]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
NIL Channel B[16..31]
NIL Channel B[48..63]
IL Channel B DQS[0..7]
NIL Channel A
DQS[2,3,6,7]
NIL Channel B
DQS[2,3,6,7]
DDR CH - B
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
D D
M_A_D[63 :0]16 M_B_D[63 :0]1 7
C C
B B
M_A_D0
M_A_D1
M_A_D2
M_A_D3
M_A_D4
M_A_D5
M_A_D6
M_A_D7
M_A_D8
M_A_D9
M_A_D10
M_A_D11
M_A_D12
M_A_D13
M_A_D14
NIL Channel A[0..15]NIL Channel A[32..47]NIL Channel B[0..15]NIL Channel B[32..47]
M_A_D15
M_A_D16
M_A_D17
M_A_D18
M_A_D19
M_A_D20
M_A_D21
M_A_D22
M_A_D23
M_A_D24
M_A_D25
M_A_D26
M_A_D27
M_A_D28
M_A_D29
M_A_D30
M_A_D31
M_A_D32
M_A_D33
M_A_D34
M_A_D35
M_A_D36
M_A_D37
M_A_D38
M_A_D39
M_A_D40
M_A_D41
M_A_D42
M_A_D43
M_A_D44
M_A_D45
M_A_D46
M_A_D47
M_A_D48
M_A_D49
M_A_D50
M_A_D51
M_A_D52
M_A_D53
M_A_D54
M_A_D55
M_A_D56
M_A_D57
M_A_D58
M_A_D59
M_A_D60
M_A_D61
M_A_D62
M_A_D63
U0301B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
940432
IL Channel A[0..63]
NIL Channel A[0..15]
NIL Channel A[32..47]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
NIL Channel B[0..15]
NIL Channel B[32..47]
IL Channel A DQS[0..7]
NIL Channel A
DQS[0,1,4,5]
NIL Channel B
DQS[0,1,4,5]
DDR CH - A
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26
AW50
AT52
AY67
AY68
BA67
AW67
M_A_A5
M_A_A9
M_A_A6
M_A_A8
M_A_A7
M_A_A12
M_A_A11
M_A_A13
M_A_A15
M_A_A14
M_A_A16
M_A_A2
M_A_A10
M_A_A1
M_A_A0
M_A_A3
M_A_A4
M_A_DQS# 0
M_A_DQS0
M_A_DQS# 1
M_A_DQS1
M_A_DQS# 2
M_A_DQS2
M_A_DQS# 3
M_A_DQS3
M_A_DQS# 4
M_A_DQS4
M_A_DQS# 5
M_A_DQS5
M_A_DQS# 6
M_A_DQS6
M_A_DQS# 7
M_A_DQS7
DDR0_VREF_ DQ
DDR_PG_CTRL _S
M_B_DIM0_ CLK#1
M_B_DIM0_ CLK1
M_B_DQS# 0
M_B_DQS0
M_B_DQS# 1
M_B_DQS1
M_B_DQS# 2
M_B_DQS2
M_B_DQS# 3
M_B_DQS3
M_B_DQS# 4
M_B_DQS4
M_B_DQS# 5
M_B_DQS5
M_B_DQS# 6
M_B_DQS6
M_B_DQS# 7
M_B_DQS7
CPUDRAMRST#
SM_RCOMP_ 0
SM_RCOMP_ 1
SM_RCOMP_ 2
M_B_A[16 :0] 17
M_B_DQS# [7:0] 17
M_B_DQS[ 7:0] 17
M_B_A5
M_B_A9
M_B_A6
M_B_A8
M_B_A7
M_B_A12
M_B_A11
M_B_A13
M_B_A15
M_B_A14
M_B_A16
M_B_A2
M_B_A10
M_B_A1
M_B_A0
M_B_A3
M_B_A4
1 2
R0402 121O HM1%
1 2
R0403 80.6 Ohm1%
1 2
R0404 100O hm1%
M_B_DIM0_ CLK#0 17
M_B_DIM0_ CLK#1 17
M_B_DIM0_ CLK0 17
M_B_DIM0_ CLK1 17
M_B_DIM0_ CKE0 17
M_B_DIM0_ CKE1 17
M_B_DIM0_ CS#0 17
M_B_DIM0_ CS#1 17
M_B_DIM0_ ODT0 17
M_B_DIM0_ ODT1 17
M_B_BG0 17
M_B_ACT# 17
M_B_BG1 17
M_B_BA0 17
M_B_BA1 17
M_B_ALE RT# 17
M_B_PAR 17
+1.2V
12
R0405
470Ohm
R0401
0Ohm
1 2
@
1 2
C0402
0.1UF/16V
DDR4_DRAMRS T# 16,17
If Mixed SO-DIMM and Memory Down,
RCOMP[0] should be 121 Ohm.
+1.2V +3VS +3VSUS
R0407
220KOhm
1%
R0411
2MOHM
@
12
R0408
220KOhm
1%@
DDR_VTT_CNTL to VTT power ready < 35us (tCPU18)
2
DDR_PG_CTRL 8 3
CPU(2)_DDR3L
CPU(2)_DDR3L
CPU(2)_DDR3L
Title :
Title :
1
Title :
Engineer:
Engineer:
Engineer:
Jack_Lee
Jack_Lee
Jack_Lee
4 110Monday, July 18, 2016
4 110Monday, July 18, 2016
4 110Monday, July 18, 2016
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW 3
BG1/HW 3
BG1/HW 3
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
ST5DB
ST5DB
Date: Sheet of
Date: Sheet of
Date: Sheet of
ST5DB
Rev
Rev
Rev
1.0
1.0
1.0
C0401
0.1UF/16V
U0401
1
NC
A
GND
74AUP1G 07GW
VCC
Y
2
3 4
A A
5
4
1 2
5
3
12
12
Vinafix.com
RF requirement
+VCORE
12
C0510
10PF/50V
@
12
5
C0511
2.2UF/6.3V
@
12
C0512
10PF/50V
@
12
C0513
2.2UF/6.3V
@
4
3
2
+VCORE
+VCCST_CPU
+VCCSTG
1
+VCCSTG 3,7+VCORE 57,80
+VCCST_CPU 3,7,9,25,32,65
D D
C C
RF requirement RF requirement
+VCORE +VCORE
12
C0514
10PF/50V
@
12
C0515
10PF/50V
@
SKL 2+2, +V1.8VS_EDRAM / +V_EDRAM_VR / +V_EOPIO_VR
From Intel, SKL-U 2+2 reserve these pins PD to GND
1 2
R0528 0Ohm@
R0529 0Ohm@
1 2
R0530 0Ohm@
1 2
12
C0501
10PF/50V
@
R0535 0Ohm@
R0531 0Ohm@
R0532 0Ohm@
R0533 0Ohm@
R0534 0Ohm@
RSVD NC
12
C0502
10PF/50V
@
T0503
T0502
1 2
1 2
1 2
1 2
1 2
+VCORE +VCORE
12
C0503
10PF/50V
@
1
SNN_RSVD53
1
SNN_RSVD54
32ARF requirement
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
AK32
AB62
AC63
AE63
AE62
AG62
AL63
AJ62
A30
A34
A39
A44
G30
K32
P62
V62
H63
G61
U0301L
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
RSVD_3
RSVD_4
VCCOPC_1
VCCOPC_2
VCCOPC_3
VCC_OPC_1P8_1
VCC_OPC_1P8_2
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO_1
VCCEOPIO_2
VCCEOPIO_SENSE
VSSEOPIO_SENSE
940432
01V010000015
CPU POWER 1 OF 4
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
RF requirement
12
C0504
10PF/50V
@
Pull H/L at power side
VIDALERT#
VIDSCK
VIDSOUT
+VCCFUSEPRG
SP0505
NB_R0402_20MIL_SMALL
12
C0506
10PF/50V
@
VCORE_VCCSENSE 80
VCORE_VSSSENSE 80
1 2
R0517 220Ohm1%
1 2
R0518 0Ohm
1 2
R0519 0Ohm
+VCCSTG
1 2
12
C0507
10PF/50V
@
CPU side VR side
+VCCST_CPU
12
R0520
56Ohm
1%
+VCCST_CPU
12
R0521
100Ohm
1%
VIDALERT#_R
VIDSCK_R
VIDSOUT_R
VCORE_VCCSENSE
VCORE_VSSSENSE
+VCCST_CPU
12
+VCCST_CPU
12
R0522
45.3Ohm
1%
R0523
100Ohm
1%
+VCORE
1 2
R0524 0Ohm
RF requirement
12
12
C0505
1UF/10V
1 2
R0525 51Ohm1%
RF requirement
12
1 2
R0526 10Ohm1%
R0540
100Ohm
1%
1 2
R0541
100Ohm
1%
1 2
C0508
10PF/50V
@
C0509
10PF/50V
@
VR_SVID_ALERT# 80
VR_SVID_CLK 80
VR_SVID_DATA 80
B B
A A
CPU(3)_+VCCCORE
CPU(3)_+VCCCORE
CPU(3)_+VCCCORE
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
5 110Monday, July 18, 2016
5 110Monday, July 18, 2016
5 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
4
3
2
1
+VCCGT
D D
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCCGT
57A
1 2
R0601 0Ohm@
1 2
R0608 0Ohm@
1 2
R0604 0Ohm@
1 2
R0605 0Ohm@
1 2
R0606 0Ohm@
1 2
R0607 0Ohm@
1 2
R0602 0Ohm@
1 2
R0603 0Ohm@
From Intel, SKL-U 2+2 reserve these pins PD to GND
+VCCGT
RF requirement
+VCCGT
12
12
12
C0604
C0601
10PF/50V
2.2UF/6.3V
@
@
C C
VCCGT_VCCSENSE80
VCCGT_VSSSENSE80
B B
C0602
10PF/50V
@
R0611
100Ohm
R0610
100Ohm
+VCCGT
1%
1%
1 2
1 2
12
C0603
2.2UF/6.3V
@
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
U0301M
CPU POWER 2 OF 4
VCCGT_1
VCCGT_2
VCCGT_3
VCCGT_4
VCCGT_5
VCCGT_6
VCCGT_7
VCCGT_8
VCCGT_9
VCCGT_10
VCCGT_11
VCCGT_12
VCCGT_13
VCCGT_14
VCCGT_15
VCCGT_16
VCCGT_17
VCCGT_18
VCCGT_19
VCCGT_20
VCCGT_21
VCCGT_22
VCCGT_23
VCCGT_24
VCCGT_25
VCCGT_26
VCCGT_27
VCCGT_28
VCCGT_29
VCCGT_30
VCCGT_31
VCCGT_32
VCCGT_33
VCCGT_34
VCCGT_35
VCCGT_36
VCCGT_37
VCCGT_38
VCCGT_39
VCCGT_40
VCCGT_41
VCCGT_42
VCCGT_43
VCCGT_44
VCCGT_45
VCCGT_46
VCCGT_47
VCCGT_48
VCCGT_49
VCCGT_50
VCCGT_51
VCCGT_52
VCCGT_53
VCCGT_54
VCCGT_55
VCCGT_SENSE
VSSGT_SENSE
940432
01V010000015
VCCGT_56
VCCGT_57
VCCGT_58
VCCGT_59
VCCGT_60
VCCGT_61
VCCGT_62
VCCGT_63
VCCGT_64
VCCGT_65
VCCGT_66
VCCGT_67
VCCGT_68
VCCGT_69
VCCGT_70
VCCGT_71
VCCGT_72
VCCGT_73
VCCGT_74
VCCGT_75
VCCGT_76
VCCGT_77
VCCGT_78
VCCGT_79
VCCGT_80
VccGTx_1
VccGTx_2
VccGTx_3
VccGTx_4
VccGTx_5
VccGTx_6
VccGTx_7
VccGTx_8
VccGTx_9
VccGTx_10
VccGTx_11
VccGTx_12
VccGTx_13
VccGTx_14
VccGTx_15
VccGTx_16
VccGTx_17
VccGTx_18
VccGTx_19
VccGTx_20
VccGTx_21
VccGTx_22
VccGTx_23
VccGTx_24
VccGTx_25
VccGTx_26
VccGTx_27
VccGTx_28
VccGTx_29
VCCGTx_SENSE
VSSGTx_SENSE
+VCCGT 57,65,80
A A
CPU(4)_+VCCGT
CPU(4)_+VCCGT
CPU(4)_+VCCGT
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
6 110Monday, July 18, 2016
6 110Monday, July 18, 2016
6 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
D D
12
12
C0729
10PF/50V
@
C0730
10PF/50V
@
R1.1 0526
12
C0701
10UF/6.3V
12
C0702
10UF/6.3V
12
C0703
10UF/6.3V
12
+1.2V
RF requirement
RF requirement
+1.2V
C C
+1.2V
12
12
12
C0727
10PF/50V
@
C0732
10PF/50V
@
C0735
2.2UF/6.3V
@
12
12
12
C0728
10PF/50V
@
C0731
10PF/50V
@
C0736
10PF/50V
@
C0704
10UF/6.3V
+1.2V
4
12
12
C0705
C0706
10UF/6.3V
10UF/6.3V
R1.1 0526
1 2
R0701 0Ohm
+VCCST_CPU
+VCCSTG
+VCCSFR_OC
C0701 - C0704 : Near by package
C0705 - C0710 : Underneath the package
12
12
12
12
C0712
1UF/6.3V
C0713
1UF/6.3V
C0714
0.1UF/16V
12
+VDDQ_CPU_CLK
C0708
C0707
1UF/6.3V
1UF/6.3V
Decoupling cap for internal power
12
C0711
0.1UF/16V
12
C0709
1UF/6.3V
12
C0710
1UF/6.3V
3
U0301N
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
AL23
A18
A22
K20
K21
CPU POWER 3 OF 4
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQC
VCCST
VCCSTG
VCCPLL_OC
VccPLL_1
VccPLL_2
940432
01V010000015
VCCIO_1
VCCIO_2
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCSA_1
VCCSA_2
VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6
VCCSA_7
VCCSA_8
VCCSA_9
VCCSA_10
VCCSA_11
VCCSA_12
VCCSA_13
VCCSA_14
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
0.06A
0.02A
0.12A
2.8A
0.13A
+VCCST_CPU
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
+1.2V
+VCCSTG
+VCCIO
+VCCSA
3.1A
VCCIO_VR_FB
VSSIO_VR_FB
+1.0V
5.1A
R1.1 0526
R0721
100Ohm
1%
1 2
2
+1.2V 4,15,16,17,18,57,65,83
+1.0V 57,91
+VCCST_CPU 3,5,9,25,32,65
+VCCSTG 3,5
+VCCIO 3,57,65,91
+VCCSA 57,80
12
C0717
1UF/6.3V
+VCCSA
R0720
100Ohm
1%
1 2
12
C0718
1UF/6.3V
RF requirement
12
C0724
10PF/50V
@
VCCSA_VSSSENSE 80
VCCSA_VCCSENSE 80
12
C0719
1UF/6.3V
12
+VCCIO
C0725
10PF/50V
@
12
C0720
1UF/6.3V
RF requirement
12
C0726
10PF/50V
@
12
C0721
10PF/50V
@
+VCCSA
+VCCIO
12
12
12
R0714
1KOhm
@
R0715
1KOhm
@
C0722
10PF/50V
@
1
12
C0723
10PF/50V
@
Reserved PH/PD
RF requirement
+VCCSA
12
C0733
10PF/50V
@
+VCCSFR
12
12
B B
A A
5
4
C0715
0.1UF/16V
C0716
0.1UF/16V
+1.0V
+1.0V +VCCSFR
+VCCIO
3
R1.0 0412
1 2
R0710 0Ohm
R1.0 0412
1 2
R0711 0Ohm
R1.0 0412
1 2
R0713 0Ohm
+VCCST_CPU
0.24A0.24A
0.24A0.24A
+VCCSTG
0.12A0.12A
RF
requirement
+VCCST_CPU
12
C0734
10PF/50V
@
R1.0 0412
1 2
R0709 0Ohm
+VCCSFR_OC+1.2V
2
Refer to CRB 0.53
CPU(5)_+VDDQ/IO/SA
CPU(5)_+VDDQ/IO/SA
CPU(5)_+VDDQ/IO/SA
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
7 110Monday, July 18, 2016
7 110Monday, July 18, 2016
7 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
D D
4
3
2
1
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW60
AW62
AW64
AW66
AY66
BA10
BA14
BA18
BA23
BA28
BA32
BA36
BA45
AV1
AW6
AW8
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA2
F68
U0301Q
GND 2 OF 3
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
940432
01V010000015
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
U0301P
GND 1 OF 3
A5
VSS_1
A67
VSS_2
A70
VSS_3
AA2
VSS_4
AA4
VSS_5
AA65
VSS_6
AA68
VSS_7
AB15
VSS_8
AB16
VSS_9
AB18
VSS_10
AB21
VSS_11
AB8
VSS_12
AD13
VSS_13
AD16
VSS_14
AD19
VSS_15
AD20
VSS_16
AD21
VSS_17
AD62
VSS_18
AD8
VSS_19
AE64
VSS_20
AE65
VSS_21
AE66
VSS_22
C C
B B
AE67
AE68
AE69
AF10
AF15
AF17
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
AF1
AF2
AF4
AH6
AJ4
AK8
AL2
AL4
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
940432
01V010000015
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
F8
G10
G22
G43
G45
G48
G5
G52
G55
G58
G6
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42
J8
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
U0301R
GND 3 OF 3
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
940432
01V010000015
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
A A
CPU(6)_CPU GND
CPU(6)_CPU GND
CPU(6)_CPU GND
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
8 110Monday, July 18, 2016
8 110Monday, July 18, 2016
8 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
D D
C C
12
R0931 1KOhm
B B
CFG3
@
4
Intel confirm NC
T0966
T0967
T0903
T0904
R0930 1KOhm
T0905
T0907
T0906
T0968
T0969
T0970
T0910
T0912
T0913
T0915
T0914
T0916
T0921
T0919
T0922
T0923
T0924
T0917
T0918
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 2
R0901 49.9Ohm1%
1
1
1
1
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP
SNN_RSVD_TP_BA70
SNN_RSVD_TP_BA68
RSVD_VSS_F65
RSVD_VSS_G65
3
U0301S
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_TP_1
RSVD_TP_2
RSVD_17
RSVD_18
VSS_360
VSS_361
RSVD_19
RSVD_20
940432
01V010000015
RESERVED SIGNALS-1
RSVD_TP_3
RSVD_TP_4
RSVD_TP_5
RSVD_TP_6
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
RSVD_28
RSVD_29
RSVD_30
RSVD_31
RSVD_32
RSVD_33
RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38
RSVD_39
RSVD_40
RSVD_41
RSVD_42
VSS_362
ZVM#
RSVD_TP_7
RSVD_TP_8
MSM#
PROC_SELECT#
TP5
TP6
TP4
TP1
TP2
AL25
AL27
BA70
BA68
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
2
SNN_RSVD_TP_BB68
SNN_RSVD_TP_BB69
RSVD_AY3
VSS_AY71
SKL_CNL#
T0925
1
T0926
1
R0902 0Ohm
1 2
R0903 0Ohm
1
1 2
+VCCST_CPU 3,5,7,25,32,65
+1.8VSUS 24,26,84
+VCCST_CPU
1 2
+VCCST_CPU
+1.8VSUS
R0904 100KOhm@
Intel confirm this pin is pulled high to +VCCST_CPU for SKL
U0301T
R1.0 0412
+1.8VSUS
A A
5
PDG 1.2
Placeholder only. Does not need to be stuffed.
Placement are required for future platform compatibility purpose only.
4
1 2
R0910 0Ohm@
1 2
R0911 0Ohm@
VCC_1P8_U12
VCC_1P8_U11
12
C0901
@
0.1UF/25V
@
12
C0902
0.1UF/25V
AW69
AW68
AU56
AW48
C7
U12
U11
H11
RSVD_43
RSVD_44
RSVD_45
RSVD_46
RSVD_47
RSVD_48
RSVD_49
RSVD_50
940432
01V010000015
SPARE
3
RSVD_51
RSVD_52
RSVD_53
RSVD_54
RSVD_55
RSVD_56
RSVD_57
RSVD_58
F6
E3
C11
B11
A11
D12
C12
F52
CPU(7)_CFG/RSVD
CPU(7)_CFG/RSVD
CPU(7)_CFG/RSVD
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
9 110Monday, July 18, 2016
9 110Monday, July 18, 2016
9 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
D D
C C
4
3
2
1
B B
A A
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENT IAL
PEGATRON PROPRIETARY AND CONFIDENT IAL
PEGATRON PROPRIETARY AND CONFIDENT IAL
<Title>
<Title>
<Title>
Engineer:
Engineer:
Engineer:
Size Project Name
ST5DB
Custom
Size Project Name
ST5DB
Custom
Size Project Name
ST5DB
Custom
10 110Monday, July 18, 2016
10 110Monday, July 18, 2016
10 110Monday, July 18, 2016
Date: Sh eet of
Date: Sh eet of
5
4
3
2
1
Date: Sh eet of
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
D D
C C
4
3
2
1
B B
A A
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
<Title>
<Title>
<Title>
Size Project Name
ST5DB 1.0
C
Size Project Name
ST5DB 1.0
C
Size Project Name
ST5DB 1.0
C
5
4
3
2
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title :
Engineer:
Engineer:
Engineer:
1
Rev
Rev
Rev
11 110Monday, July 18, 2016
11 110Monday, July 18, 2016
11 110Monday, July 18, 2016
Vinafix.com
5
D D
C C
4
3
2
1
B B
A A
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
<Title>
<Title>
<Title>
Size Project Name
ST5DB 1.0
C
Size Project Name
ST5DB 1.0
C
Size Project Name
ST5DB 1.0
C
5
4
3
2
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title :
Engineer:
Engineer:
Engineer:
1
Rev
Rev
Rev
12 110Monday, July 18, 2016
12 110Monday, July 18, 2016
12 110Monday, July 18, 2016
Vinafix.com
5
D D
C C
4
3
2
1
B B
A A
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
<Title>
<Title>
<Title>
Size Project Name
ST5DB 1.0
C
Size Project Name
ST5DB 1.0
C
Size Project Name
ST5DB 1.0
C
5
4
3
2
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title :
Engineer:
Engineer:
Engineer:
1
Rev
Rev
Rev
13 110Monday, July 18, 2016
13 110Monday, July 18, 2016
13 110Monday, July 18, 2016
Vinafix.com
5
D D
C C
4
3
2
1
B B
A A
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
<Title>
<Title>
<Title>
Size Project Name
ST5DB 1.0
C
Size Project Name
ST5DB 1.0
C
Size Project Name
ST5DB 1.0
C
5
4
3
2
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title :
Engineer:
Engineer:
Engineer:
1
Rev
Rev
Rev
14 110Monday, July 18, 2016
14 110Monday, July 18, 2016
14 110Monday, July 18, 2016
Vinafix.com
5
4
3
2
1
12
C1505
1UF/6.3V
X5R/10%
vx_c0402_small
12
C1547
10PF/50V
@
+0.6VS
+1.2V
12
vx_c0402_small
DDR4(0)_Termination
D D
+0.6VS
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C C
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R150134.8Ohm 1%
R150234.8Ohm 1%
R150334.8Ohm 1%
R150434.8Ohm 1%
R150534.8Ohm 1%
R150634.8Ohm 1%
R150734.8Ohm 1%
R150834.8Ohm 1%
R150934.8Ohm 1%
R151034.8Ohm 1%
R151134.8Ohm 1%
R151234.8Ohm 1%
R151334.8Ohm 1%
R151434.8Ohm 1%
R151534.8Ohm 1%
R151634.8Ohm 1%
R152934.8Ohm 1%
M0_MA0
M0_MA1
M0_MA2
M0_MA3
M0_MA4
M0_MA5
M0_MA6
M0_MA7
M0_MA8
M0_MA9
M_A_A10_AP
M0_MA11
M0_MA12
M0_MA13
M_A_A14_WE_N
M_A_A15_CAS_N
M_A_A16_RAS_N
M_A_A0 4,16
M_A_A1 4,16
M_A_A2 4,16
M_A_A3 4,16
M_A_A4 4,16
M_A_A5 4,16
M_A_A6 4,16
M_A_A7 4,16
M_A_A8 4,16
M_A_A9 4,16
M_A_A10 4,16
M_A_A11 4,16
M_A_A12 4,16
M_A_A13 4,16
M_A_A14 4,16
M_A_A15 4,16
M_A_A16 4,16
M_A_DIM0_CS#04,16
M_A_DIM0_CKE04,16
M_A_BG04,16
M_A_BG14,16
M_A_BA04,16
M_A_BA14,16
M_A_DIM0_ODT04,16
M_A_ACT#4, 16
M_A_PAR4,16
M_A_DIM0_CLK#04,16
M_A_DIM0_CLK04,16
M_A_ALERT#4,16
R1523 34.8Ohm1%
R1538 34.8Ohm1%
R1524 34.8Ohm1%
R1525 34.8Ohm1%
R1530 34.8Ohm1%
R1532 34.8Ohm1%
R1534 34.8Ohm1%
R1521 34.8Ohm1%
R1522 34.8Ohm1%
R1536 36Ohm5%
R1537 36Ohm5%
R1535 49.9Ohm1%
vx_r0402_small
1 2
1 2
vx_r0402_small
vx_r0402_small
vx_r0402_small
@
vx_r0402_small
vx_r0402_small
vx_r0402_small
vx_r0402_small
vx_r0402_small
vx_r0402_small
1 2
vx_r0402_small
1 2
vx_r0402_small
1 2
+0.6VS
+0.6VS
12
12
12
12
12
12
12
+0.6VS
+1.2V
Average placed close to +VDDQ_VTT power plane
+0.6VS
12
C1501
1UF/6.3V
X5R/10%
vx_c0402_small
+0.6VS
12
C1509
10UF/6.3V
X5R/20%
vx_c0603_small
12
vx_c0402_small
vx_c0603_small
C1502
1UF/6.3V
X5R/10%
12
C1510
10UF/6.3V
X5R/20%
12
C1053
1UF/6.3V
X5R/10%
vx_c0402_small
12
RF requirement
C1545
10PF/50V
@
12
C1504
1UF/6.3V
X5R/10%
vx_c0402_small
12
C1546
10PF/50V
@
C1506
1UF/6.3V
X5R/10%
+0.6VS 17,57,83
+1.2V 4,7,16, 17,18,57,65,83
12
12
C1507
1UF/6.3V
X5R/10%
vx_c0402_small
vx_c0402_small
C1508
1UF/6.3V
X5R/10%
RF requirement
12
C1542
10PF/50V
@
12
C1543
10PF/50V
@
12
C1544
10PF/50V
@
B B
A A
DDR4(1)_Termination
DDR4(1)_Termination
DDR4(1)_Termination
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
15 110Monday, July 18, 2016
15 110Monday, July 18, 2016
15 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
+1.2V
12
1UF/6.3V
C1630
12
C1615
12
12
C1606
C1602
1UF/6.3V
1UF/6.3V
Close to U1601
M_A_DIM0_CS#04,15
M_A_DIM0_ODT04,15
M_A_DIM0_CKE04,15
M_A_DIM0_CLK04,15
M_A_DIM0_CLK#04,15
M_A_ALERT#4,15
+1.2V
+1.2V
12
12
C1616
1UF/6.3V
Close to U1603
+1.2V
5
M_A_ACT#4,15
M_A_BA04,15
M_A_BA14,15
M_A_BG04,15
M_A_PAR4,15
M_A_DQS#04
M_A_DQS#14
1UF/6.3V
M_A_DQS#44
M_A_DQS#54
12
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VPP_1
VPP_2
VREFCA
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VPP_1
VPP_2
VREFCA
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
ZQ
TEN
NC
ZQ
TEN
NC
+1.2V
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B1
R9
M1
1 2
F9
R1601 240Ohm
N9
T7
R1624 0Ohm@
B2
E1
E9
MEM1_E9
G8
K1
K9
M9
MEM1_M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
+1.2V
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B1
R9
M1
F9
1 2
R1605 240Ohm
N9
T7
R1627 0Ohm@
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
+2P5VPP
MEM3_E9
MEM3_M9
U1601
DDR4
256M x 16 (4Gbit)
P3
M_A_A0
A0
P7
M_A_A1
A1
R3
M_A_A2
A2
N7
M_A_A3
A3
N3
M_A_A4
A4
P8
M_A_A5
A5
P2
M_A_A6
A6
R8
M_A_A7
A7
R2
M_A_A8
A8
R7
M_A_A9
A9
M3
M_A_A10
A10/AP
T2
M_A_A11
A11
M7
M_A_A12
A12/BC_n
T8
M_A_A13
A13
L2
M_A_A14
WE_n/A14
M8
M_A_A15
CAS_n/A15
L8
M_A_A16
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
M_A_D0
M_A_D7
M_A_D1
M_A_D2
M_A_D4
M_A_D6
M_A_D5
M_A_D3
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_D32
M_A_D38
M_A_D33
M_A_D39
M_A_D36
M_A_D35
M_A_D37
M_A_D34
ALERT_n
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
E7
DML_N/DBIL_N
G3
DQSL_t
F3
DQSL_c
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
E2
DMU_N/DBIU_N
B7
DQSU_t
A7
DQSU_c
P1
RESET_n
K4A8G165WB-BCPB
U1603
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC_n
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
E7
DML_N/DBIL_N
G3
DQSL_t
F3
DQSL_c
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
E2
DMU_N/DBIU_N
B7
DQSU_t
A7
DQSU_c
P1
RESET_n
K4A8G165WB-BCPB
DDR4
256M x 16 (4Gbit)
R1.0 0422 Swap
M_A_DQS04
M_A_DQS14
DDR4_DRAMRST#4,17
C1618
M_A_DQS44
M_A_DQS54
R1.0 0422 Swap
M_A_D8
M_A_D10
M_A_D12
M_A_D11
M_A_D9
M_A_D14
M_A_D13
M_A_D15
12
M_A_ACT#
M_A_BA0
M_A_BA1
M_A_BG0
M_A_PAR
M_A_DIM0_CS#0
M_A_DIM0_ODT0
M_A_DIM0_CKE0
M_A_DIM0_CLK0
M_A_DIM0_CLK#0
M_A_ALERT#
R1.0 0422 Swap
R1.0 0422 Swap R1.0 0422 Swap
M_A_D43
M_A_D46
M_A_D44
M_A_D42
M_A_D45
M_A_D47
M_A_D40
M_A_D41
12
C1609
C1612
1UF/6.3V
1UF/6.3V
+2P5VPP
12
C1629
C1623
1UF/6.3V
1UF/6.3V
1UF/6.3V
C1617
C1625
1UF/6.3V
RF requirement
12
C1690
10PF/50V
@
RF requirement
12
C1691
10PF/50V
@
+1.2V
12
+2P5VPP
12
1UF/6.3V
D D
C C
B B
A A
4
RF requirement
12
12
C1686
C1687
10PF/50V
10PF/50V
@
@
RF requirement
12
12
C1689
C1688
10PF/50V
10PF/50V
@
@
+V_VREF_CA_DIMM0
12
MEM1_E9
MEM1_E9
MEM1_M9
R1609 0Ohm
MEM1_M9
R1617 0Ohm
+2P5VPP
+V_VREF_CA_DIMM0
12
MEM3_E9
MEM3_E9
MEM3_M9 M_A_BG1
MEM3_M9
4
12
C1665
0.047UF/10V
1AV200000049
@
1 2
R1608 240Ohm
R1616 0Ohm
Colay
@
12
12
12
C1666
0.047UF/10V
1AV200000049
1 2
R1614 240Ohm@
R1620 0Ohm
Colay
12
R1615 0Ohm@
12
R1621 0Ohm
M_A_A[16:0] 4,15
M_A_D[63:0] 4
RF requirement
12
M_A_BG1 4,15
12
RF requirement
+1.2V
12
C1696
10PF/50V
@
+1.2V
12
C1697
10PF/50V
@
+1.2V
3
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VPP_1
VPP_2
VREFCA
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VPP_1
VPP_2
VREFCA
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
ZQ
TEN
NC
ZQ
TEN
NC
+1.2V
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B1
R9
M1
F9
1 2
R1603 240Ohm
N9
T7
R1625 0Ohm@
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
+1.2V
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B1
R9
M1
1 2
F9
R1607 240Ohm
N9
T7
R1626 0Ohm@
B2
E1
E9
MEM4_E9
G8
K1
K9
M9
MEM4_M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
RF requirement
12
+2P5VPP
MEM2_E9
MEM2_M9
C1692
10PF/50V
@
RF requirement
12
C1694
10PF/50V
@
12
+2P5VPP
12
U1602
DDR4
256M x 16 (4Gbit)
P3
M_A_A0
A0
P7
M_A_A1
A1
R3
M_A_A2
A2
N7
M_A_A3
A3
N3
M_A_A4
A4
P8
M_A_A5
A5
P2
M_A_A6
A6
R8
M_A_A7
A7
R2
M_A_A8
A8
R7
M_A_A9
A9
M3
M_A_A10
A10/AP
T2
M_A_A11
A11
M7
M_A_A12
A12/BC_n
T8
M_A_A13
A13
L2
M_A_A14
WE_n/A14
M8
M_A_A15
CAS_n/A15
L8
M_A_A16
RAS_n/A16
L3
M_A_ACT#
M_A_BA0
M_A_BA1
M_A_BG0
M_A_PAR
M_A_DIM0_CS#0
M_A_DIM0_ODT0
M_A_DIM0_CKE0
M_A_DIM0_CLK0
M_A_DIM0_CLK#0
M_A_ALERT#
R1.0 0422 Swap
M_A_DQS24
M_A_DQS#24
M_A_DQS34
M_A_DQS#34
M_A_DQS64
M_A_DQS#64
M_A_DQS74
M_A_DQS#74
R1.0 0422 Swap
M_A_D28
M_A_D27
M_A_D29
M_A_D26
M_A_D24
M_A_D30
M_A_D25
M_A_D31
DDR4_DRAMRST#
M_A_ACT#
M_A_BA0
M_A_BA1
M_A_BG0
M_A_PAR
M_A_DIM0_CS#0
M_A_DIM0_ODT0
M_A_DIM0_CKE0
M_A_DIM0_CLK0
M_A_DIM0_CLK#0
M_A_ALERT#
R1.0 0422 Swap
M_A_D56
M_A_D57
M_A_D59
M_A_D58
M_A_D62
M_A_D61
M_A_D63
M_A_D60
DDR4_DRAMRST#DDR4_DRAMRST#
3
M_A_D16
M_A_D23
M_A_D17
M_A_D18
M_A_D21
M_A_D19
M_A_D20
M_A_D22
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16M_A_A16
M_A_D49
M_A_D54
M_A_D52
M_A_D55
M_A_D48
M_A_D51
M_A_D53
M_A_D50
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
E7
DML_N/DBIL_N
G3
DQSL_t
F3
DQSL_c
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
E2
DMU_N/DBIU_N
B7
DQSU_t
A7
DQSU_c
P1
RESET_n
K4A8G165WB-BCPB
U1604
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC_n
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
L3
ACT_n
N2
BA0
N8
BA1
M2
BG0
T3
PAR
L7
CS_n
K3
ODT
K2
CKE
K7
CK_t
K8
CK_c
P9
ALERT_n
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
E7
DML_N/DBIL_N
G3
DQSL_t
F3
DQSL_c
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
E2
DMU_N/DBIU_N
B7
DQSU_t
A7
DQSU_c
P1
RESET_n
K4A8G165WB-BCPB
DDR4
256M x 16 (4Gbit)
2
+1.2V
12
C1611
1UF/6.3V
1UF/6.3V
12
C1693
10PF/50V
@
12
C1695
10PF/50V
@
+V_VREF_CA_DIMM0
12
MEM2_E9
MEM2_E9
+2P5VPP
12
C1628
1UF/6.3V
C1664
0.047UF/10V
1AV200000049
1 2
R1610 240Ohm@
R1618 0Ohm
Colay
MEM2_M9 M_A_BG1
MEM2_M9
+V_VREF_CA_DIMM0
MEM4_E9
MEM4_E9
12
R1611 0Ohm@
12
R1619 0Ohm
12
C1667
0.047UF/10V
1AV200000049
1 2
R1612 240Ohm@
R1622 0Ohm
12
Colay
MEM4_M9 M_A_BG1
MEM4_M9
12
R1613 0Ohm@
12
R1623 0Ohm
2
C1601
1UF/6.3V
12
C1627
1UF/6.3V
1UF/6.3V
12
12
+1.2V
C1621
+2P5VPP
C1626
12
C1604
1UF/6.3V
Close to U1602
12
C1619
1UF/6.3V
12
12
C1624
1UF/6.3V
1UF/6.3V
12
C1613
1UF/6.3V
C1620
12
+1.2V
+2P5VPP
12
12
C1622
1UF/6.3V
Close to U1604
10UF/6.3V
10UF/6.3V
1
+V_VREF_CA_DIMM0
12
C1633
10UF/6.3V
12
C1614
10UF/6.3V
12
12
C1605
C1607
10UF/6.3V
10UF/6.3V
12
12
C1631
C1632
10UF/6.3V
Around the DRAM devices
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
1
+2P5VPP
C1608
+1.2V
ST5DB
ST5DB
ST5DB
12
+V_VREF_CA_DIMM0 18
C1610
10UF/6.3V
Engineer:
Engineer:
Engineer:
+1.2V 4,7,15,17,18,57,65,83
+2P5VPP 17,57,65,82
12
DDR4(1)_MEMORY DOWN
DDR4(1)_MEMORY DOWN
DDR4(1)_MEMORY DOWN
Title :
Title :
Title :
Jack_Lee
Jack_Lee
Jack_Lee
16 110Monday, July 18, 2016
16 110Monday, July 18, 2016
16 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
of
Vinafix.com
5
4
3
2
1
+0.6VS
+0.6VS
10UF/6.3V
+2P5VPP
C1719
+1.2V
+2P5VPP
12
C1748
10UF/6.3V
STD
J1701A
M_B_A[0. .16]4
D D
M_B_BA14
M_B_BA04
M_B_BG14
M_B_BG04
M_B_DIM0_ CLK14
M_B_DIM0_ CLK#14
M_B_DIM0_ CLK04
M_B_DIM0_ CLK#04
M_B_DIM0_ CS#14
M_B_DIM0_ CS#04
C C
+1.2V
+1.2V
R1708
240Ohm
1 2
C1757 10PF/50V@
12
B B
1%
R1702
@
0Ohm
1 2
1 2
R1705
0Ohm
1 2
1 2
R1703
@
0Ohm
@
R1706
0Ohm
SMB_DAT_S28
SMB_CLK_ S28
+V_VREF_C A_DIMM1
12
C1713
0.1UF/16V
R1704
0Ohm
1 2
12
R1707
0Ohm
1 2
R1.0 0422B
R1.0 0422B
12
C1714
2.2UF/6.3 V
@
M_B_DIM0_ CKE14
M_B_DIM0_ CKE04
M_B_DIM0_ ODT14
M_B_DIM0_ ODT04
1 2
R1711 240Ohm 1%
1 2
R1712 240Ohm 1%
1 2
R1713 240Ohm 1%
1 2
R1714 240Ohm 1%
1 2
R1715 240Ohm 1%
1 2
R1716 240Ohm 1%
1 2
R1717 240Ohm 1%
1 2
R1718 240Ohm 1%
DDR4_DRAMRS T#4,16
M_B_ALE RT#4
+2P5_3V S_DIM
12
C1754
C1755
2.2UF/6.3 V
0.1UF/16V
1 2
SP1701
1 2
SP1702
M_B_PAR4
M_B_ACT#4
V_SA2_D IMM0_CHB
V_SA1_D IMM0_CHB
V_SA0_D IMM0_CHB
12
C1756
10PF/50V
@
SMB_DAT_S_ CHB
SMB_CLK_ S_CHB
+V_VREF_C A_DIMM1
M_B_A16
M_B_A15
M_B_A14
M_B_A13
M_B_A12
M_B_A11
M_B_A10
M_B_A9
M_B_A8
M_B_A7
M_B_A6
M_B_A5
M_B_A4
M_B_A3
M_B_A2
M_B_A1
M_B_A0
T1701
T1702
@
12
C1743
0.1UF/16V
152
156
151
158
119
120
146
121
125
122
127
126
128
131
132
133
144
145
150
113
115
138
140
137
139
165
1
162
1
157
149
110
109
161
155
104
100
105
101
143
108
134
116
114
255
166
260
256
254
253
164
87
88
91
92
DDR4_SO_ 260P
R1.0 0427 R1.0 0427
246
M_B_D60
DQ63
245
M_B_D63
RAS_n/A16
CAS_n/A15
WE_n/A14
A13
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA0
BG1
BG0
CK1_t/NF
CK1_c/NF
CK0_t
CK0_c
C1/CS3_n/NC
C0/CS2_n/NC
CS1_n
CS0_n
CKE1
CKE0
ODT1
ODT0
CB7/NC
CB6/NC
CB5/NC
CB4/NC
CB3/NC
CB2/NC
CB1/NC
CB0/NC
PARITY
RESET_n
EVENT_n/NF
ALERT_n
ACT_n
VDDSPD
SA2
SA1
SA0
SDA
SCL
VREFCA
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DM8_n/DBI_n/NC
DM7_n/DBI7_n
DM6_n/DBI6_n
DM5_n/DBI5_n
DM4_n/DBI4_n
DM3_n/DBI3_n
DM2_n/DBI2_n
DM1_n/DBI_n
DM0_n/DBI0_n
DQS8_t
DQS8_c
DQS7_t
DQS7_c
DQS6_t
DQS6_c
DQS5_t
DQS5_c
DQS4_t
DQS4_c
DQS3_t
DQS3_c
DQS2_t
DQS2_c
DQS1_t
DQS1_c
DQS0_t
DQS0_c
233
M_B_D59
232
M_B_D57
250
M_B_D61
249
M_B_D62
236
M_B_D56
237
M_B_D58
225
M_B_D51
224
M_B_D55
212
M_B_D53
211
M_B_D48
229
M_B_D50
228
M_B_D54
215
M_B_D49
216
M_B_D52
204
M_B_D44
203
M_B_D47
190
M_B_D40
191
M_B_D43
208
M_B_D45
207
M_B_D46
194
M_B_D41
195
M_B_D42
182
M_B_D39
183
M_B_D35
169
M_B_D32
170
M_B_D33
186
M_B_D34
187
M_B_D38
173
M_B_D36
174
M_B_D37
80
M_B_D26
79
M_B_D31
67
M_B_D28
66
M_B_D24
84
M_B_D27
83
M_B_D30
71
M_B_D29
70
M_B_D25
59
M_B_D18
58
M_B_D23
45
M_B_D21
46
M_B_D20
63
M_B_D22
62
M_B_D19
49
M_B_D16
50
M_B_D17
37
M_B_D6
38
M_B_D7
25
M_B_D0
24
M_B_D4
42
M_B_D2
41
M_B_D3
29
M_B_D1
DQ9
28
M_B_D5
DQ8
17
M_B_D14
DQ7
16
M_B_D11
DQ6
3
M_B_D8
DQ5
4
M_B_D13
DQ4
21
M_B_D10
DQ3
20
M_B_D15
DQ2
7
M_B_D9
DQ1
8
M_B_D12
DQ0
+1.2V
96
241
220
199
178
75
54
33
12
R1.0 0422A
97
R1.0 0422A
95
242
M_B_DQS7
240
M_B_DQS# 7
221
M_B_DQS6
219
M_B_DQS# 6
200
M_B_DQS5
198
M_B_DQS# 5
179
M_B_DQS4
177
M_B_DQS# 4
76
M_B_DQS3
74
M_B_DQS# 3
55
M_B_DQS2
53
M_B_DQS# 2
34
M_B_DQS0
32
M_B_DQS# 0
13
M_B_DQS1
11
M_B_DQS# 1
M_B_D[0.. 63] 4
7:56~63
6:48~55
5:40~47
4:32~39
R1.0 0422 Swap
R1.0 0422 Swap
R1.0 0422 Swap
R1.0 0422 Swap
3:24~31
2:16~23
R1.0 0422 Swap
0:0~7
R1.0 0422 Swap
1:8~15
1 2
R1709 240Ohm 1%
1 2
R1710 240Ohm 1%
M_B_DQS7 4
M_B_DQS# 7 4
M_B_DQS6 4
M_B_DQS# 6 4
M_B_DQS5 4
M_B_DQS# 5 4
M_B_DQS4 4
M_B_DQS# 4 4
M_B_DQS3 4
M_B_DQS# 3 4
M_B_DQS2 4
M_B_DQS# 2 4
M_B_DQS0 4
M_B_DQS# 0 4
M_B_DQS1 4
M_B_DQS# 1 4
+V_VREF_C A_DIMM1
+1.2V
C1730
1UF/6.3V
12
+0.6VS 15,57,8 3
+1.2V 4,7,15,16 ,18,57,65, 83
+2P5VPP 16,57,65 ,82
+V_VREF_C A_DIMM1 18
12
12
C1729
1UF/6.3V
12
C1751
C1702
1UF/6.3V
10PF/50V
+1.2V
C1734
10UF/6.3V
C1735
10UF/6.3V
C1701
10PF/50V
@
@
12
12
12
12
C1733
10UF/6.3V
C1738
10UF/6.3V
12
12
C1736
10UF/6.3V
C1737
10UF/6.3V
+1.2V +2P5VPP+0.6VS
12
C1704
10UF/6.3V
12
C1703
10UF/6.3V
J1701B
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
141
VDD11
142
VDD12
147
VDD13
148
VDD14
153
VDD15
154
VDD16
159
VDD17
160
VDD18
163
VDD19
1
VSS1
2
VSS2
5
VSS3
6
VSS4
9
VSS5
10
VSS6
14
VSS7
15
VSS8
18
VSS9
19
VSS10
22
VSS11
23
VSS12
26
VSS13
27
VSS14
30
VSS15
31
VSS16
35
VSS17
36
VSS18
39
VSS19
40
VSS20
43
VSS21
44
VSS22
47
VSS23
48
VSS24
51
VSS25
52
VSS26
56
VSS27
57
VSS28
60
VSS29
61
VSS30
64
VSS31
65
VSS32
68
VSS33
69
VSS34
72
VSS35
73
VSS36
77
VSS37
78
VSS38
81
VSS39
82
VSS40
85
VSS41
86
VSS42
89
VSS43
90
VSS44
93
VSS45
94
VSS46
98
VSS47
DDR4_SO_ 260P
12
12
C1708
1UF/6.3V
12
C1715
1UF/6.3V
12
C1707
1UF/6.3V
12
12
C1710
1UF/6.3V
VPP2
VPP1
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
SIDE2
SIDE1
NP_NC2
NP_NC1
1UF/6.3V
1UF/6.3V
VTT
C1706
C1716
258
259
257
99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252
264
263
262
261
12
12
C1705
1UF/6.3V
12
12
C1712
1UF/6.3V
R1.0 0428
1 2
4
R1719 0Ohm
1 2
R1720 0Ohm@
A A
5
+2P5_3V S_DIM+3VS+2P5V PP
<Variant Name>
<Variant Name>
<Variant Name>
DDR4(1)_SO-DIMM
DDR4(1)_SO-DIMM
DDR4(1)_SO-DIMM
Title :
Title :
ST5DB
ST5DB
ST5DB
1
Title :
Engineer:
Engineer:
Engineer:
Jack_Lee
Jack_Lee
Jack_Lee
17 110Monday, July 18, 20 16
17 110Monday, July 18, 20 16
17 110Monday, July 18, 20 16
Rev
Rev
Rev
1.0
1.0
1.0
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW 3
BG1/HW 3
BG1/HW 3
Size Project Name
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Custom
Custom
Date: Sheet of
Date: Sheet of
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2
Date: Sheet of
Vinafix.com
5
DDR4(3)_CA/DQ Voltage
DDR4(3)_CA/DQ Voltage
DDR4(3)_CA/DQ Voltage
4
3
2
1
M3: CPU driven VREF path is stuffed be default.
M1: VREF_DQ driven by a Voltage Divider Network during Processor power-off
D D
DIMM0_VREF_C A4
12
C1804
0.022UF/16V
12
R1818
24.9Ohm
1%
C C
M3
R1822 2.7O hm
12
10V2200004 34
12
C1802
0.1UF/16V
+1.2V
10V2200003 16
1 2
10V2200003 16
1 2
+V_VREF_CA_DIM M0
RF requirement
+V_VREF_CA_DIM M0
R1810
1.8KOhm
R1809
1.8KOhm
12
C1809
10PF/50V
@
+1.2V
+V_VREF_CA_DIM M0
+V_VREF_CA_DIM M1
+1.2V 4,7,15,1 6,17,57,65,83
+V_VREF_CA_DIM M0 16
+V_VREF_CA_DIM M1 17
M1
M3
+V_VREF_CA_DIM M1
DIMM1_VREF_D Q4,65
12
B B
12
R1823 2Ohm
C1806
0.022UF/16V
R1820
24.9Ohm
1%
12
+1.2V
R1807
1KOhm
10V2200000 02
1 2
12
C1801
0.1UF/16V
R1808
1KOhm
10V2200000 02
1 2
M1
RF
requirement
A A
DIMM1_VREF_D Q
12
C1807
10PF/50V
@
5
12
C1808
10PF/50V
@
<Variant Nam e>
<Variant Nam e>
<Variant Nam e>
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Na me
Size Project Na me
Size Project Na me
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
ST5DB
ST5DB
ST5DB
Title :
Engineer:
Engineer:
Engineer:
1
Jack_Lee
Jack_Lee
Jack_Lee
18 110Monday, July 1 8, 2016
18 110Monday, July 1 8, 2016
18 110Monday, July 1 8, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
4
3
2
1
20
RF requirement
12
SPI_CLK_R SML1_CLK_R
12
C2003
10PF/50V
@
near AV2 near W3
AW13
AY11
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
SPI_CLK_R
SPI_SO
SPI_SI
SPI_WP#_IO2
SPI_HOLD#_IO3
SPI_CS#0
1
SPI_CS1#
1
SPI_CS2#
1
GPP_D1
1
GPP_D0
CL_CLK
CL_DATA
CL_RST#
RCIN#
INT_SERIRQ
CL_CLK53
CL_DATA53
CL_RST#53
RCIN#30
INT_SERIRQ30,44,62
R2015 0Ohm
12
C2004
10PF/50V
@
T2011
T2001
T2002
T2007
SPI_CLK28
D D
SPI_SO28
SPI_SI28
SPI_WP#_IO228
SPI_HOLD#_IO328,44
SPI_CS#028
C C
PCH(1)_SPI/LPC
U0301E
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
940432
01V010000015
LPC
SMBUS, SMLINK
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
SMB_CLK
SMB_DAT
SMBALERT#
SML0_CLK_NFC
SML0_DAT_NFC
SML0ALERT#
SML1_CLK_R
SML1_DAT
SML1ALERT#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PM_SUS_STAT#
CLK_KBCPCI_PCH_R
CLK_LPC1
PM_CLKRUN#
1
1
1
1
+3VSUS_ORG
T2008
T2003
T2004
T2010
+3VS
+3VSUS_ORG 21,22,23,25,26
+3VS 3,4,17,21,22,23,24,28,30,31,32,36,40,44,45, 47,50,51,53,57,58,59,61,62,65,91,92
RF requirement
C2005
10PF/50V
@
12
12
C2002
10PF/50V
@
SMB_CLK 28
SMB_DAT 28
SODIMM
PDG Reserve For NFC
1 2
1 2
1 2
To EC
SML1_DAT 28
LPC_AD0 30,44,62
LPC_AD1 30,44,62
LPC_AD2 30,44,62
LPC_AD3 30,44,62
LPC_FRAME# 30,44,62
PM_SUS_STAT# 62
R2001 22Ohm 1%
R2002 22Ohm 1%/Debug
R2014 22Ohm 1%@
PM_CLKRUN# 30,62
R2016 0Ohm
12
TPM
R1.1 0603B
12
C2001
10PF/50V
@
12
C2006
10PF/50V
@
CLK_KBCPCI_PCH 30
CLK_DEBUG 44
LPCCLK_TPM 62
SML1_CLK 28
Unmount R2013,R2009
Vendor Suggest Pull High Resistor Need To Close To TPM
B B
1 2
R2004 20KOhm@
1 2
R2006 20KOhm@
1 2
R2008 20KOhm@
A A
5
SML0ALERT#
1 2
R2003 2.2KOhm
CRB 0.53 reserve 150k ohm
1 2
R2005 4.7KOhm@
CRB 0.53 reserve 150k ohm
1 2
R2007 4.7KOhm@
4
+3VSUS_ORG
+3VSUS_ORG
+3VSUS_ORG
BBS 21
SMBALERT# - Internal weak pull down 20k ohm
TLS Confidentiality
0 : Disable (default)
1 : Enable
SML0ALERT# - Internal weak pull down 20 kohm
0 : LPC EC (default)
1 : eSPI EC
BBS - Internal weak pull down 20k ohm
Boot BIOS Strap
0 : SPI destination (default)
1 : LPC destination
3
PM_CLKRUN#, INT_SERIRQ Need To Pull 10Kohm To+3VS at Chipset Side
+3VS
PM_CLKRUN#
INT_SERIRQSMBALERT#
R1.0 0428
SMB_DAT
SMB_CLK
SML1_CLK
SML1_DAT
SML1ALERT#
1 2
R2013 10KOhm
1 2
R2009 10KOhm
+3VSUS_ORG
3 4
RN2001B
2.2KOhm
1 2
RN2001A
2.2KOhm
3 4
RN2002B
2.2KOhm
1 2
RN2002A
2.2KOhm
1 2
R2012 150KOhm
MOW WW52
To enable Direct Connect Interface (DCI),
a 150K pull up resistor will need to be added to PCHHOT#
pin. This pin must be low during the rising edge of RSMRST#.
2
PCH(1)_SPI/LPC
PCH(1)_SPI/LPC
PCH(1)_SPI/LPC
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
20 110Monday, July 18, 2016
20 110Monday, July 18, 2016
20 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
Microsoft* Windows* 7 System WHCK Requirement – OEM platforms are
required to include a supported OS debug interface, accessible by an enduser.
This allows developers to help in driver debug. The supported
Windows 7 debug interfaces are EHCI, 1394 port and COM port.
With skylake EHCI Removal, Potential Gap with Windows* 7 Kernel Debug
and OS Installation – Mitigation Required
4
3
2
+3VSUS_ORG
+3VS
1
+3VS 3,4,17,20,22,23,24,28,30,31,32,36,40,44,45, 47,50,51,53,57,58,59,61,62,65,91,92
+3VSUS_ORG 20,22,23,25,26
R1.2 0706
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
+3VSUS_ORG
12
R2155
10KOhm
/KBL
12
R2156
10KOhm
/SKL
GND
R1.0 0330
GPP_D11
GPP_D12
ISH_I2C0_SDA
ISH_I2C0_SCL
GPP_F10
GPP_F11
TP_IRQ#
MBBD_ID_PCH
IOBD_ID_PCH
TCH_PNL_RPS#_PCH
PCB_ID0
PCB_ID1
MEM_ID3
PCB_ID3
R1.0 0422A
GPP_F5
CPU ID SKLKBL
1
T2151
1
T2152
1
T2148
1
T2147
1
T2153
R1.0 0422A
1
T2154
1 0
D D
U0301F
LPSS ISH
GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
940432
01V010000015
C 3.3V GPIO
F 1.8V GPIO
GPP_D9
GPP_D10
GPP_D11
D 3.3V GPIO
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
Sx_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
AH10
AH11
AH12
AF11
AF12
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
W4
AB3
AD1
AD2
AD3
AD4
U7
U6
U8
U9
AH9
MEM_ID0
MEM_ID1
MEM_ID2
C C
Boot BIOS Strap Bit (BBS)
BBS20
To implement UART for WIN7 WHCK requirement if need
Please refer to Intel document #548689 - RVP5
R1.0 0406
External SensorHub
Click PAD
B B
WLAN_ON_PCH53
BT_ON/OFF#_PCH53
PCH_I2C0_SDA58
PCH_I2C0_SCL58
PCH_I2C1_SDA31
PCH_I2C1_SCL31
1 2
R2102 0Ohm
R1.0 0401A
LCD_BKLTEN_PCH3,45
T2103
T2144
T2112
T2155
T2157
T2158
T2115
T2116
R1.0 0422A
R1.0 0422A
R1.0 0422A
1
1
1
1
1
1
1
1
GPP_B18
BBS_R
GPP_C8
GPP_C11
WLAN_ON_PCH
BT_ON/OFF#_PCH
GPP_C23
PCH_I2C0_SDA
PCH_I2C0_SCL
PCH_I2C1_SDA
PCH_I2C1_SCL
PCH_I2C2_SDA
PCB_ID3
PCH_I2C3_SDA
PCH_I2C3_SCL
GPP_F8
GPP_F9
Memory ID
+3VSUS_ORG +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG
12
12
A A
GND GND GND
R2104
10KOhm
@
R2105
10KOhm
R2106
10KOhm
PCB_ID0
PCB_ID1
12
R2107
10KOhm
@
R1.2 0620
12
R1.1 0607
12
R2108
10KOhm
N/A
12
R2109
10KOhm
N/A
GND
12
R2115
10KOhm
N/A
12
R2116
10KOhm
N/A
+3VSUS_ORG
SAMSUNG
K4A8G165WB-BCPB
12
12
GND
R2119
10KOhm
@
R2120
10KOhm
12
R2147
10KOhm
@
MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3
12
R2148
10KOhm
GND
2133MT 8Gb
SAMSUNG
K4A8G165WB-BCRC
2400MT 8Gb
MICRON
MT40A512M16JY-083E:B
2400MT 8Gb
SK HYNIX
H5AN8G6NAFR-UHC
2400MT 8Gb
MEM_ID3
(GPP_C15)
0
0
0
0
0
0
0
MEM_ID2
(GPP_B17)
0
0
0
0
10
1
1
1
MEM_ID1
(GPP_B16)
0
1
0 0
0
1
MEM_ID0
(GPP_B15)
00
1
0
11
1
0
11
PEGA P/N
0315-01HF0PB
0315-01C80PB
0315-01W90PB
0315-01W60PB
Reserved
Reserved
Reserved
Reserved
R1.2 0629
R1.0 0401A
+3VSUS_ORG
R1.0 0408
12
R2153
10KOhm
@
MBBD_ID_PCH
R1.0 0422A
12
R2154
10KOhm
GPP_D14
@
GND
TP_SENSOR_OFF# 31
R1.0 0408
TP_IRQ# 30,31
TCH_PNL_RPS#_PCH 61
OP_SD# 36
ISH_I2C0_SDA
ISH_I2C0_SCL
PCH_I2C0_SDA
PCH_I2C0_SCL
PCH_I2C1_SDA
PCH_I2C1_SCL
GPP_B18
GSPI0_MOSI / GPP_B18 - Internal weak pull down 20k ohm
0 : Disable No Reboot mode(default)
1 : Enable NO Reboot Enable mode
TBD DisableEnable
1 2
R2110 10KOhm@
1 2
R2111 10KOhm@
1 2
R2113 2.2KOhm
1 2
R2114 2.2KOhm
1 2
R2146 10KOhm@
1 2
R2145 10KOhm@
1 2
R2112 4.7KOhm@
1 2
R2122 4.7KOhm@
+3VSUS_ORG
Default is GPO, to reserve pull high to +3VSUS_ORG
1 0
+3VS
+3VS
+3VS
MB Version ID
PCB_ID1 PCB_ID0
(GPP_C14) (GPP_C13)
R1.0 0 0
R1.1 0 1
R1.2 1 0
R2.0 1 1
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Title :
Title :
PCH(2)_ISH
PCH(2)_ISH
PCH(2)_ISH
Jack_Lee
Jack_Lee
Jack_Lee
21 110Monday, July 18, 2016
21 110Monday, July 18, 2016
21 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
4
3
2
1
+VCCPAZIO
+3VS
D D
U0301G
1 2
HDA_SYNC36
HDA_BCLK36
HDA_SDO36
HDA_SDI036
HDA_RST#36
C C
B B
R1.0 0406
For Keyboard backlight Fn Key
KBBL_LV158
KBBL_LV058
HDA_SPKR36
KBBL_LV1
KBBL_LV0
R2211 33Ohm
1 2
R2212 33Ohm
1 2
R2213 33Ohm
1 2
R2214 33Ohm
1 2
R2217 33Ohm
T2227
T2228
GND
+VCCPAZIO
AU_I2S0_SYNC_R
AU_I2S0_BCLK_R
AU_I2S0_SDO_R
AU_I2S0_SDI0_R
1
HDA_SDI1
T2201
HDA_RST#_R
1
AU_I2S_MCLK_R
T2229
1
DMIC_CLK0_PC H_R
1
DMIC_DATA0_PCH_ R
1 2
R2202 20KOhm@
CRB 0.53 reserve 150k ohm
1 2
R2203 4.7KOhm@
BA22
AY22
BB22
BA21
AY21
AW22
AY20
AW20
AK7
AK6
AK9
AK10
AW5
HDA_SPKR
AU_I2S0_SDO_R
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
940432
01V01000001 5
R2209 4.7KOhm@
R2210 2.2KOhm@
AUDIO
1 2
1 2
+3VS
+3VSUS_ORG
SDIO/SDXC
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_A17/SD_PWR_EN#/ISH_GP7
SPKR - Internal weak pull down
0 : Disable TOP Swap mode (default)
1 : Enable Top Swap Enable
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
LID_STAT0#_C
LID_STAT1#_C
LID_STAT2#_C
KB_BL_INT#
SHB_RST#_C PU
MODE INT#_C
ESH_I2C_INT#
SKL_SD_RCOM P
R1.1 0512
Default is GPO, to reserve pull high to +3VSUS_ORG
12
D2201RB7 51V-40
PCH_FLASH_DES CRIPTOR 30
AU_I2S0_SDO_R - Internal weak pull down
FLASH DESCRIPTOR SECURITY OVERRRIDE
0 : Enable security measure defined in the Flash Descriptor
1 : Disable Flash Descriptor Security
+3VSUS_ORG
R1.0 0406
R2201 200Ohm1%
RTC_IN# 24
+VCCPAZIO 2 6
+3VS 3,4,17,20,21,2 3,24,28,30,31,32,36,40 ,44,45,47,50,51,53,57,58 ,59,61,62,65,91,92
+3VSUS_ORG 20,21,23 ,25,26
LID_STAT0#_C 58
LID_STAT1#_C 58
LID_STAT2#_C 58
KB_BL_INT# 58
SHB_RST#_C PU 58
MODE INT#_C 58
ESH_I2C_INT# 58
1 2
GND
A A
<Variant Name>
<Variant Name>
<Variant Name>
PCH(3)_HDA/SDIO
PCH(3)_HDA/SDIO
PCH(3)_HDA/SDIO
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
PEGATRON PROPRIETARY AND CONFIDENTIAL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sh eet of
Date: Sh eet of
5
4
3
2
Date: Sh eet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
22 110Monday, July 18, 2016
22 110Monday, July 18, 2016
22 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
D D
PCIE_RXN4_WLAN53
PCIE_RXP4_WLAN53
WLAN
HDD
R1.1 0608
C C
Card reader
PCIE_RCOMP PDG 0.9 need 100 ohm 0.1% / CRB 0.53 use 100 ohm +-1%
RF requirement
12
C2319
10PF/50V
@
SSD
R1.1 0608
PCIE_TXN4_WLAN53
PCIE_TXP4_WLAN53
SATA_RXN0_HDD51
SATA_RXP0_HDD51
SATA_TXN0_HDD51
SATA_TXP0_HDD51
PCIE_RXN_CR40
PCIE_RXP_CR40
PCIE_TXN_CR40
PCIE_TXP_CR40
+3VS
R2318 10KOhm
PCIE_RXN11_M2_SSD51
PCIE_RXP11_M2_SSD51
PCIE_TXN11_M2_SSD51
PCIE_TXP11_M2_SSD51
SATA_RXN12_M2_SSD51
SATA_RXP12_M2_SSD51
SATA_TXN12_M2_SSD51
SATA_TXP12_M2_SSD51
PCIE_RXN11_M2_SSD
PCIE_RXP11_M2_SSD
PCIE_TXN11_M2_SSD
PCIE_TXP11_M2_SSD
SATA_RXN12_M2_SSD
SATA_RXP12_M2_SSD
SATA_TXN12_M2_SSD
SATA_TXP12_M2_SSD
R1.0 0421B
12
4
C2309 0.1UF/16V
C2310 0.1UF/16V
1 2
R2301 100Ohm1%
T2323
T2324
1 2
1 2
1 2
1 2
C23170.1UF/16V
C23180.1UF/16V
1
PROC_PRDY#
1
PROV_PREQ#
PIRQA#
PCIE_TXN4_WLAN_C
PCIE_TXP4_WLAN_C
PCIE_TXN_CR_C
PCIE_TXP_CR_C
PCIE_RCOMPN
PCIE_RCOMPP
U0301H
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
940432
01V010000015
3
SSIC / USB3
USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
(OD)
GPP_E4/DEVSLP0
(OD)
GPP_E5/DEVSLP1
(OD)
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
2
R1.0 0330
R1.0 0406
USBCOMP
USB2_ID_OTG
USB2_VBUSSENSE_OTG
OC0#
OC1#
OC2#
NFC_IRQ_R
+3VSUS_ORG
+3VS
USB3_RXN1 52
USB3_RXP1 52
USB3_TXN1 52
USB3_TXP1 52
USB_PN1 52
USB_PP1 52
USB_PN2 66
USB_PP2 66
USB_PN3 66
USB_PP3 66
USB_PN5_BT 53
USB_PP5_BT 53
USB_PN6_FP 31
USB_PP6_FP 31
USB_PN7_CCD 45
USB_PP7_CCD 45
USB_PN9 61
USB_PP9 61
USB2_COMP PDG 1.0 R=113 +-1%
1 2
R2302 113Ohm1%
1 2
R2319 1KOhm
1 2
R2320 1KOhm
R1.2 0627
SSD_DEVSLP 51
SATA_SSD_PEDET 51
1
+3VSUS_ORG 20,21,22,25,26
+3VS 3,4,17,20,21,22,24,28,30,31,32,36,40,44,45, 47,50,51,53,57,58,59,61,62,65,91,92
USB30
USB30
USB20
USB20
Bluetooth
Fingerprinter
Camera
Touch
MOW 5.1.3 If the platform does not
GND
support Dual Role, then USB2_ID pin
GND
shall be connected directly to GND.
GND
5 6
RN2301C
10KOhm
1 2
RN2301A
10KOhm
7 8
RN2301D
10KOhm
3 4
RN2301B
10KOhm
R2321 0Ohm
R2322 0Ohm
R2310 0Ohm
1
T2325
1 2
1 2
1 2
+3VSUS_ORG
USB_OC0#_PCH 52
USB_OC1#_PCH 66
USB_OC2#_PCH 66
USB30
USB20
USB20
B B
Capture from 545659_545659_SKL_PCH_LP_EDS_Rev1_0_pub
Please refer the latest Doc.
A A
<Variant Name>
<Variant Name>
<Variant Name>
PCH(4)_USB/PCIE/SATA
PCH(4)_USB/PCIE/SATA
PCH(4)_USB/PCIE/SATA
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
23 110Monday, July 18, 2016
23 110Monday, July 18, 2016
23 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
D D
C C
CLK_REQ1#
CLK_REQ5#
RF requirement
12
C2408
10PF/50V
@
B B
CLK_PCIE_SSD#51
CLK_PCIE_SSD51
CLK_SSD_REQ#51
CLK_PCIE_WLAN#_PCH53
CLK_PCIE_WLAN_PCH53
CLK_REQ4_WLAN#53
CLK_PCIE_CR#_PCH40
CLK_PCIE_CR_PCH40
CLK_CR_REQ#40
SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
SRCCLKREQ#[5:0] (PDG v1.3 Page 835)SRCCLKREQ#[5:0] (PDG v1.3 Page 835)
Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any un-used, disabled, must be left as no connects at the PCH side on the platform.Any un-used, disabled, must be left as no connects at the PCH side on the platform.
Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.
Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.
Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.Any used, enabled, should connect to a PCIe* connector pin or a device down ball with a 10K Ohm ±10% external pull-up resistor to core rail.
CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)CLKOUT_PCIE_P/N[5:0] (PDG v1.3 Page420)
Any differential clock pair not being used must be left as no connect
Any differential clock pair not being used must be left as no connect
Any differential clock pair not being used must be left as no connectAny differential clock pair not being used must be left as no connect
2015.04.06 YenPin
Add CLOCK Buffer Schematic (CRB Page123)
A A
R2426~R2428 Close To U2401 SUSCLK is on the DSW well and is available
1 2
R2426 10KOhm
1 2
R2428 10KOhm
12
C2409
10PF/50V
@
SP2419
SP2420
SP2421
1 2
SP2412
1 2
SP2413
1 2
SP2414
SP2440
SP2441
SP2442
R1.0 0406
+3VS
+3VS
1
SNN_CLKOUT_PCIE_N0
T2401
1
SNN_CLKOUT_PCIE_N2
T2403
12
CLKOUT_PCIE_N1
12
CLKOUT_PCIE_P1
12
CLK_REQ1#
CLK_PCIE_WLAN#_PCH_R
CLK_PCIE_WLAN_PCH_R
CLK_REQ4_WLAN#_R
12
CLKOUT_PCIE_N5
12
CLKOUT_PCIE_P5
12
CLK_REQ5#
earlier in the boot sequence.
AR10
AT10
Remove SUSCLK
5
U0301I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
940432
01V010000015
U0301J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
940432
01V010000015
4
C37
CSI2_CLKN0
D37
CSI2_CLKP0
C32
CSI2_CLKN1
D32
CSI2_CLKP1
C29
CSI2_CLKN2
D29
CSI2_CLKP2
B26
CSI2_CLKN3
A26
CSI2_CLKP3
E13
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
CSI2_COMP
B7
GPP_D4
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
EMMC_RCOMP
3
1 2
R2418 100Ohm1%
1 2
R2419 200Ohm1%
2
+VCCF24NS_1P0
+VCC_RTC
+3VA
+3VS
+3VSUS
T2417
GND
GND
1
+VCCF24NS_1P0 26
+VCC_RTC 25,26,36,60
+3VA 30,31,36,53,56,57,65,81,88,93
+3VS 3,4,17,20,21,22,23,28,30,31,32,36,40,44,45, 47,50,51,53,57,58,59,61,62,65,91,92
+3VSUS 4,25,26,28,30,31,51,53,62,65,68,81,92
+3VA
R2423
1.5KOhm
1%
3.19V~3.18V VCCRTC is sourced from Vbatt in G3 or VCCDSW_3p3
R2424
45.3KOhm
1%
GND
1 2
R2405 1KOhm
+VCC_RTC
1 2
3
12
0.8V/0.2mA
C2407
1UF/6.3V
Use two in one package diode for cost reduction
Make sure +RTC BAT Voltage lower than +RTC AC
GND
R2420
1KOhm
D2401
R2425
0Ohm
R1.1 0607
+RTC_AC
@
1
2
+RTC_BAT
1
in Non-G3 state, platform designers must ensure the
effective voltage at VCCRTC does not exceed 3.2V.
+RTCBAT
J2401
3
SIDE1
1
1
2
2
4
SIDE2
WTOB_CON_2P
12V17GISM024
GND
R1.0 0331
1 2
C2401 10PF/50V
5%
1 2
C2402 10PF/50V
5%
1 2
C2403 15PF/50V
1 2
C2404 15PF/50V
1 2
R2407
10KOhm
CLOCK SIGNALS
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
SUSCLK_PCH
XTAL_24M_IN
XTAL_24M_OUT
XCLK_BIASREF
XTAL_32K_X1
XTAL_32K_X2
SRTC_RST#
RTC_RST#
1
T2404
PDG 0.9 - 2.7k +-1%
1 2
R2417 2.7KOhm
1 2
R2422 60.4Ohm@
+VCCF24NS_1P0
GND
12
R2401
1MOhm
1 2
NB_R0402_5MIL_SMALL
1 2
NB_R0402_5MIL_SMALL
12
R2402
10MOhm
SW_RTCRST30
SP2401
SP2402
13
X2401
24MHZ
XTAL_24M_OUT_R
XTAL_32K_X1_R
X2402
32.768KHZ
1 2
07V080000064
2p_3.3*1.6*0.9_ESR 50K
R2406 0Ohm
2
4
R1.1 0603
RTC Detect
1 2
R2427 10KOhm
CLK_REQ4_WLAN#_R
4
1 2
R2408 10KOhm@
1 2
R2411 10KOhm
@
+3VSUS
+3VS
GND
3
+RTCBAT +1.8VSUS
1 2
@
32
3
Q2402
2N7002
1
1
R2439
10MOhm
G
2
@
12
@
GND
R2438
100KOhm
D
S
RTC_IN# 22
2
Q2401
2N7002
12
GND
GND
GND
GND
GND
32
3
D
1
1
G
S
2
GND
1
JRST2402
1
SGL_JUMP
2
@
2
GNDGND
1
JRST2401
1
SGL_JUMP
2
@
2
GND GND
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
ST5DB
ST5DB
ST5DB
1 2
R2403 20KOhm
12
C2405
1UF/6.3V
1 2
R2404 20KOhm
12
C2406
1UF/6.3V
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
+VCC_RTC
PCH(5)_CLK
PCH(5)_CLK
PCH(5)_CLK
Jack_Lee
Jack_Lee
Jack_Lee
24 110Monday, July 18, 2016
24 110Monday, July 18, 2016
24 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
4
3
2
1
+3VSUS_ORG
+VCC_RTC
+VCCDSW
+VCCST_CPU
+3VSUS
D D
+3VSUS_ORG
12
R2501
10KOhm
PLT_RST#
PM_RSMRST#30
ALL_SYS_PWRGD delay 99 ms from EC
DSW function / non-AMT
C C
U2501
@
1
5
A
VCC
PLT_RST#
12
C2502
100PF/50V
B B
@
2
B
GND3Y
SN74LVC1G08DCKR
GND
1 2
R2515 0Ohm
4
SYS_PWROK30,68
SUSWARN#/SUSPWRDNACK30
SUSACK#30
WAKE_PCIE#53
+3V
12
12
C2503
100PF/50V
R2516
10KOhm
@
GNDGNDGND
R1.1 0526
PM_PWROK
PM_RSMRST_R
R1.0 0422A
SUS_PWR_ACK_R
BUF_PLT_RST# 30,32,40,51,53,62
R2535
R2504
R2505
R2506
R2508 0Ohm@
R2509
R2510 0Ohm@
T2502
T2508
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
1
DELAY_ALL_SYSTEM_PWRGD30
T2501
ALL_SYSTEM_PWRGD30,92
R1.1 0526
R1.1 0526
R1.1 0526
R1.1 0526
VRM_PWRGD80,92
1
PM_SYS_RESET#_R
PM_RSMRST_R
H_CPUPWRGD
H_VCCST_PWRGD_MCP
SYS_PWROK_R
PM_PCH_PWROK_R
PCH_DPWROK
SUS_PWR_ACK_R
SUSACK#_R
LAN_WAKE#
GPD11
GPD7
U0301K
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
940432
01V010000015
1 2
R2531 0Ohm@
1 2
SP2506
1 2
D2501 1.2V/0.1A
1 2
R2502 0Ohm@
1 2
D2502 1.2V/0.1A
ALL_SYSTEM_PWRGD_PMOK
VR_READY_PMOK
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
U2502
A
1
B
2
3 4
GND
Vcc=2~5.5
1 2
R2517 0Ohm@
VCC
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
5
Y
SLP_S0#
SLP_S3#_R
R2533
SLP_S4#_R
R2534
GPD10
SLP_SUS#
SLP_LAN#
SLP_WLAN#
ME_SLP_A#
R2538 0Ohm@
AC_PRESENT_R
R2532
BATLOW#
PME#
SM_INTRUDER#
MPHY_EXT_PWR_GATEB_R
VR_ALERT#
+3VSUS
12
GND
1 2
1 2
1 2
R2513 1MOhm
PM_PWROK
R2519
10KOhm
1 2
1
1
1
1
R1.1 0526
1
R1.1 0526
1 2
R1.1 0526
T2503
T2504
T2510
T2505
T2511
+VCC_RTC
+3VSUS_ORG 20,21,22,23,26
+VCC_RTC 24,26,36,60
+VCCDSW 26,30,65
+VCCST_CPU 3,5,7,9,32,65
+3V 31,44,57,58,82,91
+3V
+3VSUS 4,24,26,28,30,31,51,53,62,65,68,81,92
PM_SUSB# 30,68
PM_SUSC# 30,68
ME_PM_SLP_A# 30
PM_PWRBTN# 30
ME_AC_PRESENT 30
1
R1.0 0408
internal pull high
Set to GPI
T2509
internal pull high
BATLOW#
LAN_WAKE#
GPD7
WAKE_PCIE#
AC_PRESENT_R
PM_PWRBTN#PLT_RST#
R1.1 0526 PU EC sideR1.0 0408
PME#
VR_ALERT#
1 2
R2522 10KOhm
1 2
R2523 10KOhm
1 2
R2524 10KOhm
1 2
R2525 1KOhm
1 2
R2526 10KOhm
1 2
R2537 10KOhm@
1 2
R2527 10KOhm@
1 2
R2528 10KOhm@
+VCCDSW
+3VSUS_ORG
+3VSUS
+VCCST_CPU
12
U2503
1
NC
A
GND
74AUP1G07GW
06V030000021
VCC
Y
EC delay ALL_SYSTEM_PWRGD 2ms
A A
5
DELAY_ALL_SYSTEM_PWRGD
ALL_SYSTEM_PWRGD
4
1 2
R2529 0Ohm
1 2
R2530 0Ohm@
H_VCCST_PWRGD_L
2
3 4
3
12
5
H_VCCST_PWRGD_R H_VCCST_PWRGD_MCP
C2504
0.1UF/16V
R2520
1KOhm
R2521 60.4Ohm1%
12
C2505
0.1UF/16V
@
+VDDQ/+VCCST_CPU/+VCCSTG to VCCST_PWRGD must > 1ms
1 2
2
PCH(6)_POWER MANAGE
PCH(6)_POWER MANAGE
PCH(6)_POWER MANAGE
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
25 110Monday, July 18, 2016
25 110Monday, July 18, 2016
25 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
Vinafix.com
5
+1.0VSUS
+VCCDSW
+1.8VSUS
+VCCPAZIO
+VCC_RTC
+VCCF24NS_1P0
+3VSUS_ORG
D D
RF requirement
+VCCMPHYGTAON_1P0_LS_SIP
12
C2636
10PF/50V
@
C C
+3VSUS_ORG
B2607 600Ohm/100MHZ
+3VSUS_ORG
R2611 0Ohm
R1.0 0412
B B
+1.0VSUS
R1.0 0419
+VCCPRIM_CORE
R1.0 0419
+1.0VSUS
R1.0 0419
+VCCMPHYGTAON_1P0_LS_SIP
G
C2605
near N15
47uF/6.3V
+1.0VSUS
1 2
@
21
B2604 600Ohm/100MHZ
C2608
47uF/6.3V
21
12
12
+3VSUS_ORG/+1.8VSUS to +1.0VSUS >200us (tPCH06)
R1.0 0429
+3VSUS_ORG +VCCDSW
w/o DSW
R1.0 0419
1 2
1 2
1 2
12
12
+1.0VSUS
+VCCDSW
+3VSUS_ORG
C2609
1UF/10V
+1.0VSUS
C2611
1UF/10V
@
+VCCAPLLEBB_1P0
R2648
1 2
0Ohm
R2633
1 2
0Ohm
+3VSUS
R2601
0Ohm
R2602
0Ohm
R2603
0Ohm
near K17
12
C2606
1UF/10V
near N15
R2605 0Ohm
R2606 0Ohm
R2612
1 2
0Ohm
G
+1.0VSUS 65,82
+VCCDSW 25,30,65
+1.8VSUS 9,24,84
+VCCPAZIO 22
+VCC_RTC 24,25,36,60
+VCCF24NS_1P0 24
+3VSUS_ORG 20,21,22,23,25
+3VSUS 4,24,25,28,30,31,51,53,62,65,68,81,92
12
C2601
near AB19
1UF/10V
@
12
C2602
near AF18
1UF/10V
@
12
C2603
1UF/10V
+VCCMPHYAON_1P0
+VCCAMPHYPLL_1P0
G
R1.0 0422
1 2
+VCCPDSW_3P3
R1.0 0422
1 2
+1.8VSUS
1 2
R2609 0Ohm@
1 2
R2610 0Ohm
R1.0 0412
+VCCPRIM_3P3
+VCCFHV
12
C2612
near N18
1UF/10V
+3VSUS_ORG+3VSUS
Decoupling cap for internal power
+VCCDSW_1P0
C2604 1UF/10V
+VCCAPLL_1P0
+V1.00A_SIP
+VCCPSPI
R1.0 0428
+VCCSRAM_1P0
G
C2610 1UF/10V
+1.0VSUS +VCCMPHYGTAON_1P0_LS
R1.0 0408
A A
1 2
near AL1
1 2
@
R1.0 0419
4
+VCCPRIM_1P0
12
C2607
1UF/10V
@
near K15
+VCCPAZIO
near AF20
R2635
1 2
0Ohm
SATA Gen3 Port X 2
PCIe Gen2 Lane X 1
USB3 Port X 2
All HSIO disabled (basic comsunption)
=0.132x2+0.102+0.132x2+0.064 = 0.694A
U0301O
VCCPRIM_1P0_1
VCCPRIM_1P0_2
VCCPRIM_1P0_3
VCCPRIM_CORE_1
VCCPRIM_CORE_2
VCCPRIM_CORE_3
VCCPRIM_CORE_4
DCPDSW_1p0
VCCMPHYAON_1P0_1
VCCMPHYAON_1P0_2
VCCMPHYGT_1P0_1
VCCMPHYGT_1P0_2
VCCMPHYGT_1P0_3
VCCMPHYGT_1P0_4
VCCMPHYGT_1P0_5
VCCAMPHYPLL_1P0_1
VCCAMPHYPLL_1P0_2
VCCAPLL_1P0
VCCPRIM_1P0_4
VCCPRIM_1P0_5
VCCDSW_3p3_1
VCCDSW_3p3_2
VCCDSW_3p3_3
VCCHDA
VCCSPI
VCCSRAM_1P0_1
VCCSRAM_1P0_2
VCCSRAM_1P0_3
VCCSRAM_1P0_4
VCCPRIM_3p3_1
VCCPRIM_1P0_6
VCCAPLLEBB_1P0
940432
01V010000015
R1.0 0419
1 2
R1.0 0419
1 2
R1.0 0419
1 2
R1.0 0419
1 2
CPU POWER 4 OF 4
+VCCMPHYGTAON_1P0_LS_SIP
AB19
0.696A
AB20
AF18
2.574A
AF19
0.022A
0.694A
0.088A
0.026A
AB17
0.696A
AD17
0.118A
AD18
0.068A
0.011A
AF20
0.642A
AF21
0.075A
AK20
0.696A
0.033A
R2636 0Ohm
R2637 0Ohm
R2638 0Ohm
R2639 0Ohm
P18
V20
V21
AL1
K17
L1
N15
N16
N17
P15
P16
K15
L15
V15
Y18
AJ17
AJ19
AJ16
T19
T20
AJ21
N18
if need choke, gate power should be disabled
VCCRTCPRIM_3p3
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
+VCCSRAM_1P0
+VCCAMPHYPLL_1P0
3
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3p3_2
VCCPRIM_1P0_7
VCCATS_1p8
VCCRTC_1
VCCRTC_2
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
G
G
+VCCPGPPA
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
G
+VCCAPLLEBB_1P0
0.02A
0.075A
0.696A
0.006A
0.001A
VCCRTCEXT
0.035A
0.029A
0.024A
0.033A
0.004A
0.01A
GPP_B0
GPP_B1
1UF/10V
0.004A
+VCCPGPPB
+VCCPGPPC
C2634 0.1UF/16V
GND
C2620 0.1UF/16V
12
R2646
1KOhm
G
12
near AG15
C2635
@
0.006A
0.008A
+VCCPGPPD
1 2
12
near BB10
12
R2647
1KOhm
Intel confirm pull down 1k
0.006A
+VCCPGPPE
near AK19
0.001A
near Y16
0.161A
+VCCPGPPF
+VCCPRTC_3P3
GND
2
12
C2613
1UF/10V
@
12
C2614
1UF/10V
@
0.056A
+VCCPGPPG
R2626
1 2
0Ohm
1 2
C2619 1UF/10V
+VCC24TBT_1P0
near T16
+VCCPRIM_3P3
+VCC_RTC
R1.0 0419
GND
+VCCF24NS_1P0
+VCCDSW
R1.0 0412
12
R26200Ohm
R1.0 0419
+VCCDTS_1P0
near AK19
+VCCF135_1P0
+VCCF100OC_1P0
1
R1.0 0412
1 2
R2613 0Ohm
+1.8VSUS
+1.0VSUS
R2623
12
0Ohm
R1.0 0419
+V1.8A_SIP
+VCC19P2_1P0
+VCCF100_1P0
near A10
1 2
R2641 0Ohm
Q2601
D
3
G
1
1
3
2
1
E1
B1
C2
C1
B2
E24
5
6
12
R2634
100KOhm
@
2016.01.07
R1.2
Armani 2016 project for USB D+/D- short lesson learn solution (EC)
R2624
12
0Ohm
C2615
1UF/10V
+VCCPRTCPRIM_3P3
R1.0 0412
R1.0 0412
R1.0 0412
R1.0 0412
R1.0 0412
R1.0 0412
C2624
1UF/10V
@
@
S
23
2
SI2301CDS-T1-GE3
Q2602
BC856BS
@
+1.8VSUS
12
near AA1
12
R2627
0Ohm
R2628
0Ohm
R2629
0Ohm
R2630
0Ohm
R2631
0Ohm
R2632
0Ohm
12
12
12
12
12
12
+VCCPDSW_3P3+VCCDSW
C2617
0.1UF/16V
+1.0VSUS
+1.0VSUS
+1.0VSUS
+1.0VSUS
+1.0VSUS
+1.0VSUS
near AK17 near AK17
12
12
R2640
100KOhm
@
+3VSUS_ORG
R1.0 0414
R2625
12
0Ohm
C2618
1UF/10V
+3VSUS_ORG
12
PCH(7)_POWER
PCH(7)_POWER
PCH(7)_POWER
Title :
Title :
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
PEGATRON PROPRIETARY AND CONFIDENTI AL
BG1/HW3
BG1/HW3
BG1/HW3
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
ST5DB
ST5DB
ST5DB
Engineer:
Engineer:
Engineer:
1
Title :
Jack_Lee
Jack_Lee
Jack_Lee
26 110Monday, July 18, 2016
26 110Monday, July 18, 2016
26 110Monday, July 18, 2016
Rev
Rev
Rev
1.0
1.0
1.0
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