Acer Predator Helios 300 PH315-51 Schematic

A

www.laptoprepairsecrets.com

1 1

2 2

B

C

D

E

Compal Confidential

DH53F MB Schematic Document

LA-F991P

3 3

Rev : 1.C

2018.02.13

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

D

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

1 73Tuesday February 13 2018

1 73Tuesday February 13 2018

1 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

B

C

D

E

1 1

HDMI Conn.

eDP

Fan Control*2

age 50

p

Interleaved Memory

page 38

page 37

eDP

CoffeeLake H PROCESSOR
BGA1440

HDMI x 4 lanes

2 2

NGFF

WLAN

USB port 7

page 41

PCIE 2.0
5GT/s

port 15

Realtek 8411H

Card Reader

3 3

RJ45 conn.

RTC CKT.

page 21

Power On/Off CKT.

page 50

Nvidia N17E-G1
with gDDR5 x6

page 39

PCIE 3.0 x4
8GT/s
Port 9-12

page 40

PCIE 2.0
5GT/s

port 14

LAN(GbE)

page 32.

Sub Board

page 25~36

LS-E921P
HS/B

LS-F992P
USB2/B

SATA Re-Driver

PARADE PS8527

SATA HDD Conn.

page 47

page 48

page 48

PEG x16
8GT/s

Flexible IO

page 38

SATA3.0

6.0 Gb/s

port 4

Touch Pad Int.KBD

PS2 / I2C

page 49

(42X28) (CFL-H_6+2)

Processor

X4 DMI

Cannonlake PCH - H
FCBGA(25X24)

874pin FCBGA

LPC/eSPI BUS

CLK=24MHz

ENE
KB9022/9032

page 43

TPM

page 49

page 07~14

page 15~22

page 49

Memory BUS

Dual Channel

1.2V DDR4 2400/2666

USBx8

HD Audio

SPI

SPI ROM x1

page 17

USB 3.0
conn x1

USB (port 1)

48MHz

3.3V 24MHz

USB 3.0 x2
Type-C

USB (port 2)

page 46 page 37

page 44,45

Int. Speaker

260 pin DDR4-SO-DIMM X1

BANK 0, 1, 2, 3

260pin DDR4-SO-DIMM X1

BANK 4, 5, 6, 7

CMOS
Camera

USB (port 5)

Finger_Print

USB (port 8)

page 50

HDA Codec

ALC255

page 42

Int. DMIC

page 42

on Sub/B

page 48 page 48

page 23

page 24

UAJ

on Sub/B

DC/DC Interface CKT.

page 51

Power Circuit DC/DC

page 52~69

A

B

C

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D

AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D

AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

T tle

T tle

T tle

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date Sheet of

Date Sheet of

Date Sheet of

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

E

2 73Tuesday February 13 2018

2 73Tuesday February 13 2018

2 73Tuesday February 13 2018

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

B

C

D

E

oard ID Table for AD channel

B

cc 3.3V +/- 5%

V

Board ID

1 1

2 2

100K +/- 5%Ra

R

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

0
12K +/- 1% 0.347 V 0.345 V 0.360 V
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%

NC

b V min

B

ID

0.423 V 0.430 V 0.438 V

1.398 V

1.634 V

1.849 V

2.015 V

2.185 V

2.316 V

2.395 V

2.521 V

2.667 V

2.791 V

2.905 V

3.000 V

V

B

ID

0.000 V

1.414 V

1.650 V

1.865 V

2.031 V

2.200 V

2.329 V

2.408 V

2.533 V

2.677 V

2.800 V

2.912 V

3.000 V

typ

V

B

ID

0.300 V

1.430 V

1.667 V

1.881 V

2.046 V

2.215 V

2.343 V

2.421 V

2.544 V

2.687 V

2.808 V

2.919 V

m

ax

EC AD

0x00 - 0x13
0x14 - 0x1E
0x1F - 0x25
0x26 - 0x300.541 V 0.550 V 0.559 V
0x31 - 0x3A0.691 V 0.702 V 0.713 V
0x3B - 0x450.807 V 0.819 V 0.831 V
0x46 - 0x540.978 V 0.992 V 1.006 V
0x55 - 0x641.169 V 1.185 V 1.200 V
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA4
0xA5 - 0xAF
0xB0 - 0xB7
0xB8 - 0xBF
0xC0 - 0xC9
0xCA - 0xD4
0xD5 - 0xDD
0xDE - 0xF0
0xF1 - 0xFF

I2C Address Table

BUS

I2C_1 (+3VS)

Device

Touch PanelI2C_0 (+3VS)

TM-P2969-001 (Touch Pad)

Address(7 bit)

reserved

SB8787-1200 (Touch Pad)

PCH_SMBCLK

(+3VS)

PCH_SML1CLK

(+3VS)

DIMM1
DIMM2
LIS3DHTR(G-sensor)
N17E-G1 (VGA)

EC

CC controller 179F

0x30
0x9E

TMS

EC_SMB_CK1
(+3VLP)

3 3

BQ24780 (Charger IC)

BATTERY PACK

0x12
0x16

Address(8bit)

ReadWrite

ower State

P

STATE

S0 (Full ON) ON ON ON ONHIGH HIGH HIGH

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW HIGH

BOM Structure Table

BOM Option Table

Item BOM Structure

Unpop @

Connector
UMA only UMA@

dGPU

DIS only

TPM TPM@

For Acer IOAC
No Acer IOAC
28P keyboard connector
32P keyboard connector
Finger Print
Finger Print for ESD FPESD@

Thermal sensor
LAN LDO mode LDO@
LAN Switch mode SWR@

G-Sensor GSEN@

EMI require reserve
ESD requirement ESD@

CNVi
UART debug
Codec ALC255
Codec ALC256
Codec ALC256 for ESD 256ESD@
Codec ALC256 for EMI 256EMI@
G-PAK for GPU sequence
DIS for GPU sequence
W/ SATA re-driver
W/O SATA re-driver
PCH

CONN@

CMC@CMC
VGA@

DIS@

IOAC@
NIOAC@

28P@
32P@
FP@

PBA@PBA

TMS@

EMI@EMI requirement
@EMI@

@ESD@EMI require reserve
CNVI@
UART@
255@
256@

GPK@
NGPK@

SATARD@
NORD@
PCH@

ONONON

HIGH

LOWLOW

HIGH

OFF

ON

OFFLOW LOW LOW

OFF

OFF

OFF

OFF

OFF

OFF

Voltage Rails

Power Plane

+RTCVCC

+19V VIN

+12.6V BATT Battery power supply
+19VB

+3VLP
+5VALW
+3VALW System +3VALW always on power rail
+3VALW DSW +3VALW power for PCH DSW rails
+3VALW PCH PRIM
+3VALW SPI
+1.05VALW +1.05V Always power rail

+1.05V VCCST

+5VS System +5V power rail
+3VS

+1.05VS VCCSTG +1.05VALW PRIM Gated version of VCCST
+0.6VS VTT DDR +0.6VS power rail for DDR terminator .

+VCC CORE
+VCC GT
+VCCIO

+VCC SA

+1.8VSDGPU AON

+VGA CORE

+1.35VSDGPU +1.35VS power rail for GPU

+1.0VSDGPU

+1.8VALW System +1.8VALW always on power rail

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description
RTC Battery Power
Adapter power supply

AC or battery power rail for power circuit.
+19VB to +3VLP power rail for suspend power

+5V Always power rail

+3VALW power for PCH power rails

+3VALW PRIM supply for the SPI IO

DDR4 +1.2V power rail+1.2V VDDQ
Sustain voltage for processor in Standby modes

System +3V power rail

Core voltage for CPU
Sliced graphics power rail
CPU IO +0.95VS power rail

System Agent power rail

+1.8VS power rail for GPU(AON rails)
+1.8VS power rail for GPU GC6+1.8VSDGPU MAIN
Core voltage for VGA (merge core & core s)

+1.0VS power rail for GPU

OARD ID Table

B

Board ID

0
1
2
3
10
11
12
13

PCB Revision

0

.1 / 28P

0.2 / 28P
1

.0 / 28P

1.C / 28P

0.1 / 32P

0.2 / 32P

1.0 / 32P

1.C / 32P

S0

S3

ON

ON

N/A N/A N/A

N/A
N/A

N/A

N/A

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON ON ONON

ON

ON

ON

ON
ON ON

ON

OFF

ON

OFF OFF
OFF OFF OFF

ON
ON

OFF
OFF

ON

OFF

ON

OFF OFF OFF

ON
ON

OFF

ON

OFF

ON

OFF OFF

ON

OFF OFF OFF

ON

OFF OFF OFF

ON

ONON

S4

S5

ON ON

N/AN/AN/A

N/A N/A

ON ON
ON ON

ON*

ON
ON ON

ON*ON

ON

ON

OFF

OFF

OFF

OFF

OFF

OFF
OFF

OFF

OFF

OFF

OFF
OFF

OFF

OFFOFF

OFF
OFF OFF
OFF OFF

OFF

ON*

ON

CPU i5@/i7@

BOM table

43 Level

431AB2BOL05~08
431AB2BOL53_54
431AB1BOL67

BOM StructureDescription

X4EAB2BO001
X4EAB2BO051
X76730BOL56
X76730BOL57
X76730BOL58

ALT. GROUP PARTS N17E6G SAM 256M32 DH7VF
ALT. GROUP PARTS N17E6G HYN 256M32 DH7VF
ALT. GROUP PARTS N17E6G MIC 256M32 DH7VF

A

B

C

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D

AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D

AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

T tle

T tle

T tle

Notes List

Notes List

Notes List

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

E

3 73Tuesday February 13 2018

3 73Tuesday February 13 2018

3 73Tuesday February 13 2018

1.A

1.A

1.A

5

www.laptoprepairsecrets.com

C_IN

D

P

JP101

AC CONN.

D D

C C

B B

A A

PL101

U301

P

CHARGER

+19V_VIN

+

5

12.6V_BATT

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

P

L201,PL202

JP201

P

IMVP8

PU8102

U8103

P
PU8104
PU8105

EN:VR_ON

PQ8105
PU8106

EN:DRON

PQ8301

EN:DRON

EN:3V_EN

PU401

EN:SYSON

PU501

PU601

P

L8101,PL8306,PL8305,PL8106

PL8107

PL8301

PJ401

+1.2V

PJ501

EN:SM_PG_CTRL

+0.6VSP

PJ502

+1.05VALWP

EN:+3VALW

+1.0VS_VCCIOP

PU7201 PJ7201

EN:SUSP#

PU402

PL1303

PL1304

+5VALWP

PJ402

PR1301

LX1

+12.6V_BATT+

BATTERY

+VCC_GT

+VCC_SA

+3VALW

EC,LID

+3VLP

+1.2V_VDDQ

+0.6VS_VTT

PJ601

+5VALW

+19VB_GPU

+INVPWR_B+

4

4

CPU

+VCCIO

PR1302

PR1402

PJ1701

PANEL

CPU

JEDP1

VCC_CORE

+

JPC1,C2

JDIMM1,2

RD19,21,20

CPU

+1.2V_VDDQ_CPU

+0.6V_DDRB_VREFCA

+0.6V_B_VREFDQ

+1.05VALW

CPU

RK15

EN:NVVDD1_EN

+19VB_NVVDD

EN:NVVDD2_EN

+19VB_NVVDDS

EN:1.35VSDGPU_EN

+19VB_1.35VSDGPUP

PU1302

PQ1401

US2

US11

US12

UQ1

JIO2,3

RK14

CPU

DIMM

CPU

JUSB1

JPQ2

USB/B FPC BTB CONN

PL1401

PQ1701

P

U1801

R

S1

P

U7102

PU7105

UQ1

R19

UM1

UL1

RH99

RH97

RH101

UK1

UK2

RH92

RH93

RH94

UQ2

UC4

+USB3_VCCC

+USB_VCCA

+5VS

PL1351

+NVVDD2

GPU

+1.35VSDGPU

3

EN : 1VSDGPU_EN

+

1.0VSDGPUP

+3.3V_CC

PJ7103

JPQ1

+3VALW_TPM

+3VS_WLAN

+3V_LAN

+3VALW_DSW

+3VALW_PCH_PRIM

+3VALW_HDA

+3V_PTP

+FP_VCC

+1.05VALW_PCH_PRIM

+1.05VALW _VCCMPHY

+5V_CC

JTYPEC1

USB3.0 Conn.

GPU

+NVVDD1

GPU

3

+

1.0VSDGPU

P

J1802

+

2.5V

+1.8VALWP

G

PU

D

IMM1

D

IMM2

DR4

D

+3VS

U5

TPM

JNGFF1

WLAN CARD (IOAC)

UL2

LAN

PCH

+3VALW_SPI

RH98

PCH

JTP1

TP

JEP1

FP

PCH

PCH

+1.05VALW_PCH

RH102
RH103
RH105

RQ5

RQ6

PCH

+1.05VALW_VCCAZPLL

+1.05VALW_VCCAMPHYPLL
+1.05VALW _XTAL

+1.05V_VCCST

+1.05VS_VCCSTG

CPU

Type C Conn.

RF4

RF6

JPA1

U4

UO2

UY2

RX7 JEDP1

+VCC_FAN1

+VCC_FAN2

+VDDA

+5VS_BL

+5VS_HDD

+HDMI_5V_OUT

+TS_PWR

UH3

FAN1

FAN2

UA1

JBL1

JHDD1

JHDMI1

PJ7107

SPI

PCH
PCH
PCH

CODEC

KB BackLight

HDD

HDMI

TP

2

U

G27

1.8VS

+

+1.8VALW

UQ2

UO1

RZ1

UF1

RM11

RM1

R20

RX6

UX1

UG20

RA2

RA4

R

H100

1.8VSDGPU_MAIN_EN

R

A3

+1.8VALW_PRIM

R

H100

+3VS_WLAN

+3VS_SSD_NGFF

+3VS_TPM

+TS_PWR

+LCDVDD

+3VSDGPU

+3VS_DVDDIO

+3VS_DVDD

+3VS_DIMMA

Security C assi ica ion

Security C assi ica ion

Security C assi ica ion

Issued Date

Issued Date

Issued Date

HS SHEE O ENGNEERNG DRAWING IS HE RO RE AR RO ER O COM A E EC RONCS NC AND CON A NS CON DEN A

HS SHEE O ENGNEERNG DRAWING IS HE RO RE AR RO ER O COM A E EC RONCS NC AND CON A NS CON DEN A

HS SHEE O ENGNEERNG DRAWING IS HE RO RE AR RO ER O COM A E EC RONCS NC AND CON A NS CON DEN A

AND RADE SECRE IN ORMA ION HS SHEE MA NO BE RANS ERED ROM HE CUS OD O HE COM E EN DVISON O R&D

AND RADE SECRE IN ORMA ION HS SHEE MA NO BE RANS ERED ROM HE CUS OD O HE COM E EN DVISON O R&D

AND RADE SECRE IN ORMA ION HS SHEE MA NO BE RANS ERED ROM HE CUS OD O HE COM E EN DVISON O R&D
DE AR MEN EXCE AS AU HORIZED B COM A E EC RONICS NC NEI HER HIS SHEE NOR HE N ORMA ON I CON AINS

DE AR MEN EXCE AS AU HORIZED B COM A E EC RONICS NC NEI HER HIS SHEE NOR HE N ORMA ON I CON AINS

DE AR MEN EXCE AS AU HORIZED B COM A E EC RONICS NC NEI HER HIS SHEE NOR HE N ORMA ON I CON AINS
MA BE USED B O R DSC OSED O AN HRD AR WI HOU ROR WRI EN CONSEN O COM A E EC RON CS NC

MA BE USED B O R DSC OSED O AN HRD AR WI HOU ROR WRI EN CONSEN O COM A E EC RON CS NC

MA BE USED B O R DSC OSED O AN HRD AR WI HOU ROR WRI EN CONSEN O COM A E EC RON CS NC

2

Compal Secret Da a

Compal Secret Da a

Compal Secret Da a

20 7 07 20 20 8 0 7 20

20 7 07 20 20 8 0 7 20

20 7 07 20 20 8 0 7 20

Deciphered Da e

Deciphered Da e

Deciphered Da e

E

N:DGPU_PWR_EN

+

1.8VSDGPU_AON

+1.8VSDGPU_MAIN

EN:1.8VSDGPU_MAIN_EN

+

1.8VDDA

ODEC

C

P

CH

+

1.8V_PHVLDO

PCH

SATA Re-driver

G-SENSOR

THERMAL SENSOR

JNGFF1

WLAN

JSSD1

SSD

U5

TPM

JEDP1

TS

JEDP1

PANEL

GPU

+3VS_DVDDIO

+3VS_DVDD

GPU

G

PU

CODEC

CODEC

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

i le

i le

i le

Power Map

Power Map

Power Map

Size Document Numbe ev

Size Document Numbe ev

Size Document Numbe ev

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sh eet o

Date Sh eet o

Date Sh eet

o

4 73uesday eb ua y 3 20 8

4 73uesday eb ua y 3 20 8

4 73uesday eb ua y 3 20 8

A

A

A

5

www.laptoprepairsecrets.com

3

2

1

DH53F_EVT Power Sequence

IOS : 0.05

B

Power On

S3 S3 Resume

Power Off

AC mode

Plug in

+3VLP

D D

C_ON

E

+5VALW

→

ON/OFFBTN#

+3VALW

+1.8VALW

+1.05ALW

EC_RSMRST#

PBTN_OUT#

→

90.77ms

→

92.67ms

→

93.73ms

→

21.45ms
20ms

→

←

→

←

130.8ms

→

→

→

→

→

8.969s

8.97s

8.97S

8.497S

8.497S

+3VLP

EC_ON

+5VALW

ON/OFFBTN#

+3VALW

+1.8VALW

+1.05ALW

EC_RSMRST#

PBTN_OUT#

→

PM_SLP_S4#

C C

PM_SLP_S3#

SYSON

+1.05V_VCCST

+1.2V_VDDQ

+2.5V

SUSP#

+1.05VS_VCCSTG

+VCCIO

+5VS

+3VS

+1.8VS

B B

EC_VCCST_PG

SM_PG_CTRL

+0.6VS_VTT

VR_ON

+VCCS_A

PCH_PWROK

SYS_PWROK

PLT_RST#

+VCC_CORE

+VCC_GT

→

→

17.32ms

17.36ms

20.16ms

→

→

→

→

302.5us

752.8us

985us

9.797ms

→

→

→

→

→

→

→

→

8.607us

682.5us

926us

670.8us

438us

20.55ms

20.5ms

→

20.53ms

→

→

→

→

→

4us

1.773ms

10.15ms

120.9ms

→

1.339ms

136.8ms

6.655s

→

291us

→

→

→

→

→

→

→

560.8ms

→

→

→

→

→

→

13.77us

44.84us

9.382us

9.78us

→

→

637.6us

516.2us

5.065ms

4.447ms

2.089ms

28.72us

43.75us

74.13us

87.21us

83.73us

→

32.21ms

→

→

→

→

→

→

→

→

8.64us

679.3us

929.5us

677.4us

419.9us

19.97ms

→

→

→

→

→

→

20.38ms

4us

20.41ms

1.776ms

9.604ms

121.3ms

→

1.614ms

139.6ms

1.419s

→

→

→

→

→

→

→

→

→

→

→

→

→

→

→

→

→

→

1.837s

439.9us

291.9us

→

→

→

13.75us

53.92us

9.275us

9.764us

28.57us

4.993us

76.22us

496.3us

1.587ms

646.6us

659.4us

724us

46.27us

74.07us

87.14us

84.98us

4.683ms

2.786ms

PM_SLP_S4#

PM_SLP_S3#

SYSON

+1.05V_VCCST

+1.2V_VDDQ

+2.5V

SUSP

+1.05VS_VCCSTG

+VCCIO

+5VS

+3VS

+1.8VS

EC_VCCST_PG

SM_PG_CTRL

+0.6VS_VTT

VR_ON

+VCC_SA

PCH_PWROK

SYS_PWROK

PLT_RST#

+VCC_CORE

+VCC_GT

A A

Security Classification

Security Classification

5

3

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D

AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D

AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

T tle

T tle

T tle

Power Map

Power Map

Power Map

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

2

Date Sheet of

1

5 73Tuesday February 13 2018

5 73Tuesday February 13 2018

5 73Tuesday February 13 2018

1.A

1.A

1.A

5

www.laptoprepairsecrets.com

PCH_SMBCLK

P

CH_SMBDATA

P

CH_SML0CLK

D D

annonLake-H

C
PCH

PCH_SML0DATA

PCH_SML1CLK

PCH_SML1DATA

4

499

99

2.2K

2.2K

2

2K

.

2

.2K

3VALW_PCH_PRIM

+

+

3VS

2

N7002DW

3VALW_PCH_PRIM

+

3VALW_PCH_PRIM

+

D

_CK_SCLK

D

_CK_SDATA

2.2K

2.2K

3VS

+

S

O-DIMM A & B

G-Sensor

+1.8VSDGPU_MAIN

PJT138KA

2.2K

2.2K

EC_SMB_CK1

EC_SMB_DA1

KB9022

+3VLP_EC

100 ohm

100 ohm

0 ohm
0 ohm

EC_SMB_CK1 1

EC_SMB_DA1 1

EC_SMB_CK1_CHGR
EC_SMB_DA1_CHGR

BATTERY

CONN

Charger

+3.3V_CC

2N7002DW

+3VS

C C

2N7002DW

3

VGA_SMB_CK2

VGA_SMB_DA2

4.7K

4.7K

USB CC EJ179F

2.2K

2.2K

THERMAL SENSOR

2.2K

2.2K

+1.8VSDGPU_AON

N17E-G1

+3.3V_CC

+3VS

I2CC_SCL_R

I2CC_SDA_R

2

1.8K

1.8VSDGPU_AON

1.8K

+
+1.8VSDGPU_MAIN

PJT138KA

I2CC_SCL

I2CC_SCL

1.8K

1.8K

1

+3VSDGPU

Current Sensor

B B

A A

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTANS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTANS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTANS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PROR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PROR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PROR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Issued Date

Issued Date

Issued Date

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

N17E-GDDR5 D

N17E-GDDR5 D

N17E-GDDR5 D

Document Number Re v

Document Number Re v

Document Number Re v

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

1

6 73Tuesday, February 13, 2018

6 73Tuesday, February 13, 2018

6 73Tuesday, February 13, 2018

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

B

C

D

E

CO-LAY FOR VGA OUTPUT

G

1 2

R

GPU_EDP_TXP0<27>
GPU_EDP_TXN0<27>
G

PU_EDP_TXP1<27>

G

PU_EDP_TXN1<27>
GPU_EDP_TXP2<27>
GPU_EDP_TXN2<27>

1 1

GPU_EDP_TXP3<27>

PU_EDP_TXN3<27>

G

GPU_EDP_AUXP<27>
GPU_EDP_AUXN<27>

G203 0_0201_5%DIS@

1 2

RG204 0_0201_5%DIS@

1 2

RG205 0_0201_5%DIS@

1 2

R

G206 0_0201_5%DIS@

1 2

RG207 0_0201_5%DIS@

1 2

RG208 0_0201_5%DIS@

1 2

RG209 0_0201_5%DIS@

1 2

RG210 0_0201_5%DIS@

1 2

G211 0_0201_5%DIS@

R

1 2

RG212 0_0201_5%DIS@

PU_EDP_TXP0_R
GPU_EDP_TXN0_R
GPU_EDP_TXP1_R
G

PU_EDP_TXN1_R
GPU_EDP_TXP2_R
GPU_EDP_TXN2_R

PU_EDP_TXP3_R

G
GPU_EDP_TXN3_R

GPU_EDP_AUXP_R
GPU_EDP_AUXN_R

TC21 @
TC22 @
TC23 @
TC24 @
TC25 @

C26 @

T
TC27 @
TC28 @

C29 @

T
TC30 @

UC1D

K36

DDI1_TXP_0

K37

DDI1_TXN_0

J35

DDI1_TXP_1

J34

DDI1_TXN_1

H37

DDI1_TXP_2

H36

DDI1_TXN_2

J37

DDI1_TXP_3

J38

2 2

ZZZ

PCB@ DAZ29000103
PCB DH53F LA-F991P LS-F992P/E921P

3 3

DDI1_TXN_3

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP_0

H33

DDI2_TXN_0

F37

DDI2_TXP_1

G38

DDI2_TXN_1

F34

DDI2_TXP_2

F35

DDI2_TXN_2

E37

DDI2_TXP_3

E36

DDI2_TXN_3

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP_0

D34

DDI3_TXN_0

B36

DDI3_TXP_1

B34

DDI3_TXN_1

F33

DDI3_TXP_2

E33

DDI3_TXN_2

C33

DDI3_TXP_3

B33

DDI3_TXN_3

A27

DDI3_AUXP

B27

DDI3_AUXN

CFL-H_BGA1440

@

CFL-H

EDP_TXP_0
EDP_TXN_0
EDP_TXP_1
EDP_TXN_1
EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3

EDP_AUXP
EDP_AUXN

EDP_DISP_UTIL

DISP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

of 13

D29
E29
F28
E28
A29
B29
C28
B28

C26
B26

A33

D37

G27
G25
G29

EDP_TXP0
EDP_TXN0
EDP_TXP1
EDP_TXN1
EDP_TXP2
EDP_TXN2
EDP_TXP3
EDP_TXN3

EDP_AUXP
EDP_AUXN

DP_RCOMP

Trace Width/Space: 15 mil/ 20 mil
Max Trace Length: 600 mil

CPU_DISPA_SDI

RC1 24.9_0402_1%

RC2 20_0402_5%

1 2

12

EDP_TXP0 <37>
EDP_TXN0 <37>
EDP_TXP1 <37>
EDP_TXN1 <37>
EDP_TXP2 <37>
EDP_TXN2 <37>
EDP_TXP3 <37>
EDP_TXN3 <37>

EDP_AUXP <37>
EDP_AUXN <37>

+VCCIO

CPU_DISPA_BCLK_R
CPU_DISPA_SDO_R
CPU_DISPA_SDI_R

eDP

CPU_DISPA_BCLK_R <19>

CPU_DISPA_SDO_R <19>

CPU_DISPA_SDI_R <19>

Coffee Lake-H CPU SKU

UC1

UC1

CFL-H_BGA1440

S IC CL8068403373522 SR3Z0 U0 2.3G ABO!
SA0000BPJ40

5@

4 4

A

CFL-H_BGA1440

S IC CL8068403359524 SR3YY U0 2.2G ABO!
SA0000BPZ40
i7@

Security Classification

Security Classification

Security Classification

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2017/07/20 2018/07/20

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

D

Date Sheet of

7 73Tuesday February 13 2018

7 73Tuesday February 13 2018

7 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

B

C

D

E

CHANNEL-A

I

nterleaved Memory

UC1A

1 1

2 2

3 3

DDR_A_D[0..63]<23>

For ECC DIMM

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DR (IL)/LP3-DDR (NIL) LP3/DDR

D

BR6

DDR0_DQ_0/DDR0_DQ_0

BT6

DR0_DQ_1/DDR0_DQ_1

D

BP3

DDR0_DQ_2/DDR0_DQ_2

BR3

DDR0_DQ_3/DDR0_DQ_3

BN5

DDR0_DQ_4/DDR0_DQ_4

BP6

DDR0_DQ_5/DDR0_DQ_5

BP2

DDR0_DQ_6/DDR0_DQ_6

BN3

DDR0_DQ_7/DDR0_DQ_7

BL4

DDR0_DQ_8/DDR0_DQ_8

BL5

DDR0_DQ_9/DDR0_DQ_9

BL2

DDR0_DQ_10/DDR0_DQ_10

BM1

DDR0_DQ_11/DDR0_DQ_11

BK4

DDR0_DQ_12/DDR0_DQ_12

BK5

DDR0_DQ_13/DDR0_DQ_13

BK1

DDR0_DQ_14/DDR0_DQ_14

BK2

DDR0_DQ_15/DDR0_DQ_15

BG4

DDR0_DQ_16/DDR0_DQ_32

BG5

DDR0_DQ_17/DDR0_DQ_33

BF4

DDR0_DQ_18/DDR0_DQ_34

BF5

DDR0_DQ_19/DDR0_DQ_35

BG2

DDR0_DQ_20/DDR0_DQ_36

BG1

DDR0_DQ_21/DDR0_DQ_37

BF1

DDR0_DQ_22/DDR0_DQ_38

BF2

DDR0_DQ_23/DDR0_DQ_39

BD2

DDR0_DQ_24/DDR0_DQ_40

BD1

DDR0_DQ_25/DDR0_DQ_41

BC4

DDR0_DQ_26/DDR0_DQ_42

BC5

DDR0_DQ_27/DDR0_DQ_43

BD5

DDR0_DQ_28/DDR0_DQ_44

BD4

DDR0_DQ_29/DDR0_DQ_45

BC1

DDR0_DQ_30/DDR0_DQ_46

BC2

DDR0_DQ_31/DDR0_DQ_47

AB1

DDR0_DQ_32/DDR1_DQ_0

AB2

DDR0_DQ_33/DDR1_DQ_1

AA4

DDR0_DQ_34/DDR1_DQ_2

AA5

DDR0_DQ_35/DDR1_DQ_3

AB5

DDR0_DQ_36/DDR1_DQ_4

AB4

DDR0_DQ_37/DDR1_DQ_5

AA2

DDR0_DQ_38/DDR1_DQ_6

AA1

DDR0_DQ_39/DDR1_DQ_7

V5

DDR0_DQ_40/DDR1_DQ_8

V2

DDR0_DQ_41/DDR1_DQ_9

U1

DDR0_DQ_42/DDR1_DQ_10

U2

DDR0_DQ_43/DDR1_DQ_11

V1

DDR0_DQ_44/DDR1_DQ_12

V4

DDR0_DQ_45/DDR1_DQ_13

U5

DDR0_DQ_46/DDR1_DQ_14

U4

DDR0_DQ_47/DDR1_DQ_15

R2

DDR0_DQ_48/DDR1_DQ_32

P5

DDR0_DQ_49/DDR1_DQ_33

R4

DDR0_DQ_50/DDR1_DQ_34

P4

DDR0_DQ_51/DDR1_DQ_35

R5

DDR0_DQ_52/DDR1_DQ_36

P2

DDR0_DQ_53/DDR1_DQ_37

R1

DDR0_DQ_54/DDR1_DQ_38

P1

DDR0_DQ_55/DDR1_DQ_39

M4

DDR0_DQ_56/DDR1_DQ_40

M1

DDR0_DQ_57/DDR1_DQ_41

L4

DDR0_DQ_58/DDR1_DQ_42

L2

DDR0_DQ_59/DDR1_DQ_43

M5

DDR0_DQ_60/DDR1_DQ_44

M2

DDR0_DQ_61/DDR1_DQ_45

L5

DDR0_DQ_62/DDR1_DQ_46

L1

DDR0_DQ_63/DDR1_DQ_47

LP3/DDR

BA2

NC/DDR0_ECC_0

BA1

NC/DDR0_ECC_1

AY4

NC/DDR0_ECC_2

AY5

NC/DDR0_ECC_3

BA5

NC/DDR0_ECC_4

BA4

NC/DDR0_ECC_5

AY1

NC/DDR0_ECC_6

AY2

NC/DDR0_ECC_7

CFL-H_BGA1440

@

C

FL-H

DDR CHANNEL A

DDR0_CKP_0/DDR0_CKP_0

DR0_CKN_0/DDR0_CKN_0

D
DDR0_CKP_1/DDR0_CKP_1
DDR0_CKN_1/DDR0_CKN_1

NC/DDR0_CKP_2
NC/DDR0_CKN_2
NC/DDR0_CKP_3
NC/DDR0_CKN_3

DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1
DDR0_CKE_2/DDR0_CKE_2
DDR0_CKE_3/DDR0_CKE_3

DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1

NC/DDR0_CS#_2
NC/DDR0_CS#_3

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1
NC/DDR0_ODT_2
NC/DDR0_ODT_3

DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1
DDR0_CAA_5/DDR0_BG_0

DDR0_CAB_3/DDR0_MA_16
DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_9/DDR0_MA_0
DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4
DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8
DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13

DDR0_CAA_9/DDR0_BG_1
DDR0_CAA_8/DDR0_ACT#

NC/DDR0_PAR

NC/DDR0_ALERT#

DDR (IL)/LP3-DDR (NIL)

DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8
DDR0_DQSN_8/DDR0_DQSN_8

1 OF 3

AG1
AG2
AK2
AK1
AL3
AK3
AL2
AL1

AT1
AT2
AT3
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

AH5
AH1
AU1

AH4
AG4
AD1

AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3

AG3
AU5

BR5
BL3
BG3
BD3
AA3
U3
P3
L3

BP5
BK3
BF3
BC3
AB3
V3
R3
M3

AY3
BA3

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CS#0
DDR_A_CS#1

DDR_A_ODT0
DDR_A_ODT1

DDR_A_BA0
DDR_A_BA1
DDR_A_BG0

DDR_A_MA16_RAS#
DDR_A_MA14_WE#
DDR_A_MA15_CAS#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_BG1
DDR_A_ACT#

DDR_A_PAR
DDR_A_ALERT#

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DR_A_CLK0 <23>

D
DDR_A_CLK#0 <23>
DDR_A_CLK1 <23>
DDR_A_CLK#1 <23>

DDR_A_CKE0 <23>
DDR_A_CKE1 <23>

DDR_A_CS#0 <23>
DDR_A_CS#1 <23>

DDR_A_ODT0 <23>
DDR_A_ODT1 <23>

DDR_A_BA0 <23>
DDR_A_BA1 <23>
DDR_A_BG0 <23>

DDR_A_MA16_RAS# <23>
DDR_A_MA14_WE# <23>
DDR_A_MA15_CAS# <23>

DDR_A_MA0 <23>
DDR_A_MA1 <23>
DDR_A_MA2 <23>
DDR_A_MA3 <23>
DDR_A_MA4 <23>
DDR_A_MA5 <23>
DDR_A_MA6 <23>
DDR_A_MA7 <23>
DDR_A_MA8 <23>
DDR_A_MA9 <23>
DDR_A_MA10 <23>
DDR_A_MA11 <23>
DDR_A_MA12 <23>
DDR_A_MA13 <23>
DDR_A_BG1 <23>
DDR_A_ACT# <23>

DDR_A_PAR <23>
DDR_A_ALERT# <23>

DDR_A_DQS#0 <23>
DDR_A_DQS#1 <23>
DDR_A_DQS#2 <23>
DDR_A_DQS#3 <23>
DDR_A_DQS#4 <23>
DDR_A_DQS#5 <23>
DDR_A_DQS#6 <23>
DDR_A_DQS#7 <23>

DDR_A_DQS0 <23>
DDR_A_DQS1 <23>
DDR_A_DQS2 <23>
DDR_A_DQS3 <23>
DDR_A_DQS4 <23>
DDR_A_DQS5 <23>
DDR_A_DQS6 <23>
DDR_A_DQS7 <23>

For ECC DIMM

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

D

Date Sheet of

8 73Tuesday February 13 2018

8 73Tuesday February 13 2018

8 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

B

C

D

E

CHANNEL-B

Interleaved Memory

DR_B_D[0..63]<24>

1 1

2 2

3 3

D

For ECC DIMM

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39

DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UC1B

DR (IL)/LP3-DDR (NIL)

D

BT11

DDR1_DQ_0/DDR0_DQ_16

BR11

DR1_DQ_1/DDR0_DQ_17

D

BT9

DDR1_DQ_2/DDR0_DQ_18

BR8

DDR1_DQ_3/DDR0_DQ_19

BP11

DDR1_DQ_4/DDR0_DQ_20

BN11

DDR1_DQ_5/DDR0_DQ_21

BP8

DDR1_DQ_6/DDR0_DQ_22

BN8

DDR1_DQ_7/DDR0_DQ_23

BL12

DDR1_DQ_8/DDR0_DQ_24

BL11

DDR1_DQ_9/DDR0_DQ_25

BL8

DDR1_DQ_10/DDR0_DQ_26

BJ8

DDR1_DQ_11/DDR0_DQ_27

BJ11

DDR1_DQ_12/DDR0_DQ_28

BJ10

DDR1_DQ_13/DDR0_DQ_29

BL7

DDR1_DQ_14/DDR0_DQ_30

BJ7

DDR1_DQ_15/DDR0_DQ_31

BG11

DDR1_DQ_16/DDR0_DQ_48

BG10

DDR1_DQ_17/DDR0_DQ_49

BG8

DDR1_DQ_18/DDR0_DQ_50

BF8

DDR1_DQ_19/DDR0_DQ_51

BF11

DDR1_DQ_20/DDR0_DQ_52

BF10

DDR1_DQ_21/DDR0_DQ_53

BG7

DDR1_DQ_22/DDR0_DQ_54

BF7

DDR1_DQ_23/DDR0_DQ_55

BB11

DDR1_DQ_24/DDR0_DQ_56

BC11

DDR1_DQ_25/DDR0_DQ_57

BB8

DDR1_DQ_26/DDR0_DQ_58

BC8

DDR1_DQ_27/DDR0_DQ_59

BC10

DDR1_DQ_28/DDR0_DQ_60

BB10

DDR1_DQ_29/DDR0_DQ_61

BC7

DDR1_DQ_30/DDR0_DQ_62

BB7

DDR1_DQ_31/DDR0_DQ_63

AA11

DDR1_DQ_32/DDR1_DQ_16

AA10

DDR1_DQ_33/DDR1_DQ_17

AC11

DDR1_DQ_34/DDR1_DQ_18

AC10

DDR1_DQ_35/DDR1_DQ_19

AA7

DDR1_DQ_36/DDR1_DQ_20

AA8

DDR1_DQ_37/DDR1_DQ_21

AC8

DDR1_DQ_38/DDR1_DQ_22

AC7

DDR1_DQ_39/DDR1_DQ_23

DDR (IL)/LP3-DDR (N L)

W8

DDR1_DQ_40/DDR1_DQ_24

W7

DDR1_DQ_41/DDR1_DQ_25

V10

DDR1_DQ_42/DDR1_DQ_26

V11

DDR1_DQ_43/DDR1_DQ_27

W11

DDR1_DQ_44/DDR1_DQ_28

W10

DDR1_DQ_45/DDR1_DQ_29

V7

DDR1_DQ_46/DDR1_DQ_30

V8

DDR1_DQ_47/DDR1_DQ_31

R11

DDR1_DQ_48/DDR1_DQ_48

P11

DDR1_DQ_49/DDR1_DQ_49

P7

DDR1_DQ_50/DDR1_DQ_50

R8

DDR1_DQ_51/DDR1_DQ_51

R10

DDR1_DQ_52/DDR1_DQ_52

P10

DDR1_DQ_53/DDR1_DQ_53

R7

DDR1_DQ_54/DDR1_DQ_54

P8

DDR1_DQ_55/DDR1_DQ_55

L11

DDR1_DQ_56/DDR1_DQ_56

M11

DDR1_DQ_57/DDR1_DQ_57

L7

DDR1_DQ_58/DDR1_DQ_58

M8

DDR1_DQ_59/DDR1_DQ_59

L10

DDR1_DQ_60/DDR1_DQ_60

M10

DDR1_DQ_61/DDR1_DQ_61

M7

DDR1_DQ_62/DDR1_DQ_62

L8

DDR1_DQ_63/DDR1_DQ_63

LP3/DDR

AW11

NC/DDR1_ECC_0

AY11

NC/DDR1_ECC_1

AY8

NC/DDR1_ECC_2

AW8

NC/DDR1_ECC_3

AY10

NC/DDR1_ECC_4

AW10

NC/DDR1_ECC_5

AY7

NC/DDR1_ECC_6

AW7

NC/DDR1_ECC_7

CFL-H

DDR CHANNEL B

DDR1_CKP_0/DDR1_CKP_0

DR1_CKN_0/DDR1_CKN_0

D

DDR1_CKP_1/DDR1_CKP_1

DDR1_CKN_1/DDR1_CKN_1

DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1
DDR1_CKE_2/DDR1_CKE_2
DDR1_CKE_3/DDR1_CKE_3

DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0
DDR1_CAB_9/DDR1_MA_0

DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2

DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8

DDR1_CAA_1/DDR1_MA_9
DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13

DDR1_CAA_9/DDR1_BG_1

DDR1_CAA_8/DDR1_ACT#

DDR ( L)/LP3-DDR (NIL)

DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSP_3/DDR0_DQSP_7
DDR1_DQSP_4/DDR1_DQSP_2
DDR1_DQSP_5/DDR1_DQSP_3
DDR1_DQSP_6/DDR1_DQSP_6
DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8
DDR1_DQSN_8/DDR1_DQSN_8

LP3/DDR

NC/DDR1_CKP_2
NC/DDR1_CKN_2
NC/DDR1_CKP_3
NC/DDR1_CKN_3

NC/DDR1_CS#_2
NC/DDR1_CS#_3

NC/DDR1_ODT_1
NC/DDR1_ODT_2
NC/DDR1_ODT_3

NC/DDR1_MA_3
NC/DDR1_MA_4

NC/DDR1_PAR

NC/DDR1_ALERT#

AM9
AN9
AM7
AM8
AM11
AM10
AJ10
AJ11

AT8
AT10
AT7
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8
AH9
AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10

AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9

AJ7
AR8

BN9
BL9
BG9
BC9
AC9
W9
R9
M9

BP9
BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CS#0
DDR_B_CS#1

DDR_B_ODT0
DDR_B_ODT1

DDR_B_MA16_RAS#
DDR_B_MA14_WE#
DDR_B_MA15_CAS#

DDR_B_BA0
DDR_B_BA1
DDR_B_BG0

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7

DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_BG1
DDR_B_ACT#

DDR_B_PAR
DDR_B_ALERT#

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DR_B_CLK0 <24>

D
DDR_B_CLK#0 <24>
DDR_B_CLK1 <24>
DDR_B_CLK#1 <24>

DDR_B_CKE0 <24>
DDR_B_CKE1 <24>

DDR_B_CS#0 <24>
DDR_B_CS#1 <24>

DDR_B_ODT0 <24>
DDR_B_ODT1 <24>

DDR_B_MA16_RAS# <24>
DDR_B_MA14_WE# <24>
DDR_B_MA15_CAS# <24>

DDR_B_BA0 <24>
DDR_B_BA1 <24>
DDR_B_BG0 <24>

DDR_B_MA0 <24>
DDR_B_MA1 <24>
DDR_B_MA2 <24>
DDR_B_MA3 <24>
DDR_B_MA4 <24>
DDR_B_MA5 <24>
DDR_B_MA6 <24>
DDR_B_MA7 <24>

DDR_B_MA8 <24>
DDR_B_MA9 <24>
DDR_B_MA10 <24>
DDR_B_MA11 <24>
DDR_B_MA12 <24>
DDR_B_MA13 <24>
DDR_B_BG1 <24>
DDR_B_ACT# <24>

DDR_B_PAR <24>
DDR_B_ALERT# <24>

DDR_B_DQS#0 <24>
DDR_B_DQS#1 <24>
DDR_B_DQS#2 <24>
DDR_B_DQS#3 <24>
DDR_B_DQS#4 <24>
DDR_B_DQS#5 <24>
DDR_B_DQS#6 <24>
DDR_B_DQS#7 <24>

DDR_B_DQS0 <24>
DDR_B_DQS1 <24>
DDR_B_DQS2 <24>
DDR_B_DQS3 <24>
DDR_B_DQS4 <24>
DDR_B_DQS5 <24>
DDR_B_DQS6 <24>
DDR_B_DQS7 <24>

For ECC DIMM

1 2

RC3 121_0402_1%

1 2

RC4 75_0402_1%

1 2

RC5 100_0402_1%

Trace Width/Space: 15 mil/ 25 mil

4 4

A

Max Trace Length: 500 mil

B

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

G1

DDR_RCOMP_0

H1

DDR_RCOMP_1

J2

DDR_RCOMP_2

CFL-H_BGA1440

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2 OF 13

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

Compal Secret Data

Compal Secret Data

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

C

Compal Secret Data

BN13
BP13
BR13

Deciphered Date

Deciphered Date

Deciphered Date

+0.6V_VREFCA
+0.6V_B_VREFDQ

+0.6V_VREFCA
+0.6V_B_VREFDQ

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

9 73Tuesday February 13 2018

9 73Tuesday February 13 2018

9 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

PEG&DMI

B

C

D

E

1 1

2 2

3 3

To DGPU
PEG Lane Reversed

PEG_CRX_C_GTX_P15<25>
PEG_CRX_C_GTX_N15<25>

PEG_CRX_C_GTX_P14<25>
PEG_CRX_C_GTX_N14<25>

PEG_CRX_C_GTX_P13<25>
PEG_CRX_C_GTX_N13<25>

PEG_CRX_C_GTX_P12<25>
PEG_CRX_C_GTX_N12<25>

PEG_CRX_C_GTX_P11<25>
PEG_CRX_C_GTX_N11<25>

PEG_CRX_C_GTX_P10<25>
PEG_CRX_C_GTX_N10<25>

PEG_CRX_C_GTX_P9<25>
PEG_CRX_C_GTX_N9<25>

PEG_CRX_C_GTX_P8<25>
PEG_CRX_C_GTX_N8<25>

PEG_CRX_C_GTX_P7<25>
PEG_CRX_C_GTX_N7<25>

PEG_CRX_C_GTX_P6<25>
PEG_CRX_C_GTX_N6<25>

PEG_CRX_C_GTX_P5<25>
PEG_CRX_C_GTX_N5<25>

PEG_CRX_C_GTX_P4<25>
PEG_CRX_C_GTX_N4<25>

PEG_CRX_C_GTX_P3<25>
PEG_CRX_C_GTX_N3<25>

PEG_CRX_C_GTX_P2<25>
PEG_CRX_C_GTX_N2<25>

PEG_CRX_C_GTX_P1<25>
PEG_CRX_C_GTX_N1<25>

PEG_CRX_C_GTX_P0<25>
PEG_CRX_C_GTX_N0<25>

+VCCIO

To PCH

1 2

CC6 0.22U_0201_6.3V6KVGA@

1 2

CC8 0.22U_0201_6.3V6KVGA@

1 2

CC10 0.22U_0201_6.3V6KVGA@

1 2

CC12 0.22U_0201_6.3V6KVGA@

1 2

CC14 0.22U_0201_6.3V6KVGA@

1 2

CC15 0.22U_0201_6.3V6KVGA@

1 2

CC3 0.22U_0201_6.3V6KVGA@

1 2

CC17 0.22U_0201_6.3V6KVGA@

1 2

CC19 0.22U_0201_6.3V6KVGA@

1 2

CC21 0.22U_0201_6.3V6KVGA@

1 2

CC5 0.22U_0201_6.3V6KVGA@

1 2

CC23 0.22U_0201_6.3V6KVGA@

1 2

CC25 0.22U_0201_6.3V6KVGA@

1 2

CC27 0.22U_0201_6.3V6KVGA@

1 2

CC29 0.22U_0201_6.3V6KVGA@

1 2

CC31 0.22U_0201_6.3V6KVGA@

1 2

CC33 0.22U_0201_6.3V6KVGA@

1 2

CC35 0.22U_0201_6.3V6KVGA@

1 2

CC37 0.22U_0201_6.3V6KVGA@

1 2

CC39 0.22U_0201_6.3V6KVGA@

1 2

CC41 0.22U_0201_6.3V6KVGA@

1 2

CC43 0.22U_0201_6.3V6KVGA@

1 2

CC45 0.22U_0201_6.3V6KVGA@

1 2

CC47 0.22U_0201_6.3V6KVGA@

1 2

CC49 0.22U_0201_6.3V6KVGA@

1 2

CC51 0.22U_0201_6.3V6KVGA@

1 2

CC53 0.22U_0201_6.3V6KVGA@

1 2

CC55 0.22U_0201_6.3V6KVGA@

1 2

CC57 0.22U_0201_6.3V6KVGA@

1 2

CC59 0.22U_0201_6.3V6KVGA@

1 2

CC61 0.22U_0201_6.3V6KVGA@

1 2

CC63 0.22U_0201_6.3V6KVGA@

1 2

RC6 24.9_0402_1%

DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_N0<15>

DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_N1<15>

DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_N2<15>

DMI_CRX_PTX_P3<15>
DMI_CRX_PTX_N3<15>

PEG_CRX_GTX_P15
PEG_CRX_GTX_N15

PEG_CRX_GTX_P14
PEG_CRX_GTX_N14

PEG_CRX_GTX_P13
PEG_CRX_GTX_N13

PEG_CRX_GTX_P12
PEG_CRX_GTX_N12

PEG_CRX_GTX_P11
PEG_CRX_GTX_N11

PEG_CRX_GTX_P10
PEG_CRX_GTX_N10

PEG_CRX_GTX_P9
PEG_CRX_GTX_N9

PEG_CRX_GTX_P8
PEG_CRX_GTX_N8

PEG_CRX_GTX_P7
PEG_CRX_GTX_N7

PEG_CRX_GTX_P6
PEG_CRX_GTX_N6

PEG_CRX_GTX_P5
PEG_CRX_GTX_N5

PEG_CRX_GTX_P4
PEG_CRX_GTX_N4

PEG_CRX_GTX_P3
PEG_CRX_GTX_N3

PEG_CRX_GTX_P2
PEG_CRX_GTX_N2

PEG_CRX_GTX_P1
PEG_CRX_GTX_N1

PEG_CRX_GTX_P0
PEG_CRX_GTX_N0

PEG_RCOMP

Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil

DMI_CRX_PTX_P0
DMI_CRX_PTX_N0

DMI_CRX_PTX_P1
DMI_CRX_PTX_N1

DMI_CRX_PTX_P2
DMI_CRX_PTX_N2

DMI_CRX_PTX_P3
DMI_CRX_PTX_N3

E25

PEG_RXP_0

D25

PEG_RXN_0

E24

PEG_RXP_1

F24

PEG_RXN_1

E23

PEG_RXP_2

D23

PEG_RXN_2

E22

PEG_RXP_3

F22

PEG_RXN_3

E21

PEG_RXP_4

D21

PEG_RXN_4

E20

PEG_RXP_5

F20

PEG_RXN_5

E19

PEG_RXP_6

D19

PEG_RXN_6

E18

PEG_RXP_7

F18

PEG_RXN_7

D17

PEG_RXP_8

E17

PEG_RXN_8

F16

PEG_RXP_9

E16

PEG_RXN_9

D15

PEG_RXP_10

E15

PEG_RXN_10

F14

PEG_RXP_11

E14

PEG_RXN_11

D13

PEG_RXP_12

E13

PEG_RXN_12

F12

PEG_RXP_13

E12

PEG_RXN_13

D11

PEG_RXP_14

E11

PEG_RXN_14

F10

PEG_RXP_15

E10

PEG_RXN_15

G2

PEG_RCOMP

D8

DMI_RXP_0

E8

DMI_RXN_0

E6

DMI_RXP_1

F6

DMI_RXN_1

D5

DMI_RXP_2

E5

DMI_RXN_2

J8

DMI_RXP_3

J9

DMI_RXN_3

CFL-H_BGA1440

@

FL-H

C

C1C

U

PEG_TXP_0
PEG_TXN_0

PEG_TXP_1
PEG_TXN_1

PEG_TXP_2
PEG_TXN_2

PEG_TXP_3
PEG_TXN_3

PEG_TXP_4
PEG_TXN_4

PEG_TXP_5
PEG_TXN_5

PEG_TXP_6
PEG_TXN_6

PEG_TXP_7
PEG_TXN_7

PEG_TXP_8
PEG_TXN_8

PEG_TXP_9
PEG_TXN_9

PEG_TXP_10

PEG_TXN_10

PEG_TXP_11

PEG_TXN_11

PEG_TXP_12

PEG_TXN_12

PEG_TXP_13

PEG_TXN_13

PEG_TXP_14

PEG_TXN_14

PEG_TXP_15

PEG_TXN_15

3 OF 13

DMI_TXP_0
DMI_TXN_0

DMI_TXP_1
DMI_TXN_1

DMI_TXP_2
DMI_TXN_2

DMI_TXP_3
DMI_TXN_3

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

PEG_CTX_GRX_P15
PEG_CTX_GRX_N15

PEG_CTX_GRX_P14
PEG_CTX_GRX_N14

PEG_CTX_GRX_P13
PEG_CTX_GRX_N13

PEG_CTX_GRX_P12
PEG_CTX_GRX_N12

PEG_CTX_GRX_P11
PEG_CTX_GRX_N11

PEG_CTX_GRX_P10
PEG_CTX_GRX_N10

PEG_CTX_GRX_P9
PEG_CTX_GRX_N9

PEG_CTX_GRX_P8
PEG_CTX_GRX_N8

PEG_CTX_GRX_P7
PEG_CTX_GRX_N7

PEG_CTX_GRX_P6
PEG_CTX_GRX_N6

PEG_CTX_GRX_P5
PEG_CTX_GRX_N5

PEG_CTX_GRX_P4
PEG_CTX_GRX_N4

PEG_CTX_GRX_P3
PEG_CTX_GRX_N3

PEG_CTX_GRX_P2
PEG_CTX_GRX_N2

PEG_CTX_GRX_P1
PEG_CTX_GRX_N1

PEG_CTX_GRX_P0
PEG_CTX_GRX_N0

DMI_CTX_PRX_P0
DMI_CTX_PRX_N0

DMI_CTX_PRX_P1
DMI_CTX_PRX_N1

DMI_CTX_PRX_P2
DMI_CTX_PRX_N2

DMI_CTX_PRX_P3
DMI_CTX_PRX_N3

12

CC70.22U_0201_6.3V6K VGA@

12

CC90.22U_0201_6.3V6K VGA@

12

CC110.22U_0201_6.3V6K VGA@

12

CC130.22U_0201_6.3V6K VGA@

12

CC10.22U_0201_6.3V6K VGA@

12

CC20.22U_0201_6.3V6K VGA@

12

CC160.22U_0201_6.3V6K VGA@

12

CC180.22U_0201_6.3V6K VGA@

12

CC200.22U_0201_6.3V6K VGA@

12

CC40.22U_0201_6.3V6K VGA@

12

CC220.22U_0201_6.3V6K VGA@

12

CC240.22U_0201_6.3V6K VGA@

12

CC260.22U_0201_6.3V6K VGA@

12

CC280.22U_0201_6.3V6K VGA@

12

CC300.22U_0201_6.3V6K VGA@

12

CC320.22U_0201_6.3V6K VGA@

12

CC340.22U_0201_6.3V6K VGA@

12

CC360.22U_0201_6.3V6K VGA@

12

CC380.22U_0201_6.3V6K VGA@

12

CC400.22U_0201_6.3V6K VGA@

12

CC420.22U_0201_6.3V6K VGA@

12

CC440.22U_0201_6.3V6K VGA@

12

CC460.22U_0201_6.3V6K VGA@

12

CC480.22U_0201_6.3V6K VGA@

12

CC500.22U_0201_6.3V6K VGA@

12

CC520.22U_0201_6.3V6K VGA@

12

CC540.22U_0201_6.3V6K VGA@

12

CC560.22U_0201_6.3V6K VGA@

12

CC580.22U_0201_6.3V6K VGA@

12

CC600.22U_0201_6.3V6K VGA@

12

CC620.22U_0201_6.3V6K VGA@

12

CC640.22U_0201_6.3V6K VGA@

DMI_CTX_PRX_P0 <15>
DMI_CTX_PRX_N0 <15>

DMI_CTX_PRX_P1 <15>
DMI_CTX_PRX_N1 <15>

DMI_CTX_PRX_P2 <15>
DMI_CTX_PRX_N2 <15>

DMI_CTX_PRX_P3 <15>
DMI_CTX_PRX_N3 <15>

PEG_CTX_C_GRX_P15 <25>
PEG_CTX_C_GRX_N15 <25>

PEG_CTX_C_GRX_P14 <25>
PEG_CTX_C_GRX_N14 <25>

PEG_CTX_C_GRX_P13 <25>
PEG_CTX_C_GRX_N13 <25>

PEG_CTX_C_GRX_P12 <25>
PEG_CTX_C_GRX_N12 <25>

PEG_CTX_C_GRX_P11 <25>
PEG_CTX_C_GRX_N11 <25>

PEG_CTX_C_GRX_P10 <25>
PEG_CTX_C_GRX_N10 <25>

PEG_CTX_C_GRX_P9 <25>
PEG_CTX_C_GRX_N9 <25>

PEG_CTX_C_GRX_P8 <25>
PEG_CTX_C_GRX_N8 <25>

PEG_CTX_C_GRX_P7 <25>
PEG_CTX_C_GRX_N7 <25>

PEG_CTX_C_GRX_P6 <25>
PEG_CTX_C_GRX_N6 <25>

PEG_CTX_C_GRX_P5 <25>
PEG_CTX_C_GRX_N5 <25>

PEG_CTX_C_GRX_P4 <25>
PEG_CTX_C_GRX_N4 <25>

PEG_CTX_C_GRX_P3 <25>
PEG_CTX_C_GRX_N3 <25>

PEG_CTX_C_GRX_P2 <25>
PEG_CTX_C_GRX_N2 <25>

PEG_CTX_C_GRX_P1 <25>
PEG_CTX_C_GRX_N1 <25>

PEG_CTX_C_GRX_P0 <25>
PEG_CTX_C_GRX_N0 <25>

To DGPU
PEG Lane Reversed

To PCH

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PEG/DMI

PEG/DMI

PEG/DMI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

D

Date Sheet of

10 73Tuesday February 13 2018

10 73Tuesday February 13 2018

10 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

571391_CFL_H_PDG_Rev0p5

1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch).

2. Route the Alert signal between the Clock and the Data signals.

1 1

3. Place those resistors close CPU side.

Sensitive

Sensitive

H_CPUPW RGD<19>
H_PLTRST_CPU#<18>
H_PM_SYNC_R<18>

H_PECI<18,43>

PCH_THERMTRIP#_R<18>

PROC_SELECT#

2 2

should be unconnected on CFL processor
EDS1.2 8/21

@ESD@

1 2

@ESD@

1 2

ESD@

1 2

@ESD@

1 2

ESD@

1 2

CC95.1U_0402_16V7K

CC65.1U_0402_16V7K

CC661000P_0402_50V7K

CC67.1U_0402_16V7K

CC681000P_0402_50V7K

H_PECI

H_CPUPW RGD

H_PROCHOT#_R

H_THERMTRIP#

EC_VCCST_PG_R

Near CPU side

follow 1050 Request

+1.05V_VCCST

3 3

8/21

1 2

RH1 1K_0402_5%

+1.05VS_VCCSTG

H_THERMTRIP#

PCH_CPU_24M_CLK_P<16>
PCH_CPU_24M_CLK_N<16>

PCH_CPU_PCIBCLK_P<16>
P

CH_CPU_PCIBCLK_N<16>

PCH_CPU_BCLK_P<16>
P

CH_CPU_BCLK_N<16>

CPU_SVID_CLK_R<60,61>

RC17 0_0402_5%@

B

1 2

DDR_PG_CTRL

P

CH_CPU_BCLK_P

P

CH_CPU_BCLK_N

PCH_CPU_PCIBCLK_P
PCH_CPU_PCIBCLK_N

PCH_CPU_24M_CLK_P
PCH_CPU_24M_CLK_N

CPU_SVID_ALERT#
CPU_SVID_DAT_R

H_PROCHOT#_R
DDR_PG_CTRL

EC_VCCST_PG

H_CPUPW RGD
H_PLTRST_CPU#
H_PM_SYNC_R
H_PM_DOWN
H_PECI
H_THERMTRIP#

TC5@

TC6@

SKTOCC#

CATERR#

2
3

74AUP1G07GW_TSSOP5

NC1VCC
A
GND

UC3

Y

BH31
BH32
BH29
BR30

BT13

BT31
BP35
BM34
BP31
BT34

BR33

BM30
AT13

AW13

AU13
AY13

U

B31
A32

D35
C36

E31
D31

H13

J31

BN1

CFL-H_BGA1440

@

+1.2V_VDDQ

5

4

C

C1E

B

CLKP

BCLKN
PCI_BCLKP

PCI_BCLKN
CLK24P

CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD
PROCPWRGD

RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#
ZVM#

MSM#
RSVD1

RSVD2

.1U_0402_16V7K

SM_PG_CTRL

CFL-H

5 OF 13

CC69

C
CFG_11
C
CFG_13
CFG_14
CFG_15

CFG_17
CFG_16
CFG_19
CFG_18

BPM#_0
BPM#_1
BPM#_2
BPM#_3

PROC_TDO

PROC_TDI
PROC_TMS
PROC_TCK

PROC_TRST#

PROC_PREQ#

PROC_PRDY#

CFG_RCOMP

12

BN25

C

FG_0

BN27

CFG_1

BN26

C

FG_2

BN28

CFG_3

BR20

CFG_4

BM20

C

FG_5

BT20

CFG_6

BP20

CFG_7

BR23

CFG_8

BR22

CFG_9

BT23

FG_10

BT22
BM19

FG_12

BR19
BP19
BT19

BN23
BP23
BP22
BN22

XDP_BPM#0

BR27

XDP_BPM#1

BT27

XDP_BPM#2

BM31

XDP_BPM#3

BT30

BT28
BL32
BP28
BR28

BP30
BL30
BP27

CFG_RCOMP

BT25

Trace Width/Space: 4 mil/ 12 mil
Max Trace Length: 600 mil

+3VS

12

RC23
330K_0402_5%

PU 330K follow CRB
8/21

C

FG0

C

FG2

CFG4
C

FG5
CFG6
CFG7

CPU_XDP_TDO
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TCK0

CPU_XDP_TRST#
XDP_PREQ#
XDP_PRDY#

RC18

1 2

D

TC1 @
TC2 @
TC3 @
TC4 @

CPU_XDP_TDO <19>
CPU_XDP_TDI <19>
CPU_XDP_TMS <19>
CPU_XDP_TCK0 <19>

CPU_XDP_TRST# <22>

TC19 @
TC20 @

49.9_0402_1%

SM_PG_CTRL <56>

+1.05VS_VCCSTG

RC76 51_0402_5%CMC@
RC77 51_0402_5%CMC@
RC78 51_0402_5%CMC@

RC79 51_0402_5%CMC@
RC80 51_0402_5%@
RC81 51_0402_5%@

E

C

FG0
CFG2
C

FG4
CFG5
CFG6
C

FG7

The CFG signals have a default value of '1' if not terminated on the board.

CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted

1 = (Default) Normal Operation;

*

0 = Stall.

CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.

1 = Normal operation
0 = Lane numbers reversed.

*

CFG[4]: eDP enable:

1 = Disabled.
0 = Enabled.

*

CFG[6:5]: PCI Express* Bifurcation:

00 = 1 x8, 2 x4 PCI Express*
01 = reserved
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*

*

CFG[7]: PEG Training:

*

1 = (default) PEG Train immediately following RESET# de assertion.
0 = PEG Wait for BIOS for training.

*CFG Pin Use CMC debug on DDX03 R02 Schematic.

To be confirm

1 2

R

C7 1K_0402_5%@

1 2

RC8 1K_0402_5%

1 2

R

C9 1K_0402_5%

1 2

RC10 1K_0402_5%@

1 2

RC11 1K_0402_5%@

1 2

R

C12 1K_0402_5%@

XDP_PREQ#
XDP_PRDY#

XDP_PREQ# <22>
XDP_PRDY# <22>

Place to CPU side

12

12

12

CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_TDO

Place to CPU side

12

12

12

CPU_XDP_TCK0
PCH_JTAG_TCK1
CPU_XDP_TRST#

PCH_JTAG_TCK1 <19>

12

RC21
1K_0402_5%

1 2

H_PROCHOT#<43,54>

4 4

EC_VCCST_PG_R<43,51>

H_PM_DOWN_R<18>

A

RC14 499_0402_1%

+1.05V_VCCST

12

RC22
1K_0402_5%

1 2

RC15 60.4_0402_1%

1 2

RC16 20_0402_5%

12

RH2

@

13_0402_5%

H_PROCHOT#_R

EC_VCCST_PG

H_PM_DOWN

SVID

B

+1.05V_VCCST

12

12

RC19

56_0402_1%

CPU_SVID_ALERT#_R<60,61>

CPU_SVID_DAT_R<60,61>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RC20
100_0402_1%

1 2

RC13 220_0402_5%

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

C

CPU_SVID_ALERT#

CPU_SVID_DAT_R

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

D

Date Sheet of

11 73Tuesday February 13 2018

11 73Tuesday February 13 2018

11 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

B

C

D

E

GT
32000mA(Hexa Core GT2)

VCC_GT

+

AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37

1 1

2 2

3 3

4 4

AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35

AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38

AY29

AY30

AY31

AY32

AY35

AY36

AY37

AY38

BA13

BA14

BA29

BA30

BA31

BA32

BA33

BA34

BA35

BA36

BB13

BB14

BB31

BB32

BB33

BB34

BB35

BB36

BB37

BB38

BC29

BC30

BC31

BC32

BC35

BC36

BC37

BC38

BD13

BD14

BD29

BD30

BD31

BD32

BD33

BD34

BP37

BP38

BR15

BR16

BR17

C

U

C1K

VCCGT1
V

CCGT2
VCCGT3
VCCGT4
V

CCGT5
VCCGT6
VCCGT7
VCCGT8
VCCGT9

CCGT10

V
VCCGT11

CCGT12

V
VCCGT13
VCCGT14
VCCGT15
VCCGT16
VCCGT17
VCCGT18
VCCGT19
VCCGT20
VCCGT21
VCCGT22
VCCGT23
VCCGT24
VCCGT25
VCCGT26
VCCGT27
VCCGT28
VCCGT29
VCCGT30
VCCGT31
VCCGT32
VCCGT33
VCCGT34
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT49
VCCGT50
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT55
VCCGT56
VCCGT57
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT62
VCCGT63
VCCGT64
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT159
VCCGT160
VCCGT161
VCCGT162
VCCGT163

11 OF 3

CFL-H_BGA1440

@

FL-H

VCCGT80
V

CCGT81
VCCGT82
VCCGT83
V

CCGT84
VCCGT85
VCCGT86
VCCGT87
VCCGT88

CCGT89

V
VCCGT90

CCGT91

V
VCCGT92
VCCGT93
VCCGT94
VCCGT95
VCCGT96
VCCGT97
VCCGT98
VCCGT99

VCCGT100
VCCGT101
VCCGT102
VCCGT103
VCCGT104
VCCGT105
VCCGT106
VCCGT107
VCCGT108
VCCGT109
VCCGT110
VCCGT111
VCCGT112
VCCGT113
VCCGT114
VCCGT115
VCCGT116
VCCGT117
VCCGT118
VCCGT119
VCCGT120
VCCGT121
VCCGT122
VCCGT123
VCCGT124
VCCGT125
VCCGT126
VCCGT127
VCCGT128
VCCGT129
VCCGT130
VCCGT131
VCCGT132
VCCGT133
VCCGT134
VCCGT135
VCCGT136
VCCGT137
VCCGT138
VCCGT139
VCCGT140
VCCGT141
VCCGT142
VCCGT143
VCCGT144
VCCGT145
VCCGT146
VCCGT147
VCCGT148
VCCGT149
VCCGT150
VCCGT151
VCCGT152
VCCGT153
VCCGT154
VCCGT155
VCCGT156
VCCGT157
VCCGT158
VCCGT164
VCCGT165
VCCGT166
VCCGT167
VCCGT168

VSSGT_SENSE
VCCGT_SENSE

1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils

2. Maintain 25-mil separation distance away from any other dynamic signals.

BD35
BD36
BE31
BE32
BE33
BE34
BE35
BE36
BE37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BJ16
BJ17
BJ19
BJ20
BJ21
BJ23
BJ24
BJ26
BJ27
BJ37
BJ38
BK16
BK17
BK19
BK20
BK21
BK23
BK24
BK26
BK27
BL15
BL16
BL17
BL23
BL24
BL25
BL26
BL27
BL28
BL36
BL37
BM15
BM16
BM17
BM36
BM37
BN15
BN16
BN17
BN36
BN37
BN38
BP15
BP16
BP17
BR37
BT15
BT16
BT17
BT37

AH37
AH38

VCC_GT

+

VSSGT_SENSE
VCCGT_SENSE

VCC_CORE

+

VSSGT_SENSE <60>

VCCGT_SENSE <60>

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38

AF29
AF30
AF31
AF32
AF33
AF34
AF35
AF36
AF37

AF38
AG14
AG31
AG32
AG33
AG34
AG35
AG36

U

C1I

VCC1
V

CC2
VCC3
VCC4
V

CC5
VCC6
VCC7
VCC8
VCC9

CC10

V
VCC11

CC12

V
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63

CFL-H_BGA1440

@

VCC_CORE

AH13
AH14
AH29
AH30
AH31
AH32
AJ14
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP30
AP31
AP32
AP35
AP36
AP37
AP38
K13

AG37
AG38

+

1

28000mA(Hexa Core GT2)

VCCSENSE
VSSSENSE

VCCSENSE <60>

VSSSENSE <60>

FL-H

C

VCC64
V

CC65
VCC66
VCC67
V

CC68
VCC69
VCC70
VCC71
VCC72

CC73

V
VCC74

CC75

V
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC112
VCC113
VCC114
VCC115
VCC116
VCC117
VCC118
VCC119
VCC120
VCC121
VCC122
VCC123
VCC124

VCC_SENSE

9 OF 13

VSS_SENSE

1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils

2. Maintain 25-mil separation distance away from any other dynamic signals.

VCC_CORE

+

K14

L13

L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
V32
V33
V34
V35
V36
V37
V38

W13
W14
W29
W30
W31
W32

CFL-H_BGA1440

@

VCC1
V
VCC3
VCC4
V
VCC6
VCC7
VCC8
VCC9
V
VCC11
V
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63

C1J

U

CC2

CC5

CC10
CC12

FL-H

C

10 OF 13

VCC64
V

CC65
VCC66
VCC67
V

CC68
VCC69
VCC70
VCC71
VCC72

CC73

V
VCC74

CC75

V

W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36

VCC_CORE

+

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

Compal Secret Data

Compal Secret Data

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

12 73Tuesday February 13 2018

12 73Tuesday February 13 2018

12 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

+1.2V_VDDQ_CPU

+

VCC_SA

+

VCC_SA

Max: 11100mA

1 1

+VCC_IO
Max: 6400mA

2 2

+VCCIO

K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37

L38
M29
M30
M31
M32
M33
M34
M35
M36

AG12

G15
G17
G19
G21

H15

H16

H17

H19

H20

H21

H26

H27

J30

J15
J16
J17
J19
J20
J21
J26
J27

CFL-H_BGA1440

@

U

C1L

VCCSA1
V

CCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6

CCSA7

V
VCCSA8

CCSA9

V
VCCSA10
VCCSA11
VCCSA12
VCCSA13
VCCSA14
VCCSA15
VCCSA16
VCCSA17
VCCSA18
VCCSA19
VCCSA20
VCCSA21
VCCSA22

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21

CFL-H

12 OF 13

VDDQ1
V

DDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6

DDQ7

V
VDDQ8

DDQ9

V

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25

VCCPLL_OC1
VCCPLL_OC2
VCCPLL_OC3

VCCST
VCCSTG2
VCCSTG1

VCCPLL1
VCCPLL2

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

Max: 3300mA

+

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12

+1.2V_VCCPLL_OC

BH13
BJ13
G11

H30
H29
G30
H28

J28

M38
M37

H14
J14

B

1.2V_VDDQ_CPU

Max: 60mA

Max: 20mA

Max: 150mA

VCCIO_SENSE
VSSIO_SENSE

1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils

2. Maintain 25-mil separation distance away from any other dynamic signals.

+1.2V_VDDQ_CPU

3.3A

+1.2V_VCCPLL_OC
Max: 130mA

+1.05V_VCCST

+1.05VS_VCCSTG

+1.05V_VCCSFR

VCCSA_SENSE
VSSSA_SENSE

@

JUMP_43X118

@

JUMP_43X118

JPC1

112

JPC2

112

2

2

+

1.2V_VDDQ

VCCSA_SENSE <61>

VSSSA_SENSE <61>

VCCIO_SENSE <59>

VSSIO_SENSE <59>

+

1.2V_VDDQ_CPU

C

10U_0603_6.3V6M

10U_0402_6.3V6M

1

CC70

2

10U_0603_6.3V6M

1

CC71

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VDDQ_CPU: 10uF * 12 22uF * 4

1

1

CC72

2

2

10U_0603_6.3V6M

CC73

10U_0603_6.3V6M

1

2

RC24 0_0402_5%@

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

CC74

2

CC76

CC75

2

2

PLACE CAP BACKSIDE

+1.2V_VCCPLL_OC+1.2V_VDDQ

1 2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VCCPLL_OC: 1uF * 2

PLACE CAP BACKSIDE

+1.05V_VCCST

1

2

D

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

CC78

CC77

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CC86

2

2

1 2

RC25 0_0402_5%@

1U_0201_6.3V6M

CC92

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1

CC80

CC79

2

CC87

22U_0603_6.3V6M

10U_0603_6.3V6M

1

CC81

2

+VCCIO

10U_0603_6.3V6M

1

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+0.95VS_VCCIO: 10uF * 12 22uF * 4

+1.05V_VCCSFR

150mA

22U_0603_6.3V6M

1

1

CC82

2

2

10U_0603_6.3V6M

1

1

CC89

CC88

2

2

1U_0201_6.3V6M

1

CC93

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1

E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CC84

CC83

2

10U_0603_6.3V6M

CC90

CC85

2

10U_0402_6.3V6M

@

1

CC91

2

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

3 3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

+1.05VS_VCCSTG

1U_0201_6.3V6M

1

CC94

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

13 73Tuesday February 13 2018

13 73Tuesday February 13 2018

13 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

C

FL-H

U

C1F

A10

VSS_1

A12

V

SS_2

A16

VSS_3

A18

VSS_4

A20

V

SS_5

A22

VSS_6

A24

VSS_7

A26

VSS_8

AA12
AA29
AA30
AB33
AB34

AC12

AC37
AC38

AD10
AD11
AD12
AD29
AD30

AE33
AE34

AF12
AF13
AF14

AG10
AG11
AG13
AG29
AG30

AG6
AG7

AG8
AH12
AH33
AH34
AH35
AH36

AJ13

AJ37
AJ38

AK29
AK30

A28
A30

AB6
AC1

AC2
AC3

AC4
AC5
AC6

AD6
AD8
AD9

AE6
AF1

AF2
AF3
AF4

AH6
AJ1

AJ2
AJ3

AJ4
AJ5
AJ6

Y10
Y11
Y13
Y14
Y37
Y38

A6
A9

W4
W5

Y7
Y8
Y9

VSS_9

SS_10

V
VSS_11

SS_12

V
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80

6 OF 13

VSS_81

CFL-H_BGA1440

@

1 1

2 2

3 3

VSS_82
V

SS_83
VSS_84
VSS_85
V

SS_86
VSS_87
VSS_88
VSS_89
VSS_90

SS_91

V
VSS_92

SS_93

V
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162

AK4
AL10
AL12
AL14
AL33
AL34
AL4
AL7
AL8
AL9
AM1
AM12
AM2
AM3
AM37
AM38
AM4
AM5
AN12
AN29
AN30
AN5
AN6
AP10
AP11
AP12
AP33
AP34
AP8
AP9
AR1
AR13
AR14
AR2
AR29
AR3
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR4
AR5
AT29
AT30
AT6
AU10
AU11
AU12
AU33
AU34
AU6
AU7
AU8
AU9
AV37
AV38
AW1
AW12
AW2
AW29
AW3
AW30
AW4
U6
V12
V29
V30
A14
AD7
V6
W1
W12
W2
W3
W33
W34

AW5
AY12
AY33
AY34

BA10
BA11
BA12
BA37
BA38

BB12
BB29
BB30

BC12
BC13
BC14
BC33
BC34

BC6
BD10
BD11
BD12
BD37

BD6

BD7

BD8

BD9

BE29
BE30

BF12
BF33
BF34

BG12
BG13
BG14
BG37
BG38

BG6

BH1
BH10
BH11
BH12
BH14

BH2

BH3

BH4

BH5

BH6

BH7

BH8

BH9

BJ12
BJ14

BA6
BA7
BA8
BA9
BB1

BB2
BB3
BB4

BB5
BB6

BE1
BE2

BE3
BE4

BE5
BE6

BF6

T33
T34

U37
U38

B9

T2
T3

T4
T5
T7
T8
T9

U

C1G

VSS_163
V

SS_164
VSS_165
VSS_166
V

SS_167
VSS_168
VSS_169
VSS_170
VSS_171

SS_172

V
VSS_173

SS_174

V
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

CFL-H_BGA1440

@

C

FL-H

7 OF 13

VSS_244
V

SS_245
VSS_246
VSS_247
V

SS_248
VSS_249
VSS_250
VSS_251
VSS_252

SS_253

V
VSS_254

SS_255

V
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324

B

FL-H

C

C1H

U

BN4

V

V

SS_325

BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK13
BK14
BK15
BK18
BK22
BK25
BK29
BK6
BL13
BL14
BL18
BL19
BL20
BL21
BL22
BL29
BL33
BL35
BL38
BL6
BM11
BM12
BM13
BM14
BM18
BM2
BM21
BM22
BM23
BM24
BM25
BM26
BM27
BM28
BM29
BM3
BM33
BM35
BM38
BM5
BM6
BM7
BM8
BM9
BN12
BN14
BN18
BN19
BN2
BN20
BN21
BN24
BN29
BN30
BN31
BN34
P38
P6
R12
R29
AY14
BD38
R30
T1
T10
T11
T12
T13
T14

BN7
BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34

BP7
BR12
BR14
BR18
BR21
BR24
BR25
BR26
BR29
BR34
BR36

BR7

BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32

BT5

C11

C13

C15

C17

C19

C21

C23

C25

C27

C29

C31

C37

D10

D12

D14

D16

D18

D20

D22

D24

D26

D28

D30

D33

E34

E35

E38

N33

N34

P12

P37

M14

C5
C8
C9

D3

D6
D9

E4
E9
N3

N4
N5
N6
N7
N8
N9

M6

N1
F11
F13

CFL-H_BGA1440

@

VSS_326
V

SS_327
VSS_328
VSS_329
V

SS_330
VSS_331
VSS_332
VSS_333
VSS_334

SS_335

V
VSS_336

SS_337

V
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402
VSS_403
VSS_404
VSS_405
VSS_406
VSS_407
VSS_408

VSS_410
V
VSS_412
VSS_413
V
VSS_415
VSS_416
VSS_417
VSS_418
V
VSS_420
V
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
VSS_434
VSS_435
VSS_436
VSS_437
VSS_438
VSS_439
VSS_440
VSS_441
VSS_442
VSS_443
VSS_444
VSS_445
VSS_446
VSS_447
VSS_448
VSS_449
VSS_450
VSS_451
VSS_452
VSS_453
VSS_454
VSS_455
VSS_456
VSS_457
VSS_458
VSS_459
VSS_460
VSS_461
VSS_462
VSS_463
VSS_464
VSS_465
VSS_466
VSS_467
VSS_468
VSS_469
VSS_470
VSS_471
VSS_472
VSS_473
VSS_474
VSS_475
VSS_476
VSS_477
VSS_478
VSS_479

VSS_A34

VSS_B37

VSS_BR38

VSS_BT3
VSS_BT35
VSS_BT36

VSS_BT4

8 OF 13

VSS_D38

SS_409
SS_411

SS_414

SS_419
SS_421

VSS_A3
VSS_A4

VSS_B3

VSS_C2

F15
F17
F19
F2
F21
F23
F25
F27
F29
F3
F31
F36
F4
F5
F8
F9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
G4
G5
G6
G8
G9
H11
H12
H18
H22
H25
H32
H35
J10
J18
J22
J25
J32
J33
J36
J4
J7
K1
K10
K11
K2
K3
K38
K4
K5
K7
K8
K9
L29
L30
L33
L34
M12
M13
N10
N11
N12
N2
BT8
BR9

A3
A34
A4
B3
B37
BR38
BT3
BT35
BT36
BT4
C2
D38

C

I

mpedance Spectrum Tool Trigger

PCH_TRIGOUT_R<22>
CPU_TRIGOUT_R<22>

1 2

RC26 30_0402_5%

D

TC7@

IST_TRIG

T

C8@
TC9@
TC10@

TC11@
TC12@

PCH_TRIGOUT_R
CPU_TRIGOUT

BR1

BN35

BN33

BL34

N29

R14
AE29
AA14
AP29
AP14

H23

C30

BR35
BR31
BH30

BT2

H24

A36
A37

F30

E30

B30

E2
E3
E1
D1

J24

J23

G3

J3

U

C1M

RSVD_TP5
IST_TRIG
R

SVD_TP4

RSVD_TP3
RSVD_TP1

RSVD_TP2
RSVD15
RSVD28

RSVD27
RSVD14
RSVD13

RSVD30
RSVD31
RSVD2
RSVD1
RSVD5
RSVD4
VSS_A36

VSS_A37
PROC_TRIGIN

PROC_TRIGOUT
RSVD24

RSVD23

RSVD7
RSVD21

RSVD26
RSVD29

RSVD19
RSVD18
RSVD9

CFL-H_BGA1440

@

FL-H

C

13 OF 13

E

BK28

RSVD11

BJ28

RSVD10

BL31

RSVD12

AJ8

RSVD3

G13

RSVD25

C38

RSVD22

C1

RSVD20

BR2

RSVD17

BP1

RSVD16

B38

RSVD8

B2

RSVD6

Add for Corner NCTF testing

TC13 @
TC14 @
TC15 @
TC16 @
TC17 @
TC18 @

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

D

Date Sheet of

14 73Tuesday February 13 2018

14 73Tuesday February 13 2018

14 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

MI_CTX_PRX_N0<10>

D

H1

U

CFL-H_BGA1440

S IC FH82HM370 SR40B B0 BGA 874P PCH-H ABO!
SA0000BVP10

1 1

2 2

3 3

PCH@

DMI_CTX_PRX_P0<10>

DMI_CRX_PTX_N0<10>

D

MI_CRX_PTX_P0<10>

DMI_CTX_PRX_N1<10>
DMI_CTX_PRX_P1<10>

D

MI_CRX_PTX_N1<10>

D

MI_CRX_PTX_P1<10>

DMI_CTX_PRX_N2<10>
DMI_CTX_PRX_P2<10>

DMI_CRX_PTX_N2<10>

MI_CRX_PTX_P2<10>

D

DMI_CTX_PRX_N3<10>

MI_CTX_PRX_P3<10>

D

DMI_CRX_PTX_N3<10>

DMI_CRX_PTX_P3<10>

B

MI_CTX_PRX_N0

D

MI_CTX_PRX_P0

D

D

MI_CRX_PTX_N0

D

MI_CRX_PTX_P0

D

MI_CTX_PRX_N1

DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
D

MI_CRX_PTX_P1

DMI_CTX_PRX_N2

DMI_CTX_PRX_P2

MI_CRX_PTX_N2

D
DMI_CRX_PTX_P2

MI_CTX_PRX_N3

D

DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3

H1B

U

K34

MI0_RXN

D

J35

DMI0_RXP

C33

D

MI0_TXN

B33

DMI0_TXP

G33

D

MI1_RXN

F34

DMI1_RXP

C32

DMI1_TXN

B32

D

MI1_TXP

K32

DMI2_RXN

J32

DMI2_RXP

C31

DMI2_TXN

B31

DMI2_TXP

G30

MI3_RXN

D

F30

DMI3_RXP

C29

MI3_TXN

D

B29

DMI3_TXP

A25

RSVD

B25

RSVD

P24

RSVD

R24

RSVD

C26

RSVD

B26

RSVD

F26

RSVD

G26

RSVD

B27

RSVD

C27

RSVD

L26

RSVD

M26

RSVD

D29

RSVD

E28

RSVD

K29

RSVD

M29

RSVD

G17

PCIE1_RXN/USB31_7_RXN

F16

PCIE1_RXP/USB31_7_RXP

A17

PCIE1_TXN/USB31_7_TXN

B17

PCIE1_TXP/USB31_7_TXP

R21

PCIE2_RXN/USB31_8_RXN

P21

PCIE2_RXP/USB31_8_RXP

B18

PCIE2_TXN/USB31_8_TXN

C18

PCIE2_TXP/USB31_8_TXP

K18

PCIE3_RXN/USB31_9_RXN

J18

PCIE3_RXP/USB31_9_RXP

B19

PCIE3_TXN/USB31_9_TXN

C19

PCIE3_TXP/USB31_9_TXP

N18

PCIE4_RXN/USB31_10_RXN

R18

PCIE4_RXP/USB31_10_RXP

D20

PCIE4_TXN/USB31_10_TXN

C20

PCIE4_TXP/USB31_10_TXP

F20

PCIE5_RXN

G20

PCIE5_RXP

B21

PCIE5_TXN

A22

PCIE5_TXP

K21

PCIE6_RXN

J21

PCIE6_RXP

D21

PCIE6_TXN

C21

PCIE6_TXP

B23

PCIE7_TXP

C23

PCIE7_TXN

J24

PCIE7_RXP

L24

PCIE7_RXN

F24

PCIE8_RXN

G24

PCIE8_RXP

B24

PCIE8_TXN

C24

PCIE8_TXP

CNP-H_BGA874

@

C

CNP-H

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_F15/USB2_OC4#
GPP_F16/USB2_OC5#
GPP_F17/USB2_OC6#
GPP_F18/USB2_OC7#

USB2_VBUSSENSE

2 OF 13

SB2N_1

U
USB2P_1
U

SB2N_2
USB2P_2
U

SB2N_3
USB2P_3
USB2N_4
U

SB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6

SB2N_7

U
USB2P_7

SB2N_8

U
USB2P_8
USB2N_9
USB2P_9

USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

USB2_COMP

RSVD1

USB2_ID

GPD7

PCIE24_TXP
PCIE24_TXN
PCIE24_RXP

PCIE24_RXN

PCIE23_TXP
PCIE23_TXN
PCIE23_RXP

PCIE23_RXN

PCIE22_TXP
PCIE22_TXN
PCIE22_RXP

PCIE22_RXN

PCIE21_TXP
PCIE21_TXN
PCIE21_RXP

PCIE21_RXN

Rev1.0

J3
J2
N13
N15
K4
K3
M10
L9
M1
L2
K7
K6
L4
L3
G4
G5
M6
N8
H3
H2
R10
P9
G1
G2
N3
N2
E5
F6

AH36
AL40
AJ44
AL41
AV47
AR35
AR37
AV43

F4
F3
U13
G3

BE41
G45

G46
Y41
Y40
G48
G49
W44
W43
H48
H47
U41
U40
F46
G47
R44
T43

SB20_N1

U

SB20_P1

U
U

SB20_N2

U

SB20_P2

U

SB20_N3
USB20_P3
USB20_N4
U

SB20_P4
USB20_N5
USB20_P5

SB20_N6

U
USB20_P6

USB20_N8
USB20_P8

USB20_N14
USB20_P14

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

USB2_RCOMP
USB2_VBUS_SENSE

USB2_ID

GPD_7

D

SB20_N1 <46>

U

SB20_P1 <46>

U
U

SB20_N2 <45>

U

SB20_P2 <45>
USB20_N3 <48>
USB20_P3 <48>
USB20_N4 <48>
USB20_P4 <48>

SB20_N5 <37>

U
USB20_P5 <37>

SB20_N6 <37>

U
USB20_P6 <37>

USB20_N8 <50>
USB20_P8 <50>

USB20_N14 <41>
USB20_P14 <41>

USB_OC0# <44>
USB_OC1# <46>

1 2

RH4 113_0402_1%

1 2

RH5 0_0402_5%@

1 2

RH6 0_0402_5%@

E

SB3 MB

U
TYPE C

USB2 (SUB/B)

amera

C
TS

FingerPrint

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

10K_0804_8P4R_5%

RPH1

3VALW_PCH_PRIM

+

18
27
36
45

FOR CNVI follow 571906_CNL_PCH_TA_WW11.pdf

BT

+3VALW

12

RH3

GPD_7

STRAP

X'tal Input:
High: Differential
Low: Single ended

10K_0402_5%

12

RH7
10K_0402_5%

@

The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes

— A maximum of 16 PCIe* Ports (or devices) can be enabled

When a GbE Port is enabled, the maximum number of PCIe* Ports (or



devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured

2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19

3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled

4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled

5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PC I Express* (PCIe*)” chapt er for t he P CH PCIe* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support

6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

D

Date Sheet of

15 73Tuesday February 13 2018

15 73Tuesday February 13 2018

15 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf

R

H8 1M_0402_5%

YH1
24MHZ_18PF_XRCGB24M000F2P51R0

1 1

2 2

3 3

4 4

3

33P_0402_50V8J

3

CH5

32.768KHZ_9PF_X1A000141000200

10P_0402_50V8J

1

CH7

2

+3VS

For DDX03 R02

+1.8VALW _PRIM

RH15 4.7K_0402_5%

This signal has a weak internal pull-down 20K.
0 = 38.4/19.2MHz XTAL frequency selected.
1 = 24MHz XTAL frequency selected. (DDX03)
Notes:

1. The internal pull-down is disabled after RSMRST#
de-asserts.

2. This signal is in the primary well.

+1.8VALW _PRIM

RH21 4.7K_0402_5%

The signal has a weak internal pull-down 20K
0 = VCCPSPI is connected to 3.3V rail
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin

strap must be a ‘ 1’ fo r the prope r functionality
of the SPI (Flash) I/Os

+1.8VALW _PRIM

RH22 10K_0402_5%
RH23 10K_0402_5%

X

TAL_24M_PCH_OUT

C

4

YH2

N

C

2

XTAL_24M_PCH_IN

1

1

1 2

N

1 2

RH12 10M_0402_5%

1 2

Trace Space: 15 mil
Max Trace Length: 1000 mil

1 2

EMI@

RH11 33_0402_1%

1 2

EMI@

R

H9 33_0402_1%

18P_0402_50V8J

CH6

PCH_RTCX1
PCH_RTCX2

10P_0402_50V8J

1

CH8

2

use same part w C5MMH

RPH2

10K_0804_8P4R_5%

XTAL Frequency Select

1 2

VCCPSPI Select

1 2

An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.

Pulled down by CRF CNVi RGI_DT pin

LAN_CLKREQ#

18

VGA_CLKREQ#

27

WLAN_CLKREQ#

36

SSD_CLKREQ#

45

@

M.2 CNV Mode Select

12

@

12

A

CNV_BRI_PTX_DRX

GPP_J9

CNV_RGI_PTX_DRX

X

TAL_24M_PCH_OUT_R

XTAL_24M_PCH_IN_R

VGA_CLKREQ# <25>

STRAP

STRAP

STRAP

B

remove TP as C5PRH

P

PCH_CPU_24M_CLK_P<11>
PCH_CPU_24M_CLK_N<11>

PCH_CPU_BCLK_P<11>

CH_CPU_BCLK_N<11>

P

1 2

RH10 60.4_0402_1%

XCLK_BIASREF (PDG)
Trace Width/Space: 15mil /15 mil
Max Trace Length: 1000 mil
8/24

LAN_CLKREQ#<40>

WLAN_CLKREQ#<41>

SSD_CLKREQ#<39>

CH_CPU_24M_CLK_P

PCH_CPU_24M_CLK_N
P

CH_CPU_BCLK_P

PCH_CPU_BCLK_N

TAL_24M_PCH_OUT_R

X
XTAL_24M_PCH_IN_R

XCLK_BIASREF

PCH_RTCX1
PCH_RTCX2

VGA_CLKREQ#
LAN_CLKREQ#
WLAN_CLKREQ#
SSD_CLKREQ#

remove SD signal from PCH

remove CPU_C10_GATE#

CNV_BRI_PTX_DRX<41>
CNV_BRI_PRX_DTX<41>
CNV_RGI_PTX_DRX<41>
CNV_RGI_PRX_DTX<41>

+1.8VALW _PRIM

1 2

RH181 20K_0402_1%CNVI@

1 2

571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.

B

RH182 20K_0402_1%CNVI@

CNV_BRI_PTX_DRX
CNV_BRI_PRX_DTX
CNV_RGI_PTX_DRX
CNV_RGI_PRX_DTX

GPP_J9

CNV_BRI_PRX_DTX
CNV_RGI_PRX_DTX

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

BE33

D7
C6

B8
C8

U9

U10

T3

BA49
BA48

BF31
BE31
AR32
BB30
BA30
AN29
AE47
AC48
AE41
AF48
AC41
AC39
AE39
AB48
AC44
AC43

V2
V3

T2
T1

AA1

Y2

AC7
AC6

UH1M

AW13

GPP_G0/SD_CMD

BE9

GPP_G1/SD_DATA0

BF8

GPP_G2/SD_DATA1

BF9

GPP_G3/SD_DATA2

BG8

GPP_G4/SD_DATA3

BE8

GPP_G5/SD_CD#

BD8

GPP_G6/SD_CLK

AV13

GPP_G7/SD_WP

AP3

GPP_I11/M2_SKT2_CFG0

AP2

GPP_I12/M2_SKT2_CFG1

AN4

GPP_I13/M2_SKT2_CFG2

AM7

GPP_I14/M2_SKT2_CFG3

AV6

GPP_J0/CNV_PA_BLANKING

AY3

GPP_J1/CPU_C10_GATE#

AR13

GPP_J11/A4WP_PRESENT

AV7

GPP_J10

AW3

GPP_J_2

AT10

GPP_J_3

AV4

GPP_J4/CNV_BRI_DT/UART0B_RTS#

AY2

GPP_J5/CNV_BRI_RSP/UART0B_RXD

BA4

GPP_J6/CNV_RGI_DT/UART0B_TXD

AV3

GPP_J7/CNV_RGI_RSP/UART0B_CTS#

AW2

GPP_J8/CNV_MFUART2_RXD

AU9

GPP_J9/CNV_MFUART2_TXD

CNP-H_BGA874

@

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

C

H1G

U

G

PP_A16/CLKOUT_48

C

LKOUT_CPUNSSC_P

CLKOUT_CPUNSSC#
C

LKOUT_CPUBCLK_P

CLKOUT_CPUBCLK#
XTAL_OUT

XTAL_IN
XCLK_BIASREF
RTCX1

RTCX2
GPP_B5/SRCCLKREQ0#

GPP_B6/SRCCLKREQ1#
GPP_B7/SRCCLKREQ2#
GPP_B8/SRCCLKREQ3#
GPP_B9/SRCCLKREQ4#
GPP_B10/SRCCLKREQ5#
GPP_H0/SRCCLKREQ6#
GPP_H1/SRCCLKREQ7#
GPP_H2/SRCCLKREQ8#
GPP_H3/SRCCLKREQ9#
GPP_H4/SRCCLKREQ10#
GPP_H5/SRCCLKREQ11#
GPP_H6/SRCCLKREQ12#
GPP_H7/SRCCLKREQ13#
GPP_H8/SRCCLKREQ14#
GPP_H9/SRCCLKREQ15#

CLKOUT_PCIE_N15
CLKOUT_PCIE_P15

CLKOUT_PCIE_N14
CLKOUT_PCIE_P14

CLKOUT_PCIE_N13
CLKOUT_PCIE_P13

CLKOUT_PCIE_N12
CLKOUT_PCIE_P12

CNP-H_BGA874

@

1.8V

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

NP-H

C

C

LKOUT_ITPXDP#

CLKOUT_ITPXDP_P

C

LKOUT_CPUPCIBCLK#

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1

LKOUT_PCIE_P1

C
CLKOUT_PCIE_N2

CLKOUT_PCIE_P2
CLKOUT_PCIE_N3

CLKOUT_PCIE_P3
CLKOUT_PCIE_N4

CLKOUT_PCIE_P4
CLKOUT_PCIE_N5

CLKOUT_PCIE_P5
CLKOUT_PCIE_N6

CLKOUT_PCIE_P6
CLKOUT_PCIE_N7

CLKOUT_PCIE_P7
CLKOUT_PCIE_N8

CLKOUT_PCIE_P8
CLKOUT_PCIE_N9

CLKOUT_PCIE_P9

CLKOUT_PCIE_N10
CLKOUT_PCIE_P10

CLKOUT_PCIE_N11
CLKOUT_PCIE_P11

7 OF 13

CNP-H

13 OF 13

3.3V

CLKIN_XTAL

CNV_WR_CLKN
CNV_WR_CLKP

CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N
CNV_WR_D1P

CNV_WT_CLKN
CNV_WT_CLKP

CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P

CNV_WT_RCOMP

PCIE_RCOMPN

PCIE_RCOMPP
SD_1P8_RCOMP
SD_3P3_RCOMP

GPPJ_RCOMP_1P81
GPPJ_RCOMP_1P82
GPPJ_RCOMP_1P83

Rev1.0

Y3
Y4

B6
A6

AJ6
AJ7

AH9
AH10

AE14
AE15

AE6
AE7

AC2
AC3

AB2
AB3

W4
W3

W7
W6

AC14
AC15

U2
U3

AC9
AC11

AE9
AE11

R6

RSVD2
RSVD3

RSVD1

TP

Rev1.0

D

P

CH_CPU_PCIBCLK_N

PCH_CPU_PCIBCLK_P

LK_PEG_VGA#

C
CLK_PEG_VGA

CLK_PCIE_LAN#
CLK_PCIE_LAN

CLK_PCIE_WLAN#
CLK_PCIE_WLAN

CLK_PCIE_NGFF#
CLK_PCIE_NGFF

12

RH14

10K_0402_5%

CLK_CNV_PRX_DTX_N

BD4

CLK_CNV_PRX_DTX_P

BE3

CNV_PRX_DTX_N0

BB3

CNV_PRX_DTX_P0

BB4

CNV_PRX_DTX_N1

BA3

CNV_PRX_DTX_P1

BA2

CLK_CNV_PTX_DRX_N

BC5

CLK_CNV_PTX_DRX_P

BB6

CNV_PTX_DRX_N0

BE6

CNV_PTX_DRX_P0

BD7

CNV_PTX_DRX_N1

BG6

CNV_PTX_DRX_P1

BF6

CNV_WT_RCOMP

BA1

PCIE_RCOMPN

B12

PCIE_RCOMPP

A13

SD_RCOMP_1P8

BE5

SD_RCOMP_3P3

BE4
BD1

GPPJ_RCOMP_1P8

BE1
BE2

Y35
Y36

BC1
AL35

D

TH2@
TH3@

REFCLK_CNV

1

CH51

@ESD@

4.7P_0201_50V8B

2

RH16

1 2
1 2

RH17 100_0402_1%

1 2

RH18 200_0402_1%

1 2

RH19 200_0402_1%

1 2

RH20 200_0402_1%

#571483_CFL_H_RVP_CRB_TDK_Rev0p5
Recommend external test point

TH4@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

PCH_CPU_PCIBCLK_N <11>

CH_CPU_PCIBCLK_P <11>

P

LK_PEG_VGA# <25>

C

CLK_PEG_VGA <25>

CLK_PCIE_LAN# <40>

CLK_PCIE_LAN <40>

CLK_PCIE_WLAN# <41>

CLK_PCIE_WLAN <41>

CLK_PCIE_NGFF# <39>
CLK_PCIE_NGFF <39>

REFCLK_CNV <41>

150_0402_1%

E

GPU

D

GLAN

NGFF WL+BT(KEY E)

M2 SSD

CLK_CNV_PRX_DTX_N <41>
CLK_CNV_PRX_DTX_P <41>

CNV_PRX_DTX_N0 <41>
CNV_PRX_DTX_P0 <41>
CNV_PRX_DTX_N1 <41>
CNV_PRX_DTX_P1 <41>

CLK_CNV_PTX_DRX_N <41>
CLK_CNV_PTX_DRX_P <41>

CNV_PTX_DRX_N0 <41>

CNV_PTX_DRX_P0 <41>

CNV_PTX_DRX_N1 <41>

CNV_PTX_DRX_P1 <41>

checked CRB

16 73Tuesday February 13 2018

16 73Tuesday February 13 2018

16 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

NP-H

H1E

U

no follow naming

can remove if no use DP
08/18

remove PCH DP SCLK/SDATA

CRB PU 20k

+3VALW _SPI

+3VALW _PCH_PRIM

1 1

#571182_CFL_PCH_EDS_Rev1.0 recommend 100k

PDG P348 quad mode support PH1K

RH25 1K_0402_5%
RH26 1K_0402_5%

RH27 1K_0402_5%

RH29 100K_0402_5%

#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15

12
12

12

12

PCH_SPI_IO2
PCH_SPI_IO3

PCH_SPI_SI

GPP_H15

STRAP

HDMI_HPD_PCH<26,38>

EDP_HPD<37>

EC_PME#<40,43>

RH24 0_0402_5%

PCH_SPI_CLK<19>

HDMI_HPD_PCH

DP_HPD

E

@

EC_PME#_R

1 2

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CS#0
PCH_SPI_CLK

PCH_SPI_IO2
PCH_SPI_IO3

1 2

TH6 @

HDD_PW RGT<47>

reserve for Optane Memory

AT6

G

PP_I0/DDPB_HPD0/DISP_MISC0

AN10

GPP_I1/DDPC_HPD1/DISP_MISC1

AP9

GPP_I2/DDPD_HPD2/DISP_MISC2

AL15

G

PP_I3/DDPF_HPD3/DISP_MISC3

AN6

PP_I4/EDP_HPD/DISP_MISC4

G

CNP-H_BGA874

@

UH1A

BE36

GPP_A11/PME#/SD_VDD2_PWR_EN#

R15

RSVD2

R13

RSVD1

AL37

RH1860_0402_5% @

VSS

AN35

TP

AU41

SPI0_MOSI

BA45

SPI0_MISO

AY47

SPI0_CS0#

AW47

SPI0_CLK

AW48

SPI0_CS1#

AY48

SPI0_IO2

BA46

SPI0_IO3

AT40

SPI0_CS2#

BE19

GPP_D1/SPI1_CLK/SBK1_BK1

BF19

GPP_D0/SPI1_CS#/SBK0_BK0

BF18

GPP_D3/SPI1_MOSI/SBK3_BK3

BE18

GPP_D2/SPI1_MISO/SBK2_BK2

BC17

GPP_D22/SPI1_IO3

BD17

GPP_D21/SPI1_IO2

CNP-H_BGA874

@

C

5 OF 13

CNP-H

GPP_K15/GSXSRESET#

GPP_H18/SML4ALERT#

GPP_H15/SML3ALERT#

GPP_H12/SML2ALERT#

1 OF 13

G

PP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

G

PP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK

G

PP_I10/DDPD_CTRLDATA

GPP_F23/DDPF_CTRLDATA

GPP_F22/DDPF_CTRLCLK

GPP_F14/PS_ON#

PP_K23/IMGCLKOUT1

G
GPP_K22/IMGCLKOUT0

GPP_K21
GPP_K20

GPP_H23/TIME_SYNC0

GPP_B13/PLTRST#

GPP_K16/GSXCLK

GPP_K12/GSXDOUT

GPP_K13/GSXSLOAD

GPP_K14/GSXDIN

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

Rev1.0

AL13
AR8
AN13
AL10
AL9
AR3
AN40
AT49

AP41

M45
L48
T45
T46
AJ47

remove CIO_PLUG_EVENT#

Rev1.0

PLT_RST#

AV29

Y47
Y46
Y48
W46
AA45

AL47
AM45
BF32
BC33

AE44
AJ46
AE43
AC47
AD48
AF47
AB47
AD47
AE48

BB44

TP_INT#

GPP_H15

GPP_H12

SM_INTRUDER#

RVP: 330K
A 1 M pull-up is used on the customer reference
board (CRB). This is needed to reduce leakage
from Coin Cell Battery in G3 state.

DDP[B..F]CTRLDATA
This signal has a weak internal Pull-down.
0 = Port B~D is not detected.
1 = Port B,C,D is detected. (Default)
Notes:

1. The internal Pull-down is disabled after
PCH_PWROK de-asserts.

2. This signal is in the primary well.

PLT_RST# <19,26,36,43,49>

GPIO Serial Expander (GSX) is the capability
provided by the PCH to expand the GPIOs
on a platform that needs more GPIOs than the
ones provided by the PCH.

DH1
RB751V-40_SOD323-2

12

GPP_H12 <20>

EC_TP_INT# <43,49>

TYPEC_1P5A <44>

+RTCVCC

12

RH301M_0402_5%

PLT_RST#

1 2

CH9 100P_0402_50V8J

@ESD@

TP_INT#

RH28 100K_0402_5%

+3VS

12

SPI ROM ( 16MByte )

PCH_SPI_CS#0

PCH_SPI_IO2_0_R

UH2

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q128FVSIQ_SO8

/HOLD(IO3)

P/N: SA00005VV20

PCH_SPI_CLK_0_R

@EMI@

1 2

RH33
0_0402_5%

VCC

CLK

DI(IO0)

+3VALW _SPI

CH10 0.1U_0201_10V6K

8

PCH_SPI_IO3_0_RPCH_SPI_SO_0_R

7

PCH_SPI_CLK_0_R

6

PCH_SPI_SI_0_R

5

@EMI@

1 2

CH12
68P_0402_50V8J

1 2

PCH_SPI_CS#0

PCH_SPI_SI_0_R
PCH_SPI_SO_0_R
PCH_SPI_IO3_0_R
PCH_SPI_CLK_0_R

sch checklist 0.7
1 device 15 ohm / 2 device 33 ohm

RH107 49.9_0402_1%
RH108 49.9_0402_1%
RH109 49.9_0402_1%
RH110 49.9_0402_1%
RH111 49.9_0402_1%

1 2

RH31 4.7K_0402_5%

1 2
1 2
1 2
1 2
1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW _SPI

@

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_IO3
PCH_SPI_CLK
PCH_SPI_IO2PCH_SPI_IO2_0_R

A

PCH PLTRST Buffer

PLT_RST#

Compal Secret Data

Compal Secret Data

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1 2

RH32 0_0402_5%@

+3VS

1

B

2

A

1 2

CH11

.1U_0402_16V7K

5

UH3

P

4

Y

G

TC7SH08FU_SSOP5

3

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

PLT_RST_BUF# <39,40,41>

1.A

1.A

1.A

17 73Tuesday February 13 2018

17 73Tuesday February 13 2018

17 73Tuesday February 13 2018

A

www.laptoprepairsecrets.com

U

SB3 MB

1 1

USB3 Type C

USB3 SUB

USB3 Type C

USB3 SUB

2 2

For Intel CLINK

M.2 SSD PCIE L1

3 3

GLAN

PCIE_PTX_C_DRX_N14<40>

PCIE_PTX_C_DRX_P14<40>

PCIE_PRX_DTX_N14<40>
PCIE_PRX_DTX_P14<40>

M.2 SSD PCIE L0

+3VALW _PCH_PRIM

12

RH43

10K_0402_5%

4 4

UMA@

DGPU_PRSNT#

TH10 @
TH11 @
TH12 @

PCIE_PTX_DRX_P11<39>
PCIE_PTX_DRX_N11<39>
PCIE_PRX_DTX_P11<39>
PCIE_PRX_DTX_N11<39>

12

CH3 .1U_0402_16V7K

12

CH4 .1U_0402_16V7K

PCIE_PTX_DRX_P12<39>
PCIE_PTX_DRX_N12<39>
PCIE_PRX_DTX_P12<39>
PCIE_PRX_DTX_N12<39>

USB3_PTX_DRX_N1<46>
USB3_PTX_DRX_P1<46>
U

SB3_PRX_DTX_N1<46>

U

SB3_PRX_DTX_P1<46>

USB3_PTX_DRX_N2<45>

SB3_PTX_DRX_P2<45>

U

SB3_PRX_DTX_N2<45>

U
USB3_PRX_DTX_P2<45>

USB3_PTX_DRX_N5<48>
USB3_PTX_DRX_P5<48>
USB3_PRX_DTX_N5<48>
USB3_PRX_DTX_P5<48>

USB3_PTX_DRX_P3<45>
USB3_PTX_DRX_N3<45>
USB3_PRX_DTX_P3<45>
USB3_PRX_DTX_N3<45>

USB3_PTX_DRX_P4<48>
USB3_PTX_DRX_N4<48>
USB3_PRX_DTX_P4<48>
USB3_PRX_DTX_N4<48>

B

CL_CLK
CL_DATA
CL_RST#

DGPU_PRSNT#

PCIE_PTX_DRX_N14
PCIE_PTX_DRX_P14

PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14

UH1F

F9

U

SB31_1_TXN

F7

USB31_1_TXP

D11

USB31_1_RXN

C11

U

SB31_1_RXP

C3

USB31_2_TXN

D4

USB31_2_TXP

B9

USB31_2_RXN

C9

SB31_2_RXP

U

C17

SB31_6_TXN

U

C16

USB31_6_TXP

G14

USB31_6_RXN

F14

USB31_6_RXP

C15

USB31_5_TXN

B15

USB31_5_TXP

J13

USB31_5_RXN

K13

USB31_5_RXP

G12

USB31_3_TXP

F11

USB31_3_TXN

C10

USB31_3_RXP

B10

USB31_3_RXN

C14

USB31_4_TXP

B14

USB31_4_TXN

J15

USB31_4_RXP

K16

USB31_4_RXN

CNP-H_BGA874

@

UH1C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CNP-H_BGA874

@

C

C

NP-H

G

PP_A1/LAD0/ESPI_IO0

1.8V

GPP_A2/LAD1/ESPI_IO1

(eSPI)

GPP_A3/LAD2/ESPI_IO2
G

PP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

PP_A7/PIRQA#/ESPI_ALERT0#

G

GPP_A0/RCIN#/ESPI_ALERT1#

PP_A14/SUS_STAT#/ESPI_RESET#

G

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_K19/SMI#

GPP_K18/NMI#

GPP_E6/SATA_DEVSLP2
GPP_E5/SATA_DEVSLP1
GPP_E4/SATA_DEVSLP0

GPP_F9/SATA_DEVSLP7
GPP_F8/SATA_DEVSLP6
GPP_F7/SATA_DEVSLP5
GPP_F6/SATA_DEVSLP4
GPP_F5/SATA_DEVSLP3

6 OF 13

CNP-H

PCIE9_RXN
PCIE9_RXP

PCIE9_TXN
PCIE9_TXP

PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THRMTRIP#

PM_SYNC

3 OF 13

PLTRST_CPU#

PM_DOWN

PECI

Rev1.0

Rev1.0

BB39
AW37
AV37
BA38

BE38
AW35
BA36
BE39
BF38

BB36
BB34

T48
T47

AH40
AH35
AL48
AP47
AN37
AN46
AR47
AP48

G36
F36
C34
D34

K37
J37
C35
B35

F44
E45
B40
C40

L41
M40
B41
C41

K43
K44
A42
B42

P41
R40
C42
D42

AK48
AH41

AJ43
AK47
AN47
AM46
AM43
AM47
AM48

AU48
AV46
AV44

AD3
AF2
AF3
AG5
AE2

#571391_CFL_H_PDG_Rev0p5





* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.

L

PC_AD0
LPC_AD1
LPC_AD2
L

PC_AD3

PC_FRAME#

L
TPM_SERIRQ

PC_PIRQA#

L
ESPI_RST#
CLK_LPC

CLK_LPC_TPM

PCIE_PRX_DTX_N15
PCIE_PRX_DTX_P15
PCIE_PTX_DRX_N15
PCIE_PTX_DRX_P15

1 2

RH187 1K_0402_5%PBA@

SATA_GP5

PCH_BKL_PWM
ENBKL

PCH_ENVDD

PCH_THERMTRIP#
PCH_PECI

H_PM_SYNC
H_PLTRST_CPU#
H_PM_DOWN_R

D

eSPI clock and eSPI data mismatched: <500 mils.

eSPI clock and eSPI chip select mismatched: <500 mils.

signal maximum 9 Vias

eSPI

LPC_AD0 <43,49>
LPC_AD1 <43,49>
LPC_AD2 <43,49>
LPC_AD3 <43,49>

PC_FRAME# <43,49>

L

PM_SERIRQ <43,49>

T

SSD_DEVSLP1 <39>

TH13@

1 2
1 2
1 2

12
12

1 2
1 2

SATA_GP1 <39>

PCH_BKL_PWM <26,37>
ENBKL <26,43>
PCH_ENVDD <26,37>

RH35 22_0402_5%
RH36 22_0402_5%TPM@

SATA_PRX_DTX_N4 <47>
SATA_PRX_DTX_P4 <47>
SATA_PTX_DRX_N4 <47>
SATA_PTX_DRX_P4 <47>

RH40 620_0402_5%
RH41 13_0402_5%@

RH42 30_0402_5%

LPC Bus

LPC : +3.3V

ESPI_RST# <43>
CLK_LPC_R <43>

CLK_LPC_TPM_R <49>

PCIE_PRX_DTX_N9 <39>
PCIE_PRX_DTX_P9 <39>
PCIE_PTX_DRX_N9 <39>

PCIE_PTX_DRX_P9 <39>

PCIE_PRX_DTX_N10 <39>
PCIE_PRX_DTX_P10 <39>
PCIE_PTX_DRX_N10 <39>

PCIE_PTX_DRX_P10 <39>

PCIE_PRX_DTX_N15 <41>

CH1.1U_0402_16V7K
CH2.1U_0402_16V7K

PCIE_PRX_DTX_P15 <41>
PCIE_PTX_C_DRX_N15 <41>

PCIE_PTX_C_DRX_P15 <41>

HDD

#571391_CFL_H_PDG_Rev0p5.pdf

H_PECI
H_PM_SYNC_R

E

check straps

TPM_SERIRQ

LPC_PIRQA#

M.2 SSD PCIE L3

M.2 SSD PCIE L2

NGFF
WL+BT(KEY E)

SATA_GP1

RH39 10K_0402_5%

M.2 SSD PCIE/SATA select pin

PCH_THERMTRIP#_R <11>

H_PECI <11,43>

H_PM_SYNC_R <11>
H_PLTRST_CPU# <11>
H_PM_DOWN_R <11>

10K_0402_5%

1 2

10K_0402_5%

12

+3VS

12

RH37

RH38

+3VS

12

RH44

10K_0402_5%

VGA@

DIS,Optimus10

UMA

A

GPP_F13

DGPU PRSNT#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

C

Compal Secret Data

Compal Secret Data

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

18 73Tuesday February 13 2018

18 73Tuesday February 13 2018

18 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

1 2

ME_EN<43>

H

DA_RST#_R<42>
HDA_BIT_CLK_R<42>
HDA_SDOUT_R<42>
H

DA_SYNC_R<42>

1 1

R

PH7

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

@

R

H45 0_0402_5%

H

DA_RST#

H

DA_BIT_CLK
HDA_SDOUT
HDA_SYNC

del RF reserve cap on HDA

CPU_DISPA_SDO_R<7>

CPU_DISPA_SDI_R<7>

FOR Jefferson Peak RESET pin is glitch free,it
is recommended that a pull-down resistor of 75K
ohm on GPP_D5(CNV_RF_RESET#)

+RTCVCC

1 2

RH50 20K_0402_1%

1 2

2 2

+3VALW _DSW

3 3

+3VS

+3VS

+3VALW _PCH_PRIM

4 4

CH18 1U_0402_6.3V6K

1 2

RH52 20K_0402_1%

1 2

CH19 1U_0402_6.3V6K

1 2

JCMOS1 0_0603_5%@

1 2
1 2

RPH11

2.2K_0804_8P4R_5%

1 2
1 2

12

12
12
12

12

18
27
36
45

A

D_CK_SDATA
D_CK_SCLK

PCH_SMBCLK
PCH_SMBDATA
PCH_SML1CLK
PCH_SML1DATA

RH55 1K_0402_5%

RH56 8.2K_0402_5%
RH57 100K_0402_5%@
RH58 100K_0402_5%@

RH60 8.2K_0402_5%

RH197 2.2K_0402_5%
RH198 2.2K_0402_5%

RH63 499_0402_1%
RH64 499_0402_1%

PCH_SML0CLK
PCH_SML0DATA

CPU_DISPA_BCLK_R<7>

PCH_SRTCRST#

CLR ME
Delay 18~25 ms

PCH_RTCRST#

ECLR CMOS
Delay 18~25 ms

WAKE#

PM_BATLOW#
AC_PRESENT_R
PBTN_OUT#_R

PM_CLKRUN#

2N7002KDW_SOT363-6

PCH_SMBCLK

PCH_SML1CLK <26,43,44,48>

PCH_SML1DATA <26,43,44,48>

B

HDA_SDIN0<42>

RH48

1 2

RH49

1 2

CLKREQ_CNV#<41>

CNV_RF_RESET#<41>
PCH_DMIC_DATA0<42>
PCH_DMIC_CLK0<42>

TH22 @
TH24 @

PCH_RTCRST#<43>

PCH_PW ROK<43,51>
EC_RSMRST#<43>

PCH_SMBALERT#<20>

PCH_SML0ALERT#<20>

PCH_SML1ALERT#<20>

QH7B

3 4

D

2N7002KDW_SOT363-6

(EC, VGA, Thermal Sensor, Type-C)

B

+3VS

5

30_0402_5%
30_0402_5%

G

S

QH7A

6 1

2

G

D

HDA_BIT_CLK
HDA_SDIN0
HDA_SDOUT
HDA_SYNC

HDA_RST#

CPU_DISPA_SDO
CPU_DISPA_SDI_R
CPU_DISPA_BCLK

CLKREQ_CNV#
CNV_RF_RESET#

PCH_RTCRST#
PCH_SRTCRST#

PCH_PW ROK
EC_RSMRST#

PCH_DPW ROK
PCH_SMBALERT#
PCH_SMBCLK
PCH_SMBDATA
PCH_SML0ALERT#
PCH_SML0CLK
PCH_SML0DATA
PCH_SML1ALERT#
PCH_SML1CLK
PCH_SML1DATA

D_CK_SCLK

D_CK_SDATAPCH_SMBDATA

S

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UH1D

BD11

DA_BCLK/I2S0_SCLK

H

BE11

HDA_SDI0/I2S0_RXD

BF12

HDA_SDO/I2S0_TXD

BG13

HDA_SYNC/I2S0_SFRM

BE10

HDA_RST#/I2S1_SCLK

BF10

HDA_SDI1/I2S1_RXD

BE12

I2S1_TXD/SNDW2_DATA

BD12

I2S1_SFRM/SNDW2_CLK

AM2

HDACPU_SDO

AN3

HDACPU_SDI

AM3

HDACPU_SCLK

AV18

GPP_D8/I2S2_SCLK

AW18

GPP_D7/I2S2_RXD

BA17

GPP_D6/I2S2_TXD/MODEM_CLKREQ

BE16

GPP_D5/I2S2_SFRM/CNV_RF_RESET#

BF15

GPP_D20/DMIC_DATA0/SNDW4_DATA

BD16

GPP_D19/DMIC_CLK0/SNDW4_CLK

AV16

GPP_D18/DMIC_DATA1/SNDW3_DATA

AW15

GPP_D17/DMIC_CLK1/SNDW3_CLK

BE47

RTCRST#

BD46

SRTCRST#

AY42

PCH_PWROK

BA47

RSMRST#

AW41

DSW_PWROK

BE25

GPP_C2/SMBALERT#

BE26

GPP_C0/SMBCLK

BF26

GPP_C1/SMBDATA

BF24

GPP_C5/SML0ALERT#

BF25

GPP_C3/SML0CLK

BE24

GPP_C4/SML0DATA

BD33

GPP_B23/SML1ALERT#/PCHHOT#

BF27

GPP_C6/SML1CLK

BE27

GPP_C7/SML1DATA

CNP-H_BGA874

@

(DDR,G-Sensor)

D_CK_SCLK <23,24,47>

D_CK_SDATA <23,24,47>

Issued Date

Issued Date

Issued Date

C

NP-H

C

PP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

G

GPP_B1/GSPI1_CS1#/TIME_SYNC1

1.8V

GPP_A13/SUSWARN#/SUSPWRDNACK

4 OF 13

+3VALW _PCH_PRIM +3VALW_DSW

Compal Secret Data

Compal Secret Data

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

C

Compal Secret Data

GPP_A8/CLKRUN#
GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B0/GSPI0_CS1#

GPP_K17/ADR_COMPLETE

GPP_B11/I2S_MCLK

SYS_PWROK

GPD6/SLP_A#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#
GPD1/ACPRESENT

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

CPUPWRGD

ITP_PMODE
PCH_JTAGX

PCH_JTAG_TMS

PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

Deciphered Date

Deciphered Date

Deciphered Date

BF36
AV32

BF41
BD42
BB46

BE32
BF33
BE29
R47
AP29
AU3

BB47

WAKE#

BE40
BF40

SLP_LAN#

BC28
BF42
BE42
BC42

BE45
BF44
BE35
BC37

BG44
BG42
BD39

SLP_SUS#

BE46
AU2
AW29
AE3

AL3
AH4
AJ4
AH3
AH2
AJ3

Rev1.0

RPH8

18
27
36
45

10K_0804_8P4R_5%

1 2

RH184100K_0402_5% @

1 2

RH61100K_0402_5% @

@ESD@

1 2

CH50100P_0402_50V8J

@ESD@

1 2

CH20.1U_0402_16V7K

@ESD@

1 2

CH21.1U_0402_16V7K

@ESD@

1 2

CH22.1U_0402_16V7K

Near PCH side

From ESD Team Request

D

D

RAM_RESET#

PM_CLKRUN#
LAN_DISABLE_N
SLP_WLAN#
DRAM_RESET#

PCH_VRALERT#
LAN_GPO

PCH_GPP_K17
PCH_GPP_B11
SYS_PWROK

WAKE#
PM_SLP_A#

SLP_LAN#
PM_SLP_S0#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

SUSCLK
PM_BATLOW#

SUSACK#_R

1 2

RH51 0_0402_5%

LAN_WAKE#
AC_PRESENT_R
SLP_SUS#
PBTN_OUT#_R
SYS_RESET#
PCH_SPKR
H_CPUPW RGD

XDP_ITP_PMODE
CPU_XDP_TCK0
CPU_XDP_TMS
CPU_XDP_TDO
CPU_XDP_TDI

PCH_PW ROK
LAN_WAKE#
EC_RSMRST#
SYS_RESET#

SYS_PWROK

PCH_DPW ROK

EC_RSMRST#

SYS_RESET#

SYS_PWROK

PCH_PW ROK

D

+1.2V_VDDQ

@

1 2

RH53 0_0402_5%@

1 2

RH54 0_0402_5%

EC_RSMRST#

E

RH46
470_0402_1%

1 2

1 2

@

RH47 0_0402_5%

12

CH13 1U_0402_6.3V6K

@

PM_CLKRUN# <49>

TH14@
TH15@

TYPEC_3A <44>
LAN_GPO <40>

TH19@
TH20@

SYS_PWROK <43,51>

TH37@
TH21@

PM_SLP_S0# <43>
PM_SLP_S3# <43,51>
PM_SLP_S4# <43,51>

TH23@

T207@

SUSPWRDNACK <43>

T208

@

@

PCH_SPKR <20,42>

H_CPUPW RGD <11>

Custom

Custom

Custom

T209

@

CPU_XDP_TCK0 <11>

CPU_XDP_TMS <11>

CPU_XDP_TDO <11>
CPU_XDP_TDI <11>
PCH_JTAG_TCK1 <11>

1 2

RH59 0_0402_5%

PCH_VRALERT#

Intel critical net recommend

PM_SLP_S3#
PM_SLP_S4#
HDA_BIT_CLK
HDA_RST#

PCH_SPI_CLK<17>

PLT_RST#<17,26,36,43,49>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

SUSCLK <39,41>

--No Support Deep Sx

@

RH62 10K_0402_5%@

RH191 100K_0201_5%
RH192 100K_0201_5%
RH193 100K_0201_5%
RH194 100K_0201_5%
RH195 100K_0201_5%@
RH196 100K_0201_5%

DDR_DRAMRST#_R <23,24>

AC_PRESENT <43>
PBTN_OUT# <43>

Connect CPU & PCH

PCH_DPW ROK

+3VALW _PCH_PRIM

12

1 2
1 2
1 2
1 2
1 2
1 2

19 73Tuesday February 13 2018

19 73Tuesday February 13 2018

19 73Tuesday February 13 2018

E

1.A

1.A

1.A

+3VALW_PCH_PRIM

www.laptoprepairsecrets.com

1 8
2 7
3 6
4 5

2.2K_0804_8P4R_5%

+

3VS

RH66 10K_0402_5%@

1 1

2 2

3 3

4 4

RH68 49.9K_0402_1%
RH69 49.9K_0402_1%
RH70 49.9K_0402_1%@
RH71 49.9K_0402_1%@
RH72 10K_0402_5%VGA@

RH73 10K_0402_5%VGA@

+3VALW _PCH_PRIM

1 2

RH74 4.7K_0402_5%@

This signal has a weak internal pull-down.
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
1 = Slave Attached Flash Sharing (SAFS) enabled.
Notes:

1. This signal is in the primary well.

Warning: This strap must be configured to ‘ 0’ if the
eSPI or LPC strap is configured to ‘ 0’

+3VALW _PCH_PRIM

+3VS

A

PH12

R

1 2

1 2

2C_1_SCL

I
2C_1_SDA

I

I

2C_0_SCL

I

2C_0_SDA

12
12
12
12
12

EC_SCI# GC6_FB_EN3V3 GC6_FB_EN
UART_2_PRXD_DTXD
UART_2_PTXD_DRXD
UART_2_PRTS_DCTS
UART_2_PCTS_DRTS
DGPU_PW R_EN

DGPU_HOLD_RST#

GPP_H12

GC6_FB_EN3V3<26,36>

check needed?

CG11 connect to GPP_B15

GPP_H12 <17>

STRAP

1 2

RH112 4.7K_0402_5%@

SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS)

1 2

RH113 4.7K_0402_5%@

SML0ALERT# / GPP_C5 has a weak internal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected

1 2

RH114 150K_0402_1%

SML1ALERT# / GPP_B23 has an internal pull-down.
0 = Disable IntelR DCI-OOB (Default)
1 = Enable IntelR DCI-OOB

1 2

RH77 4.7K_0402_5%@

The signal has a weak internal Pull-down.

0 = Disable “ No Reboot” mode. (Default)
1 = Enable “ No Reboot” mod e (PCH wil l disable th e
TCO Timer system reboot feature). This function is
useful when running ITP/XDP.
Notes:

1. The internal Pull-down is disabled after
PCH_PWROK is high.

2. This signal is in the primary well.

@

1 2

RH80 150K_0402_1%

This Signal has a weak internal Pull-down.
0: SPI (Default)
1: LPC
Notes:

1. The internal Pull-down is disabled after PCH_PWROK is high.

2. This signal is in the primary well.

RH83 100K_0402_5%@

Top Swap Override

0 = Disable “ Top Swap” mode. (Default)
1 = Enable “ Top Swap” mode.
The internal Pull-down is disabled after PCH_PWROK is high.

12

GSPI0_MOSI

GSPI1_MOSI

PCH_SPKR

PCH_SMBALERT# <19>

PCH_SML0ALERT# <19>

PCH_SML1ALERT# <19>

STRAP

STRAP

PCH_SPKR <19,42>

STRAP

B

<Touch PAD>

STRAP

C

NP-H

H1K

G

SPI1_MOSI

1 2

VGA_ID1

VGA_ID2

EC_SCI#

GSPI0_MOSI

S_EN

T

DGPU_AC_DETECT
GPU_EVENT#

DGPU_HOLD_RST#
DGPU_PW R_EN

UART_2_PCTS_DRTS
UART_2_PRTS_DCTS
UART_2_PTXD_DRXD
UART_2_PRXD_DTXD

I2C_1_SCL
I2C_1_SDA
I2C_0_SCL
I2C_0_SDA

1 2

RH84 1K_0402_5%@

1 2

RH85 10K_0402_5%

1 2

RH86 1K_0402_5%@

1 2

RH87 10K_0402_5%

EC_SCI#<43>

RH67 0_0402_5%@

S_EN<37,43>

T

DGPU_AC_DETECT<26,43,54>

GPU_EVENT#<26>

DGPU_HOLD_RST#<26,36>

DGPU_PW R_EN<26,36>

UART_2_PTXD_DRXD<41>

UART_2_PRXD_DTXD<41>

I2C_1_SCL<49>

I2C_1_SDA<49>

VGA ID

*

Default
Reserve
Reserve
8 Layer, 1050

U

BA26

GPP_B22/GSPI1_MOSI

BD30

G

PP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0A_TXD

BE23

PP_C8/UART0A_RXD

G

AP24

GPP_C11/UART0A_CTS#

BA24

GPP_C10/UART0A_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CNP-H_BGA874

@

+1.8VALW _PRIM

VGA_ID1VGA_ID2

GPP_D9GPP_D10
0 0
0

1
1 0
1 1

C

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
G

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

PP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

OF 3

PROJECT_ID0

PROJECT_ID1

Project ID

DH53F(1060 W/O RD)

*

DH53F(1060 W/ RD)
DH5VF(1050 W/O RD)
DH5VF(1050 W/ RD)

SCI capability is available on all GPIOs
PCH GPIOs that can be routed to generate SMI# or NMI:

GPP_B14, GPP_B20, GPP_B23



GPP_C[23:22]



GPP_D[4:0]





GPP_E[8:0]



GPP_I[3:0]



GPP_G[7:0] (support SMI# only).



The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).

All GPIOs have programmable internal pull-up/pull-down resistors which are off by default.
The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.

D

GPP_H20/ISH_I2C0_SCL

GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL

GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0

1 2

RH88 1K_0402_5%SATARD@

1 2

RH89 10K_0402_5%NORD@

1 2

RH90 1K_0402_5%@

1 2

RH91 10K_0402_5%

BA20
BB20
BB16
AN18

BF14
AR18
BF17
BE17

AG45
AH46

AH47
AH48

AV34
AW32
BA33
BE34
BD34
BF35
BD38

Rev1.0

+1.8VALW _PRIM

Project_ID0Project_ID1

0 0
0
1
1 1

V

GA_ID1

V

GA_ID2
PROJECT_ID0
PROJECT_ID1

SUB_DET SUB_DET

G_INT
CODEC_ID

CODEC_ID

CODEC_ID / GPP_A19
0 = 2 DMIC, 255@ (default)
1 = 4 DMIC, 256@

GPP_D11GPP_D12

1
0

E

1 2

RH185 1K_0402_5%@

op for USB3.0 DB.

P

+3VS

RH78

@

10K_0402_5%

1 2

G_INT

RH79

@

100K_0402_5%

1 2

1 2

RH188 1K_0402_5%256@

+1.8VALW_PRIM

G_INT <47>

+3VALW _PCH_PRIM

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

Compal Secret Data

Compal Secret Data

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

20 73Tuesday February 13 2018

20 73Tuesday February 13 2018

20 73Tuesday February 13 2018

E

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

B

C

D

E

GPIO Group Voltag e

1.05VALW_PCH_PRIM

+1.05VALW

RH92 0_1206_5%@

1 1

RH93 0_0805_5%

12

12

+

1.05VALW_PCH_PR M

5.95A

1U_0402_6.3V6K

1

CH23

2

+1.05VALW_VCCMPHY

6.6A

22U_0402_6.3V6M

1

CH25

2

HSIO for DMIU/USB3.1/PCIE=4162mA

+1.05VALW_VCCMPHY

1U_0402_6.3V6K

1

CH26

2

+1.05VALW_PCH

3-5MM FROM PACKAGE EDGE

1 2

RH94 0_0603_5%@

+1.05VALW_PCH

2 2

place near VCCDUSB
FOR W22/W23

1-5MM FROM PACKAGE EDGE
FOR VCCAPLL C1/C2

3 3

+1.05VALW_PCH

.1U_0402_16V7K

1

2

+1.05VALW_PCH

1U_0402_6.3V6K

1

2

CH29

CH33

1 2

RH102 0_0402_5%@

1P_0402_50V8

1

CH43

2

@

1-3MM FROM PACKAGE EDGE
FOR VCCA_BCLK V19

+1.05VALW_PCH

+1.05VALW_PCH +1.05V_VCCDSW

.1U_0402_16V7K

1

CH30

2

1-3MM FROM PACKAGE
VCCPRIM_MPHY W31

+1.05VALW_PCH

.1U_0402_16V7K

1

CH34

2

+1.05VALW_VCCAZPLL

1P_0402_50V8

1

CH44

2

@

1-3MM FROM PACKAGE EDGE

1-5MM FROM PACKAGE EDGE
FOR VCCAPLL B1/B2/B3

1U_0402_63V6K

1

2

+1.05VALW_PCH

1U_0402_6.3V6K

1

2

CH31

CH35

+1.05V_VCCDSW

+1.05VALW_VCCAZPLL

+1.05VALW_VCCAMPHYPLL

+1.05VALW_XTAL

+

5.95A

6.6A

0.0012A

0.2A

0.42A

0.109A

0.015A

0.213A

0.00428A

0.169A

0.0198A

0.0085A

0.021A

+3VALW +3VALW_PCH_PRIM

RH97 0_0805_5%@

RH99 0_0402_5%@

1P_0402_50V8

1

CH41

2

@

AA22
AA23
AB20
AB22
AB23
AB27
AB28
AB30
AD20
AD23
AD27
AD28
AD30
AF23
AF27
AF30

U26
U29
V25
V27
V28
V30

V31
AD31
AE17

W22
W23

BG45
BG46

W31

C49

D49

E49

W19
W20

V19

1 2

1 2

U

H1H

VCCPRIM_1P051
VCCPRIM_1P052
V

CCPRIM_1P053
VCCPRIM_1P054
V

CCPRIM_1P055
VCCPRIM_1P056
VCCPRIM_1P057
VCCPRIM_1P058
VCCPRIM_1P059
VCCPRIM_1P0510
VCCPRIM_1P0511
VCCPRIM_1P0512
VCCPRIM_1P0513
VCCPRIM_1P0516
VCCPRIM_1P0517
VCCPRIM_1P0518

VCCPRIM_1P0523
VCCPRIM_1P0524
VCCPRIM_1P0525
VCCPRIM_1P0526
VCCPRIM_1P0527
VCCPRIM_1P0528
VCCPRIM_1P0529

VCCPRIM_1P0514
VCCPRIM_1P0515
VCCDUSB_1P051

VCCDUSB_1P052
VCCDSW_1P051

VCCDSW_1P052
VCCPRIM_MPHY_1P05

D1

VCCPRIM_1P0521

E1

VCCPRIM_1P0522
VCCAMPHYPLL_1P051
VCCAMPHYPLL_1P052
VCCAMPHYPLL_1P053

P2

VCCA_XTAL_1P051

P3

VCCA_XTAL_1P052
VCCA_SRC_1P051
VCCA_SRC_1P052

C1

VCCAPLL_1P054

C2

VCCAPLL_1P055
VCCA_BCLK_1P05

B1

VCCAPLL_1P051

B2

VCCAPLL_1P052

B3

VCCAPLL_1P053

CNP-H_BGA874

@

12

RH1010_0402_5% @

1P_0402_50V8

CH42

@

1-3MM FROM PACKAGE EDGE

A

+1.05VALW_VCCAMPHYPLL

22U_0402_6.3V6M

1

1

CH45

2

2

@

+1.05VALW_XTAL

22U_0402_6.3V6M

1

CH49

2

@

1U_0402_6.3V6K

CH46

+CHGRTC

RH104 10K_0402_5%

+RTCBATT

B

12

change to 10k

DH2

2
3

BAV70W_SOT323-3

+RTCVCC

1

.1U_0402_16V7K

1U_0402_6.3V6K

1

1

CH48

CH47

2

2

1 2

RH103 0_0402_5%@

LC filter colse to pin
1uF 1-3MM FROM PACKAGE EDGE

1 2

RH105 0_0402_5%@

NP-H

C

VCCPRIM_3P32

VCCPRIM_3P35

VCCPGPPG_3P3

VCCPRIM_3P33
VCCPRIM_3P34

VCCPGPPHK1
VCCPGPPHK2

VCCPGPPEF1
VCCPGPPEF2

VCCPGPPBC1
VCCPGPPBC2

VCCPRIM_3P31
VCCDSW_3P31
VCCDSW_3P32

VCCPRIM_1P83
VCCPRIM_1P84
VCCPRIM_1P85
VCCPRIM_1P86
VCCPRIM_1P87

VCCPRIM_1P81
VCCPRIM_1P82

VCCPRIM_1P0520
VCCPRIM_1P0519

VCCPRIM_1P241
VCCPRIM_1P242

VCCDPHY_1P241
VCCDPHY_1P242
VCCDPHY_1P243

VCCMPHY_SENSE
VSSMPHY_SENSE

8 OF 13

+3VALW_DSW

.1U_0402_16V7K

1

CH40

2

+3VALW_HDA

1

2

reserve filter folloe CRB
8/21

+RTCBATT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL

THIS SHEET OF ENGNEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D

AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D

AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVSION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

AW9
BF47

D

CPRTC1

BG47

DCPRTC2

V23
AN44

VCCSPI

BC49

VCCRTC1

BD49

VCCRTC2

AN21
AY8
BB7

AC35
AC36
AE35
AE36

AN24

VCCPGPPD

AN26
AP26

AN32

VCCPGPPA

AT44
BE48
BE49

BB14

VCCHDA

AG19
AG20
AN15
AR15
BB11

AF19
AF20

AG31
AF31
AK22
AK23

AJ22
AJ23
BG5

K47
K46

Rev1.0

+3VALW_PCH_PRIM +3VALW_SPI

RH98 0_0603_5%@

RH100 0_0603_5%@

JRTC1

1

1

2

2

3

GND

4

GND

ACES_50271-0020N-001

CONN@

SP02000RO00

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

+VCCRTCEXT

+1.8V_PHVLDO

VCCMPHY_SENSE
VSSMPHY_SENSE

1 2

1 2

0.182A

0.095A

0.05A

0.145A

0.97A

0.262A

0.174A

0.14A

0.343A

0.101A

0.106A

0.113A

0.00767A

0.766A

0.882A

0.193A

0.0895A

Internal LDO

Compal Secret Data

Compal Secret Data

Compal Secret Data

3VALW_PCH_PRIM

+

+1.8VALW_PRIM

+1.8V_PHVLDO

RH95 0_0402_5%@

TH27@
TH28@

+1.8VALW_PR M+1.8VALW

Deciphered Date

Deciphered Date

Deciphered Date

D

+

VCCRTCEXT

+3VALW_SPI

+RTCVCC

+1.8VALW_PR M

+3VALW_DSW

+3VALW_HDA

1 2

+1.05VALW_PCH

+1.05VALW_PCH
+1.24V_VCCLDOSRAM_ N
+1.24V_PRIM_DPHY
+1.24V_PRIM_MAR

1-3MM FROM PACKAGE
FOR PGPPEF AE35/AE37

+1.8VALW_PRIM

Short pins AJ22 AJ23 AK22 AK23 together
at surface layer from PDG Rev0 71

.1U_0402_16V7K

1

CH36

2

@

+VCCRTCEXT

.1U_0402_16V7K

1

CH24

2

+1.8VALW_PRIM

4.7U_0402_6.3V6M

1

1

CH27

2

2

VCCPHVLDO 1P8
(External VRM mode RH172 unmount)

For DDX03 R02

+1.24V_PRIM_MAR

4.7U_0402_6.3V6M

1

CH32

2

+3VALW_PCH_PRIM+3VALW_PCH_PRIM

.1U_0402_16V7K

1

2

1-3MM FROM PACKAGE
FOR PGPPHK AC35/AC36

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

T tle

T tle

T tle

PCH(7/8)Power

PCH(7/8)Power

PCH(7/8)Power

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

Date Sheet of

GPPA

GPPB
GPPC

GPPD

GPPE
GPPF

GPPG

PPH

G
GPPK

GPPI

GPPJ

GPD

1U_0402_63V6K

CH28

Close to BB11

+1.24V_VCCLDOSRAM_IN +1.24V_PRIM_DPHY

RH96 0_0402_5%@

RH174 for 571391 CFL H PDG Rev0p71 pdf

CH39

@

1-3MM FROM PACKAGE
FOR VCCPRIM AY8/BB7

E

1 2

+3VALW_PCH_PRIM

1U_0402_6.3V6K

1

CH37

2

3.3V

3.3V

1.8V

3.3V

3.3V

3.3V

3.3V Only

1.8V Only

3.3V Only

.1U_0402_16V7K

1

CH38

2

21 73Tuesday February 13 2018

21 73Tuesday February 13 2018

21 73Tuesday February 13 2018

1.A

1.A

1.A

A

www.laptoprepairsecrets.com

CNP-H

UH1I

A2

VSS

1 1

2 2

3 3

A28
A33

A37
A45

A46
A47
A48

AA19
AA20
AA25
AA27
AA28
AA30
AA31
AA49

AA5
AB19
AB25
AB31
AC12
AC17
AC33
AC38

AC4
AC46

AD1
AD19

AD2
AD22
AD25
AD49
AE12
AE33
AE38

AE4
AE46
AF22
AF25
AF28

AG1
AG22
AG23
AG25
AG27
AG28
AG30
AG49
AH12
AH17
AH33
AH38

AJ19
AJ20
AJ25
AJ27
AJ28
AJ30

AJ31
AK19
AK20
AK25
AK27
AK28
AK30
AK31

AK4

AK46

A3

A4

A5
A8

VSS

SS

V
VSS

SS

V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

9 OF 13

VSS

CNP-H_BGA874

@

VSS
VSS
V
VSS
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SS
SS

Rev1.0

AL12
AL17
AL21
AL24
AL26
AL29
AL33
AL38
AM1
AM18
AM32
AM49
AN12
AN16
AN34
AN38
AP4
AP46
AR12
AR16
AR34
AR38
AT1
AT16
AT18
AT21
AT24
AT26
AT29
AT32
AT34
AT45
AV11
AV39
AW10
AW4
AW40
AW46
B47
B48
B49
BA12
BA14
BA44
BA5
BA6
BB41
BB43
BB9
BC10
BC13
BC15
BC19
BC24
BC26
BC31
BC35
BC40
BC45
BC8
BD43
BE44
BF1
BF2
BF3
BF48
BF49
BG17
BG2
BG22
BG25
BG28

B

C

NP-H

U

H1L

BG3
BG33
BG37

BG4
BG48

C12
C25
C30

C48
D12

D16
D17
D30
D33

E10
E13
E15
E17
E19
E22
E24

E31
E33
E35
E40
E42

F41
F43
F47

G44

K11

K39
M16
M18
M21

E26

J10
J26
J29

J40
J46
J47
J48

C4
C5

D8

E8

G6

H8

J4

J9

VSS
VSS
VSS

SS

V
VSS

SS

V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CNP-H_BGA874

@

12 OF 13

VSS
VSS
VSS
V
VSS
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SS
SS

Rev1.0

M24
M32
M34
M49
M5
N12
N16
N34
N35
N37
N38
P26
P29
P4
P46
R12
R16
R26
R29
R3
R34
R38
R4
T17
T18
T32
T4
T49
T5
T7
U12
U15
U17
U21
U24
U33
U38
V20
V22
V4
V46
W25
W27
W28
W30
Y10
Y12
Y17
Y33
Y38
Y9

C

CNP-H

UH1J

CPU_TRST#

TRIGGER_OUT

TRIGGER_IN

10 OF 13

CNP-H_BGA874

@

RSVD7
RSVD8
RSVD6

SVD5

R

SVD3

R
RSVD4

RSVD2
RSVD1

PREQ#
PRDY#

Rev1.0

Y14
Y15
U37
U35

N32
R32

AH15
AH14

AL2
AM5
AM4
AK3
AK2

D

XDP_PREQ#
XDP_PRDY#
CPU_XDP_TRST#
PCH_TRIGOUT PCH_TRIGOUT_R
CPU_TRIGOUT_R

1 2

RH106 30_0402_5%

E

XDP_PREQ# <11>
XDP_PRDY# <11>
CPU_XDP_TRST# <11>

PCH_TRIGOUT_R <14>
CPU_TRIGOUT_R <14>

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2017/07/20 2018/07/20

2017/07/20 2018/07/20

2017/07/20 2018/07/20

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(8/8)GND/RSVD

PCH(8/8)GND/RSVD

PCH(8/8)GND/RSVD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

DH53F M/B LA-F991P

DH53F M/B LA-F991P

DH53F M/B LA-F991P

Date Sheet of

Date Sheet of

D

Date Sheet of

22 73Tuesday February 13 2018

22 73Tuesday February 13 2018

22 73Tuesday February 13 2018

E

1.A

1.A

1.A