A p A p p e n d p e n d i x E i x E
BIOS POST Checkpoints
This appendix lists the POST checkpoints of the notebook BIOS.
Table E-1 POST Checkpoint List
Checkpoint Description
04h
• Dispatch Shutdown Path
Note: At the beginning of POST, port 64 bit 2 (8042 system flag) is read to determine
whether this POST is caused by a cold or warm boot. If it is a cold boot, a
complete POST is performed. If it is a warm boot, the chip initialization and
memory test is eliminated from the POST routine.
08h
09h
0Ah
10h
14h
18h
1Ch
• Reset PIE, AIE, UIE
Note: These interrupts are disabled in order to avoid any incorrect actions from
happening during the POST routine.
• Initialize m1531
• Initialize m1533
• Initialize m7101
• DMA(8237) testing & initialization
• System Timer(8254) testing & initialization
• DRAM refresh cycle testing
• Set default SS:SP= 0:400
• CMOS shutdown byte test, battery, and check sum
Note: Several parts of the POST routine require the system to be in protected mode.
When returning to real mode from protected mode, the processor is reset,
therefore POST is re-entered. In order to prevent re-initialization of the system,
POST reads the shutdown code stored in location 0Fh in CMOS RAM. Then it
jumps around the initialization procedure to the appropriate entry point.
The CMOS shutdown byte verification assures that CMOS 0Fh area is fine to
execute POST properly.
• Initialize default CMOS setting if CMOS bad
• Initialize RTC time base
Note: The RTC has an embedded oscillator that generates a 32.768 KHz frequency. To
initialize the RTC time base, turn on this oscillator and set a divisor to 32768 so
that the RTC can count time correctly
1Dh, 1Eh
2Ch
• DRAM type determination
• 128K base memory testing
• Set default SS:SP= 0:400
Note: The 128K base memory area is tested for POST execution. The remaining
memory area is tested later.
BIOS POST Checkpoints E-1
Table E-1 POST Checkpoint List
Checkpoint Description
20h
24h
30h
34h
3Ch
4Bh
35h
40h
41h
44h
45h
50h
52h
4Ch
54h
58h
59h
5Ch
5Ah
4Eh
60h
64h
• KB controller(8041/8042) testing
• KB type determination
• Write default command byte upon KB type
• PIC(8259) testing & initialization
• System Shadow RAM
• DRAM sizing
• Initialize interrupt vectors
• Identify CPU brand and type
• PCI pass 0
• Assign I/O if device request
• Assign Memory if device requested
• Assign IRQ if device request
• Enable command byte if device is OK
• Initialize Video display
• Download keyboard matrix
• ChipUp initialization for CPU clock checking
• Process VGA shadow region
• Set POST screen mode(Graphic or Text)
• Display Acer(or OEM) logo if necessary
• Display Acer copyright message if necessary
• Display BIOS serial number
• Hook int vector 1ch for POST quiet boot
• Memory testing
• SMRAM test and SMI handler initialization
• Audio initialization
• External Cache sizing
• External Cache testing(SRAM & Controller)
• Enable internal cache if necessary
• Enable external cache if necessary
• Reset KB device
• Check KB status
Note: The keyboard LEDs should flash once.
7Ch
70h
74h
78h
• Reset pointing device
• Check pointing device
• Parallel port testing
• Serial port testing
• Math Coprocessor testing
E-2 Service Guide
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