Acer la-8061p Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

QAL30 Project

LA-8061P

3 3

SchematicREV 0.4

Intel Ivy Bridge/Panther Point

2012-01-13

4 4

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev. 0.4

Issued Date

Issued Date

Issued Date

C

Compal Secret Data

Compal Secret Data

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

E

1 46Friday, January 13, 2012

1 46Friday, January 13, 2012

1 46Friday, January 13, 2012

0.1

0.1

0.1

5

4

3

2

1

Compal Confidential

Model Name : QAL30

File Name : LA-8061PR01

D D

LVDS Conn. CRT Conn.HDMI Conn.

page 20 page 21page 22

CRT

HDMI

LVDS

Mobile Ivy Bridge

CPU Dual / Quad Core

Socket-rPGA989

37.5mm*37.5mm

page 4,5,6,7,8,9

(UMA)

100MHz

2.7GT/s

Intel Panther Point

PCBGA989

25mm*25mm

DMI x4FDI x8

100MHz
5GB/s

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1333/1600

USB

5V 480Mbps

USB/B Right

USB port 4,9

page 26

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

Int. Camera RTS5129 3IN1

USB port 10

page 20

USB port 11

page 26

page 10,11

PCI-Express (PCIE 2.5GT/s)

C C

port 2 port 1

PCIeMini Card

100MHz

RTL8111E 1G

WLAN & BT 2.0

PCIe port 1

RJ45

page 24

page 24

page 12,13,14,15,
16,17,18,19

USB port 13

PCIe port 2

page 23

LPC BUS

33MHz

SATA port 0

5V (6Gb/s)

SATA port 2

5V 1.5GHz(150MB/s)

HD Audio

3.3V 24.576MHz/48Mhz

SATA HDD

page 27

SATA ODD

page 27

BIOS ROM

page 30

HDA Codec

ALC259

page 25

ENE KB9012

B B

Touch Pad

USB/B

page 26

A A

Power/B

page 31

RTC CKT.

page 12

DC/DC Interface CKT.

page 34

(Co-Lay KB930)

page 26

page 29

Int.KBD

page 32

Int.

MIC CONN

page 25

MIC CONN

page 25

HP CONN

page 26

SPK CONN

page 26

CPU XDP

page 5

PCH XDP

page 12

Fan Control

page 31

Power Circuit DC/DC

page 35~44

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

1

2 46Wednesday, December 21, 2011

2 46Wednesday, December 21, 2011

2 46Wednesday, December 21, 2011

0.1

0.1

0.1

5

4

3

2

1

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0

D D

1
2
3
4
5
6
7 NC

100K +/- 5%Ra

Rb V min

0 0 V

8.2K +/- 5% 0.168V 0.250 V 0.362 V
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

V typ

AD_BID

0 V 0 V

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

V

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

max

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PCB Revision

QAL30

USB PORT#

0

1

2

3

4

DESTINATION

USB2/3 (Left Hand dise front)

USB2/3 (Left Hand dise back)

None

None

USB2 (Right Hand side front)

5

6

SMBUS Control Table

SOURCE

C C

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SMBCLK
PCH_SMBDATA PCH

PCH_SML1CLK
PCH_SML1DATA

KB930
KB9012

KB930
KB9012

PCH

MINI1 BATT SODIMM

0001 011x b 1001 000x b 1001 010x b

X

V

X

V

X

X

X

SODIMM

X
XX

V

X

X
X

V

X

PCH

X

V

CLKOUT

PCI0

PCI1

PCI2

PCI3

PCI4

DESTINATION

PCH_LOOPBACK

EC

TPM

None

None

PCH

7

8

9

10

11

12

13

None

None

None

None

USB2 (Left Hand side back)

CAMERA

Card Reader

None

BT Comb

OPTIMUS: XDP@/D@

DESTINATIONDIFFERENTIAL

B B

CLK

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

LAN

WLAN

None

None

None

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

None

None

None

None None

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

DESTINATION

HDD

None

ODD

None

None

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

DESTINATION

LAN

WLAN

None

None

CLKOUT_PCIE5

None

NoneCLKOUT_PCIE6

Symbol Note :

: means Digital Ground

SATA5

None

CLKOUT_PCIE7 None

A A

CLKOUT_PEG_A

VGA

: means Analog Ground

Lane 6

Lane 7

Lane 8

None

None

None

CLKOUT_PEG_B None

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

1

3 46Wednesday, December 21, 2011

3 46Wednesday, December 21, 2011

3 46Wednesday, December 21, 2011

0.1

0.1

0.1

5

JCPU1A

D D

DMI_CRX_PTX_N014
DMI_CRX_PTX_N114
DMI_CRX_PTX_N214
DMI_CRX_PTX_N314

DMI_CRX_PTX_P014
DMI_CRX_PTX_P114
DMI_CRX_PTX_P214
DMI_CRX_PTX_P314

DMI_CTX_PRX_N014
DMI_CTX_PRX_N114
DMI_CTX_PRX_N214
DMI_CTX_PRX_N314

DMI_CTX_PRX_P014
DMI_CTX_PRX_P114
DMI_CTX_PRX_P214
DMI_CTX_PRX_P314

FDI_CTX_PRX_N014
FDI_CTX_PRX_N114
FDI_CTX_PRX_N214
FDI_CTX_PRX_N314
FDI_CTX_PRX_N414
FDI_CTX_PRX_N514

C C

+V1.05S_VCCP

+V1.05S_VCCP

B B

FDI_CTX_PRX_N614
FDI_CTX_PRX_N714

FDI_CTX_PRX_P014
FDI_CTX_PRX_P114
FDI_CTX_PRX_P214
FDI_CTX_PRX_P314
FDI_CTX_PRX_P414
FDI_CTX_PRX_P514
FDI_CTX_PRX_P614
FDI_CTX_PRX_P714

FDI_FSYNC014
FDI_FSYNC114

FDI_INT14

FDI_LSYNC014
FDI_LSYNC114

RC2 24.9_0402_1%RC2 24.9_0402_1%

10K_0402_5%

10K_0402_5%
RC8

@RC8

@

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

EDP_COMP

EDP_HPD#

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

CONN@

CONN@

4

RC1

RC1

24.9_0402_1%

24.9_0402_1%

PEG_COMP

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

DMI

DMI

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

Intel(R) FDI

Intel(R) FDI

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

eDP

eDP

3

+V1.05S_VCCP

PEG_ICOMPI and RCOMPO signals should be short ed and routed
with - max leng th = 500 mils - typical impeda nce = 43 mohms
PEG_ICOMPO sign als should be r outed with - ma x length = 500 mils

- typical imped ance = 14.5 moh ms

2

JCPU1I

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS

1

F22

VSS234

F19

VSS235

E30

VSS236

E27

VSS237

E24

VSS238

E21

VSS239

E18

VSS240

E15

VSS241

E13

VSS242

E10

VSS243

E9

VSS244

E8

VSS245

E7

VSS246

E6

VSS247

E5

VSS248

E4

VSS249

E3

VSS250

E2

VSS251

E1

VSS252

D35

VSS253

D32

VSS254

D29

VSS255

D26

VSS256

D20

VSS257

D17

VSS258

C34

VSS259

C31

VSS260

C28

VSS261

C27

VSS262

C25

VSS263

C23

VSS264

C10

VSS265

C1

VSS266

B22

VSS267

B19

VSS268

B17

VSS269

B15

VSS270

B13

VSS271

B11

VSS272

B9

VSS273

B8

VSS274

B7

VSS275

B5

VSS276

B3

VSS277

B2

VSS278

A35

VSS279

A32

VSS280

A29

VSS281

A26

VSS282

A23

VSS283

A20

VSS284

A3

VSS285

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

CONN@

CONN@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

PROCESSOR(1/6) DMI,FDI,PEG

PROCESSOR(1/6) DMI,FDI,PEG

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

1

4 46Friday, January 13, 2012

4 46Friday, January 13, 2012

4 46Friday, January 13, 2012

0.1

0.1

0.1

5

4

3

2

1

SYSTEM_PWROK14

RC11

RC11

200_0402_1%

200_0402_1%

CLK_CPU_DMI 13
CLK_CPU_DMI# 13

+3V_PCH +3VS

RC12

RC12

0_0402_5%

0_0402_5%

RC21 0_0402_5%RC21 0_0402_5%

RUN_ON_CPU1.5VS3#9,34

PLT_RST#15,23,24,28,29

DDR3 Compensation Signals

SM_RCOMP0 XDP_TDO_R

SM_RCOMP1

SM_RCOMP2

@RC13

@

10K_0402_5%

10K_0402_5%

D_PWG

+V1.05S_VCCP

RC13

SUSP34,40

+3VS

RC15

RC15

200_0402_1%

200_0402_1%

@

D D

PM_DRAM_PWR GD14

C C

JCPU1B

Processor Pullups

H_PROCHOT#

H_CPUPWRGD

B B

A A

+V1.05S_VCCP

RC44

RC44
62_0402_5%

62_0402_5%

RC4510K_0402_5% RC4510K_0402_5%

H_PECI16,29

H_PROCHOT#29,35

H_THERMTRIP#16

H_PM_SYNC14

H_CPUPWRGD16

H_SNB_IVB#16

VDDPWRGOOD

T0501 @T0501 @

56_0402_5%

56_0402_5%

130_0402_1%

130_0402_1%

RC42

RC42

RC58

RC58

H_CATERR#

H_PROCHOT#_R

H_THERMTRIP#

VDDPWRGOOD_R

BUF_CPU_RST#

JCPU1B

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWR OK

AR33

RESET#

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

CONN@

CONN@

A28

BCLK

A27

BCLK#

CLK_CPU_DPLL_R

PRDY#

PREQ#

TCK
TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

TDI

A16
A15

R8

AK1
A5
A4

AP29
AP27

AR26
AR27
AP30

AR28
AP26

XDP_DBRESET#

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

CLK_CPU_DPLL#_R

H_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

XDP_PRDY#_R
XDP_PREQ#_R

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI_R
XDP_TDO_R

CLOCKS

CLOCKS

DDR3

DDR3

JTAG & BPM

JTAG & BPM

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

MISC

MISC

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

@

T504 @T504 @

T505 @T505 @

RC37 1K_0402_5%RC37 1K_0402_5%
RC41 1K_0402_5%RC41 1K_0402_5%

H_DRAMRST# 6

+3V_PCH

0.1U_0402_16V4Z

0.1U_0402_16V4Z

5

UC1

UC1

1

B

4

Y

VCC

2

A

G

MC74VHC1G09DFT2G_SC70-5

MC74VHC1G09DFT2G_SC70-5

3

RC17

RC17

0_0402_5%

0_0402_5%

RC16

@RC16

@

0_0402_5%

0_0402_5%

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CC36

CC36

1

5

UC2

UC2

P

BUFO_CPU_RST# BUF_CPU_RST#

4

NC

A2Y

G

SN74LVC1G07DCKR_SC70-5

SN74LVC1G07DCKR_SC70-5

3

RC56140_0402_1% RC56140_0402_1%

RC5925.5_0402_1% RC5925.5_0402_1%

RC61200_0402_1% RC61200_0402_1%

2

G

G

+V1.05S_VCCP

+1.5V_CPU_VDDQ

@

@

RC25

RC25
39_0402_1%

39_0402_1%

@

@

QC2

QC2

13

D

D

S

S

RC38

RC38
75_0402_5%

75_0402_5%

RC35

RC35

43_0402_1%

43_0402_1%

VDDPWRGOOD

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

CC33

CC33

PU/PD for JTAG signals

XDP_TMS_R

XDP_TDI_R

XDP_PREQ#_R

XDP_TCK_R

XDP_TRST#_R

RC14

RC14
200_0402_1%

200_0402_1%

@

@

RC40

RC40
0_0402_5%

0_0402_5%

+V1.05S_VCCP

RC4651_0402_5% RC4651_0402_5%

RC4751_0402_5% RC4751_0402_5%

RC4851_0402_5% @ RC4851_0402_5% @

RC4951_0402_5% RC4951_0402_5%

RC5351_0402_5% RC5351_0402_5%

RC5551_0402_5% RC5551_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

PROCESSOR(2/6) PM,XDP,CLK

PROCESSOR(2/6) PM,XDP,CLK

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

1

of

5 46Friday, January 13, 2012

5 46Friday, January 13, 2012

5 46Friday, January 13, 2012

0.1

0.1

0.1

5

JCPU1C

JCPU1C

DDR_A_D[0..63]10

D D

C C

B B

DDR_A_BS010
DDR_A_BS110
DDR_A_BS210

DDR_A_CAS#10
DDR_A_RAS#10
DDR_A_WE#10

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]

G10

SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]

M10

SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]

AG6

SA_DQ[32]

AG5

SA_DQ[33]

AK6

SA_DQ[34]

AK5

SA_DQ[35]

AH5

SA_DQ[36]

AH6

SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]

AK8

SA_DQ[41]

AJ9

SA_DQ[42]

AK9

SA_DQ[43]

AH8

SA_DQ[44]

AH9

SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]

AP11

SA_DQ[48]

AN11

SA_DQ[49]

AL12

SA_DQ[50]

AM12

SA_DQ[51]

AM11

SA_DQ[52]

AL11

SA_DQ[53]

AP12

SA_DQ[54]

AN12

SA_DQ[55]

AJ14

SA_DQ[56]

AH14

SA_DQ[57]

AL15

SA_DQ[58]

AK15

SA_DQ[59]

AL14

SA_DQ[60]

AK14

SA_DQ[61]

AJ15

SA_DQ[62]

AH15

SA_DQ[63]

AE10

SA_BS[0]

AF10

SA_BS[1]

V6

SA_BS[2]

AE8

SA_CAS#

AD9

SA_RAS#

AF9

SA_WE#

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

CONN@

CONN@

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]

SA_ODT[1]
RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

4

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDRA_CLK0 10
DDRA_CLK0# 10
DDRA_CKE0 10

DDRA_CLK1 10
DDRA_CLK1# 10
DDRA_CKE1 10

DDRA_SCS0# 10
DDRA_SCS1# 10

DDRA_ODT0 10
DDRA_ODT1 10

DDR_A_DQS#[0..7] 10

DDR_A_DQS[0..7] 10

DDR_A_MA[0..15] 10

3

DDR_B_D[0..63]11

DDR_B_BS011
DDR_B_BS111
DDR_B_BS211

DDR_B_CAS#11
DDR_B_RAS#11
DDR_B_WE#11

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

2

JCPU1D

JCPU1D

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

CONN@

CONN@

1

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

AB2

RSVD_TP[11]

AA2

RSVD_TP[12]

T9

RSVD_TP[13]

AA1

RSVD_TP[14]

AB1

RSVD_TP[15]

T10

RSVD_TP[16]

AD3

SB_CS#[0]

AE3

SB_CS#[1]

AD6

RSVD_TP[17]

AE6

RSVD_TP[18]

AE4

SB_ODT[0]

AD4

SB_ODT[1]

AD5

RSVD_TP[19]

AE5

RSVD_TP[20]

DDR_B_DQS#0

D7

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDRB_CLK0 11
DDRB_CLK0# 11
DDRB_CKE0 11

DDRB_CLK1 11
DDRB_CLK1# 11
DDRB_CKE1 11

DDRB_SCS0# 11
DDRB_SCS1# 11

DDRB_ODT0 11
DDRB_ODT1 11

DDR_B_DQS#[0..7] 11

DDR_B_DQS[0..7] 11

DDR_B_MA[0..15] 11

+1.5V

@

@

RC75 0_0402_5%

RC75 0_0402_5%

QC3

QC3

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

H_DRAMRST#5

A A

RC78

RC78

4.99K_0402_1%

4.99K_0402_1%

5

13

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

G

G

2

DRAMRST_CNTRL

CC37

CC37

0.047U_0402_16V4Z

0.047U_0402_16V4Z

RC76

RC76
1K_0402_5%

1K_0402_5%

RC77 1K_0402_5%RC77 1K_0402_5%

RC73 0_0402_5%RC73 0_0402_5%

4

SM_DRAMRST# 10,11

DRAMRST_CNTRL_PCH 13

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

PROCESSOR(3/6) DDRIII

PROCESSOR(3/6) DDRIII

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

1

6 46Friday, January 13, 2012

6 46Friday, January 13, 2012

6 46Friday, January 13, 2012

0.1

0.1

0.1

5

4

3

2

1

CFG Straps for Processor

D D

JCPU1E

JCPU1E

T0749@T0749@
T0750@T0750@

T0704@T0704@
T0705@T0705@
T0701@T0701@
T0702@T0702@

T0706@T0706@

T0707@T0707@
T0708@T0708@
T0709@T0709@

T0710@T0710@
T0711@T0711@
T0703@T0703@
T0712@T0712@

T0713@T0713@T0718 @T0718 @
T0714@T0714@
T0715@T0715@
T0716@T0716@
T0717@T0717@

T0719@T0719@
T0720@T0720@
T0721@T0721@
T0722@T0722@
T0723@T0723@

T0728@T0728@

CLK_RES_ITP 13
CLK_RES_ITP# 13

T0744@T0744@
T0745@T0745@
T0746@T0746@

T0748@T0748@

PEG Static Lane Reversal - CFG2 is for the 16x

Display Port Presence Strap

PCIE Port Bifurcation Straps

CFG[6:5]

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

KEY

RESERVED

RESERVED

VCC_DIE_SENSE
VSS_DIE_SENSE

RSVD_NCTF10

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

T1 @T1 @
T2 @T2 @
T3 @T3 @
T4 @T4 @
T5 @T5 @
T6 @T6 @
T7 @T7 @
T8 @T8 @
T9 @T9 @
T10 @T10 @
T11 @T11 @
T12 @T12 @
T13 @T13 @
T14 @T14 @
T15 @T15 @
T16 @T16 @
T17 @T17 @
T18 @T18 @

C C

B B

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

T0724 @T0724 @
T0725 @T0725 @
T0726 @T0726 @
T0727 @T0727 @
T0729 @T0729 @
T0731 @T0731 @
T0732 @T0732 @
T0733 @T0733 @
T0734 @T0734 @
T0735 @T0735 @
T0736 @T0736 @
T0737 @T0737 @
T0738 @T0738 @
T0739 @T0739 @ T0730@T0730@
T0740 @T0740 @
T0741 @T0741 @

T0742 @T0742 @
T0743 @T0743 @

T0747 @T0747 @

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

CONN@

CONN@

CFG

CFG

CFG2

RC79

RC79
1K_0402_1%

1K_0402_1%

1:(Default) Nor mal Operation; Lane #

CFG2

definition matc hes socket pin map definition
0:Lane Reversed

CFG4

RC82

@RC82

@

1K_0402_1%

1K_0402_1%

1 : Disabled; N o Physical Disp lay Port

CFG4

attached to Emb edded Display P ort

0 : Enabled; An external Displ ay Port device is
connected to th e Embedded Disp lay Port

CFG6

CFG5

RC83

@RC83

@

1K_0402_1%

1K_0402_1%

RC84

@RC84

@

1K_0402_1%

1K_0402_1%

11: (Default) x 16 - Device 1 f unctions 1 and 2 disabled

10: x8, x8 - De vice 1 function 1 enabled ; fu nction 2
disabled
01: Reserved - (Device 1 funct ion 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functi ons 1 and 2 ena bled

CFG7

RC85

@RC85

@

1K_0402_1%

1K_0402_1%

PEG DEFER TRAINING

1: (Default) PE G Train immedia tely

CFG7

following RESET B de assertion

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

0: PEG Wait for BIOS for train ing

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

PROCESSOR(4/6) RSVD,CFG

PROCESSOR(4/6) RSVD,CFG

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

7 46Friday, January 13, 2012

7 46Friday, January 13, 2012

7 46Friday, January 13, 2012

1

0.1

0.1

0.1

5

JCPU1H

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

D D

C C

B B

A A

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

TYCO_201362 0-2_IVY BRIDGE

TYCO_201362 0-2_IVY BRIDGE

CONN@

CONN@

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

4

JCPU1F

JCPU1F

+VCC_CORE

97A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

TYCO_201362 0-2_IVY BRIDGE

TYCO_201362 0-2_IVY BRIDGE

CONN@

CONN@

3

POWER

POWER

CORE SUPPLY

CORE SUPPLY

PEG AND DDR

PEG AND DDR

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE
VSS_SENSE

+V1.05S_VCCP

8.5A

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

130_0402_ 1%

130_0402_ 1%

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30

H_CPU_SVIDDAT

AJ28

Place the PU
resistors close to CPU

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

B10
A10

2

+V1.05S_VCCP +V1.05S_VCCP

RC91

RC91

RC90 43_040 2_1%RC90 43_0 402_1%
RC88 0_0402 _5%RC88 0 _0402_5%
RC92 0_0402 _5%RC92 0 _0402_5%

RC94 0_0402_5%RC94 0_0402_5%
RC95 0_0402_5%RC95 0_0402_5%

VCCIO_SENSE 39

12

RC98

RC98
10_0402_1 %

10_0402_1 %

Place the PU
resistors close to CPU

RC89

RC89
75_0402_5 %

75_0402_5 %

VCCIO_SENSE

+VCC_CORE

RC93

RC93
100_0402_ 1%

100_0402_ 1%

RC97

RC97
100_0402_ 1%

100_0402_ 1%

Close to CPU

R75

R75

1 2

10_0402_5 %

10_0402_5 %

VR_SVID_ALRT# 42
VR_SVID_CLK 42
VR_SVID_DAT 42

VCCSENSE 42
VSSSENSE 42

1

+V1.05S_VCCP

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

PROCESSOR(5/6) PWR,BYPASS

PROCESSOR(5/6) PWR,BYPASS

PROCESSOR(5/6) PWR,BYPASS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

8 46Friday, January 13, 2012

8 46Friday, January 13, 2012

8 46Friday, January 13, 2012

1

0.1

0.1

0.1

5

D D

RC104

CPU1.5V_S3_GATE29

RC104

0_0402_5%

0_0402_5%

@ RC100

@

2

RC100
100K_0402_5%

100K_0402_5%

4

RC101

RC101
100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3#

61

QC5A

QC5A
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

+VSBP+3VALW

RC99

RC99
100K_0402_5%

100K_0402_5%

3

QC5B

QC5B

5

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

4

3

+1.5V_CPU_VDDQ

QC4

QC4

+1.5V +1.5V_CPU_VDDQ

MDU1512RH_PPAK56-8-5

MDU1512RH_PPAK56-8-5

5

RUN_ON_CPU1.5VS3

4

0.1U_0603_50V7K

0.1U_0603_50V7K

CC39

CC39

RC102

RC102

330K_0402_1%

330K_0402_1%

2

1
2
3

R5521

R5521
470_0603_5%

470_0603_5%

1 2

13

D

D

RUN_ON_CPU1.5VS3#

S

S

2

G

G

Q5517

Q5517
2N7002H 1N SOT23-3

2N7002H 1N SOT23-3

RUN_ON_CPU1.5VS3# 5,34

1

Close to CPU

POWER

JCPU1G

JCPU1G

33A

AM24
AM23
AM21
AM20
AM18
AM17

AK24
AK23
AK21
AK20
AK18
AK17

AH24
AH23
AH21
AH20
AH18
AH17

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17

AL24
AL23
AL21
AL20
AL18
AL17

AJ24
AJ23
AJ21
AJ20
AJ18
AJ17

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

C C

+GFX_CORE

B B

+1.8VS

RC119

RC119

0_0805_5%

0_0805_5%

Material Note (+1.8VS_VCCPLL)

1 x 330 µF
Bottom Socket Edge
1U 0402 *1
10U 0805 *1

A A

+1.8VS_VCCPLL

10U_0805_6.3V6M

10U_0805_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CC58

CC58

CC59

CC59

2

2

5

1.5A

B6

VCCPLL1

1U_0402_6.3V6K

1U_0402_6.3V6K

CC60

CC60

A6

VCCPLL2

A2

330U_D2_2V_Y

330U_D2_2V_Y

1

@

@

+

+

2

CC61

CC61

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

CONN@

CONN@

POWER

GRAPHICS

GRAPHICS

1.8V RAIL

1.8V RAIL

4

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREFMISC

VREFMISC

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VCCSA_SENSE

VAXG_SENSE

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

AK35
AK34

AL1

B4
D1

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

A19

VCC_AXG_SENSE

VSS_AXG_SENSE

VCC_AXG_SENSE 42
VSS_AXG_SENSE 42

+V_SM_VREF_CNT

+1.5V_CPU_VDDQ

10A

6A

H_VCCSA_VID0 41
H_VCCSA_VID1 41

IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0

Sandy Bridge is NC for A19
VCCP_PWRCTRL:1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10U_0805_10VM

10U_0805_10VM

CC51

CC51

3

R78 100_0402_1%R78 100_0402_1%

R79 100_0402_1%R79 100_0402_1%

10U_0805_10VM

10U_0805_10VM

CC52

CC52

10U_0805_6.3V6M

10U_0805_6.3V6M

CC40

CC40

@RC112

@

10K_0402_5%

10K_0402_5%

+GFX_CORE

RC1070_0402_5% RC1070_0402_5%

QC6

QC6

@

@

D

S

D

S

13

G

G

PMV45EN_SOT23-3

PMV45EN_SOT23-3

2

RUN_ON_CPU1.5VS3

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_10VM

10U_0805_10VM

10U_0805_10VM

10U_0805_10VM

CC54

CC54

CC55

CC55

1 2

330U_D2_2V_Y

330U_D2_2V_Y

1

+

+

CC42

CC42

CC44

CC44

@

@

2

+VCCSA_SENSE 41

VCCP_PWRCTRLH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SEL

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

10U_0805_6.3V6M

10U_0805_6.3V6M

RC112

RC1140_0402_5% @ RC1140_0402_5% @

10U_0805_10VM

10U_0805_10VM CC41

CC53

CC53

CC41

@ R C111

@

0_0402_5%

0_0402_5%

+3VS

10U_0805_6.3V6M

10U_0805_6.3V6M

RC111

+V_SM_VREF

JP0901

@JP0901

@

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

330U_D2_2V_Y

330U_D2_2V_Y

1

CC56

CC56

Material Note (VDDQ)

+

+

CC57

CC57

Bottom Socket Edge
1 x 330 µF

2

10U 0805 *6

+VCCSA

+VCCSA_SENSE

RH235 100_0402_5%RH235 100_0402_5%

Material Note (VCCSA)

1 x 330 µF
Bottom Socket Cavity 10U 0805 *2
Bottom Socket Edge 10U 0805 *1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+1.5V_CPU_VDDQ

+1.5V

2

RC108

RC108
1K_0402_1%

1K_0402_1%

RC110

RC110
1K_0402_1%

1K_0402_1%

+V_SM_VREF should
have 10 mil trace width

+1.5V_CPU_VDDQ +1.5V

CC45 0.1U_0402_10V7KCC45 0.1U_0402_10V7K

CC46 0.1U_0402_10V7KCC46 0.1U_0402_10V7K

CC47 0.1U_0402_10V7KCC47 0.1U_0402_10V7K

CC48 0.1U_0402_10V7KCC48 0.1U_0402_10V7K

Compal Electronics, Inc.

Title

Title

Title

PROCESSOR(6/6) PWR,VSS

PROCESSOR(6/6) PWR,VSS

PROCESSOR(6/6) PWR,VSS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

Date: Sheet of

Date: Sheet of

Date: Sheet of

0.1

0.1

9 46Friday, January 13, 2012

9 46Friday, January 13, 2012

9 46Friday, January 13, 2012

1

0.1

5

+1.5V

RD1

RD1

1K_0402_1%

1K_0402_1%

+V_DDR_REFA

RD2

D D

C C

B B

A A

RD2

1K_0402_1%

1K_0402_1%

0.1U_0402_10V6K

0.1U_0402_10V6K
CD50

CD50

DDRA_CKE06

DDR_A_BS26

DDRA_CLK06
DDRA_CLK0#6

DDR_A_BS06

DDR_A_WE#6
DDR_A_CAS#6

DDRA_SCS1#6

+3VS

5

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
CD2

CD2

CD1

CD1

0.1U_0402_10V6K

0.1U_0402_10V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
CD25

CD25

+1.5V +1.5V

DDR3 SO-DIMM A

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDRA_CKE0

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDRA_CLK0
DDRA_CLK0#

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS# DDRA_ODT0

DDR_A_MA13
DDRA_SCS1#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

CD26

CD26

RD8

10K_0402_5%

RD8

10K_0402_5%

RD9

10K_0402_5%

RD9

10K_0402_5%

3A@1.5V

3A@1.5V

3A@1.5V3A@1.5V

JDDRL

@JDDRL

@

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013022-2

TYCO_2-2013022-2

4

4

VSS3

DQS#0

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

VTT2

DQ4
DQ5

DQ6
DQ7

A15
A14

A11

CK1

BA1

S0#

SCL

3

DDR_A_D[0..63]6

DDR_A_DQS[0..7]6

DDR_A_DQS#[0..7]6

DDRA_CKE1 6

0.1U_0402_10V6K

0.1U_0402_10V6K

DDR_A_MA[0..15]6

+1.5V

RD6

RD6
1K_0402_1%

1K_0402_1%

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

CD15

CD15

CD16

CD16

RD7

RD7
1K_0402_1%

1K_0402_1%

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

3

+VREF_CA

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26
28

SM_DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44
46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDRA_CKE1

74
76

DDR_A_MA15

78

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86

A7

88

DDR_A_MA6

90

A6
A4

A2
A0

G2

DDR_A_MA4

92
94

DDR_A_MA2

96

DDR_A_MA0

98
100

DDRA_CLK1

102

DDRA_CLK1#

104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDRA_SCS0#

114
116
118

DDRA_ODT1

120
122
124
126
128

DDR_A_D36

130

DDR_A_D37

132
134
136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168
170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198
200
202
204

206

+0.75VS

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

SM_DRAMRST# 6,11

DDRA_CLK1 6
DDRA_CLK1# 6

DDR_A_BS1 6
DDR_A_RAS# 6

DDRA_SCS0# 6
DDRA_ODT0 6

DDRA_ODT1 6

PCH_SMBDATA 11,13,23
PCH_SMBCLK 11,13,23

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Layout Note:

+1.5V

330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

CD7

CD7

1

+

+

@

@

2

2

Place near JDDRL

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD9

CD9

CD8

CD8

1

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

10U_0603_6.3V6M

CD10

CD10

1

1

2

2

Layout Note: Place these 4 Caps near
Command and Control signals of JDDRL

+1.5V

0.1U_0402_10V6K

0.1U_0402_10V6K
CD17

CD17

Layout Note:
Place near JDDRL.203,204

+0.75VS

CD21

1U_0402_6.3V6K

CD21

1U_0402_6.3V6K

1

1

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDRIII-DDRL

DDRIII-DDRL

DDRIII-DDRL

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD12

CD12

CD11

CD11

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
CD18

CD18

CD22

1U_0402_6.3V6K

CD22

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD13

CD13

CD14

1

2

CD19

CD19

CD23

1U_0402_6.3V6K

CD23

1U_0402_6.3V6K

1

CD14

1

1

@

@

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K
CD20

CD20

CD24

1U_0402_6.3V6K

CD24

1U_0402_6.3V6K

1

2

0.1

0.1

10 46Friday, January 13, 2012

10 46Friday, January 13, 2012

10 46Friday, January 13, 2012

0.1

5

+1.5V

RD10

RD10

1K_0402_1%

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1K_0402_1%

0.1U_0402_10V6K

0.1U_0402_10V6K

CD28

CD28

DDRB_CKE06

DDR_B_BS26

DDRB_CLK06
DDRB_CLK0#6

DDR_B_BS06

DDR_B_WE#6
DDR_B_CAS#6

DDRB_SCS1#6

+3VS

0.1U_0402_10V6K

0.1U_0402_10V6K

DDR_B_D0

RD11

RD11

CD27

CD27

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
CD48

CD48

DDR_B_D1

CD51

CD51

DDR_B_D2
DDR_B_D3

DDR_B_D8

1K_0402_1%

1K_0402_1%

DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDRB_CKE0

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

DDRB_CLK0
DDRB_CLK0#

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS# DDRB_ODT0

DDR_B_MA13
DDRB_SCS1#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

RD14

RD14

10K_0402_5%

10K_0402_5%

0.1U_0402_10V6K

0.1U_0402_10V6K
CD49

CD49

RD15 10K_0402_5%RD15 10K_0402_5%

5

+V_DDR_REFB

D D

C C

B B

A A

+1.5V +1.5V

3A@1.5V

3A@1.5V

3A@1.5V3A@1.5V

JDDRH

@JDDRH

@

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO 2-1932300-1 204P H8.0

TYCO 2-1932300-1 204P H8.0

VSS3

DQS#0

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

VTT2

4

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26
28

SM_DRAMRST#

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44
46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDRB_CKE1

74
76

DDR_B_MA15

78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

DDR_B_MA14

80
82

DDR_B_MA11

84

DDR_B_MA7

86
88

DDR_B_MA6

90

DDR_B_MA4

92
94

DDR_B_MA2

96

DDR_B_MA0

98
100

DDRB_CLK1

102

DDRB_CLK1#

104
106

DDR_B_BS1

108

DDR_B_RAS#

110
112

DDRB_SCS0#

114
116
118

DDRB_ODT1

120
122
124

+VREF_CB

126
128

DDR_B_D36

130

DDR_B_D37

132
134
136
138

DDR_B_D38

140

DDR_B_D39

142
144

DDR_B_D44

146

DDR_B_D45

148
150

DDR_B_DQS#5

152

DDR_B_DQS5

154
156

DDR_B_D46

158

DDR_B_D47

160
162

DDR_B_D52

164

DDR_B_D53

166
168
170
172

DDR_B_D54

174

DDR_B_D55

176
178

DDR_B_D60

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198
200
202
204

206

4

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

SM_DRAMRST# 6,10

DDRB_CKE1 6

DDRB_CLK1 6
DDRB_CLK1# 6

DDR_B_BS1 6
DDR_B_RAS# 6

DDRB_SCS0# 6
DDRB_ODT0 6

DDRB_ODT1 6

0.1U_0402_10V6K

0.1U_0402_10V6K

CD46

CD46

PCH_SMBDATA 10,13,23
PCH_SMBCLK 10,13,23

+0.75VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_B_DQS#[0..7]6

DDR_B_D[0..63]6

DDR_B_DQS[0..7]6

DDR_B_MA[0..15]6

RD12

RD12

1K_0402_1%

1K_0402_1%

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

CD47

CD47

1K_0402_1%

1K_0402_1%

3

RD13

RD13

3

+1.5V

Compal Secret Data

Compal Secret Data

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Layout Note:
Place near JDDRH

+1.5V

@

@

2

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

CD31

CD31

1

+

+

2

CD35

CD35

CD34

CD34

1

@

@

@

@

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD36

CD36

CD37

CD37

1

1

2

1

2

2

Layout Note: Place these 4 Caps near
Command and Control signals of JDDRH

+1.5V

Layout Note:
Place near JDDRH.203 and 204

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD39

CD39

CD38

CD38

1

1

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
CD32

CD32

CD29

CD29

+0.75VS

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

CD42

CD42

DDRIII-DDRH

DDRIII-DDRH

DDRIII-DDRH

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD40

CD40

0.1U_0402_10V6K

0.1U_0402_10V6K
CD30

CD30

1U_0603_10V6K

1U_0603_10V6K

CD43

CD43

CD44

CD44

11 46Friday, January 13, 2012

11 46Friday, January 13, 2012

11 46Friday, January 13, 2012

10U_0603_6.3V6M

10U_0603_6.3V6M

CD41

CD41

1

1

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K
CD33

CD33

1U_0603_10V6K

1U_0603_10V6K

CD45

CD45

0.1

0.1

0.1

5

PCH_RTCX1

RH2 10M_0402_5%RH2 10M_0402_5%

1 2

YH1 32.768KHZ_12.5PF_CM31532768DZFTYH1 32.768KHZ_12.5PF_CM31532768DZFT

PCH_RTCX2

4

3

2

1

+RTCVCC

RH23 20K_0402_5%RH23 20K_0402_5%

RH24 20K_0402_5%RH24 20K_0402_5%

+RTCVCC

HDA_SDOUT

HDA_BIT_CLK

HDA_RST#

HDA_SDOUT

RH40

RH40

XDP@

XDP@

200_0402_5%

200_0402_5%

RH46

RH46

XDP@

XDP@

100_0402_1%

100_0402_1%

PCH_JTAG_TCK

RH56

RH56

1M_0402_5%

1M_0402_5%

+RTCVCC

RH12 1M_0402_5%RH12 1M_0402_5%

CH4

CH4

1U_0402_6.3V4Z

1U_0402_6.3V4Z

CH5

CH5

1U_0402_6.3V4Z

1U_0402_6.3V4Z

+5VS

S

S

12

1

12

SHORT PADS

SHORT PADS

2

1

12

SHORT PADS

SHORT PADS

2

CLP1 & CLP2 place near DIMM

PCH_SPI_CS#30

PCH_SPI_CS1#30

PCH_SPI_MOSI30

PCH_SPI_MISO30

G

G

2

13

D

D

BSS138_SOT23

BSS138_SOT23
QH1

QH1

CMOS

CLRP1

CLRP1

CLRP2

CLRP2

ME CMOS

PCH_SPKR25

AZ_SDIN0_HD25

PCH_SPI_CLK30

HDA_SYNCAZ_SYNC_HD_R

SM_INTRUDER#

UH1A

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

PCH_SPKR

HDA_RST#

AZ_SDIN0_HD

HDA_SDOUT

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS#

PCH_SPI_CS1#

PCH_SPI_MOSI

PCH_SPI_MISO

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST # / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

RTCIHDA

RTCIHDA

JTAG

JTAG

SPI

SPI

SPI ROM FOR ME ( 4MByte )

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA 6G

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36

E36

LPC_LDRQ1#

K36

SERIRQ

V5

SATA_PRX_C_DTX_N0

AM3

SATA_PRX_C_DTX_P0

AM1

SATA_PTX_DRX_N0

AP7

SATA_PTX_DRX_P0

AP5

AM10
AM8
AP11
AP10

SATA_PRX_C_DTX_N2

AD7

SATA_PRX_C_DTX_P2

AD5

SATA_PTX_DRX_N2

AH5

SATA_PTX_DRX_P2

AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

PCH_SATALED#

P3

PCH_GPIO21

V14

BBS_BIT0_R

P1

SATA_COMP

SATA3_COMP

RBIAS_SATA3

RH34 10K_0402_5%

RH34 10K_0402_5%

LPC_AD0 28,29
LPC_AD1 28,29
LPC_AD2 28,29
LPC_AD3 28,29

LPC_FRAME# 28,29

T1509 PAD@ T1509 PAD@

SERIRQ 28,29

SATA_PRX_C_DTX_N0 27
SATA_PRX_C_DTX_P0 27
SATA_PTX_DRX_N0 27
SATA_PTX_DRX_P0 27

SATA_PRX_C_DTX_N2 27
SATA_PRX_C_DTX_P2 27
SATA_PTX_DRX_N2 27
SATA_PTX_DRX_P2 27

+1.05VS_VCC_SATA

RH41 37.4_0402_1%RH41 37.4_0402_1%

RH43 49.9_0402_1%RH43 49.9_0402_1%

RH48 750_0402_1%RH48 750_0402_1%

@

@

+1.05VS_SATA3

PCH_SATALED# 32

12

+3VS

HDD

ODD

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash
Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

+3VS

SERIRQ

PCH_GPIO21

PCH_SATALED#

PCH_SPKR

HDA_SDOUT

HDA_SYNC

This signal has a weak interna l pull-down
On Die PLL VR i s supplied by

1.5V when smapl ed high

1.8V when sampl ed low
Needs to be pul led High for Ch ief River platf rom

HDA_SYNC

RH28 10K_0402_5%RH28 10K_0402_5%

RH29 10K_0402_5%RH29 10K_0402_5%

RH31 10K_0402_5%RH31 10K_0402_5%

RH36 1K_0402_5%@RH36 1K_0402_5%@

LOW=Default
HIGH=No Reboot

*

RH42 1K_0402_5%@RH42 1K_0402_5%@

Low = Disabled

*

High = Enabled

+3V_PCH

RH55 1K_0402_5%RH55 1K_0402_5%

+3VS

+3V_PCH

CH3

CH2

CH2
12P_0402_50V8J

12P_0402_50V8J

D D

far away hot spot

PCH_INTVRMEN

H：Integrated VRM enable

*

L：Integrated VRM disable

ME_EN from EC.
Please place cl ose to RH32avio d the branch.

ME_EN29

C C

AZ_BITCLK_HD25

AZ_RST_HD#25

AZ_SDOUT_HD25

+3V_PCH +3V_PCH+3V_PCH

RH38

RH38

XDP@

XDP@

200_0402_5%

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

RH44

RH44

XDP@

XDP@

100_0402_1%

100_0402_1%

Intel DPDG Rev1.2 requirement.

B B

AZ_SYNC_HD25

CH3
12P_0402_50V8J

12P_0402_50V8J

RH33 330K_0402_5%RH33 330K_0402_5%

RH25 0_0402_5%LOCK@RH25 0_0402_5%LOCK@

1 2

RH27 33_0402_5%RH27 33_0402_5%

1 2

RH30 33_0402_5%RH30 33_0402_5%

1 2

RH32 33_0402_5%RH32 33_0402_5%

RH39

RH39

XDP@

XDP@

200_0402_5%

200_0402_5%

RH45

RH45

XDP@

XDP@

100_0402_1%

100_0402_1%

RH50

XDP@RH50

XDP@

51_0402_5%

51_0402_5%

1 2

RH54 33_0402_5%RH54 33_0402_5%

Intel recommend

RTC Battery

+RTCBATT

MAX. 8000mil

RH62

CH7

CH7

RH65

RH65

PCH_SPI_CLK

0_0402_5%

10P_0402_50V8J

10P_0402_50V8J

Reserve for EMI

A A

0_0402_5%

5

Remove JDBG1

+RTCVCC

W=20mils

1

CH8

CH8
1U_0603_10V4Z

1U_0603_10V4Z

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

4

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

RH62
1K_0402_5%

1K_0402_5%

W=20mils

1

DH1

DH1

2

3

BAS40-04_SOT23-3

BAS40-04_SOT23-3

1

+CHGRTC

W=20mils

12 46Friday, January 13, 2012

12 46Friday, January 13, 2012

12 46Friday, January 13, 2012

0.1

0.1

0.1

5

4

3

2

1

PCH_GPIO11

SMBCLK

UH1B

D D

10/100/1G LAN --->

MiniWLAN (Mini Card 1)--->

C C

10/100/1G LAN --->

MiniWLAN (Mini Card 1)--->

B B

@

@

RH113

CLK_PCI_LPBACK

Reserve for EMI please close t o
UH4

CH26

CH26

1

15P_0402_50V8J

15P_0402_50V8J

1

2

A A

RH113

33_0402_5%

33_0402_5%

RH1171M_0402_5% RH1171M_0402_5%

YH2

YH2

1

GND

GND

2

4

25MHZ_20PF_7V25000016

25MHZ_20PF_7V25000016

3

12

1 2

22P_0402_50V8J

22P_0402_50V8J

3

15P_0402_50V8J

15P_0402_50V8J

1

CH27

CH27

2

5

PCIE_PRX_GLANTX_N124
PCIE_PRX_GLANTX_P124
PCIE_PTX_GLANRX_N124
PCIE_PTX_GLANRX_P124

PCIE_PRX_WLANTX_N223
PCIE_PRX_WLANTX_P223
PCIE_PTX_WLANRX_N223
PCIE_PTX_WLANRX_P223

@

@

CH25

CH25

XTAL25_IN

XTAL25_OUT

CH9 0.1U_0402_10V7KCH9 0.1U_0402_10V7K
CH12 0.1U_0402_10V7KCH12 0.1U_0402_10V7K

CH13 0.1U_0402_10V7KCH13 0.1U_0402_10V7K
CH14 0.1U_0402_10V7KCH14 0.1U_0402_10V7K

CLK_PCIE_LAN#24
CLK_PCIE_LAN24

+3V_PCH

LANCLK_REQ#24

CLK_PCIE_WLAN#23
CLK_PCIE_WLAN23

WLANCLK_REQ#23

+3VS

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

CLK_RES_ITP#7
CLK_RES_ITP7

RH92 0_0402_5%RH92 0_0402_5%
RH93 0_0402_5%RH93 0_0402_5%

RH95 10K_0402_5%RH95 10K_0402_5%

RH97 0_0402_5%RH97 0_0402_5%
RH98 0_0402_5%RH98 0_0402_5%

RH99 10K_0402_5%RH99 10K_0402_5%

RH104 10K_0402_5%RH104 10K_0402_5%

RH107 10K_0402_5%RH107 10K_0402_5%

RH109 10K_0402_5%RH109 10K_0402_5%

RH112 10K_0402_5%RH112 10K_0402_5%

RH114 10K_0402_5%RH114 10K_0402_5%

RH116 10K_0402_5%RH116 10K_0402_5%

RH119 10K_0402_5%RH119 10K_0402_5%

RH122 0_0402_5%@RH122 0_0402_5%@
RH123 0_0402_5%@RH123 0_0402_5%@

PCIE_PRX_GLANTX_N1
PCIE_PRX_GLANTX_P1
PCIE_PTX_GLANRX_N1_C
PCIE_PTX_GLANRX_P1_C

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2_C
PCIE_PTX_WLANRX_P2_C

PCIE_LAN#
PCIE_LAN

LANCLK_REQ#

PCIE_WLAN#
PCIE_WLAN

WLANCLK_REQ#

PCH_GPIO20

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

CLK_BCLK_ITP#
CLK_BCLK_ITP

4

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

SMBUSController

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

PCI-E*

CLOCKS

CLOCKS

PCH_GPIO11

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

3

E12

SMBCLK

H14

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKIN_DMI_N
CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

SML0CLK

C8

SML0DATA

G12

PCH_HOT#

C13

SML1CLK

E14

SML1DATA

M16

M7

T11

P10

PCH_GPIO47

M10

AB37
AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12
AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

Y47

K43

F47

H47

K49

XCLK_RCOMP

MEMORY

DRAMRST_CNTRL_PCH 6

PCH_HOT# 29

RH8910K_0402_5% RH8910K_0402_5%

CLK_CPU_DMI# 5
CLK_CPU_DMI 5

CLK_PCI_LPBACK 15

RH115 90.9_0402_1%RH115 90.9_0402_1%

+3VS

RC50

RC50
10K_0402_5%

10K_0402_5%

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

+1.05VS_VCCDIFFCLKN

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

+3V_PCH

SMBCLK

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

SMBDATA

2

6 1

QH3A

QH3A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

SML1CLK

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

SML1DATA

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

PCH_HOT#

DRAMRST_CNTRL_PCH

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M

If use extenal CLK gen, please place close to CLK gen
else, please pl ace close to PC H

RH102

RH102

2.2K_0402_5%

2.2K_0402_5%

5

3

4

QH3B

QH3B

+3VS

2

6 1

QH4A

QH4A

3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Title

Title

Title

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

Date: Sheet of

Date: Sheet of

Date: Sheet of

RH105 10K_0402_5%RH105 10K_0402_5%

RH70 2.2K_0402_5%RH70 2.2K_0402_5%

RH72 2.2K_0402_5%RH72 2.2K_0402_5%

RH77 2.2K_0402_5%RH77 2.2K_0402_5%

RH73 2.2K_0402_5%RH73 2.2K_0402_5%

RH74 2.2K_0402_5%RH74 2.2K_0402_5%

RH78 2.2K_0402_5%RH78 2.2K_0402_5%

RH75 10K_0402_5%RH75 10K_0402_5%

RH76 1K_0402_1%RH76 1K_0402_1%

RH79

RH79
RH80

RH80
RH81 10K_0402_5%RH81 10K_0402_5%
RH82 10K_0402_5%RH82 10K_0402_5%
RH83 10K_0402_5%RH83 10K_0402_5%
RH84 10K_0402_5%RH84 10K_0402_5%
RH85 10K_0402_5%RH85 10K_0402_5%
RH86 10K_0402_5%RH86 10K_0402_5%
RH87 10K_0402_5%RH87 10K_0402_5%

+3VS+3VS

RH103

RH103

2.2K_0402_5%

2.2K_0402_5%

PU AT EC SIDE, +3VS AND 2.2K

5

4

QH4B

QH4B

10K_0402_5%

10K_0402_5%
10K_0402_5%

10K_0402_5%

PCH_SMBCLK 10,11,23

PCH_SMBDATA 10,11,23

Compal Electronics, Inc.

1

+3V_PCH

PCH_SMLCLK 29

PCH_SMLDATA 29

13 46Friday, January 13, 2012

13 46Friday, January 13, 2012

13 46Friday, January 13, 2012

0.1

0.1

0.1

5

UH1C

UH1C

DH2

DH2

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOMP

RBIAS_CPY

XDP_DBRESET#_R

SYSTEM_PWROK

SUSWARN#

PBTN_OUT#_R

AC_PRESENT_R

DMI_CTX_PRX_N04
DMI_CTX_PRX_N14
DMI_CTX_PRX_N24
DMI_CTX_PRX_N34

DMI_CTX_PRX_P04

D D

C C

PCH_PWROK29

PM_DRAM_PWRGD5

PCH_RSMRST#29

DMI_CTX_PRX_P14
DMI_CTX_PRX_P24
DMI_CTX_PRX_P34

DMI_CRX_PTX_N04
DMI_CRX_PTX_N14
DMI_CRX_PTX_N24
DMI_CRX_PTX_N34

DMI_CRX_PTX_P04
DMI_CRX_PTX_P14
DMI_CRX_PTX_P24
DMI_CRX_PTX_P34

+1.05VS_PCH

RH126 49.9_0402_1%RH126 49.9_0402_1%

RH127 750_0402_1%RH127 750_0402_1%

4mil width and place
within 500mil of the PCH

T1710PAD T1710PAD

RH132 0_0402_5%RH132 0_0402_5%

PBTN_OUT#29

ACIN29,36

RH137 0_0402_5%RH137 0_0402_5%

1 2

RB751V-40_SOD323-2

RB751V-40_SOD323-2

APWROK

PCH_GPIO72

RI#

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

4

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

System Power Management

SLP_LAN# / GPIO29

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

FDI_RXP6

BH9

FDI_RXP7

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

A18

DSWVRMEN

E22

DPWROK

B9

WAKE#

N3

G8

N14

D10

H4

SLP_S4#

F4

SLP_S3#

G10

SLP_A#

G16

SLP_SUS#

AP14

PMSYNCH

K14

Check EC for S3 S4 LED

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCIE_WAKE#

PM_CLKRUN#

SUS_STAT#

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PCH_GPIO29

FDI_CTX_PRX_N0 4
FDI_CTX_PRX_N1 4
FDI_CTX_PRX_N2 4
FDI_CTX_PRX_N3 4
FDI_CTX_PRX_N4 4
FDI_CTX_PRX_N5 4
FDI_CTX_PRX_N6 4
FDI_CTX_PRX_N7 4

FDI_CTX_PRX_P0 4
FDI_CTX_PRX_P1 4
FDI_CTX_PRX_P2 4
FDI_CTX_PRX_P3 4
FDI_CTX_PRX_P4 4
FDI_CTX_PRX_P5 4
FDI_CTX_PRX_P6 4
FDI_CTX_PRX_P7 4

FDI_INT 4

FDI_FSYNC0 4

FDI_FSYNC1 4

FDI_LSYNC0 4

FDI_LSYNC1 4

RH128 0_0402_5%RH128 0_0402_5%

PM_CLKRUN# 28

T1701 PADT1701 P AD

T1702 PADT1702 PAD

T1703 PADT1703 PAD

T1704 PADT1704 PAD

T1724 PADT1724 PAD

T1705 PADT1705 PAD

T1706 PADT1706 PAD

H_PM_SYNC 5

Pull high at LVDS conn side.

PCH_RSMRST#PCH_DPWROK

PCIE_WAKE# 23,24

SUS_CK 29

PM_SLP_S5# 29

PM_SLP_S4# 29

PM_SLP_S3# 29

Can be left NC when IAMT is
not support on the platfrom

3

PCH_ENBKL29

PCH_ENVDD20

PCH_BL_PWM20

LCD_EDID_CLK20
LCD_EDID_DATA20

RH245 2.37K_0402_1%RH245 2.37K_0402_1%

LCD_TXCLK-20
LCD_TXCLK+20

LCD_TXOUT0-20
LCD_TXOUT1-20
LCD_TXOUT2-20

LCD_TXOUT0+20
LCD_TXOUT1+20
LCD_TXOUT2+20

PCH_CRT_B21
PCH_CRT_G21
PCH_CRT_R21

PCH_CRT_CLK21

PCH_CRT_DATA21

PCH_CRT_HSYNC21
PCH_CRT_VSYNC21

R286

R286
R288

R288

33_0402_5%

33_0402_5%

33_0402_5%

33_0402_5%

1K_0402_0.5%

1K_0402_0.5%

PCH_ENBKL

CTRL_CLK
CTRL_DATA

LVDS_IBG

12

LCD_TXCLK­LCD_TXCLK+

LCD_TXOUT0­LCD_TXOUT1­LCD_TXOUT2-

LCD_TXOUT0+
LCD_TXOUT1+
LCD_TXOUT2+

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

PCH_CRT_CLK
PCH_CRT_DATA

PCH_CRT_HSYNC_R

12

PCH_CRT_VSYNC_R

12

RH138

RH138

CRT_IREF

2

R398

R398
100K_0402_5%

100K_0402_5%

1 2

UH1D

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

1

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

RH142

UMA_HDMI_TX2­UMA_HDMI_TX2+
UMA_HDMI_TX1­UMA_HDMI_TX1+
UMA_HDMI_TX0­UMA_HDMI_TX0+
UMA_HDMI_TXC­UMA_HDMI_TXC+

20K_0402_5%

20K_0402_5%

1 2

@RH142

@

UMA_HDMI_CLK 22
UMA_HDMI_DATA 22

UMA_HDMI_HPD 22

UMA_HDMI_TX2- 22
UMA_HDMI_TX2+ 22
UMA_HDMI_TX1- 22
UMA_HDMI_TX1+ 22
UMA_HDMI_TX0- 22
UMA_HDMI_TX0+ 22
UMA_HDMI_TXC- 22
UMA_HDMI_TXC+ 22

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

CRT

B B

+3VS

RH294 2.2K_0402_5%RH294 2.2K_0402_5%

+3VS

5

UH5

UH5

2

VGATE29,42

A A

PCH_PWROK

5

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

3

PCH_GPIO72

RI#

PCIE_WAKE#

AC_PRESENT_R

SUSWARN#

PCH_GPIO29

XDP_DBRESET#_R

SYSTEM_PWROK

PCH_RSMRST#

SYSTEM_PWROK

4

RH155 10K_0402_5%RH155 10K_0402_5%

RH157 10K_0402_5%RH157 10K_0402_5%

RH159 10K_0402_5%RH159 10K_0402_5%

RH161 330K_0402_5%RH161 330K_0402_5%

RH234 10K_0402_5%RH234 10K_0402_5%

RH162 10K_0402_5%@RH162 10K_0402_5%@

RH156 1K_0402_5%RH156 1K_0402_5%

RH168 10K_0402_5%RH168 10K_0402_5%

RH163 10K_0402_5%RH163 10K_0402_5%

SYSTEM_PWROK 5

+3V_PCH

+3VS

DSWODVREN

DSWODVREN

4

RH150 330K_0402_5%RH150 330K_0402_5%

RH151 330K_0402_5%@RH151 330K_0402_5%@

DSWODVREN - On Die DSW VR Enab le

H：Enable

*

L：Disable

PM_CLKRUN#

+3VS

RH256

RH256

8.2K_0402_5%

8.2K_0402_5%

RH160

RH160
10K_0402_5%

10K_0402_5%

@

@

+RTCVCC

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/23 2012/12/31

2011/05/23 2012/12/31

2011/05/23 2012/12/31

1 2

RH295 2.2K_0402_5%RH295 2.2K_0402_5%

1 2

RH135 150_0402_1%RH135 150_0402_1%

1 2

RH136 150_0402_1%RH136 150_0402_1%

1 2

RH139 150_0402_1%RH139 150_0402_1%

1 2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PCH_CRT_CLK

PCH_CRT_DATA

PCH_CRT_B

PCH_CRT_G

PCH_CRT_R

2

+3VS

R368 2.2K_0402_5%R368 2.2K_0402_5%

1 2

R369 2.2K_0402_5%R369 2.2K_0402_5%

1 2

R394 2.2K_0402_5%R394 2.2K_0402_5%

1 2

R393 2.2K_0402_5%R393 2.2K_0402_5%

1 2

R395 2.2K_0402_5%R395 2.2K_0402_5%

1 2

R396 2.2K_0402_5%R396 2.2K_0402_5%

1 2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP

QAL30 LA-8061P MB

QAL30 LA-8061P MB

QAL30 LA-8061P MB

CTRL_CLK

CTRL_DATA

LCD_EDID_CLK

LCD_EDID_DATA

UMA_HDMI_CLK

UMA_HDMI_DATA

1

0.1

0.1

14 46Friday, January 13, 2012

14 46Friday, January 13, 2012

14 46Friday, January 13, 2012

0.1