Acer LA-733B Schematics

A

1 1

2 2

B

C

D

E

Hurricane 1.6

N32N LA-733 REV. 4A SCHEMATIC DOCUMENT

3 3

4 4

A

uPGA2 COPPERMINE with Geyserville

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

B

C

D

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, inc.

SCHEMATIC, M/B LA-733

401138

E

147Tuesday, August 21, 2001

4C

of

A

Compal confidential

Model Name : N32N
Board Name : LA-733

B

C

D

Revision History
Date:06/28/2000 Rev#: 2.0 description: MP-test for H1.5

Date:12/20/2000 Rev#: 3.0 description: C1-test for H1.6
Date:02/02/2001 Rev#: 4.0 description: C2-test for H1.6
Date:03/05/2001 Rev#: 4A description: C3-test for H1.6

E

HP Model Name : Hurricane 1.6

1 1

Gerserville

SPR CONN.

page 33

CRT CONN.

2 2

page 24

VGA Board
CONN.

page 23

Tech.

page 6

14M_3V

AGP Bus

Dot-Matrix, Button
Board, FDD,
Touch-PAD
CONN.

page 32

Coppermine (uPGA2) CPU

page 3,4,5

HD#(0..63)HA#(3..31)

440ZXM

page 7,8,9

MD(0..63)

AD(0..31)

144Pin S.O.Dimm
Socket

page 11,12

MA(0..13)

HCLK_CPU

Y1

14.318MHZ

PCLK_MTXC
HCLK_CPU

DCLKWR

CLK_SDRAM(0..3)

+3V

PCI BUS

DCLKO

Clock
Generator
Buffer

page 10

PCLK_PIIX4

+3V
+3VS

14M_3V
14M_5V

PCLK_DOCK

PCLK_PCM

Audio CD-DJ

Mini PCI

3 3

Socket

page 31

CardBus
TI1420 Solt1/2

page 15,16 page 17

ESS
ES1988

IDE (HDD/CR-ROM)

EQ &
Speaker AMP.

page 18,19

Super IO
37N869

page 27 page 25,26

RESET CKT

page 32

14M_5V

KeyBoard
87570

ISA BUS

OZ163

page 20

USB Port 0
and Port 1

page 28

DC-DC
Interface & RTC

page 30

PIIX4M

page 13,14page 21,22

+3V / +3VS
(5VS Tolerant)

SA(0..15)

SD(0..15)

CLK_48MHZ

14M_3V

PCLK_SIO

Screw Hole

page 39

page 28 page 28

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FIR

page 28

A

SIOPIO

FDD

page 26

B

Touch Pad
CONN.

page 34

BIOS

page 29 page 29

SMBus

page 25

KBD

page 29

PS/2

SUS_ON

Power CKT DC/DC MAX1632
MAX1711

page 34,36,37,38

SM Bus

C

Battery Charge

page 35

D

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

247Tuesday, August 21, 2001

E

of

4C

TESTLO1
TESTHI
RTTIMPEDP

+VCPU_IO

CPU_LO/HI#6

HD[0..63]9
HREQ#[0..4]7

HA[3..31]7

HADS#7

RS#[0..2]7

HTRDY#7

GT_INTR6
GT_NMI6

GT_STPCLK#6

GT_CPUINIT#6

HCLK

HD[0..63]

HREQ#[0..4]

HA[3..31]

HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
HA16
HA17
HA18
HA19
HA20
HA21
HA22
HA23
HA24
HA25
HA26
HA27
HA28
HA29
HA30
HA31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

RS#0

SLP#

RS#1
RS#2

HTRDY#

HCLK

FLUSH#
CPURST#

COPPERMINE SOCKET

DEFER#7
HIT#7
HITM#7

RS#[0..2]

HCLK7,10

CPURST#7

12

R64
1K

R282
33

1 2

C360
15PF

1 2

1 2

L7 LQG21N4R7K10

U7A

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RP#

ADS#
RS0#

RS1#
RS2#
RSP#
TRDY#

BPM1#
BPM0#
BP3#
BP2#

LINT0/INTR
LINT1/NMI

STPCLK#
SLP#

BCLK
INIT#

FLUSH#
RESET#

PICCLK
PICD0
PICD1

10UF_10V_1206

AA12

AB15

BSEL0

BSEL1

Address Lines

Request Phase Request

Response Phase Signals

Debug Break Point

APIC

LO/HI#
EDGCTRLP
BSEL1 BSEL1
BSEL0

L3
K3
J2
L4
L1
K5
K1
J1
J3

K4
G1
H1

E4

F1

F4

F2

E1
C4
D3
D1

E2
D5
D4
C3
C1

B3

A3

B2
C2

A4

A5

B4
C5

T2

V4

V2
W3
W5
W2

AB2

U1

AA2

W1

Y1
U2

W19
W21
Y21

AA21

AB18
AC19

AC11
AB12

M3

AA10

AC9

A6

AA18
AB21

Y20

12

C107

AA16

EDGECTRLP

Geyserville

R2L2M2

PLL1

GHI#

Analog

12

+

C552
.01UF

AB19

PLL2

RSVD

Coppermine

H-PBGA

495 Ball

Execution Control Signals

Snoop Phase Signals

Error Signals

DEFER#

HIT#

HITM#

AERR#

AP0#

AP1#

BERR#

BINIT#

U3V1Y4

AA1

AB1Y2E6

V21

IERR#

TESTLO2

Add
CAP. by
Charles
at 6/22

AD19

AD17Y5N5

AD20H4AA17

TESTHI

TESTP1

TESTP2

TESTLO1

TESTLO2

RTTIMPEDP

CMOS Test Inputs

Arbitration Phase Signals

PC Compatibility Signals

Debug & Test Signals

IERR#

PRDY#

PREQ#

TRST#

TMS

TDI

TDO

TCK

AD9

W20

AB20

AA14

AD14

AD13

AC15

AA11

V20

AA3

T1

G4

DBSY#

DRDY#

TESTP3

TESTP4

Data Phase Signals

Data Phase Signals

Thermal Diode

SMI#

PWRGOOD

IGNNE#

FERR#

A20M#

AB10V5AC13

AC12

AD10

FERR_CPU#

TCK
TDO
TDI

TMS
TRST#
PREQ#

+VCPU_IO

12

C281
.1UF

C279
2200PF

1 2

R256

1 2

1K

Change
value. by
Charles at
6/22

+VCPU_IO

Q10

2SC2412K

2

R104

1 2

1K

+VCPU_IO

+3V

+3VS

R109
10K

1 2

+VCPU_IO

R276

1 2

1.5K
R250

1 2

0

R89

1 2

56.2_1%

1 2

U25

1

NC

2

VCC

3

DXP

4

DXN

5

NC

6

ADD1

7

GND

8 9

GND NC

NE1617DS

RP25

81
72
63
54

8P4R-1.5K

BSEL0

CPURST#

R248

10K

SMBCLK

SMBDATA

ALERT

Change
value. by
Charles at
6/22

PREQ#
IERR#
FLUSH#
SLP#

FERR# 13

DBSY# 7
DRDY# 7

T21

U21

R21

V18

P21

P20

U19

DEP0#

DEP1#

DEP2#

DEP3#

DEP4#

DEP5#

DEP6#

DEP7#

HD0

D10

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#

D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

BNR#

BPRI#

BREQ0#

LOCK#

THERMDA

THERMDC

AA15

AB16

THERMDC
THERMDA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

HD1

D11

HD2

C7

HD3

C8

HD4

B9

HD5

A9

HD6

C10

HD7

B11

HD8

C12

HD9

B13

HD10

A14

HD11

B12

HD12

E12

HD13

B16

HD14

A13

HD15

D13

HD16

D15

HD17

D12

HD18

B14

HD19

E14

HD20

C13

HD21

A19

HD22

B17

HD23

A18

HD24

C17

HD25

D17

HD26

C18

HD27

B19

HD28

D18

HD29

B20

HD30

A20

HD31

B21

HD32

D19

HD33

C21

HD34

E18

HD35

C20

HD36

F19

HD37

D20

HD38

D21

HD39

H18

HD40

F18

HD41

J18

HD42

F21

HD43

E20

HD44

H19

HD45

E21

HD46

J20

HD47

H21

HD48

L18

HD49

G20

HD50

P18

HD51

G21

HD52

K18

HD53

K21

HD54

M18

HD55

L21

HD56

R19

HD57

K19

HD58

T20

HD59

J21

HD60

L20

HD61

M19

HD62

U18

HD63

R18
T4

U4
C6
R1

GT_A20M# 6
GT_IGNNE# 6

PWRGD_CPU 6
GT_SMI# 6

BNR# 7
BPRI# 7
BREQ0# 7
HLOCK# 7

+VCPU_IO

R85

1.5K

1 2

THERMDA

THERMDC

+3V

3 1

R75

56.2_1%

R249

110_1%

R77

1.5K
R92

1K
R95

1K

Signal name

TCK
TMS
TRST#
TDO

RTTIMPEDP

EDGCTRLP

TESTHI

TESTLO1

TESTLO2

SMC 5,20,25,26,32,33,38
SMD 5,20,25,26,32,33,38

ATF# 26

+VCPU_IO

R275

1 2

@150
R80

1 2

@150
R277

1 2

@1K
R82

1 2

@1K
R273

1 2

1K
RP2

5 4
6 3
7 2
8 1

8P4R-1K

Default Mode
1K PULL-DOWN
1K PULL-DOWN
1K PULL-DOWN
1K PULL-DOWN

X

TDI

TDO

TCK

TMS

TRST#

Software Debug Mode
150 PULL-UP TO +CPU_IOTDI
1K PULL-UP TO +CPU_IO
1K PULL-UP TO +CPU_IO

150 PULL-UP TO +CPU_IO

1 2

1 2

+VCPU_IO

1 2

1 2

1 2

16

NC

15

STBY

14
13

NC

12
11
10

ADD0

12

12

R255

R262

1K

10K

+3V

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

TCK
TDI
TMS

X

347Tuesday, August 21, 2001

4C

of

A

+VCC_CORE

4 4

12

C331
.01UF

12

C318
.01UF

12

C93

3 3

.1UF

+VCC_CORE

12

C329

+

150UF_TPB_6.3V

+VCC_CORE

12

2 2

C98

+

220UF_TPB_4V

12

10UF_10V_1206

+VCC_CORE

12

1 1

C300

10UF_10V_1206

C309

12

12

12

C100

.1UF

C325

.1UF

C312
1000PF

12

C315

+

150UF_TPB_6.3V

12

C366

+

10UF_10V_1206

12

C316
.1UF

12

C302

.1UF

12

C339
.1UF

12

C354
10UF_10V_1206

12

C298

10UF_10V_1206

A

12

C310
.01UF

12

C303
.1UF

12

C108
.1UF

12

C357

+

150UF_TPB_6.3V

12

C103

+

10UF_10V_1206

12

C364

10UF_10V_1206

12

12

C311

1UF

12

C304

1UF

12

C305

1UF

+VCC_CORE

C361
10UF_10V_1206

12

12

12

12

C329, C315, C357,
C94, C98, C109
Change from TPC to
TPB for cost down

12

+

220UF_TPB_4V

12

10UF_10V_1206

C326

C317

.1UF

1000PF

+VCC_CORE

12

C333

C327

1000PF

1UF

+VCC_CORE

12

C319

C313

.1UF

1000PF

C109

C349

12

C94

+

220UF_TPB_4V

12

C350

10UF_10V_1206

Change value by
Charles at 12/20

12

C332
.1UF

12

C85

.1UF

12

C328
.1UF

12

C92

.1UF

12

C343
1000PF

12

C334
1000PF

12

C299

10UF_10V_1206

B

12

C84

1UF

12

C65

.01UF

12

C341

1UF

12

C292
10UF_10V_1206

B

+VCC_CORE

M10
M12
M14
M16

COPPERMINE SOCKET

U7B

H8

VCC

H10

VCC

H12

VCC

H14

VCC

H16

VCC

J7

VCC

J9

VCC

J11

VCC

J13

VCC

J15

VCC

K8

VCC

K10

VCC

K12

VCC

K14

VCC

K16

VCC

L7

VCC

L9

VCC

L11

VCC

L13

VCC

L15

VCC

M8

VCC
VCC
VCC
VCC
VCC

N7

VCC

N9

VCC

N11

VCC

N13

VCC

N15

VCC

P8

VCC

P10

VCC

P12

VCC

P14

VCC

P16

VCC

R7

VCC

R9

VCC

R11

VCC

R13

VCC

R15

VCC

T8

VCC

T10

VCC

T12

VCC

T14

VCC

T16

VCC

U7

VCC

U9

VCC

U11

VCC

U13

VCC

U15

VCC

VCCT

VCCT

M6

M17N6N17P1P6

+VCC_CORE

Change by
Charles at 9/2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

VCMOSREF

VCLKREFVGTLREF

E5

E16

VREF

E17F5F17

VREF

VREF

VREF

U5

VREF

Y17

VREF

Y18

VREF

VREF

P2

CLKREF

AA9

AD18

CMOSREF

CMOSREF

A15

A16

A17

C14D8D14

NC1

NC2

NC3

NC4

Coppermine

H-PBGA

495 Ball

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

VCCT

P17R6R17T6T17U6U17V6V7V8V9

V10

V11

V12

V13

C

NC5

VCCT

V14

V15

D16

NC6

VCCT

V16

NC7

VCCT

E15G2G5

G18H3H5

NC8

NC9

NC10

NC11

VCCT

VCCT

VCCT

VCCT

V17W6W7W8W9

NC12

VCCT

W10

NC13

VCCT

W11

VCCT

W12

VCCT

W13

VCCT

NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24

VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT

J5
M4
M5
P3
P4
AA5
AA19
AC3
AC17
AC20
AD15

AD8
AD7
AD6
AC8
AC7
AC6
AB8
AB7
AB6
AA8
AA7
AA6
Y8
Y7
Y6
W17
W16
W15
W14
G17
G16
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
H6
H17
K6
K17
L6
L17
J6
J17

+VCPU_IO

12

R81
1K_1%

12

R79
2K_1%

D

D

VGTLREF

+VCPU_IO

+VCPU_IO

12

C338
1000PF

+VCPU_IO

12

C62
1UF

E

VGTLREF

12

12

C56

.1UF

C69

.1UF

+VCPU_IO

12

12

+VCLK

12

12

12

C75

1000PF

R279
1K_1%

R278
2K_1%

R96
2K_1%

R93
2K_1%

12

C57

.01UF

12

C73

.1UF

VCLKREF

12

12

C291

C70

1UF

.01UF

Change value by
Charles at 6/24

VCMOSREFVCMOSREF

12

C79
.1UF

VCLKREF

12

C104
.1UF

Change value by Charles at 6/24

12

12

12

C344
.01UF

12

C288

1000PF

12

C287
.01UF

C91
.1UF

12

C67

1000PF

C68

.01UF

12

12

C282

C66
1UF

.1UF

+

C89
220U_TPB_4V

Change value by Charles at 6/24

12

12

C61

1000PF

12

C60
.01UF

12

C59
1UF

12

C63

1000PF

12

C64

.01UF

12

C553
1UF

12

C554
.1UF

12

C555

.1UF

C284

+

150UF_TPC_4V

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

E

12

12

C58

1000PF

C324
1000PF

447Tuesday, August 21, 2001

4C

of

A

B

C

D

E

U7C

AD21

VSS

AD16

VSS

AD5

VSS

AD4

VSS

AD3

VSS

AD2

VSS

AD1

VSS

AC21

VSS

AC18

VSS

AC16

VSS

AC14

VSS

AC10

VSS

AC5

VSS

AC4

VSS

AC2

VSS

AC1

VSS

AB17

VSS

AB14

VSS

AB13

VSS

AB11

VSS

AB9

VSS

AB5

VSS

AB4

VSS

AB3

VSS

AA20

VSS

AA13

VSS

AA4

VSS

Y19

VSS

Y16

VSS

Y15

VSS

Y14

VSS

Y13

VSS

Y12

VSS

Y11

VSS

Y10

VSS

Y9

VSS

Y3

VSS

W18

VSS

W4

VSS

COPPERMINE SOCKET

A2A7A8

VSS

VSS

VSS

VSS

VSS

U20V3V19

A12

A21B1B5B6B7B8B10

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

B15

B18C9C11

C15

C16

VSS

VSS

VSS

VSS

VSS

VSS

Coppermine

H-PBGA

495 Ball

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

R20T3T5T7T9

T11

T13

T15

T18

T19U8U10

U12

U14

U16

C19D2D6D7D9E3E7E8E9

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

R10

R12

R14

R16

VSS

VSS

P19R3R4R5R8

E10

E11

VSS

VSS

VSS

VSS

P13

P15

E13

E19F3F6F7F8F9F10

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

F11

F12

F13

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

N8

N10

N12

N14

N16

N18

N19

N20P5P7P9P11

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F14
F15
F16
F20
G3
G19
H2
H7
H9
H11
H13
H15
H20
J4
J8
J10
J12
J14
J16
J19
K2
K7
K9
K11
K13
K15
K20
L5
L8
L10
L12
L14
L16
L19
M7
M9
M11
M13
M15
M20
N2
N3
N4

R68
LN_0

1 2

1 2

R58

LN_0

VID[0..4]

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3

CPU_VID4

4 4

3 3

R67

@0

VID0
VID1
VID2
VID3

VID4

1 2

1 2

R57

@0

RP1

1 8
2 7
3 6
4 5

L@8P4R-0

1 2

R69

L@0

SMC3,20,25,26,32,33,38

SCKP412,13

SMD3,20,25,26,32,33,38

+3V

2 2

SDAP412,13

RP65

1 8
2 7
3 6
4 5

L@8P4R-4.7K

1 2

R461 L@4.7K

Add by
Charles at
3/27 to
reserved for
LA733L

VID[0..4] 36

2
3

4
5
6
7
8

9

10

U27

SDA
Override#

I-0
I-1
I-2
I-3
I-4

Level
GND

LN_FM3560

Non_Mux_Out

VCC3SCL
ASEL

Mux_Sel

VR_HI/LO#6

201
19

18

WP

17
16

15

Y-0

14

Y-1

13

Y-2

12

Y-3

11

Y-4

ADDRESS: ASEL = LOW => 6E/6F

+3V

R59 LN_0

1 2

VID0
VID1
VID2
VID3
VID4

CPU_VID2
CPU_VID1
CPU_VID0

CPU_VID3

CPU_VID4

12

C286

LN_.1UF

12

R265
LN_0

13

D

Q5

2

G

LN_SI2302DS

S

VID4 VID3 VID2 VID1 VID0 +VCC_CORE

1 1

1.3V01110

1.35V01101

1.5V01010

1.55V10010

1.6V10000

1.65V00111

010 1 1.70V0

110 0 1.75V0

010 0 1.80V0

100 1 1.85V0

Compal Electronics, inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

547Tuesday, August 21, 2001

E

of

4C

A

B

C

D

E

PIIX4_SLP#13,14

U10
LN_AMI11686-001

20

NMI

16

INTR

22

INIT#

24

A20M#

21

IGNNE#

17

SMI#

23

STPCLK#

19

SUSSTAT1#

13

CPU_STP#

14

G_LO/HI#

15

VR_ON

29

VGATE

43

IGN_VGATE#

28

VR100/50#

44

PLL30/60#

41

CRESET#

26

CLK_IN

25

CLK_OUT

45

CLKEN#L

38

STB#

37

DIN

36

DOUT

GND

GND

618314227

A20M#

IGNNE#

CPU_STP#
INTR
SMI#
CPUINIT#

NMI
SUSTAT1#

V_GATE G_VR_POK
STPCLK# GT_STPCLK#

GND

GND

GND

G_NMI
G_INTR
G_INIT#

G_A20M#

G_IGNNE#

G_SMI#

G_STPCLK#

G_SUSSTAT1#

G_CPU_STP#

RESERVED

CPUPWRGD

VRPWRGD

VRCHGNG#

VR_HI/LO#

LP_TRANS#

RESERVED
RESERVED
RESERVED

VCC3

VCC3

30

7

12

C367
LN_.01UF

R295
0

R293

0

RP27

L@16P8R-0

1 2

R448 L@0

1 2

R122 L@0

for without Geyserville

+3V

GT_SUSTAT1#

U13

1
2
3 4

@7SH08

1 2

R175 0

5

GHI#

1 2

1
4
8
48
2
5

3
11
47

46
10
9

32
12

33
34

35
39
40

+3V

12

C385

LN_.1UF

GT_A20M#

12

GT_IGNNE#

12

89
710
611
512
413
314
215
116

C161 @.1UF

GT_NMI
GT_INTR
GT_CPUINIT#
R111

1 2

@0

GT_SMI#

GT_STPCLK#
GT_SUSTAT1#

R115

1 2

LN_0

PWRGD_CPU
G_VR_POK

VRCHGNG#
VR_HI/LO#

R123

1 2

LN_10K

GT_CPU_STP#
GT_INTR
GT_SMI#
GT_CPUINIT#

GT_NMI
GT_SUSTAT1#

VGA_SUS_STAT# 23

R106

1 2

@0

GT_CPU_STP#

PWRGD_CPU 3
G_VR_POK 29

VRCHGNG# 13
VR_HI/LO# 5

2

G

GT_A20M#
GT_IGNNE#

CPU_LO/HI#

13

D

Q12

S

LN_SI2302DS

GT_NMI 3
GT_INTR 3
GT_CPUINIT# 3
GT_A20M# 3
GT_IGNNE# 3
GT_SMI# 3

GT_STPCLK# 3
GT_SUSTAT1# 8
GT_CPU_STP# 10

CPU_LO/HI# 3

Add by Charles
at 1/18

Change by
Charles at
2/10

Change by
Charles at
2/16

Change by
Charles at
2/10

+VCPU_IO

Change by Charles at 2/16

CPU_STP#
VRCHGNG#

without Geyserville,
GHI#(CPU_LO/HI#) can
OPEN

RP24

1 8
2 7
3 6
4 5

8P4R-1.5K

1 2

R100 L@1.5K

1 2

R87 1K

1 2

R86 680

1 2

R88 330

+3V

+3VS

+VCLK

+3VS

+3V

+3VS

+3V
+3VS
+3V

1 2

R296 LN_10K

1 2

R304 LN_10K

1 2

R289 1.5K

1 2

R300 4.7K

1 2

R99 10K

1 2

R301 LN_4.7K

1 2

R103 10K

1 2

R119 1K

1 2

R113 10K

1 2

R291 LN_10K

RP18

18
27
36
45

LN_8P4R-4.7K

D19

1
2

@RB717F

GT_NMI
GT_INTR
GT_IGNNE#
GT_A20M#

CPU_LO/HI#
GT_CPUINIT#
GT_STPCLK#
GT_SMI#

VR_HI/LO#

G_VR_POK

PWRGD_CPU

GT_CPU_STP#

GT_SUSTAT1#

CPUINIT#
NMI
INTR
SMI#

STPCLK#
VRCHGNG#

CRESET#
GT_LO/HI#
SUSTAT1#

GT_CPU_STP#

3

D20

L@RB751V

12

VR_POK

VR_POK 37

R117

12
LN_1K
R121

12
LN_1K

PIIX4_NMI13
PIIX4_INTR13
PIIX4_INIT#13
PIIX4_A20M#13

1 1

PIIX4_IGNNE#13
PIIX4_SMI#13

PIIX4_STPCLK#13
SUS_STAT#13
CPU_STP#13

GT_LO/HI#13
VR_ON26,36,37

V_GATE36,37

CRESET#7

14.3M_GCL10

Add by Charles at 2/16

2 2

3 3

4 4

NMI
INTR
CPUINIT#
A20M#

R294

1 2

IGNNE#

@0

1 2

SMI#

R292

@0
STPCLK#
SUSTAT1#
CPU_STP#
GT_CPU_STP#
GT_LO/HI#

V_GATE

Add by Charles at 3/21 for
ATE testing

CRESET#

R298

1 2

12

@0

@14.318MHZ

1 2

LN_14.318MHZ

12

C379
LN_15PF

Y5

Y6

1 2

R447
LN_1K

12

LN_15PF

R108
@0

12

C378

Add by
Charles at
1/18

Add by
Charles at
3/22

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL
ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.
THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION
OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER
THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

A

B

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

647Tuesday, August 21, 2001

E

of

4C

A

B

C

D

E

443ZXM-100_ A

+3V

12

12

12

12

12

C137

C134

C130

1 1

1000PF

12

1000PF

2 2

3 3

C154

.01UF

+3V

12

C157
.01UF

C131

.01UF

.1UF

12

12

C158

C159

.01UF

.1UF

PLACE THE
TERMINATOR ON THE

12

C132
.1UF

12

12

C156
.1UF

HCLK3,10

STUB TO CPU

C135
1000PF

C155
1000PF

12

+

C146

10UF_10V_1206

12

+

C120

10UF_10V_1206

HCLK

R150

C148
15PF

RS#[0..2]3

HREQ#[0..4]3

12

33

12

HA[3..31]

CPURST#3

HADS#3
BNR#3
BPRI#3

DBSY#3

DEFER#3

DRDY#3

HIT#3

HITM#3
HLOCK#3
HTRDY#3
BREQ0#3

R329 = @10K (no load) 2/16

R329 @10K

1 2

+3V

CRESET#6

PCIRST#13,16,31

Add by Charles
at 5/20

MMA[0..13] 12
HA[3..31] 3

HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
HA16
HA17
HA18
HA19
HA20
HA21
HA22
HA23
HA24
HA25
HA26
HA27
HA28
HA29
HA30
HA31

RS#0
RS#1
RS#2

HREQ#1
HREQ#2
HREQ#3
HREQ#4

TESTIN#

CRESET#

G25
G23
G24
G26

G22

M25
M26

AE22
AE23

H22
H23
F26

F22
F23
F24
F25
E23
E26
E25
D25
D26
B25
C26
A25
C25
A24
D24
C23
B24
C24
A23
E22
D23

B23
K21
H24
H26

K23

K22
H25
B26

K26

K24
K25

N23

P22

+3V

V21

Y21F7F9

F18

F20G6G21J6J21

AA7

AA9

AA18

AA20

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

CPURST#
ADS#
BNR#
BPRI#

L23

DBSY#

J26

DEFER#
DRDY#

L24

HIT#

L22

HITM#
HLOCK#
HTRDY#
BREQ0#

RS#0

L26

RS#1

L25

RS#2

J22

HREQ#0

J23

HREQ#1
HREQ#2
HREQ#3

J25

HREQ#4

HCLKIN
TESTIN#

CRESET#

A3

PCIRST#

CRESVA
CRESVB
CRESVC

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

82443ZXM-100

492 BGA

HOST INTERFACE

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A1

A14

A26C5C9

C18

C22E3E12

E15

E24F6F8

F19

F21H6H21J3J24

VDD

VDD

CKE2/CSA#6
CKE3/CSA#7

CKE4/CSB#6
CKE5/CSB#7

DRAM INTERFACE

CKE0/FENA

CKE1/GCKE

VSS

VSS

VSS

VSS

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8

MAA9
MAA10
MAA11
MAA12
MAA13

MAB#0
MAB#1
MAB#2
MAB#3
MAB#4
MAB#5
MAB#6
MAB#7
MAB#8
MAB#9
MAB10

MAB#11
MAB#12
MAB#13

CSA#0
CSA#1
CSA#2
CSA#3
CSA#4
CSA#5

CSB#0
CSB#1
CSB#2
CSB#3
CSB#4
CSB#5

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

DQMB1
DQMB5

SRAS_A#
SRAS_B#
SCAS_A#
SCAS_B#

WE_A#
WE_B#

DCLKO

DCLKWR

DCLKRD

U31A
443ZXM-A

AF17
AB16
AE17
AC17
AF18
AE19
AF19
AC18
AC19
AE20
AD20
AF21
AC21
AF25

AD16
AC16
AD17
AB17
AE18
AD19
AB18
AB19
AF20
AC20
AB20
AE21
AD21
AF22

AB14
AF15
AE15
AC15
AD15
AE16
AE24
AD23

AE25
AD24
AD26
AC24
AC26
AB23
AC23
AF24

AD13
AC13
AC25
AB26
AE14
AC14
AA22
AA24

AE13
AD14

AC22
AF23

AF16
AA17
AF12
AB13

AE12
AC12

AB21
AD25
AB22

MMA0
MMA1
MMA2
MMA3
MMA4
MMA5
MMA6
MMA7
MMA8
MMA9
MMA10
MMA11
MMA12
MMA13

RAS0#_BX
RAS1#_BX
RAS2#_BX
RAS3#_BX

CKE4_BX
CKE5_BX

RCAS#0
RCAS#1
RCAS#2HREQ#0
RCAS#3
RCAS#4
RCAS#5
RCAS#6
RCAS#7

CKE2_BX
CKE3_BX

W=5mils

DCLKO_R

W=5mils

R170

33

place closely to 443zx

1 2
12

C162
15PF

R193 47

1 2

R178 47

1 2

R194 47

1 2

R195 47

1 2
R186 33

1 2
1 2

R185 33

R197

1 2

R196 33

1 2

SRASA# 12
SCASA# 12

RMWEA# 12

1 2

DCLKRW 10

RCAS#[0..7] 11

33

W=5mils

Add by Charles
at 5/20

CKE[2..5]

CKE2 11
CKE3 11

12

C163
22PF

CKE[2..5]11

PLACE THE RESISTOR ON THE 443ZX

R168

18

RRAS#2 11
RRAS#3 11
RRAS#4 11
RRAS#5 11

CKE4 11
CKE5 11

DCLKO 10

4 4

AB22 leave to be NC. 2/16

Compal Electronics, inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

747Tuesday, August 21, 2001

E

of

4C

A

443ZXM-100_ B

PX4_REQ1#13

GNT#417

+3VS

+3V

+5V

+3VS

10
9
8
7
6

+3VS

1 2

R128 10K

2 1

1 2

R143 1K

REQ#0
REQ#1
REQ#2
REQ#3

1 2

R129

D7

RB751V

FRAME#13,14,31

DEVSEL#13,14,31

PHLD#13,14
PHLDA#13,14

10K

8

IRDY#13,14,31
TRDY#13,14,31

STOP#13,14,31

PAR13,14,31
SERR#13,14,31
PLOCK#14

U30C
74LVC08

+3VS POWER

12

REQ#0

31

R314 0

1 2

R322 0

1 2

R313 0

1 2

R130 0

1 2

TO DOCKING

REQ#131
REQ#213
REQ#315

GT_SUSTAT1#6

TO DOCKING

GNT#0

31

GNT#131
GNT#315
RSMRST#13,29

CLKRUN#13,14,23,27,31
PCLK_BX10

place closely to 443zx

C128

1UF

REQ#1

9

REQ#3

10

1 1

2 2

3 3

4 4

GNT#0
GNT#1
GNT#2
GNT#3

+3VS

RP4

1
2
3
4
5

10P8R_10K

B

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE#0
C/BE#1
C/BE#2
C/BE#3

FRAME#_BX
DEVSEL#_BX
IRDY#_BX
TRDY#_BX

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4

REFVCC5

W=5mils

12

12

R308
10

C393
15PF

AE3

AD4

AC4

F10
D10

E10

AF3

K6
K2
K4
K3
K5
J1

J2
H2
H1

J5
H3
H5
H4
G1
G2
G4
D1
D3
D2
C1

A2
C3

B3
D4

E5

A4
D5

B4

B5

A5

E6
C6

J4
G3

E4
C4

E2

F3

E1

F5

F4
G5

F1

F2

B6
D6

A6
C7

D8

E7
D7

E8

E9

C2

B2

+3V

L11

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13

PCI INTERFACE

AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE#0
C/BE#1
C/BE#2
C/BE#3

FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PLOCK#

PHOLD#
PHLDA#
WSC#

PREQ0#/IOREQ#
PREQ1#
PREQ2#
PERQ3#
PERQ4#
SUSTAT#

PGNT0#/IOGNT#
PGNT1#
PGNT2#
PGNT3#
PGNT4#
BXPWROK
CLKRUN#
REFVCC5
PCLKIN

VSS

VSS

VSS

VSS

VSS

M13

L15

M11

L12M5N1

L14

L16

M12

M15

N11

N16

P11

P16

R12

R15

T11

VDD

L13

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

T13

T14

T16

VDD

VDD

VDD

82443ZXM-100

492 BGA

PCI ARB & PWR MGT

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

M16

M22

N12

N13

N14

N15

P12

M14

P13

VSS

P14

P15

P26

T12

T15R5R11

C

N26P1AE1V6Y6

VDD

VDD_AGP

VDD_AGP

VDD_AGP

VSS

VSS

VSS

VSS

VSS

VSS

R13

R14

R16

R22

V3

+3V

U31B
443ZXM-A

GAD0

AB5

GAD0
GAD1
GAD2
GAD3

VDD_AGP

GAD4
GAD5
GAD6
GAD7
GAD8

GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GC/BE#0
GC/BE#1
GC/BE#2
GC/BE#3

GFRAME#

GDEVSEL#

GIRDY#
GTRDY#
GSTOP#

GPAR

GREQ#
GGNT#

AGP INTERFACE

GCLKOUT

GCLKIN

PIPE#

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

RBF#

ST0
ST1
ST2

GADSTB-A
GADSTB-B

SB-STB

AGPREFV

VSS

VSS

VSS

V24

W6

W21

AE2
AD3
AD2
AD1
AC3
AC1
AB4
AB1
AA5
AA3
AA4
AA2
AA1
Y5
Y3
W1
V2
W2
U5
V1
U4
U3
U1
T3
T4
T2
T1
U6
R3
R4
R2

AB2
Y4
V4
U2

W3
W5
V5
W4
Y1
Y2

L5
L3

P5
N5

M3
K1
M2
M1
N2
P2
P4
P3
R1

M4
L4

L2
L1

AC2
T5
N3

N4

GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GREQ#
GGNT#

GCLKOUT

PIPE#
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

AGPREFV

12

12

C536
1000PF

** Place as close to
443BX as possible.

GC/BE#0 23
GC/BE#1 23
GC/BE#2 23
GC/BE#3 23

GFRAME# 23
GDEVSEL# 23
GIRDY# 23

GTRDY# 23

GSTOP# 23
GPAR 23

GREQ# 23
GGNT# 23

W=5mils

PIPE# 23

RBF# 23
ST0 23

ST1 23
ST2 23

AD_STBA 23
AD_STBB 23
SBSTB 23

W=20mils

C145
.01UF

SBA[0..7]

12

C537
1UF

W=10mils

1 2

R162

18

+3V

12

12

D

** Place as close to
443BX as possible.

12

C141

1000PF

12

C166

1000PF

12

C149

1000PF

R166 18

1 2

SBA[0..7] 23

C535

1 2

1UF

R152

3.48K_1%

R154

2.32K_1%

12

C138

.01UF

12

C167

.01UF

12

C143

.01UF

W=5mils

12

C160
22PF

Add by
Charles at
5/20

Change
value by
Charles
at 2/16

+3V

+3V

+3V

12

12

12

C151
.01UF

C153
.01UF

C152
.01UF

GCLKO 23

12

C150
.1UF

12

C403
.1UF

12

C139
.1UF

** Trace lengths of GCLKOUT & GCLKIN
must be matched. Stub to teebshould be 1"
MAX.

R165 8.2K

GTRDY#

1 2

R158 8.2K

GIRDY#

1 2

R161 8.2K

GDEVSEL#

1 2

R338 8.2K

GSTOP#

1 2

R340 8.2K

AD_STBA

1 2

R156 8.2K

AD_STBB

1 2

R335 8.2K

GFRAME#

1 2

R145 8.2K

GREQ#

1 2

R328 8.2K

GGNT#

1 2

R332 8.2K

SBSTB

1 2

R149 8.2K

RBF#

1 2

R331 8.2K

PIPE#

1 2

R337 100K

GPAR

1 2

E

12

12

C/BE#[0..3]

AD[0..31]

GAD[0..31]

C416
1000PF

C387
1000PF

+3V

C/BE#[0..3]13,31

AD[0..31]13,31

GAD[0..31]23

12

C384
.1UF

12

C147
.1UF

12

C412
.1UF

U30D
74LVC08

PX4_REQ2#13

A

11

+3VS POWER

REQ#0

12

REQ#4

13

REQ#4 17

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

Tuesday, August 21, 2001

8

of

E

47

4C

A

B

C

D

E

443ZXM-100_ C

MMD[0..63]12
MECC[0..7]12

1 1

2 2

3 3

MMD[0..63]
MECC[0..7]

MMD0
MMD1
MMD2
MMD3
MMD4
MMD5
MMD6
MMD7
MMD8
MMD9
MMD10
MMD11
MMD12
MMD13
MMD14
MMD15
MMD16
MMD17
MMD18
MMD19
MMD20
MMD21
MMD22
MMD23
MMD24
MMD25
MMD26
MMD27
MMD28
MMD29
MMD30
MMD31
MMD32
MMD33
MMD34
MMD35
MMD36
MMD37
MMD38
MMD39
MMD40
MMD41
MMD42
MMD43
MMD44
MMD45
MMD46
MMD47
MMD48
MMD49
MMD50
MMD51
MMD52
MMD53
MMD54
MMD55
MMD56
MMD57
MMD58
MMD59
MMD60
MMD61
MMD62
MMD63

MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7

AF4

AE4

AF5
AD6
AE6
AB7
AC7

AF7
AB8
AB9
AC9
AE9

AB10
AC10
AF10
AD11

Y24

Y25

W23
W24
W26
W25

V26

U24

U23

T22

T23

T26

R24

R25

P23

N25
AC5
AE5
AB6
AC6

AF6
AD7
AE7
AC8
AD8

AF8
AE8

AF9

AD10
AE10
AB11
AC11

Y23

Y26

W22

V22

V23

V25

U22

U25

U26

T24

T25

U21

R23

R26

P24

P25

AE11
AA10
AA23
AA26
AF11
AD12
AA25

Y22

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63

MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7

+3V

B1

N22

AF14

AF2

AE26

VDD

VDD

VDD

VDD

VDD

82443ZXM-100

492 BGA

MEMORY DATA BUS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AB25

N24

AA6

AA8

AA19

AA21

AB3

AB12

AB15

AB24

AD5

AD9

AD18

AD22

AF1

HOST DATA BUS

VSS

VSS

AF13

AF26

C532

4.7UF_10V_0805

B22

HD#0

D22

HD#1

E21

HD#2

A22

HD#3

D21

HD#4

C21

HD#5

A21

HD#6

C20

HD#7

B21

HD#8

E20

HD#9

A20

HD#10

E19

HD#11

B20

HD#12

E18

HD#13

D20

HD#14

D19

HD#15

D18

HD#16

C19

HD#17

B19

HD#18

A18

HD#19

A19

HD#20

B18

HD#21

C17

HD#22

E17

HD#23

D17

HD#24

B17

HD#25

C16

HD#26

A17

HD#27

C15

HD#28

B16

HD#29

D16

HD#30

A16

HD#31

B15

HD#32

A15

HD#33

D14

HD#34

D15

HD#35

B13

HD#36

C14

HD#37

E14

HD#38

D13

HD#39

A13

HD#40

D12

HD#41

B12

HD#42

B14

HD#43

C13

HD#44

E13

HD#45

D11

HD#46

A12

HD#47

B11

HD#48

A11

HD#49

B7

HD#50

C12

HD#51

C8

HD#52

B10

HD#53

A10

HD#54

A9

HD#55

A7

HD#56

E11

HD#57

D9

HD#58

C11

HD#59

C10

HD#60

B8

HD#61

A8

HD#62

B9

HD#63

M23

GTLREFA

E16

GTLREFB

M24

VTTA

F17

VTTB

12

12

C541
.01UF

Add by Charles at 5/3

U31C
443ZXM-A

HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63

+VCPU_IO

12

C533

4.7UF_10V_0805

W=40mils

12

12

Add by Charles at 5/3

** Place as close to
443BX as possible.

C539
.01UF

C540
.01UF

12

C171

1000PF

HD[0..63]

12

VGTLREF_BX

C122
1UF

+3V

12

12

C133

C170

.01UF

.01UF

CAP. closeed to 443BX.

HD[0..63] 3

+VCPU_IO

12

R476
1K_1%

C142
1UF

12

R477
2K_1%

12

12

12

C144

C123

.1UF

.1UF

12

C538
1UF

Add by Charles at 5/3

4 4

Compal Electronics, inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

947Tuesday, August 21, 2001

E

of

4C

A

CLOCK GENERATOR & BUFFER

B

C

D

E

XOUT

XIN

+3VPCI

C372

4.7UF_10V_0805

U11

6

VDDPCI

9

VDDPCI

13

VDD

21

VDD

27

VDD

25

VDDCPU

1

XIN

2

XOUT

18

CPU_STP#

19

PCI_STP#

17

PWRDWN#

15

SEL100/66#

W48C111-17

12

C376
.01UF

CPUCLK0
CPUCLK1

PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5

PCICLKF

14.3M

48M

GND
GND
GND
GND
GND
GND

12

C381
.1UF

26

24
23

5
7
8
10
11
4

16
3

12
14
20
22
28

R105 22

1 2

R101

1 2

R110

1 2

R114@22

1 2

R118 22

1 2

R116 33

1 2

R120 15

1 2

R124

1 2

R126

1 2

R136

1 2

R112 33

1 2

R127 15

1 2

Change value by
Charles at 5/21

Reserved
by Charles
at 6/24

33
33

12

33

22
22

C121
@33PF

14MOSC 13

14.3M_SIO 27

14.3M_VGA 23

14.3M_GCL 6

HCLK 3,7

PCLK_BX 8
PCLK_MINI 31
PCLK_PCM 15
PCLK_AUD 17
PCLK_SIO 27
PCLK_PIIX4 13

48M 13

Add by Charles at 2/16

Change value by Charles for
EA at 5/26

Add by Charles at 1/4

1 1

L30

1 2

+3VS

HB1M2012-121JT

C382

4.7UF_10V_0805

L28

HB1M2012-121JT

SUSA#13,25

1 2

D5

C369

4.7UF_10V_0805

+3VS

12

R125

10K

21

RB751V

FSQ013

+3VS

+VCLK

2 2

12

C116

.01UF

PWRDWN#SUSA#

C114
.1UF

12

C370
1000PF

C113
10PF

1 2
R132 @0

1 2
R131

+3VS

VCLK_+3VS

12

C118
.01UF

CLK_CPUIO

Y1

1 2

14.318MHZ

1 2

@14.318MHZ

1 2

R107 2M

12

GT_CPU_STP#6

PCI_STP#13

FQS 0 : 66MHZ

10K

1 2

HB1M2012-121JT

12

C383
1000PF

Y2

12

C112
10PF

1 : 100MHZ

L29

3 3

+3V

4 4

L33

1 2

HB1M2012-121JT

C168

4.7UF_10V_0805

12

12

12

C417
.1UF

C415
.1UF

C421
.01UF

DCLKO7

Add by
Charles at
5/20

12

C414
.01UF

R187

33

C169
22PF

12

12

12

C420
1000PF

CLK_SMD12

CLK_SMC12

SUSA#

+3V

VCLK_SDRAM

12

C418
1000PF

D11 RB751V

R345

1 2

10K

21

SDACLK

SCKCLK

1

5
24
28
10
19
13

9

14

15

20

17
12

4

8
21
25
16

U32

VDD
VDD
VDD
VDD
VDD
VDD
VDDIIC

BUF_IN

SDATA

SCLCOK

OE

GND
GND
GND
GND
GND
GND
VSSIC

W40S11-02

CLK_SDRAM0

CLK_SDRAM1

CLK_SDRAM2

CLK_SDRAM3

CLK_SDRAM4

CLK_SDRAM5

CLK_SDRAM6

CLK_SDRAM7

CLK_SDRAM8

CLK_SDRAM9

2

3

6

7

22

23

26

27

11

18

For EA
requirment
at 6/26.

R349

1 2

10
R347

1 2

10
R346

1 2

10

R348

1 2

10

R354

1 2

22

C419

15PF_5%

CLK_SDRAM2 11

CLK_SDRAM3 11

CLK_SDRAM4 11

CLK_SDRAM5 11

DCLKRW 7

Compal Electronics, inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

Tuesday, August 21, 2001

E

of

10 47

4C

A

B

SO-DIM 144 PINS RAM MODULE CONN.

C

D

E

+3V +3V

1 1

MD0
MD1
MD2
MD3

MD4
MD5
MD6
MD7

RCAS#0
RCAS#1

MA0
MA1
MA2

MD8
MD9
MD10
MD11

MD12
MD13
MD14

2 2

CLK_SDRAM310

S_RASA#12

RM_WEA#12

R384

33

C458
22PF

3 3

DIMM0_SMD12

SMECC0
SMECC1

RRAS#3
RRAS#2

SMECC2
SMECC3

RCAS#2
RCAS#3

MD15

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MA6
MA8

MA9
MA10

MD24
MD25
MD26
MD27

MD28
MD29
MD30
MD31

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

JP28

VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CE0#
CE1#
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RESVD/DQ64
RESVD/DQ65

RFU/CLK0
VCC
RFU
WE#
RE0#
RE1#
OE#/RESVD
VSS
RESVD/DQ66
RESVD/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/RESVD
CE3#/RESVD
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC

SO-DIMM144(R)

DQ32
DQ33
DQ34
DQ35

VCC
DQ36
DQ37
DQ38
DQ39

CE4#
CE5#

VCC

DQ40
DQ41
DQ42
DQ43

VCC
DQ44
DQ45
DQ46
DQ47

RESVD/DQ68
RESVD/DQ69

RFU/CKE0

VCC

RFU

RFU/CKE1

RFU

RFU

RFU/CLK1

RESVD/DQ70
RESVD/DQ71

VCC
DQ48
DQ49
DQ50
DQ51

DQ52
DQ53
DQ54
DQ55

VCC

A11/BA0
A12/BA1

A13/A11

VCC

CE6#/RESVD
CE7#/RESVD

DQ56
DQ57
DQ58
DQ59

VCC
DQ60
DQ61
DQ62
DQ63

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
SCL

2

MD32

4

MD33

6

MD34

8

MD35

10
12

MD36

14

MD37

16

MD38

18

MD39

20
22

RCAS#4

24

RCAS#5

26
28

MA3

30

A3
A4
A5

A7

MA4

32

MA5

34
36

MD40

38

MD41

40

MD42

42

MD43

44
46

MD44

48

MD45

50

MD46

52

MD47

54
56

SMECC4

58

SMECC5

60

CKE3

62
64
66

CKE2

68

MA12

70

MA13

72
74
76

SMECC6

78

SMECC7

80
82

MD48

84

MD49

86

MD50

88

MD51

90
92

MD52

94

MD53

96

MD54

98

MD55

100
102

MA7

104

MA11

106
108

MA12

110

MA13

112
114

RCAS#6

116

RCAS#7

118
120

MD56

122

MD57

124

MD58

126

MD59

128
130

MD60

132

MD61

134

MD62

136

MD63

138
140
142
144

S_CASA# 12

CLK_SDRAM2 10

R385
33

C460
22PF

DIMM0_SMC 12

CLK_SDRAM410

S_RASA#12

RM_WEA#12

DIMM1_SMD12

R382

C444
22PF

RRAS#4
RRAS#5

33

+3V +3V

JP27

1
MD0
MD1
MD2
MD3

MD4
MD5
MD6
MD7

RCAS#0
RCAS#1

MA0
MA1
MA2

MD8
MD9
MD10
MD11

MD12
MD13
MD14
MD15

SMECC0
SMECC1

SMECC2
SMECC3

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MA6
MA8

MA9
MA10

RCAS#2
RCAS#3

MD24
MD25
MD26
MD27

MD28
MD29 MD61
MD30
MD31

3

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CE0#
CE1#
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RESVD/DQ64
RESVD/DQ65

RFU/CLK0
VCC
RFU
WE#
RE0#
RE1#
OE#/RESVD
VSS
RESVD/DQ66
RESVD/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/RESVD
CE3#/RESVD
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC

SO-DIMM144

RESVD/DQ68
RESVD/DQ69

RESVD/DQ70
RESVD/DQ71

CE6#/RESVD
CE7#/RESVD

VSS
DQ32
DQ33
DQ34
DQ35

VCC
DQ36
DQ37
DQ38
DQ39

VSS

CE4#
CE5#

VCC

VSS
DQ40
DQ41
DQ42
DQ43

VCC
DQ44
DQ45
DQ46
DQ47

VSS

RFU/CKE0

VCC

RFU

RFU/CKE1

RFU

RFU

RFU/CLK1

VSS

VCC
DQ48
DQ49
DQ50
DQ51

VSS
DQ52
DQ53
DQ54
DQ55

VCC

A11/BA0

VSS

A12/BA1

A13/A11

VCC

VSS
DQ56
DQ57
DQ58
DQ59

VCC
DQ60
DQ61
DQ62
DQ63

VSS

VCC

SCL

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

A3

32

A4

34

A5

36
38
40
42
44
46
48
50
52
54
56
58
60

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104

A7

106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

MD32
MD33
MD34
MD35

MD36
MD37
MD38
MD39

RCAS#4
RCAS#5

MA3
MA4
MA5

MD40
MD41
MD42
MD43

MD44
MD45
MD46
MD47

SMECC4
SMECC5

CKE4

CKE5
MA12
MA13

SMECC6
SMECC7

MD48
MD49
MD50
MD51

MD52
MD53
MD54
MD55

MA7
MA11

MA12
MA13

RCAS#6
RCAS#7

MD56
MD57
MD58
MD59

MD60
MD62

MD63

S_CASA# 12

CLK_SDRAM5 10

R383
33

C445
22PF

DIMM1_SMC 12

DIMM0

DIMM1

4 4

A

RCAS#[0..7]7

MD[0..63]12
MA[0..13]12

RRAS#[2..5]7

CKE[2..5]7

SMECC[0..7]12

RCAS#[0..7]
MMD[0..63]
MA[0..13]
RRAS#[2..5]
CKE[2..5]
SMECC[0..7]

Compal Electronics, inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

11 47Tuesday, August 21, 2001

E

of

4C

A

B

C

D

E

SO-DIM 144 PINS RAM MODULE CONN.

Charles add new Damping resistor for address bus and control signals at 6/21

MA0 MMA0
MA1
MA2

1 1

2 2

3 3

4 4

MA3
MA4
MA5

RP45

89

MMA1

710

MMA2

611

MMA3

512

MMA4

413

MMA5

314
215
116

16P8R-10

MD0
MD1
MD2
MD3
MD4 MMD28
MD5
MD6 MMD6
MD7

MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15

MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55

MD56 MD16
MD57
MD58
MD59
MD60
MD61
MD62
MD63

RP41

16P8R-10

RP44

16P8R-10

RP37

16P8R-10

RP34

16P8R-10

SMECC0
SMECC1
SMECC2
SMECC3
SMECC4
SMECC5

89
710
611
512
413
314
215
116

89
710
611
512
413
314
215
116

89
710
611
512
413
314
215
116

89
710
611
512
413
314
215
116

MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13

MMD0
MMD1
MMD2
MMD3
MMD4
MMD5

MMD7 MMD31

MMD8
MMD9
MMD10
MMD11
MMD12
MMD13
MMD14
MMD15 MD39

MMD48
MMD49
MMD50
MMD51
MMD52
MMD53
MMD54
MMD55

MMD56
MMD57
MMD58
MMD59
MMD60
MMD61
MMD62
MMD63

RP47

89
710
611
512
413
314
215
116

@16P8R-10

RP47 change to be no load. 2/16

RP46

16P8R-10

MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31

MD32
MD33 MMD33
MD34
MD35
MD36
MD37
MD38

MD40
MD41 MMD41
MD42 MMD42
MD43
MD44
MD45
MD46
MD47

MD17
MD18
MD19
MD20
MD21
MD22
MD23

MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6SMECC6
MECC7SMECC7

RP32

16P8R-10

RP42

16P8R-10

RP43

16P8R-10

RP40

16P8R-10

MECC0 9
MECC1 9
MECC2 9
MECC3 9
MECC4 9
MECC5 9
MECC6 9
MECC7 9

MMA6

89

MMA7

710

MMA8

611

MMA9

512

MMA10

413

MMA11

314

MMA12

215

MMA13

116

MMD24

89

MMD25

710

MMD26

611

MMD27

512
413

MMD29

314

MMD30

215
116

MMD32

89
710

MMD34

611

MMD35

512

MMD36

413

MMD37

314

MMD38

215

MMD39

116

MMD40

89
710
611

MMD43

512

MMD44

413

MMD45

314

MMD46

215

MMD47

116

MMD16

89

MMD17

710

MMD18

611

MMD19

512

MMD20

413

MMD21

314

MMD22

215

MMD23

116

R352
10

R353
10

R351
10

12

12

12

12

C212
.1UF

C441
.1UF

C210
.1UF

C453
.1UF

R182

R183

@10K

RMWEA#

SRASA#

R184

10K

10K

R181

@10K
R180

@10K
R179

10K

12

12

12

12

MMA11

C450
.01UF

C440
.01UF

C211
.01UF

C213
.01UF

MMA12

MMA10

MMA9

MMA7

MMA6

RMWEA# 7

SRASA# 7

SCASA# 7S_CASA#11

12

C448
.01UF

12

C449
.01UF

12

C452
.01UF

12

C464
.01UF

INHIB13
ENDIM113
ENDIM213

SCKP45,13
SDAP45,13

+3V

C456
1000PF

C461
1000PF

C447
1000PF

C463
1000PF

12

+3V

12

+3V

12

+3V

12

C443

4.7UF_10V_0805

C454
1UF

C446
1UF

C451
1000PF

12

12

12

C465
1000PF

C455
1000PF

C462
1000PF

C442
1000PF

12

12

12

12

12

RM_WEA#11

S_RASA#11

RM_WEA#

S_RASA#

S_CASA# SCASA#

+3V

12

C439
.1UF

12

C459
.1UF

12

C457
.1UF

12

C207
.1UF

Placement near to 440ZXM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

+3V

12

C173
.1UF

U14

16

6

INH

10

A

9

B

3

X

13

Y

1

X0

5

X1

VCC

2

X2

4

X3

12

Y0

14

Y1

15

Y2

11

Y3

GND

GND

74HC4052

7

8

Pin Name

MMA12

MMA11

MMA10

MMA9

MMA7

MMA6

SM BUS

+3V

1

1

Function

Host Freq.

In-Order

MM Config

Host

TPAD

TPAD

Select

Queue
Depth
Enable

Quick
Start

Select

AGP

Buffer

Mode

Select

1
2
3
4
5

T2

T1

Bus

SMECC[0..7]11

MMA[0..13]7

MMD[0..63]9

RP19

10P8R-10K

MA[0..13]11

MD[0..63]11

Low

66MHz

1
No
Pipe­line

Stop
Clock
Mode

Enable

Normal
Oper.

Desktop
GTL+

10
9
8
7
6

MMA[0..13]

MA[0..13]

MMD[0..63]

MD[0..63]

High

100MHz

4
Max

Quick
Start
Mode

Disable

Tri­states
certain
Memory
signal

Mobile
Low
Power
GTL+

SMECC[0..7]

+3V

DIMM0_SMC 11
DIMM1_SMC 11

CLK_SMC 10

DIMM0_SMD 11
DIMM1_SMD 11

CLK_SMD 10

Int.Res.50K

Pulldown

Pullup

Pulldown

Pulldown

Pulldown

Pulldown

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

D

Date: Sheet

12 47Tuesday, August 21, 2001

E

4C

of

CLKRUN#
DEVSEL#
FRAME#
PIIX4_IDSEL
IRDY#
PAR

PHLD#
PHLDA#
SERR#
STOP#
TRDY#

EXTSMI#25

SUSA#10,25
SUSB#25
SUSC#25

VLB#
PBTN#
LID#
SMBALT#
PIIX4_RI#

SDAP45,12
SCKP45,12

ATF_INT#25
PCI_STP#10

FERR#3

PIIX4_NMI6

RC#25

GATEA2025

R151

R155 1K

RSTDRV21,27

IOR#14,25,27

IOW#14,25,27

IOCHRDY14,25,27

RTCX1

32.768KHZ

C164
12PF

PBTN#

MID0
MID1
MID2
MID3

PIRQA#
PIRQB#
PIRQC#
PIRQD#

C/BE#0
C/BE#1
C/BE#2
C/BE#3

PIIX4_SLP#

TC27

MEMCS16#

REFRESH#
IOCS16#

AEN25,27

LID#

A

SBHE#

12

2 1

2 1

2 1

2 1

A

AD[0..31]8,31

AD17

AD16

AD10

AD8

AD14

AD13

AD9

AD15

AD19

AD18

AD12

AD11

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD9

AD8

PCI

MASTER

*
*

*
*

*

*

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA10

SA8

SA14

SA18

SA15

SA12

SA17

SA11

SA9

SA13

SA16

25,29,32

AD5

AD4

AD2

AD7

AD3

AD6

AD1

AD0

A10D9C9B9A9D8E8B8A8D7C7B7A7D6E6E4C4B4A4D3E3C3B3E2C2B2A2D1E1C1B1M1N2P3N1P2P4

B10U11

AD1

AD2

AD3

AD4

AD5

AD6

AD7

*

*

*

*

*

*

*

*

PCI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SA1

SA2

SA3

SA4

SA5

SA6

SA7

W11

Y11

T10

W10U9V9Y9T8W8U7V7Y7V6Y6T5W5U4V3W3U2T2W2Y2T1V1W16

SA2

SA7

SA3

SA4

SA6

SA5

EC_LID_SW# 26

LID_SW# 25,26,32

ON/OFF 25,29,32PBTN#14

ON/OFF_EC#

D10

D22

D9

D50

W20

M17

M19

M20

W12

C10

B12
A12

E10
A11
B11
C11

V20
V19

U18
T17
T18
U19
U20
P16
N17
P18
T20
R19
H19

K16

K20
L18

K19
L17
L19
L20
P20
J18
N20

V10
Y12
V15
U15

U10

V12

E5
A5
A3
B5
B6
A1

A6
D5
C5

R1
R2

C8
C6
D4
D2

P1

W4
U3

T7

Y1
W7

Y3
W1

Y5

T4

T3

Y4

@RB751V

RB751V

RB751V

@RB751V

AD0SA0

CLKRUN#
DEVSEL#
FRAME#
IDSEL
IRDY#
PAR
PCIRST#
PHOLD#
PHLDA#
SERR#
STOP#
TRDY#
PCIREQ1#
PCIREQ2#
PCIREQ3#
PCIREQ4#

EXTSMI#
SUSA#
SUSB#/GPO15
SUSC#/GPO16
SUS_ST1#/GPO20
SUS_ST2#/GPO21
BATLOW#/GPI9
PWRBTN#
LID/GPI10
SMBALERT#/GPI11
RI#/GPI12
SMBDATA
SMBCLK
THRM#/GPI8
CPU_STP#/GPO17
PCI_STP#/GPO18
ZZ/GPO19
RSMRST#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

SLP#
CPURST
INIT
FERR#
IGNNE#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
A20M#

TC
MEMCS16#
MEMR#
MEMW#
SMEMR#
SMEMW#
SYSCLK
BALE
IOCHK#/GPI0
REFRESH#
I0CS16#
ZEROWS#
SBHE#
RSTDRV
IOR#
IOW#
IOCHRDY
AEN

T11

SA0

SA1

LIDSW#

RP28

8P4R_10K

PIRQA#14,15,23
PIRQB#14,15,23,31
PIRQC#14,17,23
PIRQD#14,31

1 2

R141 100
PCIRST#
C126 @47PF

1 2

PX4_REQ1#8
PX4_REQ2#8

GGREQ#23

REQ#28

VLB#26

SMBALT#14

PIIX4_RI#14,26

PIIX4_SLP#6,14

+5VS

FSQ010

1 2

+5VS

R315 1K

1 2

+5VS

ZWS#14

1 2

+5VS

R153 1K

RTCX2

1 2

12

R172 22M

C165
12PF

LID#14

1 8
2 7
3 6
4 5

SUS_STAT#6

CPU_STP#6

RSMRST#8,29

PIIX4_INIT#6

PIIX4_IGNNE#6

PIIX4_INTR6
PIIX4_SMI#6

PIIX4_STPCLK#6

PIIX4_A20M#6
1K

1 2

MEMR#14,25

MEMW#14,25

X1

+3VS

1 1

AD18

2 2

3 3

4 4

AD[0..31]

AD20

AD21

AD19

AD20

B

AD24

AD25

AD22

AD23

AD21

AD22

AD23

AD24

ACIN_SYS#30

AD28

AD29

AD31

AD30

AD27

AD26

AD25

AD26

AD27

AD28

AD29

AD30

AD31

PM

CPU

ISA

SA19

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD8

SD9

SD10

SD11

T16

Y17

SD6

SD7

SD5

B

V17

SD8

SD9

SD10

SD11

VLB#

STOP# 8,14,31
TRDY# 8,14,31
PCIRST# 7,16,31

V4

SD0

SD2

SD1

SD4

SD3

1 2

+3V

R173 10K
STOP#
TRDY#
PCIRST#

Add by Charles at 4/20
that reserved for S/W

REQA#

REQB#

REQA#/GPI2

PC/PCI DMA

SD12

SD13

Y18

W18

Y19

SD13

SD12

SD14

REQC#

REQB#/GPI3

REQC#/GPI4

SD14

SD15

W19

SD15

GNTA#

GNTB#

GNTA#/GPO9

GNTB#/GPO10

DACK0#

U14W6Y10V5T15

DACK#0

C

SCI#25

GNTC#

PIRQA#

PIRQB#

SIRQ

PIRQC#

PIRQD#

J17

H18

K18

J19R3R4P5G1

SERIRQ/GPI7

GNTC#/GPO11

APICREQ#/GPI5

APICCS#/GPO13

APICACK#/GPO12

PIRQA#

PIRQB#

PIRQC#

PIRQD#

*

P19L2J3L5K3K4H1H4H5G3G4

GPI1

PID0

PID2

PID1

MID2

MID3

MID1

MID0

PID3

GPI13

GPI14

GPI15

GPI16

GPI17

GPI18

GPI19

VRCHGNG# 6

+3VS

ENDIM2

ENDIM1

FLASH#

INHIB

SHDRST

PHDRST

HDDPW#

SHDPW#

Y15

T14

T12

Y13

V13

W14

U13

GPO0

GPI20

GPI21

GPO1/LA17

GPO2/LA18

GPO7/LA23

GPO6/LA22

GPO5/LA21

GPO3/LA19

GPO4/LA20

+3V +3VS

R16

R15R6F15

N16

F4F3F2G5T19

VCC1

VCC2

GPO30

VCCSUS1

VCCSUS2

VCC3

GPO8

GPO29

GPO28

GPO27

E11F6T6

VCC4

VCC5

GPI/O PWR

MISC

IDE

*

DACK1#

DACK2#

DACK3#

DACK5#

DACK6#

DACK7#

DREQ0

DREQ1

DREQ2

DREQ3

DREQ5

DREQ6

DREQ7

IRQ0/GPO14

IRQ1

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8#/GPI6

IRQ9

IRQ10

IRQ11

IRQ12

IRQ14

IRQ15

PDD0

PDD1

PDD2

PDD3

PDD4

PDD5

PDD6

PDD7

PDD8

PDD9

V16

W17

W15U6V2U5Y16

U16

U17

H20

J20T9W9U8V8Y8Y20U1U12

DRQ5

DRQ2

DRQ6

DRQ7

DRQ3

DRQ1

DRQ0

DACK#3

DACK#1

DACK#2

IRQ4

IRQ1

IRQ0

IRQ3

Load R167 by Peter Liu 3/30

C/BE#[0..3]8,31

IRQ[0..15]14,22,25
SDD[0..15]22
PDD[0..15]22

DACK#[0..3]27

DRQ[0..7]14,27

SA[0..18]25,27
SD[0..15]14,25,27

C/BE#[0..3]
IRQ[0..15]
SDD[0..15]
PDD[0..15]
DACK#[0..3]

DRQ[0..7]

SA[0..19]

SD[0..15]

C

IRQ5

IRQ7

IRQ6

W13

IRQ9

IRQ8#

IRQ11

IRQ10

1 2

R167 1K

T13

V14

IRQ12

Y14

IRQ14

IRQ15

IRQ8# 25

F20

E18

E20

D18

D20

C20

B20

A20

A19

B19

PDD4

PDD1

PDD0

PDD2

PDD3

+3V

PID[0..3]
CLKRUN#
DEVSEL#
FRAME#
IRDY#
PAR
PCIRST#
PHLD#
PHLDA#
SERR#

PDD5

PDD6

PDD7

PDD8

PDD9

D

P15R7G6

F14F5E16

E12E9K5

VCCP1

VCCP2

VCCP3

VCCP4

VCCP5

VCCP6

VCCP7

VCCP8

PDD10

PDD11

PDD12

PDD13

PDD14

PDD15

SDDO

C19

D19

D17

E19

E17

F19

E15

PDD12

PDD11

PDD10

SDD0

PDD15

PDD14

PDD13

PID[0..3] 23
CLKRUN# 8,14,23,27,31
DEVSEL# 8,14,31
FRAME# 8,14,31
IRDY# 8,14,31
PAR 8,14,31
PCIRST# 7,16,31
PHLD# 8,14
PHLDA# 8,14
SERR# 8,14,31

D

VCCP9

SDD1

B15

SDD1

SDD2

D14

SDD2

C14

J5

VSSUSB

VCCUSB

SDD3

SDD4

A14

C13

SDD4

SDD3

SDD5

SDD5

BIOSCS# 25

GPO25

GT_LO/HI# 6

SYS_VOL_UP# 17
SYS_VOL_DW# 17

W=5mils
W=5mils
W=5mils

+RTCVCC

SPWROFF# 29
OVCUR#0 28,33

OVCUR#1 28,33
USBP1+ 28
USBP1- 28
USBP0+ 28
USBP0- 28

PDIOR# 22
PDIOW# 22
PIORDY 21,22
PDDREQ 21,22
PDDACK# 22
PDCS1# 22
PDCS3# 22

SDIOR# 22
SDIOW# 22
SIORDY 20,22

SDDREQ 20,22
SDDACK# 22
SDCS1# 22
SDCS3# 22
PDA0 22
PDA1 22
PDA2 22
SDA0 22
SDA1 22
SDA2 22

+3VS

12

12

R177 @100K

1 2
1 2

R176 100K

E

FLASH# 26
SIRQ 14,15,27

INHIB 12
ENDIM1 12
ENDIM2 12
REQA# 14
REQB# 14
REQC# 14
GNTA# 14
GNTB# 14
GNTC# 14
PHDRST 21
SHDRST 21

+3V

1 2

R169 100K

14MOSC 10
PCLK_PIIX4 10
RTCCLK 15,16,23

+3V

SPKR 19

C388
1000PF

CONFIG2

E

2

1 2

3

D24

C413 1UF

1 2

J16J9J10

GND

VREF

SDD6

SDD7

SDD8

A13

C12

D12

SDD8

SDD7

SDD6

R342 1K

1

+3VS

RB425D

J11

J12K9K10

K11

K12

GND

GND

GND

GND

GND

GND

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

NC
NC
NC

BIOSCS#
RTCALE/GPO25
RTCCS#/GPO24
KBCCS#/GPO26

XOE#/GPO23

XDIR#/GPO22

*

CONFIG1

*

CONFIG2

PCS0#
PCS1#

MCCS#

CLK48

OSC

PCICLK

*

SUSCLK

*

TEST#

SPKR

*

RTCX1

*

RTCX2

VBAT

*

PWROK

OC0#
OC1#

USBP1+

USBP1-

USBP0+

USBP0-

PDIOR#

PDIOW#

PIORDY

PDDREQ

PDDACK#

PDCS1#
PDCS3#

SDIOR#

SDIOW#

SIORDY

SDDREQ

SDDACK#

SDCS1#
SDCS3#

PDA0
PDA1
PDA2
SDA0
SDA1
SDA2

NC1
NC2
NC3

SDD9

SDD10

SDD11

SDD12

SDD13

SDD14

SDD15

B13

D13

B14

E14

A15

C15

D15

SDD12

SDD15

SDD11

SDD13

SDD10

SDD14

SDD9

Title

Size Document Number Rev

B

Date: Sheet

+5VS

FLASH#
SIRQ

INHIB
ENDIM1
ENDIM2
REQA#
REQB#
REQC#

U12

GNTA#
GNTB#
GNTC#
PHDRST

SHDRST
L9
L10
L11
L12
M9
M10
M11
M12
D10
E7
E13
M5
R5
M16

M2
L1
K2
K1
M4
M3

CONFIG1

R17

CONFIG2

R18
L4
N5
N4

48M

L3

14MOSC

V11

CLK_PX

D11

W=5mils

P17

R174 10K
V18

1 2

K17

RTCX1

N19

RTCX2

R20
L16
M18

J1
J2
F1
H2
G2
H3

F17
F16
G20
F18
G19
H17
H16

C16
B16
D16

SDDREQ

A16
A17
B18
C18
G16
G18
G17
C17
B17
A18
J4
N18
N3

C399
.1UF

PIIX4M

+3V

Compal Electronics, inc.

SCHEMATIC, M/B LA-733
401138

12

12

14MOSC
12

R148
10

12

C136
15PF

13 47Tuesday, August 21, 2001

R137
10

C124
15PF

CONFIG1

of

12

12

48M 10

CLK_PX

R330
10

C400
15PF

4C

A

B

C

D

E

+3VS

12

C398
.1UF

1 1

2 2

3 3

DRQ713
DRQ613
DRQ513

4 4

DRQ013,27

ISA BUS Pull-up PCI BUS Pull-up

+5VS

+5VS

10

10

10

RP11

8P4R_4.7K

R312

1 2

10K
RP31

8P4R_10K

R140 1K

1 2

R307 1K

1 2

RP30

1
2
3
4
5

10P8R_10K

RP8

6
7
8
9

10P8R_4.7K
RP13

6
7
8
9

10P8R_4.7K

RP35

9
8
7
6

10P8R_4.7K

SD[0..15]
SA[0..19]

45
36
27
18

45
36
27
18

ZWS#
IOCHRDY

10
9
8
7
6

5
4
3
2
1

5
4
3
2
1

1
2
3
4
5

IOW# 13,25
MEMR# 13,25
MEMW#13,25,27
IOR# 13,25,27

IRQ5 13

IRQ11 13
IRQ12 13,25
IRQ14 13,22
IRQ15 13,22

SD5
SD0
SD1
SD6

SD11
SD12
SD13
SD14

ZWS# 13
IOCHRDY 13,25,27

+5VS

IRQ4 13
IRQ6 13
IRQ7 13
IRQ9 13

+5VS

+5VS

DRQ1 13,27
DRQ3 13,27
DRQ2 13,27

1
2
3
4
5

+3VS

+3VS

+3VS

1 8
2 7
3 6
4 5

+3V

+3VS

R302 10K

+3VS

RP9

10P8R_10K

NOTE: +3V 8.2K

RP29

1 8
2 7
3 6
4 5

8P4R_10K

1 2

R171 10K
RP10

IRDY#
DEVSEL#
TRDY#
FRAME#

8P4R_10K

RP39

45
36
27
18

8P4R_4.7K

R133 10K

1 2

R134 10K

1 2
1 2

RP7

1 8
2 7
3 6
4 5

8P4R_10K

10
9
8
7
6

PBTN#
SMBALT#

PIIX4_RI#

+3VS

PERR#

PHLDA#
STOP#
SERR#

PERR#31

PHLDA#8,13

STOP#8,13,31
SERR#8,13,31

+5VS

IRQ013
IRQ113,25
IRQ1013
IRQ313

+5VS

+5VS

DRQ7
DRQ6
DRQ5
DRQ0

SD[0..15]13,25,27
SA[0..19]13,25,27

SD4
SD7
SD2

SD3

SD9
SD10
SD8
SD15

PIRQ#A
PIRQ#B
PHLD#
CLKRUN#

PIRQC# 13,17,23
PIRQD# 13,31
PAR 8,13,31
PLOCK# 8

SIRQ 13,15,27

REQA#
REQB#
REQC#
PIIX4_SLP#

+3VS

IRDY# 8,13,31
DEVSEL# 8,13,31
TRDY# 8,13,31
FRAME# 8,13,31

PBTN# 13
LID# 13
SMBALT# 13
PIIX4_RI# 13,26

GNTA# 13
GNTB# 13
GNTC# 13

PIRQA# 13,15,23
PIRQB# 13,15,23,31
PHLD# 8,13
CLKRUN# 8,13,23,27,31

REQA# 13
REQB# 13
REQC# 13
PIIX4_SLP# 6,13

+3VS

12

C396
.1UF

FOR PIIX4

12

C407

.1UF

12

C408

.1UF

12

12

C390

.1UF

C411
.1UF

C392

.1UF

+3VS

12

12

C397
1000PF

+3VS

12

12

12

12

C395

.01UF

12

C409

.01UF

.01UF

C394

.1UF

C402

C405

.01UF

+3V

12

C406

.01UF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

SCHEMATIC, M/B LA-733

B

401138

14

E

47Tuesday, August 21, 2001

of

4C

Compal Electronics, inc.

S2_WP
S2_A23

S1_D[0..15]16

S1_A[0..25]16

S2_D[0..15]16

S2_A[0..25]16

S_AD[0..31]17,31

S_C/BE#[0..3]17,31

+12VS

S_SERR#31

R84 22K

1 2
1 2

R83 22K

RTCCLK13,16,23

S1_D[0..15]
S1_A[0..25]
S2_D[0..15]
S2_A[0..25]
S_AD[0..31]
S_C/BE#[0..3]

R55

1 2

100K

G

2

2N7002
Q9

13

D

S

S2_D0 S1_D0
S2_D1 S1_D1
S2_D2 S1_D2
S2_D3 S1_D3
S2_D4 S1_D4
S2_D5 S1_D5
S2_D6 S1_D6
S2_D7 S1_D7
S2_D8 S1_D8
S2_D9 S1_D9
S2_D10 S1_D10
S2_D11 S1_D11
S2_D12 S1_D12
S2_D13 S1_D13
S2_D14 S1_D14
S2_D15 S1_D15

S2_A0 S1_A0
S2_A1 S1_A1
S2_A2 S1_A2
S2_A3 S1_A3
S2_A4 S1_A4
S2_A5 S1_A5
S2_A6 S1_A6
S2_A7 S1_A7
S2_A8 S1_A8
S2_A9 S1_A9
S2_A10 S1_A10
S2_A11 S1_A11
S2_A12 S1_A12
S2_A13 S1_A13
S2_A14 S1_A14

R280

S2_A16 SB_A16 SA_A16 S1_A16

1 2

Placement near
to PCMCIA
controller

S2_BVD116
S2_BVD216
S2_CD1#16
S2_CD2#16
S2_RDY#16
S2_WAIT#16

S2_WP16

S2_INPACK#16

S2_CE1#16
S2_CE2#16
S2_WE#16

S2_IORD#16

S2_IOWR#16

S2_OE#16
S2_VS116

S2_VS216
S2_REG#16
S2_RST16

S2_A15 S1_A15
S2_A17 S1_A17

S2_A18 S1_A18

47

S2_A19 S1_A19
S2_A20 S1_A20
S2_A21 S1_A21
S2_A22 S1_A22
S2_A23 S1_A23
S2_A24 S1_A24
S2_A25 S1_A25

S2_BVD1 S1_BVD1
S2_BVD2 S1_BVD2
S2_CD1# S1_CD1#
S2_CD2# S1_CD2#
S2_RDY# S1_RDY#
S2_WAIT# S1_WAIT#
S2_WP S1_WP
S2_INPACK# S1_INPACK#

S2_VS2
S2_RST

SLDATA16

DEV_RST#16,23

GNT#38

REQ#38
S_C/BE#317,31
S_C/BE#217,31
S_C/BE#117,31
S_C/BE#017,31

PCLK_PCM10

S_FRAME#17,31
S_DEVSEL#17,31

S_PCIRST#17,31

S_TRDY#17,31

S_IRDY#17,31
S_STOP#17,31
S_PERR#31

S_PAR17,31

76

B_D0/CAD27

78

B_D1/CAD29

80

B_D2/RSVD

17

B_D3/CAD0

19

B_D4/CAD1

21

B_D5/CAD3

24

B_D6/CAD5

26

B_D7/CAD7

77

B_D8/CAD28

79

B_D9/CAD30

81

B_D10/CAD31

18

B_D11/CAD2

20

B_D12/CAD4

23

B_D13/CAD6

25

B_D14/RSVD

27

B_D15/CAD8

67

B_A0/CAD26

66

B_A1/CAD25

65

B_A2/CAD24

62

B_A3/CAD23

60

B_A4/CAD22

59

B_A5/CAD21

57

B_A6/CAD20

54

B_A7/CAD18

39

B_A8/CC/BE1#

36

B_A9/CAD14

29

B_A10/CAD9

34

B_A11/CAD12

52

B_A12/CC/BE2#

41

B_A13/CPAR

43

B_A14/CPERR#

50

B_A15/CIRDY#

48

B_A16/CCLK

37

B_A17/CAD16

40

B_A18/RSVD

42

B_A19/CBLOCK#

45

B_A20/CSTOP#

47

B_A21/CDEVSEL#

49

B_A22/CTRDY#

51

B_A23/CFRAME#

53

B_A24/CAD17

55

B_A25/CAD19

72

B_BVD1/CSTSCHG

71 137

B_BVD2/CAUDIO A_BVD2/CAUDIO

16

B_CD1#/CCD1#

74

B_CD2#/CCD2#

69

B_READY/CINT#

70

B_WAIT#/CSERR#

73

B_WP/CCLKRUN#

61

B_INPACK/CREQ#

28

B_CE1#/CC/BE0#

30

B_CE2#/CAD10

46

B_WE#/CGNT#

33

B_IORD#/CAD13

35

B_IOWR#/CAD15

32

B_OE#/CAD11

68

B_VS1#/CVS1

56

B_VS2#/CVS2

63

B_REG#/CC/BE3#

58

B_RESET/CRST#

CBRST#

1 2

R458 10

1 2

R459 10

202

200

199

198

PAR

SERR#

PERR#

STOP#

195

IRDY#

196

166

TRDY#

RSTIN#

Slot

12
R244

33

C270

12

10PF

197

193

1805203

PCLK

FRAME#

DEVSEL#

169

192

162

168

151

152

175

GNT#

DATA

REQ#

C/BE0#

C/BE1#

C/BE2#

C/BE3#

G_RST#

PCI

Interface

B

CLOCK

149

150

LATCH

+3V

S

D

SPKOUT#

IRQ/DMA

SLATCH 16
PCM_SPK# 19

Add by Charles at 1/4Add by Charles at 3/27

Q7
2N7002

G

2

1 3

12

C43
.1UF

+3V_PCMCIA

178

1

148

VCCI

VCCP

VCCP

Power

31

64

7

VCC

VCC

VCC

Slot

A

SYSON_ALW 30

+3VALW

12

C271
.1UF

+3VALW

86

113

143

164

187

201

VCC

VCC

VCC

VCC

VCC

VCC

S1_VCC_R

S2_VCC_R

120

38

VCCA

VCCB

A_BVD1/CSTSCHG

A_INPACK/CREQ#

C77

.1UF

1 2

W=40mils

W=40mils

C74

1 2

.1UF

A_D0/CAD27
A_D1/CAD29

A_D2/RSVD

A_D3/CAD0
A_D4/CAD1
A_D5/CAD3
A_D6/CAD5

A_D7/CAD7
A_D8/CAD28
A_D9/CAD30

A_D10/CAD31

A_D11/CAD2
A_D12/CAD4
A_D13/CAD6

A_D14/RSVD

A_D15/CAD8
A_A0/CAD26

A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A7/CAD18

A_A8/CC/BE1#

A_A9/CAD14
A_A10/CAD9

A_A11/CAD12

A_A12/CC/BE2#

A_A13/CPAR

A_A14/CPERR#

A_A15/CIRDY#

A_A16/CCLK

A_A17/CAD16

A_A18/RSVD

A_A19/CBLOCK#

A_A20/CSTOP#

A_A21/CDEVSEL#

A_A22/TRDY#

A_A23/CFRAME#

A_A24/CAD17
A_A25/CAD19

A_CD1#/CCD1#

A_CD2#/CCD2#

A_READY/CINT#

A_WAIT#/CSERR#

A_WP/CCLKRUN#

A_CE1#/CC/BE0#

A_CE2#/CAD10

A_WE#/CGNT#

A_IORD#/CAD13

A_IOWR#/CAD15

A_OE#/CAD11
A_VS1#/CVS1
A_VS2#/CVS2

A_REG#/CC/BE3#

A_RESET/CRST#

R72
0_0805

1 2
1 2

R71
0_0805

U28

141
144
146
83
85
88
90
92
142
145
147
84
87
89
91
93

133
132
131
128
126
125
123
119
104
102
95
100
117
106
108
115
112
103
105
107
109
111
114
116
118
121

138
82

140
135
136
139
127

94
97
110
99
101
98

S1_VS1S2_VS1

134

S1_VS2

122
130

S1_RST

124

S2_VCC
S1_VCC

GND

AD29

AD28

AD27

AD26

S2_VCC
S2_VCC

AD4

AD10

AD9

AD8

AD7

AD6

AD5

AD3

AD2

AD1

AD0

1722346

8

91112

14

15

S_AD10

S_AD11

S_AD0

S_AD1

S_AD2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

S_AD9

S_AD4

S_AD5

S_AD7

S_AD8

S_AD6

S_AD3

AD17

AD15

AD14

AD13

AD12

AD11

208

S_AD12

AD18

AD16

165

179

183

184

185

186

188

19010204

205

206

189

191

S_AD15

S_AD21

S_AD18

S_AD23

S_AD22

S_AD20

S_AD19

S_AD17

S_AD14

S_AD13

S_AD16

S_AD25

S_AD24

AD31

AD30

INTA#/MFUNC0

IDSEL

INTB#/MFUNC1

SUSPEND#

173

174

176

177

170

171

154

182

155

156

157

PCM_INTB#

PCM_INTA#

12

S_AD26

S_AD27

R47

S_AD28

S_AD29

S_AD30

S_AD31

100

S_AD15

AD25

AD24

AD23

AD22

AD21

AD20

AD19

RIOUT#/PME#

DMAGNT#/MFUNC5

LOCK#/MFUNC4

IRQSER/MFUNC3

DMAREQ#/MFUNC2

CLKRUN#/MFUNC6

163

13

160

159

158

161

PCM_RI#

1 2

R460 10

Add by Charles at 3/27

GND

GND

GND

GND

GND

22

44

75

96

129

S_PME# 17,31
S_CLKRUN# 31

PCM_RI# 28
SIRQ 13,14,27

GND

GND

153

GND

GND

GND

167

181

194

D14 RB751V

GND

PCI1420

207

R48 22K

1 2

2 1

+3V

PCM_SUSP# 25

CARDBUS
PCI1420

R281

1 2

47

Placement near
to PCMCIA
controller

+3VALW

S1_BVD1 16
S1_BVD2 16
S1_CD1# 16
S1_CD2# 16
S1_RDY# 16
S1_WAIT# 16
S1_WP 16
S1_INPACK# 16

S1_CE1# 16
S1_CE2# 16
S1_WE# 16
S1_IORD# 16
S1_IOWR# 16
S1_OE# 16
S1_VS1 16
S1_VS2 16
S1_REG# 16
S1_RST 16

+3V_PCMCIA

12

12

C42

C40

.1UF

.1UF

+3VALW +3VALW

12

C322
1000PF

PCM_INTA#

PCM_INTB#

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-733

Size Document Number Rev

B

401138

Date: Sheet

12

12

C72
.1UF

C41
1000PF

S1_A23

S1_WP

R50
22K

12

+3VALW

12

C48
.1UF

12

C53
1000PF

12

12

12

R78 22K

1 2

1 2

R62 22K

+3V

R49
22K

D16

RB751V
D15

@RB751V

C321
.1UF

C80
1000PF

21

21

S1_VCC

S1_VCC

PIRQA# 13,14,23

PIRQB# 13,14,23,31

15 47Tuesday, August 21, 2001

of

4C