How it Works
Acer
Loading...
LA-4381P
Schematics
41 pgs1.11 Mb0

Acer LA-4381P Schematics

A
1 1
B
C
D
E
U1 - KAL00
2 2
Compal Confidential
Schematics Document
AMD S1g2/ ATI RS780M / SB700
3 3
4 4
A
B
Wednesday, January 16, 2008
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/12/12 2008/12/12
Deciphered Date
Title
Cover Sheet
Size Document Number Rev
Custom
U1 LA-4381P
D
Date: Sheet
E
141
0.0
of
A
B
C
D
E
Compal confidential
Project Code: ANRKAL0000(KAL00) File Name : LA-4381P PCB P/N:
1 1
ZZZ1
15W_PCB
Thermal Sensor ADM1032ARM
page 6 page 14
CRT
page 15
LCD CONN
page 15
HDMI CONN
page 16
Clock Generator SLG8SP626VTR
/ICS9LPRS476BKLFT
PCI EXPRESS
Turion64 x2 TLxx / Sempron
AMD S1g2 CPU
page 4,5,6,7
HT 16x16 1.6G~3.2GHZ
ATI-RS780M
page 10,11,12,13
A-Link Express
4 x PCIE
DDR-2 DDR2-SO-DIMM X2
Daul Channel DDR-2 Up to 800MHz
BUS A-->JDIM2-->UPPER SLOT BUS B-->JDIM1-->LOWER SLOT
page 8,9
2 2
Broadcom
BCM5784M
page 25
Express Card (New Card)
page 24
Mini Card WLAN
page 24
ATI-SB700
HD-Interface
USB 2.0
RJ45 CONN
page 26
PCI BUS
page 17,18,19,20,21
USB 2.0 IDE
Audio CKT ALC269
USB conn x 4 Felica Conn
Hyper Flash
page 27
page 32
page 31
page 23
Audio Jack
page 28
Crad Reader Controller
Ricoh R5C833
page 22
3 3
Media Card
page 22
Power On/Off CKT.
page 33
LPC BUS
SATA GEN2
SATA GEN2
SATA ODD Conn.
page 23
SATA HDD Conn.
page 23
ENE KB926
DC/DC Interface CKT.
page 34
Power Circuit DC/DC
4 4
page 35~42
RTC CKT.
page 17
Power OK CKT.
page 33
Touch Pad CONN.
page 31
page 29
Int. KBD
page 31
SPI BIOS
page 29
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/12/12 2008/12/12
Deciphered Date
Title
Block Diagrams
Size Document Number Rev
Custom
U1 LA-4381P
D
Date: Sheet
E
241Wednesday, January 16, 2008
0.0
of
A
Voltage Rails
Power Plane Description
VIN
1 1
2 2
B+ +CPU_CORE0,1 +VDDNB +0.8V~1.1V CPU NBVDD ON ON OFF +1.2V_HT +0.9V 0.9V switched power rail for DDR terminator +1.2VALW 1.2V always on power rail ONON +1.5VS +1.8VS 1.8V switched power rail +1.8V +3VALW +3VS +5VALW 5V always on power rail +5VS +RTCVCC RTC power
Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU
1.2V switched power rail
1.5V switched power rail
1.8V power rail for DDR
3.3V always on power rail
3.3V switched power rail
5V switched power rail
B
S1 S3 S4/ S5
ON ON ON
ON OFF
ON OFF OFF ON OFF ON ON OFF OFF ON OFF OFF ON OFFON ON ON ON
ON ONON
ONONON OFF
ON
ON ON OFF
OFF ON ON OFF
OFFON
C
SIGNAL
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
SLP_S1# SLP_S3#
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
S4 (Suspend to Disk)
S5 (Soft OFF)
LOW LOW LOW LOW
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0 1 2 3 4 5 6 7 NC
100K +/- 5%Ra / Rc
Rb / Rd V min
0
8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
D
SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
OFF
OFF
V
AD_BID
ON ON
ON
OFF
OFF
OFF
max
LOW
OFF
OFF
OFF
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
V typ
AD_BID
ON
ON
ON
ON
ON
0 V 0 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
E
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
CardBus
AD21
0
PIRQE/PIRQF/PIRQG
BOARD ID Table
Board ID
0 1 2 3 4
PCB Revision
0.1 (U1 ES1)
0.2 (U1 ES2)
0.3 (U1 PP)
0.4 (U1 PPR)
1.0 (U1 IRT)
BTO Item BOM Structure
BTO Option Table
5 6 7
EC SM Bus1 address
3 3
Device
Smart Battery EEPROM(24C16/02)
(24C04)
Address Address
1010 000X b? 1011 000Xb?
EC SM Bus2 address
Device
ADM1032
1001 110X b?0001 011X b?
SB700 SM Bus address
Device
Clock Generator ( ICS9LPRS476BKLFT)
DDRII DIMM0 DDRII DIMM1
4 4
Address
1101 001Xb?
1001 000Xb? 1001 010Xb?
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/12/12 2008/12/12
Deciphered Date
Title
Notes
Size Document Number Rev
Custom
U1 LA-4381P
D
Date: Sheet
E
341Wednesday, January 16, 2008
0.0
of
5
4
3
2
1
HT LINK
L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1 L0_CTLOUT_H0
L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1
<BOM Strucrure>
H_CADOP[0..15] H_CADON[0..15]
VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3
H_CADOP[0..15] <10>H_CADIP[0..15]<10> H_CADON[0..15] <10>H_CADIN[0..15]<10>
+1.2V_HT
1
AE2 AE3 AE4 AE5
H_CADOP0
AD1
H_CADON0
AC1
H_CADOP1
AC2
H_CADON1
AC3
H_CADOP2
AB1
H_CADON2
AA1
H_CADOP3
AA2
H_CADON3
AA3
H_CADOP4
W2
H_CADON4
W3
H_CADOP5
V1
H_CADON5
U1
H_CADOP6
U2
H_CADON6
U3
H_CADOP7
T1
H_CADON7
R1
H_CADOP8
AD4
H_CADON8
AD3
H_CADOP9
AD5
H_CADON9
AC5
H_CADOP10
AB4
H_CADON10
AB3
H_CADOP11
AB5
H_CADON11
AA5
H_CADOP12
Y5
H_CADON12
W5
H_CADOP13
V4
H_CADON13
V3
H_CADOP14
V5
H_CADON14
U5
H_CADOP15
T4
H_CADON15
T3
H_CLKOP0
Y1
H_CLKON0
W1
H_CLKOP1
Y4
H_CLKON1
Y3
H_CTLOP0H_CTLIP0
R2
H_CTLON0
R3
H_CTLOP1
T5
H_CTLON1H_CTLIN1
R5
C523
H_CLKOP0 <10> H_CLKON0 <10> H_CLKOP1 <10> H_CLKON1 <10>
H_CTLON0 <10> H_CTLOP1 <10> H_CTLON1 <10>
2
4.7U_0805_6.3V6K~N
C543
close to CPU Socket
1
C544
2
4.7U_0805_6.3V6K~N
1
1
1
C539
C522
2
2
0.22U_0603_10V7K
4.7U_0805_6.3V6K~N
1
C521
C526
2
2
0.22U_0603_10V7K 180P_0402_50V8J~N
FAN1 Control and Tachometer
EN_DFAN1<28>
FAN_SPEED1<28>
1
2
180P_0402_50V8J~N
EN_DFAN1
R364
10K_0402_5%
1SS355TE-17_SOD323-2 @
10U_0805_10V4Z~N
1000P_0402_50V7K~N
+3VS
12
2
C540
0.01U_0402_16V7K
1
+5VS
12
D27
@
12
D26 BAS16_SOT23-3
C541
12
+5VS
@
C527
12
@
FAN1_POWER
40mil
@
1 2
C545 10U_0805_10V4Z~N U25
1
VEN
2
VIN
3
VO
4
VSET
G993P1UF_SOP8 JFAN1
1 2 3
4
G
5
G
ACES_85205-0300N~N
CONN@
FAN1
GND GND GND GND
8 7 6 5
H_CADIP[0..15] H_CADIN[0..15]
+1.2V_HT
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1
H_CTLIN0 H_CTLIP1
1.5A
D1
VLDT_A0
D2
VLDT_A1
D3
VLDT_A2
D4
VLDT_A3
E3
L0_CADIN_H0
E2
L0_CADIN_L0
E1
L0_CADIN_H1
F1
L0_CADIN_L1
G3
L0_CADIN_H2
G2
L0_CADIN_L2
G1
L0_CADIN_H3
H1
L0_CADIN_L3
J1
L0_CADIN_H4
K1
L0_CADIN_L4
L3
L0_CADIN_H5
L2
L0_CADIN_L5
L1
L0_CADIN_H6
M1
L0_CADIN_L6
N3
L0_CADIN_H7
N2
L0_CADIN_L7
E5
L0_CADIN_H8
F5
L0_CADIN_L8
F3
L0_CADIN_H9
F4
L0_CADIN_L9
G5
L0_CADIN_H10
H5
L0_CADIN_L10
H3
L0_CADIN_H11
H4
L0_CADIN_L11
K3
L0_CADIN_H12
K4
L0_CADIN_L12
L5
L0_CADIN_H13
M5
L0_CADIN_L13
M3
L0_CADIN_H14
M4
L0_CADIN_L14
N5
L0_CADIN_H15
P5
L0_CADIN_L15
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
FOX_PZ6382A-284S-41F_TURION
JCPU1A
D D
C C
H_CLKIP0<10> H_CLKIN0<10> H_CLKIP1<10> H_CLKIN1<10>
H_CTLIP0<10> H_CTLOP0 <10> H_CTLIN0<10> H_CTLIP1<10> H_CTLIN1<10>
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/12/12 2008/12/12
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Griffin HT I/F & FAN
U1 LA-4381P
1
0.0
of
441Wednesday, January 16, 2008
A
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+0.9V
0.75A
D10
KEEP TRACE TO RESISTORS
4 4
3 3
2 2
LESS THAN 1" FROM CPU PIN
+1.8V
R346 39.2_0603_1%
1 2
R353 39.2_0603_1%
1 2
DDR_A_ODT0<8> DDR_A_ODT1<8>
DDR_A_CS0#<8> DDR_A_CS1#<8>
DDR_A_CKE0<8> DDR_A_CKE1<8>
DDR_A_CLK1<8>
DDR_A_CLK#1<8>
DDR_A_CLK2<8>
DDR_A_CLK#2<8>
DDR_A_MA[15..0]<8>
DDR_A_BS#0<8> DDR_A_BS#1<8> DDR_A_BS#2<8>
DDR_A_RAS#<8> DDR_A_CAS#<8> DDR_A_WE#<8>
DDR_A_CLK2
DDR_A_CLK#2 DDR_A_CLK1
DDR_A_CLK#1
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
M_ZP M_ZN
TP22
TP8 TP7
TP11 TP12
TP10 TP13
1
2
1
2
DDR_A_ODT0 DDR_A_ODT1
DDR_A_CS0# DDR_A_CS1#
DDR_A_CKE0 DDR_A_CKE1
DDR_A_CLK1 DDR_A_CLK#1 DDR_A_CLK2 DDR_A_CLK#2
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
C80
1.5P 50V F NPO 0402
C125
1.5P 50V F NPO 0402
AD10 AF10
AE10
AA16
C10 B10
H16 T19
V22 U21 V19
T20 U19 U20 V20
J22 J20
N19 N20 E16 F16 Y16
P19 P20
N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19
R20 R23
J21
R19 T22 T24
B
JCPU1B
VTT1
MEM:CMD/CTRL/CLK
VTT2 VTT3 VTT4
MEMZP MEMZN
RSVD_M1 MA0_ODT0
MA0_ODT1 MA1_ODT0 MA1_ODT1
MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1
MA_CKE0 MA_CKE1
MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3
MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15
MA_BANK0 MA_BANK1 MA_BANK2
MA_RAS_L MA_CAS_L MA_WE_L
FOX_PZ6382A-284S-41F_TURION
DDR_B_CLK2
DDR_B_CLK#2 DDR_B_CLK1
DDR_B_CLK#1
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
VTT_SENSE
MB0_ODT0 MB0_ODT1 MB1_ODT0
MB0_CS_L0 MB0_CS_L1 MB1_CS_L0
MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CLK_H2 MB_CLK_L2 MB_CLK_H3 MB_CLK_L3
MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_RAS_L MB_CAS_L
<BOM Strucrure>
VTT5 VTT6 VTT7 VTT8 VTT9
MEMVREF
RSVD_M2
MB_CKE0 MB_CKE1
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9
MB_WE_L
1
C520
1.5P 50V F NPO 0402
2
1
C549
1.5P 50V F NPO 0402
2
W10 AC10 AB10 AA10 A10
Y10 W17 B18 W26
W23 Y26
V26 W25 U22
J25 H26
P22 R22 A17 A18 AF18 AF17 R26 R25
P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24
R24 U26 J26
U25 U24 U23
R64
1 2
0_0402_5%
DDR_B_ODT0 DDR_B_ODT1
DDR_B_CS0# DDR_B_CS1#
DDR_B_CKE0 DDR_B_CKE1
DDR_B_CLK1 DDR_B_CLK#1 DDR_B_CLK2 DDR_B_CLK#2
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
+CPU_M_VREF
TP47
TP5
TP15 TP14
TP9 TP16
VTT_SENSE_FB
DDR_B_ODT0 <9> DDR_B_ODT1 <9>
DDR_B_CS0# <9> DDR_B_CS1# <9>
DDR_B_CKE0 <9> DDR_B_CKE1 <9>
DDR_B_CLK1 <9> DDR_B_CLK#1 <9> DDR_B_CLK2 <9> DDR_B_CLK#2 <9>
DDR_B_MA[15..0] <9>
DDR_B_BS#0 <9> DDR_B_BS#1 <9> DDR_B_BS#2 <9>
DDR_B_RAS# <9> DDR_B_CAS# <9> DDR_B_WE# <9>
C
D
E
Processor DDR2 Memory Interface
JCPU1C
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5
TP6
To reverse SODIMM socket (TOP)
DDR_B_DM[7..0]<9>
DDR_B_DQS0<9> DDR_B_DQS#0<9> DDR_B_DQS1<9> DDR_B_DQS#1<9> DDR_B_DQS2<9> DDR_B_DQS#2<9> DDR_B_DQS3<9> DDR_B_DQS#3<9> DDR_B_DQS4<9> DDR_B_DQS#4<9> DDR_B_DQS5<9> DDR_B_DQS#5<9> DDR_B_DQS6<9> DDR_B_DQS#6<9> DDR_B_DQS7<9> DDR_B_DQS#7<9>
DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7
AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11
AE14 AF14 AF11 AD11
AB26 AE22 AC16 AD12
AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24
Y11
A12 B16 A22 E25
C12 B12 D16 C16 A24 A23 F26 E26
MEM:DATA
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7
FOX_PZ6382A-284S-41F_TURION
<BOM Strucrure>
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8
MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7
G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12
E12 C15 E19 F24 AC24 Y19 AB16 Y13
G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7
DDR_A_D[63..0] <8>DDR_B_D[63..0]<9>
To reverse SODIMM socket (Bottom)
DDR_A_DM[7..0] <8>
DDR_A_DQS0 <8> DDR_A_DQS#0 <8> DDR_A_DQS1 <8> DDR_A_DQS#1 <8> DDR_A_DQS2 <8> DDR_A_DQS#2 <8> DDR_A_DQS3 <8> DDR_A_DQS#3 <8> DDR_A_DQS4 <8> DDR_A_DQS#4 <8> DDR_A_DQS5 <8> DDR_A_DQS#5 <8> DDR_A_DQS6 <8> DDR_A_DQS#6 <8> DDR_A_DQS7 <8> DDR_A_DQS#7 <8>
+1.8V
1
R65
1K_0402_1%
1 2
1 1
R66
1K_0402_1%
1 2
C82
+CPU_M_VREF
2
0.1U_0402_16V7K~N
1
1
C94
C81
2
2
0.1U_0402_16V7K~N
LAYOUT:PLACE CLOSE TO CPU
A
1000P_0402_50V7K~N
Place between CPU to DDR area(Reserved for EMI)
+1.8V
1
C119
2
0.1U_0402_16V7K~N
1
C106
2
0.1U_0402_16V7K~N
B
1
C118
2
1
C132
2
1
2
0.1U_0402_16V7K~N
1
2
0.1U_0402_16V7K~N
1
C104
0.1U_0402_16V7K~N
C97
0.1U_0402_16V7K~N
C96
2
0.1U_0402_16V7K~N
1
C105
2
0.1U_0402_16V7K~N
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/12/12 2008/12/12
Compal Secret Data
Deciphered Date
D
Title
Griffin DDRII MEMORY I/F
Size Document Number Rev
Custom
U1 LA-4381P
Date: Sheet
E
541Wednesday, January 16, 2008
of
0.0
R103 0_0805_5%
+3VALW
+3VS +2.5VDDA
R102 0_0805_5%
1U_0603_10V6K
D D
SYSON#<32,39>
+1.8VS
C C
LDT_RST#<17>
CPU_PWRGD<17>
LDT_STOP#<11,17>
CPU_LDT_REQ#<11,17>
B B
CPU_DBREQ#
A A
CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
5
@
12 12
2
1
C251
R112
470_0402_5%
SYSON#
2
G
1 2
R367 300_0402_5%
1 2
C557 0.01U_0402_16V7K@
1 2
R74 300_0402_5%
1 2
C122 0.01U_0402_16V7K@
1 2
R123 300_0402_5%
1 2
C276 0.01U_0402_16V7K@
1 2
R90 300_0402_5%
1 2
C188 0.01U_0402_16V7K@
+1.8V
R358220_0402_5%@
R359220_0402_5%@
R357220_0402_5%@
R356220_0402_5%@
12
12
12
12
5
U6
1
IN
OUT
2
GND SHDN3BYP
G914E_SOT23-5
12
13
D
Q10 SSM3K7002FU_SC70-3
S
@
1 2
R145 0_0402_5%
1 2
R366 0_0402_5%
1 2
R371 0_0402_5%
1 2
R77 0_0402_5%
1 2
R91 0_0402_5%
R360300_0402_5%
12
C260
0.01U_0402_16V7K
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
CPU_LDT_REQ#_CPU
CPU_HT_RESET#
CPU_ALL_PWROK CPU_PWRGD_SVID_REG
CPU_LDTSTOP#
CPU_LDT_REQ#_CPU
HDT Connector
CONN@
5
2
4
C252 1U_0603_10V6K
1
1
2
J12OPEN PADS
1 2
JDB1
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423 26
SAMTEC_ASP-68200-07
place them to CPU within 1.5"
CPU_PWRGD_SVID_REG <40>
+2.5VDDA
150U_D2_6.3VM
CLK_CPUCLK0_H<14>
CLK_CPUCLK0_L<14>
+3VS
+1.8V
+1.8V
HDT_RST#
4
C253
R193
390_0402_5%
CPU_SID
R217
390_0402_5%
CPU_SIC
U23
4
Y
4
1
+
2
20K_0402_5%
12
12
+3VS
5
P
B A
G
3
LAYOUT: ROUTE VDDA TRACE APPROX. 50 mils WIDE (USE 2x25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.
LQG21F4R7N00_0805
1 2
L8
4.7U_0805_6.3V6K~N
1 2
C555
169_0402_1%
1 2
C556 3900P_0402_50V7K
CPU_VDD0_RUN_FB_H<40> CPU_VDD0_RUN_FB_L<40>
CPU_VDD1_RUN_FB_H<40> CPU_VDD1_RUN_FB_L<40>
R189
12
S
Q25 FDV301N_NL_SOT23-3
S
Q27 FDV301N_NL_SOT23-3
LDT_RST#
2 1
NC7SZ08P5X_NL_SC70-5@
3900P_0402_50V7K
12
R365
+1.2V_HT
TP4
TP21 TP27
TP25 TP2
TP46 TP45 TP44
TP1 TP43
TP3
1 2
C355 0.1U_0402_16V4Z
R190
12
34.8K_0402_1%~N
G
2
13
D
G
2
13
D
0.25A
1
C213
2
3300P_0402_50V7K
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
CPU_HT_RESET# CPU_ALL_PWROK CPU_LDTSTOP# CPU_LDT_REQ#_CPU
CPU_SIC CPU_SID CPU_ALERT#
R67 44.2_0402_1%
1 2
R68 44.2_0402_1%
1 2
CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI
CPU_TEST23_TSTUPD CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0 CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST27_SINGLECHAIN
R81 0_0402_5%
CPU_TEST6_DIECRACKMON
1
C189
2
1 2
1
C214
0.22U_0603_10V7K
2
2.09V for Gate
EC_SMB_DA1 <28,34>
EC is PU to 5VALW
EC_SMB_CK1 <28,34>
SB_PWRGD <11,18,28>
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+VDDA_CPU
+VDDA_CPU
CPU_HTREF0 CPU_HTREF1
FDV301N, the Vgs is: min = 0.65V Typ = 0.85V Max = 1.5V
Issued Date
3
+1.8V
R76
1 2 2
@
3 1
@
M11 W18
CPU_SVC
A6
CPU_SVD
A4
CPU_THERMTRIP#_R
AF6
CPU_PROCHOT#_1.8
AC7
CPU_MEMHOT#_1.8V
AA8
THERMDC_CPU
W7
THERMDA_CPU
W8
W9 Y9
H6 G6
E10 AE9
J7 H8
D7 E7 F7 C7
C3 K8
C4
C9 C8
H18 H19 AA7 D5 C5
+3VS
10K_0402_5%
R361
4.7K_0402_5%
Q9
@
1 2
CPU_DBREQ# CPU_TDO
CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N
CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0
CPU_TEST7_ANALOG_T CPU_TEST10_ANALOGOUT
CPU_TEST8_DIG_T
CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N
THERMDA_CPU
THERMDC_CPU
EC_SMB_CK2<28> EC_SMB_DA2<28>
CPU_ALERT#
F8 F9
A9 A8
B7 A7
F10
C6
AF4 AF5
AE6
R6 P6
F6 E6
Y6
AB6
G10
AA9 AC9 AD9 AF9
AD7 H10
G9
E9 E8
AB8 AF7 AE7 AE8 AC8 AF8
C2
AA6
A3 A5 B3 B5 C1
JCPU1D
VDDA1 VDDA2
CLKIN_H CLKIN_L
RESET_L PWROK LDTSTOP_L LDTREQ_L
SIC SID ALERT_L
HT_REF0 HT_REF1
VDD0_FB_H VDD0_FB_L
VDD1_FB_H VDD1_FB_L
DBRDY TMS TCK TRST_L TDI
TEST23 TEST18
TEST19 TEST25_H
TEST25_L TEST21
TEST20 TEST24 TEST22 TEST12 TEST27
TEST9 TEST6
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5
FOX_PZ6382A-284S-41F_TURION
CONN@
THERMTRIP_L
VDDNB_FB_H VDDNB_FB_L
+1.8V
12
R75
KEY1 KEY2
PROCHOT_L
MEMHOT_L
THERMDC THERMDA
VDDIO_FB_H
VDDIO_FB_L
DBREQ_L
TEST28_H TEST28_L
TEST17 TEST16 TEST15 TEST14
TEST7
TEST10
TEST8
TEST29_H TEST29_L
RSVD10
RSVD9 RSVD8 RSVD7 RSVD6
1K_0402_5%
MMBT3904_NL_SOT23-3
SVC SVD
TDO
SMBus Address: 1001110X (b)
2007/12/12 2008/12/12
Deciphered Date
2
SMB_ALERT#
SMB_ALERT# <18>
CPU_SVC <40> CPU_SVD <40>
CPU_VDDIO_FB_H <37> CPU_VDDIO_FB_L <37>
CPU_VDDNB_RUN_FB_H <40> CPU_VDDNB_RUN_FB_L <40>
TP18 TP19
TP23 TP17 TP24TP26 TP30
TP29 TP20
TP28
TP32 TP31
VID BYPASS CIRCUIT
Thermal Sensor ADM1032
1
C525
2200P_0402_50V7K
2
EC_SMB_CK2 EC_SMB_DA2
2
1
CPU_SVC CPU_SVD CPU_THERMTRIP#_R CPU_PROCHOT#_1.8 CPU_MEMHOT#_1.8V
+1.8V
CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
route as differential as short as possible testpoint under package
CPU_TEST27_SINGLECHAIN CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN
CPU_TEST18_PLLTEST1 CPU_TEST19_PLLTEST0 CPU_TEST12_SCANSHIFTENB CPU_TEST15_BP1 CPU_TEST14_BP0
+3VS
1
C524
0.1U_0402_16V7K~N
2
U24
2 3 8 7
VDD1
D+
ALERT#
D-
THERM#
SCLK
GND
SDATA
ADM1032ARMZ MSOP 8P
Title
Griffin CTRL & ADM1032
Size Document Number Rev
Custom
U1 LA-4381P
Date: Sheet
3 1
MMBT3904_NL_SOT23-3
+1.8V
3 1
MMBT3904_NL_SOT23-3@
1 2
R345 0_0402_5%
1
SMB_ALERT#
6
THERM#
4 5
Compal Electronics, Inc.
R86 1K_0402_5% R83 1K_0402_5% R355 300_0402_5% R354 300_0402_5% R57 300_0402_5%
R351 10K_0402_5%
1 2 2
Q43
R347 10K_0402_5%
@
1 2 2
Q42
R348 300_0402_5%@
1 2
R59 300_0402_5%
1 2
R352 300_0402_5%@
1 2
R350 300_0402_5%
1 2
R349 300_0402_5%@
1 2
R73 300_0402_5%@
1 2
R72 300_0402_5%@
1 2
R58 300_0402_5%@
1 2
R71 300_0402_5%@
1 2
R82 300_0402_5%@
1 2
12
R70
10K_0402_5%@
R69
1 2
0_0402_5%
@
1
H_THERMTRIP# <18>
CPU_PROCHOT# <17>
+1.8V
CPU_PROCHOT#_1.8
641Wednesday, January 16, 2008
+1.8V
12 12 12 12 12
0.0
of
5
4
3
2
1
VDD(+CPU_CORE) decoupling.
+VCC_CORE0
D D
1
+
C120 330U_X_2VM_R6M
2
1
+
C107 330U_X_2VM_R6M
2
Near CPU Socket
+VCC_CORE0
1
C111 22U_0805_6.3V6M
2
+VCC_CORE0
1
C112
0.22U_0603_16V4Z
C C
2
1
C123 22U_0805_6.3V6M
2
1
C108
0.01U_0402_25V4Z
2
1
C110 22U_0805_6.3V6M
2
1
2
C121 180P_0402_50V8J
1
C124 22U_0805_6.3V6M
2
Under CPU Socket
+VCC_CORE1
+VCC_CORE1
1
C99 22U_0805_6.3V6M
2
1
+
C75 330U_X_2VM_R6M
2
+VCC_CORE1
1
C98 22U_0805_6.3V6M
2
1
C76
0.22U_0603_16V4Z
2
1
+
C91 330U_X_2VM_R6M
2
1
C101 22U_0805_6.3V6M
2
1
C100
0.01U_0402_25V4Z
2
1
C109 22U_0805_6.3V6M
2
1
C92 180P_0402_50V8J
2
+VCC_CORE0 +VCC_CORE1
+VDDNB
+1.8V
G4
18A 18A
H2
J9 J11 J13 J15
K6 K10 K12 K14
L4
L7
L9 L11 L13
L15
M2 M6 M8
M10
N7
N9
N11
3A
K16
M16
P16 T16 V16
H25
J17
K18 K21 K23 K25
L17 M18 M21 M23 M25
N17
JCPU1E
VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23
VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12
FOX_PZ6382A-284S-41F_TURION
VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8
VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
<BOM Strucrure>
P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2
Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
+1.8V
2A
VDDIO decoupling.
+1.8V
1
C127 22U_0805_6.3V6M
2
1
C126 22U_0805_6.3V6M
2
1
C93
0.22U_0603_16V4Z
2
1
C103
0.22U_0603_16V4Z
2
1
C95
180P_0402_50V8J
2
1
C146 180P_0402_50V8J
2
+CPU_CORE_NB decoupling.
+VDDNB
1
C113 22U_0805_6.3V6M
2
1
C114 22U_0805_6.3V6M
2
1
C102 22U_0805_6.3V6M
2
AA11 AA13 AA15 AA17 AA19
AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21
AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23
AA4
AB2 AB7 AB9
AD6 AD8
B4 B6 B8
B9 B11 B13 B15 B17 B19 B21 B23 B25
D6
D8
D9 D11 D13 D15 D17 D19 D21 D23 D25
E4
F2 F11 F13 F15 F17 F19 F21 F23 F25
H7
H9 H21 H23
J4
Under CPU Socket
JCPU1F
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65
FOX_PZ6382A-284S-41F_TURION
VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129
<BOM Strucrure>
J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
B B
A A
+1.8V
1
C88
0.22U_0603_16V4Z
2
+1.8V +1.8V
1
C83
0.01U_0402_25V4Z
2
+1.8V
1
2
Between CPU Socket and DIMM
C86
4.7U_0805_10V4Z~N
1
C89
0.22U_0603_16V4Z
2
1
C116
0.01U_0402_25V4Z
2
1
C128
4.7U_0805_10V4Z~N
2
1
C131
0.22U_0603_16V4Z
2
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
1
C84 180P_0402_50V8J
2
1
C87
4.7U_0805_10V4Z~N
2
1
C130
0.22U_0603_16V4Z
2
1
C117 180P_0402_50V8J
2
A: Add C165 and C176 to follow AMD Layout review recommand for EMI
1
C129
4.7U_0805_10V4Z~N
2
1
C85 180P_0402_50V8J
2
1
C: Change to NBO CAP
+
C90 220U_Y_4VM
@
2
1
C115 180P_0402_50V8J
2
VTT decoupling.
+0.9V
1
C215
4.7U_0805_10V4Z~N
2
+0.9V
1
C49
4.7U_0805_10V4Z~N
2
1
C216
4.7U_0805_10V4Z~N
2
Near CPU Socket Right side.
1
C47
4.7U_0805_10V4Z~N
2
1
C551
0.22U_0603_16V4Z
2
1
C48
0.22U_0603_16V4Z
2
+0.9V
Near Power Supply
1
C: Change to NBO CAP
+
C50 220U_Y_4VM
2
1
C550
0.22U_0603_16V4Z
2
1
C46
0.22U_0603_16V4Z
2
1
C553 1000P_0402_25V8J
2
1
C77 1000P_0402_25V8J
2
1
C554 1000P_0402_25V8J
2
1
C45 1000P_0402_25V8J
2
1
C552 180P_0402_50V8J
2
1
C79 180P_0402_50V8J
2
1
C559 180P_0402_50V8J
2
1
C78 180P_0402_50V8J
2
Near CPU Socket Left side.
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/12/12 2008/12/12
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Griffin PWR & GND
U1 LA-4381P
1
0.0
of
741Wednesday, January 16, 2008
5
JDIM1
1
VREF
3
DDR_A_D0
D D
C C
DDR_A_CKE0<5>
DDR_A_BS#2<5>
DDR_A_BS#0<5> DDR_A_WE#<5>
DDR_A_CAS#<5>
DDR_A_CS1#<5>
DDR_A_ODT1<5>
B B
A A
SMB_CK_DAT0<9,14,18> SMB_CK_CLK0<9,14,18>
DDR_A_D1 DDR_A_DQS#0
DDR_A_DQS0 DDR_A_D2
DDR_A_D3 DDR_A_D8
DDR_A_D9 DDR_A_DQS#1
DDR_A_DQS1 DDR_A_D10
DDR_A_D11
DDR_A_D16 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D22 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_DM3
DDR_A_D26 DDR_A_D27
DDR_A_CKE0
DDR_A_BS#2 DDR_A_MA12
DDR_A_MA9
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#
DDR_A_CAS# DDR_A_CS1#
DDR_A_ODT1 DDR_A_D32
DDR_A_D33 DDR_A_DQS#4
DDR_A_DQS4 DDR_A_D34
DDR_A_D35 DDR_A_D40
DDR_A_D41 DDR_A_DM5 DDR_A_D42
DDR_A_D43 DDR_A_D47 DDR_A_D48
DDR_A_D49 DDR_A_D53
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51 DDR_A_D55
DDR_A_D56 DDR_A_D57
DDR_A_DM7 DDR_A_D58
DDR_A_D59 SMB_CK_DAT0
SMB_CK_CLK0
+3VS
5
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_ASOA426-M2RN-7F
CONN@
REVERSE TYPE LOW SLOT
DQ4 DQ5
DM0 DQ6
DQ7
DQ12 DQ13
DM1
CK0#
DQ14 DQ15
DQ20 DQ21
DM2
DQ22 DQ23
DQ28 DQ29
DQS3#
DQS3 DQ30
DQ31
NC/CKE1
VDD NC/A15 NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
DQ36 DQ37
DM4
DQ38 DQ39
DQ44 DQ45
DQS5#
DQS5 DQ46
DQ47 DQ52
DQ53
CK1#
DM6
DQ54 DQ55
DQ60 DQ61
DQS7#
DQS7 DQ62
DQ63
VSS
VSS VSS
VSS
VSS VSS
CK0 VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A11
BA1 S0#
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS CK1
VSS VSS
VSS
VSS
VSS
VSS SA0 SA1
4
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50
NC
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92
A7
94
A6
96 98
A4
100
A2
102
A0
104 106 108 110 112 114 116 118 120
NC
122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
4
DDR_A_D4 DDR_A_D5
DDR_A_DM0 DDR_A_D6
DDR_A_D7 DDR_A_D12
DDR_A_D13 DDR_A_DM1 DDR_A_CLK1
DDR_A_CLK#1 DDR_A_D14
DDR_A_D15
DDR_A_D20 DDR_A_D21
DDR_A_DM2
DDR_A_D23 DDR_A_D28
DDR_A_D29 DDR_A_DQS#3
DDR_A_DQS3 DDR_A_D30
DDR_A_D31 DDR_A_CKE1 DDR_A_MA15
DDR_A_MA14 DDR_A_MA11
DDR_A_MA7 DDR_A_MA6DDR_A_MA8
DDR_A_MA4 DDR_A_MA2 DDR_A_MA0
DDR_A_BS#1 DDR_A_RAS# DDR_A_CS0#
DDR_A_ODT0 DDR_A_MA13
DDR_A_D36 DDR_A_D37
DDR_A_DM4 DDR_A_D38
DDR_A_D39 DDR_A_D44
DDR_A_D45 DDR_A_DQS#5
DDR_A_DQS5 DDR_A_D46
DDR_A_D52
DDR_A_CLK2 DDR_A_CLK#2
DDR_A_DM6 DDR_A_D54
DDR_A_D60 DDR_A_D61
DDR_A_DQS#7 DDR_A_DQS7
DDR_A_D62 DDR_A_D63
R61 0_0402_5%
12 12
R60 0_0402_5%
DDR_A_CLK1 <5> DDR_A_CLK#1 <5>
DDR_A_CKE1 <5>
DDR_A_BS#1 <5> DDR_A_RAS# <5> DDR_A_CS0# <5>
DDR_A_ODT0 <5>
DDR_A_CLK2 <5> DDR_A_CLK#2 <5>
3
2007-01-17 Add
1
C299
2
1000P_0402_50V7K~N
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1.8V+DIMM_VREF+1.8V+1.8V
1
C281
2
0.1U_0402_16V7K~N
1
C298
2
0.1U_0402_16V7K~N
R135
1K_0402_1%
1 2
R152
1K_0402_1%
1 2
DDR_A_ODT1 DDR_A_CS1# DDR_A_WE# DDR_A_CAS#
DDR_A_MA13 DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS#
DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12
DDR_A_MA15 DDR_A_CKE1
DDR_A_BS#0 DDR_A_MA10 DDR_A_MA1 DDR_A_MA3
DDR_A_MA7 DDR_A_MA6 DDR_A_MA11 DDR_A_MA14
DDR_A_BS#1 DDR_A_MA0 DDR_A_MA4 DDR_A_MA2
DDR_A_BS#2 DDR_A_CKE0
2007/12/12 2008/12/12
RP1
18 27 36 45
47_0804_8P4R_5%
RP2
18 27 36
RP9
RP14
RP5
RP10
47_0804_8P4R_5%
RP6
RP13
45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
Deciphered Date
+1.8V
0.1U_0402_16V7K~N
2
+1.8V
0.1U_0402_16V7K~N
+0.9V
+0.9V
0.1U_0402_16V7K~N
DDR_A_D[0..63] DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] DDR_A_DQS#[0..7]
0.1U_0402_16V7K~N
1
2
C148
0.1U_0402_16V7K~N
1
2
C168
DDR_A_D[0..63]<5>
DDR_A_DM[0..7]<5>
DDR_A_DQS[0..7]<5>
DDR_A_MA[0..15]<5>
DDR_A_DQS#[0..7]<5>
+0.9V
PLACE CLOSE TO SO-DIMM1 AS POSSIBLE
1
1
2
2
0.1U_0402_16V7K~N
C151
C138
1
1
2
0.1U_0402_16V7K~N
C142
2
1
2
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
C170
C154
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
2
C136
0.1U_0402_16V7K~N
1
2
C137
1
2
0.1U_0402_16V7K~N
C139
1
1
2
2
C150
C192
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V
0.1U_0402_16V7K~N
1
1
2
2
C193
C134
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V
1
1
2
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
C194
C153
Title
DDR2 SODIMM-I Socket
Size Document Number Rev
Custom
U1 LA-4381P
Date: Sheet
0.1U_0402_16V7K~N
1
1
2
2
C190
C179
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
1
2
2
C191
C140
1
1
2
0.1U_0402_16V7K~N
C171
1
2
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
C141
C195
1
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
1
2
2
C169
C135
C217
841Wednesday, January 16, 2008
+0.9V
330U_D2E_2.5VM
1
C147
+
2
@
1
2
4.7U_0805_6.3V6K~N
0.0
of
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
1
2
2
C152
C149
1
1
C133
2
2
0.1U_0402_16V7K~N
C218
4.7U_0805_6.3V6K~N
1
5
4
3
2
1
+DIMM_VREF+1.8V+1.8V
JDIM2
1
VREF
3
DDR_B_D0
D D
C C
DDR_B_CKE0<5>
DDR_B_BS#2<5>
DDR_B_BS#0<5> DDR_B_WE#<5>
DDR_B_CAS#<5>
DDR_B_CS1#<5>
DDR_B_ODT1<5>
B B
A A
SMB_CK_DAT0<8,14,18> SMB_CK_CLK0<8,14,18>
DDR_B_D1 DDR_B_DQS#0
DDR_B_DQS0 DDR_B_D2
DDR_B_D3 DDR_B_D8
DDR_B_D9 DDR_B_DQS#1
DDR_B_DQS1 DDR_B_D10
DDR_B_D11
DDR_B_D16 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D18 DDR_B_D22 DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_DM3
DDR_B_D26 DDR_B_D27
DDR_B_CKE0
DDR_B_BS#2 DDR_B_MA12
DDR_B_MA9
DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#
DDR_B_CAS# DDR_B_CS1#
DDR_B_ODT1 DDR_B_D32
DDR_B_D33 DDR_B_DQS#4
DDR_B_DQS4 DDR_B_D34
DDR_B_D35 DDR_B_D40
DDR_B_D41 DDR_B_DM5 DDR_B_D42
DDR_B_D43 DDR_B_D47 DDR_B_D48
DDR_B_D49 DDR_B_D53
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51 DDR_B_D55
DDR_B_D56 DDR_B_D57
DDR_B_DM7 DDR_B_D58
DDR_B_D59 SMB_CK_DAT0
SMB_CK_CLK0
+3VS
5
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_AS0A426-NARN-7F~N
CONN@
REVERSE TYPE TOP SLOT
DQ4
DQ5
DM0
DQ6
DQ7
DQ12 DQ13
DM1
CK0#
DQ14 DQ15
DQ20 DQ21
DM2
DQ22 DQ23
DQ28 DQ29
DQS3#
DQS3 DQ30
DQ31
NC/CKE1
VDD NC/A15 NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
DQ36 DQ37
DM4
DQ38 DQ39
DQ44 DQ45
DQS5#
DQS5 DQ46
DQ47 DQ52
DQ53
CK1#
DM6
DQ54 DQ55
DQ60 DQ61
DQS7#
DQS7 DQ62
DQ63
SAO
VSS
VSS VSS
VSS
VSS VSS
CK0 VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A11
BA1 S0#
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS CK1
VSS VSS
VSS
VSS
VSS
VSS SA1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50
NC
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92
A7
94
A6
96 98
A4
100
A2
102
A0
104 106 108 110 112 114 116 118 120
NC
122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
4
DDR_B_D4 DDR_B_D5
DDR_B_DM0 DDR_B_D6
DDR_B_D7 DDR_B_D12
DDR_B_D13 DDR_B_DM1 DDR_B_CLK1
DDR_B_CLK#1 DDR_B_D14
DDR_B_D15
DDR_B_D20 DDR_B_D21
DDR_B_DM2
DDR_B_D23 DDR_B_D28
DDR_B_D29 DDR_B_DQS#3
DDR_B_DQS3 DDR_B_D30
DDR_B_D31 DDR_B_CKE1 DDR_B_MA15
DDR_B_MA14 DDR_B_MA11
DDR_B_MA7 DDR_B_MA6DDR_B_MA8
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0
DDR_B_BS#1 DDR_B_RAS# DDR_B_CS0#
DDR_B_ODT0 DDR_B_MA13
DDR_B_D36 DDR_B_D37
DDR_B_DM4 DDR_B_D38
DDR_B_D39 DDR_B_D44
DDR_B_D45 DDR_B_DQS#5
DDR_B_DQS5 DDR_B_D46
DDR_B_D52
DDR_B_CLK2 DDR_B_CLK#2
DDR_B_DM6 DDR_B_D54
DDR_B_D60 DDR_B_D61
DDR_B_DQS#7 DDR_B_DQS7
DDR_B_D62 DDR_B_D63
R63 4.7K_0402_5%
1 2
R62 0_0402_5%
12
DDR_B_CLK1 <5> DDR_B_CLK#1 <5>
DDR_B_CKE1 <5>
DDR_B_BS#1 <5> DDR_B_RAS# <5> DDR_B_CS0# <5>
DDR_B_ODT0 <5>
DDR_B_CLK2 <5> DDR_B_CLK#2 <5>
+3VS
1
C297
2
1000P_0402_50V7K~N
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
DDR_B_MA8 DDR_B_MA5 DDR_B_MA9 DDR_B_MA12
DDR_B_BS#0 DDR_B_MA1 DDR_B_MA10 DDR_B_MA3
DDR_B_RAS# DDR_B_MA0 DDR_B_MA2 DDR_B_MA4
DDR_B_MA13 DDR_B_ODT0 DDR_B_CS0# DDR_B_BS#1
DDR_B_ODT1 DDR_B_CS1# DDR_B_CAS# DDR_B_WE#
DDR_B_MA6 DDR_B_MA7 DDR_B_MA11 DDR_B_MA14
DDR_B_CKE0 DDR_B_BS#2
DDR_B_MA15 DDR_B_CKE1
2007/12/12 2008/12/12
DDR_B_D[0..63]<5> DDR_B_DM[0..7]<5>
DDR_B_DQS[0..7]<5> DDR_B_MA[0..15]<5>
DDR_B_DQS#[0..7]<5>
RP11
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
RP7
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
RP8
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
RP4
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
RP3
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
RP12
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
RP15
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
RP16
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
+1.8V
1
2
0.1U_0402_16V7K~N
C157
Deciphered Date
+0.9V
PLACE CLOSE TO SO-DIMM2 AS POSSIBLE
1
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
C173
2
DDR_B_D[0..63] DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_MA[0..15] DDR_B_DQS#[0..7]
+0.9V
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
1
2
2
C178
C199
0.1U_0402_16V7K~N
1
C198
2
1
1
C143
2
2
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
941Wednesday, January 16, 2008
0.0
of
1
2
C225
C155
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
1
2
2
C175
C220
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
1
0.1U_0402_16V7K~N
C177
C159
2
2
1
1
C222
2
2
0.1U_0402_16V7K~N
C176
C197
1
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
330U_D2E_2.5VM
1
C254
+
2
+1.8V
0.1U_0402_16V7K~N
1
C224
2
+0.9V
1
1
2
C174
1
2
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
C144
C223
1
1
2
2
C196
C235
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
1
C161
2
2
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V
1
1
2
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
C221
C145
Title
Size Document Number Rev
Custom
Date: Sheet
0.1U_0402_16V7K~N
1
1
2
2
C234
C158
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
1
C160
C219
2
2
1
1
2
2
0.1U_0402_16V7K~N
C156
0.1U_0402_16V7K~N
C172
0.1U_0402_16V7K~N
DDR2 SODIMM-II Socket
U1 LA-4381P
5
4
3
2
1
TMDS_B_DATA2# TMDS_B_DATA1# TMDS_B_DATA0# TMDS_B_CLK#
TMDS_B_DATA2 <16> TMDS_B_DATA2# <16> TMDS_B_DATA1 <16> TMDS_B_DATA1# <16> TMDS_B_DATA0 <16> TMDS_B_DATA0# <16> TMDS_B_CLK <16> TMDS_B_CLK# <16>
PCIE_LAN_C_TX_P0 PCIE_LAN_C_TX_N0PCIE_LAN_TX_N0 PCIE_WLAN_C_TX_P1PCIE_WLAN_TX_P1 PCIE_WLAN_C_TX_N1 PCIE_CARD_C_TX_P2 PCIE_CARD_C_TX_N2
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N
+1.1VS
SB_TX0P <17> SB_TX0N <17> SB_TX1P <17> SB_TX1N <17> SB_TX2P <17> SB_TX2N <17> SB_TX3P <17> SB_TX3N <17>
PCIE_LAN_C_TX_P0 <25> PCIE_LAN_C_TX_N0 <25> PCIE_WLAN_C_TX_P1 <24> PCIE_WLAN_C_TX_N1 <24> PCIE_CARD_C_TX_P2 <24> PCIE_CARD_C_TX_N2 <24>
H_CLKOP0<4> H_CLKON0<4> H_CLKOP1<4> H_CLKON1<4>
H_CTLOP0<4> H_CTLON0<4> H_CTLOP1<4> H_CTLON1<4>
R387 301_0402_1%
1 2
+1.1VS
H_CADIP[0..15]<4> H_CADIN[0..15]<4>
H_CADOP[0..15]<4>
H_CADON[0..15]<4>
12
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7
H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
HT_RXCALP HT_RXCALN
R405
49.9_0402_1%
@
H_CADIP[0..15]
H_CADIN[0..15] H_CADOP[0..15] H_CADON[0..15]
Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25
AC24 AC25 AB25 AB24 AA24 AA25
Y22
Y23 W21 W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23 AA22
M22 M23
R21
R20
C23
A24
12
R406
49.9_0402_1%
@
U780MA
HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N
HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N
HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N
HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N
HT_RXCALP HT_RXCALN
RS780M_FCBGA528
H_CADIP0
HT_TXCALP HT_TXCALN
D24
H_CADIN0
D25
H_CADIP1
E24
H_CADIN1
E25
H_CADIP2
F24
H_CADIN2
F25
H_CADIP3
F23
H_CADIN3
F22
H_CADIP4
H23
H_CADIN4
H22
H_CADIP5
J25
H_CADIN5
J24
H_CADIP6
K24
H_CADIN6
K25
H_CADIP7
K23
H_CADIN7
K22
H_CADIP8
F21
H_CADIN8
G21
H_CADIP9
G20
H_CADIN9
H21
H_CADIP10
J20
H_CADIN10
J21
H_CADIP11
J18
H_CADIN11
K17
H_CADIP12
L19
H_CADIN12
J19
H_CADIP13
M19
H_CADIN13
L18
H_CADIP14
M21
H_CADIN14
P21
H_CADIP15
P18
H_CADIN15
M18
H_CLKIP0
H24
H_CLKIN0
H25
H_CLKIP1
L21
H_CLKIN1
L20
H_CTLIP0
M24
H_CTLIN0
M25
H_CTLIP1
P19
H_CTLIN1
R18
HT_TXCALP
B24
HT_TXCALN
B25
Place < 100mils from pin B25 and B24Place < 100mils from pin AC8 and AB8 Place < 100mils from pin C23 and A24
PART 1 OF 6
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N
HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P HT_TXCLK0N
HYPER TRANSPORT CPU I/F
HT_TXCLK1P HT_TXCLK1N
HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N
H_CLKIP0 <4> H_CLKIN0 <4> H_CLKIP1 <4> H_CLKIN1 <4>
H_CTLIN0 <4> H_CTLIN1 <4>
R386 301_0402_1%
1 2
H_CTLIP0 <4> H_CTLIP1 <4>
TMDS_B_DATA2 TMDS_B_DATA1 TMDS_B_DATA0
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N
GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
TMDS_B_CLK
A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2
PCIE_LAN_TX_P0
AC1 AC2 AB4
PCIE_WLAN_TX_N1
AB3
PCIE_CARD_TX_P2
AA2
PCIE_CARD_TX_N2
AA1 Y1 Y2 Y4 Y3 V1 V2
SB_TX0P_C
AD7
SB_TX0N_C
AE7
SB_TX1P_C
AE6
SB_TX1N_C
AD6
SB_TX2P_C
AB6
SB_TX2N_C
AC6
SB_TX3P_C SB_TX3P
AD5
SB_TX3N_C SB_TX3N
AE5 AC8
AB8
D D
C C
PCIE_LAN_C_RX_P0<25> PCIE_LAN_C_RX_N0<25> PCIE_WLAN_C_RX_P1<24> PCIE_WLAN_C_RX_N1<24> PCIE_CARD_C_RX_P2<24> PCIE_CARD_C_RX_N2<24>
SB_RX0P<17> SB_RX0N<17> SB_RX1P<17> SB_RX1N<17> SB_RX2P<17> SB_RX2N<17> SB_RX3P<17> SB_RX3N<17>
B B
PCIE_LAN_C_RX_P0 PCIE_LAN_C_RX_N0 PCIE_WLAN_C_RX_P1 PCIE_WLAN_C_RX_N1 PCIE_CARD_C_RX_P2 PCIE_CARD_C_RX_N2
SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N
U780MB
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS780M_FCBGA528
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)
1 2
R389 10_0402_5%@
1 2
R390 10_0402_5%@
1 2
R105 10_0402_5%@
1 2
R388 10_0402_5%@
TMDS_B_DATA2 TMDS_B_DATA2# TMDS_B_DATA1 TMDS_B_DATA1# TMDS_B_DATA0 TMDS_B_DATA0# TMDS_B_CLK TMDS_B_CLK#
C547 0.1U_0402_16V7K~N C546 0.1U_0402_16V7K~N C182 0.1U_0402_16V7K~N C183 0.1U_0402_16V7K~N C548 0.1U_0402_16V7K~N C558 0.1U_0402_16V7K~N
C532 0.1U_0402_16V7K~N
1 2
C533 0.1U_0402_16V7K~N
1 2
C535 0.1U_0402_16V7K~N
1 2
C534 0.1U_0402_16V7K~N
1 2
C537 0.1U_0402_16V7K~N
1 2
C536 0.1U_0402_16V7K~N
1 2
C542 0.1U_0402_16V7K~N
1 2
C538 0.1U_0402_16V7K~N
PCE_PCAL PCE_NCAL
1 2
R85 1.27K_0402_1%
1 2
R84 2K_0402_1%
1 2
1 2 1 2 1 2 1 2 1 2 1 2
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/12/12 2008/12/12
Deciphered Date
Title
Size Document Number Rev
Custom
U1 LA-4381P
2
Date: Sheet
RS780MC HT / PCIE / DVI
1
10 41Wednesday, January 16, 2008
0.0
of
+3VS +3VS
12
R431 3K_0402_5%
VGA_CRT_VSYNC
Pull-up: Disable Debug Port
+1.1VS
L53
L16
L12
L10
12 12
CLK_NB_REFCLK
12
2
1
15mil
15mil
15mil
15mil
EDID_CLK_LCD EDID_DAT_LCD
+1.8VS
+1.8VS
+1.8VS
+3VS
R415
33_0402_5%
C577
22P_0402_50V8J
+3VS
R116 10K_0402_5%
1 2
NB_STRAP_DATA
12
+1.1VS
1K_0402_1%
1 2
1K_0402_1%
1 2
1 2
FCM2012C-800_0805
1 2
FCM2012C-800_0805
1 2
FCM2012C-800_0805
1 2
FCM2012C-800_0805
R412 4.7K_0402_5% R414 4.7K_0402_5%
@
@
R117 2K_0402_5%
@
R378
NB_REFCLK_N
R377
+NB_PLLVDD
1
C576
2.2U_0603_10V6K
2
+NB_PLLVDD18
1
C268
2.2U_0603_10V6K
2
+NB_PCIEPLL
1
C255
2.2U_0603_10V6K
2
+NB_HTPLL
1
C233
2.2U_0603_10V6K
2
SB_PWRGD<6,18,28>
12
R108 3K_0402_5%
VGA_CRT_HSYNC
Pull-up: Disable Side Port Memory
SB_PWRGD
12
R155
10K_0402_5%
1 2
R101 150_0402_1%
1 2
R110 150_0402_1%
1 2
R111 150_0402_1%
VGA_DDC_CLK<15>
EDID_CLK_LCD<15> EDID_DAT_LCD<15>
+5VS
R140 10K_0402_5%
1 2
SB_PWRGD#
13
D
2
G
S
+3VS
1 2
FCM2012C-800_0805
+1.8VS
0_0603_5%
+1.8VS
1 2
FCM2012C-800_0805
VGA_DDC_CLK
+1.8VS
12
13
2
G
Q22
SSM3K7002FU_SC70-3
L13
2.2U_0603_10V6K
R407
1 2
2.2U_0603_10V6K
L54
2.2U_0603_10V6K
VGA_CRT_G VGA_CRT_B
R99 0_0402_5%
EDID_CLK_LCD EDID_DAT_LCD
HDMICLK_UMA<16> HDMIDAT_UMA<16>
R410 300_0402_5%
NB_PWRGD
D
Q14
SSM3K7002FU_SC70-3
S
@
+AVDD
1
C262
2
+AVDDDI
1
C267
2
+AVDDQ
1
C565
2
VGA_CRT_HSYNC<15> VGA_CRT_VSYNC<15>
1 2
VGA_DDC_DATA<15>
NB_RST#<17,23,24,25,28>
CLK_HTREFCLKP<14> CLK_HTREFCLKN<14>
CLK_NB_REFCLK<14>
CLK_NB_GFX_CLKP<14> CLK_NB_GFX_CLKN<14>
CLK_SBLINKCLK<14> CLK_SBLINKCLK#<14>
R413 0_0402_5%
1 2
NB_STRAP_DATA<38>
12
R4090_0402_5%
15mil
VGA_CRT_R<15> VGA_CRT_G<15> VGA_CRT_B<15>
VGA_CRT_HSYNC VGA_CRT_VSYNC VGA_DDC_CLK_NB VGA_DDC_DATA
R100 715_0402_1%
1 2
+NB_PLLVDD +NB_PLLVDD18
+NB_HTPLL +NB_PCIEPLL
NB_RST# NB_PWRGD NB_LDTSTOP# NB_ALLOW_LDTSTOP
CLK_HTREFCLKP CLK_HTREFCLKN
CLK_NB_REFCLK NB_REFCLK_N
CLK_NB_GFX_CLKP CLK_NB_GFX_CLKN
CLK_SBLINKCLK CLK_SBLINKCLK#
EDID_CLK_LCD_NB
NB_STRAP_DATA
1 2
R104 150_0402_1%@
NB_PWRGD_SB <18>
LDT_STOP#<6,17>
15mil
15mil
U780MC
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
VGA_CRT_RVGA_CRT_R VGA_CRT_G VGA_CRT_B
CPU_LDT_REQ#<6,17>
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_CLK0/AUX0P(NC)
A8
DDC_DATA0/AUX0N(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS780M_FCBGA528
+1.8VS
12
@
R156
4.7K_0402_5%
G
2
@
13
D
S
BSS138_NL_SOT23-3
Q18
R141 0_0402_5%
+3VS
12
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PART 3 OF 6
TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
PM
CLOCKs PLL PWR
MIS.
+1.8VS
12
R143
4.7K_0402_5%
@
G
2
13
D
S
@
Q19 BSS138_NL_SOT23-3
R144 0_0402_5%
12
R408
4.7K_0402_5%
@
NB_LDTSTOP#LDT_STOP#
2007/12/12 2008/12/12
TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U2P(NC) TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
VDDLTP18(NC) VSSLTP18(NC)
VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)
VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
TMDS_HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P THERMALDIODE_N
TESTMODE
+3VS
12
R142
@
4.7K_0402_5%
NB_ALLOW_LDTSTOPCPU_LDT_REQ#
12
Deciphered Date
HPD(NC)
A22 B22 A21 B21 B20 A20 A19 B19
B18 A18 A17 B17 D20 D21 D18 D19
B16 A16 D16 D17
A13 B13
A15 B15 A14 B14
C14 D15 C16 C18 C20 E20 C22
E9 F7 G12
D9 D10
D12 AE8
AD8 D13
LVDSL0+ LVDSL0­LVDSL1+ LVDSL1­LVDSL2+ LVDSL2-
LVDSU0+ LVDSU0­LVDSU1+ LVDSU1­LVDSU2+ LVDSU2-
LVDSLC+ LVDSLC­LVDSUC+ LVDSUC-
ENVDD_NB ENABLT_NB
SB_SUS_STAT#
12
+LPVDD
+LVDDR18D
+LVDDR33A
R109
1.8K_0402_5%
LVDSL0+ <15> LVDSL0- <15> LVDSL1+ <15> LVDSL1- <15> LVDSL2+ <15> LVDSL2- <15>
LVDSU0+ <15> LVDSU0- <15> LVDSU1+ <15> LVDSU1- <15> LVDSU2+ <15> LVDSU2- <15>
LVDSLC+ <15> LVDSLC- <15> LVDSUC+ <15> LVDSUC- <15>
0.1U_0402_16V7K~N
R106 0_0402_5%
12
R98 0_0402_5%
12
HPD <16>
R439 0_0402_5%@
12
R363 0_0402_5%
12
R362 0_0402_5%
12
12
R411 3K_0402_5%
NB_PWRGD
SSM3K7002FU_SC70-3
L19
1 2
FCM2012C-800_0805
1
C269
2.2U_0603_10V6K
2
1
C257
2
1
C261
2.2U_0603_10V6K
2
R107
1.27K_0402_1%
+5VS
@
2
G
Q13
Title
Size Document Number Rev
Custom
Date: Sheet
1 2
FCM2012C-800_0805
1
C263
4.7U_0805_6.3V6K~N
2
1 2
FCM2012C-800_0805
12
1.27K_0402_1%
SUS_STAT# <18> SB_NB_THRMDA <19>
SB_NB_THRMDC <19>
ENVDD_NB
R139
10K_0402_5%
1 2
NB_PWRGD5V#
13
D
ENABLT_NB
@
S
AP2301GN 1P SOT23
U1 LA-4381P
L14
L11
ENVDD ENABLT
R97
+1.8VS
0.08A
15mil
+3VS
0.22A
@
12
Q12 AP2301GN 1P SOT23
S
G
G
S
Q21
@
2
2
@
15mil
ENVDD <15> ENABLT <15,28>
D
ENVDD
13
12
R122
1K_0402_5%
@
ENABLT
13
D
12
R154
1K_0402_5%
RS780MC VIDEO_IF/CLOCK GEN
of
11 41Wednesday, January 16, 2008
0.0
5
+1.1VS
0.6A
D D
C C
FBMA-L11-322513-201LMA40T_1210
FBMA-L11-322513-201LMA40T_1210
0.45A
FBMA-L11-322513-201LMA40T_1210
For A11, This VTTHTTX power plane should connect to +1.35VS.
0.5A
FBMA-L11-322513-201LMA40T_1210
+1.8VS
1 2
+1.1VS
1 2
+1.2V_HT
1 2
L49
1 2
C531
R382
1 2
0_0603_5%
L17
L18
L4
0.25A
C575
C574
1
C164
2
4.7U_0805_6.3V6K~N
1
C256 1U_0402_6.3V6K
2
C167
+VDDHT
1
C246
2
4.7U_0805_6.3V6K~N
+VDDHTRX
1
C250
2
4.7U_0805_6.3V6K~N
+VDDHTTX
1
C212
2
4.7U_0805_6.3V6K~N
+VDDA18PCIE
1
C241
2
4.7U_0805_6.3V6K~N
+VDD18
1
C248
2
0.1U_0402_16V7K~N
1
C259
2
0.1U_0402_16V7K~N
1
C186
2
0.1U_0402_16V7K~N
1
C207
2
0.1U_0402_16V7K~N
1
1
C232
2
0.1U_0402_16V7K~N
1
C249
2
0.1U_0402_16V7K~N
1
C187
2
0.1U_0402_16V7K~N
1
C184
2
0.1U_0402_16V7K~N
1
C211
2
2
0.1U_0402_16V7K~N
1
1
C258
2
2
0.1U_0402_16V7K~N
1
1
C166
2
2
0.1U_0402_16V7K~N
1
1
C185
2
2
0.1U_0402_16V7K~N
0.005A
+1.8VS
R80
1 2
0_0603_5%
0.005A
+VDD18_MEM
1
C165 1U_0402_6.3V6K
2
@
4
U780ME
J17
VDDHT_1
K16 L16
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
M16
G19
AE25 AD24 AC23 AB22 AA21
W19
M17
M10
AA9 AB9 AD9 AE9
AE11 AD11
P16 R16 T16
H18 F20
E21 D22 B23 A23
Y20 V18
U17 T17 R17 P17
J10 P10 K10
L10
W9
H9 T10 R10
Y9
U10
F9
G9
PART 5/6
VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7
VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7
VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13
VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15
VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)
RS780M_FCBGA528
VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
POWER
VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)
VDD33_1(NC) VDD33_2(NC)
VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8 VDDPCIE_9
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8
VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22
A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16
AE10 AA11 Y11 AD10 AB10 AC10
H11 H12
C209
C240
C243
3
+VDDPCIE
1
1
1
C205
C204
2
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
1
C206
2
C266
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C229
2
2
10U_0805_6.3V6M
4.7U_0805_6.3V6K~N
300mil
1
1
1
C230
2
C247
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
+VDD33
1
1
C242
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C208
C244
2
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1
1
C245
C231
2
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
R381
1 2
0_0603_5%
2
+1.1VS
L15
0.1U_0402_16V7K~N
+3VS
C560
0.7A
1.0V-1.1V 7A
+NB_CORE
1
C210
2
22U_0805_6.3VAM
1
2
1 2
FBMA-L11-322513-201LMA40T_1210
1
2
0.03A
C203
22U_0805_6.3VAM
1
U780MF
A25
VSSAHT1
D23 E22 G22 G24 G25 H19
J22 L17 L22 L24 L25
M20
N22 P20 R19 R22 R24 R25 H20 U22
330U_X_2VM_R6M
W22 W24 W25
AD25
M14
W11
W15 AC12 AA14
AB11 AB15 AB17 AB19 AE20 AB21
V19
Y21
L12
N13 P12 P15 R11 R14 T12 U14 U11 U15 V12
Y18
K11
1
+
2
PART 6/6
VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27
VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34
RS780M_FCBGA528
VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30
GROUND
VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40
VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8 VSSAPCIE9
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9
VSS10
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2
AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15
B B
RS740/RX780/RS780 POWER DIFFERENCE TABLE
PIN NAME VDDHT VDDHTRX VDDHTTX VDDA18PCIE
VDD18_MEM VDDPCIE VDDC VDD_MEM VDDG33
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/12/12 2008/12/12
IOPLLVDD18
RS740
NC
+1.2V NC +1.8V NC NC +1.2V +1.1V +1.1V +1.2V
+1.8V/1.5V
+3.3V +1.8V +1.8VNC
RX780
+1.1V +1.1V +1.2V +1.8V +1.8VVDDG18 NC
+1.1V NC NC
+1.8V/1.5V
Deciphered Date
2
RS780
+1.1V +1.1V +1.2V +1.8V +1.8V +1.8V
+1.1V
+3.3V
PIN NAME IOPLLVDD
AVDDDI AVDDQ PLLVDD PLLVDD18
VDDA18HTPLL VDDLTP18 VDDLT18 VDDLT33
RS740 RX780 RS780
+1.2V +3.3V NC
+1.2V +1.8V +1.2VVDDA18PCIEPLL +1.8V +1.8V +1.8V +3.3V
Title
Size Document Number Rev Custom
U1 LA-4381P
Date: Sheet
NC
+1.1V
+3.3VAVDDNC NC+1.8V +1.8V NC+1.8V +1.8V
+1.1V NC
+1.8V +1.8V
+1.8V +1.8V
+1.8V
+1.8V
NC NC
+1.8V NC
NC
RS780MC Power/GND
1
0.0
of
12 41Wednesday, January 16, 2008
2
B B
1
U780MD
MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)
MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)
MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)
MEM_CKP(NC) MEM_CKN(NC)
MEM_COMPP(NC) MEM_COMPN(NC)
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC) MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21
Y17 W18 AD20 AE21
W17 AE19
AE23
VDD_MUX_IOPLLVDD
AE24 AD23 AE18
1
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
L47
0_0402_5%
C529
2.2U_0603_10V6K
@
2007/12/12 2008/12/12
+1.8V_IOPLLVDD
12
+1.1VS
1
C528 0.1U_0402_16V7K~N
2
Deciphered Date
0_0402_5%
1
C530
2.2U_0603_10V6K
2
@
+1.8VS
L48
12
1
Title
Size Document Number Rev
Custom
U1 LA-4381P
Date: Sheet
RS780MC Power/GND
13 41Wednesday, January 16, 2008
of
0.0
AB12 AE16
V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14
Y14 AD16
AE17 AD17
W12
Y12 AD18 AB13 AB18
A A
2
V14
V15
W14
AE12 AD12
RS780M_FCBGA528
Loading...
+ 28 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use