Acer LA-4381P Schematics

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1 1

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D

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U1 - KAL00

2 2

Compal Confidential

Schematics Document

AMD S1g2/ ATI RS780M / SB700

3 3

4 4

A

B

Wednesday, January 16, 2008

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Cover Sheet

Size Document Number Rev

Custom

U1 LA-4381P

D

Date: Sheet

E

141

0.0

of

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B

C

D

E

Compal confidential

Project Code: ANRKAL0000(KAL00)
File Name : LA-4381P
PCB P/N:

1 1

ZZZ1

15W_PCB

Thermal Sensor
ADM1032ARM

page 6 page 14

CRT

page 15

LCD CONN

page 15

HDMI CONN

page 16

Clock Generator
SLG8SP626VTR

/ICS9LPRS476BKLFT

PCI EXPRESS

Turion64 x2 TLxx / Sempron

AMD S1g2 CPU

page 4,5,6,7

HT 16x16 1.6G~3.2GHZ

ATI-RS780M

page 10,11,12,13

A-Link Express

4 x PCIE

DDR-2 DDR2-SO-DIMM X2

Daul Channel DDR-2
Up to 800MHz

BUS A-->JDIM2-->UPPER SLOT
BUS B-->JDIM1-->LOWER SLOT

page 8,9

2 2

Broadcom

BCM5784M

page 25

Express Card
(New Card)

page 24

Mini Card
WLAN

page 24

ATI-SB700

HD-Interface

USB 2.0

RJ45 CONN

page 26

PCI BUS

page 17,18,19,20,21

USB 2.0
IDE

Audio CKT
ALC269

USB conn x 4
Felica Conn

Hyper Flash

page 27

page 32

page 31

page 23

Audio Jack

page 28

Crad Reader Controller

Ricoh R5C833

page 22

3 3

Media Card

page 22

Power On/Off CKT.

page 33

LPC BUS

SATA GEN2

SATA GEN2

SATA ODD Conn.

page 23

SATA HDD Conn.

page 23

ENE KB926

DC/DC Interface CKT.

page 34

Power Circuit DC/DC

4 4

page 35~42

RTC CKT.

page 17

Power OK CKT.

page 33

Touch Pad
CONN.

page 31

page 29

Int. KBD

page 31

SPI BIOS

page 29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Block Diagrams

Size Document Number Rev

Custom

U1 LA-4381P

D

Date: Sheet

E

241Wednesday, January 16, 2008

0.0

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Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+
+CPU_CORE0,1
+VDDNB +0.8V~1.1V CPU NBVDD ON ON OFF
+1.2V_HT
+0.9V 0.9V switched power rail for DDR terminator
+1.2VALW 1.2V always on power rail ONON
+1.5VS
+1.8VS 1.8V switched power rail
+1.8V
+3VALW
+3VS
+5VALW 5V always on power rail
+5VS
+RTCVCC RTC power

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2V switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V switched power rail

5V switched power rail

B

S1 S3 S4/ S5

ON ON ON

ON OFF

ON OFF OFF
ON OFF
ON
ON OFF OFF
ON OFF OFF
ON OFFON
ON
ON
ON

ON ONON

ONONON
OFF

ON

ON ON
OFF

OFF
ON ON
OFF

OFFON

C

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

LOW LOW LOW LOW

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

D

SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

OFF

OFF

V

AD_BID

ON ON

ON

OFF

OFF

OFF

max

LOW

OFF

OFF

OFF

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

V typ

AD_BID

ON

ON

ON

ON

ON

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

E

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus

AD21

0

PIRQE/PIRQF/PIRQG

BOARD ID Table

Board ID

0
1
2
3
4

PCB Revision

0.1 (U1 ES1)

0.2 (U1 ES2)

0.3 (U1 PP)

0.4 (U1 PPR)

1.0 (U1 IRT)

BTO Item BOM Structure

BTO Option Table

5
6
7

EC SM Bus1 address

3 3

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b?
1011 000Xb?

EC SM Bus2 address

Device

ADM1032

1001 110X b?0001 011X b?

SB700 SM Bus address

Device

Clock Generator (
ICS9LPRS476BKLFT)

DDRII DIMM0
DDRII DIMM1

4 4

Address

1101 001Xb?

1001 000Xb?
1001 010Xb?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Notes

Size Document Number Rev

Custom

U1 LA-4381P

D

Date: Sheet

E

341Wednesday, January 16, 2008

0.0

of

5

4

3

2

1

HT LINK

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1
L0_CTLOUT_H0

L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

<BOM Strucrure>

H_CADOP[0..15]
H_CADON[0..15]

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

H_CADOP[0..15] <10>H_CADIP[0..15]<10>
H_CADON[0..15] <10>H_CADIN[0..15]<10>

+1.2V_HT

1

AE2
AE3
AE4
AE5

H_CADOP0

AD1

H_CADON0

AC1

H_CADOP1

AC2

H_CADON1

AC3

H_CADOP2

AB1

H_CADON2

AA1

H_CADOP3

AA2

H_CADON3

AA3

H_CADOP4

W2

H_CADON4

W3

H_CADOP5

V1

H_CADON5

U1

H_CADOP6

U2

H_CADON6

U3

H_CADOP7

T1

H_CADON7

R1

H_CADOP8

AD4

H_CADON8

AD3

H_CADOP9

AD5

H_CADON9

AC5

H_CADOP10

AB4

H_CADON10

AB3

H_CADOP11

AB5

H_CADON11

AA5

H_CADOP12

Y5

H_CADON12

W5

H_CADOP13

V4

H_CADON13

V3

H_CADOP14

V5

H_CADON14

U5

H_CADOP15

T4

H_CADON15

T3

H_CLKOP0

Y1

H_CLKON0

W1

H_CLKOP1

Y4

H_CLKON1

Y3

H_CTLOP0H_CTLIP0

R2

H_CTLON0

R3

H_CTLOP1

T5

H_CTLON1H_CTLIN1

R5

C523

H_CLKOP0 <10>
H_CLKON0 <10>
H_CLKOP1 <10>
H_CLKON1 <10>

H_CTLON0 <10>
H_CTLOP1 <10>
H_CTLON1 <10>

2

4.7U_0805_6.3V6K~N

C543

close to CPU Socket

1

C544

2

4.7U_0805_6.3V6K~N

1

1

1

C539

C522

2

2

0.22U_0603_10V7K

4.7U_0805_6.3V6K~N

1

C521

C526

2

2

0.22U_0603_10V7K
180P_0402_50V8J~N

FAN1 Control and Tachometer

EN_DFAN1<28>

FAN_SPEED1<28>

1

2

180P_0402_50V8J~N

EN_DFAN1

R364

10K_0402_5%

1SS355TE-17_SOD323-2 @

10U_0805_10V4Z~N

1000P_0402_50V7K~N

+3VS

12

2

C540

0.01U_0402_16V7K

1

+5VS

12

D27

@

12

D26 BAS16_SOT23-3

C541

12

+5VS

@

C527

12

@

FAN1_POWER

40mil

@

1 2

C545 10U_0805_10V4Z~N
U25

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8
JFAN1

1
2
3

4

G

5

G

ACES_85205-0300N~N

CONN@

FAN1

GND
GND
GND
GND

8
7
6
5

H_CADIP[0..15]
H_CADIN[0..15]

+1.2V_HT

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

H_CTLIN0
H_CTLIP1

1.5A

D1

VLDT_A0

D2

VLDT_A1

D3

VLDT_A2

D4

VLDT_A3

E3

L0_CADIN_H0

E2

L0_CADIN_L0

E1

L0_CADIN_H1

F1

L0_CADIN_L1

G3

L0_CADIN_H2

G2

L0_CADIN_L2

G1

L0_CADIN_H3

H1

L0_CADIN_L3

J1

L0_CADIN_H4

K1

L0_CADIN_L4

L3

L0_CADIN_H5

L2

L0_CADIN_L5

L1

L0_CADIN_H6

M1

L0_CADIN_L6

N3

L0_CADIN_H7

N2

L0_CADIN_L7

E5

L0_CADIN_H8

F5

L0_CADIN_L8

F3

L0_CADIN_H9

F4

L0_CADIN_L9

G5

L0_CADIN_H10

H5

L0_CADIN_L10

H3

L0_CADIN_H11

H4

L0_CADIN_L11

K3

L0_CADIN_H12

K4

L0_CADIN_L12

L5

L0_CADIN_H13

M5

L0_CADIN_L13

M3

L0_CADIN_H14

M4

L0_CADIN_L14

N5

L0_CADIN_H15

P5

L0_CADIN_L15

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

FOX_PZ6382A-284S-41F_TURION

JCPU1A

D D

C C

H_CLKIP0<10>
H_CLKIN0<10>
H_CLKIP1<10>
H_CLKIN1<10>

H_CTLIP0<10> H_CTLOP0 <10>
H_CTLIN0<10>
H_CTLIP1<10>
H_CTLIN1<10>

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Griffin HT I/F & FAN

U1 LA-4381P

1

0.0

of

441Wednesday, January 16, 2008

A

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED

ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+0.9V

0.75A

D10

KEEP TRACE TO RESISTORS

4 4

3 3

2 2

LESS THAN 1" FROM CPU PIN

+1.8V

R346 39.2_0603_1%

1 2

R353 39.2_0603_1%

1 2

DDR_A_ODT0<8>
DDR_A_ODT1<8>

DDR_A_CS0#<8>
DDR_A_CS1#<8>

DDR_A_CKE0<8>
DDR_A_CKE1<8>

DDR_A_CLK1<8>

DDR_A_CLK#1<8>

DDR_A_CLK2<8>

DDR_A_CLK#2<8>

DDR_A_MA[15..0]<8>

DDR_A_BS#0<8>
DDR_A_BS#1<8>
DDR_A_BS#2<8>

DDR_A_RAS#<8>
DDR_A_CAS#<8>
DDR_A_WE#<8>

DDR_A_CLK2

DDR_A_CLK#2
DDR_A_CLK1

DDR_A_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

M_ZP
M_ZN

TP22

TP8
TP7

TP11
TP12

TP10
TP13

1

2

1

2

DDR_A_ODT0
DDR_A_ODT1

DDR_A_CS0#
DDR_A_CS1#

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CLK1
DDR_A_CLK#1
DDR_A_CLK2
DDR_A_CLK#2

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

C80

1.5P 50V F NPO 0402

C125

1.5P 50V F NPO 0402

AD10
AF10

AE10

AA16

C10
B10

H16
T19

V22
U21
V19

T20
U19
U20
V20

J22
J20

N19
N20
E16
F16
Y16

P19
P20

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

R20
R23

J21

R19
T22
T24

B

JCPU1B

VTT1

MEM:CMD/CTRL/CLK

VTT2
VTT3
VTT4

MEMZP
MEMZN

RSVD_M1
MA0_ODT0

MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

MA_CKE0
MA_CKE1

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_BANK0
MA_BANK1
MA_BANK2

MA_RAS_L
MA_CAS_L
MA_WE_L

FOX_PZ6382A-284S-41F_TURION

DDR_B_CLK2

DDR_B_CLK#2
DDR_B_CLK1

DDR_B_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

VTT_SENSE

MB0_ODT0
MB0_ODT1
MB1_ODT0

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3

MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_RAS_L
MB_CAS_L

<BOM Strucrure>

VTT5
VTT6
VTT7
VTT8
VTT9

MEMVREF

RSVD_M2

MB_CKE0
MB_CKE1

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9

MB_WE_L

1

C520

1.5P 50V F NPO 0402

2

1

C549

1.5P 50V F NPO 0402

2

W10
AC10
AB10
AA10
A10

Y10
W17
B18
W26

W23
Y26

V26
W25
U22

J25
H26

P22
R22
A17
A18
AF18
AF17
R26
R25

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

R24
U26
J26

U25
U24
U23

R64

1 2

0_0402_5%

DDR_B_ODT0
DDR_B_ODT1

DDR_B_CS0#
DDR_B_CS1#

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CLK1
DDR_B_CLK#1
DDR_B_CLK2
DDR_B_CLK#2

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

+CPU_M_VREF

TP47

TP5

TP15
TP14

TP9
TP16

VTT_SENSE_FB

DDR_B_ODT0 <9>
DDR_B_ODT1 <9>

DDR_B_CS0# <9>
DDR_B_CS1# <9>

DDR_B_CKE0 <9>
DDR_B_CKE1 <9>

DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>
DDR_B_CLK2 <9>
DDR_B_CLK#2 <9>

DDR_B_MA[15..0] <9>

DDR_B_BS#0 <9>
DDR_B_BS#1 <9>
DDR_B_BS#2 <9>

DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>

C

D

E

Processor DDR2 Memory Interface

JCPU1C

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5

TP6

To reverse SODIMM socket (TOP)

DDR_B_DM[7..0]<9>

DDR_B_DQS0<9>
DDR_B_DQS#0<9>
DDR_B_DQS1<9>
DDR_B_DQS#1<9>
DDR_B_DQS2<9>
DDR_B_DQS#2<9>
DDR_B_DQS3<9>
DDR_B_DQS#3<9>
DDR_B_DQS4<9>
DDR_B_DQS#4<9>
DDR_B_DQS5<9>
DDR_B_DQS#5<9>
DDR_B_DQS6<9>
DDR_B_DQS#6<9>
DDR_B_DQS7<9>
DDR_B_DQS#7<9>

DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11

AE14
AF14
AF11
AD11

AB26
AE22
AC16
AD12

AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24

Y11

A12
B16
A22
E25

C12
B12
D16
C16
A24
A23
F26
E26

MEM:DATA

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

FOX_PZ6382A-284S-41F_TURION

<BOM Strucrure>

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

E12
C15
E19
F24
AC24
Y19
AB16
Y13

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

DDR_A_D[63..0] <8>DDR_B_D[63..0]<9>

To reverse SODIMM socket (Bottom)

DDR_A_DM[7..0] <8>

DDR_A_DQS0 <8>
DDR_A_DQS#0 <8>
DDR_A_DQS1 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS2 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS3 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS4 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS5 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS6 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS7 <8>
DDR_A_DQS#7 <8>

+1.8V

1

R65

1K_0402_1%

1 2

1 1

R66

1K_0402_1%

1 2

C82

+CPU_M_VREF

2

0.1U_0402_16V7K~N

1

1

C94

C81

2

2

0.1U_0402_16V7K~N

LAYOUT:PLACE CLOSE TO CPU

A

1000P_0402_50V7K~N

Place between CPU to DDR area(Reserved for EMI)

+1.8V

1

C119

2

0.1U_0402_16V7K~N

1

C106

2

0.1U_0402_16V7K~N

B

1

C118

2

1

C132

2

1

2

0.1U_0402_16V7K~N

1

2

0.1U_0402_16V7K~N

1

C104

0.1U_0402_16V7K~N

C97

0.1U_0402_16V7K~N

C96

2

0.1U_0402_16V7K~N

1

C105

2

0.1U_0402_16V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

D

Title

Griffin DDRII MEMORY I/F

Size Document Number Rev

Custom

U1 LA-4381P

Date: Sheet

E

541Wednesday, January 16, 2008

of

0.0

R103
0_0805_5%

+3VALW

+3VS +2.5VDDA

R102 0_0805_5%

1U_0603_10V6K

D D

SYSON#<32,39>

+1.8VS

C C

LDT_RST#<17>

CPU_PWRGD<17>

LDT_STOP#<11,17>

CPU_LDT_REQ#<11,17>

B B

CPU_DBREQ#

A A

CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

5

@

12
12

2

1

C251

R112

470_0402_5%

SYSON#

2

G

1 2

R367 300_0402_5%

1 2

C557 0.01U_0402_16V7K@

1 2

R74 300_0402_5%

1 2

C122 0.01U_0402_16V7K@

1 2

R123 300_0402_5%

1 2

C276 0.01U_0402_16V7K@

1 2

R90 300_0402_5%

1 2

C188 0.01U_0402_16V7K@

+1.8V

R358220_0402_5%@

R359220_0402_5%@

R357220_0402_5%@

R356220_0402_5%@

12

12

12

12

5

U6

1

IN

OUT

2

GND
SHDN3BYP

G914E_SOT23-5

12

13

D

Q10
SSM3K7002FU_SC70-3

S

@

1 2

R145 0_0402_5%

1 2

R366 0_0402_5%

1 2

R371 0_0402_5%

1 2

R77 0_0402_5%

1 2

R91 0_0402_5%

R360300_0402_5%

12

C260

0.01U_0402_16V7K

CPU_ALL_PWROK

CPU_LDTSTOP#

CPU_HT_RESET#

CPU_LDT_REQ#_CPU

CPU_HT_RESET#

CPU_ALL_PWROK
CPU_PWRGD_SVID_REG

CPU_LDTSTOP#

CPU_LDT_REQ#_CPU

HDT Connector

CONN@

5

2

4

C252
1U_0603_10V6K

1

1

2

J12OPEN PADS

1 2

JDB1

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

place them to CPU within 1.5"

CPU_PWRGD_SVID_REG <40>

+2.5VDDA

150U_D2_6.3VM

CLK_CPUCLK0_H<14>

CLK_CPUCLK0_L<14>

+3VS

+1.8V

+1.8V

HDT_RST#

4

C253

R193

390_0402_5%

CPU_SID

R217

390_0402_5%

CPU_SIC

U23

4

Y

4

1

+

2

20K_0402_5%

12

12

+3VS

5

P

B
A

G

3

LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

LQG21F4R7N00_0805

1 2

L8

4.7U_0805_6.3V6K~N

1 2

C555

169_0402_1%

1 2

C556 3900P_0402_50V7K

CPU_VDD0_RUN_FB_H<40>
CPU_VDD0_RUN_FB_L<40>

CPU_VDD1_RUN_FB_H<40>
CPU_VDD1_RUN_FB_L<40>

R189

12

S

Q25 FDV301N_NL_SOT23-3

S

Q27 FDV301N_NL_SOT23-3

LDT_RST#

2
1

NC7SZ08P5X_NL_SC70-5@

3900P_0402_50V7K

12

R365

+1.2V_HT

TP4

TP21
TP27

TP25
TP2

TP46
TP45
TP44

TP1
TP43

TP3

1 2

C355 0.1U_0402_16V4Z

R190

12

34.8K_0402_1%~N

G

2

13

D

G

2

13

D

0.25A

1

C213

2

3300P_0402_50V7K

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_LDT_REQ#_CPU

CPU_SIC
CPU_SID
CPU_ALERT#

R67 44.2_0402_1%

1 2

R68 44.2_0402_1%

1 2

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

CPU_TEST23_TSTUPD
CPU_TEST18_PLLTEST1

CPU_TEST19_PLLTEST0
CPU_TEST25_H_BYPASSCLK_H

CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN

CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN

R81 0_0402_5%

CPU_TEST6_DIECRACKMON

1

C189

2

1 2

1

C214

0.22U_0603_10V7K

2

2.09V for Gate

EC_SMB_DA1 <28,34>

EC is PU to 5VALW

EC_SMB_CK1 <28,34>

SB_PWRGD <11,18,28>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+VDDA_CPU

+VDDA_CPU

CPU_HTREF0
CPU_HTREF1

FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V

Issued Date

3

+1.8V

R76

1 2
2

@

3 1

@

M11
W18

CPU_SVC

A6

CPU_SVD

A4

CPU_THERMTRIP#_R

AF6

CPU_PROCHOT#_1.8

AC7

CPU_MEMHOT#_1.8V

AA8

THERMDC_CPU

W7

THERMDA_CPU

W8

W9
Y9

H6
G6

E10
AE9

J7
H8

D7
E7
F7
C7

C3
K8

C4

C9
C8

H18
H19
AA7
D5
C5

+3VS

10K_0402_5%

R361

4.7K_0402_5%

Q9

@

1 2

CPU_DBREQ#
CPU_TDO

CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N

CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0

CPU_TEST7_ANALOG_T
CPU_TEST10_ANALOGOUT

CPU_TEST8_DIG_T

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

THERMDA_CPU

THERMDC_CPU

EC_SMB_CK2<28>
EC_SMB_DA2<28>

CPU_ALERT#

F8
F9

A9
A8

B7
A7

F10

C6

AF4
AF5

AE6

R6
P6

F6
E6

Y6

AB6

G10

AA9
AC9
AD9
AF9

AD7
H10

G9

E9
E8

AB8
AF7
AE7
AE8
AC8
AF8

C2

AA6

A3
A5
B3
B5
C1

JCPU1D

VDDA1
VDDA2

CLKIN_H
CLKIN_L

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

SIC
SID
ALERT_L

HT_REF0
HT_REF1

VDD0_FB_H
VDD0_FB_L

VDD1_FB_H
VDD1_FB_L

DBRDY
TMS
TCK
TRST_L
TDI

TEST23
TEST18

TEST19
TEST25_H

TEST25_L
TEST21

TEST20
TEST24
TEST22
TEST12
TEST27

TEST9
TEST6

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

FOX_PZ6382A-284S-41F_TURION

CONN@

THERMTRIP_L

VDDNB_FB_H
VDDNB_FB_L

+1.8V

12

R75

KEY1
KEY2

PROCHOT_L

MEMHOT_L

THERMDC
THERMDA

VDDIO_FB_H

VDDIO_FB_L

DBREQ_L

TEST28_H
TEST28_L

TEST17
TEST16
TEST15
TEST14

TEST7

TEST10

TEST8

TEST29_H
TEST29_L

RSVD10

RSVD9
RSVD8
RSVD7
RSVD6

1K_0402_5%

MMBT3904_NL_SOT23-3

SVC
SVD

TDO

SMBus Address: 1001110X (b)

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

2

SMB_ALERT#

SMB_ALERT# <18>

CPU_SVC <40>
CPU_SVD <40>

CPU_VDDIO_FB_H <37>
CPU_VDDIO_FB_L <37>

CPU_VDDNB_RUN_FB_H <40>
CPU_VDDNB_RUN_FB_L <40>

TP18
TP19

TP23
TP17
TP24TP26
TP30

TP29
TP20

TP28

TP32
TP31

VID BYPASS CIRCUIT

Thermal Sensor
ADM1032

1

C525

2200P_0402_50V7K

2

EC_SMB_CK2
EC_SMB_DA2

2

1

CPU_SVC
CPU_SVD
CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
CPU_MEMHOT#_1.8V

+1.8V

CPU_THERMTRIP#_R

CPU_PROCHOT#_1.8

route as differential
as short as possible
testpoint under package

CPU_TEST27_SINGLECHAIN
CPU_TEST21_SCANEN

CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN

CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0

+3VS

1

C524

0.1U_0402_16V7K~N

2

U24

2
3
8
7

VDD1

D+

ALERT#

D-

THERM#

SCLK

GND

SDATA

ADM1032ARMZ MSOP 8P

Title

Griffin CTRL & ADM1032

Size Document Number Rev

Custom

U1 LA-4381P

Date: Sheet

3 1

MMBT3904_NL_SOT23-3

+1.8V

3 1

MMBT3904_NL_SOT23-3@

1 2

R345 0_0402_5%

1

SMB_ALERT#

6

THERM#

4
5

Compal Electronics, Inc.

R86 1K_0402_5%
R83 1K_0402_5%
R355 300_0402_5%
R354 300_0402_5%
R57 300_0402_5%

R351
10K_0402_5%

1 2
2

Q43

R347
10K_0402_5%

@

1 2
2

Q42

R348 300_0402_5%@

1 2

R59 300_0402_5%

1 2

R352 300_0402_5%@

1 2

R350 300_0402_5%

1 2

R349 300_0402_5%@

1 2

R73 300_0402_5%@

1 2

R72 300_0402_5%@

1 2

R58 300_0402_5%@

1 2

R71 300_0402_5%@

1 2

R82 300_0402_5%@

1 2

12

R70

10K_0402_5%@

R69

1 2

0_0402_5%

@

1

H_THERMTRIP# <18>

CPU_PROCHOT# <17>

+1.8V

CPU_PROCHOT#_1.8

641Wednesday, January 16, 2008

+1.8V

12
12
12
12
12

0.0

of

5

4

3

2

1

VDD(+CPU_CORE) decoupling.

+VCC_CORE0

D D

1

+

C120
330U_X_2VM_R6M

2

1

+

C107
330U_X_2VM_R6M

2

Near CPU Socket

+VCC_CORE0

1

C111
22U_0805_6.3V6M

2

+VCC_CORE0

1

C112

0.22U_0603_16V4Z

C C

2

1

C123
22U_0805_6.3V6M

2

1

C108

0.01U_0402_25V4Z

2

1

C110
22U_0805_6.3V6M

2

1

2

C121
180P_0402_50V8J

1

C124
22U_0805_6.3V6M

2

Under CPU Socket

+VCC_CORE1

+VCC_CORE1

1

C99
22U_0805_6.3V6M

2

1

+

C75
330U_X_2VM_R6M

2

+VCC_CORE1

1

C98
22U_0805_6.3V6M

2

1

C76

0.22U_0603_16V4Z

2

1

+

C91
330U_X_2VM_R6M

2

1

C101
22U_0805_6.3V6M

2

1

C100

0.01U_0402_25V4Z

2

1

C109
22U_0805_6.3V6M

2

1

C92
180P_0402_50V8J

2

+VCC_CORE0 +VCC_CORE1

+VDDNB

+1.8V

G4

18A 18A

H2

J9
J11
J13
J15

K6
K10
K12
K14

L4

L7

L9
L11
L13

L15

M2
M6
M8

M10

N7

N9

N11

3A

K16

M16

P16
T16
V16

H25

J17

K18
K21
K23
K25

L17
M18
M21
M23
M25

N17

JCPU1E

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

FOX_PZ6382A-284S-41F_TURION

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8

VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

<BOM Strucrure>

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8V

2A

VDDIO decoupling.

+1.8V

1

C127
22U_0805_6.3V6M

2

1

C126
22U_0805_6.3V6M

2

1

C93

0.22U_0603_16V4Z

2

1

C103

0.22U_0603_16V4Z

2

1

C95

180P_0402_50V8J

2

1

C146
180P_0402_50V8J

2

+CPU_CORE_NB decoupling.

+VDDNB

1

C113
22U_0805_6.3V6M

2

1

C114
22U_0805_6.3V6M

2

1

C102
22U_0805_6.3V6M

2

AA11
AA13
AA15
AA17
AA19

AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21

AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23

AA4

AB2
AB7
AB9

AD6
AD8

B4
B6
B8

B9
B11
B13
B15
B17
B19
B21
B23
B25

D6

D8

D9
D11
D13
D15
D17
D19
D21
D23
D25

E4

F2
F11
F13
F15
F17
F19
F21
F23
F25

H7

H9
H21
H23

J4

Under CPU Socket

JCPU1F

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

FOX_PZ6382A-284S-41F_TURION

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

<BOM Strucrure>

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

B B

A A

+1.8V

1

C88

0.22U_0603_16V4Z

2

+1.8V +1.8V

1

C83

0.01U_0402_25V4Z

2

+1.8V

1

2

Between CPU Socket and DIMM

C86

4.7U_0805_10V4Z~N

1

C89

0.22U_0603_16V4Z

2

1

C116

0.01U_0402_25V4Z

2

1

C128

4.7U_0805_10V4Z~N

2

1

C131

0.22U_0603_16V4Z

2

180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>

1

C84
180P_0402_50V8J

2

1

C87

4.7U_0805_10V4Z~N

2

1

C130

0.22U_0603_16V4Z

2

1

C117
180P_0402_50V8J

2

A: Add C165 and C176
to follow AMD Layout
review recommand for
EMI

1

C129

4.7U_0805_10V4Z~N

2

1

C85
180P_0402_50V8J

2

1

C: Change to NBO CAP

+

C90
220U_Y_4VM

@

2

1

C115
180P_0402_50V8J

2

VTT decoupling.

+0.9V

1

C215

4.7U_0805_10V4Z~N

2

+0.9V

1

C49

4.7U_0805_10V4Z~N

2

1

C216

4.7U_0805_10V4Z~N

2

Near CPU Socket Right side.

1

C47

4.7U_0805_10V4Z~N

2

1

C551

0.22U_0603_16V4Z

2

1

C48

0.22U_0603_16V4Z

2

+0.9V

Near Power Supply

1

C: Change to NBO CAP

+

C50
220U_Y_4VM

2

1

C550

0.22U_0603_16V4Z

2

1

C46

0.22U_0603_16V4Z

2

1

C553
1000P_0402_25V8J

2

1

C77
1000P_0402_25V8J

2

1

C554
1000P_0402_25V8J

2

1

C45
1000P_0402_25V8J

2

1

C552
180P_0402_50V8J

2

1

C79
180P_0402_50V8J

2

1

C559
180P_0402_50V8J

2

1

C78
180P_0402_50V8J

2

Near CPU Socket Left side.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Griffin PWR & GND

U1 LA-4381P

1

0.0

of

741Wednesday, January 16, 2008

5

JDIM1

1

VREF

3

DDR_A_D0

D D

C C

DDR_A_CKE0<5>

DDR_A_BS#2<5>

DDR_A_BS#0<5>
DDR_A_WE#<5>

DDR_A_CAS#<5>

DDR_A_CS1#<5>

DDR_A_ODT1<5>

B B

A A

SMB_CK_DAT0<9,14,18>
SMB_CK_CLK0<9,14,18>

DDR_A_D1
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18 DDR_A_D22
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_A_CKE0

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_A_CS1#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43 DDR_A_D47
DDR_A_D48

DDR_A_D49 DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
SMB_CK_DAT0

SMB_CK_CLK0

+3VS

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

CONN@

REVERSE TYPE
LOW SLOT

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA0
SA1

4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
DDR_A_CLK1

DDR_A_CLK#1
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_A_CKE1
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6DDR_A_MA8

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_A_CS0#

DDR_A_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D52

DDR_A_CLK2
DDR_A_CLK#2

DDR_A_DM6
DDR_A_D54

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R61 0_0402_5%

12
12

R60 0_0402_5%

DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>

DDR_A_CKE1 <5>

DDR_A_BS#1 <5>
DDR_A_RAS# <5>
DDR_A_CS0# <5>

DDR_A_ODT0 <5>

DDR_A_CLK2 <5>
DDR_A_CLK#2 <5>

3

2007-01-17 Add

1

C299

2

1000P_0402_50V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V+DIMM_VREF+1.8V+1.8V

1

C281

2

0.1U_0402_16V7K~N

1

C298

2

0.1U_0402_16V7K~N

R135

1K_0402_1%

1 2

R152

1K_0402_1%

1 2

DDR_A_ODT1
DDR_A_CS1#
DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_A_ODT0
DDR_A_CS0#
DDR_A_RAS#

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12

DDR_A_MA15
DDR_A_CKE1

DDR_A_BS#0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3

DDR_A_MA7
DDR_A_MA6
DDR_A_MA11
DDR_A_MA14

DDR_A_BS#1
DDR_A_MA0
DDR_A_MA4
DDR_A_MA2

DDR_A_BS#2
DDR_A_CKE0

2007/12/12 2008/12/12

RP1

18
27
36
45

47_0804_8P4R_5%

RP2

18
27
36

RP9

RP14

RP5

RP10

47_0804_8P4R_5%

RP6

RP13

45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Compal Secret Data

Deciphered Date

+1.8V

0.1U_0402_16V7K~N

2

+1.8V

0.1U_0402_16V7K~N

+0.9V

+0.9V

0.1U_0402_16V7K~N

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]

0.1U_0402_16V7K~N

1

2

C148

0.1U_0402_16V7K~N

1

2

C168

DDR_A_D[0..63]<5>

DDR_A_DM[0..7]<5>

DDR_A_DQS[0..7]<5>

DDR_A_MA[0..15]<5>

DDR_A_DQS#[0..7]<5>

+0.9V

PLACE CLOSE TO SO-DIMM1 AS POSSIBLE

1

1

2

2

0.1U_0402_16V7K~N

C151

C138

1

1

2

0.1U_0402_16V7K~N

C142

2

1

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C170

C154

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C136

0.1U_0402_16V7K~N

1

2

C137

1

2

0.1U_0402_16V7K~N

C139

1

1

2

2

C150

C192

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

0.1U_0402_16V7K~N

1

1

2

2

C193

C134

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

1

1

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C194

C153

Title

DDR2 SODIMM-I Socket

Size Document Number Rev

Custom

U1 LA-4381P

Date: Sheet

0.1U_0402_16V7K~N

1

1

2

2

C190

C179

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C191

C140

1

1

2

0.1U_0402_16V7K~N

C171

1

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C141

C195

1

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C169

C135

C217

841Wednesday, January 16, 2008

+0.9V

330U_D2E_2.5VM

1

C147

+

2

@

1

2

4.7U_0805_6.3V6K~N

0.0

of

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C152

C149

1

1

C133

2

2

0.1U_0402_16V7K~N

C218

4.7U_0805_6.3V6K~N

1

5

4

3

2

1

+DIMM_VREF+1.8V+1.8V

JDIM2

1

VREF

3

DDR_B_D0

D D

C C

DDR_B_CKE0<5>

DDR_B_BS#2<5>

DDR_B_BS#0<5>
DDR_B_WE#<5>

DDR_B_CAS#<5>

DDR_B_CS1#<5>

DDR_B_ODT1<5>

B B

A A

SMB_CK_DAT0<8,14,18>
SMB_CK_CLK0<8,14,18>

DDR_B_D1
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_B_CKE0

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_B_CS1#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
SMB_CK_DAT0

SMB_CK_CLK0

+3VS

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-NARN-7F~N

CONN@

REVERSE TYPE
TOP SLOT

DQ4

DQ5

DM0

DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
DDR_B_CLK1

DDR_B_CLK#1
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_B_CKE1
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_B_CS0#

DDR_B_ODT0
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_CLK2
DDR_B_CLK#2

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

R63 4.7K_0402_5%

1 2

R62 0_0402_5%

12

DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>

DDR_B_CKE1 <5>

DDR_B_BS#1 <5>
DDR_B_RAS# <5>
DDR_B_CS0# <5>

DDR_B_ODT0 <5>

DDR_B_CLK2 <5>
DDR_B_CLK#2 <5>

+3VS

1

C297

2

1000P_0402_50V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_B_MA8
DDR_B_MA5
DDR_B_MA9
DDR_B_MA12

DDR_B_BS#0
DDR_B_MA1
DDR_B_MA10
DDR_B_MA3

DDR_B_RAS#
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4

DDR_B_MA13
DDR_B_ODT0
DDR_B_CS0#
DDR_B_BS#1

DDR_B_ODT1
DDR_B_CS1#
DDR_B_CAS#
DDR_B_WE#

DDR_B_MA6
DDR_B_MA7
DDR_B_MA11
DDR_B_MA14

DDR_B_CKE0
DDR_B_BS#2

DDR_B_MA15
DDR_B_CKE1

2007/12/12 2008/12/12

Compal Secret Data

DDR_B_D[0..63]<5>
DDR_B_DM[0..7]<5>

DDR_B_DQS[0..7]<5>
DDR_B_MA[0..15]<5>

DDR_B_DQS#[0..7]<5>

RP11

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP7

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP8

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP4

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP3

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP12

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP15

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP16

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

+1.8V

1

2

0.1U_0402_16V7K~N

C157

Deciphered Date

+0.9V

PLACE CLOSE TO SO-DIMM2 AS POSSIBLE

1

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C173

2

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

+0.9V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C178

C199

0.1U_0402_16V7K~N

1

C198

2

1

1

C143

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

941Wednesday, January 16, 2008

0.0

of

1

2

C225

C155

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C175

C220

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

0.1U_0402_16V7K~N

C177

C159

2

2

1

1

C222

2

2

0.1U_0402_16V7K~N

C176

C197

1

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

330U_D2E_2.5VM

1

C254

+

2

+1.8V

0.1U_0402_16V7K~N

1

C224

2

+0.9V

1

1

2

C174

1

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C144

C223

1

1

2

2

C196

C235

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

C161

2

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

1

1

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C221

C145

Title

Size Document Number Rev

Custom

Date: Sheet

0.1U_0402_16V7K~N

1

1

2

2

C234

C158

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

C160

C219

2

2

1

1

2

2

0.1U_0402_16V7K~N

C156

0.1U_0402_16V7K~N

C172

0.1U_0402_16V7K~N

DDR2 SODIMM-II Socket

U1 LA-4381P

5

4

3

2

1

TMDS_B_DATA2#
TMDS_B_DATA1#
TMDS_B_DATA0#
TMDS_B_CLK#

TMDS_B_DATA2 <16>
TMDS_B_DATA2# <16>
TMDS_B_DATA1 <16>
TMDS_B_DATA1# <16>
TMDS_B_DATA0 <16>
TMDS_B_DATA0# <16>
TMDS_B_CLK <16>
TMDS_B_CLK# <16>

PCIE_LAN_C_TX_P0
PCIE_LAN_C_TX_N0PCIE_LAN_TX_N0
PCIE_WLAN_C_TX_P1PCIE_WLAN_TX_P1
PCIE_WLAN_C_TX_N1
PCIE_CARD_C_TX_P2
PCIE_CARD_C_TX_N2

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N

+1.1VS

SB_TX0P <17>
SB_TX0N <17>
SB_TX1P <17>
SB_TX1N <17>
SB_TX2P <17>
SB_TX2N <17>
SB_TX3P <17>
SB_TX3N <17>

PCIE_LAN_C_TX_P0 <25>
PCIE_LAN_C_TX_N0 <25>
PCIE_WLAN_C_TX_P1 <24>
PCIE_WLAN_C_TX_N1 <24>
PCIE_CARD_C_TX_P2 <24>
PCIE_CARD_C_TX_N2 <24>

H_CLKOP0<4>
H_CLKON0<4>
H_CLKOP1<4>
H_CLKON1<4>

H_CTLOP0<4>
H_CTLON0<4>
H_CTLOP1<4>
H_CTLON1<4>

R387 301_0402_1%

1 2

+1.1VS

H_CADIP[0..15]<4>
H_CADIN[0..15]<4>

H_CADOP[0..15]<4>

H_CADON[0..15]<4>

12

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

HT_RXCALP
HT_RXCALN

R405

49.9_0402_1%

@

H_CADIP[0..15]

H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22
M23

R21

R20

C23

A24

12

R406

49.9_0402_1%

@

U780MA

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

RS780M_FCBGA528

H_CADIP0

HT_TXCALP
HT_TXCALN

D24

H_CADIN0

D25

H_CADIP1

E24

H_CADIN1

E25

H_CADIP2

F24

H_CADIN2

F25

H_CADIP3

F23

H_CADIN3

F22

H_CADIP4

H23

H_CADIN4

H22

H_CADIP5

J25

H_CADIN5

J24

H_CADIP6

K24

H_CADIN6

K25

H_CADIP7

K23

H_CADIN7

K22

H_CADIP8

F21

H_CADIN8

G21

H_CADIP9

G20

H_CADIN9

H21

H_CADIP10

J20

H_CADIN10

J21

H_CADIP11

J18

H_CADIN11

K17

H_CADIP12

L19

H_CADIN12

J19

H_CADIP13

M19

H_CADIN13

L18

H_CADIP14

M21

H_CADIN14

P21

H_CADIP15

P18

H_CADIN15

M18

H_CLKIP0

H24

H_CLKIN0

H25

H_CLKIP1

L21

H_CLKIN1

L20

H_CTLIP0

M24

H_CTLIN0

M25

H_CTLIP1

P19

H_CTLIN1

R18

HT_TXCALP

B24

HT_TXCALN

B25

Place < 100mils from pin B25 and B24Place < 100mils from pin AC8 and AB8 Place < 100mils from pin C23 and A24

PART 1 OF 6

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P
HT_TXCLK0N

HYPER TRANSPORT CPU I/F

HT_TXCLK1P
HT_TXCLK1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

H_CLKIP0 <4>
H_CLKIN0 <4>
H_CLKIP1 <4>
H_CLKIN1 <4>

H_CTLIN0 <4>
H_CTLIN1 <4>

R386 301_0402_1%

1 2

H_CTLIP0 <4>
H_CTLIP1 <4>

TMDS_B_DATA2
TMDS_B_DATA1
TMDS_B_DATA0

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N

GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

TMDS_B_CLK

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

PCIE_LAN_TX_P0

AC1
AC2
AB4

PCIE_WLAN_TX_N1

AB3

PCIE_CARD_TX_P2

AA2

PCIE_CARD_TX_N2

AA1
Y1
Y2
Y4
Y3
V1
V2

SB_TX0P_C

AD7

SB_TX0N_C

AE7

SB_TX1P_C

AE6

SB_TX1N_C

AD6

SB_TX2P_C

AB6

SB_TX2N_C

AC6

SB_TX3P_C SB_TX3P

AD5

SB_TX3N_C SB_TX3N

AE5
AC8

AB8

D D

C C

PCIE_LAN_C_RX_P0<25>
PCIE_LAN_C_RX_N0<25>
PCIE_WLAN_C_RX_P1<24>
PCIE_WLAN_C_RX_N1<24>
PCIE_CARD_C_RX_P2<24>
PCIE_CARD_C_RX_N2<24>

SB_RX0P<17>
SB_RX0N<17>
SB_RX1P<17>
SB_RX1N<17>
SB_RX2P<17>
SB_RX2N<17>
SB_RX3P<17>
SB_RX3N<17>

B B

PCIE_LAN_C_RX_P0
PCIE_LAN_C_RX_N0
PCIE_WLAN_C_RX_P1
PCIE_WLAN_C_RX_N1
PCIE_CARD_C_RX_P2
PCIE_CARD_C_RX_N2

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

U780MB

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS780M_FCBGA528

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

1 2

R389 10_0402_5%@

1 2

R390 10_0402_5%@

1 2

R105 10_0402_5%@

1 2

R388 10_0402_5%@

TMDS_B_DATA2
TMDS_B_DATA2#
TMDS_B_DATA1
TMDS_B_DATA1#
TMDS_B_DATA0
TMDS_B_DATA0#
TMDS_B_CLK
TMDS_B_CLK#

C547 0.1U_0402_16V7K~N
C546 0.1U_0402_16V7K~N
C182 0.1U_0402_16V7K~N
C183 0.1U_0402_16V7K~N
C548 0.1U_0402_16V7K~N
C558 0.1U_0402_16V7K~N

C532 0.1U_0402_16V7K~N

1 2

C533 0.1U_0402_16V7K~N

1 2

C535 0.1U_0402_16V7K~N

1 2

C534 0.1U_0402_16V7K~N

1 2

C537 0.1U_0402_16V7K~N

1 2

C536 0.1U_0402_16V7K~N

1 2

C542 0.1U_0402_16V7K~N

1 2

C538 0.1U_0402_16V7K~N

PCE_PCAL
PCE_NCAL

1 2

R85 1.27K_0402_1%

1 2

R84 2K_0402_1%

1 2

1 2
1 2
1 2
1 2
1 2
1 2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

U1 LA-4381P

2

Date: Sheet

RS780MC HT / PCIE / DVI

1

10 41Wednesday, January 16, 2008

0.0

of

+3VS +3VS

12

R431
3K_0402_5%

VGA_CRT_VSYNC

Pull-up: Disable
Debug Port

+1.1VS

L53

L16

L12

L10

12
12

CLK_NB_REFCLK

12

2

1

15mil

15mil

15mil

15mil

EDID_CLK_LCD
EDID_DAT_LCD

+1.8VS

+1.8VS

+1.8VS

+3VS

R415

33_0402_5%

C577

22P_0402_50V8J

+3VS

R116
10K_0402_5%

1 2

NB_STRAP_DATA

12

+1.1VS

1K_0402_1%

1 2

1K_0402_1%

1 2

1 2

FCM2012C-800_0805

1 2

FCM2012C-800_0805

1 2

FCM2012C-800_0805

1 2

FCM2012C-800_0805

R412 4.7K_0402_5%
R414 4.7K_0402_5%

@

@

R117
2K_0402_5%

@

R378

NB_REFCLK_N

R377

+NB_PLLVDD

1

C576

2.2U_0603_10V6K

2

+NB_PLLVDD18

1

C268

2.2U_0603_10V6K

2

+NB_PCIEPLL

1

C255

2.2U_0603_10V6K

2

+NB_HTPLL

1

C233

2.2U_0603_10V6K

2

SB_PWRGD<6,18,28>

12

R108
3K_0402_5%

VGA_CRT_HSYNC

Pull-up: Disable
Side Port Memory

SB_PWRGD

12

R155

10K_0402_5%

1 2

R101 150_0402_1%

1 2

R110 150_0402_1%

1 2

R111 150_0402_1%

VGA_DDC_CLK<15>

EDID_CLK_LCD<15>
EDID_DAT_LCD<15>

+5VS

R140
10K_0402_5%

1 2

SB_PWRGD#

13

D

2

G

S

+3VS

1 2

FCM2012C-800_0805

+1.8VS

0_0603_5%

+1.8VS

1 2

FCM2012C-800_0805

VGA_DDC_CLK

+1.8VS

12

13

2

G

Q22

SSM3K7002FU_SC70-3

L13

2.2U_0603_10V6K

R407

1 2

2.2U_0603_10V6K

L54

2.2U_0603_10V6K

VGA_CRT_G
VGA_CRT_B

R99 0_0402_5%

EDID_CLK_LCD
EDID_DAT_LCD

HDMICLK_UMA<16>
HDMIDAT_UMA<16>

R410
300_0402_5%

NB_PWRGD

D

Q14

SSM3K7002FU_SC70-3

S

@

+AVDD

1

C262

2

+AVDDDI

1

C267

2

+AVDDQ

1

C565

2

VGA_CRT_HSYNC<15>
VGA_CRT_VSYNC<15>

1 2

VGA_DDC_DATA<15>

NB_RST#<17,23,24,25,28>

CLK_HTREFCLKP<14>
CLK_HTREFCLKN<14>

CLK_NB_REFCLK<14>

CLK_NB_GFX_CLKP<14>
CLK_NB_GFX_CLKN<14>

CLK_SBLINKCLK<14>
CLK_SBLINKCLK#<14>

R413 0_0402_5%

1 2

NB_STRAP_DATA<38>

12

R4090_0402_5%

15mil

VGA_CRT_R<15>
VGA_CRT_G<15>
VGA_CRT_B<15>

VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_DDC_CLK_NB
VGA_DDC_DATA

R100 715_0402_1%

1 2

+NB_PLLVDD
+NB_PLLVDD18

+NB_HTPLL
+NB_PCIEPLL

NB_RST#
NB_PWRGD
NB_LDTSTOP#
NB_ALLOW_LDTSTOP

CLK_HTREFCLKP
CLK_HTREFCLKN

CLK_NB_REFCLK
NB_REFCLK_N

CLK_NB_GFX_CLKP
CLK_NB_GFX_CLKN

CLK_SBLINKCLK
CLK_SBLINKCLK#

EDID_CLK_LCD_NB

NB_STRAP_DATA

1 2

R104 150_0402_1%@

NB_PWRGD_SB <18>

LDT_STOP#<6,17>

15mil

15mil

U780MC

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

VGA_CRT_RVGA_CRT_R
VGA_CRT_G
VGA_CRT_B

CPU_LDT_REQ#<6,17>

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_CLK0/AUX0P(NC)

A8

DDC_DATA0/AUX0N(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS780M_FCBGA528

+1.8VS

12

@

R156

4.7K_0402_5%

G

2

@

13

D

S

BSS138_NL_SOT23-3

Q18

R141 0_0402_5%

+3VS

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

CLOCKs PLL PWR

MIS.

+1.8VS

12

R143

4.7K_0402_5%

@

G

2

13

D

S

@

Q19 BSS138_NL_SOT23-3

R144 0_0402_5%

12

R408

4.7K_0402_5%

@

NB_LDTSTOP#LDT_STOP#

2007/12/12 2008/12/12

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC)

TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)

TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)
VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

THERMALDIODE_P
THERMALDIODE_N

TESTMODE

+3VS

12

R142

@

4.7K_0402_5%

NB_ALLOW_LDTSTOPCPU_LDT_REQ#

12

Compal Secret Data

Deciphered Date

HPD(NC)

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

D9
D10

D12
AE8

AD8
D13

LVDSL0+
LVDSL0­LVDSL1+
LVDSL1­LVDSL2+
LVDSL2-

LVDSU0+
LVDSU0­LVDSU1+
LVDSU1­LVDSU2+
LVDSU2-

LVDSLC+
LVDSLC­LVDSUC+
LVDSUC-

ENVDD_NB
ENABLT_NB

SB_SUS_STAT#

12

+LPVDD

+LVDDR18D

+LVDDR33A

R109

1.8K_0402_5%

LVDSL0+ <15>
LVDSL0- <15>
LVDSL1+ <15>
LVDSL1- <15>
LVDSL2+ <15>
LVDSL2- <15>

LVDSU0+ <15>
LVDSU0- <15>
LVDSU1+ <15>
LVDSU1- <15>
LVDSU2+ <15>
LVDSU2- <15>

LVDSLC+ <15>
LVDSLC- <15>
LVDSUC+ <15>
LVDSUC- <15>

0.1U_0402_16V7K~N

R106 0_0402_5%

12

R98 0_0402_5%

12

HPD <16>

R439 0_0402_5%@

12

R363 0_0402_5%

12

R362 0_0402_5%

12

12

R411
3K_0402_5%

NB_PWRGD

SSM3K7002FU_SC70-3

L19

1 2

FCM2012C-800_0805

1

C269

2.2U_0603_10V6K

2

1

C257

2

1

C261

2.2U_0603_10V6K

2

R107

1.27K_0402_1%

+5VS

@

2

G

Q13

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

FCM2012C-800_0805

1

C263

4.7U_0805_6.3V6K~N

2

1 2

FCM2012C-800_0805

12

1.27K_0402_1%

SUS_STAT# <18>
SB_NB_THRMDA <19>

SB_NB_THRMDC <19>

ENVDD_NB

R139

10K_0402_5%

1 2

NB_PWRGD5V#

13

D

ENABLT_NB

@

S

AP2301GN 1P SOT23

U1 LA-4381P

L14

L11

ENVDD
ENABLT

R97

+1.8VS

0.08A

15mil

+3VS

0.22A

@

12

Q12
AP2301GN 1P SOT23

S

G

G

S

Q21

@

2

2

@

15mil

ENVDD <15>
ENABLT <15,28>

D

ENVDD

13

12

R122

1K_0402_5%

@

ENABLT

13

D

12

R154

1K_0402_5%

RS780MC VIDEO_IF/CLOCK GEN

of

11 41Wednesday, January 16, 2008

0.0

5

+1.1VS

0.6A

D D

C C

FBMA-L11-322513-201LMA40T_1210

FBMA-L11-322513-201LMA40T_1210

0.45A

FBMA-L11-322513-201LMA40T_1210

For A11, This
VTTHTTX power plane
should connect to
+1.35VS.

0.5A

FBMA-L11-322513-201LMA40T_1210

+1.8VS

1 2

+1.1VS

1 2

+1.2V_HT

1 2

L49

1 2

C531

R382

1 2

0_0603_5%

L17

L18

L4

0.25A

C575

C574

1

C164

2

4.7U_0805_6.3V6K~N

1

C256
1U_0402_6.3V6K

2

C167

+VDDHT

1

C246

2

4.7U_0805_6.3V6K~N

+VDDHTRX

1

C250

2

4.7U_0805_6.3V6K~N

+VDDHTTX

1

C212

2

4.7U_0805_6.3V6K~N

+VDDA18PCIE

1

C241

2

4.7U_0805_6.3V6K~N

+VDD18

1

C248

2

0.1U_0402_16V7K~N

1

C259

2

0.1U_0402_16V7K~N

1

C186

2

0.1U_0402_16V7K~N

1

C207

2

0.1U_0402_16V7K~N

1

1

C232

2

0.1U_0402_16V7K~N

1

C249

2

0.1U_0402_16V7K~N

1

C187

2

0.1U_0402_16V7K~N

1

C184

2

0.1U_0402_16V7K~N

1

C211

2

2

0.1U_0402_16V7K~N

1

1

C258

2

2

0.1U_0402_16V7K~N

1

1

C166

2

2

0.1U_0402_16V7K~N

1

1

C185

2

2

0.1U_0402_16V7K~N

0.005A

+1.8VS

R80

1 2

0_0603_5%

0.005A

+VDD18_MEM

1

C165
1U_0402_6.3V6K

2

@

4

U780ME

J17

VDDHT_1

K16
L16

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

M16

G19

AE25
AD24
AC23
AB22
AA21

W19

M17

M10

AA9
AB9
AD9
AE9

AE11
AD11

P16
R16
T16

H18
F20

E21
D22
B23
A23

Y20
V18

U17
T17
R17
P17

J10
P10
K10

L10

W9

H9
T10
R10

Y9

U10

F9

G9

PART 5/6

VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

RS780M_FCBGA528

VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

POWER

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

C209

C240

C243

3

+VDDPCIE

1

1

1

C205

C204

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

C206

2

C266

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C229

2

2

10U_0805_6.3V6M

4.7U_0805_6.3V6K~N

300mil

1

1

1

C230

2

C247

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

+VDD33

1

1

C242

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C208

C244

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

C245

C231

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

R381

1 2

0_0603_5%

2

+1.1VS

L15

0.1U_0402_16V7K~N

+3VS

C560

0.7A

1.0V-1.1V 7A

+NB_CORE

1

C210

2

22U_0805_6.3VAM

1

2

1 2

FBMA-L11-322513-201LMA40T_1210

1

2

0.03A

C203

22U_0805_6.3VAM

1

U780MF

A25

VSSAHT1

D23
E22
G22
G24
G25
H19

J22
L17
L22
L24
L25

M20

N22
P20
R19
R22
R24
R25
H20
U22

330U_X_2VM_R6M

W22
W24
W25

AD25

M14

W11

W15
AC12
AA14

AB11
AB15
AB17
AB19
AE20
AB21

V19

Y21

L12

N13
P12
P15
R11
R14
T12
U14
U11
U15
V12

Y18

K11

1

+

2

PART 6/6

VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

RS780M_FCBGA528

VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30

GROUND

VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

B B

RS740/RX780/RS780 POWER DIFFERENCE TABLE

PIN NAME
VDDHT
VDDHTRX
VDDHTTX
VDDA18PCIE

VDD18_MEM
VDDPCIE
VDDC
VDD_MEM
VDDG33

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

IOPLLVDD18

Compal Secret Data

RS740

NC

+1.2V
NC
+1.8V NC
NC
+1.2V +1.1V +1.1V
+1.2V

+1.8V/1.5V

+3.3V
+1.8V +1.8VNC

RX780

+1.1V
+1.1V
+1.2V
+1.8V
+1.8VVDDG18
NC

+1.1V
NC
NC

+1.8V/1.5V

Deciphered Date

2

RS780

+1.1V
+1.1V
+1.2V
+1.8V
+1.8V
+1.8V

+1.1V

+3.3V

PIN NAME
IOPLLVDD

AVDDDI
AVDDQ
PLLVDD
PLLVDD18

VDDA18HTPLL
VDDLTP18
VDDLT18
VDDLT33

RS740 RX780 RS780

+1.2V
+3.3V NC

+1.2V
+1.8V
+1.2VVDDA18PCIEPLL
+1.8V
+1.8V
+1.8V
+3.3V

Title

Size Document Number Rev
Custom

U1 LA-4381P

Date: Sheet

NC

+1.1V

+3.3VAVDDNC
NC+1.8V +1.8V
NC+1.8V +1.8V

+1.1V
NC

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V

+1.8V

NC
NC

+1.8V
NC

NC

RS780MC Power/GND

1

0.0

of

12 41Wednesday, January 16, 2008

2

B B

1

U780MD

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

MEM_CKP(NC)
MEM_CKN(NC)

MEM_COMPP(NC)
MEM_COMPN(NC)

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)
MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

IOPLLVDD(NC)

IOPLLVSS(NC)

MEM_VREF(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23

VDD_MUX_IOPLLVDD

AE24
AD23
AE18

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L47

0_0402_5%

C529

2.2U_0603_10V6K

@

2007/12/12 2008/12/12

+1.8V_IOPLLVDD

12

+1.1VS

1

C528 0.1U_0402_16V7K~N

2

Compal Secret Data

Deciphered Date

0_0402_5%

1

C530

2.2U_0603_10V6K

2

@

+1.8VS

L48

12

1

Title

Size Document Number Rev

Custom

U1 LA-4381P

Date: Sheet

RS780MC Power/GND

13 41Wednesday, January 16, 2008

of

0.0

AB12
AE16

V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14

Y14
AD16

AE17
AD17

W12

Y12
AD18
AB13
AB18

A A

2

V14

V15

W14

AE12
AD12

RS780M_FCBGA528

A

B

C

D

E

F

G

H

VDDIO voltage range is 1.05V~3.3V

+3VS

L60

@

+1.2V_HT

1 1

+3VS

FBM-L11-160808-601LMT_0603

2 2

3 3

HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK
GPP_REFCLK
GPPSB_REFCLK 100M DIFF 100M DIFF

* RS780 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.

R40/R41 (value may change)

L55

C582

Clock chip has internal serial terminations
for differencial pairs, external resistors are
reserved for debug purpose.

NB CLOCK INPUT TABLE

NB CLOCKS

RS740 RX780 RS780

66M SE(SINGLE END)

NC

14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V)
NC NC vref

100M DIFF
NC
100M DIFF

OSC_14M_NB

FBM-L11-160808-601LMT_0603

FBM-L11-160808-601LMT_0603

+3VS_CLK (40 mils)

12

1

1

C583

2

2

22U_0805_6.3V6M

100M DIFF
100M DIFF

100M DIFF
100M DIFF

3.3V 33R serialRS740

1.8V 33R/43RRX780

RS780

4 4

* default

1.1V 200R/100R

1 66 MHz 3.3V single ended HTT clock

SEL_HTT66

0*

100 MHz differential HTT clock

1*

SEL_SATA

SEL_27

100 MHz non-spreading differential SRC clock

0

100 MHz spreading differential SRC clock

1

Pin 4 / 5 configure as 27M and 27M_SS outputs

0*

Pin 4 / 5 configure as SRC_7 output

A

12

L56

1

C332

2

2.2U_0603_10V6K

12

1

C310

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

27P_0402_50V8J

1 2

1 2

27P_0402_50V8J

100M DIFF
100M DIFF

100M DIFF(IN/OUT)*

NC or 100M DIFF OUTPUT

C293

C567

C566

C598

1

2

B

1

1

C354

C312

2

2

0.1U_0402_16V7K~N

22U_0805_6.3V6M

1

1

C294

C335

0.1U_0402_16V7K~N

12

Y4

14.31818MHz_20P_1BX14318BE1A

2

2

0.1U_0402_16V7K~N

XTALIN_CLK
XTALOUT_CLK

SEL_HT66
SEL_SATA
SEL_27

1

2

C311

0.1U_0402_16V7K~N

C334

0.1U_0402_16V7K~N

+3VS

@

1

2

1

C296

2

0.1U_0402_16V7K~N

SMB_CK_CLK0<8,9,18>

SMB_CK_DAT0<8,9,18>

L58

1 2

0_0805_5%

L59

1 2

0_0805_5%

+3VS_CLK

12

R133

8.2K_0402_5%

12

R134

@

8.2K_0402_5%

C597

0.1U_0402_16V7K~N

R132

R131

1

2

CLKREQ_MINICARD#<24>

12

8.2K_0402_5%

12

8.2K_0402_5%

C

1

2

C295

0.1U_0402_16V7K~N

+3VS_CLK

CLKREQ_54CARD#<24>

C588

R130

@

R129

@

C584

0.1U_0402_16V7K~N

1

2

CLKREQ_LAN#<25>

1

2

22U_0805_6.3V6M

12

8.2K_0402_5%

12

8.2K_0402_5%

+1.1VS_3VS_CLK_VDDIO

1

1

C596

2

2

0.1U_0402_16V7K~N

+3VS_CLK

1

C333

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1 2

R422 10K_0402_5%

SMB_CK_CLK0
SMB_CK_DAT0

1

C587

2

CLKREQ_54CARD#
CLKREQ_LAN#
CLKREQ_MINICARD#

0.1U_0402_16V7K~N

CLK_RESET

CLKREQ_54CARD#
CLKREQ_LAN#
CLKREQ_MINICARD#

GNDVSS

0.1U_0402_16V7K~N

U27

CPUCLK0H

12

VDD_SRC_IO

18

VDD_SRC_IO

28

VDD_ATIG_IO

37

VDD_SB_SRC_IO

53

VDD_CPU_I/O

3

VDD_DOT

17

VDD_SRC

29

VDD_ATIG

38

VDD_SB_SRC

44

VDD_SATA

54

VDD_CPU

61

VDD_HTT

62

VDD_REF

69

VDD_48

57

PD#

1

SCL

2

SDA

67

XTAL_IN

68

XTAL_OUT

24

CLKREQ_0#

51

CLKREQ_1#

50

CLKREQ_2#

43

CLKREQ_3#

42

CLKREQ_4#

41

SB_SRC_SLOW#

49

VDD_A

48

VSS_A

6

VSS_DOT

11

VSS_SRC

19

VSS_SRC

27

VSS_ATIG

36

VSS_SB_SRC

47

VSS_SATA

52

VSS_CPU

58

VSS_HTT

66

VSS_REF

72

VSS_48

73

GND

SLG8SP626VTR_QFN72_10x10

+3VS_CLK

12

12

R432

@

10K_0402_5%

R149

2.2K_0402_5%

10K_0402_5%

12

2.2K_0402_5%

R433

R150

@

R458

12

R459

@

12

10K_0402_5%

12

2.2K_0402_5%

SRC_6#/SATA#

SRC_7/27M_SS

HTT_0/66M_0

HTT_0#/66M_1

REF_0/SEL_HTT66

REF_1/SEL_SATA

REF_2/SEL_27

ICS9LPRS476BKLFT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

56

CPU_K8_0

CPU_K8_0#

ATIGCLK_0

ATIGCLK_0#

ATIGCLK_1

ATIGCLK_1#

ATIGCLK_2

ATIGCLK_2#

SB_SRC_0

SB_SRC_0#

SB_SRC_1

SB_SRC_1#

SRC_0#
SRC_1#
SRC_2#
SRC_3#
SRC_4#
SRC_5#

SRC_6/SATA

SRC_7#/27M

48MHz_0
48MHz_1

2007/12/12 2008/12/12

E

SRC_0
SRC_1
SRC_2
SRC_3
SRC_4
SRC_5

CPUCLK0L

55

CLK_GFX_CLKP

33

CLK_GFX_CLKN

32
31
30
26
25

SBLINKCLK_R

40

SBLINKCLK#_R

39

SBSRCCLK_R

35

SBSRCCLK#_R

34

CLK_CARD

23

CLK_CARD#

22

CLK_LAN

21

CLK_LAN#

20

CLK_WCARD

16

CLK_WCARD#

15
14
13
10
9
8
7
46
45
5
4

HTREFCLKP

60

HTREFCLKN

59

71
70

SEL_HT66

65

SEL_SATA

64

SEL_27

63

Compal Secret Data

R423 0_0402_5%
R424 0_0402_5%

R416 33_0402_5%

R417 33_0402_5% @
R418 33_0402_5% @
R419 158_0402_1%

12
12

R461 0_0402_5%
R460 0_0402_5%

R446 0_0402_5%
R447 0_0402_5%
R463 0_0402_5%
R462 0_0402_5%

R457 0_0402_5%
R456 0_0402_5%
R455 0_0402_5%
R454 0_0402_5%
R445 0_0402_5%
R444 0_0402_5%

R420 0_0402_5%
R421 0_0402_5%

1 2

1 2
1 2
1 2

12
12

90.9_0402_1%

CLK_USBCLK_EXT
CLK_NB_REFCLK

Deciphered Date

F

R391

12

R392
261_0402_1%

@

12

CLK_NB_GFX_CLKP
CLK_NB_GFX_CLKN

CLK_SBLINKCLK
CLK_SBLINKCLK#
CLK_SBSRCCLK
CLK_SBSRCCLK#

CLK_PCIE_CARD
CLK_PCIE_CARD#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_WCARD
CLK_PCIE_WCARD#

CLK_USBCLK_EXTCLK_USB

CLK_NB_REFCLK <11>

CLK_NB_REFCLK will
get 1.1V with R400
200ohm and R401 100
ohm.

C578 10P_0402_25V8K@

1 2

C568 10P_0402_25V8K@

1 2

CLK_HTREFCLKP <11>
CLK_HTREFCLKN <11>

Title

Size Document Number Rev

Custom

Date: Sheet

12
12

12
12
12
12

12
12
12
12
12
12

CLK_CPUCLK0_H <6>

CLK_CPUCLK0_L <6>

CLK_NB_GFX_CLKP <11>
CLK_NB_GFX_CLKN <11>

CLK_SBLINKCLK <11>
CLK_SBLINKCLK# <11>
CLK_SBSRCCLK <17>
CLK_SBSRCCLK# <17>

CLK_PCIE_CARD <24>
CLK_PCIE_CARD# <24>
CLK_PCIE_LAN <25>
CLK_PCIE_LAN# <25>
CLK_PCIE_WCARD <24>
CLK_PCIE_WCARD# <24>

CLK_USBCLK_EXT <18>

U1 LA-4381P

G

CLK_USBCLK_EXT

Clock Generator

@

@

12

R146
33_0402_5%

2

C277
22P_0402_50V8J

1

of

14 41Wednesday, January 16, 2008

H

0.0

A

1 1

VGA_CRT_R<11>

VGA_CRT_G<11>

VGA_CRT_B<11>

VGA_CRT_HSYNC<11>

2 2

VGA_CRT_VSYNC<11>

VGA_CRT_VSYNC CRT_VSYNC D_CRT_VSYNC

1 2

R8 39_0402_5%

1 2

R5 39_0402_5%

B

VGA_CRT_R

VGA_CRT_G CRT_G_L

VGA_CRT_B

1

1

12

12

12

R323

R334

150_0402_1%

1 2

C6 0.1U_0402_16V7K~N

CRT_HSYNC D_CRT_HSYNCVGA_CRT_HSYNC

+CRT_VCC

1 2

C5 0.1U_0402_16V7K~N

R333

150_0402_1%

150_0402_1%

+CRT_VCC

1

5

P

OE#

A2Y

G

U2

74AHCT1G125GW_SOT353-5

3

1

5

P

OE#

A2Y

G

U1
74AHCT1G125GW_SOT353-5

3

4

4

C469

C472

2

2

8P_0402_50V8K

8P_0402_50V8K

R7 10K_0402_5%

FCM2012C-800_0805

FCM2012C-800_0805

FCM2012C-800_0805

1

C480

2

8P_0402_50V8K

C

L39

1 2

L38

1 2

L37

1 2

12

D16

DAN217_SC59-3

CRT_R_L

CRT_B_L

2

3

1

DAN217_SC59-3

1

C481

2

8P_0402_50V8K

2

3

D15

DAN217_SC59-3

1

1

C473

2

8P_0402_50V8K

1 2

R6 0_0603_5%

1 2

R4 0_0603_5%

+5VS

3

D13

C470

8P_0402_50V8K

10P_0402_50V8J

2

1

1

2

DAN217_SC59-3

MSEN#<28>

C4

1

2

D3

HSYNC_L

VSYNC_L

+3VS+CRT_VCC +3VS+CRT_VCC +3VS

D

+5VS

F3

1.1A_6VDC_FUSE

2

D2

DAN217_SC59-3

1

C489

100P_0402_25V8K

100P_0402_25V8K

C467

2

3

3

1

1

C3

2

10P_0402_50V8J

21

1

C7

2

68P_0402_50V8K

W=40mils

D19

2 1

RB491D_SOT23

VGA_DDC_DATA_C

VGA_DDC_CLK_C

1

C1
68P_0402_50V8K

2

W=40mils

C490

E

+CRT_VCC

1

2

JCRT

0.1U_0402_16V7K~N

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070546FR015S2307R~D

16
17

LCD POWER CIRCUIT

+3VS

1

C8

0.1U_0402_16V7K~N

2

ENVDD<11>

3 3

4 4

ENVDD

10K_0402_5%

BKOFF#<28>

ENABLT<11,28>

12

R12

BKOFF# DISPOFF#

A

21

21

D17
RB751V-40TE17_SOD323-2

D18
RB751V-40TE17_SOD323-2@

U3

IN6OUT
EN3NC

5

GND

AOZ1320CI-04_SOT23-6

+3VS

GND

12

R335
1K_0402_5%

W=60milsW=60mils

1
4
2

1N4148_SOT23@

D14

1

C10

4.7U_0805_6.3V6K~N

2

12

B+

+LCDVDD

1

C468

2

F2

3A_32V

B

+LCDVDD

1

C9

0.1U_0402_16V7K~N

2

INVT_PWM

1U_0603_10V6K@

21

0.1U_0603_50V4Z

VGA_DDC_DATA_C

VGA_DDC_CLK_C

+3VS

1

C487

0.1U_0402_16V7K~N@

2

INVPWR_B+ INVPWR_B+

0.1U_0603_50V4Z

2

2

C475

C474

1

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R11

1 2

6.8K_0402_5%

2007/12/12 2008/12/12

C

R3

6.8K_0402_5%

BSS138_NL_SOT23-3

+LCDVDD

EDID_CLK_LCD<11>

EDID_DAT_LCD<11>

LVDSUC+<11>

LVDSUC-<11>
LVDSU0+<11>

LVDSU0-<11>

LVDSU1+<11>

LVDSU1-<11>

LVDSU2+<11>

LVDSU2-<11>

R9

0_0402_5%

1 2

1 3

D

BSS138_NL_SOT23-3

1 2

R13 0_1206_5%

+3VS

Compal Secret Data

R10

1 2
2

G

S

2

Q2

1 3

D

Q1

+LCDVDD_R

EDID_CLK_LCD
EDID_DAT_LCD

LVDSUC+
LVDSUC-

LVDSU0+
LVDSU0-

LVDSU1+
LVDSU1-

LVDSU2+
LVDSU2-

Deciphered Date

R2

4.7K_0402_5% 1 2

4.7K_0402_5% 1 2

JLCD1

GND41GND

39

39

37

37

35

35

33

33

31

31

29

29

27

27

25

25

23

23

21

21

19

19

17

17

15

15

13

13

11

11

9

9

7

7

5

5

3

3

1

1

ACES_87242-4001

D

VGA_DDC_DATA <11>

VGA_DDC_CLK <11>

42
40

40

38

38
36
34
32
30
28
26
24
22
20
18
16
14
12
10

LVDSLC+

36

LVDSLC-

34
32

LVDSL0+

30

LVDSL0-

28
26

LVDSL1+

24

LVDSL1-

22
20

LVDSL2+

18

LVDSL2-

16
14
12
10

INVT_PWM

8

8

6

6

4

4

2

2

LVDSLC+ <11>
LVDSLC- <11>

LVDSL0+ <11>
LVDSL0- <11>

LVDSL1+ <11>
LVDSL1- <11>

LVDSL2+ <11>
LVDSL2- <11>

DAC_BRIG

Title

Size Document Number Rev

Custom

Date: Sheet

DISPOFF#

2

2

2

C471

C482

C483

1

@

0.1U_0402_16V4Z

1

1

@

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CRT Conn.& LCD Conn. & Camera

U1 LA-4381P

E

DAC_BRIG <28>
INVT_PWM <28>

0.0

of

15 41Wednesday, January 16, 2008

G

S

A

B

C

D

E

FOR U1H

R164

+HDMI_5V_OUT+3VS

R137

6.8K_0402_5%

HDMI_SDATA

HDMI_SCLK

1 1

0.1U_0402_16V4Z

2 2

C275

U1H@

+HDMI_5V_OUT

2

5

1

P

A2Y

G

3

1

OE#

U1H@

2.2K_0402_5%

4

U8
SN74AHCT1G125GW_SOT353-5

U1H@

12

R136

HPD <11>

+3VS

R121

100K_0402_5%

U1H@

1 2

HDMI_HPD

C273

2

0.1U_0402_16V4Z

U1H@

1

12

R180

4.7K_0402_5%

HDMIDAT_UMA<11>

HDMICLK_UMA<11>

R138

4.7K_0402_5%

1 2

+3VS

G

2

13

D

S

Q17
BSH111_SOT23

+3VS

G

2

S

Q24
BSH111_SOT23

U1H@

13

D

U1H@

6.8K_0402_5%

MP:Update D10 to meet HDMI.

SI:Add R6161~R624 for EMI requset

HDMI_CLK-

C201 0.1U_0402_16V7K

TMDS_B_CLK<10>
TMDS_B_CLK#<10>

TMDS_B_DATA0<10>

3 3

4 4

TMDS_B_DATA0#<10>

TMDS_B_DATA1<10>

TMDS_B_DATA1#<10>

TMDS_B_DATA2<10>
TMDS_B_DATA2#<10>

1 2

C200 0.1U_0402_16V7K

1 2

C226 0.1U_0402_16V7K

1 2

C202 0.1U_0402_16V7K

1 2

C228 0.1U_0402_16V7K

1 2

C227 0.1U_0402_16V7K

1 2

C239 0.1U_0402_16V7K

1 2

C238 0.1U_0402_16V7K

1 2

HDMI_CLK+
HDMI_CLK-

HDMI_TX0+

HDMI_TX0-

HDMI_TX1+

HDMI_TX1-

HDMI_TX2+

HDMI_TX2-

HDMI_TX0-

HDMI_TX0+

HDMI_TX1-

HDMI_TX1+

HDMI_TX2+

1 2

R87 0_0402_5%@

L5

4

4

1

1

WCM-2012-900T_0805

1 2

R88 0_0402_5%@

1 2

R89 0_0402_5%@

L6

4

4

1

1

WCM-2012-900T_0805

1 2

R92 0_0402_5%@

1 2

R93 0_0402_5%@

L7

4

4

1

1

WCM-2012-900T_0805

1 2

R94 0_0402_5%@

1 2

R95 0_0402_5%@

L9

4

4

1

1

WCM-2012-900T_0805

1 2

R96 0_0402_5%@

3

3

2

2

3

3

2

2

3

3

2

2

3

3

2

2

HDMI_R_CK-

HDMI_R_CK+HDMI_CLK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-HDMI_TX2-

HDMI_R_D2+

HDMI_R_CK+
HDMI_R_CK-

HDMI_R_D0­HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2+

HDMI_R_D2-

SI:Add Q136 & Q137 for AMD request

D

+5VS

+5VS

+5VS

+5VS

1 3

SSM3K7002FU_SC70-3

U1H@

Q44

G

2

D

1 3

SSM3K7002FU_SC70-3

U1H@

Q45

G

2

D

1 3

SSM3K7002FU_SC70-3

U1H@

Q46

G

2

D

1 3

SSM3K7002FU_SC70-3

U1H@

Q47

G

2

1 2

R369 750_0402_1%

1 2

R368 750_0402_1%

1 2

R370 750_0402_1%

1 2

R372 750_0402_1%

1 2

R373 750_0402_1%

1 2

R374 750_0402_1%

1 2

R380 750_0402_1%

1 2

R379 750_0402_1%

+5VS +HDMI_5V_OUT

S

S

+HDMI_5V_OUT

S

S

HDMI Connector

HDMI_HPD

HDMI_SDATA
HDMI_SCLK

HDMI_R_CK­HDMI_R_CK+

HDMI_R_D0­HDMI_R_D0+

HDMI_R_D1­HDMI_R_D1+

HDMI_R_D2­HDMI_R_D2+

D7

2 1

RB491D_SOT23

U1H@

19
18
17
16
15
14
13
12
11
10

1

C274

U1H@

0.1U_0402_16V4Z

2

JHDMI

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CK-

GND

CK_shield

GND

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

FOX_QJ1119L-NT02-7F

20
21

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

HDMI

U1 LA-4381P

16 41Wednesday, January 16, 2008

E

0.0

of

5

+3VALW

C591

1 2

0.1U_0402_16V7K~N

5

NB_RST#

D D

U28

4

Y

NC7SZ08P5X_NL_SC70-5

P

B
A

G

3
U1H@

A_RST#

2
1

0.1A

C C

B B

A A

+1.2V_HT

NB_RST#<11,23,24,25,28>
SB_RX0P<10>

SB_RX0N<10>

SB_RX1P<10>

SB_RX1N<10>

SB_RX2P<10>

SB_RX2N<10>

SB_RX3P<10>

SB_RX3N<10>

SB_TX0P<10>
SB_TX0N<10>
SB_TX1P<10>
SB_TX1N<10>
SB_TX2P<10>
SB_TX2N<10>
SB_TX3P<10>
SB_TX3N<10>

18P_0402_50V8J~N

18P_0402_50V8J~N

L25

1 2

BLM21A601SPT_0805

R425
20M_0603_5%

C579

1 2

C580

1 2

CPU_PROCHOT#<6>

NB_RST#
SB_RX0P

SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

12

12

R426

20M_0603_5%

@

CPU_LDT_REQ#<6,11>

CPU_PWRGD<6>

LDT_STOP#<6,11>

LDT_RST#<6>

4

R464 33_0402_5%

C345 0.1U_0402_16V7K
C363 0.1U_0402_16V7K
C600 0.1U_0402_16V7K
C599 0.1U_0402_16V7K
C601 0.1U_0402_16V7K
C595 0.1U_0402_16V7K
C343 0.1U_0402_16V7K
C344 0.1U_0402_16V7K

+PCIE_VDDR

+PCIE_PVDD

1

2

C34122U_0805_6.3V6M

C3421U_0603_10V6K

2

1

CLK_SBSRCCLK<14>
CLK_SBSRCCLK#<14>

Y5

4

OUT

NC

1

IN

NC

32.768KHZ_12.5PF_1TJS125BJ4A421P

R428 10K_0402_5%@

+1.8VS

1 2

U1L@

12

R452 562_0402_1%
R166 2.05K_0402_1%

3
2

CPU_LDT_REQ#

LDT_RST#

A_RST#
SB_RX0P_C

SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

12
12

CLK_SBSRCCLK
CLK_SBSRCCLK#

SB_32KHI

SB_32KH0

3

USB700A

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

25M_X2

A3

X1

B3

X2

SB700

Part 1 of 5

PCI EXPRESS INTERFACE

RTC XTAL

F23

ALLOW_LDTSTP

F24

PROCHOT#

F22

LDT_PG

G25

LDT_STP#

G24

LDT_RST#

218S7EALA11FG_BGA528_SB700~D

CPU

PCICLK5/GPIO41

PCI CLKS

PCI INTERFACE

REQ3#/GPIO70
REQ4#/GPIO71

GNT3#/GPIO72
GNT4#/GPIO73

INTE#/GPIO33

CLOCK GENERATOR

INTF#/GPIO34

INTG#/GPIO35

INTH#/GPIO36

LPC

LDRQ1#/GNT5#/GPIO68

BMREQ#/REQ5#/GPIO65

INTRUDER_ALERT#

RTC

P4

PCICLK0

P3

PCICLK1

P1

PCICLK2

P2

PCICLK3

T4

PCICLK4

T3

N1

PCIRST#

U2

AD0

P7

AD1

V4

AD2

T1

AD3

V3

AD4

U1

AD5

V1

AD6

V2

AD7

T2

AD8

W1

AD9

T9

AD10

R6

AD11

R7

AD12

R5

AD13

U8

AD14

U5

AD15

Y7

AD16

W8

AD17

V9

AD18

Y8

AD19

AA8

AD20

Y4

AD21

Y3

AD22

Y2

AD23

AA2

AD24

AB4

AD25

AA1

AD26

AB3

AD27

AB2

AD28

AC1

AD29

AC2

AD30

AD1

AD31

W2

CBE0#

U7

CBE1#

AA7

CBE2#

Y1

CBE3#

AA6

FRAME#

W5

DEVSEL#

AA5

IRDY#

Y5

TRDY#

U6

PAR

W6

STOP#

W4

PERR#

V7

SERR#

AC3

REQ0#

AD4

REQ1#

AB7

REQ2#

AE6
AB6
AD2

GNT0#

AE4

GNT1#

AD5

GNT2#

AC6
AE5
AD6

CLKRUN#

V5

LOCK#

AD3
AC4
AE2
AE3

G22

LPCCLK0

E22

LPCCLK1

H24

LAD0

H23

LAD1

J25

LAD2

J24

LAD3

H25

LFRAME#

H22

LDRQ0#

AB8
AD7
V15

SERIRQ

C3

RTCCLK

C2
B2

VBAT

0.1U_0402_16V7K~N

PCICLK0_R
PCICLK1_R
PCICLK2_R
PCICLK3_R
PCICLK4_R
PCICLK5_R

PCIRST#

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0

PCI_GNT#0

PM_CLKRUN#
LOCK#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LDRQ0#
LDRQ1#

SIRQ

RTC_CLK

R167 22_0402_5%

1 2

R450 22_0402_5%

1 2

R448 22_0402_5%

1 2

R451 22_0402_5%

1 2

R427 22_0402_5%

1 2

R403 22_0402_5%

1 2

C581

+SB_VBAT

2

C585
1U_0603_10V6K

1

1

2

2

PCICLK2_R <21>
PCICLK3_R <21>

CLK_PCI_TPM

R449

1 2

33_0402_5%

PCI_AD[0..31]

PCI_CBE#0 <22>
PCI_CBE#1 <22>
PCI_CBE#2 <22>
PCI_CBE#3 <22>
PCI_FRAME# <22>
PCI_DEVSEL# <22>
PCI_IRDY# <22>
PCI_TRDY# <22>
PCI_PAR <22>
PCI_STOP# <22>
PCI_PERR# <22>
PCI_SERR# <22>
PCI_REQ#0 <22>

PCI_GNT#0 <22>

PM_CLKRUN# <22,28>

TP35

PCI_PIRQE# <22>

PCI_PIRQF# <22>

TP39
TP38

LPC_CLK0 <21>

LPC_AD0 <24,28>
LPC_AD1 <24,28>
LPC_AD2 <24,28>
LPC_AD3 <24,28>

LPC_FRAME# <24,28>

TP48
TP49

SIRQ <22,28>

RTC_CLK <21>

LPC_CLK1 <21>

PCI_RST#

CLK_PCI_EC <28>
CLK_PCI_MINI <24>

CLK_PCI_CB <22>

PCI_RST# <22,24>

PCI_AD[0..31] <21,22>

JBATT1

2

-

+SB_VBAT

PCICLK4_R
PCICLK5_R

ACES_20385-0001

CONN@

R78
510_0603_5%

1 2

CLK_PCI_MINI
CLK_PCI_CB
CLK_PCI_EC
CLK_PCI_TPM

+

1

+

W=20mils

1

C593 10P_0402_25V8K@
C592 10P_0402_25V8K@
C331 10P_0402_25V8K@
C594 10P_0402_25V8K@

+3VS +3VS

12

R185
10K_0402_5%

@

12

R184
10K_0402_5%

@

Reserved

RTC_BAT_PWR

R79

0_0603_5%

1 2

@

3

CLR_CMOS <29>

1 2
1 2
1 2
1 2

1

D4
BAS40-04_SOT23-3

2

12

R169
10K_0402_5%

@

12

R168
10K_0402_5%

@

CHGRTC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

U1 LA-4381P

SB700-PCI_EXP/PCI/LPC/RTC

of

1

17 41Wednesday, January 16, 2008

0.0

5

4

3

2

1

USB700D

SB700

ACPI / WAKE UP EVENTS

USB OC

HD AUDIO

INTEGRATED uC

1 2
1 2

R162 0_0402_5%@

R43733_0402_5%
R44133_0402_5%

R15833_0402_5%
R17133_0402_5%

+3VS_VDD33_18

12

EC_SWI#
EC_SCI#

SLP_S3#
SLP_S5#
PWRBTN_OUT#
SB_PWRGD
SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0
EC_GA20
KB_RST#

PCIE_WAKE#
H_THERMTRIP#

NB_PWRGD_SB
EC_RSMRST#

SB_SPKR
SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

1 2

SB_HD_BITCLK
SB_HD_SDOUT
HD_SDIN0

HD_SDIN3
SB_HD_SYNC
SB_HD_RST#

12

10K_0402_5%
R436

EC_SWI#<28>
EC_SCI#<28>

SLP_S3#<28>
SLP_S5#<28>

PWRBTN_OUT#<28>

D D

R147 100K_0402_5%

1 2

+3VS

R440 10K_0402_5%

1 2

R192 10K_0402_5%

1 2

R491 2.2K_0402_5%

1 2

R490 2.2K_0402_5%

1 2

+3VALW

C C

B B

R438 2.2K_0402_5%@

1 2

R160 2.2K_0402_5%@

1 2

R159 2.2K_0402_5%@

1 2

R161 2.2K_0402_5%

1 2

R170 2.2K_0402_5%

1 2

EC_RSMRST#

SUS_STAT#
SB_SPKR

SMB_CK_CLK0
SMB_CK_DAT0

SB_TEST0
SB_TEST1
SB_TEST2
SMB_CK_CLK1
SMB_CK_DAT1

DDR/CLK

SB_PWRGD<6,11,28>
SUS_STAT#<11>

EC_GA20<28>
KB_RST#<28>

PCIE_WAKE#<22,24,25,28>
H_THERMTRIP#<6>

NB_PWRGD_SB<11>

EC_RSMRST#<28>

SB_SPKR<27>
SMB_CK_CLK0<8,9,14>
SMB_CK_DAT0<8,9,14>
SMB_CK_CLK1<24>
SMB_CK_DAT1<24>

SMB_ALERT#<6>

EC_SMI#<28>

NC_PWR_EN#<24>

EC_LID_OUT#<28>

OVCUR#3<30>

TP33

OVCUR#1<30>

OVCUR#0<30>

HD_BITCLK<27>
HD_SDOUT<27>

TP34

HD_SDIN3<27>
HD_SYNC<27>
HD_RST#<21,27>

IDE_RST#<23>

R492 10K_0402_5%
R182 10K_0402_5%

EC_SMI#
NC_PWR_EN#
EC_LID_OUT#
OVCUR#3

OVCUR#1
OVCUR#0

1 2
1 2

1 2
1 2

R429 0_0402_5%

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVENT2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMATVOLT1/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SMARTVOLT2/SHUTDOWN#/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

H19

IMC_GPIO0

H20

IMC_GPIO1

H21

SPI_CS2#/IMC_GPIO2

F25

IDE_RST#/F_RST#/IMC_GPO3

D22

IMC_GPIO4

E24

IMC_GPIO5

E25

IMC_GPIO6

D23

IMC_GPIO7

218S7EALA11FG_BGA528_SB700~D

Part 4 of 5

USBCLK/14M_25M_48M_OSC

INTEGRATED uC

USB_RCOMP

USB_FSD13P

USB MISC

USB_FSD13N
USB_FSD12P

USB_FSD12N

USB 1.1

USB_HSD11P

USB_HSD11N

USB_HSD10P

USB_HSD10N

USB_HSD9P

USB_HSD9N

USB_HSD8P

USB_HSD8N

USB_HSD7P

USB_HSD7N

USB_HSD6P

USB_HSD6N

USB_HSD5P

USB_HSD5N

USB_HSD4P

USB 2.0

USB_HSD4N

USB_HSD3P

GPIO

USB_HSD3N

USB_HSD2P

USB_HSD2N

USB_HSD1P

USB_HSD1N

USB_HSD0P

USB_HSD0N

IMC_GPIO8
IMC_GPIO9

IMC_PWM0/IMC_GPIO10

SCL2/IMC_GPIO11
SDA2/IMC_GPIO12

SCL3_LV/IMC_GPIO13

SDA3_LV/IMC_GPIO14

IMC_PWM1/IMC_GPIO15

IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

C8
G8

E6
E7

F7
E8

H11
J10

E11
F11

A11
B11

C10
D10

G11
H12

E12
E14

C12
D12

B12
A12

G12
G14

H14
H15

A13
B13

B14
A14

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

G20
G21
D25
D24
C25
C24
B25
C23

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

CLK_USBCLK_EXT

CLK_USBCLK_EXT <14>

1 2

USB20P11+
USB20P11-

USB20P10+
USB20P10-

USB20P9+ <24>
USB20P9- <24>

USB20P8+
USB20P8-

USB20P7+
USB20P7-

USB20P6+ <24>
USB20P6- <24>

USB20P5+
USB20P5-

USB20P4+ <29>
USB20P4- <29>

USB20P3+ <30>
USB20P3- <30>

USB20P2+ <30>
USB20P2- <30>

USB20P1+ <30>
USB20P1- <30>

USB20P0+ <30>
USB20P0- <30>

CPU_SIC_SB
CPU_SID_SB

GP16 <21>
GP17 <21>

R15711.8K_0402_1%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

U1 LA-4381P

2

Date: Sheet

SB700 USB/ACPI/AC97/GPIO

of

1

18 41Wednesday, January 16, 2008

0.0

5

4

3

2

1

D D

C C

C388

SATA_LED#<29>

+PLLVDD_ATA

1

1

C369

2

2

1U_0402_6.3V6K

12

R222
10M_0402_5%

Y2

1 2

0.1A

+1.2V_HT

KC FBM-L11-201209-221LMAT_0805

B B

25MHZ_12P_X8A025000FC1H-H

L31

1 2

C387

10P_0402_50V8J

10P_0402_50V8J

C375

12

12

SATA_DTX_IRX_P0
SATA_DTX_IRX_N0

SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

SATA_DTX_IRX_P1
SATA_DTX_IRX_N1

SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

R1831K_0402_1%

12

L30

1 2

+3VS

KC FBM-L11-201209-221LMAT_0805

1U_0402_6.3V6K

SATA_X1

SATA_X2

C351

SATA_CAL
SATA_X1
SATA_X2
SATA_LED#

+XTLVDD_ATA

1

2

USB700B

AD9

SATA_TX0P

AE9

SATA_TX0N

AB10

SATA_RX0N

AC10

SATA_RX0P

AE10

SATA_TX1P

AD10

SATA_TX1N

AD11

SATA_RX1N

AE11

SATA_RX1P

AB12

SATA_TX2P

AC12

SATA_TX2N

AE12

SATA_RX2N

AD12

SATA_RX2P

AD13

SATA_TX3P

AE13

SATA_TX3N

AB14

SATA_RX3N

AC14

SATA_RX3P

AE14

SATA_TX4P

AD14

SATA_TX4N

AD15

SATA_RX4N

AE15

SATA_RX4P

AB16

SATA_TX5P

AC16

SATA_TX5N

AE16

SATA_RX5N

AD16

SATA_RX5P

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

SATA_ACT#/GPIO67

AA11

PLLVDD_SATA

W12

XTLVDD_SATA

1U_0402_6.3V6K

218S7EALA11FG_BGA528_SB700~D

SB700

Part 2 of 5

SATA PWR SERIAL ATA

HW MONITOR

IDE_IORDY

IDE_IRQ

IDE_A0
IDE_A1
IDE_A2

IDE_DACK#

IDE_DRQ
IDE_IOR#

IDE_IOW#

IDE_CS1#
IDE_CS3#

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23

ATA 66/100/133

IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11

SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS1#/GPIO32

LAN_RST#/GPIO13

SPI ROM

ROM_RST#/GPIO14

FANOUT0/GPIO3

FANOUT1/GPIO48
FANOUT2/GPIO49

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

AVDD
AVSS

IDEIORDYA

AA24

IDEIRQA

AA25

IDESAA0

Y22

IDESAA1

AB23

IDESAA2

Y23

IDEDACK#A

AB24

IDEREQA

AD25

IDEIOR#A

AC25

IDEIOW#A

AC24

IDECS#A1

Y25

IDECS#A3

Y24

IDEDA0

AD24

IDEDA1

AD23

IDEDA2

AE22

IDEDA3

AC22

IDEDA4

AD21

IDEDA5

AE20

IDEDA6

AB20

IDEDA7

AD19

IDEDA8

AE19

IDEDA9

AC20

IDEDA10

AD20

IDEDA11

AE21

IDEDA12

AB22

IDEDA13

AD22

IDEDA14

AE23

IDEDA15

AC23

G6
D2
D1
F4
F3

U15
J1

M8
M5
M7

P5
P8
R8

TEMP_COMM 10mil trace

TEMP_COMM

C6

SB_NB_THRMDA

B6
A6
A5

EC_THERM_SB#

B5
A4

100P_0402_25V8K

B4
C4
D4
D5
D6
A7
B7

F6

1

G7

C569

C290

2

2.2U_0603_10V6K

TP37

C278

1

2

0.1U_0402_16V7K~N

IDEIORDYA <23>
IDEIRQA <23>
IDESAA0 <23>
IDESAA1 <23>

IDEDACK#A <23>
IDEREQA <23>
IDEIOR#A <23>
IDEIOW#A <23>
IDECS#A1 <23>
IDECS#A3 <23>

IDEDA[0..15] <23>

+3VS

R394
10K_0402_5%

1 2

4.7K_0402_5%

TEMP_COMM

MBK1608301YZF_0603

L50

1 2

1 2

R124 0_0402_5%

+5VS

12

+3VALW

R393

12

R383

4.7K_0402_5%

G

2

EC_THERM#

13

D

S

Q50 SSM3K7002FU_SC70-3

SB_NB_THRMDA <11>
SB_NB_THRMDC <11>

+3VALW

EC_THERM# <28>

SATA_DTX_IRX_N0

SATA_DTX_IRX_P0 SATA_DTX_C_IRX_P0

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0 SATA_ITX_C_DRX_P0

A A

SATA_DTX_IRX_N1

SATA_DTX_IRX_P1 SATA_DTX_C_IRX_P1

SATA_ITX_DRX_N1

SATA_ITX_DRX_P1

5

SATA_DTX_C_IRX_N0

12

C606 0.01U_0402_16V7K

12

C607 0.01U_0402_16V7K

SATA_ITX_C_DRX_N0

12

C614 0.01U_0402_16V7K

12

C613 0.01U_0402_16V7K

close to connector

SATA_DTX_C_IRX_N1

12

C609 0.01U_0402_16V7K

12

C608 0.01U_0402_16V7K

SATA_ITX_C_DRX_N1

12

C237 0.01U_0402_16V7K

SATA_ITX_C_DRX_P1

12

C236 0.01U_0402_16V7K

close to connector

4

SATA_DTX_C_IRX_N0 <23>

SATA_DTX_C_IRX_P0 <23>

SATA_ITX_C_DRX_N0 <23>

SATA_ITX_C_DRX_P0 <23>

SATA_DTX_C_IRX_N1 <23>

SATA_DTX_C_IRX_P1 <23>

SATA_ITX_C_DRX_N1 <23>

SATA_ITX_C_DRX_P1 <23>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

U1 LA-4381P

Date: Sheet

SB700 IDE/SATA

1

of

19 41Wednesday, January 16, 2008

0.0

+3VS

FBM-L11-321611-260-LMT_1206

L62

1 2

0.45A

+1.2V_HT

FBM-L11-321611-260-LMT_1206

0.8A

+3VS

+1.8VS

1 2

0.2A

+3VALW

KC FBM-L11-201209-221LMAT_0805

0.2A

KC FBM-L11-201209-221LMAT_0805

1 2

+3VS

1 2

@

1

C604

1 2

R482 0_0402_5%@

1 2

R483 0_0402_5%

L27

+1.2V_HT

KC FBM-L11-201209-221LMAT_0805

L51

L52

1

C365

C350

2

2

1U_0402_6.3V4Z

22U_0805_6.3VAM

+1.8VS : FLASH MEMORY MODE(DEFAULT)
+3VS : IDE MODE

+PCIE_VDDR

1

1

C303

C282

C573

2

22U_0805_6.3VAM

L61

1 2

1

C288

2

22U_0805_6.3VAM

2

1

2

C612

1

2

C322

1U_0402_6.3V4Z

C610

C307

1U_0402_6.3V4Z

C370

1U_0402_6.3V4Z

1

2

For A11 version this
power should connected to
+1.2VALW due to PWRBTN

1

2

1

2

C292

1U_0402_6.3V4Z

C570

1U_0402_6.3V4Z

C328

1U_0402_6.3V4Z

C305

2.2U_0603_10V6K

1

C283

2

1U_0402_6.3V4Z

1

2

1

2

0.1U_0402_16V7K~N

no response issue.

1

1

C329

2

1U_0402_6.3V4Z

1

C590

2

2.2U_0603_10V6K

1

2

22U_0805_6.3VAM

R163 0_0805_5%

R148 0_0805_5%@

1

2

22U_0805_6.3VAM

1

2

2.2U_0603_10V6K

C323

1U_0402_6.3V4Z

C589

2.2U_0603_10V6K

R119 0_0805_5%

R118 0_0805_5%@

R396
0_0805_5%@

R395
0_0805_5%

C586

2

1

2

1U_0402_6.3V4Z

C571

1U_0402_6.3V4Z

C306

0.6A

1

1

C325

C271

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

L26

1 2

KC FBM-L11-201209-221LMAT_0805

1

2

2.2U_0603_10V6K

+3VALW

12

0.01A

+3VS

12

+1.2VALW

0.22A

12

+1.2V_HT

12

+1.2V_HT

12

+1.2VALW

12

L57

1 2

KC FBM-L11-201209-221LMAT_0805

1

2

0.01A

2.2U_0603_10V6K

AB21

AA21
AA22
AE25

L9

M9

T15

U9

U16

U17

V8

W7

Y6
AA4
AB5

Y20

USB700C

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

SB700

Part 3 of 5

POWER

P18

PCIE_VDDR_1

P19

PCIE_VDDR_2

P20

PCIE_VDDR_3

P21

PCIE_VDDR_4

R22

PCIE_VDDR_5

R24

PCIE_VDDR_6

R25

PCIE_VDDR_7

AA14

AVDD_SATA_1

AB18

AVDD_SATA_4

AA15

AVDD_SATA_2

AA17

AVDD_SATA_3

AC18

AVDD_SATA_5

AD17

AVDD_SATA_6

AE17

AVDD_SATA_7

A16

AVDDTX_0

B16

AVDDTX_1

C16

AVDDTX_2

D16

AVDDTX_3

D17

AVDDTX_4

E17

AVDDTX_5

F15

AVDDRX_0

F17

AVDDRX_1

F18

AVDDRX_2

G15

AVDDRX_3

G17

AVDDRX_4

G18

AVDDRX_5

218S7EALA11FG_BGA528_SB700~D

PCI/GPIO I/O

IDE/FLSH I/O

A-LINK I/O

SATA I/O

PLL CLKGEN I/O

USB I/O

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8

CORE S0

VDD_9

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

3.3V_S5 I/OCORE S5

S5_1.2V_1
S5_1.2V_2

USB_PHY_1.2V_1
USB_PHY_1.2V_2

V5_VREF
AVDDCK_3.3V
AVDDCK_1.2V

AVDDC

L15
M12
M14
N13
P12
P14
R11
R15
T16

L21
L22
L24
L25

A17
A24
B17
J4
J5
L1
L2

G2
G4

A10
B10

+V5_VREF

AE7

+AVDDCK_3.3V

J16

+AVDDCK_1.2V

K17

+AVDDC

E9

C270

C327

C301

C285

1

2

1

2

C291

C572

1

2

C324

1U_0402_6.3V4Z

C302

10U_0805_6.3V6M

+3VALW_SB

1

C309

2

1U_0402_6.3V4Z

+1.2VALW_SB

1

2

+1.2V_USBPHY

1

2

C289

2.2U_0603_10V6K

+1.2V_VDD_SB

+1.2V_CKVDD

1

2

0.6A

1

C326

2

1U_0402_6.3V4Z

1

C347

2

22U_0805_6.3VAM

1

1

C319

2

2

1U_0402_6.3V4Z

1

1

C349

2

2

22U_0805_6.3VAM

1

1

C286

2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C611

1

2

C321

1U_0402_6.3V4Z

C366

1U_0402_6.3V4Z

C284

1U_0402_6.3V4Z

C348

1U_0402_6.3V4Z

1

2

1

2

C364

1U_0402_6.3V4Z

1

C304

2

1U_0402_6.3V4Z

1

C368

2

1U_0402_6.3V4Z

1

C308

2

0.1U_0402_16V7K~N

+3VS_VDDQ_SB

1

C352

2

1U_0402_6.3V4Z

+3VS_VDD33_18

1

C346

2

1U_0402_6.3V4Z

+PCIE_VDDR

1

C318

2

1U_0402_6.3V4Z

+1.2V_AVDD_SATA

1

C367

2

0.1U_0402_16V7K~N

+3VS_AVDDTX

1

C287

2

0.1U_0402_16V7K~N

1

C353

2

1U_0402_6.3V4Z

+3VS_VDD33_18

1

2

1U_0402_6.3V4Z

1

C320

2

0.1U_0402_16V7K~N

1

2

0.1U_0402_16V7K~N

1

2

0.1U_0402_16V7K~N

1

C330

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

0.1U_0402_16V7K~N

@

1 2

FBM-L11-321611-260-LMT_1206

1 2

FBM-L11-321611-260-LMT_1206

1

2

22U_0805_6.3VAM

+1.2V_HT

0.2A

+3VS

+1.2VALW

L22

+1.2V_HT

L23

USB700E

SB700

T10

AVSS_SATA_1

U10

AVSS_SATA_2

U11

AVSS_SATA_3

U12

AVSS_SATA_4

V11

AVSS_SATA_5

V14

AVSS_SATA_6

W9

AVSS_SATA_7

Y9

AVSS_SATA_8

Y11

AVSS_SATA_9

Y14

AVSS_SATA_10

Y17

AVSS_SATA_11

AA9

AVSS_SATA_12

AB9

AVSS_SATA_13

AB11

AVSS_SATA_14

AB13

AVSS_SATA_15

AB15

AVSS_SATA_16

AB17

AVSS_SATA_17

AC8

AVSS_SATA_18

AD8

AVSS_SATA_19

AE8

AVSS_SATA_20

A15

AVSS_USB_1

B15

AVSS_USB_2

C14

AVSS_USB_3

D8

AVSS_USB_4

D9

AVSS_USB_5

D11

AVSS_USB_6

D13

AVSS_USB_7

D14

AVSS_USB_8

D15

AVSS_USB_9

E15

AVSS_USB_10

F12

AVSS_USB_11

F14

AVSS_USB_12

G9

AVSS_USB_13

H9

AVSS_USB_14

H17

AVSS_USB_15

J9

AVSS_USB_16

J11

AVSS_USB_17

J12

AVSS_USB_18

J14

AVSS_USB_19

J15

AVSS_USB_20

K10

AVSS_USB_21

K12

AVSS_USB_22

K14

AVSS_USB_23

K15

AVSS_USB_24

H18

PCIE_CK_VSS_1

J17

PCIE_CK_VSS_2

J22

PCIE_CK_VSS_3

K25

PCIE_CK_VSS_4

M16

PCIE_CK_VSS_5

M17

PCIE_CK_VSS_6

M21

PCIE_CK_VSS_7

P16

PCIE_CK_VSS_8

F9

AVSSC

Part 5 of 5

218S7EALA11FG_BGA528_SB700~D

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42

GROUND

VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25

L17

0.1A

+5VS

+3VS

1 2

2 1

R489
1K_0402_5%

D28
RB751V-40TE17_SOD323-2

+V5_VREF

2

C605
1U_0402_6.3V4Z

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/12/12 2008/12/12

+AVDDCK_1.2V

+AVDDC

+AVDDC

Compal Secret Data

Deciphered Date

L24

1 2

KC FBM-L11-201209-221LMAT_0805

L21

1 2

KC FBM-L11-201209-221LMAT_0805

L20

1 2

KC FBM-L11-201209-221LMAT_0805@

+1.2V_HT

+3VALW

+3VS

Title

Size Document Number Rev

Custom

U1 LA-4381P

Date: Sheet

SB700 Power/GND

of

20 41Wednesday, January 16, 2008

0.0

5

4

3

2

1

PCI_CLK3

PULL
HIGH

PULL

D D

LOW

BOOTFAIL
TIMER
ENABLED

BOOTFAIL
TIMER
DISABLED

DEFAULT

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

PCI_CLK4 PCI_CLK5

RESERVED

RESERVED

LPC_CLK0

ENABLE PCI
MEM BOOT

DISABLE PCI
MEM BOOT

DEFAULT

CLKGEN
ENABLED

CLKGEN
DISABLED

DEFAULT

WITH A12 SB700, STRAP PIN FOR MEM BOOT AND EC ENABLE SWAPED.
I.E. LPC_CLK0 FOR EC ENABLE, AZ_RST# FOR MEM BOOT ENABLE.

RTC_CLKLPC_CLK1

INTERNAL
RTC

DEFAULT

EXT. RTC

(PD on X1,
apply
32KHz to
RTC_CLK)

AZ_RST#

EC
ENABLED

EC
DISABLED

DEFAULT

GP17

GP16PCI_CLK2

H,H = Reserved

H,L = SPI ROM

L,H = LPC ROM (Default)

L,L = FWH ROM

REQUIRED STRAPS

+3VALW+3VALW +3VALW +3VS +3VS+3VALW +3VALW+3VALW

12

R399

2.2K_0402_5%

@

GP17<18>
GP16<18>
HD_RST#<18,27>

RTC_CLK<17>
LPC_CLK0<17>
LPC_CLK1<17>
PCICLK2_R<17>

C C

PCICLK3_R<17>

12

R401

2.2K_0402_5%

12

R398

2.2K_0402_5%

12

R397

2.2K_0402_5%

12

R173
10K_0402_5%

@

12

R172

@

10K_0402_5%

DEBUG STRAPS

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

12

R477
10K_0402_5%

B B

PCI_AD31

PCI_AD29

TP41
TP40
TP36

PCI_AD28

No Stuff

12

R473

2.2K_0402_5%

12

R478

@

@

10K_0402_5%

No Stuff

12

R474

2.2K_0402_5%

12

R434
10K_0402_5%

12

R435

2.2K_0402_5%

@

12

R475

@

PCI_AD26PCI_AD30 PCI_AD24PCI_AD27 PCI_AD23PCI_AD25

@

No StuffNo Stuff

10K_0402_5%

@

No Stuff

12

R471

2.2K_0402_5%

@

No Stuff

@

@

No Stuff

12

R400
10K_0402_5%

@

12

R402
10K_0402_5%

+3VS +3VS+3VS+3VS +3VS+3VS

12

R465
10K_0402_5%

No Stuff

12

R466

2.2K_0402_5%

@

@

No Stuff

PCI_AD[0..31] <17,22>

12

R404
10K_0402_5%

@

12

R430
10K_0402_5%

PCI_AD[0..31]

12

R476
10K_0402_5%

No Stuff No Stuff

12

R472

2.2K_0402_5%

12

R188
10K_0402_5%

@

12

R174
10K_0402_5%

12

R467
10K_0402_5%

@

12

R468

2.2K_0402_5%

@

No Stuff

12

R186
10K_0402_5%

@

12

R187
10K_0402_5%

PCI_AD31

RESERVED

PULL
HIGH

PULL
LOW

A A

PCI_AD30 PCI_AD29 PCI_AD26

RESERVED RESERVED

PCI_AD28

USE LONG
RESET

USE SHORT
RESET

PCI_AD27

USE PCI
PLL

BYPASS
PCI PLL

USE ACPI
BCLK

BYPASS
ACPI
BCLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PCI_AD25

USE IDE
PLL

BYPASS IDE
PLL

2007/12/12 2008/12/12

PCI_AD24

USE DEFAULT
PCIE STRAPS

USE EEPROM
PCIE STRAPS

Compal Secret Data

PCI_AD23

RESERVED

Deciphered Date

Title

Size Document Number Rev

Custom

U1 LA-4381P

2

Date: Sheet

SB700 HW Strap

1

0.0

of

21 41Wednesday, January 16, 2008

5

PCI_AD[0..31]<17,21>

+3VS_CB

12

R301
100K_0402_5%

CBS_GRST#

D D

1

C456
1U_0603_10V6K

2

CLK_PCI_CB

@

10_0402_5%

12

R265

PCI_CBE#3<17>

R255

PCI_PAR<17>
PCI_FRAME#<17>
PCI_TRDY#<17>
PCI_IRDY#<17>
PCI_STOP#<17>
PCI_DEVSEL#<17>

1 2

CLK_PCI_CB<17>

+3VS_CB

PCI_CBE#2<17>
PCI_CBE#1<17>
PCI_CBE#0<17>

100_0402_5%

PCI_PERR#<17>
PCI_SERR#<17>

PCI_REQ#0<17>
PCI_GNT#0<17>

PCI_RST#<17,24>

1 2
1 2
1 2

@

4.7P_0402_50V8C

CLK_PCI_CB_TERM

C422

2

1

C C

B B

PCI_AD21 PCI_IDSEL

PM_CLKRUN#<17,28>

PCIE_WAKE#<18,24,25,28>

PCI_PIRQE#<17>
PCI_PIRQF#<17>

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

PCI_PERR#
PCI_SERR#

PCI_RST#

CBS_GRST#

R270 0_0402_5%@
R271 10K_0402_5%
R299 0_0402_5%@

R300 10K_0402_5%

1 2

12

R298

100K_0402_5%

Layout Note: Place close to R5C833 Chip

TPBIAS0

A A

R268

R276

C447

56.2_0603_1%

12

R269

56.2_0603_1%

12

R277

270P_0402_50V7K

R279

2

1

56.2_0603_1%

12

56.2_0603_1%

12

5.1K_0603_1%

1 2

5

0.01U_0402_16V7K
C439

C438

1

2

IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

0.33U_0603_10V7K

1

2

P-TWO_CU8042-A0G1G-P

U17

125

AD31

126

AD30

127

AD29

1

AD28

2

AD27

3

AD26

5

AD25

6

AD24

9

AD23

11

AD22

12

AD21

14

AD20

15

AD19

17

AD18

18

AD17

19

AD16

36

AD15

37

AD14

38

AD13

39

AD12

40

AD11

42

AD10

43

AD9

44

AD8

46

AD7

47

AD6

48

AD5

49

AD4

50

AD3

51

AD2

52

AD1

53

AD0

7

C/BE3#

21

C/BE2#

35

C/BE1#

45

C/BE0#

33

PAR

23

FRAME#

25

TRDY#

24

IRDY#

29

STOP#

26

DEVSEL#

8

IDSEL

30

PERR#

31

SERR#

124

REQ#

123

GNT#

121

PCICLK

119

PCIRST#

71

GBRST#

117

CLKRUN#

70

PME#

115

INTA#

116

INTB#

69

HWSPND#

66

TEST

99

AGND

102

AGND

103

AGND

107

AGND

111

AGND

97

RSV

R5C833-TQFP128P_TQFP128_14X14~D

J139A1

4

TPA+

3

TPA-

2
1

CONN@

TPB+
TPB-

GND
GND

6
5

R5C833

2007-02-12 Protect Circuit for ALPS conn

SDDATA1_MSDATA1_XDDATA1
SDDET#_XDDET0#

SDDATA2_MSDATA2_XDDATA2
SDDET#_XDDET0#

+3VS

SD_EN

10K_0402_1%

12

R225

4

VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V

VCC_RIN

VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT

VCC_3V

VCC_MD3V

AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V

TPBIAS0

TPAP0
TPAN0

TPBP0
TPBN0

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

MSEN

XDEN

XI

XO

FIL0
REXT
VREF

UDIO0/SRIRQ#

UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

U14

3

VIN

VOUT

4

VIN/CE

VOUT

2

GND

RT9701-CB_SOT23-5

4

10
20
27
32
41
128

61

VCC_ROUT

16
34
64
114
120

67
86

+3VS_PHY

98
106
110
112

TPBIAS0

113

IEEE1394_TPAP0

109

IEEE1394_TPAN0

108

IEEE1394_TPBP0

105

IEEE1394_TPBN0

104

SDDET#_XDDET0#

80

MSDET#_XDDET1#

79

XDCE#

78

SDWP#_XDRB#

77

SD_EN

76

XDWP

75
74
73

SDCMD_MSBS_XDWE#

88

R302 0_0402_5%

84

1 2

SDDATA0_MSDATA0_XDDATA0

82

SDDATA1_MSDATA1_XDDATA1

81

SDDATA2_MSDATA2_XDDATA2

93

SDDATA3_MSDATA3_XDDATA3

90

XDDATA4

91

XDDATA5

89

XDDATA6

92

XDDATA7

87

XDCLE

85

XDALE

83
58

55
94

95
96

101
100

72
60
56
65

UDIO4

59

UDIO5

57
4

13
22
28
54
62
63
68
118
122

U12

VCC

2

B

4

OE

GND

SN74CBT1G384_SOT23-5

U13

VCC

2

B

4

OE

GND

SN74CBT1G384_SOT23-5

1
5

1

C390

2

0.01U_0402_16V7K

C455

1

2

+3VS_CB

0.01U_0402_16V7K

C413

1

2

R5C833XI
R5C833XO

C460 0.01U_0402_16V7K

R267 10K_0402_5%
R274 100K_0402_5%

+5VS

5

SD_MS_XDDATA1

1

A

3

+5VS

5

SD_MS_XDDATA2

1

A

3

10U_0805_6.3V6M

1

C423

2

SDCLK_MSCLK_XDRE#

1 2

@

SIRQ <17,28>

+3VS_CB

1 2
1 2

+3VS_SD

1

C397

2

1U_0603_10V6K

0.01U_0402_16V7K

0.01U_0402_16V7K

C428

1

2

CARD_LED# <29>

+3VS_SD

+3VS_SD

3

0.01U_0402_16V7K

0.01U_0402_16V7K

C414

C457

1

1

2

2

10U_0805_6.3V6M

C436

1

1

C452

2

2

Layout Note: Place close to
R5C833 and Shield GND.

Place close to JSD1.

+3VS_SD

C376

R214 100_0402_5%

1 2

R213 100_0402_5%

1 2

R204 39_0402_5%

1 2

R203 100_0402_5%

1 2

R202 100_0402_5%

1 2

R215 100_0402_5%

1 2

R211 22_0402_5%

1 2

R210 100_0402_5%

1 2

R209 100_0402_5%

1 2

R208 100_0402_5%

1 2

R207 100_0402_5%

1 2

R206 100_0402_5%

1 2

R205 100_0402_5%

1 2

R234 100K_0402_5%

1 2

R295 100K_0402_5%

1 2

2007/12/12 2008/12/12

10U_0805_6.3V6M

1

2

1 2

12

0.01U_0402_16V7K

C421

C415

1

2

L36

R275
10K_0402_5%

+3VS
+3VS

+3VS_CB

0.1U_0402_16V7K~N

C445

1

C461

2

+3VS_CB

BLM21AG601SN1D_0805~D

Layout Note:
Place close to R5C833.

0.01U_0402_16V7K

C446

1

2

SDDATA3_MSDATA3_XDDATA3
SDCMD_MSBS_XDWE#

SDCLK_MSCLK_XDRE#
SDDATA0_MSDATA0_XDDATA0

SD_MS_XDDATA1
SD_MS_XDDATA2

SDCLK_MSCLK_XDRE#
SDDATA3_MSDATA3_XDDATA3
MSDET#_XDDET1#
SDDATA2_MSDATA2_XDDATA2
SDDATA0_MSDATA0_XDDATA0
SDDATA1_MSDATA1_XDDATA1
SDCMD_MSBS_XDWE#

SDDET#_XDDET0#
SDWP#_XDRB#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

0.01U_0402_16V7K

C416

1

1

2

2

+3VS_PHY

0.1U_0402_16V7K~N

0.01U_0402_16V7K

C451

1

2

C458

12

15P_0402_50V8J

C459

12

15P_0402_50V8J

0.01U_0402_16V7K

C378

1

1

2

2

+3VS_CB

R254
0_0805_5%

0.01U_0402_16V7K

10U_0805_6.3V6M

C412

1

2

1000P_0402_50V7K~N

C437

1

2

X1

24.576MHz_16P_3XG-24576-43E1

1 2

0.01U_0402_16V7K

0.01U_0402_16V7K

12

C377

1

R212
150K_0402_5%

2

24
22
20
19

8
6
4
3

25

18
17
16
15
14
13
12
11
10

9

1
2

46

Compal Secret Data

Deciphered Date

2

+3VS

12

VCC_ROUT

R5C833XI

R5C833XO

JSD1

CD/D3
CMD
VSS
VDD
CLK
VSS
D0
D1
D2

VSS
VCC
SCLK
MS-D3
INS
MS-D2
MS-D0
MS-D1
BS
VSS

CD_SW
COMMDN
WP_SW

ALPS_SCDE2B0101_46P

CONN@

C429

0.01U_0402_16V7K

C435

1

2

2

1

2

0.01U_0402_16V7K

+3VS_SD

GND

R/-B

-WE

-WP

GND

VCC

GND

SD,MMC,MS,XD muti-function pin define

Media I/F XD Card
MDIO00

SD Card

SDCD#
MDIO01
MDIO02

C450

MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08

0.47U_0603_16V7K

C420

1

1

2

2

MDIO09

0.47U_0603_16V7K

MDIO10
MDIO11
MDIO12
MDIO13

SDWP#

SDPWR0

SDPWR1

SDLED#

MTEST

SDCCMD

SDCCLK

SDCDAT1

SDCDAT2

MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19 XDALE

Function set pin define

UDIO4UDIO3 XDEN

Pull-up

XDDET0#

MSDET#_XDDET1# XDDET0#

SDDET#_XDDET0#

R293 100_0402_5%

28

CD

-RE

-CE
CLE
ALE

D0
D1
D2
D3
D4
D5
D6
D7

NC
NC
NC
NC

1 2

R278 0_0402_5%

27

1 2

R294 100_0402_5%

29

1 2

R292 22_0402_5%

30

1 2

R304 100_0402_5%

31

1 2

R303 100_0402_5%

32

1 2

R316 100_0402_5%

33

1 2

R314 100_0402_5%

34

1 2

R315 100_0402_5%

35

1 2

36

R313 100_0402_5%

37

1 2

R312 100_0402_5%

38

1 2

R311 100_0402_5%

39

1 2

R296 100_0402_5%

40

1 2

R297 100_0402_5%

41

1 2

R291 100_0402_5%

42

1 2

R290 100_0402_5%

43

1 2

R289 100_0402_5%

44

1 2

45

5
7
23
21

26

Pull-up Pull-up Pull-up

R236

12

0_0805_5%@

D

S

13

Q29

SI2303BDS-T1-E3_SOT23-3~D

G

2

+3VS_CB

12

D8
RB751V_SOD323

2 1

2 1

D9
RB751V_SOD323

XDDET0#
SDWP#_XDRB#

SDCLK_MSCLK_XDRE#
XDCE#
XDCLE
XDALE
SDCMD_MSBS_XDWE#
XDWP

SDDATA0_MSDATA0_XDDATA0
SDDATA1_MSDATA1_XDDATA1
SDDATA2_MSDATA2_XDDATA2
SDDATA3_MSDATA3_XDDATA3

XDDATA4
XDDATA5
XDDATA6
XDDATA7

Title

Size Document Number Rev

Wednesday, January 16, 2008

Date: Sheet

1

MMC Card
MMCCD#

MMCPWR

MMCLED#

MMCCMD
MMCCLK
MMCDAT0
MMCDAT1
MMCDAT2
MMCDAT3
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7

MSEN

+3VS_XD

R235
33K_0402_5%

SDCLK_MSCLK_XDRE#

12

@

2

@

1

+3VS_XD

+3VS

12

@

R224
33K_0402_5%

R5C833 Media Card/1394

U1 LA-4381P

1

MS Card

XDCD0#

MSCD#

XDCD1#
XDCE#
XDR/B#

MSWR

XDPWR
XDWP#

MSLED#

MSBS
MSCCLK
MSCDAT0
MSCDAT1
MSCDAT2
MSCDAT3SDCDAT3

XDLED#

XDWE#

XDRE#
XDCDAT0SDCDAT0
XDCDAT1
XDCDAT2
XDCDAT3
XDCDAT4
XDCDAT5
XDCDAT6
XDCDAT7

XDCLE

Function
Enable

SD,XD,MS,MMC Card

R223
10_0402_5%

C389

4.7P_0402_50V8C

+3VS_XD

12

R305

2.2K_0402_5%

@

XDCE#SDCMD_MSBS_XDWE#

of

22 41

0.0

5

4

3

2

1

CDROM CONN

D D

+5VS

1

C162

2

Close to ODD Conn

10U_0805_10V4Z~N

C C

1

C180

2

1U_0603_10V6K

1

C163

2

0.1U_0402_16V7K~N

1

C181

2

1000P_0402_50V7K~N

Pin2, 20 is NC for Flash module

+1.8VS_FLASH

IDEDA[0..15]<19>

IDEDA[0..15]

SATA_DTX_C_IRX_P1<19>
SATA_DTX_C_IRX_N1<19>

SATA_ITX_C_DRX_N1<19>
SATA_ITX_C_DRX_P1<19>

SATA_DTX_C_IRX_P0<19>
SATA_DTX_C_IRX_N0<19>

SATA_ITX_C_DRX_N0<19>
SATA_ITX_C_DRX_P0<19>

SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N1

SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1

+5VS

SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0

SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0

+3VS

SATA HDD CONN

80mils

+5VS

IDECS#A3<19>

IDEIRQA<19>

B B

A A

IDEIRQA

IDEDACK#A<19>

IDEIOR#A<19>

IDEREQA<19>

R227

8.2K_0402_5%

1 2

NB_RST#<11,17,24,25,28>

IDE_RST#<18>

D10 RB751V-40TE17_SOD323-2

D11 RB751V-40TE17_SOD323-2

@

5

IDEDACK#A

IDEIOR#A

IDEREQA
IDEDA15 IDEDA1
IDEDA14

IDEDA13
IDEDA12

IDEDA11
IDEDA10

IDEDA9
IDEDA8

+3VS

12

R246
20K_0402_1%

21

21

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

41

IDE_FLASH_RST#

JHF1

PDCS3#

PDCS1#
PDA2
PIDE_INTR
PDACK#
RSVD

PDIORDY#
PDIOR#
RSVD

PDIOW#
PDREQ
PDD15
PDD14
RSVD
PDD13
PDD12
RSVD
PDD11
PDD10
RSVD
PDD9
PDD8

F_RST#

PDDMA66
GND

MOLEX_78188-0001~D

CONN@

PDA0

RSVD

PDA1
RSVD
PDD0

PDD1
PDD2
RSVD
PDD3
PDD4
RSVD
PDD5
PDD6
RSVD
PDD7

RSVD

GND

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

42

4

IDECS#A1IDECS#A3

IDESAA0
IDESAA1

IDEIOW#A
IDEDA0

IDEDA2
IDEDA3

IDEDA4
IDEDA5

IDEDA6

IDEDA7

IDE_FLASH_RST#

IDECS#A1 <19>

IDESAA0 <19>
IDESAA1 <19>

IDEIORDYA <19>

IDEIOW#A <19>

+1.8VS_FLASH +1.8VS

12

L32

26ohm 500mA

BLM31AJ260SN1L_1206~D

1

1

C407

1U_0402_6.3V6K

2

2007/12/12 2008/12/12

C40522U_0805_6.3V6M

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C406

1U_0402_6.3V6K

2

Compal Secret Data

Deciphered Date

2

C394

+5VS

+

+3VS

C403

1

150U_D2_6.3VM

C373

2

10U_0805_10V4Z~N@

1

2

0.1U_0402_16V7K~N@

1

2

10U_0805_10V4Z~N

C396

Title

Size Document Number Rev

Custom

Date: Sheet

JODD1

1

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

DP

9

5V

10

5V

11

MD

12

GND

13

GND

SUYIN_127382FR013S52_NR

JSATA1

S1

GND

S2

HTX+

S3

HTX-

S4

GND

S5

HRX-

S6

HRX+

S7

GND

P1

VCC3.3

P2

VCC3.3

P3

VCC3.3

P4

GND

P5

GND

P6

GND

P7

VCC5

P8

VCC5

P9

VCC5

P10

GND

P11

RESERVED

P12

GND

P13

VCC12

P14

VCC12

P15

VCC12

SUYIN_127043FR022G226ZL

CONN@

1

C374

2

0.1U_0402_16V7K~N

Close to SATA HDD

0.1U_0402_16V7K~N@

1

2

C395

1

2

14

GND

15

GND

27

NC

28

NC

23

GND

24

GND

25

GND

26

GND

0.1U_0402_16V7K~N

1

C385

2

1000P_0402_50V7K~N

1

C404

2

1000P_0402_50V7K~N@

SATA HDD/CDROM
U1 LA-4381P

1

C386

1

2

0.0

of

23 41Wednesday, January 16, 2008

CLK_PCI_MINI

12

R53

10_0402_5%@

2

C34
10P_0402_25V8K

1

@

Mini-Express Card

+3VALW

+1.5VS

JMINI1

1

1

WLAN_P#<28>

CLKREQ_MINICARD#<14>

CLK_PCIE_WCARD#<14>

CLK_PCIE_WCARD<14>

PCI_RST#<17,22>

CLK_PCI_MINI<17>

PCIE_WLAN_C_RX_N1<10>
PCIE_WLAN_C_RX_P1<10>

PCIE_WLAN_C_TX_N1<10>

PCIE_WLAN_C_TX_P1<10>

PCI_RST#
CLK_PCI_MINI

R51 0_0402_5%

1 2

R52 0_0402_5%

1 2

1 2

R44 0_0402_5%

1 2

R43 0_0402_5%

R49 0_0402_5%

1 2

R50 0_0402_5%

1 2

PCIE_C_RXN1

PCIE_C_RXP1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

ACES_88911-5204

CONN@

GND2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

+3VS

1 2
1 2
1 2
1 2
1 2

W_DISABLE#
NB_RST#

SMB_CK_CLK1
SMB_CK_DAT1

USB20P9­USB20P9+

LED_WLAN#

LPC_FRAME#

R420_0402_5%

LPC_AD3

R450_0402_5%

LPC_AD2

R460_0402_5%

LPC_AD1

R470_0402_5%

LPC_AD0

R480_0402_5%

W_DISABLE# <28,29>
NB_RST# <11,17,23,25,28>

USB20P9- <18>
USB20P9+ <18>

LED_WLAN# <29>
12

+3VS

R15310K_0402_5%

LPC_FRAME# <17,28>
LPC_AD3 <17,28>
LPC_AD2 <17,28>
LPC_AD1 <17,28>
LPC_AD0 <17,28>

2

C41

0.1U_0402_16V7K~N

1

2

C44

0.1U_0402_16V7K~N

1

2

C32

0.1U_0402_16V7K~N

1

2

C33

0.1U_0402_16V7K~N

1

+1.5VS +3VALW

1

C40
10U_0805_10V4Z~N

2

1

C43
10U_0805_10V4Z~N

2

+3VS

2

C35

0.1U_0402_16V7K~N

1

Placement Closed to JMINI1

2

C36

0.1U_0402_16V7K~N

1

New Card

+3V_CARD_AUX

1.5Vout

1.5Vout

3.3Vout

3.3Vout

OC#

PERST#

GND

+1.5V_CARD

11
13

3
5

15
19
8
16

NC

7

1A 1.5A

1

1

PCIE_PERST#

1

C3170.1U_0402_16V7K~N

2

C30010U_0805_6.3V6M

C3160.1U_0402_16V7K~N

2

2

C3140.1U_0402_16V7K~N

+3V_CARD

10U_0805_6.3V6M

1

2

1

C3600.1U_0402_16V7K~N

C362

2

+3V_CARD_AUX

0.5A

1

C3130.1U_0402_16V7K~N

2

1

1

C3610.1U_0402_16V7K~N

2

2

+3V_CARD +1.5V_CARD

JEXP1

1
USB20P6-<18>
USB20P6+<18>

SMB_CK_CLK1<18>
SMB_CK_DAT1<18>

PCIE_WAKE#<18,22,25,28>

CLKREQ_54CARD#<14>

NC_PWR_EN#<18>

CLK_PCIE_CARD#<14>

CLK_PCIE_CARD<14>

PCIE_CARD_C_RX_N2<10>
PCIE_CARD_C_RX_P2<10>

PCIE_CARD_C_TX_N2<10>
PCIE_CARD_C_TX_P2<10>

SMB_CK_CLK1
SMB_CK_DAT1

NC_PWR_EN#

PCIE_CARD_C_RX_N2
PCIE_CARD_C_RX_P2

PCIE_CARD_C_TX_N2
PCIE_CARD_C_TX_P2

R442 0_0402_5%
R443 0_0402_5%

NC_CPUSB#

R453 0_0402_5%
R470 0_0402_5%

R469 0_0402_5%

PCIE_PERST#

R484 0_0402_5%
R485 0_0402_5%

1 2

1 2
1 2

12
12

12
12

USB20P6-_R
USB20P6+_R

NC_CPPE#

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

FOX_1CH4310C-KL_RB

GND

GND

GND
GND

+3VALW

1

1

C3590.1U_0402_16V7K~N

C3400.1U_0402_16V7K~N

2

NB_RST#<11,17,23,25,28>

SYSON<28,32,37>
SUSP#<28,32,38,39>

R165 100K_0402_5%@

1 2

R181 100K_0402_5%@

1 2

2

27

28

29
30

+3VALW

NB_RST#

NC_PWR_EN#
NC_CPUSB#

+1.5VS+3VS

1

C3150.1U_0402_16V7K~N

2

U9

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

P2231NF_QFN20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

KB / TP / Express Card
U1 LA-4381P

24 41Wednesday, January 16, 2008

of

0.0

5

Layout Notice : 1.2V filter. Place as close
chip as possible.

+1.2VLAN

2

C496

C503

2

2

C498

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

C497

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

12

12

2

C15

1

C508

C506

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

2

1

2

1

2

C502

1

0.1U_0402_16V4Z

2

C509

1

0.1U_0402_16V4Z

+BIASVDDH

C17

0.1U_0402_16V4Z

+XTALVDDH

C499

0.1U_0402_16V4Z

+AVDDH

C16

0.1U_0402_16V4Z

2

C510

D D

C C

1

4.7U_0805_6.3V6K

Layout Notice : 3.3V filter. Place as close
chip as possible.

+3VLAN

2

C20

1

4.7U_0805_10V4Z~N

Layout Notice : Filter place as close
chip as possible.

+3VLAN

L41 FBM-L11-160808-601LMT_0603

L46 FBM-L11-160808-601LMT_0603

L42 FBM-L11-160808-601LMT_0603

0.1U_0402_16V4Z

C501

C505

2

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

C507

2

C494

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

PCIE_LAN_C_RX_P0<10>
PCIE_LAN_C_RX_N0<10>

PCIE_LAN_C_TX_P0<10>
PCIE_LAN_C_TX_N0<10>

PCIE_WAKE#<18,22,24,28>

NB_RST#<11,17,23,24,28>

CLK_PCIE_LAN<14>

CLK_PCIE_LAN#<14>

4

+1.2VLAN_IO

+1.2VLAN

+AVDDL

+GPHY_PLLVDDL

+PCIE_PLLVDDL

+PCIE_VDDL

C21 0.1U_0402_16V7K~N
C26 0.1U_0402_16V7K~N

PCIE_MRX_C_LTX_P0

12

PCIE_MRX_C_LTX_N0

12

U5

5

VDDC_IO

55

VDDC_IO

13

VDDC

20

VDDC

34

VDDC

60

VDDC

39

AVDDL

45

AVDDL

51

AVDDL

35

GPHY_PLLVDDL

30

PCIE_PLLVDDL

27

PCIE_PLLVDDL

33

PCIE_VDDL

24

PCIE_VDDL

26

PCIE_TXD_P

25

PCIE_TXD_N

31

PCIE_RXD_P

32

PCIE_RXD_N

12

WAKE#

10

PERST#

29

PCIE_REFCLK_P

28

PCIE_REFCLK_N

+3VLAN

61

15

VDDIO6VDDIO56VDDIO

19

VDDIO

VDDIO

38

52

DC

DC

BIASVDDH

XTALVDDH

AVDDH
AVDDH

TRD3_N

TRD3_P

TRD2_N

TRD2_P

TRD1_N

TRD1_P

TRD0_N

TRD0_P

LINKLED#

SPD100LED#
SPD1000LED#
TRAFFICLED#

GPIO2

UART_MODE

GPIO1_SERIALDI

GPIO0_SERIALDO

SCLK_EECLK

SO_EEDATA

3

68

DC

36

+BIASVDDH

23

+XTALVDDH

48

+AVDDH

42

MDIN3

49

MDIP3

50

MDIN2

47

MDIP2

46

MDIN1

43

MDIP1

44

MDIN0

41

MDIP0

40
2

1
67
66

GPIO2

8

9

LAN_WP

7
4

LAN_CLK

65

SI

63

SI

LAN_DATA

64

CS#

62

CS#

MDIN3 <26>
MDIP3 <26>

MDIN2 <26>
MDIP2 <26>

MDIN1 <26>
MDIP1 <26>

MDIN0 <26>
MDIP0 <26>

1 2

R370_0402_5%@

0_0402_5%@
0_0402_5%@

R340 4.7K_0402_5%

1 2

R29 4.7K_0402_5%

1 2

R28 4.7K_0402_5%

1 2

R38

1 2

R360_0402_5%@

1 2
1 2

R35

EN_WOL#<28>

+3VLAN

2

R32

470K_0402_5%

SSM3K7002FU_SC70-3

2

G

B+_BIAS

1 2
13

D

Q6

S

1U_0603_10V6K

EN_WOL

LAN_WP
LAN_CLK
LAN_DATA

C23

@

1 2

+3VALW

1

2

R31

1.5M_0402_5%

CTL12

0.1U_0402_16V4Z

1

6
2

1

Q40

12

4.7K_0402_5%

@

R338

D

C512

Q5

G

2 3

R341

1 2

4.7K_0402_5%

1

L3

FBMA-L11-322513-201LMA40T_1210

S

45

1 2

SI3456BDV-T1-E3_TSOP6

3

+3VLAN

C30 0.1U_0402_16V4Z

1 2

C31 4.7U_0805_10V4Z~N

R33 1.5_1206_5%

MMJT9435T1G_SOT223-4~D

4

1

1

2

2

+3VLAN

12

1 2

+1.2VLAN

C511
10U_0805_10V4Z~N

1 2

C504 0.1U_0402_16V4Z

U21

8

VCC

7

WP

6

SCL

5

SDA

AT24C02N-10SU-2.7_SO8

+3VLAN

1

C24

C25

@

2

22U_0805_6.3VAM

1

A0

2

A1

3

NC

4

GND

1

1

C29

2

2

22U_0805_6.3VAM

0.1U_0402_10V7K~N

@

+1.2VLAN

B B

L43 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

L40 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

L45 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

L44 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

A A

2

C28

1

27P_0402_50V8J

12

2

C12

1

12

2

C13

1

12

2

C22

1

12

1

C19

2

R30
200_0603_1%

12

Y1

1 2

25MHZ_16P_XSL025000FK1H

2

C14

0.1U_0402_16V4Z

1

2

C18

0.1U_0402_16V4Z

1

2

C495

0.1U_0402_16V4Z

1

2

C500

0.1U_0402_16V4Z

1

2

1

5

+AVDDL

+GPHY_PLLVDDL

+PCIE_PLLVDDL

+PCIE_VDDL

XTALO

XTALI

C27

27P_0402_50V8J

CLKREQ_LAN#<14>

R24 1K_0402_5%

+3VLAN

R22 1K_0402_5%

+3VS

LAN_LOW_PWR

R26 47K_0402_1%

+3VLAN

R25 47K_0402_1%

+3VLAN

R23 1.24k_0402_1%

R39 0_0402_5%

1 2
1 2

R34 0_0402_5%@

1 2

1 2

LOW_PWR

12
12

12

4

XTALO
XTALI

CLKREQ#

CBE#1

54

VAUX_PRSNT

53

VMAIN_PRSNT

3

LOW_PWR

58

TEST1

57

TEST2

22

XTALO

21

XTALI

37

RDAC

11

CLK_REQ#

69

GND

BCM5784MA0KMLG_QFN68_10x10

ENERGY_DET

REGOUT12_IO

SUPER_IDDQ

59

17

VDDC_IO

18

CTL12

14

REGCTL12

SUPER_IDDQ

16

1 2

R41 0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

R270_0402_5%

+1.2VLAN_IO

R40 0_0402_5%@

2007/12/12 2008/12/12

LAN_LOW_PWR

12

CABLE_DET <28>

LAN_LOW_PWR <28>

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

BroadCom LAN bcm5784M

U1 LA-4381P

1

of

25 41Wednesday, January 16, 2008

0.0

5

2

@

C485

0.01U_0402_16V7K

1

12

12

R328

R327

@

R332

@

49.9_0402_1%

@

49.9_0402_1%

49.9_0402_1%

R331

49.9_0402_1%

1 2

1 2

@

1

C488

0.01U_0402_16V7K

@

2

R325

V_DAC
MDIN3
MDIP3

V_DAC
MDIN2
MDIP2

V_DAC
MDIN1
MDIP1

V_DAC
MDIN0
MDIP0

R330

12

@

@

1 2

D D

C477 0.01U_0402_16V7K

1 2

C476 0.01U_0402_16V7K

1 2

C478 0.01U_0402_16V7K

1 2

C479 0.01U_0402_16V7K

1 2

C C

49.9_0402_1%

MDIN3<25>
MDIP3<25>

MDIN2<25>
MDIP2<25>

MDIN1<25>
MDIP1<25>

MDIN0<25>
MDIP0<25>

49.9_0402_1%

2

@

C484

0.01U_0402_16V7K

1

12

R326

49.9_0402_1%

@

T1

1
2
3

4
5

7
8
9

10
11
12

BOTH_GST5009-LF

R329

49.9_0402_1%

@

1 2

1

C486

0.01U_0402_16V7K

@

2

4

TCT1

MCT1

TD1+

MX1+

TD1-

MX1-

TCT2

MCT2

TD2+

MX2+

TD2-6MX2­TCT3

MCT3

TD3+

MX3+

TD3-

MX3-

TCT4

MCT4

TD4+

MX4+

TD4-

MX4-

3

V_DAC

RP17

12

18
27
36
45

C463
1000P_1206_2KV7K

12

+3VLAN

R324 FBM-L11-160808-601LMT_0603@

24

RJ45_TX3-

23

RJ45_TX3+

22
21

RJ45_TX2-

20

RJ45_TX2+

19
18

RJ45_RX1-

17

RJ45_RX1+

16
15

RJ45_TX0-

14

RJ45_TX0+

13

75_1206_8P4R_5%

RJ45_TX3­RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+
RJ45_TX0­RJ45_TX0+

2

JLAN1

12

NC

11

NC

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

NC

9

NC

FOXCONN_JM36113-L0R7-7F

CONN@

SHLD2
SHLD1

SHLD2
SHLD1

16
15

R320 0_0805_5%@

14

R1 0_0805_5%@

13

R321 0_0805_5%@

1

12

12

12

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RJ45 / Hyper Flash

U1 LA-4381P

1

0.0

of

26 41Wednesday, January 16, 2008

A

Adjustable Output

U31

4

VIN

2

DELAY
ERROR7CNOISE

C628

C449

4.7U_0805_10V4Z~N

1 1

+5VS

R508 10K_0402_5%

2 2

3 3

2

C419

1

@

@

10P_0402_25V8K

10P_0402_25V8K

4 4

EC_MUTE#<28>

0.1U_0402_16V7K~N

1 2

MIC1
MIC2

2

C618

1

@

10P_0402_25V8K

HD_RST#

EC_MUTE#

A

8

SD

SI9182DH-AD-T1-E3_MSOP8~N

+3VS

10U_0805_6.3V6M

1 2

R506 1K_0402_5%

1 2

R507 1K_0402_5%

HD_RST#<18,21>

MIC_JD

HD_RST#
HD_SYNC
HD_SYNC

2

C617

1

10U_0805_6.3V6M

VOUT

SENSE or ADJ

GND

For EMI

0_0603_5%

12

R493

C619

PD#

HP_JD

R494

1 2

10_0402_5%

R495

1 2

1M_0402_5%

C615

12

R252 0_0402_5%

20mil

1

2

0.1U_0402_16V7K~N

C620 4.7U_0805_6.3V6K
C621 4.7U_0805_6.3V6K

D29

RB751V_SOD323

1

2

B

5
6
1
3

C631 0.01U_0402_16V7K

0.1U_0402_16V7K~N

1

C418

2

C_MIC1

12

C_MIC2

12

1 2

R499 0_0402_5%

R496 39.2K _0402_1%
R502 20K_0402_1%

C627 2.2U_0603_10V6K

21

74LVC1G125GW_SOT353-5

R251 0_0402_5%@

1 2

12

1

C410

2

12
12

1 2

GND_AMP

@

R253 0_0402_5%

+3VS +3VS

1

5

P

I2O

G

U29

3

12

B

+VDDA=4.5V

+VDDA+5VS

R287
27K_0603_1%

R288
10K_0603_1%

23
24

14
15

21
22

16
17

11

12

13
18
36
35
31
43

42

1

2

C629 4.7U_0805_10V4Z~N

+3VS_DVDD +5VS_PVDD

1

9

DVDD

DVDD_IO

LINE1_L
LINE1_R

LINE2_L
LINE2_R

MIC1_L
MIC1_R

MIC2_L
MIC2_R

2

GPIO0/DMIC_DATA

3

GPIO1/DMIC_CLK

4

PD#

RESET#

PCBEEP

SENSE A
SENSE B
CBP
CBN
CPVREF
PVSS2

PVSS1

7

DVSS

ALC269-GR_LQFP48

1

2

C630 0.1U_0402_16V7K~N

+AVDD_AC97

46

PVDD139PVDD2

SPK_OUT_L+

SPK_OUT_L-

SPK_OUT_R+

SPK_OUT_R-

HP_OUT_L
HP_OUT_R

SYNC

SDATA_OUT

SDATA_IN

EAPD/SPDIFO2

SPDIFO

MONO_OUT

MIC2_VREFO

MIC1_VREFO_R
MIC1_VREFO_L

VREF

JDREF

CPVEE

AVSS1
AVSS2

AGND

49

GND_AMP

EAPD Control for Vista

12

4

OE#

5

U30

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

R250 0_0402_5%@

4

Y

C

+5VS

38

UA1

AVDD125AVDD2

40
41

45
44

32
33

10
6

BCLK

5
8

47
48
20

29
30

28
27
19
34
26

37

C

12

R258 0_0805_5%

10U_0805_10V4Z~N

0.1U_0402_16V7K~N

1

C442

2

0.1U_0402_16V7K~N

L66

1 2

8.2UH_FRH5D28-8R2NNP_1.6A_30%

L63

1 2

8.2UH_FRH5D28-8R2NNP_1.6A_30%

L33

1 2

8.2UH_FRH5D28-8R2NNP_1.6A_30%

L34

1 2

8.2UH_FRH5D28-8R2NNP_1.6A_30%

HP_OUTL
HP_OUTR

1 2

R498 33_0402_5%

1 2

R259 0_0402_5%@

SDIN_CODEC

1 2

R497 33_0402_5%

AC97_VREF
AC_JDREF

AGND

12

D

+5VS_PVDD

0.1U_0402_16V7K~N

1

1

C427

C426

2

0.1U_0402_16V7K~N

40mil

1

C433

2

C417 22P_0402_25V8K@

+MIC2_VREFO

+MIC1_VREFO_R
+MIC1_VREFO_L

1 2

R50320K_0402_1%

1 2

C6262.2U_0603_10V6K

PD#

1

C616

0.1U_0402_16V7K~N

2

C434

2

FBM-L11-160808-800LMT_0603

1

C441
10U_0805_10V4Z~N

2

Inductor under survey

HD_SYNC <18>

HD_BITCLK <18>

1 2

HD_SDOUT <18>

HD_SDIN3 <18>

10mil

C624

10U_0805_10V4Z~N

D

1

2

GND_AMP

12

SPK_L1
SPK_L2

SPK_R1
SPK_R2

E

EC Beep

BEEP#<28>

L35

+VDDA

ICH Beep

SB_SPKR<18>

SPK_L1
SPK_L2

SPK_R1
SPK_R2

1 2

C432 1U_0603_16V6K~N

1 2

C431 0.22U_0603_16V4Z

1 2

C440 0.22U_0603_16V4Z

1 2

C424 0.22U_0603_16V4Z

1 2

C430 0.22U_0603_16V4Z

1 2

C425 1U_0603_16V6K~N

R260

1 2

0_0402_5%

SSM3K7002FU_SC70-3

R261

1 2

0_0402_5%

SPK_L1SPK_L2

SPK_R2SPK_R1

F

13

D

Q30

2

G

S

13

D

Q31

2

SSM3K7002FU_SC70-3

G

S

GND_AMP

MIC2
MIC1

10mil
10mil

10mil

C625

1

1

2

2

0.1U_0402_16V4Z

HP_OUTR

1 2

R504 62_0603_1%

HP_OUTL

1 2

R505 62_0603_1%

+3VS

R501

R500

PLUG_IN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

1 2

100K_0402_5%

100K_0402_5%

PLUG_IN#

13

D

Q51

2

SSM3K7002FU_SC70-3

G

S

2007/12/12 2008/12/12

E

HP_JD

13

D

Q52

2

SSM3K7002FU_SC70-3

G

S

Compal Secret Data

Deciphered Date

F

G

BUZR_OFF<28>

Speaker Connector

MICROPHONE IN JACK

R2733K_0402_5%
R2723K_0402_5%

12
12

1 2

L68 CHB2012U170_0805

1 2

L67 CHB2012U170_0805

220P_0402_50V7K

MIC-2

MIC-1

C443

+MIC1_VREFO_R
+MIC1_VREFO_L

MIC_JD

1

C444

2

220P_0402_50V7K

HEADPHONE OUT JACK

PLUG_IN

HP_R

1 2

L64 CHB2012U170_0805

HP_L

1 2

L65 CHB2012U170_0805

HPR

HPL

2

C623

470P_0402_50V7K

Date: Sheet

1

1 2

R249 0_0805_5%

1 2

R257 0_0805_5%

GND_AMP

Title

Size Document Number Rev

Compal Electronics, Inc.

U1 LA-4381P

G

+3VS

56.2_0603_1%

56.2_0603_1%

12

12

R262

R263

RB751V-40TE17_SOD323-2

1

2

2

1

S

G

Q32

2

AP2301GN 1P SOT23

D

1 3

D12

2 1

SPK_R1
SPK_R2
SPK_L1
SPK_L2

FOX_JA6333L-B3S0-7F~N

5
4
3

6 7
2
1

CONN@

FOX_JA6333L-B3S0-7F~N

5
4
3

6 7
2
1

C622
470P_0402_50V7K

JHP1

CONN@

Reserved for TEST

1 2

R266 0_0805_5%

1 2

R264 0_0805_5%

1 2

R286 0_0805_5%

GND AGND

Codec ALC262

H

2

C411

0.1U_0402_16V7K

1

BUZZER

JSPK1

1

1

2

2

3

3

4

4

ACES_88266-04001~N

CONN@

JMIC1

27 41Wednesday, January 16, 2008

H

BUR1

+

1
2

-

LET9040-03A_2P

45@

5

G1

6

G2

10
9
8

of

10
9
8

0.0

5

L28

+3VALW

D D

C C

+3VALW

B B

+5VS

+3VS

+5VALW

A A

1 2

1 2

+3VALW

1 2

MBK1608800YZF 0603

1 2

L29 MBK1608800YZF 0603

CLK_PCI_EC

12

R221
10_0402_5%@

1

C384
15P_0402_50V8D@

2

PCIE_WAKE#<18,22,24,25>

SW_RSV1

1 2

R487 10K_0402_5%
R480 10K_0402_5%
R479 10K_0402_5%
R242 10K_0402_5%
R486 10K_0402_5%
R488 10K_0402_5%
R191 10K_0402_5%
R241 10K_0402_5%
R200 10K_0402_5%
R481 10K_0402_5%
R196 10K_0402_5%

R220 100K_0402_5%@

R231 10K_0402_5%
R230 10K_0402_5%

R219 4.7K_0402_5%
R218 4.7K_0402_5%

R195
0_0402_5%

R198 4.7K_0402_5%
R197 4.7K_0402_5%

R194
0_0402_5%

@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2
1 2

12
12

1000P_0402_50V7K~N

12
12

SW_CONFIG2
SW_CONFIG1
SW_RSV2
INTERNET_BTN
EMAIL_BTN
ECO_BTN
SOFT_BTN
LID_SW#
EC_MUTE#
MSEN#

NB_RST#

TP_DATA
TP_CLK

EC_SMB_DA2
EC_SMB_CK2

EC_SMB_DA1
EC_SMB_CK1

2

C3560.1U_0402_16V7K~N

1

ECAGND

+3VALW

1 2

R201 0_0402_5%

2

@

C382

1

5

+EC_AVCC

1

C358
1000P_0402_50V7K~N

2

R178

1 2

47K_0402_5%

EC_PME#

C338

1 2

0.1U_0402_16V7K~N

+3VALW

EC_RST#

2

1

+3VALW

R199 10K_0402_5%

R179

1 2

0_0805_5%

LPC_AD[0..3]<17,24>

KSI[0..7]<29>

KSO[0..15]<29>

SW_CONFIG1<29>
SW_CONFIG2<29>

EC_SMB_CK1<6,34>
EC_SMB_DA1<6,34>
EC_SMB_CK2<6>
EC_SMB_DA2<6>

SLP_S3#<18>
SLP_S5#<18>

EC_SMI#<18>

LID_SW#<29>

SUSP#<24,32,38,39>

PWRBTN_OUT#<18>

USBSW_EN#<30>

FAN_SPEED1<4>

W_DISABLE#<24,29>

SCRLED#<29>

NUMLED#<29>

15P_0402_50V8J

4

+3VALW_ECVCC

1

2

0.1U_0402_16V7K~N

CLK_PCI_EC<17>

PM_CLKRUN#<17,22>

ON_OFF<31>

C400

0.1U_0402_16V7K~N

1

C398

C383

2

EC_GA20<18>

KB_RST#<18>

SIRQ<17,22>

NB_RST#<11,17,23,24,25>

EC_SCI#<18>

KSI[0..7]

KSO[0..15]

SW_CONFIG1
SW_CONFIG2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMI#
LID_SW#

EC_PME#
FAN_SPEED1
EC_TX_P80DATA

EC_RX_P80CLK

1

4

2

Y3

OUT

NC3NC

32.768KHZ_12.5PF_1TJS125BJ4A421P

4

0.1U_0402_16V7K~N

1

C372

2

1000P_0402_50V7K~N

EC_GA20

1

KB_RST#

2
3
4

LPC_AD3

5

LPC_AD2

7

LPC_AD1

8

LPC_AD0

10
12

NB_RST#

13
37

EC_SCI#

20
38

KSI0

55

KSI1

56

KSI2

57

KSI3

58

KSI4

59

KSI5

60

KSI6

61

KSI7

62

KSO0

39

KSO1

40

KSO2

41

KSO3

42

KSO4

43

KSO5

44

KSO6

45

KSO7

46

KSO8

47

KSO9

48

KSO10

49

KSO11

50

KSO12

51

KSO13

52

KSO14

53

KSO15

54
81
82

77
78
79
80

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

CRY2
CRY1

1

2

122
123

1

C399
15P_0402_50V8J

2

IN

1

2

U10

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0

CRY1

CRY2

C339

LPC & MISC

2

Int. K/B
Matrix

C392

SM Bus

1000P_0402_50V7K~N

1

3

+EC_AVCC

9

22

33

96

111

125

67

VCC

VCC

VCC

VCC

VCC

VCC

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

PWM Output

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD Input

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

GPIO

GND

GND

GND

11

24

35

94

IREF/DA2/GPIO3E

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

GPO

BKOFF#/GPXO08

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

GPI

AGND

GND

GND

KB926QFC0_LQFP128_14X14

69

113

ECAGND

SDIDI/GPXID0

SPICLK/GPIO58

CIR_RX/GPIO40

SYSON/GPIO56

AC_IN/GPIO59

ENBKL/GPXID2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

AD3/GPIO3B

AD4/GPIO42

DA3/GPIO3F

SPIDI/RD#

SPIDO/WR#

SPICS#

GPXO10
GPXO11

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

21
23
26
27

BATT_TEMP

63

BATT_OVP

64
65

AD_BID0

66
75
76

68
70
71
72

EC_MUTE#

83
84
85
86

TP_CLK

87

TP_DATA

88

2007-02-12 MUST PULL DOWN!

SPI_PD

97
98
99
109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

73

MSEN#

74
89

BATT_CHG_LED#

90
91
92
93
95
121

ACIN

127

100
101
102
103

VLDT_EN

104
105

DIMMER_STATUS

106

SB_PWRGD_EC

107

BUZR_OFF

108

110

ENABLT

112
114

EC_THERM#

115
116

EMAIL_BTN

117

INTERNET_BTN

118
124

1

C603

0.1U_0402_10V7K~N

2

2007-05-02 Support KB926 C0

2007/12/12 2008/12/12

INVT_PWM <15>
BEEP# <27>

ECO_BTN <29>

ACOFF <35>LPC_FRAME#<17,24>

BATT_TEMP <34>
BATT_OVP <35>
ADP_I <35>

VFIX_EN <40>
LAN_LOW_PWR <25>

DAC_BRIG <15>
EN_DFAN1 <4>
IREF <35>
CHGVADJ <35>

EC_MUTE# <27>
USB_EN# <30>
ECO_GRN_LED# <29>

ECO_BLU_LED# <29>
TP_CLK <29>
TP_DATA <29>

R239 4.7K_0402_5%

1 2

EN_WOL# <25>

CABLE_DET <25>
SOFT_BTN <29>

R243 15_0402_5%

12

R247 15_0402_5%

12

R244 15_0402_5%

12

R245 15_0402_5%

12

GPLED <29>

MSEN# <15>

FSTCHG <35>

BATT_CHG_LED# <29>
CAPSLED# <29>
BATT_LOW_LED# <29>

PWR_BTN_LED# <29>

SYSON <24,32,37>
VR_ON <40>
ACIN <33,35>

EC_RSMRST# <18>
EC_LID_OUT# <18>
EC_ON <31>
EC_SWI# <18>

VLDT_EN <32>
BKOFF# <15>

DIMMER_STATUS <29>

BUZR_OFF <27>

SW_RSV2 <29>

ENABLT <11,15>

WLAN_P# <24>
EC_THERM# <19>

SW_RSV1 <29>
EMAIL_BTN <29>
INTERNET_BTN <29>

1

C602

4.7U_0805_6.3V6K~N

2

Compal Secret Data

Deciphered Date

2

ACIN

BATT_TEMP

BATT_OVP

EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK_R
SPI_CS#

2

SB_PWRGD_EC

C401

100P_0402_25V8K

C337

100P_0402_25V8K

C336

100P_0402_25V8K

+5VALW

+3VALW

1

R240
0_0402_5%

1 2

R228 0_0603_5%

1 2

@

R229

1 2

0_0603_5%

@

EC_SMB_CK1
EC_SMB_DA1

1

0.47U_0603_16V7K@

2

+3VALW

12

R177

@

Ra

100K_0402_5%

R176

56K_0402_5%~N

Rb

1 2

20mil

0.1U_0402_16V7K~N

C381

1 2

U15

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SU-2-7 SO 8P

@

C408

AD_BID0

1

2

@

GND

SB_PWRGD <6,11,18>

FOR Board ID

C357

0.1U_0402_16V7K~N

1

A0

2

A1

3

A2

4

SPI Flash (8Mb*1)

C393

1 2

0.1U_0402_10V7K~N

10K_0402_5%

+3VALW

20mils

R232

1 2

SPI_CS#
SPI_CLK_R
EC_SO_SPI_SI EC_SI_SPI_SO

U16

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

SST25VF080B-50-4C-S2AF_SO8

4

VSS

2

Q

Reserve for EMI, close to SPI ROM

EC DEBUG

+3VALW

JECDB1

1

EC_TX_P80DATA
EC_RX_P80CLK

Title

Size Document Number Rev

Custom

Date: Sheet

1

2

2

3

3

4

4

ACES_85205-0400

CONN@

KB926&BIOS
U1 LA-4381P

@

@

1

12

@

R237
100K_0402_5%

@

12

R238
100K_0402_5%

SPI_CLK_R

12

R233
33_0402_5%

2

C402
22P_0402_50V8J

1

of

28 41Wednesday, January 16, 2008

0.0

A

INT_KBD CONN.

KSO8

C66 100P_0402_25V8K@

KSI3

C55 100P_0402_25V8K@

KSO9

1 1

2 2

3 3

KSI2
KSI1
KSO10
KSO11
KSI0
KSO12
KSO13
KSO14
KSO15

C65 100P_0402_25V8K@
C56 100P_0402_25V8K@
C57 100P_0402_25V8K@

C63 100P_0402_25V8K@
C58 100P_0402_25V8K@
C62 100P_0402_25V8K@
C61 100P_0402_25V8K@
C60 100P_0402_25V8K@
C59 100P_0402_25V8K@

W_DISABLE#<24,28>

+5VS

PWR_BTN_LED#<28>

BATT_LOW_LED#<28>

BATT_CHG_LED#<28>

W_DISABLE#

C42

1U_0603_10V6K

1 2

1 2

R54 1M_0402_5%

100K_0402_5%

Q7
AOS3401_SOT23

S

2

12

R55

2

D

G

KSI7
KSI6
KSI5
KSO0
KSO1
KSO2
KSI4
KSO3
KSO4
KSO5
KSO6
KSO7

KSI[0..7]
KSO[0..15]

PWR_BTN_LED#

BATT_LOW_LED#

BATT_CHG_LED#

WLAN_EN

13

D

G

S

13

2

@

1000P_0402_50V7K~N

1

2

1

0.1U_0402_16V7K~N

C51 100P_0402_25V8K@
C52 100P_0402_25V8K@
C53 100P_0402_25V8K@
C74 100P_0402_25V8K@
C73 100P_0402_25V8K@
C72 100P_0402_25V8K@C64 100P_0402_25V8K@
C54 100P_0402_25V8K@
C71 100P_0402_25V8K@
C70 100P_0402_25V8K@
C69 100P_0402_25V8K@
C68 100P_0402_25V8K@
C67 100P_0402_25V8K@

LED1

HT-F194BP5 0603 WHITE

LED2

HT-F191UY 0603 AMBER

LED3

HT-F191UY 0603 AMBER

LED4

HT-F194BP5 0603 WHITE

Q36
SSM3K7002FU_SC70-3

+5VS_DIMMER

C37

C38

KSI[0..7] <28>
KSO[0..15] <28>

2

C39

0.1U_0402_16V7K~N

1

21

21

21

21

B

KSO0
KSO1

(Right)

KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

(Left)

1 2

R307 680_0402_5%

1 2

R308 390_0603_5%

1 2

R309 390_0603_5%

1 2

R310 680_0402_5%

ACES_85202-24051~N

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1
2
3
4
5
6
7
8
9

JKB1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2

CONN@

+5VALW

+5VS

C

+5VS

1

C519

0.01U_0402_16V7K

2

USB20P4-<18>

USB20P4+<18>

D

Function Brd CONN.

LED_WLAN#<24>
CARD_LED#<22>
SATA_LED#<19>
CAPSLED#<28>
SCRLED#<28>
NUMLED#<28>
PWR_ON-OFF_BTN#<31>
EMail_BTN<28>
Internet_BTN<28>
ECO_BTN<28>
SOFT_BTN<28>
ECO_GRN_LED#<28>
ECO_BLU_LED#<28>
PWR_BTN_LED#<28>

LID_SW#<28>

+3VALW

GPLED<28>
TP_DATA<28>

TP_CLK<28>

+5VS

F1 1.1A_6VDC_FUSE
R248 0_0402_5%
R256 0_0402_5%

LED_WLAN#
CARD_LED#
SATA_LED#
CAPSLED#
SCRLED#
NUMLED#
PWR_ON-OFF_BTN#
EMail_BTN
Internet_BTN
ECO_BTN
SOFT_BTN
ECO_GRN_LED#
ECO_BLU_LED#
PWR_BTN_LED#

LID_SW#

PJSOT24C_SOT23-3

TOUCHPAD CONN.

TP_DATA
TP_CLK

1

1

@

@

C518100P_0402_25V8K

2

2

100P_0402_25V8K

21
1 2
1 2

+5VS_DIMMER

3

2

3

2

3

@

@

D21

D22

1

PACDN042Y3R_SOT23-3

PACDN042Y3R_SOT23-3

C517

PACDN042Y3R_SOT23-3

1

1

PACDN042Y3R_SOT23-3

2

3

@

D25

1

Felica CONN.

+5VS_FP_FE
USBP4_R­USBP4_R+

1

C409
10U_0805_10V4Z~N

2

2

3

2

@

@

D24

D23

1

LEC

TP42

1A

E

JFN2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

ACES_85201-20051

JTP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND

10

GND

ACES_85201-08051

JFE1

66G1

5

5

G2

4

4

3

3

2

2

1

1

ACES_87151-06051~N

CONN@

7
8

Dip Switch CONN.

ONOFF

SW1

ON

CLR_CMOS<17>
SW_CONFIG1<28>
SW_CONFIG2<28>

SW_RSV1<28>
SW_RSV2<28>

1
2
3
4
5
6 7

FHDS-06-T-V-T/R_12P

12
11
10
9
8

13

DIMMER_STATUS<28>

4 4

DIMMER_STATUS

@

1 2

A

2

G

R56
100K_0402_5%

D

Q8

S

SSM3K7002FU_SC70-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

MINICARD/TPM
U1 LA-4381P

E

0.0

of

29 41Wednesday, January 16, 2008

A

iPOD Charger when system shutdown

+5VALW

U20

1

GND

2

1

C493

C491

0.1U_0402_16V7K~N

2

USB_EN#

470P_0402_50V7K

1

C492

2

1 1

USB_EN#<28>

+USB_AS

1

2

470P_0402_50V7K

1

2

+

C11

150U_D2_6.3VM

2 2

3
4

USB_EN Hi=Enable, Low=Disable IPOD USB power

AC
/DC

OUT

IN

OUT
OUT

IN

OC#

EN#

G548B2P8U_MSOP8

BIOS
MENU

ON
OFFONONONOFFONOFFONOFF

B

+USB_AS

8
7
6
5

S0

S3 S4 S5

W=40mils

OVCUR#0 <18>

SSM3K7002FU_SC70-3

USBSW_EN#<28>

C

+USB_AS

2

G

+3VS

+3VALW

USB_EN#

USB20P0-<18>
USB20P0+<18>

R337 0_0402_5%U1H@

1 2

R336 0_0402_5%@

1 2

R15

1 2

10K_0603_1%

U1H@

R14

1 2

0_0603_5%

@

USB20P0- USBP0-_SW
USB20P0+

12

R339
470_0805_5%

13

D

Q39

S

20mil

USB20P0­USB20P0+

+5VS

1 2

U4

8

NC

VCC
HSD-2D-

6

D+

HSD+

7

GND

OE#

FSUSB31K8X_US8

U1H@

U1L@

1 2

U1L@

R20 0_0402_5%

1 2

R21 0_0402_5%

SUSP<32>

R322

100K_0402_5%

1
3
5
4

USBP0-_SW
USBP0+_SW

J2

1 2

OPEN PADS@

Q4

U1H@

AP2301GN 1P SOT23

S

G

2

R16

43K_0402_1%

U1H@

USBP0+_SW

R18
51K_0402_1%

U1H@

SUSP

2

G

SSM3K7002FU_SC70-3

Q3

U1H@

D

13

1 2

1 2

13

D

S

R17
75K_0402_1%

U1H@

1 2

R19
51K_0402_1%

U1H@

1 2

J3
OPEN PADS

1 2

@

D

L2

2

2

3

3

WCM-2012-670T_4P

CM1293A-04SO_SOT23-6

E

+USB_AS

1

1

4

4

4

CH4

D20

CH1

1

<Part Type>

CON-USBP0­CON-USBP0+

6

5

Vp

CH3

CH2

3Vn2

JUSB1

1

VCC

2

USB_N

3

USB_P

4

GND

5

GND

6

GND

7

GND

8

GND

TYCO 0-1775501-1 4P

CONN@

沉板

OUT
OUT
OUT
OC#

OUT
OUT
OUT
OC#

8
7
6
5

8
7
6
5

+USB_CS

+USB_BS

W=40mils

OVCUR#1 <18>

SSM3K7002FU_SC70-3

W=40mils

OVCUR#3 <18>

SSM3K7002FU_SC70-3

+USB_BS

12

R317
470_0805_5%

13

D

Q38

SUSP

2

G

S

150U_D2_6.3VM

C2

1

+

2

470P_0402_50V7K

1

C464

2

+USB_CS

470P_0402_50V7K

1

C465

2

USB20P1-<18>

USB20P1+<18>

3

2

L1

3

2

WCM-2012-670T_4P

CM1293A-04SO_SOT23-6

4

4

1

1

D1

4

CH4

CH1

1

<Part Type>

5

Vp

Vn

2

+USB_BS

JUSB2

1

USB20P1_R­USB20P1_R+

6

CH3

CH2

3

VBUS

2

D-

3

D+

4

GND

5

GND

6

GND

7

GND

8

GND

SUYIN_020167MR004S511ZR

板下

USB Brd CONN.

1

2

470P_0402_50V7K

1

C514

2

12

R342
470_0805_5%

13

D

Q41

SUSP

2

G

S

150U_D2_6.3VM

+

C515

470P_0402_50V7K

1

C513

2

+USB_CS

JUSB3

1

9

1

GND

2

USB20P2-<18>
USB20P2+<18>

USB20P3-<18>
USB20P3+<18>

USB20P2­USB20P2+

USB20P3­USB20P3+

2

3

3

4

4

5

5

6

6

7

7

8

10

8

GND

ACES_87213-0800G

+5VS

U19

1

GND

2

IN

1

C466

0.1U_0402_16V7K~N

2

SUSP<32>

3 3

+5VS

1

C516

0.1U_0402_16V7K~N

2

SUSP<32>

4 4

1 2

R318
0_0402_5%

1 2

R344
0_0402_5%

3
4

12

R319
100K_0402_5%

@

1
2
3
4

12

R343
100K_0402_5%

@

IN
EN#

G548B2P8U_MSOP8

U22

GND
IN
IN
EN#

G548A2P8U_MSOP8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

USB Port X3 + Felica

Size Document Number Rev

Wednesday, January 16, 2008

Date: Sheet

U1 LA-4381P

of

E

30 41

0.0

A

H1

HOLEA@

HOLEA@

1

1

H17

H34

HOLEA@

HOLEA@

1

1

1 1

H15

H21

HOLEA@

HOLEA@

1

1

H18
HOLEA@

1

H19

H20

HOLEA@

HOLEA@

1

1

H23
HOLEA@

1

H6

2 2

HOLEA@

1

H13
HOLEA@

1

H32

H28

HOLEA@

HOLEA@

1

1

H11

H9

HOLEA@

HOLEA@

1

1

H10
HOLEA@

1

3 3

CF2

CF4

HOLEA@

HOLEA@

1

1

H30

HOLEA@

HOLEA@

1

1

H33
HOLEA@

1

H22

H14

HOLEA@

HOLEA@

1

1

H5

H31

HOLEA@

HOLEA@

1

1

CF1

CF3

HOLEA@

HOLEA@

1

1

H7

H2

H25

H29

HOLEA@

HOLEA@

1

1

H3

H4

HOLEA@

HOLEA@

1

1

H16

H12

HOLEA@

HOLEA@

H_3P0

1

1

H8

H24

HOLEA@

HOLEA@

1

1

H_4P2

PWR_ON-OFF_BTN#<29>

H27
HOLEA@

1

H26
HOLEA@

1

B

SW3
SW TJG-533-V-T/R

3
4

3
4

EC_ON<28>

5

6

SW2
SW TJG-533-V-T/R

5

6

PWR_ON-OFF_BTN#

+3VALW

EC_ON

1
2

Power Button

1
2

DAN202U_SC70

R114

4.7K_0402_5%
R113

1 2

1 2

33K_0402_5%@

1

2

+3VALW

1 2

D6

2
3

13

C

R115
100K_0402_5%

51ON#

2

C265

@

1000P_0402_50V7K~N

1

Q11

DTC124EKAT146_SC59-3

ON_OFF <28>
51ON# <33>

12

D5
RLZ20A_LL34

D

E

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

PWR_OK/BTN
U1 LA-4381P

E

0.0

of

31 41Wednesday, January 16, 2008

A

B

C

D

E

+5VALW

8
7
6
5

1 1

2 2

3 3

1

2

+3VALW

8
7
6
5

1

2

+1.8V

8
7
6
5

1

2

0.22U_0603_10V7K

+5VS

U18

1

S

D

2

S

D

3

S

D

4

G

D

AO4468_SO8

C462
10U_0805_10V4Z~N

+3VALW TO +3VS

U11

1

S

D

2

S

D

3

S

D

4

G

D

AO4468_SO8

C371
10U_0805_10V4Z~N

+1.8V TO +1.8VS

U26

1

S

D

2

S

D

3

S

D

4

G

D

AO4468_SO8

C564
10U_0805_10V4Z~N

C561

@

1

C454

4.7U_0805_10V4Z~N

2

1

2

3VS_GATE RUN_ON

1.8VS_GATE

1

2

1 2

C448

0.22U_0603_10V7K
SSM3K7002FU_SC70-3

1

C391

4.7U_0805_10V4Z~N

2

1 2

1

C380

0.22U_0603_10V7K

2

1

C563

4.7U_0805_6.3V6K~N

2

R375

1 2

0_0402_5%

R376

1 2

10K_0402_5%

@

R284
0_0402_5%

+3VS

1

2

R216
0_0402_5%

+1.8VS

1

2

1

2

RUN_ON

Q35

C379
1U_0603_10V6K

C562
1U_0603_10V6K

RUN_ON

+5VS

C453
1U_0603_10V6K

100K_0603_5%

1 2

13

D

S

R285

G

+1.2VALW

U7

8
7
6
5

1

B+_BIAS

SUSP

2

2

1

S

D

2

S

D

3

S

D

4

G

D

AO4468_SO8

C264
10U_0805_10V4Z~N

0.1U_0603_25V7K~N

SSM3K7002FU_SC70-3

SUSP#<24,28,38,39>

R283

10K_0402_5%

C272

SUSP

1.2VS_GATE

1

2

12

+1.2V_HT

1

C279

4.7U_0805_10V4Z~N

2

R126

1 2

10K_0402_5%

+5VALW

R282
10K_0402_5%

1 2

Q34

13

D

2

G

S

1

2

RUN_ON_1.2

Q15

VLDT_EN<28>

C280
1U_0603_10V6K

13

D

2

G

SSM3K7002FU_SC70-3

S

SYSON<24,28,37>

R127

100K_0603_5%

1 2

VLDT_EN#

VLDT_EN

10K_0402_5%

SYSON#<6,39>SUSP<30>

SSM3K7002FU_SC70-3

SYSON

10K_0402_5%

R128

R281

B+_BIAS

12

SYSON#

12

2

2

+5VALW

G

+5VALW

G

R120
10K_0402_5%

1 2

13

D

Q16

SSM3K7002FU_SC70-3

S

R280
10K_0402_5%

1 2

Q33

13

D

S

+1.2VALW TO +1.2V_HT+5VALW TO +5VS

SUSP

B

+1.8VS+1.2V_HT

12

R385
470_0805_5%

DISCHG_1.8VS

13

D

Q49

2

G

S

SSM3K7002FU_SC70-3

+5VS+3VS

12

R226
470_0805_5%

DISCHG_3VS

13

D

Q28

2

G

S

SSM3K7002FU_SC70-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/12 2008/12/12

Compal Secret Data

12

DISCHG_5VS

13

D

SUSPSUSP

2

G

S

SSM3K7002FU_SC70-3

Deciphered Date

R306
470_0805_5%

Q37

12

DISCHG_1.5VS

13

D

SUSP

2

G

S

SSM3K7002FU_SC70-3

D

R175
470_0805_5%

Q26

Title

Size Document Number Rev

Custom

Date: Sheet

DC Interface
U1 LA-4381P

E

of

32 41Wednesday, January 16, 2008

0.0

+0.9V

12

R151
470_0805_5%

DISCHG_0.9V

13

SYSON#

4 4

D

Q23

2

G

S

SSM3K7002FU_SC70-3

VLDT_EN#

A

12

R125
470_0805_5%

DISCHG_1.2VHT

13

D

Q20

2

G

S

SSM3K7002FU_SC70-3

+1.8V +1.5VS

12

R384
470_0805_5%

DISCHG_1.8V

13

SYSON#

D

Q48

2

G

S

SSM3K7002FU_SC70-3

5

4

3

2

1

Vin Detector

ADPIN

PL1

PF1

PJP2

2

JUMP_43X118@

PJP5

2

JUMP_43X118@

PJP10

2

JUMP_43X118@

PJP11

2

JUMP_43X118@

10A_65VDC_451010

112

112

112

112

21

12

+1.1VS+1.1VSP

+0.9V+0.9VP

D D

C C

B B

PCN1

1

1

2

2

3

3

4

4

SINGA_2WA-8291T041

+3VALWP +3VALW

(5A,200mils ,Via NO.= 10)

+5VALWP +5VALW +1.8VP +1.8V

(5A,200mils ,Via NO.= 10) (8A,320mils ,Via NO.= 16)

(2.0A,80mils ,Via NO.=4)

(2A,80mils ,Via NO.= 4)

FBMA-L18-453215-900LMA90T_1812

12

PC2

PC1

1000P_0402_50V7K~N

100P_0402_50V8J~N

(7A,280mils ,Via NO.=14)

1 2

2

2

2

2

2

PJP25

JUMP_43X118@
PJP3

JUMP_43X118@

PJP26

JUMP_43X118@
PJP6

JUMP_43X118@

PJP8

JUMP_43X118@

12

PC3

100P_0402_50V8J~N

112

112

112

112

112

VIN

12

PC4

1000P_0402_50V7K~N

+1.2VALW+1.2VALWP

+NB_CORE+NB_COREP

High 14.57 14.01 13.46
Low 14.06 13.51 12.98

VIN

12

PR2

61.9K_0402_1%~N

12

12

PC6

32.3

0.1U_0402_16V7K~N

CHGRTC

PR6
20K_0402_1%~N

PR13

1 2

560_0603_5%

PR5

1 2

15.4K_0402_1%

32.3

BATT+

51ON#<31>

3.3V

1 2

560_0603_5%

PC143

2200P_0402_50V7K~N

@

1 2

12

PC7

10K_0402_5%~N

0.1U_0402_16V7K~N

7

LM393DR_SO8~N

PD3

RLS4148_LLDS2

CHGRTCP

PR10

100K_0402_5%

PR11

22K_0402_5%

1 2

RTCVREF

PR14

PC10

3

+

2

-

PR8

0

12

1 2

PR1
1M_0402_1%~N

1 2

VS

8

PU1A

P

0

G

LM393DR_SO8~N

4

12

8

PU1B

P

+

-

G

4

12

12

G920AT24U_SOT89

3

4.7U_0805_6.3V6K~N

PR203

56K_0402_5%~N@

PC5

1

RTCVREF

5
6

12

PC8

PU3

OUT

VS

12

0.01U_0402_25V7K~N

PJP1
JUMP_43X118@

112

0.22U_1206_25V7K

GND

1

12

PR3

5.6K_0402_5%

12

PD1

RLZ4.3B_LL34

PR9

2

33_1206_5%

PQ1

TP0610K-T1-E3_SOT23-3

13

32.8

2

12

PR12
200_0805_5%

2

IN

12

PC11
1U_0805_25V4Z

1 2

PR4
10K_0402_1%~N

12

PR7
10K_0402_5%~N

VIN

PD2
RLS4148_LLDS2

1 2
12

12

PC9

0.1U_0603_25V7K~N

VS

ACIN <28,35>

(5.0A,200mils ,Via NO.=10)

A A

+VDDNBP +VDDNB

PJP4

2

112

JUMP_43X118@

(3A,120mils ,Via NO.= 6)

5

PJP12

2

112

JUMP_43X118@

(3.0A,120mils ,Via NO.=6)

4

+1.5VS+1.5VSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

2

Title

DCIN / Precharge

Size Document Number Rev

Custom

Date: Sheet

LA-4381P

of

1

33 41Wednesday, January 16, 2008

0.0

5

4

3

2

1

D D

C C

B B

BATT+

PL2

FBMA-L18-453215-900LMA90T_1812

BATT+

1 2

12

PC12

0.01U_0402_25V7K~N

PJPB1 battery connector

SMART
Battery:

1.BAT+

2.BAT+

3.ID

4.B/I

5.TS

6.SMD

7.SMC

8.GND

9.GND

12

SUYIN_200275MR009G154ZL_RV

10

GND

11

GND

PR25

1 2

B+

100_0805_5%~N

+5VALW

PD5

PR29

1 2

32.6

220K_0402_5%

12

PC19

PR30

0.1U_0603_25V7K~N

PC13
1000P_0402_50V7K~N

12

1 2

BATT++

PJP13

BATT+
BATT+

B/I

TS
SMD
SMC

GND­GND-

PR27

1 2

1SS355_SOD323-2

220K_0402_5%

ID

1
2
3
4
5
6
7
8
9

470K_0402_5%

PQ3

2

G

BATT++

21

PF2
15A_65VDC_451015

PQ2

TP0610K-T1-E3_SOT23-3

13

32.6

2

13

D

RHU002N06_SOT323

S

PC16

+3VALWP

1 2

100_0402_5%

1 2

100_0402_5%

1 2

0.1U_0805_25V7M~N

1 2

PR19

PR20

PR15
47K_0402_5%~N

B+_BIAS

PR17

1K_0402_5%

12

EC_SMB_DA1 <6,28>

EC_SMB_CK1 <6,28>

Place clsoe to EC pin

BATT_TEMP

1 2

PR16

1K_0402_5%

1 2

1 2

PR18

6.49K_0402_1%

PC14

0.1U_0402_16V7K~N

@

1000P_0402_50V7K~N

BATT_TEMP <28>

+3VALWP

PC17

Battery Connect/OTP

CPU

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL VS

CPU

12

12

PR21

10.7K_0402_1%~N

PR24

61.9K_0402_1%~N

1 2

1 2

VL

PR26

12

150K_0402_1%~N
PH1
100K_0603_1%_TH11-4H104FT

150K_0402_1%~N

PR28

PR22

442K_0402_1%~N

1 2

12

12

PC18
1U_0603_6.3V6M~N

3

+

2

-

1 2

8

PU4A

P

1

0

G

LM358ADT_SO8~N

4

PC15

0.1U_0603_25V7K~N

PD4

1 2

1SS355_SOD323-2

VL

PR23
150K_0402_1%~N

1 2

MAINPWON <36>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

BATTERY CONN

Size Document Number Rev

2

Date: Sheet

LA-4381P

Wednesday, January 16, 2008

1

34 41

0.0Custom

of

A

B

C

D

E

PQ4

VIN

12

PR33

1_1210_5%

1 1

12

PR35

1_1210_5%

PC29

2.2U_0805_25V6K

1 2

1 2

75W adapter

2 2

Input OVP : 22.3V
Input UVP : 17.26V
Fsw : 300KHz

3 3

FDS4435BZ_SO8

8
7
6
5

PC21

0.01U_0603_50V7K~N

PR39
340K_0402_1%

1 2

ACDET

PR37

54.9K_0402_1%

1 2

PR42
340K_0402_1%

1 2

OVPSET

PR43

54.9K_0402_1%

1 2

100K_0402_1%

0.1U_0603_25V7K~N

ACGOOD#

D
D
D
D

PR44

1 2

P2

1

S

2

S

3

S

4

G

PC25

1 2

0.01U_0402_25V7K~N

CP setting

SI2301BDS-T1-E3_SOT23-3

2

12

PC41

ACSET

BATT+

12

PR52
453K_0402_1%

VS

12

PR55

12

8

PU4B

5

P

+

7

0

6

-

4 4

BATT_OVP<28>

G

LM358ADT_SO8~N

4

499K_0402_1%

PC45

0.01U_0402_25V7K~N

12

PR57

86.6K_0402_1%

FDS4435BZ_SO8

1

S

2

S

3

S

4

G

12

PR34

100K_0402_1%

80.6K_0402_1%

1 2

VREF

0.01U_0402_25V7K~N

PQ9

1 3

1 2

CHGVADJ<28>

PQ5

D
D
D
D

PR40

PC34

1U_0603_10V6K~N

PR197
0_0402_5%

PR31

0.015_2512_1%

8
7

P3

6

1

5

2

PC26

0.1U_0402_16V7K~N

1 2

12

PC30

0.1U_0603_25V7K~N

24751_ACP
24751_ACDRV

12

12

PR41
100K_0402_1%

PC40

REGN

PR53

4.32K_0402_1%

1 2

4
3

CHGEN#

PU5

1

12

24751_ACN

ACSET

24751_ACOP

1 2

PC36

0.47U_0603_16V7K~N

VREF

12

VADJ

/BATDRV

12

PR51
0_0402_5%@

VADJ

12

PR54
10K_0402_1%~N

CHGEN

PC28

0.1U_0603_25V7K~N

@

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

PVCC

BTST

HIDRV

REGN

LODRV

PGND

LEARN

CELLS

SRP

SRN

BAT

SRSET

IADAPT

ADP_I<28>

CHGVADJ

3.3V

0V

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

28

27

26

25

PH

24

23

22

21

20

19
18
17

29

TP

16

15

100P_0402_50V8J~N

Pre Cell

4.35V

4V+0.105*CHGVADJ

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

B+

0.1U_0805_25V7M~N

1 2

0_0603_5%

BST_CHG

1 2

DH_CHG

LX_CHG

RLS4148_LLDS2

REGN

12

PC35
1U_0603_10V6K~N

DL_CHG

CELLS

12

PC42

0.1U_0603_25V7K~N

PC27

PR38

BST_CHGA

12

PD6

PJP14

2

JUMP_43X118@

0.1U_0603_25V7K~N

ACOFF <28>

24751_SRP
24751_SRN
24751_BAT

112

1 2

PC31

CHG_B+

578

578

1 2

PQ6
AO4466_SO8

3 6

241

10UH_SIL1045RA-100PF_4.5A_30%

1 2

PQ8
AO4466_SO8

3 6

241

PC22

PL3

ICHG setting

24751_SRSET

1 2

PR49

10_0603_5%

PC44

12

12

PR50
133K_0402_1%

4V

0.4V 0.2A

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

PR47

12

270K_0402_1%

12

PC43

0.01U_0402_25V7K~N

@

IREF Current

3.3V 1.65A

D

4.7U_1206_25V6K~N

1 2

PC23

4.7U_1206_25V6K~N

IREF <28>

0.01U_0402_25V7K~N

1 2

PC24

4.7U_1206_25V6K~N

CHG

PC32

1 2

10U_1206_25V6M~N

12

PC38

0.1U_0603_25V7K~N

12

PR32

PC20

/BATDRV

PR36

0.02_2512_1%

1
2

PC37

0.1U_0402_16V7K~N

1 2

100K_0402_1%

ACGOOD#

FSTCHG<28>

Title

Size Document Number Rev

B

Date: Sheet

100K_0402_1%

1 2

3

4

S1S2S

G

D8D7D6D

5

4
3

12

PC39

0.1U_0603_25V7K~N

@

RTCVREF

PR46

@

VREF

2

G

2

G

PR48
100K_0402_1%

@

1 2

13

D

PQ11
SSM3K7002F_SC59-3

@

S

VREF

PR56
100K_0402_1%

1 2

CHGEN#

13

D

PQ12
SSM3K7002F_SC59-3

S

12

Compal Electronics, Inc.

Charger

JAL70

PQ7
FDS4435BZ_SO8

12

E

BATT+

PC33

10U_1206_25V6M~N

ACIN <28,33>

35 41Wednesday, January 16, 2008

0.0

of

5

4

3

2

1

B+

PF3

2 1

7A_24VDC_429007.WRML

D D

+3VALWP

1

+

PC55

330U_D3L_6.3VM_R25M

C C

2

PL4

HCB4532KF-800T90_1812

1 2

4.7UH_SIL104R-4R7PF_5.7A_30%

PR62

0_0402_5%

1 2

PR65
10K_0402_1%~N

@

1 2

12

PC46

4.7U_1206_25V6K~N

PL5

1 2

12

PC47

4.7U_1206_25V6K~N

12

PC48

2200P_0402_50V7K~N

PR63

@

4.7_1206_5%

PC59

@

680P_0603_50V7K

Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

3.3VALWP
Imax=5A

VS

PD7

RLZ5.1B_LL34

1 2

Iocp=9A

B B

2

1 3

ISL6237_B+

12

12

PR69

100K_0402_1%

1 2

MAINPWON<34>

PQ36

TP0610K-T1-E3_SOT23-3

578

PQ13

AO4466_SO8

3 6

241

578

PQ15
AO4712_SO8

3 6

241

PR70

1 2

200K_0402_5%

PR77

0_0402_5%

0.047U_0603_16V7K~N

PC56

0.1U_0603_25V7K~N

1 2

PC63

0.22U_0603_25V7-K

1 2

VL

PR75

1 2

806K_0603_1%

12

12

PC64

PR58

0_0805_5%

1 2

0.1U_0603_25V7K~N

PR59

BST3A BST5A

12

0_0603_5%

LX3

DL3

FB3

VL

2VREF_ISL6237

1 2

PC62 0.22U_0603_10V7K~N

EN_LDO

PR73

@

0_0402_5%

1 2

PR78

1 2

47K_0402_5%~N

12

@

PC65

0.047U_0402_16V7K~N

@

3-5V_B23-5V_B1

PC52

1 2

2VREF_ISL6237

1 2

PU6

33
26
24

25

23

30

32

1

8

20

4

14

27

PR74

0_0402_5%

PC142

6

VIN

TP
UGATE2
BOOT2

PHASE2

LGATE2

OUT2

REFIN2

REF

LDOREFIN

NC

EN_LDO

EN1

EN2

NC

5

12

1U_0603_10V6K~N

1 2

PC53

3

VCC

TON

2

12

PR76

@

0_0402_5%

2VREF_ISL6237

VL

12

PC54

1U_0603_10V6K~N

7

19

LDO

PVCC

15

UGATE1

17

BOOT1

16

PHASE1

18

LGATE1

22

PGND

10

OUT1

11

FB1

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

GND

ISL6237IRZ-T_QFN32_5X5

21

PC57

1U_0603_10V6K~N

4.7U_0805_6.3V6K~N

1 2

DH5DH3

0_0603_5%

0.1U_0603_25V7K~N

LX5

DL5

FB5

PR68 0_0402_5%

1 2

ILM1EN1

ILIM2

578

PQ14

AO4466_SO8

3 6

241

578

PR60

12

PC58

PR67 0_0402_5%@

12

AO4712_SO8

1 2

PR71

255K_0402_1%

PR72

255K_0402_1%

PQ16

PR61

@

3 6

241

PC60

@

VL

POK <39>

12

12

Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

5VALWP
Imax=5A

Iocp=9A

ISL6237_B+

12

12

PC50

PC49

4.7U_1206_25V6K~N

4.7U_1206_25V6K~N

PL6

4.7UH_SIL104R-4R7PF_5.7A_30%

12

4.7_1206_5%

12

680P_0603_50V7K

12

PC51

2200P_0402_50V7K~N

12

1 2

1 2

+5VALWP

PR64

1

61.9K_0402_1%~N

+

2

PR66
10K_0402_1%~N

PC61
330U_D3L_6.3VM_R25M

PD8

1 2

A A

5

1SS355TE-17_SOD323-2

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/12/12 2008/12/12

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

+3VALWP, +5VALWP

Size Document Number Rev

Date: Sheet

LA-4381P

Wednesday, January 16, 2008

1

36 41

of

0.0Custom

A

1 1

B

C

D

12

24
23
22
21
20
19

PR82

75K_0402_1%

BST_1.2V
UG_1.2V_1

LX_1.2V

LG_1.2V

12

0_0603_1%

12

PC79

0.1U_0402_16V7K~N

@

+1.2VALWP

PR85

PR87

0_0603_1%

PC71

0.1U_0402_16V7K~N

BST_1.2VA

1 2

12
12

PR92
0_0402_5%

1 2

UG_1.2V

+3VALW

B+++

578

3 6

578

3 6

241

241

PF4

2 1

7A_24VDC_429007.WRML

PQ18
FDS8884_SO8

PQ20
FDS6690AS_NL_SO8

PC68

1.8UH_SIL104R-1R8PF_9.5A_30%

12

10U_1206_25V6M~N

12

12

HCB4532KF-800T90_1812

B++++

1 2

12

PC69

2200P_0402_50V7K~N

PL8

1 2

PR166

4.7_1206_5%@

4.7U_0805_6.3V6K~N
PC138
680P_0603_50V7K@

1.2VALWP
Imax=7A

Iocp=11A

PL14

+1.2VALWP

PC74

B+

+1.2VALWP

1

+

PC75
220U_D2_4VM

1 2

2

PR79

B+++

B+++

12

12

PC66

2 2

PC72

+1.8VP

1

+

2

12

+1.8VP

220U_D2_4VM

3 3

PC67

2200P_0402_50V7K~N

10U_1206_25V6M~N

PL7

1.8UH_SIL104R-1R8PF_9.5A_30%

1 2

PC73

4.7U_0805_6.3V6K~N

578

PQ17
FDS8884_SO8

3 6

241

578

PQ19
FDS6690AS_NL_SO8

3 6

241

SYSON<24,28,32>

+1.8VP

0.1U_0402_16V7K~N

UG_1.8V

0_0402_5%

PC70

PR90

1.8VP
Imax=8A

0.1U_0402_16V7K~N

Iocp=12.6A

105K_0402_1%

1 2

PR84

0_0603_1%

BST_1.8VA

12

PR86

0_0603_1%

+1.8VP_EN +1.2VALWP_EN

12

PC76

12

@

BST_1.8V

12

UG_1.8V_1

LX_1.8V

LG_1.8V

12

1U_0603_10V6K~N

75K_0402_1%

1 2

PU7

25

7
8

9
10
11
12

PR89

14K_0402_1%

1 2

PC77

PR80

0_0402_5%

VFB2

P PAD

PGOOD2
EN2
VBST2
DR VH2
LL2
DR VL2

12

PR83

5

6

VO2

VFB2

TRIP2

PGND2

14

13

5VFILT

1 2

PR91

3.3_0402_5%

1 2

TONSEL

4

2

3

GND

TONSEL

V5FILT

V5IN

17

15

16

12

12

PC78

4.7U_0805_25V6M~N

PR81

127K_0402_1%

VFB1

1

VO1

VFB1

PGOOD1

EN1

VBST1

DR VH1

LL1

DR VL1

TRIP1

PGND1

TPS51124RGER_QFN24_4x4

18

PR88
14K_0402_1%

+5VALW

CPU_VDDIO_FB_L <6>CPU_VDDIO_FB_H <6>

12

PR113
0_0402_5%

@

4 4

A

12

PR196
0_0402_5%

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

1.8VP/1.2VALWP

Size Document Number Rev

Date: Sheet

LA-4381P

Wednesday, January 16, 2008

of

D

37 41

0.0Custom

5

4

3

2

1

PF5

D D

PR93

200K_0402_5%

1 2

PR103
0_0402_5%

12

PC89

0.01U_0402_25V7K~N

1 2

EN_PSV

NB_TON

NB_V5FILT

NB_VFB

1

15

TP

EN_PSV

GND7PGND

2
3
4
5
6

PU8

TON
VOUT
V5FILT
VFB
PGOOD

NB_STRAP_DATA

HIGH

LOW

+1.12V/+1.05V

NB_STRAP_DATA <11>

BST_NBCORE

14

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

TPS51117RGYR_QFN14_3.5x3.5

8

NB_CORE

1.05V

1.12V

C C

B B

A A

SUSP#<24,28,32,39>

+5VALW

PR94

0_0402_5%

1 2

PC83

0.1U_0402_16V7K~N

@

PR96

300_0603_1%

1 2

PC87

1U_0603_10V6K~N

PR100

84.5K_0402_1%

1 2

13

D

G

PQ23

S

SSM3K7002F_SC59-3

12

12

0_0402_5%

1 2

2

12

PC88

0.1U_0402_16V7K~N

PR102

PR114
100K_0402_5%~N

1 2

PC85

47P_0402_50V8J~N

1 2

PR98

8.06K_0402_1%

1 2

12

PR99
20K_0402_1%~N

+5VALW

12

PR101
10K_0402_1%~N

PQ24

13

D

SSM3K7002F_SC59-3

2

G

S

NB_VFBA

PR95

0_0603_1%

1 2

DH_NBCORE

LX_NBCORE

DL_NBCORE

12

PR97

15.4K_0402_1%

BST_NBCORE-1

+5VALW

12

PC82

1 2

0.1U_0603_25V7K~N

PC86

4.7U_0805_25V6M~N

B+

578

578

2 1

7A_24VDC_429007.WRML

PQ21
AO4466_SO8

3 6

241

PQ22
AO4712_SO8

3 6

241

NB_B+

51117_B+

12

12

PC80

4.7U_1206_25V6K~N

1.8UH_SIL104R-1R8PF_9.5A_30%

1 2

12

PR147

4.7_1206_5%@

12

PC137
680P_0603_50V7K@

PL15

HCB4532KF-800T90_1812

1 2

PC81

4.7U_1206_25V6K~N

PL9

1

2

+

PC84
220U_D2_4VM

+NB_COREP

AO4712
Rds(on)=15mohm~18mohm

1.05VSP
Imax=5A

Iocp=9A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/12/12 2008/12/12

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

NB_CORE

Wednesday, January 16, 2008

U1 LA-4381P

1

of

38 41

0.0

5

4

3

2

1

D D

+3VALW

12

PR104
10K_0402_1%~N

PR105

SUSP#<24,28,32,38>

1 2

0_0402_5%

32.8

PR107

1 2

0_0402_5%

32.8

POK<36>

C C

B B

PU10

7

POK

8

EN

APL5912-KAC-TRL_SO8~N

+5VALW

+1.2VALW

12

PC90
1U_0603_6.3V6M~N

6

5

VIN

3

VOUT

VCNTL

4

VOUT

2

FB

9

VIN

GND

1

32.8

3K_0402_1%

PR108

1.15K_0402_1%

32.8

PR111

32.8

12

12

0.8V

PC94

12

32.8

0.01U_0402_25V7K~N

1

1

2

2

12

12

PC95
22U_1206_6.3V6M~N

32.8

PJP18

JUMP_43X118@

PC92
10U_1206_6.3V6M~N

32.8

+1.1VSP

10U_1206_25V6M~N

PR109

0_0402_5%

SYSON#

SYSON#<6,32>

1 2

0.1U_0402_16V7K~N

@

SUSP#

+1.8V

PC91

PQ25

2N7002-7-F_SOT23-3

2

G

12

PC98

10U_1206_25V6M~N

PR115

0_0402_5%

1 2

PC105

0.1U_0402_16V7K~N

@

1

PJP17

1

JUMP_43X118@

2

2

12

1K_0402_1%

13

D

S

PC99

PQ26

2N7002-7-F_SOT23-3

12

+1.8V

2

G

PR106

PR110

1

1

2

2

12

PJP19

12

12

1K_0402_1%

JUMP_43X118@

1K_0402_1%

13

D

S

12

PC96

0.1U_0402_16V7K~N

12

PR112

12

PR116

4.99K_0402_1%

PU9

2
3
4

G2992F1U_SO8

12

PC97
10U_1206_25V6M~N

12

PC103

0.1U_0402_16V7K~N

VIN1VCNTL
GND
VREF
VOUT

+0.9VP

2
3
4

12

PC104
10U_1206_25V6M~N

6
5

NC

7

NC

8

NC

9

TP

PU11

VIN1VCNTL
GND
VREF
VOUT

G2992F1U_SO8

+1.5VSP

NC
NC
NC
TP

12

6
5
7
8
9

+3VALW

PC93
1U_0603_6.3V6M~N

12

PC101
1U_0603_6.3V6M~N

+3VALW

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/12 2008/12/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

0.9VP/1.5VSP/1.1/VSP

Size Document Number Rev

2

Date: Sheet

LA-4381P

Wednesday, January 16, 2008

1

39 41

0.0Custom

of

5

ISL6265_PWROK

PR121

13

D D

C C

B B

A A

CPU_PWRGD_SVID_REG<6>

PR158

255_0402_1%

1K_0402_5%

VFIX_EN<28>

105K_0402_1%

VGATE

CPU_SVD<6>
CPU_SVC<6>

VR_ON<28>

PR141

17.8K_0402_1%

DIFF_0

PC129

4700P_0402_25V7K~N

12

12

PR160

12

54.9K_0402_1%

5

2

G

PR131

100K_0402_1%

12

FB_0

180P_0402_50V8J~N

PR161

D

PQ37
SSM3K7002F_SC59-3

S

12

12

PR132
10K_0402_1%~N

@

PR199

100K_0402_5%~N

PR142

12

CPU_VDD0_RUN_FB_H<6>

CPU_VDD0_RUN_FB_L<6>
CPU_VDD1_RUN_FB_L<6>

CPU_VDD1_RUN_FB_H<6>

12

PC130

PC135

12

1000P_0402_50V7K~N

+5VS +3VS

12

PR128
0_0402_5%

12

ISL6265_PWROK

0_0402_5%

VW0

COMP0

1000P_0402_50V7K~N

6.81K_0402_1%

12

PR137

PC131

@

PR162

12

12

12

+5VS

CPU_B+

0.1U_0603_16V7K~N

PR129
105K_0402_1%@

PR134
105K_0402_1%@

12

@

12

PR140

0_0402_5%

@

PC1441000P_0402_50V7K~N

PC1451000P_0402_50V7K~N

@

+VCC_CORE0

10_0402_5%

+VCC_CORE1

12

10_0603_5%

1 2

0.1U_0603_16V7K~N

1 2

10_0603_5%

PR198
0_0402_5%

12

12
12

PR146

PR152

1 2

100_0402_5%

PC113

PR125

PC117

PU13

1

OFS/VFIXEN

2

PGOOD

3

PWROK

4

SVD

5

SVC

6

ENABLE

7

RBIAS

8

OCSET

9

VDIFF0

10

FB0

11

COMP0

12

VW0

ISP0
ISN0

12

PR145

0_0402_5%

PR150

PR156

10_0402_5%

255_0402_1%

4

12

12

48

47

VIN

VCC

ISL6265HRTZ-T_QFN48_6X6~D

ISN0

ISP0

14

13

PR144

12

0_0402_5%

RTN0

12

PR149

0_0402_5%

1 2

100_0402_5%

PR155

0_0402_5%

12

DIFF_1

PC132

PR159

4700P_0402_25V7K~N

12

PR163

1K_0402_5%

4

44.2K_0402_1%

46

45

FB_NB

VSEN0

15

16

VSEN0

RTN1

12

VSEN1

12

12

12

PC108

33P_0402_50V8J~N

12

PR120

PC112

1000P_0402_50V7K~N

PR122

22K_0402_1%

43

44

FSET_NB

VSEN_NB

COMP_NB

RTN1

RTN0

VSEN1

17

18

54.9K_0402_1%

12

12

PC109

1000P_0402_50V7K~N

12

12

PR126

0_0402_5%

12

PR127

11.3K_0402_1%

42

39

40

41

RTN_NB

PGND_NB

LGATE_NB

OCSET_NB

VDIFF1

VW1

COMP121ISP1

FB1

19

22

20

12

PC133

180P_0402_50V8J~N

PR164

12

1000P_0402_50V7K~N

3

578

UGATE_NB

PHASE_NB

BOOT_NB

PR200

1 2

PR124

10_0402_5%

+VDDNBP

1 2

CPU_VDDNB_RUN_FB_H <6>

PHASE_NB

38

PHASE_NB

23

ISP1

COMP1FB_1

PC136

12

VW1

12

0_0402_5%

37

BOOT_NB

UGATE_NB

BOOT0

UGATE0

PHASE0

PGND0

LGATE0

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

ISN1

24

12

ISN1

PC146

@

PR130

PVCC

LGATE_NB
PHASE_NB
UGATE_NB

12

PR133
10_0402_5%

1 2

BOOT_NB

36

BOOT0

35

UGATE0

34

PHASE0

33
32

LGATE0

31
30

LGATE1

29
28

PHASE1

27

UGATE1

26

BOOT1

25

TP

49

12

PC147

@

1000P_0402_50V7K~N

1000P_0402_50V7K~N

12

PC134

1000P_0402_50V7K~N

@

PR165

6.81K_0402_1%

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

PC114

0_0603_5%

0.22U_0603_10V7K~N

LGATE_NB

CPU_VDDNB_RUN_FB_L <6>

UGATE0

PHASE0

PR135

0_0603_5%

BOOT0

1 2

0.22U_0603_10V7K~N

SI4856DY-T1-E3_SO8

+5VS

12

PC123
1U_0603_10V6K~N

<BOM Structure>

UGATE1

PHASE1

PR148

0_0603_5%

BOOT1

1 2

0.22U_0603_10V7K~N

SI4856DY-T1-E3_SO8

2007/12/12 2008/12/12

PQ27
AO4466_SO8

3 6

241

578

PQ28

AO4712_SO8

3 6

241

PR201

12

0_0603_5%

1 2

PC120

PR202
0_0603_5%

1 2

PC126

LGATE1

3 5

5

PQ30

4

LGATE0

12

3 5

5

PQ33

4

Compal Secret Data

Deciphered Date

12

12

241

D8D7D6D

S1S2S3G

241

D8D7D6D

S1S2S3G

2

CPU_B+

12

PC110

10U_1206_25V6M~N

4.7UH_MPL73-4R7_5.5A_20%

1 2

PR123

4.7_1206_5%@

PC116
680P_0603_50V7K@

PQ29

SI7686DP-T1-E3_SO8

5

D8D7D6D

S1S2S3G

4

PQ32

SI7686DP-T1-E3_SO8

5

D8D7D6D

S1S2S3G

4

2

1

+

PC111

100U_25V_M

2

PL11

12

PC118

10U_1206_25V6M~N

PQ31
SI4856DY-T1-E3_SO8

12

PC124

10U_1206_25V6M~N

PQ34
SI4856DY-T1-E3_SO8

PL10

HCB4532KF-800T90_1812

1 2

+VDDNBP

1

+

PC115
220U_D2_4VM

2

CPU_B+

12

PC119

10U_1206_25V6M~N

0.36UH_PCMC104T-R36MN1R17_30A_20%

12

12

CPU_B+

PR138

4.7_1206_5%@

PC121
680P_0603_50V7K@

PR136

16.2K_0402_1%

1 2

PR143

10K_0603_5%_TSM1A103J4302RE

10_0402_5%

ISP0

+VCC_CORE0
Design Current: 12.6A
Max current: 18A

12

PC125

10U_1206_25V6M~N

12

12

OCP_min:24A

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR151

PR153

4.7_1206_5%@

PC127
680P_0603_50V7K@

16.2K_0402_1%

1 2

PR157

10_0402_5%

ISP1

+VCC_CORE1
Design Current: 12.6A
Max current: 18A
OCP_min:24A

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

+CPU_CORE

JAL70

Wednesday, January 16, 2008

1

B+

+VDDNBP
Design Current: 2.1A
Max current: 3A
OCP_min:5A

PJP27

1 2

PAD-OPEN 4x4m

@

PJP22

1 2

PAD-OPEN 4x4m

@

PJP23

1 2

PAD-OPEN 4x4m@

PL12

1 2

PR139

1 2

4.02K_0402_1%
PC122

12

0.1U_0603_16V7K~N

PH2

12

PL13

1 2

PR154

1 2

4.02K_0402_1%
PC128

12

0.1U_0603_16V7K~N

PH3

12

10K_0603_5%_TSM1A103J4302RE

12

ISN0

12

ISN1

+VCC_CORE0

+VCC_CORE1

40 41

1

+VCC_CORE1+VCC_CORE0

0.0

of

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1

Request

Item Issue DescriptionDate

D D

1

P37

2

3

P37

P38

4

C C

P41

5

P41 +CPU_CORE 08'01/08

6

7 P36

+CPU_CORE

1.8VP/1.2VALWP 08'01/08

1.8VP/1.2VALWP 08'01/08 adjust 1.8VP/1.2VALWP OCP set

NB_CORE 08'01/08 Change PR114 from @0 to 100KModify NB_CORE turn off avoised cause force PWM mode

+CPU_CORE 08'01/08

+3VALWP,+5VALWP 08'01/08 Compal adjust +3VALWP,+5VALWP ocp set

08'01/02 Add PR200 for BOOT_NB.

Owner

CompalP41 0.1

Compal

Compal

Compal

Compal

Compal

Intersil FAE request.

modify current limit

Modify while S3 mode avoised cause voltage drop

Change PQ17 PQ18 from AO4466 to FDS8884

Change PQ19 PQ20 from AO4712 to FDS6690AS

Change PR88 from 16.5K to 14K

Change PR89 from 20.5K to 14K

Change PR199 from 0ohm to 100K

ADD PQ37

ADD PR201 PR202Modify improve EMI

Change PR71 from 330K to 255K

Change PR72 from 330K to 255K

Solution Description Rev.Page# Title

0.1

0.1

0.1

0.1

0.1

0.1

8

P35 Charger 08'01/08 Compal adjust Charger pre cell set Change PR53 from 15K to 4.32K

9 P38 NB_CORE 08'01/08 Compal Change PR96 from 0ohm to 300ohmTI FAE request.TI FAE request.

B B

A A

0.1

0.1

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Next: PR238, PC202, PQ56, PD42, PJP21

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

EE-PIR

Size Document Number Rev

U1 LA-4381P

Date: Sheet

Wednesday, January 16, 2008 4141

1

of

0.0