Acer LA-4211P Schematics

ZZZ1

ZZZ1

A

ZZZ3

ZZZ2

ZZZ2

ZZZ3

ZZZ4

ZZZ4

ZZZ5

ZZZ5

ZZZ6

ZZZ6

B

C

D

E

PCB

PCB

1 1

PCB

PCB

DAZ@

DAZ@

Power Switch

Power Switch

DAZ@

DAZ@

Left LED

Left LED

DAZ@

DAZ@

Right LED

Right LED

DAZ@

DAZ@

Touch Sensor

Touch Sensor

DAZ@

DAZ@

JIWA1/A2

2 2

Compal confidential

Schematics Document

Mobile Penryn uFCPGA

3 3

Intel Cantiga_GM/PM+ICH9-M

Saturday, June 06, 2009

Saturday, June 06, 2009

Saturday, June 06, 2009

REV:2.0

4 4

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

E

of

of

of

153

153

153

I

I

I

A

Compal confidential

File Name :

B

C

Right LED Board

D

Swithch & CAP SENSE LEDs Board

E

Left LED Board

1 1

VRAM 16*16
VRAM 32*16

page20,21

PCI-E X16

nVIDIA NB9M

page16,19

CONN

page23

CH7318

page23

CRT & TV OUT

page25

2 2

LVDS
Connector

page24

PCI-EHDMI

Intel Cantiga GMCH

LVDS I/F

Mobile Penryn

uFCPGA-478 CPU

H_A#(3..35)
H_D#(0..63)

PCBGA 1329

page 8,9,10,11,12,13

DMI

page5,6,7

FSB

667/800/1066MHz

C-Line

DDR2 -667 (1.8V)
DDR2 -800 (1.8V)

Dual Channel

Clock Gen.
SLG8SP556VTR

ICS9LPRS387AKLFT

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page22

page 14,15

AMP&Audio Jack

AZALIA

PCI Express
Mini card Slot 1

page32

6*PCI-E BUS

Intel ICH9-M

mBGA-676

page26,27,28,29

BCM5906
10/100/LAN

3 3

RJ45 CONN

page33

page34

Card Reader

JMB 385

page36

New Card

page40

LPC BUS

EC
ENE KB926

C version

page35

12*USB2.0

Audio Codec

AMOM_CX20561

4*SATA serial

BlueTooth Conn

USB conn X3

page24

page30

page32

page43

MODEM_CX20548

Card reader(XD/SD
MMC/MS/MS-Pro

HD SD)

page36

Int.KBD

page37

SATA HDD

SUB Board

*Right LED

page32,36

Touch Pad

page37

BIOS

page38

*Left LED

4 4

*SWITCH & CAP sensor

Connector
SATA CDROM

Connector

page39

page39

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

E

of

of

of

253Saturday, June 06, 2009

253Saturday, June 06, 2009

253Saturday, June 06, 2009

I

I

I

A

B

C

D

E

1 1

2 2

Voltage Rails

VIN
B+
+CPU_CORE

+1.05VS

+1.5VS
+1.8V

+2.5VS
+3VALW
+3VS
+5VALW
+5VS

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

DescriptionPower Plane

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

0.9V switched power rail for DDR terminator+0.9VS

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

1.8V switched power rail+1.8VS

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

RTC power+RTCVCC

SLP_S3#SLP_S1#

SLP_S4#

SLP_S5#

HIGHHIGHHIGHHIGH

HIGH HIGH HIGH

LOW

HIGH

LOW

LOW

LOW LOW LOW

HIGH

HIGH

LOWLOWLOW

LOW

S3S1

N/A N/A N/A

OFFON
OFFON

ON

ON
OFF

ON
ON

OFF
ON
ON

OFF
ON

ON

OFF

ON OFF

ONONON

+VALW

+V +VS Clock

ON

ON

ON

ON

ON

ON

ON

OFF

ON

OFF

S5

N/AN/AN/A

OFF
OFF
OFFOFFON

OFFOFFON
OFF
OFF
OFF
ON*ON
OFF
ON*

ON*ONVSB always on power rail+VSB
ON

ON

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

SMB_CK_CLK1
SMB_CK_DAT1 ICH9

LCD_CLK
LCD_DAT

KB926

KB926

Cantiga

INVERTER BATT EEPROM

X
X

X
XX

SERIAL SENSOR

VV

XX
X

X
XX

THERMAL
(CPU)

SODIMM CLK CHIP

XX

V

X

X

VVV

XX

X
X

MINI CARD

LCD

XX
X

X
X

X

V

3 3

PM@
GM@
X76@

4 4

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

E

of

of

of

353Saturday, June 06, 2009

353Saturday, June 06, 2009

353Saturday, June 06, 2009

I

I

I

A

Voltage Rails

Power Plane Description

VIN

1 1

B+
+VGA_CORE
+1.1VS
+1.8V
+1.8VS 1.8V switched power rail
+3VALW
+3VS
+5VALW
+5VS
+VSB VSB always on power rail ON ON*
+RTCVCC RTC power

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for GPU

1.1V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

B

S1 S3 S5

N/A N/A N/A

ON OFF
ON OFF
ON
ON
ON
ON
ON
ON OFF
ON
ON

N/AN/AN/A
OFF
OFF

ON

OFF
OFF

OFF
ON ON*

OFF

OFF
ON

ON*

OFF

ONON

C

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

The ramp time for any rail must be more than 40us

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW

HIGH

LOW

LOWLOWLOW

LOW LOW LOW LOW

POWER SQUENCE

D

HIGHHIGHHIGH

HIGH

HIGH

E

ON

ON

ON

OFF

OFF

ON ON

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

ON

ON

ON

ON

ON

EDP at Tj = 97C*

Power Supply Rail

NVVDD Variable

2 2

3 3

FB_DLLAVDD 1.1
FB_PLLAVDD
IFPC_IOVDD
IFPD_IOVDD
IFPE_IOVDD
IFPF_IOVDD
PEX_IOVDD/Q
PEX_PLLVDD
PLLVDD
SP_PLLVDD
VID_PLLVDD

TOTAL

FBVDD/Q
IFPA_IOVDD
IFPB_IOVDD
IFPAB_PLLVDD
IFPCD_PLLVDD
IFPEF_PLLVDD

TOTAL

DACA_VDD
DACB_VDD
DACC_VDD
MIOA_VDDQ
MIOB_VDDQ
VDD33

TOTAL 3.3 0.645A

(V)

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.8

1.8

1.8

1.8

1.8

1.8

1.8

3.3

3.3

3.3

3.3

3.3

3.3

NB9M-GS

GDDR3 DDR2

12.68A 11.57A

3080mA

3.6A 3.53A 2.2A

25mA
10mA
385mA
385mA
385mA
385mA
1400mA
110mA
65mA
25mA
50mA

3.225A

1720mA 3010mA 1680mA

50mA
50mA
100mA
160mA
160mA

2.24A

130mA
255mA
130mA
10mA
10mA
110mA

NB9M-GE

GDDR3 DDR2

10.52A 9.59A

(+3VS)

(1.1VS)

(+VGA_CORE)

(1.8VS)

VDD33

PEX_VDD

NVVDD

FBVDDQ

PEX_VDD can ramp up any time

tNVVDD>=0

tNV-FB

tFBVDDQ>=0

4 4

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

E

of

of

of

453Saturday, June 06, 2009

453Saturday, June 06, 2009

453Saturday, June 06, 2009

I

I

I

5

4

3

2

1

XDP Reserve

D D

H_A#[3..16](8)

H_ADSTB#0(8)

H_REQ#0(8)
H_REQ#1(8)
H_REQ#2(8)
H_REQ#3(8)
H_REQ#4(8)

H_A#[17..35](8)

C C

H_ADSTB#1(8)

H_A20M#(27)

H_FERR#(27)

H_IGNNE#(27)
H_STPCLK#(27)

H_INTR(27)

H_NMI(27)
H_SMI#(27)

B B

RSVD pins on the CPU
should be left as NO
CONNECT

A A

H_ADSTB#0
H_REQ#0

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

AA4
AB2
AA3

D22

K5
M3
N2

N3
P5
P2

P4
P1
R1
M1

K3
H2
K2

Y2
U5
R3

W6

U4
Y5
U1
R4
T5

T3
W2
W5

Y4

U2

V4
W3

V1

A6

A5

C4

D5

C6

B4

A3

M4

N5

T2

V3

B2

D2

D3

J4
L5
L4

J1

L2

J3
L1

F6

ME@

ME@
JCPUA

JCPUA

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

Penryn

Penryn

ADDR GROUP_0

ADDR GROUP_0

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

ADDR GROUP_1

ADDR GROUP_1

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

THERMAL

THERMAL

PROCHOT#

THERMDA

THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

BCLK[0]
BCLK[1]

RESERVED

RESERVED

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#

H_DRDY#

H_DBSY#
H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

XDP_DBRESET#

H_PROCHOT#
H_THERMDA

H_THERMDC
H_THERMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS# (8)
H_BNR# (8)

H_BPRI# (8)

H_DEFER# (8)

H_DRDY# (8)
H_DBSY# (8)

H_BR0# (8)

XDP_BPM#5 reserve a via for debuging

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

5

4

+VCCP

12

R83

R83
56_0402_5%

56_0402_5%

H_INIT# (27)

H_LOCK# (8)

H_RESET# (8)
H_RS#0 (8)
H_RS#1 (8)
H_RS#2 (8)
H_TRDY# (8)

H_HIT# (8)
H_HITM# (8)

XDP_DBRESET# (28)

12

R84 68_0402_5%R84 68_0402_5%

H_THERMTRIP# (8,27)

CLK_CPU_BCLK (22)
CLK_CPU_BCLK# (22)

+3VS

1

C89

C89

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VCC_FAN1

EN_FAN1

R7261K_0402_5%

R7261K_0402_5%

H_THERMDA
H_THERMDC

THERM#

Address:100_1100

+5VS

1 2

FAN_SPEED1(35)

2

1

2

C95

C95

1 2

2200P_0402_50V7K

+3VS

EN_FAN1(35)

2200P_0402_50V7K

R94

R94

1 2

10K_0402_5%

10K_0402_5%

2200p change to
1000p for ADT7421

+VCCP

H_PROCHOT#

Security Classification

Security Classification

Security Classification

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

reserved by XDP_BPM#5

U5

U5

1

VDD

2

D+

3

ALERT/THERM2

D-

4

THERM

EMC1402-1-ACZL-TR_MSOP8

EMC1402-1-ACZL-TR_MSOP8

U24

U24

1
2
3
4

G990P1UF_SOP8

G990P1UF_SOP8

C808

C808

0.1U_0402_25V6

0.1U_0402_25V6

+3VS

XDP_DBRESET#

XDP_TDI
XDP_TMS
XDP_TDO

XDP_TRST#
XDP_TCK

+3VS

8

SCLK

7

SDATA

6
5

GND

FAN1 Conn

C594 10U_0805_10V4ZC594 10U_0805_10V4Z

1 2

VEN
VIN
VO
VSET

12

R469

R469
10K_0402_5%

10K_0402_5%

1

C596

C596
1000P_0402_50V7K

1000P_0402_50V7K

2

8

GND

7

GND

6

GND

5

GND

+VCC_FAN1

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

1 2

R43

R43

R11 54.9_0402_1%R11 54.9_0402_1%

1 2

R14 54.9_0402_1%R14 54.9_0402_1%

1 2

R12 54.9_0402_1%@R12 54.9_0402_1%@

1 2

R13 54.9_0402_1%@R13 54.9_0402_1%@

1 2

R16 54.9_0402_1%R16 54.9_0402_1%

1 2

R15 54.9_0402_1%R15 54.9_0402_1%

1 2

R95

R95
10K_0402_5%

10K_0402_5%

1 2

EC_SMB_CK2
EC_SMB_DA2

+5VS

12

D17

D17
1SS355TE-17_SOD323-2@

1SS355TE-17_SOD323-2@

D16

D16

1 2

C595

C595

1U_0603_10V4Z

1U_0603_10V4Z

1 2

C597

C597

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

40mil

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

+3VS

1K_0402_5%@

1K_0402_5%@

+VCCP

EC_SMB_CK2 (16,35,41)

EC_SMB_DA2 (16,35,41)

BAS16_SOT23-3@

BAS16_SOT23-3@

JP13

JP13

1

1

2

2

3

3

4

GND

5

GND

E&T_3801-F03N-01R

E&T_3801-F03N-01R

ME@

ME@

553Saturday, June 06, 2009

553Saturday, June 06, 2009

553Saturday, June 06, 2009

of

of

1

of

I

I

I

5

4

3

2

1

ME@

H_D#[0..15](8)

D D

H_DSTBN#0(8)
H_DSTBP#0(8)

H_DINV#0(8)

H_D#[16..31](8)

C C

H_DSTBN#1(8)
H_DSTBP#1(8)

H_DINV#1(8)

R45 1K_0402_5%@R45 1K_0402_5%@

1 2

R46 1K_0402_5%@R46 1K_0402_5%@

1 2

Trace Close CPU < 0.5'

Width=4 mil ,
Spacing: 15mil
(55Ohm)

B B

Layout note: Z0=55 ohm

0.5" max for GTLREF.

A A

+CPU_GTLREF

T16T16 R9 54.9_0402_1%R9 54.9_0402_1%
T15T15
T14T14
T17T17
T10T10

CPU_BSEL0(22)
CPU_BSEL1(22)
CPU_BSEL2(22)

+VCCP

12

R471

R471
1K_0402_1%

1K_0402_1%

12

R470

R470
2K_0402_1%

2K_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

+CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

Close to CPU pin AD26
within 500mils.

5

E22
F24
E26

G22

F23

G25

E25
E23
K24

G24

H22
F26
K22
H23

H26
H25

N22
K25
P26
R23
L23

M24

L22

M23

P25
P23
P22
T24

R24

L25
T25

N25

L26
M26
N24

AD26

C23
D25
C24

AF26

AF1

A26

B22

B23
C21

J24
J23

J26

C3

ME@
JCPUB

JCPUB

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

Penryn

Penryn

DATA GRP 0

DATA GRP 0

MISC

MISC

DATA GRP 1

DATA GRP 1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

COMP0
COMP1
COMP2
COMP3

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

R63 27.4_0402_1%R63 27.4_0402_1%

1 2

R64 54.9_0402_1%R64 54.9_0402_1%

1 2

R10 27.4_0402_1%R10 27.4_0402_1%

1 2

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

1 2

H_D#[32..47] (8)

H_DSTBN#2 (8)
H_DSTBP#2 (8)
H_DINV#2 (8)
H_D#[48..63] (8)

H_DSTBN#3 (8)
H_DSTBP#3 (8)
H_DINV#3 (8)

H_DPRSTP# (8,27,51)
H_DPSLP# (27)
H_DPWR# (8)
H_PWRGOOD (27)
H_CPUSLP# (8)

H_PSI# (51)

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

FSB

BCLK BSEL2 BSEL1 BSEL0
533
667
800

133

166

200

001

110

100

1067 266 0 0 0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

3

+CPU_CORE +CPU_CORE

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

A10
A12
A13
A15
A17
A18
A20

B10
B12
B14
B15
B17
B18
B20

C10
C12
C13
C15
C17
C18

D10
D12
D14
D15
D17
D18

E10
E12
E13
E15
E17
E18
E20

F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AB9

ME@

ME@
JCPUC

JCPUC

A7

VCC[001]

A9

VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]

B7

VCC[010]

B9

VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]

C9

VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]

D9

VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]

E7

VCC[033]

E9

VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]

F7

VCC[042]

F9

VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]

VCCSENSE
VCC[065]
VCC[066]
VCC[067]

VSSSENSE

Penryn

Penryn

Length match within 25 mils.
The trace width/space/other is
16/7/25.

Layout Note:
Route VCCSENSE and VSSSENSE traces at

27.4 Ohms with 50 mil spacing.
Place PU and PD within 1 inch of CPU.
Length matched to within 25 mils.

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

R47 0_0402_5%R47 0_0402_5%

G21
V6

R8 0_0402_5%R8 0_0402_5%

J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

.

For testing purpose only

12
12

+VCCP

Near pin B26

VCCSENSE

VSSSENSE

20mils

CPU_VID0 (51)
CPU_VID1 (51)
CPU_VID2 (51)
CPU_VID3 (51)
CPU_VID4 (51)
CPU_VID5 (51)
CPU_VID6 (51)

VCCSENSE (51)

VSSSENSE (51)

+CPU_CORE

1

C599

C599

2

R23

R23
100_0402_1%

100_0402_1%

1 2

R24

R24
100_0402_1%

100_0402_1%

1 2

10U_0805_10V4Z

10U_0805_10V4Z

1

C598

C598

2

+1.5VS

0.01U_0402_16V7K

0.01U_0402_16V7K

VCCSENSE

VSSSENSE

Close to CPU pin
within 500mils.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

653Saturday, June 06, 2009

653Saturday, June 06, 2009

653Saturday, June 06, 2009

of

of

1

of

I

I

I

5

ME@

ME@
JCPUD

JCPUD

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

D D

C C

B B

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

Penryn

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

.

.

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

220U_D2_4VM

220U_D2_4VM

4

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

+VCCP

1

+

+

C8

C8

2

1

2

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

South Side Secondary

C11

C11

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C13

C13
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

@

@
C28

C28
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C583

C583
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C588

C588
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C10

C10

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C39

C39
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

@

@

C24

C24
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C585

C585
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C587

C587
10U_0805_6.3V6M

10U_0805_6.3V6M

2

+CPU_CORE

C47

C47

1

2

3

1

+

+

2

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

C51

C51

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C36

C36
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C40

C40
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C586

C586
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C590

C590
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

+

+

C17

C17

2

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

1

2

1

@

@

+

+

C41

C41

2

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

C50

C50

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C30

C30
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C37

C37
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C589

C589
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C592

C592
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C16

C16

2

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

1

2

+

+

C48

C48

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C27

C27
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C31

C31
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C591

C591
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C35

C35
10U_0805_6.3V6M

10U_0805_6.3V6M

2

North Side Secondary

1

C9

C9

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C19

C19
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C26

C26
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C593

C593
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

@

@
C29

C29
10U_0805_6.3V6M

10U_0805_6.3V6M

2

Place these inside
socket cavity on L8
(North side
Secondary)

1

C14

C14
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C20

C20
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C582

C582
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C25

C25
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C12

C12
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C15

C15
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C584

C584
10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

@

@

C33

C33
10U_0805_6.3V6M

10U_0805_6.3V6M

2

Mid Frequence Decoupling

ESR <= 1.5m ohm
Capacitor > 1980uF

1

A A

5

4

Security Classification

Security Classification

Security Classification

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

753Saturday, June 06, 2009

753Saturday, June 06, 2009

753Saturday, June 06, 2009

of

of

1

of

I

I

I

5

H_D#[0..63](6)

D D

C C

H_SWNG
H_RCOMP

H_RESET#(5)
H_CPUSLP#(6)

layout note:
Route H_SCOMP and H_SCOMP# with trace width

spacing and impedance (55 ohm) same as FSB data traces

B B

+VCCP

12

R493

R493

12

R488

R488

H_RESET#
H_CPUSLP#

H_VREF

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

1K_0402_1%

1K_0402_1%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C623

C623

2

2K_0402_1%

2K_0402_1%

within 100 mils from NB

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

12

R89

R89

24.9_0402_1%

24.9_0402_1%

AD14

AA13
AA11

AD11
AD10
AD13
AE12

AE14

AE11

AG2

M11

N12

P13

N10

Y10
Y12
Y14

AA8

AA9

AE9
AA2
AD8
AA3
AD3
AD7

AF3
AC1
AE3
AC3

AE8
AD6

C12
E11

A11
B11

F2

G8

F8
E6
G2
H6
H2

F6
D4
H3
M9

J1

J2

J6
P2

L2
R2
N9

L6
M5

J3
N2
R1
N5
N6

N8

L7
M3

Y3

Y6

Y7
W2

Y9

C5
E3

H_RCOMP H_SWNGH_VREF

U26A

U26A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

GM@

GM@

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

HOST

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

+VCCP

12

R482

R482

221_0603_1%

221_0603_1%

12

1

R484

R484

2

100_0402_1%

100_0402_1%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Near B3 pin

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

C616

C616

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

4

H_A#[3..35] (5)

H_ADS# (5)
H_ADSTB#0 (5)
H_ADSTB#1 (5)
H_BNR# (5)
H_BPRI# (5)
H_BR0# (5)
H_DEFER# (5)
H_DBSY# (5)
CLK_MCH_BCLK (22)
CLK_MCH_BCLK# (22)
H_DPWR# (6)
H_DRDY# (5)
H_HIT# (5)
H_HITM# (5)
H_LOCK# (5)
H_TRDY# (5)

H_DINV#0 (6)
H_DINV#1 (6)
H_DINV#2 (6)
H_DINV#3 (6)

H_DSTBN#0 (6)
H_DSTBN#1 (6)
H_DSTBN#2 (6)
H_DSTBN#3 (6)

H_DSTBP#0 (6)
H_DSTBP#1 (6)
H_DSTBP#2 (6)
H_DSTBP#3 (6)

H_REQ#0 (5)
H_REQ#1 (5)
H_REQ#2 (5)
H_REQ#3 (5)
H_REQ#4 (5)

H_RS#0 (5)
H_RS#1 (5)
H_RS#2 (5)

ICH_POK(28,35)

VGATE(28,51)

PLT_RST#(16,26,32,33,36,40)

+DDR_MCH_REF

SMRCOMP_VOH

SMRCOMP_VOL

+3VS

12

R206

R206

10K_0402_5%

10K_0402_5%

R177 0_0402_5%R177 0_0402_5%
R178 0_0402_5%@R178 0_0402_5%@

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

2

C641

C641

1

C640

C640

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

C635

C635

2

C636

C636

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

12

R217

R217
10K_0402_5%

10K_0402_5%

PM_EXTTS#0
PM_EXTTS#1

12
12

1 2

R103 100_0402_5%R103 100_0402_5%

R160

R160

10K_0402_5%

10K_0402_5%

+DDR_MCH_REF

R162

R162

1

10K_0402_5%

10K_0402_5%

C273

C273

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

1

2

+1.8V

+1.8V

12

R502

R502
1K_0402_1%

1K_0402_1%

0.01U_0402_25V7K

0.01U_0402_25V7K

12

R501

R501

3.01K_0402_1%

3.01K_0402_1%

NA lead free

12

R500

R500
1K_0402_1%

1K_0402_1%

0.01U_0402_25V7K

0.01U_0402_25V7K

PM_POK_R

0309 add

PLT_RST#_R

12

12

3

MCH_CLKSEL0(22)
MCH_CLKSEL1(22)
MCH_CLKSEL2(22)

CFG5

PM_BMBUSY#(28)

H_DPRSTP#(6,27,51)
PM_EXTTS#0(14)
PM_EXTTS#1(15)

H_THERMTRIP#(5,27)

DPRSLPVR(28,51)

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5
CFG6

T48T48

CFG7

T47T47

CFG8

T45T45

CFG9

T41T41

CFG10

T50T50

CFG11

T49T49

CFG12

T39T39

CFG13

T43T43

CFG14

T38T38

CFG15

T37T37

CFG16

T46T46

CFG17

T42T42

CFG18

T55T55

CFG19

T53T53

CFG20

T54T54

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST#_R
H_THERMTRIP#
DPRSLPVR

U26B

U26B

M36

T69T69

RSVD1

N36

T70T70

RSVD2

R33

T58T58

RSVD3

T33

T66T66

RSVD4

AH9

T23T23

RSVD5

AH10

T25T25

RSVD6

AH12

T27T27

RSVD7

AH13

T30T30

RSVD8

K12

T26T26

RSVD9

AL34

T62T62

RSVD10

AK34

T61T61

RSVD11

AN35

T67T67

RSVD12

AM35

T68T68

RSVD13

T24

T44T44

RSVD14

B31

T56T56

RSVD15

B2

T84T84

RSVD16

M1

T83T83

RSVD17

AY21

T40T40

RSVD20

BG23

T87T87

RSVD22

BF23

T88T88

RSVD23

BH18

T34T34

RSVD24

BF18

T35T35

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

A47

NC_26

GM@

GM@

RSVD CFG PM NC

RSVD CFG PM NC

SM_RCOMP_VOH
SM_RCOMP_VOL

DDR CLK/ CONTROL/ COMPENSATIONHDA

DDR CLK/ CONTROL/ COMPENSATIONHDA

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLKDMIGRAPHICS VIDMEMISC

CLKDMIGRAPHICS VIDMEMISC

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1

SB_ODT_O

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

2

M_CLK_DDR0

AP24

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

SMRCOMP_VOH

BF28

SMRCOMP_VOL

BH28

+DDR_MCH_REF

AV42

SM_PWROK

AR36

SM_REXT

BF17
BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33

T90 PADT90 PAD

B32

T89 PADT89 PAD

G33

T65 PADT65 PAD

F33

T64 PADT64 PAD

E33

T63 PADT63 PAD

C34

T91T91

For AMT function

CL_CLK0

AH37

CL_DATA0

AH36
AN36

CL_RST#

AJ35

CL_VREF

AH34

N28
M28

HDMICLK_NB

G36

HDMIDAT_NB

E36

MCH_CLKREQ#

K36

MCH_ICH_SYNC#

H36

B12

MCH_HDA_BCLK

B28

MCH_HDA_RST#

B30

MCH_HDA_SDIN

B29

MCH_HDA_SDOUT

C29

MCH_HDA_SYNC

A28

M_CLK_DDR0 (14)
M_CLK_DDR1 (14)
M_CLK_DDR2 (15)
M_CLK_DDR3 (15)

M_CLK_DDR#0 (14)
M_CLK_DDR#1 (14)
M_CLK_DDR#2 (15)
M_CLK_DDR#3 (15)

DDR_CKE0_DIMMA (14)
DDR_CKE1_DIMMA (14)
DDR_CKE2_DIMMB (15)
DDR_CKE3_DIMMB (15)

DDR_CS0_DIMMA# (14)
DDR_CS1_DIMMA# (14)
DDR_CS2_DIMMB# (15)
DDR_CS3_DIMMB# (15)

M_ODT0 (14)
M_ODT1 (14)
M_ODT2 (15)
M_ODT3 (15)

R497 80.6_0402_1%R497 80.6_0402_1%

1 2

DDR3

CLK_MCH_DREFCLK (22)

CLK_MCH_DREFCLK# (22)

MCH_SSCDREFCLK (22)

MCH_SSCDREFCLK# (22)

CLK_MCH_3GPLL (22)
CLK_MCH_3GPLL# (22)

DMI_TXN0 (28)
DMI_TXN1 (28)
DMI_TXN2 (28)
DMI_TXN3 (28)

DMI_TXP0 (28)
DMI_TXP1 (28)
DMI_TXP2 (28)
DMI_TXP3 (28)

DMI_RXN0 (28)
DMI_RXN1 (28)
DMI_RXN2 (28)
DMI_RXN3 (28)

DMI_RXP0 (28)
DMI_RXP1 (28)
DMI_RXP2 (28)
DMI_RXP3 (28)

connect to power CPU_CORE

CL_CLK0 (28)
CL_DATA0 (28)

M_PWROK (28)
CL_RST# (28)

T52T52
T51T51

1 2

56_0402_5%

56_0402_5%

R105

R105

R80 33_0402_5%GM_HDMI@R80 33_0402_5%GM_HDMI@

1 2

R82 33_0402_5%GM_HDMI@R82 33_0402_5%GM_HDMI@

1 2

R79 33_0402_5%GM_HDMI@R79 33_0402_5%GM_HDMI@

1 2

R85 33_0402_5%GM_HDMI@R85 33_0402_5%GM_HDMI@

1 2

R81 33_0402_5%GM_HDMI@R81 33_0402_5%GM_HDMI@

1 2

Notice: Please check HDA power rail to select HDA controller.

+1.8V

R498

R498

80.6_0402_1%

80.6_0402_1%

1 2

20mil

R148 10K_0402_5%R148 10K_0402_5%

1 2
1 2

R111 499_0402_1%R111 499_0402_1%

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C238

HDMICLK_NB (23)
HDMIDAT_NB (23)

C238

MCH_CLKREQ# (22)
MCH_ICH_SYNC# (28)

TSATN# (35)

+VCCP

1

For Crestline: 20ohm
For Calero: 80.6ohm
For Cantiga: 80.6ohm

MCH_HDA_BCLK

10P_0402_50V8J

10P_0402_50V8J

+VCCP

12

R143

R143
1K_0402_1%

1K_0402_1%

12

1

R147

R147
499_0402_1%

499_0402_1%

2

check list 511ohm 1%
ISPD only 510ohm 5%

HDA_BITCLK_CODEC (16,27,30)

HDA_RST_CODEC# (16,27,30)
HDA_SDIN0 (27)
HDA_SDOUT_CODEC (16,27,30)

HDA_SYNC_CODEC (16,27,30)

C646

C646
@

@

1

2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

1

of

of

of

853Saturday, June 06, 2009

853Saturday, June 06, 2009

853Saturday, June 06, 2009

I

I

I

5

4

3

2

1

D D

DDR_A_D[0..63](14) DDR_B_D[0..63](15)

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AJ38
AJ41

AN38

AM38

AJ36

AJ40
AM44
AM42

AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36

AW36

BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12

BB9
BA9

AU10

AV9

BA11

BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5

AN10

AM11

AM5

AN12

AM13

AJ11

AJ12

AJ9
AJ8

U26D

U26D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

GM@

GM@

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

DDR_A_BS#1

BG18

DDR_A_BS#2

AT25

DDR_A_RAS#

BB20

DDR_A_CAS#

BD20

DDR_A_WE# DDR_B_CAS#

AY20

DDR_A_DM0

AM37

DDR_A_DM1

AT41

DDR_A_DM2

AY41

DDR_A_DM3

AU39

DDR_A_DM4

BB12

DDR_A_DM5

AY6

DDR_A_DM6

AT7

DDR_A_DM7

AJ5

DDR_A_DQS0

AJ44

DDR_A_DQS1

AT44

DDR_A_DQS2

BA43

DDR_A_DQS3

BC37

DDR_A_DQS4

AW12

DDR_A_DQS5

BC8

DDR_A_DQS6

AU8

DDR_A_DQS7

AM7

DDR_A_DQS#0

AJ43

DDR_A_DQS#1

AT43

DDR_A_DQS#2

BA44

DDR_A_DQS#3

BD37

DDR_A_DQS#4

AY12

DDR_A_DQS#5

BD8

DDR_A_DQS#6

AU9

DDR_A_DQS#7

AM8

DDR_A_MA0

BA21

DDR_A_MA1

BC24

DDR_A_MA2

BG24

DDR_A_MA3

BH24

DDR_A_MA4

BG25

DDR_A_MA5

BA24

DDR_A_MA6

BD24

DDR_A_MA7

BG27

DDR_A_MA8

BF25

DDR_A_MA9

AW24

DDR_A_MA10

BC21

DDR_A_MA11

BG26

DDR_A_MA12

BH26

DDR_A_MA13

BH17

DDR_A_MA14

AY25

DDR_A_BS#0

BD21

DDR_A_BS#0 (14)
DDR_A_BS#1 (14)
DDR_A_BS#2 (14)

DDR_A_RAS# (14)
DDR_A_CAS# (14)
DDR_A_WE# (14)

DDR_A_DM[0..7] (14)

DDR_A_DQS[0..7] (14)

DDR_A_DQS#[0..7] (14)

DDR_A_MA[0..14] (14)

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AK47
AH46
AP47
AP46

AJ46

AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43

BF43
BE45
BC41

BF40

BF41
BG38

BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BG8

BH12

BF11

BF8
BG7
BC5
BC6
AY3
AY1

BF6

BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1

AL1

AL2

AJ1
AH1
AM2
AM3
AH3

AJ3

U26E

U26E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

GM@

GM@

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS#1
DDR_B_BS#2

DDR_B_RAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS#0

BC16

DDR_B_BS#0 (15)
DDR_B_BS#1 (15)
DDR_B_BS#2 (15)

DDR_B_RAS# (15)
DDR_B_CAS# (15)
DDR_B_WE# (15)

DDR_B_DM[0..7] (15)

DDR_B_DQS[0..7] (15)

DDR_B_DQS#[0..7] (15)

DDR_B_MA[0..14] (15)

A A

5

4

Security Classification

Security Classification

Security Classification

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

953Saturday, June 06, 2009

953Saturday, June 06, 2009

953Saturday, June 06, 2009

of

of

1

of

I

I

I

5

4

3

2

1

Strap Pin Table

CFG[2:0] FSB Freq select

D D

U26C

U26C

L32

GMCH_ENBKL(24)

+3VS

LVDS_SCL(24)
LVDS_SDA(24)
GM_ENVDD(24)

For Cantiga:2.37kohm
For Crestline:2.4kohm
For Calero: 1.5Kohm

Note: All LVDS data

C C

B B

A A

signals/and it's compliments
should be routed
Differentially

Layout Note: Place 150
Ohmtermination resistors
close to GMCH

GM@

GM@

R127 75_0402_5%

R127 75_0402_5%
R121 75_0402_5%GM@R121 75_0402_5%GM@
R122 75_0402_5%

R122 75_0402_5%

R132 150_0402_1%

R132 150_0402_1%
R124 150_0402_1%

R124 150_0402_1%
R123 150_0402_1%

R123 150_0402_1%

GMCH_CRT_HSYNC(25)

GMCH_CRT_VSYNC(25)

GM@

GM@

GM@

GM@

1 2

GM@

GM@

1 2

GM@

GM@

1 2

12
12
12

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

1 2

R203 30_0402_1%

R203 30_0402_1%

GM@

GM@

1 2

R204 30_0402_1%

R204 30_0402_1%

GM@

GM@

For Cantiga:1.02kohm
For Crestline:1.3kohm
For Calero: 255ohm

R213 10K_0402_5%R213 10K_0402_5%
R159 10K_0402_5%R159 10K_0402_5%

LVDS_SCL
LVDS_SDA

GM_ENVDD

R167 2.37K_0402_1%R167 2.37K_0402_1%

LVDS_ACLK#(24)
LVDS_ACLK(24)

LVDS_A0#(24)
LVDS_A1#(24)
LVDS_A2#(24)

LVDS_A0(24)
LVDS_A1(24)
LVDS_A2(24)

TVA_DAC
TVB_DAC
TVC_DAC

GMCH_CRT_B(25)
GMCH_CRT_G(25)
GMCH_CRT_R(25)

GMCH_CRT_CLK(25)
GMCH_CRT_DATA(25)

R139

R139

0_0402_5%

0_0402_5%

@

@

1 2
1 2

12

LVDS_ACLK#
LVDS_ACLK

LVDS_A0#
LVDS_A1#
LVDS_A2#

LVDS_A0
LVDS_A1
LVDS_A2

R140

R140

0_0402_5%

0_0402_5%

@

@

GMCH_ENBKL

T93T93

T94T94

T72T72

T73T73

TVA_DAC
TVB_DAC
TVC_DAC

GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R

GMCH_CRT_CLK
GMCH_CRT_DATA

T1T1

5

20mil

12

R138

R138

1.02K_0402_1%

1.02K_0402_1%

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

GM@

GM@

4

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

LVDS TV VGA

LVDS TV VGA

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

Place the resistor within 500mils
(1.27mm)of the (G)MCH

PEGCOMP trace width
and spacing is 20/25 mils.

T37

PEGCOMP

R163

T36

PCIE_GTX_C_MRX_N0

H44

PCIE_GTX_C_MRX_N1

J46

PCIE_GTX_C_MRX_N2

L44

PCIE_GTX_C_MRX_N3

L40

PCIE_GTX_C_MRX_N4

N41

PCIE_GTX_C_MRX_N5

P48

PCIE_GTX_C_MRX_N6

N44

PCIE_GTX_C_MRX_N7

T43

PCIE_GTX_C_MRX_N8

U43

PCIE_GTX_C_MRX_N9

Y43

PCIE_GTX_C_MRX_N10

Y48

PCIE_GTX_C_MRX_N11

Y36

PCIE_GTX_C_MRX_N12

AA43

PCIE_GTX_C_MRX_N13

AD37

PCIE_GTX_C_MRX_N14

AC47

PCIE_GTX_C_MRX_N15

AD39

PCIE_GTX_C_MRX_P0

H43

PCIE_GTX_C_MRX_P1

J44

PCIE_GTX_C_MRX_P2

L43

PCIE_GTX_C_MRX_P3

L41

PCIE_GTX_C_MRX_P4

N40

PCIE_GTX_C_MRX_P5

P47

PCIE_GTX_C_MRX_P6

N43

PCIE_GTX_C_MRX_P7

T42

PCIE_GTX_C_MRX_P8

U42

PCIE_GTX_C_MRX_P9

Y42

PCIE_GTX_C_MRX_P10

W47

PCIE_GTX_C_MRX_P11

Y37

PCIE_GTX_C_MRX_P12

AA42

PCIE_GTX_C_MRX_P13

AD36

PCIE_GTX_C_MRX_P14

AC48

PCIE_GTX_C_MRX_P15

AD40

PCIE_MTX_GRX_N0

J41

PCIE_MTX_GRX_N1

M46

PCIE_MTX_GRX_N2

M47

PCIE_MTX_GRX_N3

M40

PCIE_MTX_GRX_N4

M42

PCIE_MTX_GRX_N5

R48

PCIE_MTX_GRX_N6

N38

PCIE_MTX_GRX_N7

T40

PCIE_MTX_GRX_N8

U37

PCIE_MTX_GRX_N9

U40

PCIE_MTX_GRX_N10

Y40

PCIE_MTX_GRX_N11

AA46

PCIE_MTX_GRX_N12

AA37

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AD43

PCIE_MTX_GRX_N15

AC46

PCIE_MTX_GRX_P0

J42

PCIE_MTX_GRX_P1

L46

PCIE_MTX_GRX_P2

M48

PCIE_MTX_GRX_P3

M39

PCIE_MTX_GRX_P4

M43

PCIE_MTX_GRX_P5

R47

PCIE_MTX_GRX_P6

N37

PCIE_MTX_GRX_P7

T39

PCIE_MTX_GRX_P8

U36

PCIE_MTX_GRX_P9

U39

PCIE_MTX_GRX_P10

Y39

PCIE_MTX_GRX_P11

Y46

PCIE_MTX_GRX_P12

AA36

PCIE_MTX_GRX_P13

AA39

PCIE_MTX_GRX_P14

AD42

PCIE_MTX_GRX_P15

AD46

PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0

PCIE_GTX_C_MRX_P3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R163

3

PCIE_MTX_C_GRX_N[0..15] (16)
PCIE_MTX_C_GRX_P[0..15] (16)

PCIE_GTX_C_MRX_N[0..15] (16)
PCIE_GTX_C_MRX_P[0..15] (16)

+VCC_PEG

49.9_0402_1%

49.9_0402_1%

1 2

Please check Power
source if want
support IAMT

C277 0.1U_0402_10V7KPM@C277 0.1U_0402_10V7KPM@

1 2

C303 0.1U_0402_10V7KPM@C303 0.1U_0402_10V7KPM@

1 2

C317 0.1U_0402_10V7KPM@C317 0.1U_0402_10V7KPM@

1 2

C315 0.1U_0402_10V7KPM@C315 0.1U_0402_10V7KPM@

1 2

C325 0.1U_0402_10V7KPM@C325 0.1U_0402_10V7KPM@

1 2

C343 0.1U_0402_10V7KPM@C343 0.1U_0402_10V7KPM@

1 2

C358 0.1U_0402_10V7KPM@C358 0.1U_0402_10V7KPM@

1 2

C349 0.1U_0402_10V7KPM@C349 0.1U_0402_10V7KPM@

1 2

C368 0.1U_0402_10V7KPM@C368 0.1U_0402_10V7KPM@

1 2

C354 0.1U_0402_10V7KPM@C354 0.1U_0402_10V7KPM@

1 2

C371 0.1U_0402_10V7KPM@C371 0.1U_0402_10V7KPM@

1 2

C356 0.1U_0402_10V7KPM@C356 0.1U_0402_10V7KPM@

1 2

C372 0.1U_0402_10V7KPM@C372 0.1U_0402_10V7KPM@

1 2

C364 0.1U_0402_10V7KPM@C364 0.1U_0402_10V7KPM@

1 2

C375 0.1U_0402_10V7KPM@C375 0.1U_0402_10V7KPM@

1 2

C348 0.1U_0402_10V7KPM@C348 0.1U_0402_10V7KPM@

1 2

C271 0.1U_0402_10V7KPM@C271 0.1U_0402_10V7KPM@

1 2

C296 0.1U_0402_10V7KPM@C296 0.1U_0402_10V7KPM@

1 2

C314 0.1U_0402_10V7KPM@C314 0.1U_0402_10V7KPM@

1 2

C311 0.1U_0402_10V7KPM@C311 0.1U_0402_10V7KPM@

1 2

C322 0.1U_0402_10V7KPM@C322 0.1U_0402_10V7KPM@

1 2

C336 0.1U_0402_10V7KPM@C336 0.1U_0402_10V7KPM@

1 2

C352 0.1U_0402_10V7KPM@C352 0.1U_0402_10V7KPM@

1 2

C344 0.1U_0402_10V7KPM@C344 0.1U_0402_10V7KPM@

1 2

C363 0.1U_0402_10V7KPM@C363 0.1U_0402_10V7KPM@

1 2

C346 0.1U_0402_10V7KPM@C346 0.1U_0402_10V7KPM@

1 2

C366 0.1U_0402_10V7KPM@C366 0.1U_0402_10V7KPM@

1 2

C351 0.1U_0402_10V7KPM@C351 0.1U_0402_10V7KPM@

1 2

C367 0.1U_0402_10V7KPM@C367 0.1U_0402_10V7KPM@

1 2

C359 0.1U_0402_10V7KPM@C359 0.1U_0402_10V7KPM@

1 2

C373 0.1U_0402_10V7KPM@C373 0.1U_0402_10V7KPM@

1 2

C347 0.1U_0402_10V7KPM@C347 0.1U_0402_10V7KPM@

1 2

C670 0.1U_0402_10V7KHDMI_GM@ C670 0.1U_0402_10V7KHDMI_GM@

1 2

C674 0.1U_0402_10V7KHDMI_GM@ C674 0.1U_0402_10V7KHDMI_GM@

1 2

C669 0.1U_0402_10V7KHDMI_GM@ C669 0.1U_0402_10V7KHDMI_GM@

1 2

C673 0.1U_0402_10V7KHDMI_GM@ C673 0.1U_0402_10V7KHDMI_GM@

1 2

C662 0.1U_0402_10V7KHDMI_GM@ C662 0.1U_0402_10V7KHDMI_GM@

1 2

C663 0.1U_0402_10V7KHDMI_GM@ C663 0.1U_0402_10V7KHDMI_GM@

1 2

C658 0.1U_0402_10V7KHDMI_GM@ C658 0.1U_0402_10V7KHDMI_GM@

1 2

C661 0.1U_0402_10V7KHDMI_GM@ C661 0.1U_0402_10V7KHDMI_GM@

1 2

C306 0_0402_5%HDMI_GM@ C306 0_0402_5%HDMI_GM@

1 2

R

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0

PCIE_MTX_C_GRX_P1

PCIE_MTX_C_GRX_P2

PCIE_MTX_C_GRX_P3

PCIE_MTX_C_GRX_P4

PCIE_MTX_C_GRX_P5

PCIE_MTX_C_GRX_P6

PCIE_MTX_C_GRX_P7

PCIE_MTX_C_GRX_P8

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

TMDS_B_CLK (23)
TMDS_B_CLK# (23)
TMDS_B_DATA0 (23)
TMDS_B_DATA0# (23)
TMDS_B_DATA1 (23)
TMDS_B_DATA1# (23)
TMDS_B_DATA2 (23)
TMDS_B_DATA2# (23)

TMDS_B_HPD# (23)

2

CFG[4:3] Reserved

CFG5 (DMI select)

CFG6

CFG6

CFG7 (Intel Management
Engine Crypto strap)

CFG8

CFG9
(PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11
CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable

*

1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in order

0 = Enable
1 = Disable
Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

*

(Default)11 = Normal Operation

ReservedCFG[15:14]

0 = Disabled
1 = Enabled

*

ReservedCFG[18:17]

0 = Normal Operation

(Lane number in Order)

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

10 53Saturday, June 06, 2009

10 53Saturday, June 06, 2009

10 53Saturday, June 06, 2009

1

*

*

*

*

I

I

I

of

of

of

5

GM@

GM@

+3VS_DAC_CRT

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

2

GM@

GM@
C206

C206

0.022U_0402_16V7K

0.022U_0402_16V7K
10U_0805_10V4Z

10U_0805_10V4Z

C681

C681

1

1

C213

C213

@

@

2

2

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

+3VS

R120

R120

1 2

0_0603_5%

0_0603_5%

GM@

GM@

VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1)

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

GM@

GM@

2

GM@

GM@
R117

R117

1 2

0_0603_5%

0_0603_5%

0.022U_0402_16V7K

0.022U_0402_16V7K

C181

C181

0_0402_5%

0_0402_5%

PM@

PM@

+3VS_DAC_BG

1

C638

C638

C637

C637

2

1

C181

C181

2

0.022U_0402_16V7K

0.022U_0402_16V7K

GM@

GM@

C639

C639

C206

C206

0_0402_5%

0_0402_5%

PM@

PM@

+VCCP

+3VS_TVDAC

1

2

GM@

GM@

10U_0805_10V4Z

10U_0805_10V4Z

1

GM@

GM@

2

C605

C605

150U_D_6.3VM

150U_D_6.3VM

C171

C171

0.1U_0402_16V4Z

0.1U_0402_16V4Z

GM@

GM@

+1.5VS_PEG_BG: 0.414mA
(0.1UF*1)

+1.5VS

0_0603_5%

0_0603_5%

R108

R108

1 2

0_0805_5%

0_0805_5%

1

+

+

2

10U_0805_10V4Z

10U_0805_10V4Z

R134

R134

0_0603_5%

0_0603_5%

C87

C87

12

C194

C194

R166

R166

1

2

+1.05VS_A_SM_CK

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

2

+1.5VS_PEG_BG

12

4.7U_0805_10V4Z

4.7U_0805_10V4Z
C96

C96

10U_0805_10V4Z

10U_0805_10V4Z

1

C211

C211

2

+3VS

D D

C C

B B

R115

R115

1 2

0_0603_5%

0_0603_5%

GM@

GM@

C637

C637

0_0402_5%

0_0402_5%

PM@

PM@

VCCA_SM:720mA
(22UF*2, 4.7UF*1, 1UF*1)

VCCA_SM_CK: 220mA
(22UF*1, 2.2UF*1, 0.1UF*1)

+3VS

4

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_DPLLA
+1.05VS_DPLLB

+1.05VS_HPLL
+1.05VS_MPLL

+1.8V_TXLVDS

1000P_0402_50V7K

1000P_0402_50V7K

1

C301

C301

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C214

C214

1

2

+3VS_TVDAC: 40mA
(0.1UF*1, 0.01UF*1 for
each DAC)

VCC_HDA: 50mA
(0.1UF*1)

+1.05VS_PEGPLL

+1.05VS_A_SM

1

1U_0603_10V4Z

1U_0603_10V4Z

2

1U_0603_10V4Z

1U_0603_10V4Z

C210

C210

+3VS_TVDAC

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

+1.5VS_TVDAC
+1.5VS_QDAC

+1.05VS_HPLL

+1.05VS_PEGPLL

+1.8V_LVDS

C300

C300
GM@

GM@

+1.5VS

20 mils

1

C102

C102

2

U26H

U26H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

GM@

GM@

CRTPLLA LVDSA PEG

CRTPLLA LVDSA PEG

POWER

POWER

A SM

A SM

TV

TV

HDA

HDA

LVDS D TV/CRT

LVDS D TV/CRT

U26

U26

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14

VTT

VTT

VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

A CK

A CK

VCC_HV_1
VCC_HV_2
VCC_HV_3

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

DMI PEG

DMI PEG

VTTLF1
VTTLF2
VTTLF3

VTTLF

VTTLF

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

3

+VCCP

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

BF21
BH20
BG20
BF20

K47

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

220U_D2_4VM

220U_D2_4VM

1

+

+

@

@

C606

C606

C265

C265

2

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K
1

1

C136

C136

C126

C126

2

2

in B test ,
please change C126 to 0402 size

+V1.05VS_AXF

+1.8V_SM_CK

+1.8V_TXLVDS

+3VS_HV

1

C649

C649

2

+VCC_PEG

+VCC_DMI

VCC_DMI: 456mA
(0.1UF*1)

20mils

A8
L1
AB2

C94 0.47U_0402_6.3V6KC94 0.47U_0402_6.3V6K

1

2

C618 0.47U_0402_6.3V6KC618 0.47U_0402_6.3V6K

C611 0.47U_0402_6.3V6KC611 0.47U_0402_6.3V6K

1

1

2

2

2

C278

C278

0_0402_5%

0_0402_5%

PM@

PM@

C312

C312

0_0402_5%

0_0402_5%

PM@

PM@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VCCP

+3VS

+1.05VS_DPLLA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C278

C278

1

2
GM@

GM@

+1.05VS_DPLLB

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C312

C312

1

2
GM@

GM@

+1.05VS_HPLL

1

C609

C609

2

+1.05VS_MPLL

1

C608

C608

2

+1.05VS_PEGPLL

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C342

C342

1

2

+VCCP_D

@

@

D1

D1

2 1

CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

10U_0805_10V4Z

10U_0805_10V4Z

MCK3225151YZF_1210

MCK3225151YZF_1210

1

C275

C275

2

GM@

GM@

+1.05VS_DPLLA
+1.05VS_DPLLB: 64.8mA
(470UF*1, 0.1UF*1)

R191

R191

1 2

10U_0805_10V4Z

10U_0805_10V4Z

MCK3225151YZF_1210

MCK3225151YZF_1210

1

GM@

GM@

C310

C310

2

GM@

GM@

R474

R474

MBK2012121YZF_0805

MBK2012121YZF_0805

1

C604

C604

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

R473

R473

MBK2012121YZF_0805

MBK2012121YZF_0805

1

C603

C603

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1

C355

C355

2.2U_0603_10V6K

2.2U_0603_10V6K

2

@

@
R158

R158

12

10_0402_5%

10_0402_5%

R151

R151

+VCCP

GM@

GM@

+VCCP

+1.05VS_HPLL: 24mA
(4.7UF*1, 0.1UF*1)

12

+VCCP

1.05VS_MPLL: 139.2mA
(22UF*1, 0.1UF*1)

12

+VCCP

+1.5VS_PEG_PLL: 50mA
(0.1UF*1)

L17

L17

12

+VCCP

R157

R157

12

0_0402_5%

0_0402_5%

+3VS_HV

+V1.05VS_AXF

+1.5VS_TVDAC

40 mils

1000P_0402_50V7K

1000P_0402_50V7K

1

C299

C299

GM@

GM@

2

+VCC_PEG

1

C339

C339

+

+

2

0316 add

+VCC_DMI

C337

C337

1

2

0316 add

10U_0805_10V4Z

10U_0805_10V4Z

1

2

1

C180

C180

2

GM@

GM@

+1.8V_TXLVDS

220U_D2_4VM

220U_D2_4VM

1U_0603_10V4Z

1U_0603_10V4Z

C629

C629

0.022U_0402_16V7K

0.022U_0402_16V7K

C370

C370

C323

C323

C353

C353

1U_0603_10V4Z

1U_0603_10V4Z

+1.8V_SM_CK

C627

C627

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C195

C195

2

GM@

GM@

10U_0805_10V4Z

10U_0805_10V4Z

1

2

10U_0805_10V4Z

10U_0805_10V4Z

1

2

10U_0805_10V4Z

10U_0805_10V4Z

1

2

C631

C631

1

2

10U_0805_10V4Z

10U_0805_10V4Z

1

2

C198

C198

1

2

R208

R208

0_0603_5%

0_0603_5%

GM@

GM@

GM@

GM@

R186

R186

0_0805_5%

0_0805_5%

C784

C784

1

2

1

GM@

GM@

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

0_0805_5%

0_0805_5%

VCC_AXF: 321.35mA
(10UF*1, 1UF*1)

+VCCP

R495

R495

0_0603_5%

0_0603_5%

VCC_SM_CK: 119.85mA
(10UF*1, 0.1UF*1)

1

2

VCCD_TVDAC: 58.696mA
(0.1UF*1, 0.01UF*1)

+1.8V_TXLVDS: 118.8mA
(22UF*1, 1000PF*1)

+VCCP

12

R202

R202

R496

R496

1 2

0_0805_5%

0_0805_5%

C628

C628

R136

R136

0_0603_5%

0_0603_5%

GM@

GM@

C180

C180

0_0402_5%

0_0402_5%

PM@

PM@

+1.8V

12

C299

C299

0_0402_5%

0_0402_5%

PM@

PM@

+VCCP

+1.8V

+1.5VS

12

PM

PM

PM@

PM@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C207

C207

2

2

5

VCCD_QDAC: 48.363mA
(0.1UF*1, 0.01UF*1)

R142

R142

12

0_0603_5%

0_0603_5%

10U_0805_10V4Z

10U_0805_10V4Z

1

C221

C221

2

GM@

GM@

+1.5VS

+1.8V_LVDS

10U_0805_10V4Z

10U_0805_10V4Z

C226

C226

GM@

GM@

1

2

+1.5VS_QDAC

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C208

GM@

GM@

C208

A A

1.8V_LVDS: 60.311111mA
(1UF*1)

R137

R137

0_0603_5%

0_0603_5%

1U_0603_10V4Z

1U_0603_10V4Z

GM@

GM@

C237

C237

1

2

GM@

GM@

12

C237

C237

0_0603_5%

0_0603_5%

PM@

PM@

4

+1.8V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

1

of

of

of

11 53Saturday, June 06, 2009

11 53Saturday, June 06, 2009

11 53Saturday, June 06, 2009

I

I

I

5

D D

+VCCP

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1

C178

C178

2

C C

B B

A A

0.1U_0402_16V4Z

C175

C175

C220

C193

C193

1

2

C220

1

1

2

2

AG34
AC34
AB34
AA34

AM33

AK33

AJ33
AG33
AF33

AE33
AC33
AA33

W33

AH28
AF28
AC28
AA28

AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24

AJ23
AH23
AF23

U26G

U26G

VCC_1
VCC_2
VCC_3
VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15

Y33

VCC_16
VCC_17

V33

VCC_18

U33

VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

T32

VCC_35

GM@

GM@

VCC CORE

VCC CORE

5

POWER

POWER

VCC NCTF

VCC NCTF

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

4

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

4

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+VCCP

3

U26F

U26F

AP33

VCC_SM_1

AN33

VCC_SM_2

C645

C645

T32T32
T31T31

Deciphered Date

Deciphered Date

Deciphered Date

BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16

BB21
AW16
AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21
AG21
AE21
AC21
AA21

AH20
AF20
AE20
AC20
AB20
AA20

AM15

AL15
AE15

AJ15
AH15
AG15
AF15
AB15
AA15

AN14
AM14

AJ14
AH14

Y26

Y24

Y21

T17
T16

Y15
V15
U15

U14
T14

VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

VCC_AXG_SENSE
VSS_AXG_SENSE

GM@

GM@

+1.8V

220U_D2_4VM_R15

220U_D2_4VM_R15

1

C177

C177

+

+

2

+VCCP +AXG_CORE

1U_0603_10V4Z

1U_0603_10V4Z

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

J4

J4

112

JUMP_43X118

JUMP_43X118

+AXG_CORE

GM@

GM@

C149

C149

Issued Date

Issued Date

Issued Date

@

@

2

1

GM@

GM@

1

+

+

C84

C84

2

2

220U_D2_4VM_R15

220U_D2_4VM_R15

C104

C104

0_0805_5%

0_0805_5%

PM@

PM@

3

10U_0805_10V4Z

10U_0805_10V4Z

GM@

GM@
C104

C104

C157

C157

0_0805_5%

0_0805_5%

PM@

PM@

10U_0805_10V4Z

10U_0805_10V4Z

0.01U_0402_16V7K

0.01U_0402_16V7K

C643

C643

1

2

GM@

GM@

1

C157

C157

2

10U_0805_10V4Z

10U_0805_10V4Z

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

0.1U_0402_16V4Z

0.1U_0402_16V4Z

GM@

GM@

1

C167

C167

2

2

1

1

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC SM

VCC SM

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52

POWER

POWER

VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC GFX

VCC GFX

VCC SM LF

VCC SM LF

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

2

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

1

C101 0.22U_0402_10V4ZC101 0.22U_0402_10V4Z

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

C129

C129

1

GM@ C99

GM@

2

C159 0.22U_0402_10V4ZC159 0.22U_0402_10V4Z

1

1

2

2

1

+AXG_CORE

1

C99

2

C264 0.47U_0402_6.3V6KC264 0.47U_0402_6.3V6K

C243 1U_0402_6.3V6KC243 1U_0402_6.3V6K

1

2

C99

C99

0_0603_5%

0_0603_5%

PM@

PM@

1

2

12 53Saturday, June 06, 2009

12 53Saturday, June 06, 2009

12 53Saturday, June 06, 2009

C297 1U_0402_6.3V6KC297 1U_0402_6.3V6K

of

of

of

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Check : power

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C197

C197

1

GM@

GM@

GM@

GM@

2

0.22U_0402_10V4Z

0.22U_0402_10V4Z

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

C114 0.1U_0402_16V4ZC114 0.1U_0402_16V4Z

C121 0.1U_0402_16V4ZC121 0.1U_0402_16V4Z

1

1

1

2

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

I

I

I

5

U26I

U26I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

D D

C C

B B

A A

AJ47
AF47
AD47
AB47

BD46
BA46
AY46
AV46
AR46

AM46

BF44
AH44
AD44
AA44

BC43
AV43
AU43

AM43

BG42
AY42
AT42
AN42

AJ42
AE42

BD41
AU41

AM41

AH41
AD41
AA41

BG40
BB40
AV40
AN40

AT39

AM39

AJ39
AE39

BH38
BC38
BA38
AU38
AH38
AD38
AA38

BF37
BB37

AW37

AT37
AN37

AJ37

BG36
BD36
AK15
AU36

VSS_6
VSS_7
VSS_8
VSS_9
VSS_10

Y47

VSS_11

T47

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26
VSS_27
VSS_28
VSS_29
VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44

VSS_34

F44

VSS_35
VSS_36
VSS_37
VSS_38
VSS_39

J43

VSS_40

C43

VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47

N42

VSS_48

L42

VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58

M41

VSS_59

G41

VSS_60

B41

VSS_61
VSS_62
VSS_63
VSS_64
VSS_65

H40

VSS_66

E40

VSS_67
VSS_68
VSS_69
VSS_70
VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93

H37

VSS_94

C37

VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

GM@

GM@

VSS

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

4

U26J

U26J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

G9

VSS_291

B9

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

GM@

GM@

VSS

VSS

3

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9

VSS_NCTF_10

VSS NCTF

VSS NCTF

VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

VSS SCB

VSS SCB

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34

NC

NC

NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

2

1

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

1

of

of

of

13 53Saturday, June 06, 2009

13 53Saturday, June 06, 2009

13 53Saturday, June 06, 2009

I

I

I

5

DDR_A_DQS#[0..7](9)

DDR_A_D[0..63](9)

DDR_A_DM[0..7](9)
DDR_A_DQS[0..7](9)
DDR_A_MA[0..13](9)

D D

Layout Note:
Place near JP41

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C235

C235

C152

C152

1

1

2

2

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C170

C170

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C179

C179

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

56_0804_8P4R_5%

R128

R128

1 2

R133

R133

1 2

R146

R146

1 2

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

56_0804_8P4R_5%

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

56_0804_8P4R_5%

5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

B B

A A

DDR_A_WE#
DDR_A_CAS#
M_ODT1
DDR_CS1_DIMMA#

DDR_A_BS#0
DDR_A_MA10
DDR_A_MA14

DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_MA8

DDR_A_MA9
DDR_A_MA12
DDR_A_BS#2
DDR_CKE0_DIMMA

2.2U_0805_16V4Z

2.2U_0805_16V4Z
1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C209

C209

RP1

RP1

56_0402_5%

56_0402_5%
56_0402_5%

56_0402_5%
56_0402_5%

56_0402_5%

RP6

RP6

RP10

RP10

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C644

C644

1

2

C228

C228

+0.9VS

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

C151

C151

C268

C268

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C236

C236

C161

C161

RP2

RP2

DDR_A_RAS#

18

M_ODT0

27

DDR_A_MA13

36

DDR_CS0_DIMMA#

45

RP5

RP5

DDR_A_BS#1

45

DDR_A_MA0

36

DDR_A_MA2

27

DDR_A_MA4

18

RP9

RP9

DDR_A_MA6

45

DDR_A_MA7

36

DDR_A_MA11

27

DDR_CKE1_DIMMA

18

0.1U_0402_16V4Z

C218

C218

C219

C219

1

1

2

2

0.1U_0402_16V4Z

1

2

C230

C230

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C162

C162

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C223

C223

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4

+DDR_MCH_REF1(15)

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C650

C650

C653

C653

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C217

C217

C163

C163

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

4

1

+

+

C215

C215
470U_D2_2.5VM_R15

470U_D2_2.5VM_R15
@

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C242

C242

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

+DDR_MCH_REF1

1

C404

C404

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C164

C164

3

+1.8V

JP17

JP17

1

VREF

3

+1.8V

12

R225

R225

100_0402_1%

100_0402_1%

12

R232

R232

100_0402_1%

100_0402_1%

EC_TX_P80_DATA(15,35,37)

DDR_CKE0_DIMMA(8)

EC_RX_P80_CLK(15,35,37)

DDR_A_BS#2(9)

DDR_A_BS#0(9)

DDR_A_WE#(9)

DDR_A_CAS#(9)

DDR_CS1_DIMMA#(8)

M_ODT1(8)

EC_RX_P80_CLK_R(15)

CLK_SMBDATA(15,22)

CLK_SMBCLK(15,22)

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9 DDR_A_D11
DDR_A_D15 DDR_A_D10

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1

DDR_A_D37
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D38 DDR_A_D34
DDR_A_D32

DDR_A_D40
DDR_A_D44

DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48
EC_RX_P80_CLK_R
DDR_A_DQS#6

DDR_A_DQS6

DDR_A_D50
DDR_A_D61 DDR_A_D57

DDR_A_D60
DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C83

C83

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

FOX_ASOA426-M2RN-7F
ME@

ME@

SO-DIMM A

Top side

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VSS
DQ4
DQ5
VSS

DM0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SA0

SA1

2

+1.8V

+DDR_MCH_REF1

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34
36
38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D33
DDR_A_D39

DDR_A_DM4
DDR_A_D35

DDR_A_D45
DDR_A_D43

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D47
DDR_A_D42

DDR_A_D52
DDR_A_D53

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_DM6
DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R77

R77

R73

R73

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C388

C388

1

2

M_CLK_DDR0 (8)
M_CLK_DDR#0 (8)

PM_EXTTS#0 (8)

DDR_CKE1_DIMMA (8)

DDR_A_MA14 (9)

DDR_A_BS#1 (9)
DDR_A_RAS# (9)
DDR_CS0_DIMMA# (8)

M_ODT0 (8)

M_CLK_DDR1 (8)
M_CLK_DDR#1 (8)

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

1

C402

C402

+DDR_MCH_REF1 (15)

1

I

I

I

of

of

of

14 53Saturday, June 06, 2009

14 53Saturday, June 06, 2009

14 53Saturday, June 06, 2009

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

2

5

DDR_B_DQS#[0..7](9)

DDR_B_D[0..63](9)

DDR_B_DM[0..7](9)
DDR_B_DQS[0..7](9)
DDR_B_MA[0..13](9)

D D

Layout Note:
Place near JP42

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

RP4

RP4

RP7

RP7

RP11

RP11

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C241

C241

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C187

C187

DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#DDR_CS3_DIMMB#
DDR_B_RAS#

DDR_B_BS#1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4

DDR_B_MA7
DDR_B_MA6
DDR_B_MA11
DDR_CKE3_DIMMB

0.1U_0402_16V4Z
C192

C192

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C247

C247

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C188

C188

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C246

C246

C229

C229

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C232

C232

C150

C150

1

1

2

2

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

B B

A A

DDR_B_CAS#
DDR_B_WE#

M_ODT3

DDR_B_BS#0
DDR_B_MA10
DDR_B_MA14

DDR_B_MA1
DDR_B_MA3
DDR_B_MA5
DDR_B_MA9

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA8

1

2

C244

C244

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C240

C240

56_0804_8P4R_5%

56_0804_8P4R_5%

R135

R135
R131

R131
R152

R152

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

5

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C227

C227

RP3

RP3

1 2
56_0402_5%

56_0402_5%

56_0402_5%

56_0402_5%
1 2

56_0402_5%

56_0402_5%
1 2

RP8

RP8

RP12

RP12

C387

C387

1

2

C216

C216

+0.9VS

18
27
36
45

45
36
27
18

18
27
36
45

2.2U_0805_16V4Z
C156

C156

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C196

C196

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

56_0804_8P4R_5%

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

56_0804_8P4R_5%

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

56_0804_8P4R_5%

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C191

C191

C199

C199

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C204

C204

C222

C222

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C185

C185

1

+

+

C155

C155
470U_D2_2.5VM_R15

470U_D2_2.5VM_R15
@

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C176

C176

3

+1.8V

JP16

JP16

1

VREF

3
DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D25

T80T80

EC_TX_P80_DATA(14,35,37)

DDR_CKE2_DIMMB(8)

EC_RX_P80_CLK(14,35,37)

DDR_B_BS#2(9)

DDR_B_BS#0(9)
DDR_B_WE#(9)

DDR_B_CAS#(9)

DDR_CS3_DIMMB#(8)

M_ODT3(8)

T22T22

EC_RX_P80_CLK_R(14)

CLK_SMBDATA(14,22)

CLK_SMBCLK(14,22)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_B_D28
DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
EC_RX_P80_CLK_R
DDR_B_DQS#6

DDR_B_DQS6

DDR_B_D50
DDR_B_D56

DDR_B_D61
DDR_B_DM7
DDR_B_D58

DDR_B_D59
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C82

C82

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-NARN-7F~N

FOX_AS0A426-NARN-7F~N
ME@

ME@

SO-DIMM B

Deciphered Date

Deciphered Date

Deciphered Date

DQS3#

NC/CKE1

NC/A15
NC/A14

NC/A13

DQS5#

DQS7#

DM0

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3
DQ30

DQ31

VDD

VDD

VDD

VDD

RAS#

VDD

ODT0

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7
DQ62

DQ63

SAO

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2

+1.8V

+DDR_MCH_REF1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_D14

DDR_B_D15

DDR_B_D21
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_DM6
DDR_B_D54DDR_B_D51

DDR_B_D55
DDR_B_D60

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%

10K_0402_5%

12

R78

R78

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C403

C403

2

2

M_CLK_DDR2 (8)
M_CLK_DDR#2 (8)

PM_EXTTS#1 (8)

DDR_CKE3_DIMMB (8)

DDR_B_MA14 (9)

DDR_B_BS#1 (9)
DDR_B_RAS# (9)
DDR_CS2_DIMMB# (8)

M_ODT2 (8)

M_CLK_DDR3 (8)
M_CLK_DDR#3 (8)

R74

R74

1 2
10K_0402_5%

10K_0402_5%

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

+3VS

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

401557

401557

1

+DDR_MCH_REF1 (14)

C407

C407

1

I

I

I

of

15 53Saturday, June 06, 2009

of

15 53Saturday, June 06, 2009

of

15 53Saturday, June 06, 2009

5

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

CLK_PCIE_VGA
CLK_PCIE_VGA#

1 2

R183 200_0402_5% @R183 200_0402_5% @
R504 2.4K_0402_1% PM@R504 2.4K_0402_1% PM@

PLT_RST#

10K_0402_5%

10K_0402_5%

1 2

R173

@R173

@

XTALOUT
XTALIN

PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P4

PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15

12

PCIE_MTX_C_GRX_N[0..15](10)
PCIE_MTX_C_GRX_P[0..15](10)
PCIE_GTX_C_MRX_N[0..15](10)
PCIE_GTX_C_MRX_P[0..15](10)

D D

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4

C C

PCIE_GTX_C_MRX_N4 PCIE_GTX_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

B B

OSC_SPREAD

10K_0402_5%

10K_0402_5%

If External Spread Spectrum not stuff than stuff resistor

C261 0.1U_0402_16V7KPM@C261 0.1U_0402_16V7KPM@
C260 0.1U_0402_16V7KPM@C260 0.1U_0402_16V7KPM@
C294 0.1U_0402_16V7KPM@C294 0.1U_0402_16V7KPM@
C293 0.1U_0402_16V7KPM@C293 0.1U_0402_16V7KPM@
C259 0.1U_0402_16V7KPM@C259 0.1U_0402_16V7KPM@
C258 0.1U_0402_16V7KPM@C258 0.1U_0402_16V7KPM@
C292 0.1U_0402_16V7KPM@C292 0.1U_0402_16V7KPM@
C291 0.1U_0402_16V7KPM@C291 0.1U_0402_16V7KPM@
C257 0.1U_0402_16V7KPM@C257 0.1U_0402_16V7KPM@
C256 0.1U_0402_16V7KPM@C256 0.1U_0402_16V7KPM@
C290 0.1U_0402_16V7KPM@C290 0.1U_0402_16V7KPM@
C289 0.1U_0402_16V7KPM@C289 0.1U_0402_16V7KPM@
C255 0.1U_0402_16V7KPM@C255 0.1U_0402_16V7KPM@
C254 0.1U_0402_16V7KPM@C254 0.1U_0402_16V7KPM@
C287 0.1U_0402_16V7KPM@C287 0.1U_0402_16V7KPM@
C288 0.1U_0402_16V7KPM@C288 0.1U_0402_16V7KPM@
C253 0.1U_0402_16V7KPM@C253 0.1U_0402_16V7KPM@
C252 0.1U_0402_16V7KPM@C252 0.1U_0402_16V7KPM@
C285 0.1U_0402_16V7KPM@C285 0.1U_0402_16V7KPM@
C286 0.1U_0402_16V7KPM@C286 0.1U_0402_16V7KPM@
C251 0.1U_0402_16V7KPM@C251 0.1U_0402_16V7KPM@
C250 0.1U_0402_16V7KPM@C250 0.1U_0402_16V7KPM@
C284 0.1U_0402_16V7KPM@C284 0.1U_0402_16V7KPM@
C283 0.1U_0402_16V7KPM@C283 0.1U_0402_16V7KPM@
C249 0.1U_0402_16V7K

C249 0.1U_0402_16V7K
C248 0.1U_0402_16V7K

C248 0.1U_0402_16V7K
C282 0.1U_0402_16V7KPM@C282 0.1U_0402_16V7KPM@
C281 0.1U_0402_16V7KPM@C281 0.1U_0402_16V7KPM@
C267 0.1U_0402_16V7KPM@C267 0.1U_0402_16V7KPM@
C266 0.1U_0402_16V7KPM@C266 0.1U_0402_16V7KPM@
C280 0.1U_0402_16V7KPM@C280 0.1U_0402_16V7KPM@
C279 0.1U_0402_16V7KPM@C279 0.1U_0402_16V7KPM@

12

R99

R99

PM@

PM@

PM@

PM@
PM@

PM@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

R100

R100
10K_0402_5%

10K_0402_5%
PM@

PM@

CLK_PCIE_VGA(22)
CLK_PCIE_VGA#(22)

PLT_RST#(8,26,32,33,36,40)

4

U27A

U27A

AE12

PEX_RX0

AF12

PEX_RX0_N

AG12

PEX_RX1

AG13

PEX_RX1_N

AF13

PEX_RX2

AE13

PEX_RX2_N

AE15

PEX_RX3

AF15

PEX_RX3_N

AG15

PEX_RX4

AG16

PEX_RX4_N

AF16

PEX_RX5

AE16

PEX_RX5_N

AE18

PEX_RX6

AF18

PEX_RX6_N

AG18

PEX_RX7

AG19

PEX_RX7_N

AF19

PEX_RX8

AE19

PEX_RX8_N

AE21

PEX_RX9

AF21

PEX_RX9_N

AG21

PEX_RX10

AG22

PEX_RX10_N

AF22

PEX_RX11

AE22

PEX_RX11_N

AE24

PEX_RX12

AF24

PEX_RX12_N

AG24

PEX_RX13

AF25

PEX_RX13_N

AG25

PEX_RX14

AG26

PEX_RX14_N

AF27

PEX_RX15

AE27

PEX_RX15_N

AD10

PEX_TX0

AD11

PEX_TX0_N

AD12

PEX_TX1

AC12

PEX_TX1_N

AB11

PEX_TX2

AB12

PEX_TX2_N

AD13

PEX_TX3

AD14

PEX_TX3_N

AD15

PEX_TX4

AC15

PEX_TX4_N

AB14

PEX_TX5

AB15

PEX_TX5_N

AC16

PEX_TX6

AD16

PEX_TX6_N

AD17

PEX_TX7

AD18

PEX_TX7_N

AC18

PEX_TX8

AB18

PEX_TX8_N

AB19

PEX_TX9

AB20

PEX_TX9_N

AD19

PEX_TX10

AD20

PEX_TX10_N

AD21

PEX_TX11

AC21

PEX_TX11_N

AB21

PEX_TX12

AB22

PEX_TX12_N

AC22

PEX_TX13

AD22

PEX_TX13_N

AD23

PEX_TX14

AD24

PEX_TX14_N

AE25

PEX_TX15

AE26

PEX_TX15_N

AB10

PEX_REFCLK

AC10

PEX_REFCLK_N

AF10

PEX_TSTCLK_OUT

AE10

PEX_TSTCLK_OUT_N

AG10

PEX_TERMP

AD9

PEX_RST_N

D11

XTAL_SSIN

E9

XTAL_OUTBUFF

E10

XTAL_OUT

D10

XTAL_IN

PM@

PM@

NB9M-GS_BGA533

NB9M-GS_BGA533

External Spread Spectrum

Part 1 of 5

Part 1 of 5

GPIO

GPIO

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_VREF
DACA_RSET

DACB_CSYNC

DACB_RED

DACB_BLUE

DACB_GREEN

DACBI2CHDA DACADACC

DACBI2CHDA DACADACC

DACB_VREF
DACB_RSET

DACC_HSYNC
DACC_VSYNC

DACC_RED

DACC_BLUE

DACC_GREEN

DACC_VREF
DACC_RSET

I2CA_SCL
I2CA_SDA
I2CB_SCL

PCI EXPRESS

PCI EXPRESS

I2CB_SDA
I2CC_SCL

I2CC_SDA

I2CD_SCL

I2CD_SDA

I2CE_SCL
I2CE_SDA
I2CH_SCL

I2CH_SDA

I2CS_SCL
I2CS_SDA

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST_N

TEST

TEST

TESTMODE

VDD_SENSE

HDA_RST_N

HDA_SDI

CLK

CLK

HDA_SDO
HDA_SYNC
HDA_BCLK

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

SPDIF

3

N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2

AD2
AD1

AE2
AD3
AE3

AF1
AE1

D6
F7

E6
E7

G6
F8

U6
U4

T5
R4
T4

R6
V6

R1
T3
R2
R3
A2
B1
N2
N3
Y6
W6
A3
A4
T1
T2

AF3
AG4
AE4
AF4
AG3
AD25

F9
W15

C6
A6
B6
B7
A7

NV_INVTPWM
VGA_ENVDD
VGA_ENBKL

VGA_HSYNC
VGA_VSYNC

VGA_CRT_R
VGA_CRT_B
VGA_CRT_G

DACA_VREF
DACA_RSET

R116 2.2K_0402_5% PM@R116 2.2K_0402_5% PM@
R119 2.2K_0402_5% PM@R119 2.2K_0402_5% PM@

R196 2.2K_0402_5% PM@R196 2.2K_0402_5% PM@
R193 2.2K_0402_5% PM@R193 2.2K_0402_5% PM@

SPDIF_IN

HDA_RST_CODEC#_R
HDA_SDIN1_R
HDA_SDOUT_CODEC_R
HDA_SYNC_CODEC_R
HDA_BITCLK_CODEC_R

R503 124_0402_1%PM@R503 124_0402_1%PM@

VGA_DDCCLK_C
VGA_DDCDATA_C

1 2

1 2
VGA_LVDS_SCL_C
VGA_LVDS_SDA_C

1 2

1 2
VGA_HDMI_SCL
VGA_HDMI_SDA

HDCP_SMB_CK1
HDCP_SMB_DAI
EC_SMB_CK2
EC_SMB_DA2

JTAG_TCK
JTAG_TDO
JTAG_TRST_N

TESTMODE

+VGASENSE

2

12

R69

R69
10K_0402_5%

10K_0402_5%
HDMI_PM@

HDMI_PM@

12

R71

R71
10K_0402_5%

10K_0402_5%
@

@

JTAG_TRST_N
TESTMODE

L39 MBK1608121YZF_0603PM@L39 MBK1608121YZF_0603PM@

1 2
1 2

L40 MBK1608121YZF_0603PM@L40 MBK1608121YZF_0603PM@
L41

L41

1 2
1 2

L42 MBK1608121YZF_0603PM@L42 MBK1608121YZF_0603PM@

12P_0402_50V8J

12P_0402_50V8J

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA_HDMI_SDA
VGA_HDMI_SCL
VGA_DDCCLK
VGA_DDCDATA

MBK1608121YZF_0603PM@

MBK1608121YZF_0603PM@

C770

C770

12P_0402_50V8JPM@

12P_0402_50V8JPM@

PM@

PM@

12

R65

R65
10K_0402_5%

10K_0402_5%
@

@

12

R66

R66
10K_0402_5%

10K_0402_5%
@

@

1 2
1 2

R492 2.2K_0402_5%@R492 2.2K_0402_5%@
R490 2.2K_0402_5%@R490 2.2K_0402_5%@
R489 2.2K_0402_5%@R489 2.2K_0402_5%@
R491 2.2K_0402_5%@R491 2.2K_0402_5%@

R164 150_0402_1%PM@R164 150_0402_1%PM@
R168 150_0402_1%PM@R168 150_0402_1%PM@
R180 150_0402_1%PM@R180 150_0402_1%PM@

R645

R645
R646

R646
10K_0402_5%PM@

10K_0402_5%PM@

1 2
1 2
1 2
1 2

VGA_DDCCLK_C

R75

R75

10K_0402_5%

10K_0402_5%

HDMI_PM@

HDMI_PM@

VGA_DDCDATA_C

VGA_LVDS_SCL_C
VGA_LVDS_SDA_C

+3VS

12

HDMI_DETECT_VGA (23) VGA_DDCDATA (25)

PAD

PAD

T86

T86
VGA_ENVDD (24)
VGA_ENBKL (24)

PAD

PAD

T29

T29

VGA_HSYNC (25)
VGA_VSYNC (25)

VGA_CRT_R (25)
VGA_CRT_B (25)
VGA_CRT_G (25)

PM@

PM@

12

C648 0.1U_0402_16V4Z

C648 0.1U_0402_16V4Z

EC_SMB_CK2 (5,35,41)
EC_SMB_DA2 (5,35,41)

PAD

PAD

PAD

PAD

PAD

PAD

PAD

PAD

PAD

PAD

T28

T28

R650 22_0402_5%PM@R650 22_0402_5%PM@

1 2

R86 10_0402_5%PM@R86 10_0402_5%PM@

1 2

R651 22_0402_5%PM@R651 22_0402_5%PM@

1 2

R652 22_0402_5%PM@R652 22_0402_5%PM@

1 2

R653 22_0402_5%PM@R653 22_0402_5%PM@

1 2

12

R647

R647
10K_0402_5%

10K_0402_5%
@

@

VGA_HDMI_SCL (23)
VGA_HDMI_SDA (23)

T60

T60
T59

T59
T92

T92
T57

T57

+VGASENSE

CRT OUT

HDCP_SMB_CK1
HDCP_SMB_DAI

+3VS

HDA_RST_CODEC# (8,27,30)
HDA_SDIN1 (27)
HDA_SDOUT_CODEC (8,27,30)
HDA_SYNC_CODEC (8,27,30)
HDA_BITCLK_CODEC (8,27,30)

1

1

1

1

C771

C771

C772

C772

C773

C773

2

2

2

12P_0402_50V8JPM@

12P_0402_50V8JPM@

PM@

PM@

12P_0402_50V8J

12P_0402_50V8J

1 2
1 2
1 2

C79

HDMI_PM@C79

HDMI_PM@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

U4

U4

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SU-2.7_SO8

AT24C16AN-10SU-2.7_SO8

HDMI_PM@

HDMI_PM@

10K_0402_5%PM@

10K_0402_5%PM@

VGA_DDCCLK (25)

VGA_LVDS_SCL (24)
VGA_LVDS_SDA (24)

1

2

A0
A1
A2

GND

100K_0402_1% HDMI_PM@

100K_0402_1% HDMI_PM@

1
2
3
4

12

R70

R70

+3VS

Y3

OUT
GND

PM@

PM@

Y3

4

GND

1

IN

18P_0402_50V8J

18P_0402_50V8J

PM@

PM@

C614

C614

1

2

3
2

27MHZ_16PF_X7S027000BG1H-U

27MHZ_16PF_X7S027000BG1H-U

1

C612

A A

18P_0402_50V8J

18P_0402_50V8J

PM@

PM@

C612

2

5

U3

@U3

@

1
2
3

ASM3P2872AF-06OR_TSOT-23-6

ASM3P2872AF-06OR_TSOT-23-6

4

REFOUT
XOUT
XIN/CLKIN

VSS

MODOUT

VDD

6
5
4

@

@

OSC_SPREAD

1 2

R55 22_0402_5%

R55 22_0402_5%

+3VS

2

C66

C66

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

@

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/15 2008/10/15

2007/10/15 2008/10/15

2007/10/15 2008/10/15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

SCHEMATIC, M/B LA-4211P

401557

16 53Saturday, June 06, 2009

16 53Saturday, June 06, 2009

16 53Saturday, June 06, 2009

1

of

of

of

I

I

I