Acer LA-4011 Schematics

ZZZ1

ZZZ1

A

ZZZ3

ZZZ2

ZZZ2

ZZZ3

ZZZ4

ZZZ4

ZZZ5

ZZZ5

B

C

D

E

PCB

PCB

PCB

DAZ@

DAZ@

1 1

PCB

PCB

DA2@

DA2@

LA-4011P LS-4011P LS-4012P LS-4013P

PCB

DA2@

DA2@

PCB

PCB

DA2@

DA2@

PCB

PCB

DA2@

DA2@

2 2

Compal Confidential

JAW91 Schematics Document

AMD S1/ ATI RS690M(C) / SB600

2008/11/20

3 3

Rev:1.0

4 4

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

E

of

of

of

138Friday, November 21, 2008

138Friday, November 21, 2008

138Friday, November 21, 2008

C

C

C

A

B

C

D

E

Compal Confidential

Project Code: JAW91
File Name : LA-4011P

1 1

Thermal Sensor
ADM1032ARM

page 6 page 13

Clock Generator
ICS951462

AMD S1 CPU

Athlon x2 TK-XX

page 4,5,6,7

HT 16x16 800MHZ

DDR-2 DDR2-SO-DIMM X2

page 8,9

Daul Channel DDR-2

CRT

page 14

ATI-RS690M(C)

LCD CONN

page 14

PCI EXPRESS

2 2

Realtek

RTL8111B

page 22

Express Card
(New Card)

page 27

Mini Card1
WLAN

page 25

RJ45 CONN

page 22

PCI BUS

CradBus Controller

BGA465

page 10,11,12

A-Link Express

2 x PCIE

ATI-SB600

BGA548

page 15,16,17,18

USB 2.0

HD-Interface

USB conn x 4

page 28

Audio CKT

ALC268

page 23

MDC Conn.

page 23

AMP & Audio Jack

RJ11 CONN(Combine RJ45)

page 24

page 22

Ricoh R5C847

page 20,21

3 3

Slot 0

page 21

Media Card

page 21

1394
Conn.

page 20

Power On/Off CKT.

page 29

LPC BUS

SATA

PATA

SATA HDD Conn.

page 19

HDD Conn.
CDROM Conn.

page 19

ENE KB926

DC/DC Interface CKT.

page 30

Power Circuit DC/DC

page 31~38

4 4

RTC CKT.

page 15

Power OK CKT.

page 29

Touch Pad
CONN.

page 27

page 26

Int. KBD

page 27

SPI BIOS

page 26

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

E

of

of

of

238Friday, November 21, 2008

238Friday, November 21, 2008

238Friday, November 21, 2008

C

C

C

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+
+CPU_CORE
+1.2V_HT
+0.9V 0.9V switched power rail for DDR terminator
+1.2VALW 1.2V always on power rail
+1.5VS
+1.8VS 1.8V switched power rail
+1.8V
+3VALW
+3V
+3VS
+5VALW
+5VS
+RTCVCC RTC power

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2V switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

B

S1 S3 S4/ S5

ON ON ON

ON OFF
ON OFF
ON OFF
ON
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON

ON ONON

ONONON
OFF
OFF

ON

ONON

OFF

ON
ON ON

OFF

ON

OFF

OFF
ON

ON

OFF

OFFON

C

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

LOW LOW LOW LOW

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7NC

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

D

SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

OFF

OFF

V

AD_BID

ON ON

ON

OFF

OFF

OFF

max

LOW

OFF

OFF

OFF

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

V typ

AD_BID

ON

ON

ON

ON

ON

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

E

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus

AD21

0

PIRQE/PIRQF/PIRQG

BOARD ID Table

Board ID

0
1
2
3
4

PCB Revision

0.2 (KH4 ES1)

0.3 (KH4 ES2)

0.4 (KH4 PP)

0.5 (KH4 PPR)

1.0 (KH4 IRT)

BTO Item BOM Structure

BTO Option Table

5
6
7

EC SM Bus1 address

3 3

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b?
1011 000Xb?

EC SM Bus2 address

Device

ADM1032

1001 110X b?0001 011X b?

SB600 SM Bus address

Device

Clock Generator
(ICS 951462AGT)

DDRII DIMM0
DDRII DIMM2

4 4

Address

1101 001Xb?

1001 000Xb?
1001 010Xb?

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

E

of

of

of

338Friday, November 21, 2008

338Friday, November 21, 2008

338Friday, November 21, 2008

C

C

C

5

4

3

2

1

H_CADIP[0..15]<10>

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]
H_CADON[0..15]

H_CADOP[0..15] <10>
H_CADON[0..15] <10>H_CADIN[0..15]<10>

PROCESSOR HYPERTRANSPORT INTERFACE

D D

C C

+1.2V_HT

R236 51_0402_1%R236 51_0402_1%
R235 51_0402_1%R235 51_0402_1%

B B

A A

2006-10-17 Change from 49.9 1% to 51 1%

VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

H_CLKIP1<10>
H_CLKIN1<10>
H_CLKIP0<10>
H_CLKIN0<10>

1 2
1 2

H_CTLIP0<10> H_CTLOP0 <10>
H_CTLIN0<10>

+1.2V_HT

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

H_CTLIP0
H_CTLIN0

D4
D3
D2
D1

N5

P5
M3
M4

L5
M5

K3

K4
H3
H4
G5
H5

F3

F4

E5

F5
N3
N2

L1
M1

L3

L2

J1

K1
G1
H1
G3
G2

E1

F1

E3

E2

J5

K5

J3

J2

P3

P4
N1

P1

+1.2V_HT

1

C4314.7U_0805_6.3V6K~N C4314.7U_0805_6.3V6K~N

2

VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLIN_H0
L0_CTLIN_L0

1

C4284.7U_0805_6.3V6K~N C4284.7U_0805_6.3V6K~N

2

CPU1A

CPU1A

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10

L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0

HTT Interface

HTT Interface

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1
L0_CTLOUT_L1

L0_CTLOUT_H0
L0_CTLOUT_L0

Athlon 64 S1
Processor Socket

1

1

1

C429180P_0402_50V8J~N C429180P_0402_50V8J~N

C427180P_0402_50V8J~N C427180P_0402_50V8J~N

C4300.22U_0603_10V7K C4300.22U_0603_10V7K

C4260.22U_0603_10V7K C4260.22U_0603_10V7K

2

2

2

AE5
AE4
AE3
AE2

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

Y4
Y3
Y1
W1

T5
R5

R2
R3

1

2

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0

H_CTLOP0
H_CTLON0

1 2

C394 4.7U_0805_6.3V6K~NC394 4.7U_0805_6.3V6K~N

H_CLKOP1 <10>
H_CLKON1 <10>
H_CLKOP0 <10>
H_CLKON0 <10>

H_CTLON0 <10>

FAN1 Control and Tachometer

EN_DFAN1<26>

FAN_SPEED1<26>

EN_DFAN1

R38

R38

10K_0402_5%

10K_0402_5%

+3VS

12

2

C114

C114

0.01U_0402_16V7K

0.01U_0402_16V7K

1

+5VS

12

D3

D3

1SS355_SOD323 @

1SS355_SOD323 @

@

@

12

D14 1N4148_SOT23

D14 1N4148_SOT23

C424

C424

10U_0805_10V4Z~N

10U_0805_10V4Z~N

12

C113

C113

1000P_0402_50V7K~N

1000P_0402_50V7K~N

12

FAN1_POWER

+5VS

40mil

1 2

C410 10U_0805_10V4Z~N

C410 10U_0805_10V4Z~N
U20

U20

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8

G993P1UF_SOP8
JFAN1

JFAN1

1
2
3

4

G

5

G

MOLEX_53398-0371~N

MOLEX_53398-0371~N
CONN@

CONN@

GND
GND
GND
GND

8
7
6
5

FAN1

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

1

of

of

of

438Friday, November 21, 2008

438Friday, November 21, 2008

438Friday, November 21, 2008

C

C

C

A

B

C

D

E

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED

ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.8V

4 4

3 3

2 2

12

R222

R222

39.2_0603_1%

39.2_0603_1%

12

R223

R223

39.2_0603_1%

39.2_0603_1%

PLACE THEM CLOSE TO
CPU WITHIN 1"

DDR_CS3_DIMMA#<8>
DDR_CS2_DIMMA#<8>
DDR_CS1_DIMMA#<8>
DDR_CS0_DIMMA#<8>

DDR_CS3_DIMMB#<9>
DDR_CS2_DIMMB#<9>
DDR_CS1_DIMMB#<9>
DDR_CS0_DIMMB#<9>

DDR_CKE1_DIMMB<9>
DDR_CKE0_DIMMB<9>
DDR_CKE1_DIMMA<8>
DDR_CKE0_DIMMA<8>

DDR_A_MA[15..0]<8>

DDR_A_BS#2<8>
DDR_A_BS#1<8>
DDR_A_BS#0<8>

DDR_A_RAS#<8>
DDR_A_CAS#<8>
DDR_A_WE#<8>

DDR_A_CLK2

DDR_A_CLK#2
DDR_A_CLK1

DDR_A_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

TP1TP1

M_ZN
M_ZP

1

C392

C392

1.5P 50V F NPO 0402

1.5P 50V F NPO 0402

2

1

C439

C439

1.5P 50V F NPO 0402

1.5P 50V F NPO 0402

2

+CPU_M_VREF

VTT_SENSE

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

AE10
AF10

W17

Y10

V19
J22
V22
T19

Y26
J24

W24

U23
H26

J23
J20
J21

K19
K20
V24
K24
L20
R19
L19
L22

L21
M19
M20
M24
M22

N22

N21

R21

K22

R20

T22

T20

U20

U21

M_VREF
VTT_SENSE

M_ZN
M_ZP

MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0

MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0

MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

MA_BANK2
MA_BANK1
MA_BANK0

MA_RAS_L
MA_CAS_L
MA_WE_L

Athlon 64 S1
Processor
Socket

CPU1B

CPU1B

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9

MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1

MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10

MB_ADD9

DDRII Cmd/Ctrl//Clk

DDRII Cmd/Ctrl//Clk

MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

MB_BANK2
MB_BANK1
MB_BANK0

MB_RAS_L
MB_CAS_L

MB_WE_L

DDR_B_CLK2

DDR_B_CLK#2
DDR_B_CLK1

DDR_B_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10

Y16
AA16
E16
F16

AF18
AF17
A17
A18

W23
W26
V20
U19

J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24

K26
T26
U26

U24
V26
U22

+0.9V

DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1

DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

1

2

1

2

C393

C393

1.5P 50V F NPO 0402

1.5P 50V F NPO 0402

C438

C438

1.5P 50V F NPO 0402

1.5P 50V F NPO 0402

DDR_A_CLK2 <8>
DDR_A_CLK#2 <8>
DDR_A_CLK1 <8>
DDR_A_CLK#1 <8>

DDR_B_CLK2 <9>
DDR_B_CLK#2 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>

DDR_B_ODT1 <9>
DDR_B_ODT0 <9>
DDR_A_ODT1 <8>
DDR_A_ODT0 <8>

DDR_B_MA[15..0] <9>

DDR_B_BS#2 <9>
DDR_B_BS#1 <9>
DDR_B_BS#0 <9>

DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>

Processor DDR2 Memory Interface

DDR_B_D[63..0]<9>

To reverse SODIMM socket

DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>

DDR_B_DQS7<9>
DDR_B_DQS#7<9>
DDR_B_DQS6<9>
DDR_B_DQS#6<9>
DDR_B_DQS5<9>
DDR_B_DQS#5<9>
DDR_B_DQS4<9>
DDR_B_DQS#4<9>
DDR_B_DQS3<9>
DDR_B_DQS#3<9>
DDR_B_DQS2<9>
DDR_B_DQS#2<9>
DDR_B_DQS1<9>
DDR_B_DQS#1<9>
DDR_B_DQS0<9>
DDR_B_DQS#0<9>

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

AD11
AF11
AF14
AE14

AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24

AD12
AC16
AE22
AB26

AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26

Y11

G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11

E25
A22
B16
A12

F26
E26
A24
A23
D16
C16
C12
B12

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0

CPU1C

CPU1C

DDRII Data

DDRII Data

Athlon 64 S1
Processor Socket

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

MA_DQS_H7

MA_DQS_L7

MA_DQS_H6

MA_DQS_L6

MA_DQS_H5

MA_DQS_L5

MA_DQS_H4

MA_DQS_L4

MA_DQS_H3

MA_DQS_L3

MA_DQS_H2

MA_DQS_L2

MA_DQS_H1

MA_DQS_L1

MA_DQS_H0

MA_DQS_L0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

Y13
AB16
Y19
AC24
F24
E19
C15
E12

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[63..0] <8>

DDR_A_DQS7 <8>
DDR_A_DQS#7 <8>
DDR_A_DQS6 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS5 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS4 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS3 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS2 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS1 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS0 <8>
DDR_A_DQS#0 <8>

To normal SODIMM socket

+1.8V

R35

R35

1K_0402_1%

1K_0402_1%

1 2

1 1

R34

R34

1K_0402_1%

1K_0402_1%

1 2

1

C54

C54

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

A

VDD_VREF_SUS_CPU

+CPU_M_VREF

1

C53

C53

2

1000P_0402_50V7K~N

1000P_0402_50V7K~N

LAYOUT:PLACE CLOSE TO CPU

Placement between CPU to DDR area(Reserved for EMI)

+1.8V

1

C609

C609

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

C613

C613

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

B

1

C610

C610

2

1

C614

C614

2

1

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

C612

C611

C611

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C615

C615

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C612

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

C616

C616

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

A1

Athlon 64 S1g1

uPGA638
Top View

AF1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

E

A26

C

C

538Friday, November 21, 2008

538Friday, November 21, 2008

538Friday, November 21, 2008

C

of

of

of

5

R252

@R252

@

0_0805_5%

0_0805_5%

+3VALW

+3VS +2.5VDDA

R2530_0805_5%

D D

C C

B B

A A

R2530_0805_5%
1U_0603_10V6K

1U_0603_10V6K

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

CPUCLK0_H
CPUCLK0_L

CPU_VDD_FB_H
CPU_VDD_FB_L

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
CPU_THERMTRIP#_R

SB_PWRGD<16,26>

C433

C433

12
12

2

1

470_0402_5%

470_0402_5%

Q42

Q42

@

@

R241

R241

CPU_PWRGD<15>

D

D

S

S

LDT_STOP#<11,15>

LDT_RST#<15>

12

13

2

G

G

SB_PWRGD
LDT_RST#

5

U21

U21

1

IN

2

GND
SHDN3BYP

G914E_SOT23-5

G914E_SOT23-5

SYSON#

TP49PADTP49PAD
TP51PADTP51PAD

TP12PADTP12PAD
TP20PADTP20PAD

TP18PADTP18PAD
TP17PADTP17PAD

TP46PADTP46PAD
TP16PADTP16PAD
TP45PADTP45PAD
TP30PADTP30PAD

2
1

5

OUT

4

C432

C432

0.01U_0402_16V7K

0.01U_0402_16V7K

CPU_SIC_SB<15>

SYSON# <30,35>

1 2

1 2

1 2

+3VALW

5

U3

U3

P

B

4

Y

A

G

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

3

@

@

2

1

1

2

R248

R248

1 2

0_0402_5%

0_0402_5%

R255

R255
680_0402_5%

680_0402_5%

R48

R48

1 2

0_0402_5%

0_0402_5%

R51

R51
680_0402_5%

680_0402_5%

R247

R247

1 2

0_0402_5%

0_0402_5%

R58

R58
680_0402_5%

680_0402_5%

CPU_DBREQ#
CPU_DBRDY CPU_TDO
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

HDT_RST#

+2.5VDDA

150U_D2_6.3VM

150U_D2_6.3VM

C444

C444
1U_0603_10V6K

1U_0603_10V6K

R31

R31

1 2

0_0402_5%

0_0402_5%

@

@

CPU_ALL_PWROK

CPU_LDTSTOP#

2007-01-17 ATI recommend

CPU_HT_RESET#

12

TP54TP54

+1.8V

R22220_0402_5% R22220_0402_5%

4

L35

L35
LQG21F4R7N00_0805

LQG21F4R7N00_0805

1 2

1

+

+

C457

C457

+1.8V

@

@

12

12

2

R226

R226
300_0402_5%

300_0402_5%

CPU_SIC

R228

R228
300_0402_5%

300_0402_5%

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

CPU_SID_SB<15>

CPUCLK0_H<13>

CPUCLK0_L<13>

HDT Connector

R24220_0402_5% R24220_0402_5%

R20220_0402_5% R20220_0402_5%

12

R21220_0402_5% R21220_0402_5%

12

12

R18220_0402_5% R18220_0402_5%

12

R23

R23

0_0402_5%

0_0402_5%

@

@

4

R19220_0402_5%

R19220_0402_5%

12

@

@

12

12

@

@

12

@

@

LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

1

C458

C458

2

1

1

C459

C459

C460

C460

0.22U_0603_10V7K

0.22U_0603_10V7K

2

2
3300P_0402_50V7K

3300P_0402_50V7K

R30

R30

1 2

0_0402_5%

0_0402_5%

@

@

place them to CPU within 1"

3900P_0402_50V7K

3900P_0402_50V7K

1 2

C446

C446

1 2

C445 3900P_0402_50V7K

C445 3900P_0402_50V7K

R16220_0402_5%

R16220_0402_5%

R17

R17
0_0402_5%

0_0402_5%

3

ATHLON Control and Debug

CPU_+VDDA

CPU1D

F8

+1.8V

12

R29

R29

@

@

300_0402_5%

300_0402_5%

R234 44.2_0402_1%R234 44.2_0402_1%

+1.2V_HT

12

R249

R249
169_0402_1%

169_0402_1%

1 2

R233 44.2_0402_1%R233 44.2_0402_1%

1 2

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0

TP15TP15

CPU_TEST18_PLLTEST1

TP19TP19

CPU_TEST17_BP3

TP23TP23

CPU_TEST16_BP2

TP21TP21

CPU_TEST15_BP1

TP13TP13

CPU_TEST14_BP0

TP44TP44

CPU_TEST12_SCANSHIFTENB

TP33TP33

THERMDC_CPU
THERMDA_CPU

CPU_RSVD_MA0_CLK3_P

TP7TP7

CPU_RSVD_MA0_CLK3_N

TP10TP10

CPU_RSVD_MA0_CLK0_P

TP9TP9

CPU_RSVD_MA0_CLK0_N

TP11TP11

CPU_RSVD_MB0_CLK3_P

TP39TP39

CPU_RSVD_MB0_CLK3_N

TP40TP40

CPU_RSVD_MB0_CLK0_P

TP6TP6

CPU_RSVD_MB0_CLK0_N

TP8TP8

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CPU_VDD_FB_H<36>
CPU_VDD_FB_L<36>

3

CPU_SIC
CPU_SID

TP2TP2
TP26TP26

CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#

VDDIOFB_H
VDDIOFB_L

CPU_DBRDY
CPU_TMS

CPU_TCK
CPU_TRST#
CPU_TDI

CPU_HTREF1
CPU_HTREF0

VDDA2

F9

VDDA1

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

AF4

SIC

AF5

SID

P6

HTREF1

R6

HTREF0

F6

VDD_FB_H

E6

VDD_FB_L

W9

VDDIO_FB_H

Y9

VDDIO_FB_L

A9

CLKIN_H

A8

CLKIN_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI
TEST25_HE9TEST29_H

E8

TEST25_L

G9

TEST19

H10

TEST18

AA7

TEST13

C2

TEST9

D7

TEST17

E7

TEST16

F7

TEST15

C7

TEST14

AC8

TEST12

C3

TEST7

AA6

TEST6

W7

THERMDC

W8

THERMDA

Y6

TEST3

AB6

TEST2

P20

RSVD0

P19

RSVD1

N20

RSVD2

N19

RSVD3

R26

RSVD4

R25

RSVD5

P22

RSVD6

R22

RSVD7

THERMDA_CPU

2200P_0402_50V7K

2200P_0402_50V7K

THERMDC_CPU

EC_SMB_CK2<26>
EC_SMB_DA2<26>

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

CPU1D

THERMTRIP_L

PROCHOT_L

VID5
VID4
VID3
VID2
VID1
VID0

CPU_PRESENT_L

PSI_L

DBREQ_L

TDO

TEST29_L

TEST24
TEST23

MISC

MISC

TEST22
TEST21
TEST20

TEST28_H

TEST28_L

TEST27
TEST26
TEST10

TEST8

RSVD8
RSVD9

RSVD10
RSVD11

RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

1

C396

C396

2

EC_SMB_CK2
EC_SMB_DA2

SMBus Address: 1001110X (b)

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

AF6
AC7

A5
C6
A6
A4
C5
B5

AC6
A3

E10

AE9

C9
C8

AE7
AD7
AE8
AB8
AF7

J7
H8
AF8
AE6
K8
C4

H16
B18

B3
C1

H6
G6
D5

R24
W18
R23
AA8
H18
H19

2

+1.8V

12

12

R227

R227

CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8

VID5
VID4
VID3
VID2
VID1
VID0

CPU_PRESENT#
CPU_PSI#

CPU_DBREQ#

CPU_TDO

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"

CPU_TEST24_SCANCLK1
CPU_TEST23_TSTUPD
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2

CPU_TEST26_BURNIN#

CPU_MA_RESET#
CPU_MB_RESET#

CPU_RSVD_VIDSTRB1
CPU_RSVD_VIDSTRB0

CPU_RSVD_VDDNB_FB_P
CPU_RSVD_VDDNB_FB_N
CPU_RSVD_CORE_TYPE

AMD NPT S1 SOCKET
Processor Socket

U19

U19

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARMZ MSOP 8P

ADM1032ARMZ MSOP 8P

2

300_0402_5%

300_0402_5%

TP50TP50

CPU_PSI# <36>

+3VS

1

C395

C395

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

2

VDD1

ALERT#

THERM#

GND

1
6
4
5

R254

R254

R221

R221

1 2

300_0402_5%

300_0402_5%

MMBT3904_NL_SOT23

MMBT3904_NL_SOT23

R44

R44

80.6_0402_1%

80.6_0402_1%

1 2

THERM#

+1.8V +3VALW

Q41

Q41

300_0402_5%

300_0402_5%
3 1

TP27TP27
TP31TP31
TP29TP29
TP32TP32
TP28TP28

TP14TP14
TP48TP48

TP47TP47
TP41TP41

TP37TP37
TP38TP38
TP22TP22

12

1

2006-10-02 unpop (ATI recommend)

R229

R229

R220

R220

@

@

1 2
2

10K_0402_5%

10K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

1 2

H_THERMTRIP# <16>

+1.8V

VID5 <36>
VID4 <36>
VID3 <36>
VID2 <36>
VID1 <36>
VID0 <36>

CPU_PROCHOT#_1.8

CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H

CPU_TEST21_SCANEN
CPU_TEST19_PLLTEST0
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST18_PLLTEST1

MMBT3904_NL_SOT23

MMBT3904_NL_SOT23

@

@

@

@

+3VALW

R219

R219

1 2

10K_0402_5%

10K_0402_5%

R218

R218

CPU_PH_G

@

@

1 2

2

Q40

Q40

CPU_PROCHOT#

31

R225 300_0402_5%R225 300_0402_5%

1 2

R224 1K_0402_5%R224 1K_0402_5%

1 2

R45 510_0402_5%R45 510_0402_5%

1 2

R230 300_0402_5%R230 300_0402_5%

1 2

R47 300_0402_5%R47 300_0402_5%

1 2

R46 510_0402_5%R46 510_0402_5%

1 2

R50 300_0402_5%R50 300_0402_5%

1 2

4.7K_0402_5%

4.7K_0402_5%

TP25TP25

+1.8V

Thermal Sensor
ADM1032

R232

R232

10K_0402_5%@

10K_0402_5%@

CPU_PROCHOT#

R231 0_0402_5%

R231 0_0402_5%

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

12

@

@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

1

of

of

of

638Friday, November 21, 2008

638Friday, November 21, 2008

638Friday, November 21, 2008

C

C

C

5

D D

C C

+1.8V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

B B

A A

+1.8V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

BOTTOMSIDE DECOUPLING

+CPU_CORE

1

proadlizer 1200uF

2

+

+

PC44

PC44
1200P_PFAF250E128MNTTE_2.5VM

1200P_PFAF250E128MNTTE_2.5VM

3 4

+1.8V

1

1

C69

C69

C101

C101

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

PLACE CLOSE TO SO-DIMM1 AS POSSIBLE

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C85

C85

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C84

C84

C60

C60

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C50

C50

C96

C96

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C67

C67

1

1

2

2

C406

C406

C409

C409

PLACE CLOSE TO SO-DIMM2 AS POSSIBLE

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C88

C88

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C62

C62

1

1

2

2

C83

C83

C109

C109

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C405

C405

0.1U_0402_16V7K~N

1

1

2

2

C402

C402

C400

C400

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C73

C73

4

+CPU_CORE +CPU_CORE

330U_D2E_2.5VM

330U_D2E_2.5VM

330U_D2E_2.5VM

330U_D2E_2.5VM

1

1

C385

C385

C386

C386

+

+

+

@

@

1

1

C398

C398

C403

C403

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C108

C108

C74

C74

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C399

C399

C99

C99

+

@

@

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C87

C87

C77

C77

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C61

C61

C68

C68

C126

C126

C55

C55

1

1

C100

C100

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

1

C48

C48

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

AC4
AD2

K10
K12
K14

M10

N11
P10

R11

U11
U13

V10

G4

J11
J13

L11
L13

M2
M6
M8

T10
T12
T14

H2
J9

K6

L4
L7
L9

N7
N9

P8
R4

R7
R9

T2
T6
T8

U7
U9

V6
V8

3

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42

Athlon 64 S1
Processor Socket

CPU1E

CPU1E

VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9

VDDIO10

Power

Power

VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16

+1.8V+CPU_CORE

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

2

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE

+1.8V

C391

C391

1

1

1

C49

C49

C423

C397

C397

2

+0.9V

1

C461

C461

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

C423

1

2

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

1

C52

C52

C447

C447

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

1

C125

C125

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

C111

C111

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

C408

C408

C401

C401

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

C448

C448

C464

C464

2

0.22U_0603_10V7K

0.22U_0603_10V7K

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

1

C404

C404

C102

C102

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

1

1

C390

C390

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

C389

C389

C90

C90

C91

C91

0.22U_0603_10V7K

0.22U_0603_10V7K

1

2

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

C435

C435

C387

C387

0.22U_0603_10V7K

0.22U_0603_10V7K
1000P_0402_50V7K~N

1000P_0402_50V7K~N

Athlon 64 S1
Processor Socket

1

2

180P_0402_50V8J~N

180P_0402_50V8J~N

C436

C436

1000P_0402_50V7K~N

1000P_0402_50V7K~N

1

C70

C70

2

1000P_0402_50V7K~N

1000P_0402_50V7K~N

CPU1F

CPU1F

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101

Ground

Ground

VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

C92

C92

C89

C89

180P_0402_50V8J~N

180P_0402_50V8J~N

C434

C434

1000P_0402_50V7K~N

1000P_0402_50V7K~N

+1.8V

@

@

C437

C437

1

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

330U_D2E_2.5VM

330U_D2E_2.5VM

330U_D2E_2.5VM

330U_D2E_2.5VM

1

1

C166

C166

+

+

+

+

2

2

2

2

C463

C463

C462

C462

1

1

180P_0402_50V8J~N

180P_0402_50V8J~N

180P_0402_50V8J~N

180P_0402_50V8J~N

2

2

1

C388

C388

1

180P_0402_50V8J~N

180P_0402_50V8J~N

180P_0402_50V8J~N

180P_0402_50V8J~N

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

1

of

of

of

738Friday, November 21, 2008

738Friday, November 21, 2008

738Friday, November 21, 2008

C

C

C

5

JDIM1

DDR_A_D0

D D

C C

DDR_CKE0_DIMMA<5>
DDR_CS2_DIMMA#<5>

DDR_A_BS#2<5>

DDR_A_BS#0<5>
DDR_A_WE#<5>

DDR_A_CAS#<5>
DDR_CS1_DIMMA#<5>

DDR_A_ODT1<5>

B B

A A

SMB_CK_DAT1<9,13,16,27>

SMB_CK_CLK1<9,13,16,27>

DDR_A_D1
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18 DDR_A_D22
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43 DDR_A_D47
DDR_A_D48

DDR_A_D49 DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
SMB_CK_DAT1

SMB_CK_CLK1

+3VS

5

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692C-A0G16

P-TWO_A5692C-A0G16

CONN@

CONN@

VSS
DQ4
DQ5

VSS
DM0
VSS
DQ6
DQ7
VSS

DQ12
DQ13

VSS
DM1
VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1

4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
DDR_A_CLK1

DDR_A_CLK#1
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6DDR_A_MA8

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_ODT0
DDR_A_MA13

DDR_CS3_DIMMA#
DDR_A_D36

DDR_A_D37
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D52

DDR_A_CLK2
DDR_A_CLK#2

DDR_A_DM6
DDR_A_D54

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R28 0_0402_5%R28 0_0402_5%

12
12

R25 0_0402_5%R25 0_0402_5%

DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>

DDR_CKE1_DIMMA <5>

DDR_A_BS#1 <5>
DDR_A_RAS# <5>
DDR_CS0_DIMMA# <5>

DDR_A_ODT0 <5>

DDR_CS3_DIMMA# <5>

DDR_A_CLK2 <5>
DDR_A_CLK#2 <5>

3

2007-01-17 Add

1

C181

C181

2

1000P_0402_50V7K~N

1000P_0402_50V7K~N

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V+DIMM_VREF+1.8V+1.8V

1

C179

C179

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

C180

C180

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

R78

R78

1K_0402_1%

1K_0402_1%

1 2

R79

R79

1K_0402_1%

1K_0402_1%

1 2

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

+1.8V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C95

C95

+0.9V

+0.9V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C75

C75

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C93

C93

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C81

C81

DDR_CKE1_DIMMA
DDR_A_MA7
DDR_A_MA14
DDR_A_MA15

DDR_A_CAS#
DDR_A_MA10
DDR_A_BS#0
DDR_A_MA1

DDR_A_MA2
DDR_A_BS#1
DDR_A_MA0
DDR_A_RAS#

DDR_A_MA9
DDR_A_MA5
DDR_A_MA3
DDR_A_MA8

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_ODT1
DDR_CS1_DIMMA#

DDR_A_WE#

DDR_CS0_DIMMA#
DDR_A_MA13
DDR_A_ODT0
DDR_CS3_DIMMA#

DDR_A_BS#2
DDR_A_MA12
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_D[0..63]<5>
DDR_A_DM[0..7]<5>

DDR_A_DQS[0..7]<5>
DDR_A_MA[0..15]<5>

DDR_A_DQS#[0..7]<5>

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

2

2

C104

C104

C103

C103

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C58

C58

C98

C98

2

1

2

1

2

C71

C71

C106

C106

1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

1

2

C94

C94

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C72

C72

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

2

C132

C132

C80

C80

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

C110

C110

+0.9V

+0.9V

330U_D2E_2.5VM

330U_D2E_2.5VM

1

C47

C47

+

+

2

@

@

1

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C51

C51

RP14

RP14

18
27
36
45

RP5

RP5

18
27
36
45

RP6

RP6

18
27
36
45

RP9

RP9

18
27
36
45

RP10

RP10

18
27
36
45

RP1

RP1

18
27
36
45

RP2

RP2

18
27
36
45

RP13

RP13

18
27
36
45

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

C

C

C

of

of

of

838Friday, November 21, 2008

838Friday, November 21, 2008

838Friday, November 21, 2008

5

4

3

2

1

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C82

C82

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C65

C65

DDR_CKE1_DIMMB
DDR_B_MA14
DDR_B_MA15
DDR_B_MA11

DDR_B_MA1
DDR_B_MA3
DDR_B_MA9
DDR_B_MA12

DDR_B_BS#0
DDR_B_MA10
DDR_B_WE#
DDR_B_MA5

DDR_B_MA2
DDR_B_BS#1
DDR_CS0_DIMMB#
DDR_B_RAS#

DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#

DDR_B_MA7
DDR_B_MA0
DDR_B_MA6
DDR_B_MA4

DDR_B_BS#2
DDR_B_MA8
DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

1

2

C59

C59

1

2

C105

C105

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

Layout Note:
Place one cap close to every 2 pullup

2

C63

C63

resistors terminated to +0.9V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

Layout Note:

1

Place one cap close to every 2 pullup
resistors terminated to +0.9V

2

C56

C56

+0.9V

RP16

RP16

18
27
36

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

45

RP11

RP11

18
27
36
45

RP7

RP7

18
27
36
45

RP8

RP8

18
27
36
45

RP4

RP4

18
27
36
45

RP3

RP3

18
27
36
45

RP12

RP12

18
27
36
45

RP15

RP15

18
27
36
45

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

1

C

C

C

of

of

of

938Friday, November 21, 2008

938Friday, November 21, 2008

938Friday, November 21, 2008

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C97

C97

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C57

C57

Deciphered Date

Deciphered Date

Deciphered Date

DDR_B_D[0..63]<5>
DDR_B_DM[0..7]<5>

DDR_B_DQS[0..7]<5>
DDR_B_MA[0..15]<5>

DDR_B_DQS#[0..7]<5>

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C64

C64

C86

C86

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C79

C79

C66

C66

2

+DIMM_VREF+1.8V+1.8V

JDIM2

DDR_B_D0

D D

C C

DDR_CKE0_DIMMB<5>
DDR_CS2_DIMMB#<5>

DDR_B_BS#2<5>

DDR_B_BS#0<5>
DDR_B_WE#<5>

DDR_B_CAS#<5>
DDR_CS1_DIMMB#<5>

DDR_B_ODT1<5>

B B

A A

SMB_CK_DAT1<8,13,16,27>

SMB_CK_CLK1<8,13,16,27>

DDR_B_D1
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
SMB_CK_DAT1

SMB_CK_CLK1

+3VS

5

JDIM2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5652C-A0G16

P-TWO_A5652C-A0G16

CONN@

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

DQ12
DQ13

VSS
DM1
VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
DDR_B_CLK1

DDR_B_CLK#1
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_ODT0
DDR_B_MA13

DDR_CS3_DIMMB#
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_CLK2
DDR_B_CLK#2

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

R26 4.7K_0402_5%R26 4.7K_0402_5%

1 2

R27 0_0402_5%R27 0_0402_5%

12

DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>

DDR_CKE1_DIMMB <5>

DDR_B_BS#1 <5>
DDR_B_RAS# <5>
DDR_CS0_DIMMB# <5>

DDR_B_ODT0 <5>

DDR_CS3_DIMMB# <5>

DDR_B_CLK2 <5>
DDR_B_CLK#2 <5>

+3VS

1

C182

C182

2

1000P_0402_50V7K~N

1000P_0402_50V7K~N

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C142

C142

+0.9V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

330U_D2E_2.5VM

330U_D2E_2.5VM

1

+

+

2

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

0.1U_0402_16V7K~N

1

1

2

2

C107

C107

C112

C112

+1.8V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C78

C78

C76

C76

+0.9V

Compal Secret Data

Compal Secret Data

Compal Secret Data

5

4

3

2

1

D D

H_CADIP[0..15]<4>
H_CADIN[0..15]<4>

H_CLKOP1
H_CLKON1

H_CLKOP0
H_CLKON0

H_CTLOP0
H_CTLON0

H_CADOP[0..15]<4>

H_CADON[0..15]<4>

U690A

U690A

R19

HT_RXCAD15P

R18

HT_RXCAD15N

R21

HT_RXCAD14P

R22

HT_RXCAD14N

U22

HT_RXCAD13P

U21

HT_RXCAD13N

U18

HT_RXCAD12P

U19

HT_RXCAD12N

W19

HT_RXCAD11P

W20

HT_RXCAD11N

AC21

HT_RXCAD10P

AB22

HT_RXCAD10N

AB20

HT_RXCAD9P

AA20

HT_RXCAD9N

AA19

HT_RXCAD8P

Y19

HT_RXCAD8N

T24

HT_RXCAD7P

R25

HT_RXCAD7N

U25

HT_RXCAD6P

U24

HT_RXCAD6N

V23

HT_RXCAD5P

U23

HT_RXCAD5N

V24

HT_RXCAD4P

V25

HT_RXCAD4N

AA25

HT_RXCAD3P

AA24

HT_RXCAD3N

AB23

HT_RXCAD2P

AA23

HT_RXCAD2N

AB24

HT_RXCAD1P

AB25

HT_RXCAD1N

AC24

HT_RXCAD0P

AC25

HT_RXCAD0N

W21

HT_RXCLK1P

W22

HT_RXCLK1N

Y24

HT_RXCLK0P

W25

HT_RXCLK0N

P24

HT_RXCTLP

P25

HT_RXCTLN

A24

HT_RXCALP

C24

HT_RXCALN

216MQA6AVA11FG FCBGA 465P

216MQA6AVA11FG FCBGA 465P

U690B

U690B

G5

GFX_RX0P

G4

GFX_RX0N

J8

GFX_RX1P

J7

GFX_RX1N

J4

GFX_RX2P

J5

GFX_RX2N

L8

GFX_RX3P

L7

GFX_RX3N

L4

GFX_RX4P

L5

GFX_RX4N

M8

GFX_RX5P

M7

GFX_RX5N

M4

GFX_RX6P

M5

C C

PCIE_LAN_C_RX_P2<22>
PCIE_LAN_C_RX_N2<22>

PCIE_WLAN_C_RX_P1<25>
PCIE_WLAN_C_RX_N1<25>

SB_RX2P<15>
SB_RX2N<15>

SB_RX3P<15>

B B

SB_RX3N<15>

SB_RX0P<15>
SB_RX0N<15>

SB_RX1P<15>
SB_RX1N<15>

PCIE_LAN_C_RX_P2
PCIE_LAN_C_RX_N2

PCIE_WLAN_C_RX_P1
PCIE_WLAN_C_RX_N1

SB_RX2P
SB_RX2N

SB_RX3P
SB_RX3N

SB_RX0P
SB_RX0N

SB_RX1P
SB_RX1N

GFX_RX6N

P8

GFX_RX7P

P7

GFX_RX7N

P4

GFX_RX8P

P5

GFX_RX8N

R4

GFX_RX9P

R5

GFX_RX9N

R7

GFX_RX10P

R8

GFX_RX10N

U4

GFX_RX11P

U5

GFX_RX11N

W4

GFX_RX12P

W5

GFX_RX12N

Y4

GFX_RX13P

Y5

GFX_RX13N

V9

GFX_RX14P

W9

GFX_RX14N

AB7

GFX_RX15P

AB6

GFX_RX15N

Y7

GPP_RX2P

AA7

GPP_RX2N

AB9

GPP_RX3P

AA9

GPP_RX3N

W11

GPP_RX0P(SB_RX2P)

W12

GPP_RX0N(SB_RX2N)

AA11

GPP_RX1P(SB_RX3P)

AB11

GPP_RX1N(SB_RX3N)

W14

SB_RX0P

W15

SB_RX0N

AB12

SB_RX1P

AA12

SB_RX1N

AA14

PCE_ISET(NC)

AB14

PCE_TXISET(NC)

216MQA6AVA11FG FCBGA 465P

216MQA6AVA11FG FCBGA 465P

PART 2 OF 5

PART 2 OF 5

PCIE GFX I/F

PCIE GFX I/F

PCIE I/F GPP

PCIE I/F GPP

GPP_TX0P(SB_TX2P)

GPP_TX0N(SB_TX2N)

GPP_TX1P(SB_TX3P)
GPP_TX1N(SB_TX3N)

PCIE I/F SB

PCIE I/F SB

PCE_PCAL(PCE_CALRP)

PCE_NCAL(PCE_CALRN)

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4

PCIE_LAN_TX_P2

AD4
AE5

AD5

PCIE_WLAN_TX_N1

AD6

SB_TX2P_C

AD8

SB_TX2N_C

AE8

SB_TX3P_C

AD7

SB_TX3N_C

AE7

SB_TX0P_C

AE9

SB_TX0N_C

AD10

SB_TX1P_C

AC8

SB_TX1N_C

AD9

R238 562_0402_1%R238 562_0402_1%

AD11

R237 2K_0402_1%R237 2K_0402_1%

AE11

C415 0.1U_0402_16V7K~NC415 0.1U_0402_16V7K~N
C416 0.1U_0402_16V7K~NC416 0.1U_0402_16V7K~N

C413 0.1U_0402_16V7K~NC413 0.1U_0402_16V7K~N
C414 0.1U_0402_16V7K~NC414 0.1U_0402_16V7K~N

C417 0.1U_0402_16V7K~NC417 0.1U_0402_16V7K~N
C418 0.1U_0402_16V7K~NC418 0.1U_0402_16V7K~N

C119 0.1U_0402_16V7K~NC119 0.1U_0402_16V7K~N
C120 0.1U_0402_16V7K~NC120 0.1U_0402_16V7K~N

1 2
1 2

C411 0.1U_0402_16V7K~NC411 0.1U_0402_16V7K~N

1 2

C412 0.1U_0402_16V7K~NC412 0.1U_0402_16V7K~N

1 2

C117 0.1U_0402_16V7K~NC117 0.1U_0402_16V7K~N

1 2

C118 0.1U_0402_16V7K~NC118 0.1U_0402_16V7K~N

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

+VDDA12_PKG2

PCIE_LAN_C_TX_P2
PCIE_LAN_C_TX_N2PCIE_LAN_TX_N2

PCIE_WLAN_C_TX_P1PCIE_WLAN_TX_P1
PCIE_WLAN_C_TX_N1

SB_TX2P
SB_TX2N

SB_TX3P
SB_TX3N

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

SB_TX2P <15>
SB_TX2N <15>

SB_TX3P <15>
SB_TX3N <15>

SB_TX0P <15>
SB_TX0N <15>

SB_TX1P <15>
SB_TX1N <15>

PCIE_LAN_C_TX_P2 <22>
PCIE_LAN_C_TX_N2 <22>

PCIE_WLAN_C_TX_P1 <25>
PCIE_WLAN_C_TX_N1 <25>

+VDDHT_PKG

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8

H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1<4>

H_CLKON1<4>

H_CLKOP0<4>

H_CLKON0<4>

H_CTLOP0<4>
H_CTLON0<4>

R282 49.9_0402_1%R282 49.9_0402_1%

1 2

R261 49.9_0402_1%R261 49.9_0402_1%

1 2

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]

H_CADON[0..15]

PART 1 OF 5

PART 1 OF 5

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

HT_TXCLK1P
HT_TXCLK1N

HT_TXCLK0P
HT_TXCLK0N

HYPER TRANSPORT I/F

HYPER TRANSPORT I/F

HT_TXCTLP
HT_TXCTLN

HT_TXCALP
HT_TXCALN

H_CADIP15

P21

H_CADIN15

P22

H_CADIP14

P18

H_CADIN14

P19

H_CADIP13

M22

H_CADIN13

M21

H_CADIP12

M18

H_CADIN12

M19

H_CADIP11

L18

H_CADIN11

L19

H_CADIP10

G22

H_CADIN10

G21

H_CADIP9

J20

H_CADIN9

J21

H_CADIP8

F21

H_CADIN8

F22

H_CADIP7

N24

H_CADIN7

N25

H_CADIP6

L25

H_CADIN6

M24

H_CADIP5

K25

H_CADIN5

K24

H_CADIP4

J23

H_CADIN4

K23

H_CADIP3

G25

H_CADIN3

H24

H_CADIP2

F25

H_CADIN2

F24

H_CADIP1

E23

H_CADIN1

F23

H_CADIP0

E24

H_CADIN0

E25

H_CLKIP1

L21

H_CLKIN1

L22

H_CLKIP0

J24

H_CLKIN0

J25

H_CTLIP0

N23

H_CTLIN0

P23

R260 100_0402_1%R260 100_0402_1%

C25

1 2

D24

H_CLKIP1 <4>
H_CLKIN1 <4>

H_CLKIP0 <4>
H_CLKIN0 <4>

H_CTLIP0 <4>

H_CTLIN0 <4>

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

1

of

of

of

10 38Friday, November 21, 2008

10 38Friday, November 21, 2008

10 38Friday, November 21, 2008

C

C

C

Reserve for EMI, close to U690

NB_REFCLK

12

R63

R63

@

@

33_0402_5%

33_0402_5%

2

C161

@ C161

@

22P_0402_50V8J

22P_0402_50V8J

1

HTREFCLK

12

R281

R281

@

@

33_0402_5%

33_0402_5%

2

C474

@ C474

@

22P_0402_50V8J

22P_0402_50V8J

1

2006-12-30 Cap follow Bowfin2.1

1 2

R57 150_0402_1%

R57 150_0402_1%

1 2

R56 150_0402_1%

R56 150_0402_1%

1 2

R55 150_0402_1%

R55 150_0402_1%

+1.8VS

+1.8VS

1 2

FBML10160808121LMT_0603

FBML10160808121LMT_0603

1 2

FBML10160808121LMT_0603

FBML10160808121LMT_0603

+1.8VS

2006-12-30 Cap follow Bowfin2.1

L36

L36

L12

L12

+1.2V_HT

15mil

+3VS

R304

R304

R273

R273

1 2

1 2

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

EDID_CLK_LCD

EDID_DAT_LCD

+3VS

12

R275

R275
1K_0402_5%

1K_0402_5%

NB_STRAP_DATA

12

R276

R276
2K_0402_5%

2K_0402_5%
@

@

POWER PLAY
HI: 1.2V
LOW : 1.0V

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

L39

L39

1 2

FBML10160808121LMT_0603

FBML10160808121LMT_0603

VGA_DDC_CLK<14>

1

C169

C169

2.2U_0603_10V6K

2.2U_0603_10V6K

2

15mil

1

C173

C173
1U_0603_10V6K

1U_0603_10V6K

2

L37

L37

1 2

FBML10160808121LMT_0603

FBML10160808121LMT_0603

EDID_CLK_LCD<14>
EDID_DAT_LCD<14>

15mil

2006-12-30 Bowfin 2.1

VGA_DDC_CLK

15mil

EDID_CLK_LCD
EDID_DAT_LCD

BMREQ#<15>

+3VS

L5

L5

1 2

FBML10160808121LMT_0603

FBML10160808121LMT_0603

+1.8VS

15mil

1

C473

C473

2.2U_0603_10V6K

2.2U_0603_10V6K

2

VGA_CRT_R<14>
VGA_CRT_G<14>

VGA_CRT_B<14>
VGA_CRT_VSYNC<14>
VGA_CRT_HSYNC<14>

R277 0_0402_5%R277 0_0402_5%

1 2

VGA_DDC_DATA<14>

R62 10K_0402_5%@ R62 10K_0402_5%@
R54 10K_0402_5%@ R54 10K_0402_5%@
R279 10K_0402_5%@ R279 10K_0402_5%@
R305 10K_0402_5%@ R305 10K_0402_5%@
R278 10K_0402_5%@ R278 10K_0402_5%@
R306 10K_0402_5%@ R306 10K_0402_5%@

R274 0_0402_5%R274 0_0402_5%

1 2

2006-12-30 bowfin 2.1

+3VS

R272

BMREQ# BMREQ#_NB

R280 715_0402_1%

R280 715_0402_1%

1 2

NB_RST#<15,19,22,25,26,27>

NB_PWRGD<26>

ALLOW_LDTSTOP<15>

NB_REFCLK<13>

NB_GFX_CLKP<13>

NB_GFX_CLKN<13>

R303 4.7K_0402_5%@R303 4.7K_0402_5%@
R302 4.7K_0402_5%

R302 4.7K_0402_5%

+3VS

10K_0402_5%

10K_0402_5%
@R272

@

1 2

1

C471

C471
15P_0402_50V8D@

15P_0402_50V8D@

2

HTREFCLK<13>

SBLINKCLK<13>

SBLINKCLK#<13>

12
12
12
12
12
12

1 2

2 1

12

12

D16

D16

RB751V_SOD323

RB751V_SOD323

@

@

+AVDD

1

C472

C472

2.2U_0603_10V6K

2.2U_0603_10V6K

2

+AVDDQ

VGA_CRT_R
VGA_CRT_G

VGA_CRT_B
VGA_CRT_VSYNC
VGA_CRT_HSYNC

VGA_DDC_CLK_NB
VGA_DDC_DATA

+NB_PLLVDD

+NB_HTPVDD

NB_RST#

NB_PWRGD
NB_LDTSTOP#

ALLOW_LDTSTOP

HTREFCLK

12

NB_REFCLK

NB_GFX_CLKP
NB_GFX_CLKN

SBLINKCLK

SBLINKCLK#

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

BMREQ#_NB

EDID_CLK_LCD_NB

NB_STRAP_DATA

15mil

1

C152

C152

2.2U_0603_10V6K

2.2U_0603_10V6K

2

R26210K_0402_5% R26210K_0402_5%

R25910K_0402_5% R25910K_0402_5%

U690C

U690C

B22
C22
G17
H17
A20
B20

A21
A22

C21
C20
D19

E19
G19

B21

A10
B10

B24
B25

C10
C11

C23
B23

B11
A11

AA15
AB15

C14

F19

C6

A5

B6
A6

C5

B5

C2

F2
E1

G1
G2

D6
D7
C8
C7

B8
A8

B2
A2
B4

B3

C3

A3

PART 3 OF 5

PART 3 OF 5

AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI

AVDDQ
AVSSQ

C
Y
COMP

RED
GREEN
BLUE
DACVSYNC
DACHSYNC

RSET
DACSCL

DACSDA
PLLVDD(PLLVDD18)

PLLVSS
HTPVDD

HTPVSS
SYSRESET#

POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP

HTTSTCLK
HTREFCLK

TVCLKIN
OSCIN

OSCOUT(PLLVDD12)
GFX_CLKP

GFX_CLKN
SB_CLKP

SB_CLKN
DFT_GPIO0

DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

BMREQ#
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N

TMDS_HPD
DDC_DATA
TESTMODE
STRP_DATA

216MQA6AVA11FG FCBGA 465P

216MQA6AVA11FG FCBGA 465P

CRT/TVOUT

CRT/TVOUT

LVTM

LVTM

LVDDR18A_1(LVDDR33_1)
LVDDR18A_2(LVDDR33_2)

PLL PWR

PLL PWR

PMCLOCKs

PMCLOCKs

DVO_D0(GPP_TX0P)
DVO_D1(GPP_TX0N)

DVO_D2(DEBUG6)

DVO_D3(GPP_RX0P)

DVO_D4(GPP_RX0N)

DVO_D5(DEBUG9)

DVO_D6(DEBUG10)
DVO_D7(GPP_TX1N)
DVO_D8(GPP_TX1P)
DVO_D9(GPP_RX1N)

DVO_D10(GPP_RX1P)

DVO

DVO

MIS.

MIS.

DVO_D11(DEBUG15)

DVO_VSYNC(DEBUG0)

DVO_DE(DEBUG2)

DVO_HSYNC(DEBUG1)
DVO_IDCKP(DEBUG14)
DVO_IDCKN(DEBUG13)

LDT_STOP#<6,15>

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

TXOUT_U0P

TXOUT_U0N

TXOUT_U1P

TXOUT_U1N

TXOUT_U2P

TXOUT_U2N

TXOUT_U3P

TXOUT_U3N

TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN

LPVDD
LPVSS

LVDDR18D_1
LVDDR18D_2

LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8

LVSSR12
LVSSR13

LVDS_DIGON

LVDS_BLON
LVDS_BLEN

LVDSL0+

B14

LVDSL0-

B15

LVDSL1+

B13

LVDSL1-

A13

LVDSL2+

H14

LVDSL2-

G14
D17
E17

LVDSU0+

A15

LVDSU0-

B16

LVDSU1+

C17

LVDSU1-

C18

LVDSU2+

B17

LVDSU2-

A17
A18
B18

LVDSLC+

E15

LVDSLC-

D15

LVDSUC+

H15

LVDSUC-

G15
D14

E14
A12

B12
C12
C13

A16
A14
D12
C19
C15
C16

F14
F15

ENVDD_NB

E12

ENABLT_NB

G12
F12

PCIE_CARD_TX_P1

AD14

PCIE_CARD_TX_N1

AD15
AE15

PCIE_CARD_C_RX_P1

AD16

PCIE_CARD_C_RX_N1

AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21

AD13

SUS_STAT#

AC13
AE13
AE17
AD17

R239

R239

470K_0402_5%

470K_0402_5%

+1.8VS

Q44

Q44

3 1

MMBT3904_NL_SOT23

MMBT3904_NL_SOT23

+LVDDR18D

+LVDDR33A

1 2

R84

R84

1 2

10K_0402_5%

10K_0402_5%

2

LVDSL0+ <14>
LVDSL0- <14>
LVDSL1+ <14>
LVDSL1- <14>
LVDSL2+ <14>
LVDSL2- <14>

LVDSU0+ <14>
LVDSU0- <14>
LVDSU1+ <14>
LVDSU1- <14>
LVDSU2+ <14>
LVDSU2- <14>

LVDSLC+ <14>
LVDSLC- <14>
LVDSUC+ <14>
LVDSUC- <14>

+LPVDD

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

GND_LVSSR

R69 0_0402_5%R69 0_0402_5%
R68 0_0402_5%R68 0_0402_5%

C419 0.1U_0402_16V7K~N C419 0.1U_0402_16V7K~N

1 2

C420 0.1U_0402_16V7K~N C420 0.1U_0402_16V7K~N

1 2

@

@

+3VS

12

C163

C163

12
12

R70

R70
10K_0402_5%

10K_0402_5%

NB_LDTSTOP#

+3VS

FBML10160808121LMT_0603

FBML10160808121LMT_0603

1

1

C171

C171

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

2

2

NB_PWRGD

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

L11

L11

12

L9

L9

1 2

FBML10160808121LMT_0603

FBML10160808121LMT_0603

1

C170

C170

2.2U_0603_10V6K

2.2U_0603_10V6K

2

L10

L10

1 2

FBML10160808121LMT_0603

FBML10160808121LMT_0603

ENVDD

ENABLT

PCIE_CARD_C_TX_P1
PCIE_CARD_C_TX_N1

+5VS

R81

R81

@

@

10K_0402_5%

10K_0402_5%

1 2
13

D

D

2

G

G

Q17

@

Q17

@

S

S

1

1

C162

C172

C172

NB_PWRGD5V#

AP2301GN 1P SOT23

AP2301GN 1P SOT23

C162

2

2

GND_LVSSR

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

+1.8VS

ENVDD <14>
ENABLT <14,26>

PCIE_CARD_C_TX_P1 <27>
PCIE_CARD_C_TX_N1 <27>

PCIE_CARD_C_RX_P1 <27>
PCIE_CARD_C_RX_N1 <27>

S

S

ENVDD_NB

ENABLT_NB

S

S

+LVDDR33A

R71

R71
0_0805_5%

0_0805_5%

15mil

+1.8VS

15mil

Q19

Q19
AP2301GN 1P SOT23

AP2301GN 1P SOT23

D

D

ENVDD

13

@

@

G

G

2

R83

R83

@

@

G

G

2

ENABLT

13

D

D

@

@

Q18

Q18

R82

R82

12

12

1K_0402_5%

1K_0402_5%

12

1K_0402_5%

1K_0402_5%

2006-09-27

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

of

of

of

11 38Friday, November 21, 2008

11 38Friday, November 21, 2008

11 38Friday, November 21, 2008

C

C

C

5

+1.2V_HT

D D

0.2A

+1.8VS

0.3A

+3VS

C C

B B

C1511U_0402_6.3V6K C1511U_0402_6.3V6K

12

C1501U_0402_6.3V6K C1501U_0402_6.3V6K

12

15mil

+1.2V_HT

L3

L3

1 2

FBMA-L11-322513-201LMA40T_1210

FBMA-L11-322513-201LMA40T_1210

NB_VDDHT12

+

+

C407150U_D2_6.3VM

C407150U_D2_6.3VM

12

@

@

C422 22U_1206_6.3V6M

C422 22U_1206_6.3V6M

12

C122 1U_0402_6.3V6K

C122 1U_0402_6.3V6K

1 2

C124 1U_0402_6.3V6K

C124 1U_0402_6.3V6K

1 2

C123 1U_0402_6.3V6K

C123 1U_0402_6.3V6K

1 2

C131 1U_0402_6.3V6K

C131 1U_0402_6.3V6K

1 2

C421 1U_0402_6.3V6K

C421 1U_0402_6.3V6K

1 2

15mil

C1751U_0402_6.3V6K C1751U_0402_6.3V6K

12

C1641U_0402_6.3V6K C1641U_0402_6.3V6K

12

+1.8VS

2006-11-13 Follow ATI reference schematic

2006-10-03 ATI recommend

FBMA-L11-322513-201LMA40T_1210

FBMA-L11-322513-201LMA40T_1210

L7

L7

1 2

C1211U_0402_6.3V6K C1211U_0402_6.3V6K

12

C1301U_0402_6.3V6K C1301U_0402_6.3V6K

12

C1291U_0402_6.3V6K C1291U_0402_6.3V6K

12

+VDDHT_PKG
+VDDA12_PKG1
+VDDA12_PKG2

C42522U_1206_6.3V6M C42522U_1206_6.3V6M

12

C1571U_0402_6.3V6K C1571U_0402_6.3V6K

12

C1461U_0402_6.3V6K C1461U_0402_6.3V6K

12

C1271U_0402_6.3V6K C1271U_0402_6.3V6K

12

C1451U_0402_6.3V6K C1451U_0402_6.3V6K

12

C1161U_0402_6.3V6K C1161U_0402_6.3V6K

12

40mil

0.5A

NB_VDDA12_HT

120mil

NB_VDDA12

NB_VDDA12_HT

4

U690D

U690D
AA17
AB17
AB19
AC18
AC19
AC20
AD21
AD22
AD23
AD24
AE23
AE24
AE25

W17

Y17

J14
J15

AB3
AB4
AC3
AD2
AE1
AE2

U7

D11
E11

AC12
AD12
AE12

E7
F7
F9

G9

D22

M1

AC11

+VDDA12_PKG1

PART 4 OF 5

PART 4 OF 5

VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15

VDD18_1
VDD18_2

VDDA18_1(VDDA12_13)
VDDA18_2(VDDA12_14)
VDDA18_3(VDDA12_15)
VDDA18_4(VDDA12_16)
VDDA18_5(VDDA12_17)
VDDA18_6(VDDA12_18)
VDDA18_7(VDDA12_19)
VDDA18_8(VDDA12_20)W7VDDC_14

VDDR3_1
VDDR3_2

VDD_DVO1(VDDR_1)
VDD_DVO2(VDDR_2)
VDD_DVO3(VDDR_3)

VDDA12(VDDPLL_1)
VDDA12(VDDPLL_2)
VSSA12(VSSPLL_1)
VSSA12(VSSPLL_2)

VDDHT_PKG
VDDA12_PKG1
VDDA12_PKG2

216MQA6AVA11FG FCBGA 465P

216MQA6AVA11FG FCBGA 465P

1

2

follow Bowfin 2.1

C456

C456

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

+1.2V_HT

12

L4

L4
FBML10160808121LMT_0603

FBML10160808121LMT_0603

NB_VDDA12

C1494.7U_0805_6.3V6K~N C1494.7U_0805_6.3V6K~N

1

2

C1481U_0402_6.3V6K C1481U_0402_6.3V6K

VDDA12_1
VDDA12_2
VDDA12_3
VDDA12_4
VDDA12_5
VDDA12_6
VDDA12_7
VDDA12_8

VDDA12_9
VDDA12_10
VDDA12_11
VDDA12_12

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

POWER

POWER

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13

VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32

1

2

3

B1
C1
D1
D2
D3
E2
E3
F4
E6
G7
L9
M9

A4
A7
A9
A19
B9
B19
C9
D9
D20
G20
H11
J11
J19
L11
L13
L15
L17
M12
M14
N11
N13
N15
P12
P14
P17
R11
R13
R15
U11
U12
U14
U15

2A

NB_VDDA12_HT

1

1

1

C1530.1U_0402_16V7K~N C1530.1U_0402_16V7K~N

C1600.1U_0402_16V7K~N C1600.1U_0402_16V7K~N

C1350.1U_0402_16V7K~N C1350.1U_0402_16V7K~N

2

2

2

300mil

1

C1340.1U_0402_16V7K~N C1340.1U_0402_16V7K~N

C1580.1U_0402_16V7K~N C1580.1U_0402_16V7K~N

2

C467 22U_1206_6.3V6MC467 22U_1206_6.3V6M

1 2

+1.2V_NBCORE

5A

1

1

1

1

C1360.1U_0402_16V7K~N C1360.1U_0402_16V7K~N

C1650.1U_0402_16V7K~N C1650.1U_0402_16V7K~N

C1590.1U_0402_16V7K~N C1590.1U_0402_16V7K~N

C1400.1U_0402_16V7K~N C1400.1U_0402_16V7K~N

2

2

2

2

A25

F11

AE18

W23

AD25

W24

AC23

AC14
AC22

AE22

AE14

AC15

AC16

D23

E9
G11
Y23
P11
R24

M15

J22

G23

J12
L12
L14
L20

L23
M11
M20
M23
M25
N12
N14

L24
P13
P20
P15
R12
R14
R20

Y25
U20

H25
Y22
D25

G24

R23

C4

T23
T25

R17
H23
M17
A23

F17

D4
M13
H12

B7

C1471U_0402_6.3V6K C1471U_0402_6.3V6K

12

C1281U_0402_6.3V6K C1281U_0402_6.3V6K

12

C1391U_0402_6.3V6K C1391U_0402_6.3V6K

12

C1151U_0402_6.3V6K C1151U_0402_6.3V6K

12

1

1

1

C14122U_1206_6.3V6M C14122U_1206_6.3V6M

C13322U_1206_6.3V6M C13322U_1206_6.3V6M

2

2

2

2

U690E

U690E

VSS1

PAR 5 OF 5

PAR 5 OF 5

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23

VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

VSS59
VSS60
VSS61
VSS62

216MQA6AVA11FG FCBGA 465P

216MQA6AVA11FG FCBGA 465P

GROUND

GROUND

VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8

VSSA9
VSSA10
VSSA11

VSSA13
VSSA15

VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22

VSSA24
VSSA25
VSSA26
VSSA27
VSSA28

VSSA30
VSSA32

VSSA33
VSSA34
VSSA35
VSSA36
VSSA93
VSSA94
VSSA95
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45
VSSA46
VSSA47
VSSA48
VSSA49
VSSA50
VSSA51

V12
V11
V14
F3
V15
A1
H1
G3
J2
H3

J6
F1

L6
M2
M6
J3
P6
T1
N3

R6
U2
T3
U3
U6

Y1
W6

AC2
Y3
Y9
Y11
Y12
Y14
AA3
R9
AD1
AC5
AC6
AC7
AD3
AC9
AC10
G6
Y15
AC4
P9
AE6
AE10
M3

1

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/7/6 2008/7/6

2007/7/6 2008/7/6

2007/7/6 2008/7/6

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011

SCHEMATICS,MB A4011
401521

401521

401521

1

of

of

of

12 38Friday, November 21, 2008

12 38Friday, November 21, 2008

12 38Friday, November 21, 2008

C

C

C