Acer LA-3733P Schematics
A
B
C
D
E
http://hobi-elektronika.net
1 1
2 2
Compal Confidential
6FKHPDWLFV'RFXPHQW
AMD Turion/Sempron + Nvidia MCP67-MV
2007-01-12
3 3
4 4
A
B
Rev:0.1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AN D CONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. TH IS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R &D
DEPARTMENT EXCE PT AS AU THOR IZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
C
Compal Secret Data
Deciphered Date
D
Compal Electronics, Inc.
Title
Cover Sheet
Size Document Number Re v
Custom
LA-3733P
Date: Sheet
136Monday, March 05, 2007
of
E
0.1
5
Compal confidential
Project Code: IBL80
File Name : LA-3733P
D D
4
http://hobi-elektronika.net
Thermal Sensor
ADM1032ARM
page 4
AMD Turion/Sempron CPU
Socket S1 638P
3
page 4,5,6,7
HT LINK
200-800MHz
2
533/667/800
DDRII DDRII-SO-DIMM X2
page 08,09
Dual Channel
1
USB conn x1
CRT & TV-out
page 19
LCD Conn. 2CH LVDS
page 18
Nvidia
MCP67-MV
836 BGA
USB 2.0 BUS
HD Audio
IDE BUS
SATA2.0 BUS
3.3V 24.576MHz/48Mhz
3.3V ATA-100
CDROM
C C
PCI-Express
port 1
Conn.
page 20
USB SUB/B
page 26page 26
HDA Codec
CX20549
page 22
S-ATA HDD
MINI Card
WLAN
page 20
B B
Power On/Off CKT / LID switch / Power OK CKT
DC/DC Interface CKT.
Power Circuit DC/DC
A A
page 28
page 29~36
LED
page 25
LAN(10/100)
RTL8201CL
page 21
RJ-45
page 21
page 25
RTC CKT.
page 16
MII
page 10,11,12,13,14,15,16,17
LPC BUS
ENE KB926
page 27
Touch Pad
page 25
EC I/O Buffer SPI ROM
page 26
Int.KBD
page 27
page 26
Conn.
page 20
Audio AMP
TI6017 CX20548
page 24
Phone Jack
page 24
AMOM
RJ-11
page 24
page 21
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDE NTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIV ISION O F R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CO NTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL EL ECTRONICS , INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Title
BLOCK DIAGRAM
Size Document Number Re v
Custom
LA-3733P
2
Date: Sheet of
236Monday, March 05, 2007
1
0.1
5
Voltage Rails
Power Plane Description
D D
C C
VIN
B+
+CPU_CORE
+0.9V 0.9V switched power rail for DDR terminator
+1.5VS
+1.2VALW ON ON ON*
+1.2VS ON OFF OFF
+1.2V_HT
+1.8V 1.8V power rail for DDR
+1.8VS 1.8V switched power rail
+3VALW
+3VS
+5VALW
+5VS
Note : ON* means t hat this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.5V switched power rail
1.2V always on power rail
1.2V switched power rail
1.2V switched power rail ON OFF OFF
2.5V switched power rail+2.5VS OFFON OFF
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
4
http://hobi-elektronika.net
S1 S3 S5
N/A N/A N/A
ON OFF
ON ON
ON OFFOFF
N/AN/AN/A
OFF
OFF
3
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
Board ID / SKU ID Table for AD channel
ON
ON
ON OFF
OFF
ON
ON
OFF
ON
ON
ON
ON OFF
OFF
ON+RTCVCC
ONRTC power
OFF
ON*
OFF
ON*
ON
Vcc 3.3V +/- 5%
100K +/- 5%Ra/Rc/Re
Board ID
Rb / Rd / Rf V min
0
1
2
3
4
5
6
7 NC
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
2
SLP_S1# SLP_S3#
HIGH HIGH HIGH
LOW
LOW
LOW LOW LOW
SLP_S5# +VALW +V +VS Clock
ONONON ON
ON
HIGHHIGH
ON
LOW
HIGH
LOWLOW
HIGH
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
ON
ON
OFF
ON
ON
OFF
V typ
AD_BID
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
ON
OFF
OFF
OFF
V
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
1
LOW
OFF
OFF
OFF
max
External PCI Devices
Devic e IDSE L# REQ#/GNT# Int errupts
B B
EC SM Bus1 address
Device
Smart Battery
Address Address
EC SM Bus2 address
Device
ADM1032
1001 100X b0001 011X b
BTO Option Table
BTO Item BOM Structure
45@DI P CAP & RTC
MCP67 SM Bus address
Device Address
DDR DIMM0
A A
DDR DIMM2
MINI CARD
5
1001 000Xb
1001 001Xb
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDE NTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIV ISION O F R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CO NTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL EL ECTRONICS , INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Title
TABLE OF CONTENTS
Size Document Number Re v
Custom
LA-3733P
2
Date: Sheet of
336Monday, March 05, 2007
1
0.1
5
4
http://hobi-elektronika.net
3
2
1
PROCESSOR HYPERTRANSPORT INTERFACE
D D
H_CADIP1510 H_CADOP15 10
H_CADIN1510
H_CADIP1410
H_CADIN1410
H_CADIP1310
H_CADIN1310
H_CADIP1210
H_CADIN1210
H_CADIP1110
H_CADIN1110
H_CADIP1010
H_CADIN1010
H_CADIP910
H_CADIN910
H_CADIP810
C C
B B
H_CADIN810
H_CADIP710
H_CADIN710
H_CADIP610
H_CADIN610
H_CADIP510
H_CADIN510
H_CADIP410
H_CADIN410
H_CADIP310
H_CADIN310
H_CADIP210
H_CADIN210
H_CADIP110
H_CADIN110
H_CADIP010
H_CADIN010
+1.2V_HT
R2 51_0402_1%
1 2
R3 51_0402_1%
1 2
+1.2V_HT
1
C6
2
4.7U_0 805_10V4Z
H_CLKIP110
H_CLKIN110
H_CLKIP010
H_CLKIN010
H_CTLIP010
H_CTLIN010
4.7U_0 805_10V4Z
1
2
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECT ED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.2V_HT
JP1A
D4
VLDT_A3
D3
VLDT_A2
D2
VLDT_A1
D1
VLDT_A0
N5
L0_CADIN_H15
P5
L0_CADIN_L15
M3
L0_CADIN_H14
M4
L0_CADIN_L14
L5
L0_CADIN_H13
M5
L0_CADIN_L13
K3
L0_CADIN_H12
K4
L0_CADIN_L12
H3
L0_CADIN_H11
H4
L0_CADIN_L11
G5
L0_CADIN_H10
H5
L0_CADIN_L10
F3
L0_CADIN_H9
F4
L0_CADIN_L9
E5
L0_CADIN_H8
F5
L0_CADIN_L8
N3
L0_CADIN_H7
N2
L0_CADIN_L7
L1
L0_CADIN_H6
M1
L0_CADIN_L6
L3
L0_CADIN_H5
L2
L0_CADIN_L5
J1
L0_CADIN_H4
K1
L0_CADIN_L4
G1
L0_CADIN_H3
H1
L0_CADIN_L3
G3
L0_CADIN_H2
G2
L0_CADIN_L2
E1
L0_CADIN_H1
F1
L0_CADIN_L1
E3
L0_CADIN_H0
E2
L0_CADIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
FOX_PZ63823-284S-41F
0.22U_ 0402_10V4Z
1
C9
2
180P_0402_50V8J
1
2
C10
Athlon 64 S1
Processor Socket
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
bdf
bdf
bdf
bdf
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
IUU!Joufsg
IUU!Joufsg
L0_CLKOUT_H1
IUU!Joufsg
IUU!Joufsg
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
180P_0402_50V8J
1
C11
2
C7
H_CADIP15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0
H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0
H_CTLIP1
H_CTLIN1
H_CTLIP0
H_CTLIN0
1
C8
2
0.22U_ 0402_10V4Z
C1
AE5
VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0
1 2
4.7U_0 805_10V4Z
AE4
AE3
AE2
H_CADOP15
T4
H_CADON15H_CADIN15
T3
H_CADOP14
V5
H_CADON14
U5
H_CADOP13
V4
H_CADON13
V3
H_CADOP12
Y5
H_CADON12
W5
H_CADOP11
AB5
H_CADON11
AA5
H_CADOP10
AB4
H_CADON10
AB3
H_CADOP9
AD5
H_CADON9
AC5
H_CADOP8
AD4
H_CADON8
AD3
H_CADOP7
T1
H_CADON7
R1
H_CADOP6
U2
H_CADON6
U3
H_CADOP5
V1
H_CADON5
U1
H_CADOP4
W2
H_CADON4
W3
H_CADOP3
AA2
H_CADON3
AA3
H_CADOP2
AB1
H_CADON2
AA1
H_CADOP1
AC2
H_CADON1
AC3
H_CADOP0
AD1
H_CADON0
AC1
H_CLKOP1
Y4
H_CLKON1
Y3
H_CLKOP0
Y1
H_CLKON0
W1
T5
R5
H_CTLOP0
R2
H_CTLON0
R3
LAYOUT: Place bypass cap on topside of board
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECT LY
TO DOWNSTREAM HT DEVICE, BUT CONNECTE D INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS
H_CADON15 10
H_CADOP14 10
H_CADON14 10
H_CADOP13 10
H_CADON13 10
H_CADOP12 10
H_CADON12 10
H_CADOP11 10
H_CADON11 10
H_CADOP10 10
H_CADON10 10
H_CADOP9 10
H_CADON9 10
H_CADOP8 10
H_CADON8 10
H_CADOP7 10
H_CADON7 10
H_CADOP6 10
H_CADON6 10
H_CADOP5 10
H_CADON5 10
H_CADOP4 10
H_CADON4 10
H_CADOP3 10
H_CADON3 10
H_CADOP2 10
H_CADON2 10
H_CADOP1 10
H_CADON1 10
H_CADOP0 10
H_CADON0 10
H_CLKOP1 10
H_CLKON1 10
H_CLKOP0 10
H_CLKON0 10
H_CTLOP0 10
H_CTLON0 10
Thermal Sensor ADM1032ARMZ
C2
0.1U_0 402_16V4Z
H_THERMDA
H_THERMDC
+3VS
R1
1 2
10K_0402_5%
2
C3
2200P_0402_50V7K
1
H_THERMDA6
H_THERMDC6
PWM Fan Control circuit
+3VS
5
U2
1
THERM#
INB
2
INA
P
4
O
G
TC7SH00FU_SSOP5
3
3
FAN_PWM27
G
+3VS
THERM#
2
1
2
1
+5VS
2 1
6
S
4 5
U1
1
VDD
2
D+
3
D-
THERM#4GND
ADM1032ARMZ-2REEL_MSOP8
Address:100_1100
1
D1
RB751V_SOD323
2
D
Q1
SI3456BDV-T1-E3_TSOP6
CLOSE CPU,
CPU_THERMDA&CPU_THERMDC PL ACE
CLOSE TO PROCESSOR WITHIN 1" INCH
SMB_EC_CK2
8
SCLK
SMB_EC_DA2
7
SDATA
6
ALERT#
5
1
C5
0.1U_0 402_16V4Z
2
12
ZD1
@
RLZ5.1B_LL34
SMB_EC_DA2
SMB_EC_CK2
SMB_EC_DA227
SMB_EC_CK227
SP02000D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P
C4
4.7U_0 805_10V4Z
FAN
JP2
1
1
2
2
3
G1
4
G2
ACES_85204-02001
CONN@
A1
A26
ZZZ1
A A
PCB
LA-3733P
DA600005I00
5
AF1
Athlon 64 S1g1
uPGA638
Top View
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDE NTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIV ISION O F R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CO NTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL EL ECTRONICS , INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Title
AMD CPU HT I/F
Size Document Number Re v
Custom
LA-3733P
2
Date: Sheet of
436Monday, March 05, 2007
1
0.1
A
B
C
D
E
Processor DDR2 Memory Interface
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD _VTT_SUS P OWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.8V
4 4
12
R4
39.2_0402_1%~D
R5
12
39.2_0402_1%~D
DDR_CS3_DIMMA#8
DDR_CS2_DIMMA#8
DDR_CS1_DIMMA#8
DDR_CS0_DIMMA#8
DDR_CS3_DIMMB#9
DDR_CS2_DIMMB#9
PLACE THEM CLOSE TO
CPU WITHIN 1"
3 3
2 2
DDR_CS1_DIMMB#9
DDR_CS0_DIMMB#9
DDR_CKE1_DIMMB9
DDR_CKE0_DIMMB9
DDR_CKE1_DIMMA8
DDR_CKE0_DIMMA8
DDR_A_MA[15..0]8
DDR_A_BS#28
DDR_A_BS#18
DDR_A_BS#08
DDR_A_RAS#8
DDR_A_CAS#8
DDR_A_WE#8
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1
PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INC H
1K_0402_1%
1K_0402_1%
R6
R7
10:8:10:8:10
1
2
1
2
+1.8V
12
12
+0.9VREF_CPU
TP1PAD
M_ZN
M_ZP
DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#
DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0
DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
C12
1.5P_0402_50V8C
C14
1.5P_0402_50V8C
VTT_SENSE
JP1B
W17
M_VREF
Y10
VTT_SENSE
AE10
M_ZN
AF10
M_ZP
V19
MA0_CS_L3
J22
MA0_CS_L2
V22
MA0_CS_L1
T19
MA0_CS_L0
Y26
MB0_CS_L3
J24
MB0_CS_L2
W24
MB0_CS_L1
U23
MB0_CS_L0
H26
MB_CKE1
J23
MB_CKE0
J20
MA_CKE1
J21
MA_CKE0
K19
MA_ADD15
K20
MA_ADD14
V24
MA_ADD13
K24
MA_ADD12
L20
MA_ADD11
R19
MA_ADD10
L19
MA_ADD9
L22
MA_ADD8
L21
MA_ADD7
M19
MA_ADD6
M20
MA_ADD5
M24
MA_ADD4
M22
MA_ADD3
N22
MA_ADD2
N21
MA_ADD1
R21
MA_ADD0
K22
MA_BANK2
R20
MA_BANK1
T22
MA_BANK0
T20
MA_RAS_L
U20
MA_CAS_L
U21
MA_WE_L
FOX_PZ63823-284S-41F
Athlon 64 S1
Processor
Socket
CPU_VREF_REF
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
!Dne0Dusm00Dml
!Dne0Dusm00Dml
!Dne0Dusm00Dml
!Dne0Dusm00Dml
EESJJ
EESJJ
EESJJ
EESJJ
C16
0.1U_0402_16V4Z
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_BANK2
MB_BANK1
MB_BANK0
MB_RAS_L
MB_CAS_L
MB_WE_L
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INC H
1
2
http://hobi-elektronika.net
+0.9V
D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10
DDR_A_CLK2
Y16
AA16
E16
F16
AF18
AF17
A17
A18
W23
W26
V20
U19
J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24
K26
T26
U26
U24
V26
U22
1
C17
2
1000P_0402_50V7K
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0
DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0
DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
1
C13
1.5P_0402_50V8C
2
1
C15
1.5P_0402_50V8C
2
+0.9VREF_CPU
DDR_A_CLK2 8
DDR_A_CLK#2 8
DDR_A_CLK1 8
DDR_A_CLK#1 8
DDR_B_CLK2 9
DDR_B_CLK#2 9
DDR_B_CLK1 9
DDR_B_CLK#1 9
DDR_B_ODT1 9
DDR_B_ODT0 9
DDR_A_ODT1 8
DDR_A_ODT0 8
DDR_B_MA[15..0] 9
DDR_B_BS#2 9
DDR_B_BS#1 9
DDR_B_BS#0 9
DDR_B_RAS# 9
DDR_B_CAS# 9
DDR_B_WE# 9
DDR_B_D[63..0]9
To reverse SODIMM socket
DDR_B_DM[7..0]9 DDR_A_DM[7..0] 8
DDR_B_DQS79
DDR_B_DQS#79
DDR_B_DQS69
DDR_B_DQS#69
DDR_B_DQS59
DDR_B_DQS#59
DDR_B_DQS49
DDR_B_DQS#49
DDR_B_DQS39
DDR_B_DQS#39
DDR_B_DQS29
DDR_B_DQS#29
DDR_B_DQS19
DDR_B_DQS#19
DDR_B_DQS09
DDR_B_DQS#09
DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0
DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0
JP1C
AD11
MB_DATA63
AF11
MB_DATA62
AF14
MB_DATA61
AE14
MB_DATA60
Y11
MB_DATA59
AB11
MB_DATA58
AC12
MB_DATA57
AF13
MB_DATA56
AF15
MB_DATA55
AF16
MB_DATA54
AC18
MB_DATA53
AF19
MB_DATA52
AD14
MB_DATA51
AC14
MB_DATA50
AE18
MB_DATA49
AD18
MB_DATA48
AD20
MB_DATA47
AC20
MB_DATA46
AF23
MB_DATA45
AF24
MB_DATA44
AF20
MB_DATA43
AE20
MB_DATA42
AD22
MB_DATA41
AC22
MB_DATA40
AE25
MB_DATA39
AD26
MB_DATA38
AA25
MB_DATA37
AA26
MB_DATA36
AE24
MB_DATA35
AD24
MB_DATA34
AA23
MB_DATA33
AA24
MB_DATA32
G24
MB_DATA31
G23
MB_DATA30
D26
MB_DATA29
C26
MB_DATA28
G26
MB_DATA27
G25
MB_DATA26
E24
MB_DATA25
E23
MB_DATA24
C24
MB_DATA23
B24
MB_DATA22
C20
MB_DATA21
B20
MB_DATA20
C25
MB_DATA19
D24
MB_DATA18
A21
MB_DATA17
D20
MB_DATA16
D18
MB_DATA15
C18
MB_DATA14
D14
MB_DATA13
C14
MB_DATA12
A20
MB_DATA11
A19
MB_DATA10
A16
MB_DATA9
A15
MB_DATA8
A13
MB_DATA7
D12
MB_DATA6
E11
MB_DATA5
G11
MB_DATA4
B14
MB_DATA3
A14
MB_DATA2
A11
MB_DATA1
C11
MB_DATA0
AD12
MB_DM7
AC16
MB_DM6
AE22
MB_DM5
AB26
MB_DM4
E25
MB_DM3
A22
MB_DM2
B16
MB_DM1
A12
MB_DM0
AF12
MB_DQS_H7
AE12
MB_DQS_L7
AE16
MB_DQS_H6
AD16
MB_DQS_L6
AF21
MB_DQS_H5
AF22
MB_DQS_L5
AC25
MB_DQS_H4
AC26
MB_DQS_L4
F26
MB_DQS_H3
E26
MB_DQS_L3
A24
MB_DQS_H2
A23
MB_DQS_L2
D16
MB_DQS_H1
C16
MB_DQS_L1
C12
MB_DQS_H0
B12
MB_DQS_L0
FOX_PZ63823-284S-41F
ESJJ!Ebub
ESJJ!Ebub
ESJJ!Ebub
ESJJ!Ebub
E
E
E
E
Athlon 64 S1
Processor Socket
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12
Y13
AB16
Y19
AC24
F24
E19
C15
E12
W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_D[63..0] 8
DDR_A_DQS7 8
DDR_A_DQS#7 8
DDR_A_DQS6 8
DDR_A_DQS#6 8
DDR_A_DQS5 8
DDR_A_DQS#5 8
DDR_A_DQS4 8
DDR_A_DQS#4 8
DDR_A_DQS3 8
DDR_A_DQS#3 8
DDR_A_DQS2 8
DDR_A_DQS#2 8
DDR_A_DQS1 8
DDR_A_DQS#1 8
DDR_A_DQS0 8
DDR_A_DQS#0 8
To normal SODIMM socket
VDD_VREF_SUS_C PU
1 1
A
LAYOUT:PLACE CLOSE TO C PU
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COMPAL E LECTRON ICS, IN C. NEI THER THI S SHEE T NOR THE I NFORMAT ION IT CO NTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal Secret Data
2007/01/07 2008/01/12
Deciphered Date
D
Title
AMD CPU DDRII MEMORY I/ F
Size Doc ument Nu mber Re v
Custom
LA-3733P
Date: Sheet
E
of
536Monda y, March 05, 2007
0.1
5
+2.5VS
1
C18
22U_0805_6.3V6M
2
D D
C C
HTCPU_PWRGD10
HTCPU_STO P#10
HTCPU_RST#10
1 2
FCM2012C-800_0805
L1
1
C19
2
4.7U_0805_10V4Z
+1.8V
12
R17
300_0402_5%
+1.8V
12
R20
300_0402_5%
+1.8V
12
R22
300_0402_5%
1
C20
2
0.22U_0603_16V7K
1 2
R19 0_0402_5%
1 2
R21 0_0402_5%
1 2
R23 0_0402_5%
4
http://hobi-elektronika.net
W=50mils
1
C21
3300P_0402_50V7K
2
CPU_SIC15
CPU_SID15
place them to CPU within 1"
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
+1.8V
+1.2V_HT
R10 300_0402_5%
1 2
R11 300_0402_5%
1 2
R12 0_0402_5%
1 2
R13 0_0402_5%
1 2
R14 44.2_0603_1%
1 2
R15 44.2_0603_1%
1 2
CPUCLK10
CPUCLK#10
3
ATHLON Control and Debug
LAYOUT: ROUTE VDDA TRACE APPR OX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
+2.5VS_VDDA
CPU_SIC_R
CPU_SID_R
CPU_ HTREF1
CPU_ HTREF0 VID0
5:10
CPU_VCC_SENSE34
CPU_VSS_SENSE34
C22
1 2
12
3900P_0402_50V7K
R16
169_0402_1%
1 2
H_THERMDC4
H_THERMDA4
R24 300_0402_5%
R25 1K_0402_5%
R26 510_0402_5%
R27 300_0402_5%
R28 510_0402_5%
R29 300_0402_5%
R30 300_0402_5%
C23
3900P_0402_50V7K
CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST21_SCANEN
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
TP2PAD
TP3PAD
CPU_ CLKIN_ SC_P
CPU_CLKIN_SC_N
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
H_THERMDC
H_THERMDA
10:10
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_VCC_SENSE
CPU_VSS_SENSE
CPU_DB RDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
TP4
TP6
TP8
TP10
TP11
+1.8V
JP1D
F8
VDDA2
F9
VDDA1
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
AF4
SIC
AF5
SID
P6
HTREF1
R6
HTREF0
F6
VDD_FB_H
E6
VDD_FB_L
W9
VDDIO_FB_H
Y9
VDDIO_FB_L
A9
CLKIN_H
A8
CLKIN_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
TEST25_HE9TEST29_H
E8
TEST25_L
G9
TEST19
H10
TEST18
AA7
TEST13
C2
TEST9
D7
TEST17
E7
TEST16
F7
TEST15
C7
TEST14
AC8
TEST12
C3
TEST7
AA6
TEST6
W7
THERMDC
W8
THERMDA
Y6
TEST3
AB6
TEST2
P20
RSVD0
P19
RSVD1
N20
RSVD2
N19
RSVD3
R26
RSVD4
R25
RSVD5
P22
RSVD6
R22
RSVD7
FOX_PZ63823-284S-41F
2
THERMTRIP_L
PROCHOT_L
CPU_PRESENT_L
TD
TD
TD
TD
NJ
NJ
NJ
NJ
AMD NPT S1 SOCKET
Processor Socket
DBREQ_L
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
TEST8
AF6
AC7
A5
VID5
C6
VID4
A6
VID3
A4
VID2
C5
VID1
B5
VID0
AC6
A3
PSI_L
E10
AE9
TDO
C9
C8
AE7
AD7
AE8
AB8
AF7
J7
H8
AF8
AE6
K8
C4
H16
B18
B3
C1
H6
G6
D5
R24
W18
R23
AA8
H18
H19
R8
300_0402_5%
H_THERMTRIP_S#
CPU_PROCHOT#_1.8
VID5
VID4
VID3
VID2
VID1
CPU_PRESENT#
PSI#
CPU_DBREQ#
CPU_TDO
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
5:5:5
TP5
TP7
TP9
CPU_TEST21_SCANEN
TP12
CPU_TEST26_BURNIN#
+1.8V
12
PSI# 34
1 2
80.6_0402_1%
R18
12
R9
300_0402_5%
1
VID5 34
VID4 34
VID3 34
VID2 34
VID1 34
VID0 34
ROUTE AS 80 Ohm DIFFERENTIAL P AIR
PLACE IT CLOSE TO CPU WI THIN 1"
HDT Connector
B B
CPU_DBREQ#
CPU_DB RDY
CPU_TCK
CPU_TDI
CPU_TRST#
CPU_TDO
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ON LY.
A A
+1.8V
JP3
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423
26
SAMTEC_ASP-68200-07
@
R35
220_0402_5%@
3V_LDT_RST# CPU_HT_RESET#
+3VALW+3VS
12
2
G
1 3
D
S
Q4
2N7002_SOT23@
PROCHOT#10
+1.8V +1.8V +3VALW +3VALW
12
@
Q2
3 1
MMBT3904_SOT23
1 2
R36 0_0402_5%
CPU_PROCHOT#_1.8
12
2
10K_0402_5%
R31
300_0402_5%
H_THERMTRIP_S# H_THERMTRIP#CPU_TMS
1 2
R39 0_0402_5%
R32
1K_0402_5%
@
R37
+1.8V +3VS
12
CPU_PH_G
B
2
Q5
E
3 1
C
MMBT3904_SOT23
12
R34
10K_0402_5%
@
12
12
2
3 1
R38
4.7K_0402_5%
R33
1K_0402_5%@
Q3
MMBT3904_SOT23
@
EC_THERM# 15,27
MAINPW ON 31,35
H_THERMTRIP# 10
Connect to MCP67
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COMPAL E LECTRON ICS, IN C. NEI THER THI S SHEE T NOR THE I NFORMAT ION IT CO NTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
2007/01/07 2008/01/12
Deciphered Date
2
Title
AMD CPU CTRL & DEBUG
Size Doc ument Nu mber Re v
C
LA-3733P
Date: Sheet
1
of
636Monda y, March 05, 2007
0.1
5
4
3
2
1
http://hobi-elektronika.net
D D
PROCESSOR POWER AND GROUND
JP1F
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ63823-284S-41F
fs
fs
fs
fs
VDDIO10
VDDIO11
Qpx
Qpx
Qpx
Qpx
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
+CPU_CORE+CPU_CORE
V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16
+1.8V
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
JP1E
AC4
VDD1
AD2
VDD2
G4
VDD3
H2
VDD4
J9
VDD5
J11
VDD6
J13
VDD7
K6
VDD8
K10
VDD9
K12
VDD10
K14
VDD11
L4
VDD12
L7
VDD13
L9
VDD14
L11
VDD15
L13
VDD16
M2
C C
B B
VDD17
M6
VDD18
M8
VDD19
M10
VDD20
N7
VDD21
N9
VDD22
N11
VDD23
P8
VDD24
P10
VDD25
R4
VDD26
R7
VDD27
R9
VDD28
R11
VDD29
T2
VDD30
T6
VDD31
T8
VDD32
T10
VDD33
T12
VDD34
T14
VDD35
U7
VDD36
U9
VDD37
U11
VDD38
U13
VDD39
V6
VDD40
V8
VDD41
V10
VDD42
FOX_PZ63823-284S-41F
Athlon 64 S1
Processor Socket
Athlon 64 S1
Processor Socket
voe
voe
voe
voe
Hsp
Hsp
Hsp
Hsp
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
+CPU_CORE
1
2
+CPU_CORE
1
2
C29
10U_0805_10V6M
+
C24
330U_4V_M
C30
10U_0805_10V6M
1
2
0125 Cost down $0.155
1
+
C25
330U_4V_M
2
C32
10U_0805_10V6M
1
1
2
2
C31
10U_0805_10V6M
1
+
C26
330U_4V_M
2
1
2
C33
10U_0805_10V6M
C34
10U_0805_10V6M
1
2
1
+
2
1
2
C35
10U_0805_10V6M
C27
330U_4V_M
CPU SOCKET S1 DECOUPLING
+CPU_CORE
1
2
22U_0805_6.3V
+CPU_CORE
1
2
0.22U_0603_10V7K
C36
0.22U_0603_10V7K
C45
22U_0805_6.3V
1
2
1
2
1
C38
C37
2
22U_0805_6.3V
180P_0402_50V8J
1
C46
C47
2
0.01U_0402_16V7K
22U_0805_6.3V
1
2
1
2
C39
22U_0805_6.3V
C48
22U_0805_6.3V
1
C40
2
1
C49
180P_0402_50V8J
2
22U_0805_6.3V
1
1
C41
2
22U_0805_6.3V
1
1
C43
C42
2
2
2
+1.8V
10U_0805_10V6M
1
C50
2
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8V
1
C54
4.7U_0805_10V4Z
2
1
C61
0.22U_0402_10V4Z
2
+0.9V
1
C66
4.7U_0805_10V4Z
2
1
C55
4.7U_0805_10V4Z
2
1
C62
0.01U_0402_16V7K
2
1
C67
4.7U_0805_10V4Z
2
1
C56
4.7U_0805_10V4Z
2
1
C63
0.01U_0402_16V7K
2
1
C68
4.7U_0805_10V4Z
2
1
C57
4.7U_0805_10V4Z
2
1
2
1
C69
4.7U_0805_10V4Z
2
1
2
C64
180P_0402_50V8J
1
2
C58
0.22U_0402_10V4Z
1
C65
180P_0402_50V8J
2
C70
0.22U_0402_10V4Z
+CPU_CORE
C44
22U_0805_6.3V
1
C51
2
10U_0805_10V6M
1
C59
0.22U_0402_10V4Z
2
1
C71
0.22U_0402_10V4Z
2
1
+
C28
820U_E9_2.5V_M_R7
45@
2
0.22U_0402_10V4Z
1
C52
2
1
C53
0.22U_0402_10V4Z
2
1
C60
0.22U_0402_10V4Z
2
1
C72
0.22U_0402_10V4Z
2
1
C73
0.22U_0402_10V4Z
2
1
C76
1000P_0402_50V7K
2
Compal Secret Data
Deciphered Date
2
1
C77
1000P_0402_50V7K
2
1
1
2
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COMPAL E LECTRON ICS, IN C. NEI THER THI S SHEE T NOR THE I NFORMAT ION IT CO NTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C75
C74
1000P_0402_50V7K
1000P_0402_50V7K
2
2007/01/07 2008/01/12
1
C78
180P_0402_50V8J
2
1
C79
180P_0402_50V8J
2
Title
Size Doc ument Nu mber Re v
C
Date: Sheet
1
1
C80
180P_0402_50V8J
2
2
AMD CPU PW R & GND
LA-3733P
C81
180P_0402_50V8J
1
0.1
of
736Monda y, March 05, 2007
5
http://hobi-elektronika.net
DDR_CKE0_DIMMA5
DDR_CS2_DIMMA#5
DDR_A_BS#25
DDR_A_BS#05
DDR_A_WE#5
DDR_A_CAS#5
DDR_CS1_DIMMA#5
DDR_A_ODT15
MEM_SMBD ATA9,15
MEM_SMBCLK9,15
DDR_A_D[0..63]
DDR _A_DM[0..7]
DDR _A_DQS[0..7]
DDR_A_MA[0..15]
DDR _A_DQS#[0..7]
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18 DDR_A_D22
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43 DDR_A_D47
DDR_A_D48
DDR_A_D49 DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51 DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
MEM_SMBD ATA
MEM_SMBCLK
+3VS
1
C111
0.1U_0402_16V4Z
2
5
JP4
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_AS0A 426-M2RN-7F
<BOM Structure>
DIMM1 REV H:4mm (BOT)
DDR_A_D[0..63]5
DDR_A_DM[0..7]5
DDR_A_DQS[0..7]5
DDR_A_MA[0..15]5
DDR_A_DQS#[0..7]5
D D
C C
B B
A A
DQS3#
NC/CKE1
NC/A15
NC/A14
NC/A13
DQS5#
DQS7#
4
2
VSS
4
DQ4
6
DQ5
8
VSS
10
DM0
12
VSS
14
DQ6
16
DQ7
18
VSS
20
DQ12
22
DQ13
24
VSS
26
DM1
28
VSS
30
CK0
32
CK0#
34
VSS
36
DQ14
38
DQ15
40
VSS
42
VSS
44
DQ20
46
DQ21
48
VSS
50
NC
52
DM2
54
VSS
56
DQ22
58
DQ23
60
VSS
62
DQ28
64
DQ29
66
VSS
68
70
DQS3
72
VSS
74
DQ30
76
DQ31
78
VSS
80
82
VDD
84
86
88
VDD
90
A11
92
A7
94
A6
96
VDD
98
A4
100
A2
102
A0
104
VDD
106
BA1
108
RAS#
110
S0#
112
VDD
114
ODT0
116
118
VDD
120
NC
122
VSS
124
DQ36
126
DQ37
128
VSS
130
DM4
132
VSS
134
DQ38
136
DQ39
138
VSS
140
DQ44
142
DQ45
144
VSS
146
148
DQS5
150
VSS
152
DQ46
154
DQ47
156
VSS
158
DQ52
160
DQ53
162
VSS
164
CK1
166
CK1#
168
VSS
170
DM6
172
VSS
174
DQ54
176
DQ55
178
VSS
180
DQ60
182
DQ61
184
VSS
186
188
DQS7
190
VSS
192
DQ62
194
DQ63
196
VSS
198
SAO
200
SA1
4
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6DDR_A_MA8
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_MA13
DDR_CS3_DIMMA#
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D52
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_DM6
DDR_A_D54
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R42 10K_0402_5%
1 2
R43 10K_0402_5%
1 2
DDR_A_CLK1 5
DDR_A_CLK#1 5
DDR_CKE1_DIMMA 5
DDR_A_BS#1 5
DDR_A_RAS# 5
DDR_CS0_DIMMA# 5
DDR_A_ODT0 5
DDR_CS3_DIMMA# 5
DDR_A_CLK2 5
DDR_A_CLK#2 5
3
+1.8V+DIMM_VREF+1.8V+1.8V
C83 0.1U_0402_16V4Z
C82 4.7U_0805_10V4Z
1
2
12
R40
1
1K_0402_1%
2
12
R41
1K_0402_1%
2
+1.8V
0.1U_0402_16V4Z
1
2
C84
+0.9V
+0.9V
0.1U_0402_16V4Z
1
2
C93
+1.8V
+0.9V
DDR_A_MA8
DDR_A_MA9
DDR_A_MA3
DDR_A_MA5
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_MA12
DDR_A_BS#2
DDR_A_BS#1
DDR_A_MA0
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_ODT0
DDR_A_MA13
DDR_CS3_DIMMA#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_MA15
DDR_A_MA14
DDR_CKE1_DIMMA
DDR_A_MA11
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
RP1
18
27
36
45
47_0804_8P4R_5%
RP2
18
27
36
45
47_0804_8P4R_5%
RP3
45
36
27
18
47_0804_8P4R_5%
RP4
45
36
27
18
47_0804_8P4R_5%
RP5
45
36
27
18
47_0804_8P4R_5%
RP6
18
27
36
45
47_0804_8P4R_5%
RP7
18
27
36
45
47_0804_8P4R_5%
RP8
45
36
27
18
47_0804_8P4R_5%
2007/01/07 2008/01/12
Compal Secret Data
Deciphered D ate
220U_D2_4VM_R15
1
C101
+
2
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C85
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C94
2.2U_0805_16V4Z
C102
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C86
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
0.1U_0402_16V4Z
1
2
C95
2.2U_0805_16V4Z
C103
1
2
0.1U_0402_16V4Z
1
1
2
C87
1
2
C96
2.2U_0805_16V4Z
1
2
2
C88
C89
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C98
C97
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C104
C105
1
1
2
2
Title
DDR2 SO-DIMM I
Size Document Number Rev
Custom
LA-3733P
Date: Sheet
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C90
C91
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
C99
0.1U_0402_16V4Z
C106
C107
1
1
2
2
C92
1
+
150U_D2_6.3VM
2
2
C100
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C108
C109
1
2
1
C110
1
1
2
2
of
836Monday, March 05, 2007
0.1
5
http://hobi-elektronika.net
DDR_B_D[0..63]5
DDR_B_DM[0..7]5
DDR_B_DQS[0..7]5
DDR_B_MA[0..15]5
DDR_B_DQS#[0..7]5
D D
C C
B B
A A
DDR_B_D[0..63]
DDR _B_DM[0..7]
DDR _B_DQS[0..7]
DDR_B_MA[0..15]
DDR _B_DQS#[0..7]
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18 DDR_B_D22
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB5
DDR_CS2_DIMMB#5
DDR_B_BS#25
DDR_B_BS#05
DDR_B_WE#5
DDR_B_CAS#5
DDR_CS1_DIMMB#5
DDR_B_ODT15
MEM_SMBD ATA8,15
MEM_SMBCLK8,15
DDR_CKE0_DIMMB
DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43 DDR_B_D47
DDR_B_D48
DDR_B_D49 DDR_B_D53
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51 DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
MEM_SMBD ATA
MEM_SMBCLK
+3VS
1
C139
0.1U_0402_16V4Z
2
5
JP5
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_AS0A 426-MARG-7F
Change PC B Footprint
DIMM0 REV H:8mm (BOT)
DQS3#
NC/CKE1
NC/A15
NC/A14
NC/A13
DQS5#
DQS7#
4
2
VSS
4
DQ4
6
DQ5
8
VSS
10
DM0
12
VSS
14
DQ6
16
DQ7
18
VSS
20
DQ12
22
DQ13
24
VSS
26
DM1
28
VSS
30
CK0
32
CK0#
34
VSS
36
DQ14
38
DQ15
40
VSS
42
VSS
44
DQ20
46
DQ21
48
VSS
50
NC
52
DM2
54
VSS
56
DQ22
58
DQ23
60
VSS
62
DQ28
64
DQ29
66
VSS
68
70
DQS3
72
VSS
74
DQ30
76
DQ31
78
VSS
80
82
VDD
84
86
88
VDD
90
A11
92
A7
94
A6
96
VDD
98
A4
100
A2
102
A0
104
VDD
106
BA1
108
RAS#
110
S0#
112
VDD
114
ODT0
116
118
VDD
120
NC
122
VSS
124
DQ36
126
DQ37
128
VSS
130
DM4
132
VSS
134
DQ38
136
DQ39
138
VSS
140
DQ44
142
DQ45
144
VSS
146
148
DQS5
150
VSS
152
DQ46
154
DQ47
156
VSS
158
DQ52
160
DQ53
162
VSS
164
CK1
166
CK1#
168
VSS
170
DM6
172
VSS
174
DQ54
176
DQ55
178
VSS
180
DQ60
182
DQ61
184
VSS
186
188
DQS7
190
VSS
192
DQ62
194
DQ63
196
VSS
198
SAO
200
SA1
4
DDR_B_D4
DDR_B_D5
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6DDR_B_MA8
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D52
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_DM6
DDR_B_D54
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R44 10K_0402_5%
1 2
R45 10K_0402_5%
1 2
4.7U_0805_10V4Z
DDR_B_CLK1 5
DDR_B_CLK#1 5
DDR_CKE1_DIMMB 5
DDR_B_BS#1 5
DDR_B_RAS# 5
DDR_CS0_DIMMB# 5
DDR_B_ODT0 5
DDR_CS3_DIMMB# 5
DDR_B_CLK2 5
DDR_B_CLK#2 5
+3VS
3
+DIMM_VREF+1.8V+1.8V
0.1U_0402_16V4Z
C113
C112
1
1
2
2
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_BS#1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4
DDR_B_MA6
DDR_B_MA7
DDR_CKE0_DIMMB
DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA8
DDR_B_MA3
DDR_B_MA9
DDR_B_MA5
DDR_B_MA1
DDR_B_WE#
DDR_B_BS#0
DDR_B_MA10
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_ODT1
DDR_CS3_DIMMB#
DDR_B_MA13
DDR_B_ODT0
DDR_B_MA11
DDR_B_MA14
DDR_B_MA15
DDR_CKE1_DIMMB
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C114
+1.8V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C122
+0.9V
RP9
47_0804_8P4R_5%
RP10
47_0804_8P4R_5%
RP11
47_0804_8P4R_5%
RP12
47_0804_8P4R_5%
RP13
47_0804_8P4R_5%
RP14
47_0804_8P4R_5%
RP15
47_0804_8P4R_5%
RP16
47_0804_8P4R_5%
2007/01/07 2008/01/12
1
2
C115
1
2
C123
45
36
27
18
45
36
27
18
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
45
36
27
18
45
36
27
18
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C116
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C124
+0.9V
Compal Secret Data
1
2
C117
1
2
C125
Deciphered D ate
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C119
C118
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C127
C126
2
1
0.1U_0402_16V4Z
1
1
2
C120
1
2
C128
Layout Note:
Place one cap close to every 2 pullup
2
resistors terminated to +0.9V
C121
0.1U_0402_16V4Z
Layout Note:
1
Place one cap close to every 2 pullup
resistors terminated to +0.9V
2
C129
+1.8V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C130
C131
1
1
2
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C132
C133
1
1
2
2
Title
DDR2 SO-DIMM II
Size Document Number Rev
Custom
LA-3733P
Date: Sheet
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C134
C135
1
1
2
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C138
C137
C136
1
1
1
2
2
2
of
936Monday, March 05, 2007
0.1
5
4
http://hobi-elektronika.net
3
2
1
U3A
AF16
HT_MCP_RXD0_P
AG16
HT_MCP_RXD0_N
AH16
HT_MCP_RXD1_P
AJ16
HT_MCP_RXD1_N
AJ15
HT_MCP_RXD2_P
AK15
HT_MCP_RXD2_N
AK16
HT_MCP_RXD3_P
AL16
HT_MCP_RXD3_N
AG17
HT_MCP_RXD4_P
AF17
HT_MCP_RXD4_N
AL17
HT_MCP_RXD5_P
AK17
HT_MCP_RXD5_N
AL18
HT_MCP_RXD6_P
AK18
HT_MCP_RXD6_N
AJ19
HT_MCP_RXD7_P
AK19
HT_MCP_RXD7_N
AD14
HT_MCP_RXD8_P
AE14
HT_MCP_RXD8_N
AF14
HT_MCP_RXD9_P
AG14
HT_MCP_RXD9_N
AH14
HT_MCP_RXD10_P
AJ14
HT_MCP_RXD10_N
AL13
HT_MCP_RXD11_P
AK13
HT_MCP_RXD11_N
AC15
HT_MCP_RXD12_P
AD15
HT_MCP_RXD12_N
AD16
HT_MCP_RXD13_P
AE16
HT_MCP_RXD13_N
AE17
HT_MCP_RXD14_P
AD17
HT_MCP_RXD14_N
AB17
HT_MCP_RXD15_P
AC17
HT_MCP_RXD15_N
AJ17
HT_MCP_RX_CLK0_P
AH17
HT_MCP_RX_CLK0_N
AL14
HT_MCP_RX_CLK1_P
AK14
HT_MCP_RX_CLK1_N
AH19
HT_MCP_RXCTL0_P
AG19
HT_MCP_RXCTL0_N
AC18
HT_MCP_RXCTL1_P/RESERVED
AD18
HT_MCP_RXCTL1_N/RESERVED
AC13
THERMTRIP#/GPIO_58
AB13
PROCHOT#/GPIO_20
AB16
+3.3V_PLL_CPU
AB15
+1.2V_PLL_CPU_HT
AM12
HT_MCP_COMP_VDD
AL12
HT_MCP_COMP_GND
MCP67-MV_PBGA836
0.1U_0 402_16V4Z
C141
C144
0.1U_0 402_16V4Z
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
H_CTLOP0
H_CTLON0
+1.2V_ PLL_CPU_HT
+1.2V_HT
1 2
R47 150_0402_1%
1 2
R48 150_0402_1%
H_CADOP04
H_CADON04
H_CADOP14
D D
C C
+3.3V_PLL
4.7U_0 805_10V4Z
B B
+1.2V_HT
L2
1 2
MBK1608121YZF_0603
10U_0805_10V4Z
H_CADON14
H_CADOP24
H_CADON24
H_CADOP34
H_CADON34
H_CADOP44
H_CADON44
H_CADOP54
H_CADON54
H_CADOP64
H_CADON64
H_CADOP74
H_CADON74
H_CADOP84
H_CADON84
H_CADOP94
H_CADON94
H_CADOP104
H_CADON104
H_CADOP114
H_CADON114
H_CADOP124
H_CADON124
H_CADOP134
H_CADON134
H_CADOP144
H_CADON144
H_CADOP154
H_CADON154
H_CLKOP04
H_CLKON04
H_CLKOP14
H_CLKON14
H_CTLOP04
H_CTLON04
H_THERMTRIP#6
PROCHOT#6
1
1
C140
2
2
1
1
C143
2
2
MCP67
PART 1 OF 8
HT
RESERVED/HT_MCP_TXCTL1_P
RESERVED/HT_MCP_TXCTL1_N
HT_MCP_TXD0_P
HT_MCP_TXD0_N
HT_MCP_TXD1_P
HT_MCP_TXD1_N
HT_MCP_TXD2_P
HT_MCP_TXD2_N
HT_MCP_TXD3_P
HT_MCP_TXD3_N
HT_MCP_TXD4_P
HT_MCP_TXD4_N
HT_MCP_TXD5_P
HT_MCP_TXD5_N
HT_MCP_TXD6_P
HT_MCP_TXD6_N
HT_MCP_TXD7_P
HT_MCP_TXD7_N
HT_MCP_TXD8_P
HT_MCP_TXD8_N
HT_MCP_TXD9_P
HT_MCP_TXD9_N
HT_MCP_TXD10_P
HT_MCP_TXD10_N
HT_MCP_TXD11_P
HT_MCP_TXD11_N
HT_MCP_TXD12_P
HT_MCP_TXD12_N
HT_MCP_TXD13_P
HT_MCP_TXD13_N
HT_MCP_TXD14_P
HT_MCP_TXD14_N
HT_MCP_TXD15_P
HT_MCP_TXD15_N
HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N
HT_MCP_TXCTL0_P
HT_MCP_TXCTL0_N
HT_MCP_REQ#
HT_MCP_STOP#
HT_MCP_RST#
HT_MCP_PWRGD
CLKOUT_200MHZ_P
CLKOUT_200MHZ_N
CLKOUT_25MHZ
CPU_SBVREF
CLK200_TERM_GND
H_CADIP0
AK27
H_CADIN0
AJ27
H_CADIP1
AK26
H_CADIN1
AL26
H_CADIP2
AK25
H_CADIN2
AL25
H_CADIP3
AL24
H_CADIN3
AK24
H_CADIP4
AK22
H_CADIN4
AL22
H_CADIP5
AK21
H_CADIN5
AL21
H_CADIP6
AH21
H_CADIN6
AJ21
H_CADIP7
AL20
H_CADIN7
AM20
H_CADIP8
AG27
H_CADIN8
AH27
H_CADIP9
AF25
H_CADIN9
AG25
H_CADIP10
AH25
H_CADIN10
AJ25
H_CADIP11
AE23
H_CADIN11
AF23
H_CADIP12
AD21
H_CADIN12
AE21
H_CADIP13
AF21
H_CADIN13
AG21
H_CADIP14
AC20
H_CADIN14
AD20
H_CADIP15
AE19
H_CADIN15
AF19
H_CLKIP0
AK23
H_CLKIN0
AJ23
H_CLKIP1
AG23
H_CLKIN1
AH23
H_CTLIP0
AK20
H_CTLIN0
AJ20
AD19
AC19
HTCPU_REQ#
AD23
HTCPU_STOP#
AB20
HTCPU_RST#
AC21
HTCPU_PWRGD
AD22
AL28
AM28
0208_change to page 12
AK28
AG28
CLK200_TERM_GND
AJ28
R49
2.37K_0402_1%
H_CADIP0 4
H_CADIN0 4
H_CADIP1 4
H_CADIN1 4
H_CADIP2 4
H_CADIN2 4
H_CADIP3 4
H_CADIN3 4
H_CADIP4 4
H_CADIN4 4
H_CADIP5 4
H_CADIN5 4
H_CADIP6 4
H_CADIN6 4
H_CADIP7 4
H_CADIN7 4
H_CADIP8 4
H_CADIN8 4
H_CADIP9 4
H_CADIN9 4
H_CADIP10 4
H_CADIN10 4
H_CADIP11 4
H_CADIN11 4
H_CADIP12 4
H_CADIN12 4
H_CADIP13 4
H_CADIN13 4
H_CADIP14 4
H_CADIN14 4
H_CADIP15 4
H_CADIN15 4
H_CLKIP0 4
H_CLKIN0 4
H_CLKIP1 4
H_CLKIN1 4
H_CTLIP0 4
H_CTLIN0 4
HTCPU_STOP# 6
HTCPU_RST# 6
HTCPU_PWRGD 6
CPUCLK 6
CPUCLK# 6
1
12
C142
0.1U_0 402_16V4Z
2
+3VS
12
+1.2V_HT
R46
22K_0402_5%
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDE NTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIV ISION O F R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CO NTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL EL ECTRONICS , INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Title
MCP67 HT LINK
Size Document Number Re v
Custom
LA-3733P
2
Date: Sheet of
10 36Monday, March 05, 2007
1
0.1
5
D D
C C
B B
L3
1 2
+1.2VS
MBK1608121YZF_0603
L4
1 2
+1.2VS
MBK1608121YZF_0603
A A
5
C150
4.7U_0 805_10V4Z
1
2
MINI_CLKREQ#20
C148
4.7U_0 805_10V4Z
1
2
1
C151
0.1U_0 402_16V4Z
2
4.7U_0 805_10V4Z
4
http://hobi-elektronika.net
U3B
F23
PE0_RX0_P
G23
PE0_RX0_N
F24
PE0_RX1_P
F25
PE0_RX1_N
D25
PE0_RX2_P
D26
PE0_RX2_N
C28
PE0_RX3_P
D28
PE0_RX3_N
C29
PE0_RX4_P
C30
PE0_RX4_N
D29
PE0_RX5_P
D30
PE0_RX5_N
F26
PE0_RX6_P
F27
PE0_RX6_N
F28
PE0_RX7_P
F29
PE0_RX7_N
H23
PE0_RX8_P
H24
PE0_RX8_N
H25
PE0_RX9_P
H26
PE0_RX9_N
H27
PE0_RX10_P
H28
PE0_RX10_N
K24
PE0_RX11_P
K25
PE0_RX11_N
K27
PE0_RX12_P
K26
PE0_RX12_N
K28
PE0_RX13_P
K29
PE0_RX13_N
J31
PE0_RX14_P
J30
PE0_RX14_N
K31
PE0_RX15_P
K30
PE0_RX15_N
PE_CLK_COMP
12
R53
2.37K_0402_1%
H17
PE_WAKE#/GPIO_21
U31
PE0_PRSNTX1#/DDC_CLK1
U30
PE0_PRSNTX4#/DDC_DATA1
U29
PE0_PRSNTX8#/EXP_EN
U28
PE0_PRSNTX16#
L29
PE1_RX_P
L30
PE1_RX_N
W27
PEA_CLKREQ#
W28
PEA_PRSNT#
M26
PE2_RX_P
M27
PE2_RX_N
U26
PEB_CLKREQ#
U27
PEB_PRSNT#
N23
PE3_RX_P
N22
PE3_RX_N
U25
PEC_CLKREQ#
U24
PEC_PRSNT#
N30
PE4_RX_P
N31
PE4_RX_N
R22
PED_CLKREQ#/GPIO_16
U23
PED_PRSNT#
P31
PE5_RX_P
P30
PE5_RX_N
T22
PEE_CLKREQ#/GPIO_17
V31
PEE_PRSNT#
P26
PE6_RX_P
P27
PE6_RX_N
U22
PEF_CLKREQ#/GPIO_18
V30
PEF_PRSNT#
U19
+1.2V_PLL_PE_SS1
U20
+1.2V_PLL_PE_SS2
R20
+1.2V_PLL_PE1
R19
+1.2V_PLL_PE2
P19
+3.3V_PLL_PE_SS1
P20
+3.3V_PLL_PE_SS2
V24
PE_CLK_COMP
MCP67-MV_PBGA836
PCIE_WAKE#20
PCIE_RXP120
PCIE_RXN120
0209_new card doesn't use
C149
0.1U_0 402_16V4Z
1
2
+3.3V_PLL
1
C152
2
+1.2V_PLL_PE_SS1
+1.2V_PLL_PE1
1
C153
0.1U_0 402_16V4Z
2
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDE NTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIV ISION O F R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CO NTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL EL ECTRONICS , INC.
MVP67
PART 2 OF 8
Issued Date
3
D24
PE0_TX0_P
C24
PE0_TX0_N
A24
PE0_TX1_P
B24
PE0_TX1_N
B25
PE0_TX2_P
C25
PE0_TX2_N
B26
PE0_TX3_P
C26
PE0_TX3_N
C27
PE0_TX4_P
D27
PE0_TX4_N
A28
PE0_TX5_P
B28
PE0_TX5_N
A29
PE0_TX6_P
B29
PE0_TX6_N
A30
PE0_TX7_P
B30
PE0_TX7_N
B31
PE0_TX8_P
B32
PE0_TX8_N
C31
PE0_TX9_P
C32
PE0_TX9_N
D31
PE0_TX10_P
D32
PE0_TX10_N
E31
PE0_TX11_P
PCIE GFX I/F
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N
PE0_REFCLK_P
PE0_REFCLK_N
PE1_TX_P
PE1_TX_N
PE1_REFCLK_P
PE1_REFCLK_N
PE2_TX_P
PE2_TX_N
PE2_REFCLK_P
PE2_REFCLK_N
PE3_TX_P
PE3_TX_N
PE3_REFCLK_P
PE3_REFCLK_N
PE4_TX_P
PE4_TX_N
PE4_REFCLK_P
PE4_REFCLK_N
PE5_TX_P
PE5_TX_N
PE5_REFCLK_P
PE5_REFCLK_N
PE6_TX_P
PE6_TX_N
PE6_REFCLK_P
PE6_REFCLK_N
PEX_RST#
PEX_RST1#
E30
F31
F30
G29
G30
H29
H30
H32
H31
R29
R30
M28
M29
T32
T31
M24
M25
T29
T30
M22
M23
T27
T28
M30
M31
T25
T26
P29
P28
T23
T24
P24
P25
P23
R23
W30
W29
PCIE_TXP1_R
PCIE_TXN1_R
2007/01/07 2008/01/12
3
C145 0.1U_0402_16V7K
C146 0.1U_0402_16V7K
R52 0_0402_5%
1 2
Compal Secret Data
Deciphered Date
1 2
1 2
HT_VLD15,26
PE_RST0#
PCIE_RST1#
2
PCIE_TXP1 20
PCIE_TXN1 20
CLK_PCIE_MCARD 20
CLK_P CIE_MCARD# 20
1
MINI CARD
01/24
+3VALW
HT_VLD
PE_RST0#
2
2
1
R51 0_0402_5%
1 2
PCIE_RST1# 20
FOR MINI CARD
Title
Size Document Number Re v
Custom
Date: Sheet of
5
U4
P
B
4
Y
A
G
NC7SZ0 8P5X_NL_SC70-5
3
@
MCP67 PCIE LINK
LA-3733P
1
C147
0.1U_0 402_16V4Z
2
PCIE_RST#
PCIE_RST# 20
FOR LAN, IDE
1
11 36Monday, March 05, 2007
0.1
5
01/24
1
C156
2
+3.3V_PLL
4.7U_0 805_10V4Z
L7
MBK1608121YZF_0603
1
1
C170
2
2
0.1U_0 402_16V4Z
5
12
L5
MBK1608121YZF_0603
C157
1
0.1U_0 402_16V4Z
2
+3VS
C171
1U_0402_6.3V4Z
C161
1
2
1 2
L8
4.7U_0 805_10V4Z
01/24
+3VALW
C162
1
0.1U_0 402_16V4Z
2
MBK1608121YZF_0603
C172
1
2
+3VS
C177
4.7U_0 805_10V4Z
D D
4.7U_0 805_10V4Z
C C
+1.8VS
C169
0.1U_0 402_16V4Z
12
1
2
B B
A A
4
MII_RXD021
MII_RXD121
MII_RXD221
MII_RXD321
MII_RXCLK21
MII_RXDV21
MII_RXER21
MII_COL21
MII_CRS21
R58 10K_0402_5%
12
R60 49.9_0402_1%
1 2
1 2
R61 49.9_0402_1%
R63 124_0402_1%
1 2
1 2
C159 0.01U_0402_16V7K
1 2
R64 124_0402_1%
1 2
C160 0.01U_0402_16V7K
Y1
1 2
27MHZ_20P_7A27000010
1
C165
18P_0402_50V8J
2
ENABLT18
R72 22K_0402_5%
R73 6.2K_0402_5%
R74 10K_0402_5%
+3VS
0125 checklist
1
C178
2
0.1U_0 402_16V4Z
4
R67 0_0402_5%@
1 2
1 2
1 2
C174
1
0.1U_0 402_16V4Z
2
1K_0402_1%
INV_PWM18,27
ENAVDD18
1
C173
0.1U_0 402_16V4Z
2
1
2
Issued Date
3
MCP67
PART 3 OF 8
LAN
DACS
+3.3V_DUAL_RMGT
+1.2V_DUAL_RMGT
RGMII_TXD 0/MII_TXD 0
RGMII_TXD 1/MII_TXD 1
RGMII_TXD 2/MII_TXD 2
RGMII_TXD 3/MII_TXD 3
RGMII_TXCLK/MII_TXCLK
RGMII_TXC TL/MII_TXE N
RGMII/MII_PWRDWN#/GPIO_37
RGB_DAC_GREEN
RGB_DAC_HSYNC
RGB_DAC_VSYNC
FLAT PANEL
2007/01/07 2008/01/12
3
RGMII/MII_ MDC
RGMII/MII_ MDIO
BUF_25MHZ
MII_RESET#
MII_VREF
RGB_DAC_RED
RGB_DAC_BLUE
DDC_CLK0
DDC_DATA0
+3.3V_RGB_DAC
+3.3V_TV_DAC
TV_DAC_RED
TV_DAC_GREEN
TV_DAC_BLUE
IFPA_TXC_P
IFPA_TXC_N
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
IFPB_TXC_P
IFPB_TXC_N
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
DDC_CLK2
DDC_DATA2
DDC_CLK3
DDC_DATA3
IFPAB_RSET
IFPAB_VPROBE
L14
N18
J19
K19
L19
L18
H19
K18
K20
L20
D17
0208_change from page 10
G17
C18
H20
B21
C21
B22
G21
H21
G8
H8
E21
F21
C23
C22
D23
AE30
AE31
AC30
AC29
AC27
AC28
AD30
AD29
AD31
AD32
AJ31
AJ32
AE28
AE29
AF30
AF31
AG30
AG29
AH31
AH30
L21
J22
L22
K22
AB31
AB30
0.01U_0402_16V7K
Compal Secret Data
Deciphered Date
0130_same name
C163
0.1U_0 402_16V4Z
1
2
TV_CRMA
TV_LUMA
TV_COM PS
LVDSAC+
LVDSAC-
LVDSA0+
LVDSA0LVDSA1+
LVDSA1LVDSA2+
LVDSA2-
LVDSBC+
LVDSBC-
LVDSB0+
LVDSB0-
LVDSB1+
LVDSB1-
LVDSB2+
LVDSB2-
LCD_CLK
LCD_DAT
DDC_DATA3
IFPAB_RSET
IFPAB_PROBE
C176
http://hobi-elektronika.net
U3C
1
2
1 2
+1.8V_IFP_MCP
+3.3V_P LL_IFPP
R78
@
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RXCLK
MII_RXDV
MII_RXER
MII_COL
MII_CR S
MII_COMP_3P3V
RGB_DAC_RSET
RGB_DAC_VREF
TV_DAC_RSET
TV_DAC_VREF
NB_XTALIN
NB_XTALOUT
C166
18P_0402_50V8J
MII_COMP _GND
HDMI_RSET
12
B20
RGMII_RXD0/MII_RXD0
C20
RGMII_RXD1/MII_RXD1
E19
RGMII_RXD2/MII_RXD2
F19
RGMII_RXD3/MII_RXD3
G19
RGMII_RXC/MII_RXCLK
J20
RGMII_RXCTL/MII_RXDV
C19
MII_RXER/GPIO_36
J18
MII_COL/MI2C_DATA
D19
MII_CRS/MI2C_CLK
B18
RGMII/MII_ INTR/GPIO3 5
N13
+3.3V_PLL_MAC_DUAL
B17
MII_COMP_3P3V
C17
MII_COMP_GND
K21
RGB_DAC_RSET
D21
RGB_DAC_VREF
E23
TV_DAC_RSET
H22
TV_DAC_VREF
N15
+3.3V_PLL_DISP
E17
TV_XTA LIN
F17
TV_XTA LOUT
U11
GPIO_6/FERR//SYS_SERR/IGPU_GPIO_6*
T11
GPIO_7/NFERR//SYS_PERR/IGPU_GPIO_7*
AD24
LCD_BKL_CTL
AE25
LCD_BKL_ON
AE27
LCD_PANEL_PWR
AL29
HDMI_TXC_P
AM29
HDMI_TXC_N
AK29
HDMI_TXD0_P
AJ29
HDMI_TXD0_N
AM30
HDMI_TXD1_P
AL30
HDMI_TXD1_N
AK30
HDMI_TXD2_P
AJ30
HDMI_TXD2_N
AE26
HPLUG_DET3
AL32
HPLUG_DET2
AD25
HDCP_ROM_SCLK
AC26
HDCP_ROM_SDATA
AC24
+1.8V_IFPA
AC25
+1.8V_IFPB
AC23
+3.3V_IFPAB_HVDD
AC22
+3.3V_HDMI_PLL_HVDD
AH29
+3.3V_HDMI
AK31
HDMI_RSET
AK32
HDMI_VPROBE
1
MCP67-MV_PBGA836
C175
@
0.1U_0 402_16V4Z
2
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDE NTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIV ISION O F R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CO NTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL EL ECTRONICS , INC.
R54 0_0603_5%
R55 0_0603_5%
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
MII_TXCLK_R
MII_MDC
MII_MDIO
MII_PW RDWN
MII_RESET#
1
@
2
2
1 2
1 2
1 2
R5622_0402_5%
1 2
R33422_0402_5%
CRT_R 19
CRT_G 19
CRT_B 19
CRT_HSYNC 19
CRT_VSYNC 19
3VDDCCL 19
3VDDCDA 19
C164
4.7U_0 805_10V4Z
1
2
R77 10K_0402_5%
2
LVDSAC+ 18
LVDSAC- 18
LVDSA0+ 18
LVDSA0- 18
LVDSA1+ 18
LVDSA1- 18
LVDSA2+ 18
LVDSA2- 18
LVDSBC+ 18
LVDSBC- 18
LVDSB0+ 18
LVDSB0- 18
LVDSB1+ 18
LVDSB1- 18
LVDSB2+ 18
LVDSB2- 18
LCD_CLK 18
LCD_DATA 18
1 2
12
R79
@
1K_0402_1%
1
2
TV_CRMA 19
TV_LUMA 19
TV_COMPS 19
01/24
+3VALW
01/24
+1.2VALW+3VALW
C155
1
MII_TXD0 21
MII_TXD1 21
MII_TXD2 21
2
0.1U_0 402_16V4Z
MII_TXD3 21
MII_TXCLK 21
MII_TXEN 21
MII_MDC 21
MII_MDIO 21
MII_PW RDWN# 21
MII_RESET# 21
C158
1
0.1U_0 402_16V4Z
2
C167
0.1U_0 402_16V4Z
C168
1
4.7U_0 805_10V4Z
2
+3VS
Title
Size Document Number Re v
Custom
Date: Sheet of
C154
1
0.1U_0 402_16V4Z
2
01/24
+3VALW
12
R59
1.47K_0402_1%
12
R62
1.47K_0402_1%
L6
1 2
MBK2012121YZF_0805
CRT_R
R65 150_0402_1%
CRT_G
CRT_B
TV_CRMA
TV_LUMA
TV_COM PS
LCD_CLK
LCD_DAT
1 2
R66 150_0402_1%
1 2
R68 150_0402_1%
1 2
R69
1 2
R70
1 2
R71
1 2
CLOSE to CHIP
MCP67 LAN/ CRT/ LVDS
LA-3733P
1
MII_MDIO
+3VS
1
1 2
R57 1. 5K_0402_5%
150_0402_1%
150_0402_1%
150_0402_1%
+3VS
R752.7K_0402_5%
12
R762.7K_0402_5%
12
12 36Monday, March 05, 2007
01/24
+3VALW
0.1
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