Acer LA-3732P Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Merom uFCPGA with Satna Rosa Platform

3 3

2007-01-08

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-3732P

E

0.2

of

140Wednesday, March 14, 2007

A

B

C

D

E

Compal confidential

File Name : LA-3732P

ZZZ1

PCB

1 1

Spartan 1.0 (Merom +Crestline+ICH8)

Fan Control

page 4

H_A#(3..31)

Mobile Yonah/Merom

uFCPGA-478 CPU

Socket P

FSB

533/667/800MHz

H_D#(0..63)

Thermal Sensor
ADM1032AR

page 4page 4,5,6

Clock Generator

ICS9LPRS355

page 15

CRT/TV-OUT

page 16

LVDS Conn

page 17

2 2

NB Crestline

page 7,8,9,10,11,12

DDR2 -400/533/667

Dual Channel

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

DMI

USB2.0

USB Conn

page 27

PCI BUS

MODEM AMOM

PCI-E BUS

SB ICH8

AC-LINK/Azalia

Realtac

LED

3 3

page 28

RTL8100CL

page 23

page 18,19,20,21

SATA

Audio Conexant

CX20549-12

page 24

SATA HDD Connector

page 22

CX20548

page 25

AMP & Audio Jack
TPA6017A2

page 26

Mini-Card

RTC CKT.

page 19

RJ45/11 CONN

page 23

WLAN

page 22

PATA Master

IDE ODD Connector

page 22

LPC BUS

Power On/Off CKT.

page 28

4 4

DC/DC Int erface CKT.

page 31

Touch Pad CONN.

Power Circuit DC/DC

Page 32,33,34,35,36,37,38

A

B

ENE KB926

page 30

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SPI

Int.KBD

page 30page 28

2006/02/13 2006/07/26

SPI ROM

25LF080A

page 29

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-3732P

E

0.2

of

240Wednesday, March 14, 2007

5

4

3

2

1

Voltage Rails

+5VS

power
plane

D D

State

+B

+5VALW
+3VALW

+1.8V

+3VS
+1.5VS
+1.25VS
+0.9V
+VCCP
+CPU_CORE

Symbol Note :

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery

C C

don't exist

O
O
O
O
O

X

O
O
O
O

X

O

XX
X

XX X

OO
OO

X

X

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means jus t r e s e r v e for debug.

External PCI Devices

LAN AD22 0 A

B B

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

IDSEL # PIRQREQ/GNT #DEVICE

SMBUS Control Table

THERMAL
(CPU)

ADM1032

XX

V

X

X

XX

SODIMM CLK CHIP

X

X
X

MINI CARD

XX
X

VVV

XX

X

LCD

X
X

V

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

SMB_CK_CLK1
SMB_CK_DAT1 ICH8

LCD_CLK
LCD_DAT

KB925

KB925

Crestline

INVERTER BATT EEPROM

X
X

X

SERIAL SENSOR

VV

XX
X

XX

A A

BOM: 43XXXXXX
Jump-Short: PJP?

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-3732P

340Wednesday, March 14, 2007

1

0.2

of

5

4

3

2

1

XDP Connector

XDP_BPM#5

D D

H_A#[3..16]<7>

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_NMI<19>
H_SMI#<19>

12

R17

56_0402_5%@

B

2

C

Q2
MMBT3904_SOT23

H_ADSTB#0
H_REQ#0

H_REQ#1
H_REQ#2

H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

OCP# <20>

H_ADSTB#0<7>

H_REQ#0<7>
H_REQ#1<7>
H_REQ#2<7>
H_REQ#3<7>
H_REQ#4<7>

C C

B B

A A

H_A#[17..35]<7>

H_ADSTB#1<7>

H_A20M#<19>

H_FERR#<19>

H_IGNNE#<19>
H_STPCLK#<19>

H_INTR<19>

+VCCP

H_PROCHOT# OCP#

E

3 1

@

JP2A

J4

ADDR GROUP 0 ADDR GROUP 1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

CONN@

SP07000FP00 S SOCKET TYCO 2-1871873-2 478P H3 CPU
SP07000FD00 S SOCKET FOXCONN PZ4782A-274M-41 478P H3

DEFER#

CONTROL

RESET#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

ADS#
BNR#

BPRI#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

TDI

H_ADS#H_A#3

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#H_REQ#3

G2

H_HIT#

G6

H_HITM#

E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA_R

A24

H_THERMDC_R

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

For Merom, R14 and R15 are 0ohm
For Penryn, R14 and R15 are 100ohm.

H_ADS# <7>
H_BNR# <7>

H_BPRI# <7>

H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>

H_BR0# <7>

H_INIT# <19>
H_LOCK# <7>
H_RESET# <7>

H_RS#0 <7>

H_RS#1 <7>

H_RS#2 <7>

H_TRDY# <7>

H_HIT# <7>
H_HITM# <7>

XDP_DBRESET# <20>

R14 0_0402_5%

1 2

R15 0_0402_5%

1 2

R10

56_0402_5%

12

+VCCP

C2 0.1U_0402_16V4Z

1 2

R13

12

68_0402_5%

CLK_CPU_BCLK <15>
CLK_CPU_BCLK# <15>

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_THERMDA
H_THERMDC

H_THERMTRIP# <7,19>

H_PROCHOT# <37>

+VCCP

H_PWRGOOD_R<5>

+VCCP +VCCP

0.1U_0402_16V4Z

1

2

XDP_BPM#4
XDP_BPM#3

XDP_BPM#2
XDP_BPM#1

XDP_BPM#0

H_PWRGOOD_R
XDP_HOOK1

C1

XDP_TCK

layout note: C h a n ge R 7 to 6 4 9 ohm if using XTP to ITP adapter

XDP_DBRESET#_R

JP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

Thermal Sensor ADM1032ARMZ

0.1U_0402_16V4Z

C4

1 2

2200P_0402_50V7K

R16

1 2

+3VS

10K_0402_5%

ITPCLK#/HOOK5

RESET#/HOOK6

SAMTE_BSH-030-01-L-D-A@

+3VS

C3

H_THERMDA
H_THERMDC

THERM#

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

VCC_OBS_CD

DBR#/HOOK7

2

1

PWM Fan Control circuit

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3

10
12
14

GND5

16
18
20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44
46
48
50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

U1

1

VDD

2

D+

3

D­THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

Address:100_1100

+5VS

0306_Reserve.

R405 0_0402_5%@

1 2

+3VS

5

U2

1

FAN_PWM<30>

THERM#

INB

2

INA

P

4

O

G

TC7SH00FU_SSOP5

3

2 1

6

2

1

G

3

S

4 5

D1
RB751V_SOD323

D

Q1

SI3456BDV-T1-E3_TSOP6

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1

XDP_TRST#
XDP_TCK

CLK_CPU_XDP
CLK_CPU_XDP#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

Place R9 within 200ps (~1") to CPU

8

SCLK

7

SDATA

6

ALERT#

5

SMB_EC_DA2<30>

SMB_EC_CK2<30>

1

C5

4.7U_0805_10V4Z

2

R1

1 2

R2 54.9_0402_1%

1 2

R3 54.9_0402_1%

1 2

R4 54.9_0402_1%

1 2

R5 54.9_0402_1%

1 2

R6 54.9_0402_1%@

1 2

R7 51_0402_1%

1 2

R8 54.9_0402_1%

1 2

1K_0402_1%

H_RESET#H_RESET#_R

R9

1 2

XDP_DBRESET#XDP_DBRESET#_R

12

200_0402_1%

R11

R12 0_0402_5%

1 2

SMB_EC_CK2
SMB_EC_DA2

SMB_EC_DA2
SMB_EC_CK2

SP02000D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P

1

C6

0.1U_0402_16V4Z

2

FAN

12

D26

@

RLZ5.1B_LL34

+3VS

1K_0402_5%@

+VCCP

CLK_CPU_XDP <15>
CLK_CPU_XDP# <15>

JP3

1

1

2

2

3

G1

4

G2

ACES_85204-02001

CONN@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(1/3)-AGTL+/XDP

LA-3732P

1

0.2

of

440Wednesday, March 14, 2007

5

4

3

2

1

H_D#[0..15]<7>

D D

H_DSTBN#0<7>
H_DSTBP#0<7>

H_DINV#0<7>

H_D#[16..31]<7>

C C

H_DSTBN#1<7>
H_DSTBP#1<7>

H_DINV#1<7>

R20 1K_0402_5%@

1 2

R21 1K_0402_5%@

1 2

C8 0.1U_0402_16V4Z@

1 2

CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>

T1
T2

T3

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1 H_DINV#3

V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL0 H_PWRGOOD
CPU_BSEL1
CPU_BSEL2

JP2B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

CONN@

DATA GRP 1

MISC

DATA GRP 0

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#

H_CPUSLP#
H_PSI#

R26

1K_0402_5%

H_PWRGOOD_R

12

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

01

0

1

CPU_BSEL0

1

0

H_D#[32..47] <7>

H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>
H_D#[48..63] <7>

H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>

H_DPRSTP# <7,19,37>

H_DPSLP# <19>
H_DPWR# <7>
H_PWRGOOD <19>

H_CPUSLP# <7>
H_PSI# <37>

H_PWRGOOD_R <4>

12

R23

27.4_0402_1%

R24

12

R25

54.9_0402_1%

27.4_0402_1%

12

R22

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

12

+VCC_CORE +VCC_CORE

JP2C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

CONN@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

R18 0_0402_5%

G21
V6

R19 0_0402_5%

J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VSSSENSE

AE7

.

Length match within 25 mils.

+VCCP

12
12

1

+

C7

330U_4V_M

2

CPU_VID0 <37>
CPU_VID1 <37>
CPU_VID2 <37>
CPU_VID3 <37>
CPU_VID4 <37>
CPU_VID5 <37>
CPU_VID6 <37>

VCCSENSE <37>

VSSSENSE <37>

+1.5VS

1

1

C9

C10

2

2

0.01U_0402_16V7K

10U_0805_6.3V6M

Near pin B26

The trace width/space/other is
20/7/25.

+VCC_CORE

1 2

1 2

R28
100_0402_1%

R30
100_0402_1%

VCCSENSE

VSSSENSE

V_CPU_GTLREF

+VCCP

12

R27
1K_0402_1%

12

R29
2K_0402_1%

Close to CPU pin AD26
within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

Close to CPU pin
within 500mils.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Merom(2/3)-AGTL+/PWR

LA-3732P

1

of

540Wednesday, March 14, 2007

0.2

5

Place these capacitors on L8

D D

C C

B B

JP2D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

CONN@

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

+VCCP

1

C50

0.1U_0402_16V4Z

2

4

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

330U_D2E_2.5VM_R7

1

C51

0.1U_0402_16V4Z

2

1

C11
10U_0805_6.3V6M

2

1

C19
10U_0805_6.3V6M

2

1

C27
10U_0805_6.3V6M

2

1

C35
10U_0805_6.3V6M

2

1

C12
10U_0805_6.3V6M

2

1

C20
10U_0805_6.3V6M

2

1

C28
10U_0805_6.3V6M

2

1

C36
10U_0805_6.3V6M

2

Near CPU CORE regulator

+VCC_CORE

1

1

+

C45

+

2

330U_D2E_2.5VM_R7

1

C52

0.1U_0402_16V4Z

2

@

C46

2

1

C13
10U_0805_6.3V6M

2

1

C21
10U_0805_6.3V6M

2

1

C29
10U_0805_6.3V6M

2

1

C37
10U_0805_6.3V6M

2

330U_D2E_2.5VM_R7

1

+

C47

C48

2

330U_D2E_2.5VM_R7

1

C53

0.1U_0402_16V4Z

2

3

1

C14
10U_0805_6.3V6M

2

1

C22
10U_0805_6.3V6M

2

1

C30
10U_0805_6.3V6M

2

1

C38
10U_0805_6.3V6M

2

ESR <= 1.5m ohm
Capacitor > 1980uF

1000U 2.5V M H80 LESR8M

1

1

+

+

C49

2

2

0214_Change type from DIP to SMD.
0301_Delete C49.0301_Remount C46.

1

C54

0.1U_0402_16V4Z

2

1

C15
10U_0805_6.3V6M

2

1

C23
10U_0805_6.3V6M

2

1

C31
10U_0805_6.3V6M

2

1

C39
10U_0805_6.3V6M

2

Place these inside
socket cavity on L8
(North side
Secondary)

1

C55

0.1U_0402_16V4Z

2

1

C16
10U_0805_6.3V6M

2

1

C24
10U_0805_6.3V6M

2

1

C32
10U_0805_6.3V6M

2

1

C40
10U_0805_6.3V6M

2

2

1

C17
10U_0805_6.3V6M

2

1

C25
10U_0805_6.3V6M

2

1

C33
10U_0805_6.3V6M

2

1

C41
10U_0805_6.3V6M

2

1

C18
10U_0805_6.3V6M

2

1

C26
10U_0805_6.3V6M

2

1

C34
10U_0805_6.3V6M

2

1

C42
10U_0805_6.3V6M

2

1

Mid Frequence Decoupling

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(3/3)-GND&Bypass

LA-3732P

1

0.2

of

640Wednesday, March 14, 2007

5

W10

AD12

AC14
AD11
AC11

AJ14

AE11
AH12

AH13

M10
N12

AE3
AD9
AC9
AC7

AB2
AD7
AB1

AC6
AE2
AC5
AG3

AH8
AE9

AH5
AE7

AE5
AH2

E2

G2
G7
M6
H7
H3
G4

F3
N8
H2

N9
H5

P13

K9
M2

Y8

V4
M3

J1
N5
N3
W6
W9
N2

Y7

Y9

P4
W3
N1

Y3

AJ9

AJ5
AJ6
AJ7

AJ2
AJ3

B3
C2

W1
W2

B6

E5

B9

A9

U3A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

HOST

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_D#[0..63]<5>

D D

C C

+VCCP

12

12

R39

R40

54.9_0402_1%

54.9_0402_1%

H_RESET#<4>

H_CPUSLP#<5>

B B

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57

H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#
H_CPUSLP#

H_VREF

layout note:
Route H_SCOMP and H_SCOMP# with trace width, spacing and

impedance (55 ohm) same as FSB data traces

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

12

R45

12

R51

221_0603_1%

1

2

100_0402_1%

H_SWNGH_VREF

C63

0.1U_0402_16V4Z

+VCCP

12

R44

1K_0402_1%

A A

0.1U_0402_16V4Z

12

1

C62

R49

2

2K_0402_1%

R50

24.9_0402_1%

H_RCOMP

12

Near B3 pinwithin 100 mils from NB

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#
H_DBSY#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

4

V_DDR_MCH_REF<13,14,35>

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0H_D#58
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

H_A#[3..35] <4>

H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <15>
CLK_MCH_BCLK# <15>
H_DPWR# <5>
H_DRDY# <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>

H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>

H_DSTBN#0 <5>
H_DSTBN#1 <5>
H_DSTBN#2 <5>
H_DSTBN#3 <5>

H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>

H_REQ#0 <4>
H_REQ#1 <4>
H_REQ#2 <4>
H_REQ#3 <4>
H_REQ#4 <4>

H_RS#0 <4>
H_RS#1 <4>
H_RS#2 <4>

V_DDR_MCH_REF

1

C61

2

0.1U_0402_16V4Z

3

+1.8V

2

2

C56

1

2.2U_0805_16V4Z

SMRCOMP_VOH

SMRCOMP_VOL

2.2U_0805_16V4Z

1

C58

2

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_B DMI_TXN0

+1.8V

12

R43

@

1K_0402_1%

12

R46

@

1K_0402_1%

MCH_CLKSEL0<15>
MCH_CLKSEL1<15>
MCH_CLKSEL2<15>

PM_BMBUSY#<20>

PM_PWROK<20,30>

H_THERMTRIP#<4,19>

10K_0402_5%

10K_0402_5%

10K_0402_5%

H_DPRSTP#<5,19,37>
PM_EXTTS#0<13>
PM_EXTTS#1<14>

PLT_RST#<18,22>

DPRSLPVR<20,37>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

R31

C57

1

1K_0402_1%

0.01U_0402_16V7K

12

R32

3.01K_0402_1%

NA lead free

12

R33

1

1K_0402_1%

2

C59

0.01U_0402_16V7K

DDR_A_MA14<13>
DDR_B_MA14<14>

R36

R37

R38

<>

+3VS

12

12

12

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5

T4

CFG6

T5

CFG7

T6

CFG8

T7

CFG9

T8

CFG10

T9

CFG11

T10

CFG12

T11

CFG13

T12

CFG16

T13

CFG18

T44

CFG19

T14

CFG20

T15

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK
PLT_RST#
H_THERMTRIP#
DPRSLPVR

2006/02/13 2006/03/10

U3B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRESTLINE_1p0

Compal Secret Data

Deciphered Date

2

DDR MUXINGCLK

CFGRSVD

DMI

PM

GRAPHICS VID

ME

NC

MISC

2

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

TEST_1
TEST_2

20K_0402_5%

1

For Crestline: 20ohm

M_CLK_DDR0

AV29

M_CLK_DDR1

BB23

M_CLK_DDR2

BA25

M_CLK_DDR3

AV23

M_CLK_DDR#0

AW30

M_CLK_DDR#1

BA23

M_CLK_DDR#2

AW25

M_CLK_DDR#3

AW23

DDR_CKE0_DIMMA

BE29

DDR_CKE1_DIMMA

AY32

DDR_CKE2_DIMMB

BD39

DDR_CKE3_DIMMB

BG37

DDR_CS0_DIMMA#

BG20

DDR_CS1_DIMMA#

BK16

DDR_CS2_DIMMB#

BG16

DDR_CS3_DIMMB#

BE13

M_ODT0

BH18

M_ODT1

BJ15

M_ODT2

BJ14

M_ODT3

BE16

SMRCOMP

BL15

SMRCOMP#

BK14

SMRCOMP_VOH

BK31

SMRCOMP_VOL

BL31
AR49

V_DDR_MCH_REF

AW4

CLK_MCH_DREFCLK

B42

CLK_MCH_DREFCLK#

C42

MCH_SSCDREFCLK

H48

MCH_SSCDREFCLK#

H47

CLK_MCH_3GPLL

K44

CLK_MCH_3GPLL#

K45

AN47

DMI_TXN1

AJ38

DMI_TXN2

AN42

DMI_TXN3

AN46

DMI_TXP0

AM47

DMI_TXP1

AJ39

DMI_TXP2

AN41

DMI_TXP3

AN45

DMI_RXN0

AJ46

DMI_RXN1

AJ41

DMI_RXN2

AM40

DMI_RXN3

AM44

DMI_RXP0

AJ47

DMI_RXP1

AJ42

DMI_RXP2

AM39

DMI_RXP3

AM43

E35
A39
C38
B39
E36

CL_CLK0

AM49

CL_DATA0

AK50

M_PWROK

AT43

CL_RST#

AN49

CL_VREF CL_VREF

AM50

H35
K36

CLKREQ#_B

G39

MCH_ICH_SYNC#

G40

A37
R32

12

12

R47

R48
0_0402_5%

Title

CRESTLINE(1/6)-AGTL+/DMI/DDR2

Size Document Number Rev

Custom

LA-3732P

Date: Sheet

For Calero: 80.6ohm

M_CLK_DDR0 <13>
M_CLK_DDR1 <13>
M_CLK_DDR2 <14>
M_CLK_DDR3 <14>

M_CLK_DDR#0 <13>
M_CLK_DDR#1 <13>
M_CLK_DDR#2 <14>
M_CLK_DDR#3 <14>

DDR_CKE0_DIMMA <13>
DDR_CKE1_DIMMA <13>
DDR_CKE2_DIMMB <14>
DDR_CKE3_DIMMB <14>

DDR_CS0_DIMMA# <13>
DDR_CS1_DIMMA# <13>
DDR_CS2_DIMMB# <14>
DDR_CS3_DIMMB# <14>

M_ODT0 <13>
M_ODT1 <13>
M_ODT2 <14>
M_ODT3 <14>

CLK_MCH_DREFCLK <15>

CLK_MCH_DREFCLK# <15>

MCH_SSCDREFCLK <15>

MCH_SSCDREFCLK# <15>

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

DMI_TXN0 <20>
DMI_TXN1 <20>
DMI_TXN2 <20>
DMI_TXN3 <20>

DMI_TXP0 <20>
DMI_TXP1 <20>
DMI_TXP2 <20>
DMI_TXP3 <20>

DMI_RXN0 <20>
DMI_RXN1 <20>
DMI_RXN2 <20>
DMI_RXN3 <20>

DMI_RXP0 <20>
DMI_RXP1 <20>
DMI_RXP2 <20>
DMI_RXP3 <20>

T16
T17
T18
T19
T20

CL_CLK0 <20>
CL_DATA0 <20>
M_PWROK <20,30>
CL_RST# <20>

0.1U_0402_16V4Z

CLKREQ#_B <15>
MCH_ICH_SYNC# <20>

20_0402_1%

R34
R35 20_0402_1%

+1.25VM_AXD

1

C60

2

Compal Electronics, Inc.

1

12
12

12

12

740Wednesday, March 14, 2007

+1.8V

R41
1K_0402_1%

R42
392_0402_1%

of

0.2

5

D D

DDR_A_D[0..63]<13>

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BG10

AW9

AM8

AN10

AN9
AM9

AN11

BD8
AY9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AT9

U3D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

4

DDR_A_BS0

BB19
BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2

DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_RAS#
SA_RCVEN#

DDR_A_WE#

DDR_A_BS0 <13>
DDR_A_BS1 <13>
DDR_A_BS2 <13>

DDR_A_CAS# <13> DDR_B_CAS# <14>
DDR_A_DM[0..7] <13>

DDR_A_DQS[0..7] <13>

DDR_A_DQS#[0..7] <13>

DDR_A_MA[0..13] <13>

DDR_A_RAS# <13>

T22

DDR_A_WE# <13>

3

DDR_B_D[0..63]<14>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18DDR_A_DQS3
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41

DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BK10

BK5
BK9

BF4
BH5
BG1
BC2
BK3
BE4
BD3

BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

BL9
BL5

BJ8
BJ6

BJ2

2

U3E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

1

DDR_B_BS0

AY17

SB_BS_0
SB_BS_1

SB_BS_2
SB_CAS#
SB_DM_0

SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18
BG36

BE17
AR50

BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10DDR_B_D42
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#

SB_RCVEN#

DDR_B_WE#

DDR_B_BS0 <14>
DDR_B_BS1 <14>
DDR_B_BS2 <14>

DDR_B_DM[0..7] <14>

DDR_B_DQS[0..7] <14>

DDR_B_DQS#[0..7] <14>

DDR_B_MA[0..13] <14>

DDR_B_RAS# <14>

T21

DDR_B_WE# <14>

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 A/B CH

LA-3732P

1

of

840Wednesday, March 14, 2007

0.2

5

4

3

2

1

Strap Pin Table

010 = FSB 800MHz

CFG[2:0] FSB Freq select

D D

ENABLT<17>

+3VS

LCD_CLK<17>

For Crestline:2.4kohm
For Calero: 1.5Kohm

C C

B B

LCD_DATA<17>

ENAVDD<17>

+3VS

0312_Add test point.

ENABLT

R53 10K_0402_5%

1 2

R54 10K_0402_5%

1 2

LCD_CLK
LCD_DATA

ENAVDD

12

R55 2.4K_0402_1%

LVDSAC-<17>

LVDSAC+<17>
LVDSBC-<17>
LVDSBC+<17>

LVDSA0-<17>

LVDSA1-<17>

LVDSA2-<17>

LVDSA0+<17>

LVDSA1+<17>

LVDSA2+<17>

LVDSB0-<17>

LVDSB1-<17>

LVDSB2-<17>

LVDSB0+<17>

LVDSB1+<17>

LVDSB2+<17>

TV_COMPS<16>
TV_LUMA<16>
TV_CRMA<16>

2.2K_0402_5%

R56

1 2

CRT_B<16>
CRT_G<16>
CRT_R<16>

3VDDCCL<16>
3VDDCDA<16>

CRT_HSYNC<16>
CRT_VSYNC<16>

BKLT_CTRL

LVDSAC­LVDSAC+
LVDSBC­LVDSBC+

LVDSA0­LVDSA1­LVDSA2-

LVDSA0+
LVDSA1+
LVDSA2+

LVDSB0­LVDSB1­LVDSB2-

LVDSB0+
LVDSB1+
LVDSB2+

TV_COMPS
TV_LUMA
TV_CRMA

CRT_B
CRT_G
CRT_R

3VDDCCL
3VDDCDA
CRT_HSYNC

CRT_VSYNC

1.3K_0402_1%

12

R57

U3C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

CRESTLINE_1p0

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

LVDS

TV VGA

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

PEGCOMP

N43
M43

PEGCOMP tr ace width
and spacing is 20/25 mils.

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

R52

24.9_0402_1%

1 2

+VCCP

CFG5 (DMI select)

CFG6

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

CFG9

(PCIE Graphics Lane Reversal)

CFG[11:10]

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CFG[17:3] have internal pull up
CFG[19:18] have internal pull down

011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4

*

Reserved

0 = Reserved
1 = Mobile CPU

*

0 = Normal mode
1 = Low Power mode

*

0 = Reverse Lane
1 = Normal Operation

*

Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

11 = Normal Operation

(Default)

*

ReservedCFG[15:14]

0 = Disabled
1 = Enabled

*

ReservedCFG[18:17]

0 = No SDVO Device Present
1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

*

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO a r e o p e r a t ing simu.

*

For Crestline:1.3kohm
For Calero: 255ohm

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((3/6)-VGA/LVDS/TV

LA-3732P

1

of

940Wednesday, March 14, 2007

0.2

5

+3VS_DAC_BG

BLM18PG181SN1D_0603

0.022U_0402_16V7K

0.1U_0402_16V4Z

1

1

C65

C66

2

2

D D

+3VS_DAC_CRT

C C

0.022U_0402_16V7K

C73

+1.25VS

BLM18PG181SN1D_0603

1

1

C74

2

2

220U_6.3V_M

0.1U_0402_16V4Z

+3VS

C90

R71

0_0603_5%

+3VS

12

R59

R62

1

+

10U_0805_10V4Z

2

+1.25VM_A_SM_CK

12

C99

+3VS

12

R66

0_0603_5%

0.1U_0402_16V4Z

R68

1 2

0_0805_5%

1U_0603_10V4Z

C100

1

2

+3VS

+1.8V_TXLVDS

+3VS_PEG_BG

12

C85

1

C91

4.7U_0805_10V4Z

2

100mA

10U_0805_10V4Z

1

2

0215_Change package from 0402 to 0603.

+3VS_TVDACC

B B

0.022U_0402_16V7K

C111

+3VS_TVDACA

0.022U_0402_16V7K

C115

A A

+3VS_TVDACB

0.022U_0402_16V7K

C121

1

C112

2

1

C116

2

1

C122

2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

2

5

+3VS

12

R74

+3VS

12

R78

+3VS

12

R80

1

2

C101

R58

0_0603_5%

10mA

5mA

+1.25VM_A_SM

C92

1U_0603_10V4Z

1

2

+1.25VS_PEGPLL

VCCSYNC

12

1

C64

2

+3VS_DAC_CRT

+1.25VS_DPLLA
+1.25VS_DPLLB

+1.25VM_HPLL
+1.25VM_MPLL

1000P_0402_50V7K
C82

+1.25VS_PEGPLL

950mA

1

2

1U_0603_10V4Z

0.1U_0402_16V4Z

C102

1

2

+1.5VS_TVDAC

+1.5VS_QDAC

+1.25VM_HPLL

+1.8V_LVDS

+1.5VS_QDAC

0.022U_0402_16V7K

10U_0805_10V4Z

10mA

0.1U_0402_16V4Z

+3VS_DAC_BG

80mA
80mA
50mA
150mA

1

2

1

C93

2

40mA

+3VS_TVDACA

40mA

+3VS_TVDACB

40mA

+3VS_TVDACC

75mA

250mA
100mA

150mA

1

C113

C114

2

+1.8V_LVDS

1U_0603_10V4Z

C119

1

2

80mA

5mA

20 mils

5mA

1

2

C120

AM2

AW18
AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18

AT17
AR17
AR16

BC29
BB29

50mA

M32

25mA

AN2

0.1U_0402_16V4Z

R81

0_0603_5%

1

2

4

U3H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL
VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC
VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0

R77

100_0603_1%

4

3

+VCCP

850mA

350mA

100mA

120mA

100mA

1200mA

330U_4V_M

C71

+1.25VM_AXD

200mA

1U_0603_10V4Z

+V1.25VS_AXF

+1.25VS_DMI

+1.8V_SM_CK

+1.8V_TXLVDS

1450mA

+VCC_PEG

1

+

2

1

C75

2

C83

1

2

0.47U_0603_10V7K

C84

100mA

C72

1

C76

2

10U_0805_10V4Z

1

2

+3VS_HV

C103

4.7U_0805_10V4Z

1

2

4.7U_0805_10V4Z

C77

R65

1 2

0_0805_5%

0.1U_0402_16V4Z

1

2

2.2U_0805_16V4Z

1

2

250mA

20mils

0.47U_0603_10V7K

0.47U_0603_10V7K
C109

C108

1

2

1

1

C117
10U_0805_10V4Z

2

2

0208_Change C117 value from 220uF to 10uF.

Issued Date

1

2

0_0603_5%

3

0.47U_0603_10V7K

C110

1

2

R79

12

2006/02/13 2006/03/10

+1.25VS

+1.8V

Compal Secret Data

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

AXD

VCC_AXD_NCTF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

PEG

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

VCC_DMI

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VTTLF1
VTTLF2
VTTLF3

U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

VTTLF

+1.5VS

12

12

+1.8V

1000P_0402_50V7K

+1.8V_TXLVDS

C118

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.25VS_DPLLB

0.1U_0402_16V4Z

+1.25VS_DMI

+1.25VS_PEGPLL

+1.25VS_DPLLA

220U_6.3V_M

@

1

C94

+

2

Deciphered Date

10U_0805_10V4Z

C67

1

2

1 2

0.1U_0402_16V4Z

C81

1

2

0.1U_0402_16V4Z
C86

1

2

C95

1

2

0.1U_0402_16V4Z

+VCC_PEG

220U_6.3V_M

1

C104

+

2

2

R60

1 2

10U_FLC-453232-100K_0.25A_10%

C68

1

2

R63

0_0603_5%

BLM18PG121SN1D_0603

10U_0805_10V4Z

1

2

C96

1

2

C105

1

2

2

+1.25VS

+1.25VS

L1

12

C87

R69

1 2

10U_0805_10V4Z

10U_FLC-453232-100K_0.25A_10%

R72

0_0805_5%

10U_0805_10V4Z

+VCCP

+3VS

1

+V1.25VS_AXF

10U_0805_10V4Z

1U_0603_10V4Z

C69

1

2

+1.8V_SM_CK

10U_0805_10V4Z

10U_0805_10V4Z

C78

1

2

+1.25VS

+1.25VS

0.1U_0402_16V4Z

+VCCP

12

0.1U_0402_16V4Z

+VCCP_D

D2

2 1

CH751H-40PT_SOD323-2

Title

Size Docum ent Number Rev

Custom

LA-3732P

Date: Sheet

C79

1

2

+1.5VS_TVDAC

0.022U_0402_16V7K

1

C88

2

+1.25VM_HPLL

1

C97

2

+1.25VM_MPLL

1

C106

2

R75

12

10_0402_5%

Compal Electronics, Inc.

CRESTLINE(4/6)-PWR

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C89

2

MBK2012121YZF_0805

1

C98
10U_0805_10V4Z

2

MBK2012121YZF_0805

1

C107
10U_0805_10V4Z

2

R76

0_0402_5%

1

C70

1

2

1 2

C80

1

2

1 2

R70

R73

12

0_0805_5%

0_0805_5%

1 2

0_0603_5%

R64

R67

12

+1.25VS

12

+3VS_HV

10 40Wednesday, March 14, 2007

+1.25VS

R61

+1.8V

+1.5VS

+1.25VS

0.2

of

5

4

3

2

1

+VCCP

VCC=1260mA

D D

0.22U_0603_10V7K

220U_6.3V_M

C126

C C

B B

1

2

0.22U_0402_10V4Z

10U_0805_10V4Z

1

+

2

0.22U_0402_10V4Z
C142

C128

C127

1

2

0.22U_0402_10V4Z
C143

1

2

1

1

2

2

+VCCP

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C144

1

1

2

2

+VCCP

VCC=1260mA

0.1U_0402_16V4Z

C129

C130

1

2

VCC_AXM=970mA

10U_0805_10V4Z

C136

C135

1

1

2

2

0.1U_0402_16V4Z

C145

C146

1

2

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36

AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

AL24

AL26

AL28

AM26
AM28
AM29
AM31
AM32
AM33

AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

U3F

CRESTLINE_1p0

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

VSS NCTF

VCC NCTF

POWER

VCC AXM NCTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

VCC_AXM=970mA

+VCCP

C138

1U_0603_10V4Z

R82

1 2

0_0603_5%

3720mA

+1.8V

C131

330U_4V_M

1

C137

2

330U_4V_M

10U_0805_10V4Z

1

+

C139

2

10U_0805_10V4Z

1

+

2

1

C140

2

10U_0805_10V4Z

10U_0805_10V4Z

C132

C133

1

1

2

2

VCC_AXG=7700mA

+VCCP

0.1U_0402_16V4Z

1

C141

2

0.01U_0402_16V7K

C134

2

1

1

2

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

W13

W14
AA20

AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R30

R20

T14

Y12

U3G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

+VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

VCC_AXG=7700mA

0.1U_0402_16V4Z
C123

1

2

0.22U_0603_10V7K

C147 0.1U_0402_16V4Z

C148 0.1U_0402_16V4Z

1

1

1

2

2

2

C124

1

1

2

C149 0.22U _0603_10V7K

1

2

C150 0.22U _0603_10V7K

1

2

C125

2

4.7U_0805_10V4Z

C151 0.47U _0603_10V7K

C152 1U_0603_10V4Z

1

1

2

2

C153 1U_0603_10V4Z

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

CRESTLINE_1p0

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((5/6)-PWR/GND

LA-3732P

1

of

11 40Wednesday, March 14, 2007

0.2

5

U3I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

AB23
AB26
AB28
AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50
AE10

AE14
AF20

AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH40
AH41

AJ11

AJ13

AJ21

AJ24

AJ29

AJ32

AJ43

AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM3

AM4
AM41
AM45

AN38
AN39
AN43

AP48
AP50
AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51
AV39
AV48

AW1

AW12
AW16

AC3

AD1

AD3

AD5
AD8

AE6

AH3

AH7
AH9

AL1

AN1

AN5
AN7
AP4

AR2

AR7

AU1

AU3

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U3J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

2

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((6/6)-PWR/GND

LA-3732P

1

0.2

of

12 40Wednesday, March 14, 2007

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>

DDR_A_DQS[0..7]<8>

DDR_A_MA[0..14]<7,8>

D D

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

DDR_A_MA3
DDR_A_MA10

DDR_A_MA8
DDR_A_MA5

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_MA1
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_CS1_DIMMA# M_ODT0
M_ODT1

DDR_A_MA11

1

2

1

2

C157

C166

C158

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C167

RP1

RP3

RP5

RP7

RP9

RP11

R85 56_0402_5%

5

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

1 2

2.2U_0805_16V4Z
C159

1

2

0.1U_0402_16V4Z

1

1

2

2

C168

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

C169

+0.9V

2.2U_0805_16V4Z
C160

1

2

0.1U_0402_16V4Z

1

2

C170

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C161

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C171

C172

RP2 56_0404_4P2R_5%

DDR_CKE0_DIMMA

14

DDR_A_BS2

23

RP4 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP6 56_0404_4P2R_5%

DDR_A_MA12

14

DDR_A_MA9

23

RP8 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP10 56_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS1

23

RP12 56_0404_4P2R_5%

14

DDR_A_MA13

23

RP13 56_0404_4P2R_5%

DDR_CKE1_DIMMA

14

DDR_A_MA14

23

0.1U_0402_16V4Z

C162

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C173

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C164

C163

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C175

C174

1

C165

1

+

C156

330U_4V_M

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

2

C176

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"

C178

C177

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP4

1

VREF

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9 DDR_A_D11
DDR_A_D15 DDR_A_D10

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA<7>

DDR_A_BS2<8>

DDR_A_BS0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<7>

M_ODT1<7>

CLK_SMBDATA<14,15>

CLK_SMBCLK<14,15>

3

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D61 DDR_A_D57

DDR_A_D60
DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

2

2.2U_0805_16V4Z

2006/02/13 2006/03/10

C180

C179

Compal Secret Data

1

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

FOX_ASOA426-M4R-TR

CONN@

SO-DIMM A

SP07F001720 S SOCKET FOXCONN AS0A426-N4RN-7F DR2R H4
FOX_AS0A426-M4R-TR_200P

0.1U_0402_16V4Z

Deciphered Date

VSS
DQ4
DQ5
VSS

DM0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO
GND

2

+1.8V

V_DDR_MCH_REF

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34
36
38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

SA1

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D39
DDR_A_D38

DDR_A_DM4
DDR_A_D34

DDR_A_D33
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R83

R84

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C154

1

2

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

PM_EXTTS#0 <7>

DDR_CKE1_DIMMA <7>

DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3732P

1

C155

1

V_DDR_MCH_REF <7,14,35>

of

13 40Wednesday, March 14, 2007

0.2

0.1U_0402_16V4Z

1

2

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>
DDR_B_DM[0..7]<8>

DDR_B_DQS[0..7]<8>

DDR_B_MA[0..14]<7,8>

D D

C C

B B

A A

Layout Note:
Place near JP10

+1.8V

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C184

1

2

0.1U_0402_16V4Z

1

2

C193

RP14

1 4
2 3

RP16

56_0404_4P2R_5%

1 4
2 3

RP18

56_0404_4P2R_5%

1 4
2 3

RP20

56_0404_4P2R_5%

1 4
2 3

RP22

56_0404_4P2R_5%

1 4
2 3

RP24

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

1 2

R88

56_0402_5%

5

2.2U_0805_16V4Z
C185

1

2

0.1U_0402_16V4Z

1

2

C194

2.2U_0805_16V4Z
C183

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

1

2

C192

DDR_B_MA1
DDR_B_MA3

DDR_B_BS0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2
M_ODT3

DDR_CKE3_DIMMB

2.2U_0805_16V4Z
C186

1

2

0.1U_0402_16V4Z

1

1

2

2

C195

C196

+0.9V

RP15 56_0404_4P2R_5%

RP17 56_0404_4P2R_5%

RP19 56_0404_4P2R_5%

RP21 56_0404_4P2R_5%

RP23 56_0404_4P2R_5%

RP25 56_0404_4P2R_5%

RP26

56_0404_4P2R_5%

2.2U_0805_16V4Z
C187

1

2

0.1U_0402_16V4Z

1

2

C197

14
23

14
23

14
23

14
23

14
23

14
23

14
23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C188

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C198

C199

DDR_B_MA9
DDR_B_MA12

DDR_B_MA14
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13

DDR_B_BS2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C189

1

2

0.1U_0402_16V4Z

1

2

C200

0.1U_0402_16V4Z

C190

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C202

C201

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

C191

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C203

C204

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP5

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB<7>

DDR_B_BS2<8>

DDR_B_BS0<8>
DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

CLK_SMBDATA<13,15>

CLK_SMBCLK<13,15>

+3VS

3

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D59

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

C206

1

2

Compal Secret Data

1

C205

2

2.2U_0805_16V4Z

2006/02/13 2006/03/10

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

FOX_AS0A426-N8RN-7F

CONN@

SO-DIMM B

SP07000BZ00 S SOCKET FOXCON AS0A426-N8RN-7F H8 DDR2R
FOX_AS0A426-N8RN-7F_200P

0.1U_0402_16V4Z

Deciphered Date

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

SA0

SA1

GND

2

+1.8V

V_DDR_MCH_REF

2

DDR_B_D5

4

DDR_B_D4

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D7

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR3

30

M_CLK_DDR#3

32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D21DDR_B_D17

44

DDR_B_D16

46
48
50

NC

A7
A6

A4
A2
A0

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24DDR_B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

10K_0402_5%

12

R87

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C181

2

2

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

PM_EXTTS#1 <7>

DDR_CKE3_DIMMB <7>

DDR_B_BS1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

R86

1 2

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet of

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3732P

1

V_DDR_MCH_REF <7,13,35>

C182

1

14 40Wednesday, March 14, 2007

0.2

5

PCI

SRC

CPU

CLKSEL1

FSLA

CLKSEL0

MHz

MHz

MHz

FSLC FSLB

CLKSEL2

011000 133 33.3

0

1200

1

FSB Frequency Selet:

D D

CPU Driven

(Default)

*

Stuff

No Stuff

Stuff

667MHz

No Stuff

Stuff

800MHz

C C

CPU_BSEL0<5>

CPU_BSEL1<5>

B B

CPU_BSEL2<5>

+3VS +3VS +3VS

A A

1 2

1 2

No Stuff

R97

2.2K_0402_5%

FSA

NO SHORT PADS

FSC

R134
10K_0402_5%

ITP_EN 27_SEL PCI2_TME

R138
10K_0402_5%

@

CLRP2

FSB

1 2

R115

0_0402_5%

R124

10K_0402_5%

1 2

R126

0_0402_5%

R135
10K_0402_5%

@

1 2

R139
10K_0402_5%

1 2

12

12

+VCCP

+VCCP

12

5

100

33.30

100

1661

33.30

R1107 R1135 R1 083

R1074 R1086 R1 098 R1113 R1139

R1139 R1135R1135 R1139

R1083

R1107

R1128

R1098

R1113

R1128

R1074R1086

R1135 R1139

R1083

R1086

R1098

R1074

R93

1 2

12

56_0402_5%
CLRP1
NO SHORT PADS

1 2

R98

1K_0402_5%

12

R102
1K_0402_5%@

R111
1K_0402_5%@

1 2

1 2

R114

1K_0402_5%

12

R116

@

0_0402_5%

R121
1K_0402_5%@

1 2

1 2

R125

1K_0402_5%

12

R129

@

0_0402_5%

R1107

R1128

R1113

+VCCP

MCH_CLKSEL0 <7>

MCH_CLKSEL1 <7>

MCH_CLKSEL2 <7>

CLRP4,CLRP5 for 667/800 FSB select
SHORT CLRP5, NO SHORT CLRP4 -- CPU option
SHORT CLRP4, NO SHORT CLRP5 -- FSB 667

0301_Change R105 from 22 ohm to 0 ohm.
0312_Change R106, 107, 109 from 22 to 33 ohm.

CLKSATAREQ#<20>

CLK_DEBUG_PORT<22,29,30>

CLK_PCI_LAN<23>
CLK_PCI_EC<30>
CLK_PCI_ICH<18>

Routing the trace at
least 10mil

CLK_48M_ICH<20>

CLK_14M_ICH<20>

CLK_14M_DEBUG<30>

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For 27_SEL, 0 = Enable DOT96 & SRC1,

R136
10K_0402_5%

1 2

R140
10K_0402_5%

@

1 2

1= Enable SRC0 & 27MHz

For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed

4

1 2

+3VS

FBMA-L11-201209-221LMA30T_0805

CLKREQ#_B<7>

C230

18P_0402_50V8J

4

+3VS_CK505

R89

+1.25VS_CK505

1 2
1 2
1 2
1 2
1 2
1 2

Y1

14.31818MHZ_16P

2

1

1 2

1 2
1 2

3

1

C207
10U_0805_10V4Z

2

FBMA-L11-201209-221LMA30T_0805

1

C208

0.1U_0402_16V4Z

2

+1.25VS

1 2

R92

1

C209
680P_0402_50V7K

2

1

C214

2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C215

2

1

C210

0.1U_0402_16V4Z

2

680P_0402_50V7K

1

C211
680P_0402_50V7K

2

Place close to U4

10U_0805_10V4Z

1

1

C216

C217

2

2

1

C212

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C218

2

680P_0402_50V7K

+1.25VS_CK505

0308_Change R89 and R92 form 0 ohm to bead, C209, C211, C216, C218 from 0.1uF to 680pF.

12

2

1

+3VS_CK505

R103475_0402_1%
R104475_0402_1%
R1050_0402_5%
R10633_0402_5%
R10733_0402_5%
R10933_0402_5%

CLK_XTAL_IN

CLK_XTAL_OUT

C231
18P_0402_50V8J

R11733_0402_1%

R12033_0402_1%
R40033_0402_1% @

+1.25VS_CK505

PCI_CLK1
PCI2_TME

PCI_LANCLK

FSA

FSB

FSC

U4

2

VDD_PCI

9

VDD48

16

VDDPLL3

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96_IO

20

VDDPLL3_IO

26

VDDSRC_IO

36

VDDSRC_IO

49

VDDCPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

27_SEL

6

PCI4/27_Select

ITP_EN

7

PCIF5/ITP_EN

60

X1

59

X2

10

USB_48MHZ/FSLA

57

FSLB/TEST MODE

62

REF0/FSLC/TEST_SEL

45

VDDSRC_IO

42

GNDSRC

8

GNDPCI

11

GND48

15

GND

19

GND

52

GNDCPU

23

GNDSRC

29

GNDSRC

58

GNDREF

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CPU_STOP#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2#/SATA#

SRC1/SE1/27MHz_NonSS

SRC1#/SE2/27MHz_SS

SRC0/DOT96

SRC0/DOT96#

CK_PWRGD/PD#

ICS9LPRS355_TSSOP64

2006/02/13 2006/03/10

SCLK

SDATA

PCI_STOP#

CPU0

CPU0#

CPU1_F

CPU1#_F

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

SRC2/SATA

48

NC

CLK_SMBCLK

64

CLK_SMBDATA

63
38

37

R_CPU_BCLK

54

R_CPU_BCLK#

53

R_MCH_BCLK

51

R_MCH_BCLK#

50

47

R_CPU_XDP#

46

35
34

33
32

30
31

44

R_CLKREQ#_G

43

R_CLK_PCIE_MCard

41

R_CLK_PCIE_MCard#

40

R_MCH_3GPLL

27

R_MCH_3GPLL#

28

R_PCIE_ICH

24

R_PCIE_ICH#

25

R_PCIE_SATA

21

R_PCIE_SATA#

22

SSCDREFCLK

17

SSCDREFCLK#

18

R_MCH_DREFCLK

13

R_MCH_DREFCLK#

14

56

Compal Secret Data

R94

1 2
1 2

R95
R96

1 2
1 2

R99

R100 0_0402_5%

1 2
1 2

R101

For Layout request:

1. Change MINI_CLKREQ# from pin 32 to pin 43.

2. Change CL K _ P C I E_ M C ARD from SRC9 to SRC6.

R108 475_0402_1%

R112

1 2
1 2

R113
R118

1 2
1 2

R119
R122

1 2
1 2

R123
R127

1 2
1 2

R128

R130 0_0402_5%

1 2

R131 0_0402_5%

1 2

R132

1 2
1 2

R133

1 2

R137 0_0402_5%@

1 2

R367 0_0402_5%@

1 2

R344 0_0402_5%

Deciphered Date

1

C219

2

12

2

1

C213

0.1U_0402_16V4Z

2

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%

R110 10K_0402_5%

1 2

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

2

ICH_SMBDATA<20,22>

SB, MINI PCI

ICH_SMBCLK<20,22>

CLK_SMBCLK <13,14>
CLK_SMBDATA <13,14>

H_STP_PCI# <20>
H_STP_CPU# <20>

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>

CLK_CPU_XDP <4>
CLK_CPU_XDP# <4>

MINI_CLKREQ# <22>

+3VS

CLK_PCIE_MCARD <22>
CLK_PCIE_MCARD# <22>

CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>

CLK_PCIE_ICH <20>

CLK_PCIE_ICH# <20>

CLK_PCIE_SATA <19>
CLK_PCIE_SATA# <19>

MCH_SSCDREFCLK <7>
MCH_SSCDREFCLK# <7>

CLK_MCH_DREFCLK <7>
CLK_MCH_DREFCLK# <7>

VGATE <20,37>

CLK_ENABLE <30>
CK_PWRGD <20>

1

+3VS

R90

2.2K_0402_5%

Q3
2N7002_SOT23-3

D

S

1 3

G

+3VS

Title

Size Document Number Rev

Date: Sheet

2

2

G

Q4
2N7002_SOT23-3

1 3

D

S

C220
C221
C222
C225
C227
C229

Compal Electronics, Inc.

Clock generator

LA-3732P

R91

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

CLK_48M_ICH

12

5P_0402_50V8C@

CLK_14M_ICH

12

4.7P_0402_50V8C@

CLK_PCI_ICH

12

4.7P_0402_50V8C@

CLK_PCI_EC

12

4.7P_0402_50V8C@

CLK_PCI_LAN

12

4.7P_0402_50V8C@

CLK_DEBUG_PORTR_CPU_XDP

12

5P_0402_50V8C@

of

15 40Wednesday, March 14, 2007

1

0.2

A

B

C

D

E

1 1

2 2

R146

CRT_HSYNC<9>

CRT_VSYNC<9>

1 2

R151

1 2

0_0402_5%

0_0402_5%

CRT_R<9>

CRT_G<9>

CRT_B<9>

C239

1 2

0.1U_0402_16V4Z

CRTVSYNC

CRTL_B
CRTL_G
CRTL_R

+5VS

1

2

5

P

A2Y

G

3

5

P

A2Y

G

3

D4

DAN217_SC59

@

2

3

EMI

1

U5

4

OE#

1

U6

4

OE#

D5

1

3

74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5

D6

1

DAN217_SC59

2

CRT_R

CRT_G

CRT_B

DAN217_SC59@

3

R141

@

EMI

Place close to JP6

+CRTVDD

1

2

1 2

75_0402_5%

C233

10P_0402_50V8J

@

CRT_HSYNC_R

CRT_VSYNC_R

R142

1 2

75_0402_5%

C234

+R_CRT_VCC , +CRTVDD (40mils)

1

2

R144 4.7K_0402_5%

1

2

C241 10P_0402_50V8J

+CRTVDD

R145 4.7K_0402_5%

+CRTVDD

C242 220P_0402_50V8J

JP6

CONN@

6

11

1

16

7

17

12

2
8

13

3
9

DC060001M00 D-CONN 15P D-SUB_F C10510-11505-L

14

4

DC060002300 D-CONN 15P VGA_F 070546FR015S235ZR SUYIN

10
15

5

ALLTO_C10510-115A5-L
Q5
2N7002_SOT23-3

D

S

1 3

G

2

D

1

1

2

2

C243 220P_0402_50V8J

1 3

G

2

Q6

2N7002_SOT23-3

S

R149

2.2K_0402_5%

3V_DDCDA

3V_DDCCL

R150

2.2K_0402_5%

+3VS

R147

1 2

R148

1 2

+5VS

+R_CRT_VCC

1.1A_6VDC_FUSE

0.1U_0402_16V4Z

CRTL_R

CRTL_G

CRTL_B

1

2

CRT_HSYNCRFLCRTHSYNC

CRT_VSYNCRFL

F1

21

C232

1

2

C240

10P_0402_50V8J

D7

2 1

RB411D_SOT23

CRT CONNECTOR

EMI

L2
MBK2012800YZF

1 2

L3
MBK2012800YZF

1 2

L4
MBK2012800YZF

1 2

R143

1 2

75_0402_5%

C235

@

1

2

10P_0402_50V8J

1

2

10P_0402_50V8J

@

EMI

1

1

2

2

C236

22P_0402_50V8J

C237

22P_0402_50V8J

1 2

L5
FBM-L11-160808-800LMT_0603

1 2

L6
FBM-L11-160808-800LMT_0603

C238

22P_0402_50V8J

EMI

NZQA5V6AXV5T1_SOT533-5

2

1 5

D3

@

CLOSE TO JP3

0_0402_5%

0_0402_5%

3VDDCDA <9>

3VDDCCL <9>

43

3 3

TV-Out Connector
S-Video

EMI

L7

R152

TV_LUMA<9>

TV_CRMA<9>

TV_COMPS<9>

4 4

A

1 2

R153

1 2

R154

1 2

0_0402_5%

0_0402_5%

0_0402_5%

TVLUMA

TVCRMA

TVCOMPS

R155

75_0402_5%

12

B

12

R156

75_0402_5%

12

R157

75_0402_5%

C244

2

2

270P_0402_50V7K

270P_0402_50V7K

1

1

C245

MBC1608121YZF_0603

1 2

L8
MBC1608121YZF_0603

1 2

L9
MBC1608121YZF_0603

1 2

1

C246

2

270P_0402_50V7K

R158

1 2

0_0805_5%

TVGND

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

LUMA_CL

CRMA_CL

COMPS_CL

1

C247

2

330P_0402_50V7K

2006/02/13 2006/07/26

1

1

2

C249

C248

2

330P_0402_50V7K

Compal Secret Data

Deciphered Date

DC230001300 CONN SUYIN 030107FR007G317ZR 7P S_VIDEO
SUYIN_030107FR007G317ZR_7P

330P_0402_50V7K

JP7

1

1

2

2

3

3

4

4

5

5

6
7

8

6

GND

9

7

GND

SUYIN_030107FR007G317ZR

CONN@

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

LA-3732P

16 40Wednesday, March 14, 2007

E

of

0.2

5

4

3

2

1

LVDS CONN

D D

@

L10 0_0805_5%

1 2

L11

1 2

FBMA-L11-201209-221LMA30T_0805

INVPWR_B+B+

0308_Reserve L10 and install L11.

JP8

INVPWR_B+

+LCDVDD

+3VS

C C

C252680P_0402_50V7K

1

12

2

LVDSBC+<9>

LVDSBC-<9>

LVDSB0+<9>

LVDSB0-<9>

LVDSB1+<9>

C254

C253680P_0402_50V7K

LVDSB1-<9>

LVDSB2+<9>

LVDSB2-<9>

12

680P_0402_50V7K

LVDSBC+
LVDSBC-

LVDSB0+
LVDSB0-

LVDSB1+
LVDSB1-

LVDSB2+
LVDSB2-

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

GND41GND

ACES_88242-4001

CONN@

LVDS connector

SP02000EA00 S W-CONN ACES 88242-4001 40P P1
ACES_88242-4001_40P

+LCDVDD

C250

0.1U_0402_16V4Z

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

1

1

C251

0.1U_0402_16V4Z

2

2

LVDSA2+
LVDSA2-

LVDSA1+
LVDSA1-

LVDSA0+
LVDSA0-

LVDSAC+

LVDSAC-

INVTPWM
DISPLAYOFF#
DAC_BRIG
LCD_CLK
LCD_DAT

680P_0402_50V7K

0308_Install all cap for EMI request.0308_Install all cap for EMI request.

C255

LVDSA2+ <9>
LVDSA2- <9>
LVDSA1+ <9>

LVDSA1- <9>
LVDSA0+ <9>

LVDSA0- <9>

LVDSAC+ <9>
LVDSAC- <9>

1

1

2

2

C256
680P_0402_50V7K

INV_PWM <30>

DAC_BRIG <30>
LCD_CLK <9>
LCD_DATA <9>

2.2K_0402_5%

LCD_CLK
LCD_DATA

R159

+3VS

R160

2.2K_0402_5%

1 2

1 2

R161

100_0402_5%

Q8

1

2

+LCDVDD

12

13

D

S

2N7002_SOT23-3

+5VALW

R163
47K_0402_5%

1 2

2

G

13

D

2

G

S

Q9

C259

0.047U_0402_16V7K

SI2301BDS-T1-E3_SOT23-3

1

C257

4.7U_0805_10V4Z

2

Q7

1 3

D

2

S

G

4.7U_0805_10V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS+LCDVDD

BKOFF#<30>

1

C258

2

2006/02/13 2006/07/26

3

Compal Secret Data

Deciphered Date

ENABLT<9>

2

D8

CH751H-40PT_SOD323-2
D9

CH751H-40PT_SOD323-2

R164

100K_0402_5%

1 2

Title

Size Document Number Rev

Date: Sheet

+3VS

R162

4.7K_0402_5%

1 2

21

21

DISPLAYOFF#

Compal Electronics, Inc.

LCD CONN.

LA-3732P

1

0.2

of

17 40Wednesday, March 14, 2007

B B

2N7002_SOT23-3

R298

ENAVDD<9>

R308

100K_0402_5%

A A

Avoid Panel display garbage after power on.

5

1 2

47K_0402_5%

12

C260

0.1U_0402_16V4Z

5

4

3

2

1

+3VS

1 2

R166 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

12

R167 8.2K_0402_5%

D D

C C

R168 8.2K_0402_5%
R169 8.2K_0402_5%
R170 8.2K_0402_5%
R171 8.2K_0402_5%
R172 8.2K_0402_5%
R173 8.2K_0402_5%

+3VS

R175 8.2K_0402_5%
R176 8.2K_0402_5%
R177 8.2K_0402_5%
R179 8.2K_0402_5%
R180 8.2K_0402_5%
R181 8.2K_0402_5%
R182 8.2K_0402_5%
R183 8.2K_0402_5%
R184 8.2K_0402_5%
R185 8.2K_0402_5%
R187 8.2K_0402_5%
R188 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

PCI_AD[0..31]<23>

PCI_PIRQA#<23>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15 PCI_PAR
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U7B

D20

AD0

E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15

B6

C11

A9
D11
B12
C12
D10

C7
F13
E11
E13
E12

D8

A6
E8

D6

A3

F9
B5

C5
A10

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

ICH8M REV 1.0

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2

PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCI_REQ0#

A4

PCI_GNT0#

D7

PCI_REQ1#

E18
C18

PCI_REQ2#

B19
F18

PCI_REQ3#

A11

PCI_GNT3#

C10

PCI_CBE#0

C17

PCI_CBE#1

E15

PCI_CBE#2

F16

PCI_CBE#3

E17

PCI_IRDY#

C8
D9

PCI_PCIRST#

G6

PCI_DEVSEL#

D16

PCI_PERR#

A7

PCI_PLOCK#

B7

PCI_SERR#

F10

PCI_STOP#

C16

PCI_TRDY#

C9

PCI_FRAME#

A17

PCI_PLTRST#

AG24

CLK_PCI_ICH

B10

PCI_PME#

G7

PCI_PIRQE#

F8

PCI_PIRQF# CLK_PCI_ICH

G11

PCI_PIRQG#

F12

PCI_PIRQH#

B3

PCI_REQ0# <23>
PCI_GNT0# <23>

T23

PCI_CBE#0 <23>
PCI_CBE#1 <23>
PCI_CBE#2 <23>
PCI_CBE#3 <23>

PCI_IRDY# <23>
PCI_PAR <23>

PCI_DEVSEL# <23>
PCI_PERR# <23>

PCI_SERR# <23>
PCI_STOP# <23>
PCI_TRDY# <23>
PCI_FRAME# <23>

CLK_PCI_ICH <15>
PCI_PME# <23,30>

R174
0_0402_5%

R178
0_0402_5%

Place closely pin B10

R186

10_0402_5% @

1 2
1

C261

8.2P_0402_50V@

2

12

12

PCI_RST#

PLT_RST#

PCI_GNT0#

12

R165

@

1K_0402_5%

PCI_RST# <23,29,30>

PLT_RST# <7,22>

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

1

0

1

Boot BIOS Location

SPI1

PCI

LPC

*

A16 swap override Strap

Low= A16 swap override Enble

*

PCI_GNT3# High= Default

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

ICH8(1/4)-PCI/INT

LA-3732P

18 40Wednesday, March 14, 2007

1

0.2

of

5

4

3

2

1

+RTCVCC

R189 330K_0402_1%

LAN100_SLP

1 2

R191 1M_0402_5%

SM_INTRUDER#

1 2

R193 330K_0402_1%

ICH_INTVRMEN

1 2

C262

1

2

R197

1 2

10M_0402_5%

1

IN

2

D D

15P_0402_50V8J

C C

B B

R195

@

0_0402_5%

ICH_RTCX1

ICH_RTCX2

1

2

Y2

4

OUT

32.768KHZ_12.5P_1TJS125BJ2A251

NC3NC

0205_Change Crystal type.

1 2

1 2

C263
15P_0402_50V8J

R192

@

0_0402_5%

ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

ICH8M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP Low = Internal VR Disabled

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

High = Internal VR Enabled(Default)

R199

+RTCVCC

1 2

20K_0402_5%

1U_0603_10V4Z

C264

CLRP3

2

SHORT PADS

1 2

1

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#
SM_INTRUDER#
ICH_INTVRMEN

LAN100_SLP

0205_Remove R401.

R202 24.9_0402_1%

R203 33_0402_5%
R205 33_0402_5%

R206 33_0402_5%

R208 33_0402_5%

SATA_LED#

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0
SATA_TXP0

CLK_PCIE_SATA#<15>
CLK_PCIE_SATA<15>

1 2

3900P_0402_50V7K

C265

1 2

C266

1 2

3900P_0402_50V7K

1 2
1 2

1 2

1 2

CLK_PCIE_SATA#
CLK_PCIE_SATA

1 2

24.9_0402_1%

Within 500 mils

SATA_TXN0_C
SATA_TXP0_C

R211

+1.5VS

ACZ_BITCLK<24>

ACZ_SYNC<24>

ACZ_RST#<24,30>

ACZ_SDIN0<24>

ACZ_SDOUT<24>

SATA_LED#<28>

SATA_RXN0_C<22>
SATA_RXP0_C<22>

SATA_TXN0<22>
SATA_TXP0<22>

GLAN_COMP
HDA_BITCLK

HDA_SYNC
HDARST#
ACZ_SDIN0

HDA_SDOUT

U7A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD/GPIO49

IGNNE#

RCIN#

STPCLK#

THRMTRIP#

IHDA

IDE

SATA

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

INIT#

INTR

SMI#

DD10
DD11
DD12
DD13
DD14
DD15

NMI

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

DA0
DA1
DA2

E5
F5
G8
F6

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23
AG28

AA24
AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ0#

GATEA20
H_A20M#

H_DPSLP#
H_FERR#

H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR
KB_RST#

H_NMI
H_SMI#

H_STPCLK#
THRMTRIP_ICH#

IDE_HDD0
IDE_HDD1
IDE_HDD2
IDE_HDD3
IDE_HDD4
IDE_HDD5
IDE_HDD6
IDE_HDD7
IDE_HDD8
IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15

IDE_HDA0
IDE_HDA1
IDE_HDA2

IDE_HDCS1#
IDE_HDCS3#

IDE_HDIOR#

IDE_HDIOW#

IDE_HDACK#

IDE_HIRQ

IDE_HIORDY

IDE_HDREQ

T25 PAD

LPC_AD[0..3] <22,29,30>

LPC_FRAME# <22,29,30>
LPC_DRQ#0 <30>

GATEA20 <30>
H_A20M# <4>

12

R201 0_0402_5%

H_DPSLP# <5>

H_FERR# <4>
H_PWRGOOD <5>
H_IGNNE# <4>
H_INIT# <4>

H_INTR <4>

KB_RST# <30>

H_NMI <4>
H_SMI# <4>

H_STPCLK# <4>
1 2

IDE_HDD[0..15] <22>

IDE_HDA0 <22>
IDE_HDA1 <22>
IDE_HDA2 <22>

IDE_HDCS1# <22>
IDE_HDCS3# <22>

IDE_HDIOR# <22>

IDE_HDIOW# <22>

IDE_HDACK# <22>

IDE_ HIRQ <22>
IDE_HIORDY <22>
IDE_HDREQ <22>

H_DPRSTP#H_DPRSTP_R#

R207 24_0402_1%

GATEA20

KB_RST#

H_FERR#

H_DPRSTP#

H_DPSLP#

H_DPRSTP# <5,7,37>

within 2" from R1557

+VCCP

12

R204
56_0402_5%

H_THERMTRIP# <4,7>

placed within 2" from ICH8M

IDE_HIORDY
IDE_HIRQ

R209 4.7K_0402_5%
R210 8.2K_0402_5%

0226_Change RTC battery and connector.

BATT1

10K_0402_5%

10K_0402_5%

1 2
1 2

R190

R194

R196

56_0402_5%

R198

@

56_0402_5%

R200

@

56_0402_5%

+3VS

12

12

+VCCP

12

12

12

+3VS

45@

CR2032 RTC BATTERY

+3VL+RTCVCC

BATT1.1

R213

1 2

1K_0402_5%

W=20mils

JBATT1

1

1

2

2

3

G1

4

G2

ACES_85204-02001

CONN@

Compal Electronics, Inc.

ICH8(2/4)_LAN,HD,IDE,LPC

LA-3732P

1

0.2

of

19 40Wednesday, March 14, 2007

1

DAN202U_SC70

D10

2
3

W=20mils

Title

Size Document Number Rev

Custom

Date: Sheet

W=20mils

R212

1 2

W=20mils

0_0402_5%

2

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

C267
1U_0603_10V4Z

1

2

5

LINKALERT#

+3VALW

D D

+3VS

+3VS

C C

+3VS

1 2

R214 10K_0402_5%

R215 8.2K_0402_5%

1 2

R218 1K_0402_5%

1 2

R221 10K_0402_5%

1 2

R223 1K_0402_5%

R224 10K_0402_5%

R225 10K_0402_5%

1 2

R228 10K_0402_5%

1 2

R230 10K_0402_5%

1 2

R231 8.2K_0402_5%@

1 2

R232 8.2K_0402_5%

1 2

R235 8.2K_0402_5%@

1 2

R394 8.2K_0402_5%

1 2

R236 10K_0402_5%@

1 2

R237 10K_0402_5%@

1 2

R239 10K_0402_5%

1 2

R241 10K_0402_5%

1 2

R242 8.2K_0402_5%

1 2

SB_SPKR

R244 8.2K_0402_5%

1 2

R248 10K_0402_5% @

ICH_LOW_BAT#

12

ICH_PCIE_W AKE#

ICH_RI#

XDP_DBRESET#

ME_EC_DATA1

12

ME_EC_CLK1

12

GPIO38

GPIO39

GPIO18

GPIO22

GPIO20

CLKRUN#

OCP#

MCH_ICH_SYNC#

SIRQ

CLKSATAREQ#

IDE_RESET#

PM_BMBUSY# ICH_RSVD

H_STP_PCI#<15>
H_STP_CPU#<15>

+3VS

R226

@

10K_0402_5%

ICH_SMBCLK<15,22>
ICH_SMBDATA<15,22>

R227

@

10K_0402_5%

1 2

1 2

R395 100K_0402_5%

low-->default
High -->No boot

WLAN

B B

USB_OC#3

1 2

R392 10K_0402_5%

USB_OC#4

1 2

R385 10K_0402_5%

USB_OC#5

1 2

R386 10K_0402_5%

USB_OC#6

1 2

R387 10K_0402_5%

USB_OC#7

1 2

R388 10K_0402_5%

1 2

R389 10K_0402_5%

USB_OC#9

1 2

R390 10K_0402_5%

USB_OC#2

1 2

R391 10K_0402_5%

A A

USB_OC#0

1 2

R380 10K_0402_5%

1 2

R381 0_0402_5%

5

+3VALW

USB_OC#1

4

+3VALW

12

R216

2.2K_0402_5%

XDP_DBRESET#<4>
PM_BMBUSY#<7>

EC_LID_OUT#<30>

R229 0_0402_5%

12

PCIE_RXN1<22>

PCIE_RXP1<22>
PCIE_TXN1<22>
PCIE_TXP1<22>

12

ICH_PCIE_WAKE#<22>

SIRQ<30>

THERM_SCI#<30>

VGATE<15,37>

OCP#<4>

EC_SMI#<30>
EC_SCI#<30>

CLKSATAREQ#<15>

IDE_RESET#<22>

SB_SPKR<24>

MCH_ICH_SYNC#<7>

R246 1K_0402_5%@

4

3

12

R217

2.2K_0402_5%

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1

ICH_RI#
SUS_STAT#

T26PAD

XDP_DBRESET#
PM_BMBUSY#
EC_LID_OUT#
H_STP_PCI#

R_STP_CPU#
CLKRUN# DPRSLPVR
ICH_PCIE_W AKE#

SIRQ
THERM_SCI#

VGATE
SST_CTL

T29PAD

OCP#

EC_SMI#
EC_SCI#

GPIO18
GPIO20
GPIO22

CLKSATAREQ#

SB_SPKR
MCH_ICH_SYNC#

12

R250

@

USB_OC#0<27>
USB_OC#2<27>

GPIO27

GPIO38
GPIO39

IDE_RESET#

+3VALW

1 2

T31PAD

10K_0402_5%

AD19
AG21
AC17
AE19

AF17

AD15
AG12
AG22
AE20

AG18
AH11
AE17

AF12
AC13

AE16
AC19

AH12
AE11
AG10
AH25
AD16
AG13

AD10

C2720.1U_0402_16V4Z

12

C2730.1U_0402_16V4Z

12

T40PAD
T41PAD
T42PAD

T43PAD

U7C

AJ26

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

RI#

F4

SUS_STAT#/LPCPD#
SYS_RESET#

BMBUSY#/GPIO0
SMBALERT#/GPIO11
STP_PCI#/GPIO15

STP_CPU#/GPIO25
CLKRUN#/GPIO32
WAKE#

SERIRQ
THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7
GPIO8
GPIO12

AG8

TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8M REV 1.0

AJ19
AG16
AG15
AE15
AF15
AG17
AD12

AJ18
AD14
AH18

P27
P26
N29
N28

M27
M26

L29
L28

K27
K26

J29
J28

H27
H26
G29
G28

F27
F26
E29
E28

D27
D26
C29
C28

C23
B23
E22

D23
F21

U7D

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

ICH8M REV 1.0

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

SPICLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

USB_OC#0
USB_OC#1USB_OC#8
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SMB

SYS

GPIO

GPIO

MISC

3

SATA

GPIO

Clocks

Power MGTController Link

USB

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW#
PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB26

DMI2RXN

AB25

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

PCI-Express

DMI_ZCOMP

DMI_IRCOMP

SPI

T26

DMI_CLKN

T25

DMI_CLKP

Y23
Y24

Direct Media Interface

G3

USBP0N

G2

USBP0P

H5

USBP1N

H4

USBP1P

H2

USBP2N

H1

USBP2P

J3

USBP3N

J2

USBP3P

K5

USBP4N

K4

USBP4P

K2

USBP5N

K1

USBP5P

L3

USBP6N

L2

USBP6P

M5

USBP7N

M4

USBP7P

M2

USBP8N

M1

USBP8P

N3

USBP9N

N2

USBP9P

F2

USBRBIAS#

F3

USBRBIAS

2006/02/13 2006/03/10

AJ12
AJ10
AF11
AG11

CLK_14M_ICH

AG9

CLK_48M_ICH

G5

ICH_SUSCLK

D3

SLP_S3#

AG23

SLP_S4#

AF21

SLP_S5#

AD18

S4_STATE#

AH27

PM_PWROK

AE23
AJ14

ICH_LOW_BAT#

AE21

PWRBTN_OUT#

C2
AH20

EC_RMRST#

AG27

CK_PWRGD

E1

M_PWROK

E3

PM_SLP_M#

AJ25

CL_CLK0

F23
AE18

CL_DATA0

F22
AF19

CL_VREF0_ICH

D24

CL_VREF1_ICH

AH23
AJ23

WL_ON#

AJ27
AJ24
AF22
AG19

12

R396
100K_0402_5%

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

USBRBIAS

Within 500 mils

Compal Secret Data

Deciphered Date

2

T45 PAD
T46 PAD
T47 PAD
T48 PAD

CLK_14M_ICH <15>
CLK_48M_ICH <15>

T27 PAD

SLP_S3# <30>
SLP_S4# <30>
SLP_S5# <30>

T28 PAD

PM_PWROK <7,30>

DPRSLPVR <7,37>

1 2

R398 100K_0402_5%@

1 2

0_0402_5%

1 2

100_0402_5%

T30 PAD

1 2

DMI_RXN0 <7>

DMI_RXP0 <7>
DMI_TXN0 <7>
DMI_TXP0 <7>

DMI_RXP1 <7>
DMI_TXN1 <7>
DMI_TXP1 <7>

DMI_RXN2 <7>

DMI_RXP2 <7>
DMI_TXN2 <7>
DMI_TXP2 <7>

DMI_RXN3 <7>

DMI_RXP3 <7>
DMI_TXN3 <7>
DMI_TXP3 <7>

CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>

R249 24.9_0402_1%

1 2

PWRBTN_OUT# <30>

R234

CK_PWRGD <15>
M_PWROK <7,30>

CL_CLK0 <7>

CL_DATA0 <7>

CL_RST# <7>

WL_ON# <22>

+3VALW

DMI_RXN1 <7>

Within 500 mils

USB20_N0 <27>
USB20_P0 <27>
USB20_N1 <27>
USB20_P1 <27>
USB20_N2 <27>
USB20_P2 <27>

USB20_N4 <27>

USB20_P4 <27>

EC_RSMRST#

+1.5VS

To USB/B.
To USB/B.
To MB.

To Card reader/B.

R233

R24510K_0402_5%

0228_Connect U S B 4 to Card reader/B.

1 2

R251 22.6_0402_1%

2

1

Place closely pin AG9Place closely pin G5

12

R219

10_0402_5%@

1

C268

4.7P_0402_50V8C@

2

12

R220

1

C269

2

0205 Change to connect to GND.

EC_RSMRST# <30>

R238 3.24K_0402_1%

1 2

12

1

C270

R240

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

1

C271

2

Title

Size Document Number Rev

Custom

LA-3732P

Date: Sheet

+3VS

453_0402_1%

R243 3.24K_0402_1%

1 2

R247
453_0402_1%

+3VALW

Compal Electronics, Inc.

ICH8(3/4)_PM,USB,GPIO

1

CLK_14M_ICHCLK_48M_ICH

10_0402_5%@

4.7P_0402_50V8C@

0.2

of

20 40Wednesday, March 14, 2007

5

D D

R254

100_0402_5%

R255

C C

10_0402_5%

+1.5VS

B B

0.1U_0402_16V4Z

A A

+1.5VS

+5VS +3VS

12

D11

CH751H-40PT_SOD323-2

+3VALW+5VALW

12

D12

CH751H-40PT_SOD323-2

1 2

CHB1608U301_0603

C307

R252 CHB1608U301_0603

1 2

21

20 mils

ICH_V5REF_RUN

1

C284

0.1U_0402_16V4Z

2

21

ICH_V5REF_SUS

20 mils

1

C291

0.1U_0402_16V4Z

2

R256

C296

+1.5VS

C304

0.1U_0402_16V4Z

+3VS

1

1 2

+1.5VS

2

5

+RTCVCC

1

C274

2

0.1U_0402_16V4Z

40 mils

1

C278

220U_6.3V_M

+

C279

2

10U_0805_10V4Z

1

1

C297

2

2

1U_0603_10V4Z

10U_0805_10V4Z

+1.5VS

1

0.1U_0402_16V4Z

2

R257 CHB1608U301_0603

1

C308

C309

2

10U_0805_10V4Z

20 mils

1

C275

2

0.1U_0402_16V4Z

10U_0805_10V4Z

1

1

C280

2

2

ICH_VCCSATAPLL

1U_0603_10V4Z

+1.5VS

1U_0603_10V4Z

1

C305

2

T36
T37

ICH_VCCGLANPLL

1

+1.5VS

2

4.7U_0805_10V4Z

+3VS

2.2U_0805_16V4Z

ICH_V5REF_RUN

ICH_V5REF_SUS

ICH_VCC1_5

1

C281

2

2.2U_0805_16V4Z

VCC1_5_A=1120mA

+1.5VS

1

C298

2

VCC1_5_A=1120mA

1

C300

2

VCC1_5_A=1120mA

VCC1_5_A=1120mA

+1.5VS

VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2

R258

@

ICH_VCCGLAN1_5

1 2

CHB1608U301_0603

1

C310

@

2

ICH_VCCGLAN3_3

1 2

R2590_0402_5%@

770mA

50mA

10mA

12mA

27mA
74mA

1mA

6mA

3mA

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AG7

AC10

W23

A16

T7

G4

D28
D29
E25
E26
E27

F24

F25
G24
H23
H24

J23

J24
K24
K25

L23

L24

L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27

T23

T24

T27

T28

T29
U24
U25
V23
V24
V25

Y25

AJ6
AE7

AF7
AH7

AJ7
AC1

AC2
AC3
AC4
AC5

AC9
AA5

AA6
G12

G17

H7

AC7
AD7

D1

F1
L6

L7
M6
M7

F17

G18

F19

G20
A24
A26

A27
B26
B27
B28

B25

4

U7F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

4

CORE

VCCA3GP ATXARX

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCCCL3_3[1]
VCCCL3_3[2]

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCCL1_05

VCCCL1_5

3

+VCCP

1170mA

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

VCC3_3=310mA

AA3
U7
V7
W1
W6
W7
Y7

VCC3_3=310mA

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11
J6

AF20

VCCSUS1_5_ICH_1

AC16

VCCSUS1_5_ICH_2

J7

0.1U_0402_16V4Z

C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

VCCCL1_05_ICH

G22
A22

12mA

F20
G21

0.1U_0402_16V4Z

1

C276

26mA
40mA

14mA

VCC3_3=310mA
VCC3_3=310mA
VCC3_3=310mA

+3VS

0.1U_0402_16V4Z
C292

0.1U_0402_16V4Z

0.1U_0402_16V4Z

24mA
4mA

T32

T33
T34
T35

1U_0603_10V4Z

+3VS

1

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C277 0.1U_0402_16V4Z

2

2

ICH_VCCDMIPLL

1

C282

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

1

+3VS

2

1

2

0.1U_0402_16V4Z

1

1

C293

C294

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C301

+3VALW

1

1

C302

2

2

+3VALW

VCCSUS3_3=141mA

1

C306

4.7U_0805_10V4Z

2

T38

C311

@

3

R253 CHB1608U301_0603

1 2

1

C283

2

10U_0805_10V4Z

+1.25VS

10U_0805_10V4Z

C285

1

2

0.1U_0402_16V4Z

+3VS

(SATA)

C290

+3VS

1

C295

2

+3VALW

1

2

VCCSUS3_3=141mA

0.1U_0402_16V4Z

C303

2006/02/13 2006/03/10

+1.5VS

+3VS

(DMI)

1

C289

2

1

C299

2

Compal Secret Data

+VCCP

4.7U_0805_10V4Z

+3VS

Deciphered Date

0.1U_0402_16V4Z

C286

1

1

2

2

C287

2

0.1U_0402_16V4Z
C288

1

2

2

U7E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

ICH8M REV 1.0

Title

Size Document Number Rev

Custom

LA-3732P

Date: Sheet

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

Compal Electronics, Inc.

ICH8(4/4)_POWER&GND

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

1

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

1

0.2

of

21 40Wednesday, March 14, 2007

A

B

C

D

E

F

G

+5VS

H

Placea caps. near ODD CONN.

HDD Connector CD-ROM Connector

+5VS

C317

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

1

C318

C319

2

2

0.1U_0402_16V4Z

1 1

1

C320

2

0.1U_0402_16V4Z

Pleace near HD CONN (JP23)

+3VS +3VS_HDD

R2630_0805_5%@

12

0.1U_0402_16V4Z

1

1

C323

@

@

2

2

1000P_0402_50V7K

C324

1U_0603_10V4Z

1

1

+

C325

@

C322

@

2

2

330U_V_2.5VK_R9

Pleace near HD CONN

DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA
SUYIN_127043FR022G204ZL_22P_NR

2 2

JP9

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

23

GND

24

GND

CONN@

SUYIN_127043FR022G204ZL_NR

0.01U_0402_16V7K

SATA_RXN0

SATA_RXP0

0.01U_0402_16V7K

Near CONN side.

+3VS_HDD

+5VS

SATA_TXP0
SATA_TXN0

SATA_RXN0_C

C316

12

SATA_RXP0_C

C321

12

SATA_TXP0 <19>

SATA_TXN0 <19>

SATA_RXN0_C <19>

SATA_RXP0_C <19>

IDE_RESET#<20>

PLT_RST#<7,18>

+5VS

IDE_HDD[0..15] <19>

R260 0_0402_5%@

1 2

R261 33_0402_5%

1 2

IDE_HDIOW#<19>
IDE_HIORDY<19>

IDE_HIRQ<19>
IDE_HDA1<19>
IDE_HDA0<19>

IDE_HDCS1#<19>

12

R264 10K_0402_5%

+5VS

IDE_HDD7
IDE_HDD6
IDE_HDD5
IDE_HDD4
IDE_HDD3
IDE_HDD2
IDE_HDD1
IDE_HDD0

IDE_HDIOW#
IDE_HIORDY

IDE_HIRQ
IDE_HDA1
IDE_HDA0
IDE_HDCS1#
IDE_ACT#

SEC_CSEL

12

R265
470_0402_5%

JP10

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49
G53G

SUYIN_800194MR050S102ZU

CONN@

DC030001P00 WAFER OCTEK CDR-50JD1 50P P0.822P SATA
OCTEK_CDR-50JD1_50P

0213_Change C onnector type.

2

2

4

4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

IDE_HDD8

6

IDE_HDD9

8

IDE_HDD10

10

IDE_HDD11

12

IDE_HDD12

14

IDE_HDD13

16

IDE_HDD14

18

IDE_HDD15

20

IDE_HDREQ

22

IDE_HDIOR#

24
26

IDE_HDACK#

28
30

PDIAG#

32
34
36
38
40
42
44
46
48
50

54

R262 100K_0402_5%

1 2

IDE_HDA2
IDE_HDCS3#

IDE_HDREQ <19>

IDE_HDIOR# <19>

IDE_HDACK# <19>

IDE_HDA2 <19>

IDE_HDCS3# <19>

+5VS

+5VS

C312

0.1U_0402_16V4Z

1

C313

2

10U_0805_10V4Z

1U_0603_10V4Z

1

1

C314

2

1

C315
10U_0805_10V4Z

2

2

Mini-Express Card---WLAN

+3VS_MINI +1.5VS_MINI

C326

1

0.01U_0402_16V7K

3 3

ICH_PCIE_WAKE#<20>

MINI_CLKREQ#<15>

CLK_PCIE_MCARD#<15>

CLK_PCIE_MCARD<15>

CLK_DEBUG_PORT<15,29,30>

PCIE_RXN1<20>
PCIE_RXP1<20>

PCIE_TXN1<20>
PCIE_TXP1<20>

4 4

0.1U_0402_16V4Z

2

1

C327

2

1 2

R266 0_0402_5%

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

PLT_RST#

R273 0_0402_5%

PCIE_RXP1

R274 0_0402_5%

PCIE_TXN1
PCIE_TXP1

4.7U_0805_10V4Z

ICH_PCIE_W AKE#

R272 0_0402_5% DEBUG@

1 2
1 2

Mini Card STANDOFF

H19

H20

HOLEA

HOLEA

1

1

A

EC029000100 MINICARD_STANDOFF_8

B

C

C328

MINI_CLKREQ#_MC

1 2

PCIE_C_RXN1PCIE_RXN1
PCIE_C_RXP1

1

0.01U_0402_16V7K

2

1

C329

0.1U_0402_16V4Z

2

JP11

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

GND2

FOX_AS0B226-S40N-7F~D

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1

C330

2

+1.5VS_MINI

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

1

C331

4.7U_0805_10V4Z

2

+3VS_MINI

FBMA-L11-201209-102LMA10T

1 2

L13 FBMA-L11-201209-102LMA10T

R267 0_0402_5% DEBUG@

1 2

R268 0_0402_5% DEBUG@

1 2

R269 0_0402_5% DEBUG@

1 2

R270 0_0402_5% DEBUG@

1 2

R271 0_0402_5% DEBUG@

1 2

WL_ON#
PLT_RST#

WL_LED#

L12

1 2

SP01000P700 S H-CONN ACES 88914-5204 52P P0.8

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2006/02/13 2007/08/29

E

Compal Secret Data

C332

0.1U_0402_16V4Z@

WL_ON# <20>

+3VALW

ICH_SMBCLK <15,20>
ICH_SMBDATA <15,20>

WL_LED# <28>

Deciphered Date

+3VALW

+3VS

1

2

+1.5VS

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

F

LPC_FRAME# <19,29,30>

LPC_AD[0..3] <19,29,30>

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

HDD/ODD/Mini Card CONN.

LA-3732P

G

0.2

of

22 40Wednesday, March 14, 2007

H

5

4

3

2

1

+3VALW

R275

ACTIVITY#

D D

1 2

PCI_AD[0..31]

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

LAN_IDSEL

PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#

PCI_PERR#
PCI_SERR#

PCI_REQ0#
PCI_GNT0#

PCI_PIRQA#
PCI_PME#
PCI_RST#
CLK_PCI_LAN

1 2

R289
10K_0402_5%

U8

104

AD0

103

AD1

102

AD2

98

AD3

97

AD4

96

AD5

95

AD6

93

AD7

90

AD8

89

AD9

87

AD10

86

AD11

85

AD12

83

AD13

82

AD14

79

AD15

59

AD16

58

AD17

57

AD18

55

AD19

53

AD20

50

AD21

49

AD22

47

AD23

43

AD24

42

AD25

40

AD26

39

AD27

37

AD28

36

AD29

34

AD30

33

AD31

92

C/BE#0

77

C/BE#1

60

C/BE#2

44

C/BE#3

46

IDSEL

76

PAR

61

FRAME#

63

IRDY#

67

TRDY#

68

DEVSEL#

69

STOP#

70

PERR#

75

SERR#

30

REQ#

29

GNT#

25

INTA#

31

PME#

27

RST#

28

CLK

65

CLKRUN#

4

GND/VSS

17

GND/VSS

128

GND/VSS

21

GND/VSSPST

38

GND/VSSPST

51

GND/VSSPST

66

GND/VSSPST

81

GND/VSSPST

91

GND/VSSPST

101

GND/VSSPST

119

GND/VSSPST

35

GND

52

GND

80

GND

100

GND

RTL8100CL_LQFP128

EEDO

AUX/EEDI

EESK
EECS

LED0
LED1
LED2

NC/LED3

TXD+/MDI0+

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

NC/MDI2+

NC/MDI2-

NC/MDI3+

NC/MDI3-

X1
X2

LWAKE

ISOLATE#

RTSET

NC/SMBCLK

NC/SMBDATA

NC/M66EN
NC/AVDDH

NC/HV

PCI I/F

NC/HSDAC+

NC/HG
NC/LG2
NC/LV2

NC/VSS
NC/VSS

NC/GND
NC/GND
NC/GND
NC/GND
NC/GND

LAN I/F

NC/GND

CTRL25

RTT3/CRTL18

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL

NC/AVDDL

VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18

NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18

Power

AVDD25/HSDAC-

LAN_EEDO

108

LAN_EEDI

109

LAN_EECLK

111

LAN_EECS

106

ACTIVITY#_R ACTIVITY#

117
115
114
113

TXD+/MDI0+

1

TXD-/MDI0-

2

RXIN+/MDI1+

5

RXIN-/MDI1-

6
14

15
18
19

LAN_X1

121

LAN_X2

122

R281 1K_0402_5%

105

R282 15K_0402_5%

23

R283 5.6K_0603_1%

127
72
74

88
10

120
11

123
124
126

9
13

22
48
62
73
112
118

8
125
26

41
56
71
84
94
107

3
7
20
16

32
54
78
99

24
45
64
110
116

V_12P

12

1

C359

0.1U_0402_16V4Z

2

4

PCI_AD[0..31]<18>

C C

PCI_CBE#0<18>
PCI_CBE#1<18>
PCI_CBE#2<18>
PCI_CBE#3<18>

PCI_AD17

R285 100_0402_5%

PCI_PAR<18>

PCI_FRAME#<18>

PCI_IRDY#<18>

PCI_TRDY#<18>

PCI_DEVSEL#<18>

PCI_STOP#<18>

PCI_PERR#<18>
PCI_SERR#<18>

PCI_REQ0#<18>

PCI_GNT0#<18>

B B

A A

PCI_PIRQA#<18>

PCI_PME#<18,30>

PCI_RST#<18,29,30>

CLK_PCI_LAN<15>

CLK_PCI_LAN

12

R292

@

10_0402_5%

1

C356

@

10P_0402_50V8J

2

5

1 2

R278 0_0603_5%

1 2

R279 0_0603_5%

1 2
1 2
1 2

CTRL25

1

C343

0.1U_0402_16V4Z

2

1

C349

0.1U_0402_16V4Z

2

1

C352

0.1U_0402_16V4Z

2

R276

3.6K_0402_5%

1 2

+3VALW

Q10

1

R293
0_0402_5%

1 2

+3VA_LAN

U9

4

DO

GND

3

DI

NC

2

SK

NC

1

CS

VCC

AT93C46-10SU-2.7_SO8

Y3
25MHZ_20P_1BG25000CK1A

1 2

+3VS

C340 1U_0603_10V4Z

1 2

2SB1188T100R_SC62-3

2 3

C342 4.7U_0805_10V4Z

1 2

1

C344

0.1U_0402_16V4Z

2

1

C350

0.1U_0402_16V4Z

2

1

C353

0.1U_0402_16V4Z

2

V2.5_LAN

5

1
6
7
8

V2.5_LAN

C333 0.1U_0402_16V4Z

2

LINK_100#LINK_100#_R

C336 27P_0402_50V8J

1 2

C337 27P_0402_50V8J

1 2

1

C345

0.1U_0402_16V4Z

2

1

C351

0.1U_0402_16V4Z

2

1

C354

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW

1 2

C334 680P_0402_50V7K

1 2

C335 680P_0402_50V7K

1

C346

0.1U_0402_16V4Z

2

1

C355

0.1U_0402_16V4Z

2

3

For EMI,
locate close
to LAN chip

TXD+/MDI0+

1 2

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

1

C347

0.1U_0402_16V4Z

2

V2.5_LAN

C339

0.1U_0402_16V4Z

2006/02/13 2007/08/29

U10

TD-8TX-

7

TD+

6

CT

3

CT

2

RD-

1

RD+

NS0013_16P

+3VA_LAN

R288

12

0_0603_5%

Compal Secret Data

Deciphered Date

TX+

RX+

CT

CT

RX-

9
10
11

14
15
16

+3VALW

300_0603_5%

1 2

MDO1-

MDO1+
MDO0-

LINK_100#

MDO0+
MDO0-

MCT1
MDO1+
MDO1-

R277
300_0603_5%

1 2

+3VALW

MDO0+

TIP
RING

close to chip

R286

49.9_0402_1%

TXD+/MDI0+

TXD-/MDI0-

R287

49.9_0402_1%

close to magnetic

R290

RXIN-/MDI1-

49.9_0402_1%

R291

49.9_0402_1%

C357

220P_1808_3KV@

2

1

RXIN+/MDI1+

Footprint can not match part number.

2

JP12

11

Yellow LED+

12

Yellow LED-

8

RX2-

7

RX2+

6

RX1-

5

TX2-

4

TX2+

3

RX1+

2

TX1-

1

TX1+

10

Green LED-

9

Green LED+

RJ45 / LED

13

RJ11_1

14

RJ11_2

RJ11

JM34F2-M5125-7FCON N@

JM34F2*-N5125-7F
JM34F2A-M5125-7F

R280
75_0402_5%

R284
75_0402_5%

0310_Dammy by safty request.

RING
TIP

2

C358

@

1

220P_1808_3KV

RJ45_GNDMCT0

12

12

C341

0.01U_0402_16V7K

12

12

12

C348

0.01U_0402_16V7K

12

12

12

SP020008Y00 S W-CONN ACES 88266-02001 2P P1.25
ACES_88266-02001_2P

JP13

1

1

2

2

3

G1

4

G2

ACES_88266-02001

CONN@

Title

LAN-8100CL

Size Document Number Rev

Date: Sheet

15

SGND1

16

SGND2

C338

12

1000P_1206_2KV7K

RJ11

Compal Electronics, Inc.

LA-3732P

23 40Wednesday, March 14, 2007

1

0.2

of

A

B

C

D

E

0308_Change R294 and R295 from 0 ohm to bead, C363 from 10uF to 680pF, C365 and C368 from 0.1uF to 680p

In order for the modem wake on ring feature to function,
the CODEC must be powered by a rail that is not
removed when the system is in standby.

1

2

680P_0402_50V7K

12

C366

0.1U_0402_16V4Z

ACZ_RST#

EAPD

RCOSC

+3VDD_CODEC

1

2

C367

0.1U_0402_16V4Z@

DIBP_C

DIBN_C

1 1

+3VS

ACZ_BITCLK<19>

R300

47_0402_5%

C374

2 2

33P_0402_50V8K

0216_Change value.

R294

ACZ_RST#<19,30>

ACZ_SYNC<19>

ACZ_SDIN0<19>
ACZ_SDOUT<19>

R302
0_0402_5%

1 2

+3VDD_CODEC

12

C363

680P_0402_50V7K

DIB_P<25>

DIB_N<25>

@

1 2

1

1

C365

2

2

C364

1U_0603_10V4Z

R299 33_0402_5%

1 2

R301 0_0402_5%

1 2

R305 0_0402_5%

1 2

C373
1U_0603_10V4Z

1 2

R306

5.1K_0402_5%

T39

R311 237K_0402_1%

MBV2012301YZF_0805

12

1

2

SB_SPKR MONO_IN1 MONO_INR

AUDIO CODEC

1

2

U12

10

RESET#

5

BIT_CLK

9

SYNC

7

SDI

4

SDO

44

DIBP

43

DIBN

11

PCBEEP

48

SPDIF

47

EAPD

1

NC_1

2

NC_2

16

NC_16

41

RCOSC

3

VDDIO

VSSIO_42

42

CODEC POWER

For Layout:

Place decoupling caps near the
power pins of SmartAMC
device.

+3VAMP_CODEC

1

1

2

2

C368

C369

0.1U_0402_16V4Z

680P_0402_50V7K

8

45

20

31

DVDD

DVDDM

AVDD_20

AVDD_31

PORT-A_BIAS_L

PORT-A_BIAS_R

PORT-B_BIAS_L

PORT-B_BIAS_R

DVSS

AVSS_25

VSSIO_46

AVSS_12

6

25

46

12

37

AVDDHP

MIC_BIAS_L

MIC_BIAS_R

MIC_L

MIC_R

LINEOUT_L

LINEOUT_R

PORT-A_L

PORT-A_R

PORT-B_L

PORT-B_R

CD_L

CD_GND

CD_R

SENSE

VREF_HI
VREF_LO
VC_REFA

AVSSHP

AVSS_32

CX20549-12Z_LQFP48_9X9

40

32

29
30
21
22

35
36

33
34
38
39

14
15
23
24

17
18
19

13

26
27
28

SENSE

For Vista

VREF_HI
VREF_LO
VC_REFA

MBV2012301YZF_0805

1

2

1U_0603_10V4Z

C370

+CODEC_REFF_INR

MIC_INL
MIC_INR

LINE_OUTL
LINE_OUTR

HP_OUTL
HP_OUTR

+CODEC_REFF_EXTL
+CODEC_REFF_EXTR

MIC_EXTL
MIC_EXTR

1 2

R307 20K_0402_1%

1 2

R309 5.1K_0402_1%

1 2

R310 5.1K_0402_1%

1 2

R337 10K_0402_1%

1

2

R295

12

C371 10U_0805_10V4Z

1 2

C372 10U_0805_10V4Z

1 2

LINE_OUTL <26>
LINE_OUTR <26>

HP_OUTL <26>
HP_OUTR <26>

C375 10U_0805_10V4Z

1 2

C376 10U_0805_10V4Z

1 2

1 2

C377 1U_0603_10V4Z

C378
1U_0603_10V4Z

+VDDA_CODEC

+CODEC_REFF_INR

+CODEC_REFF_EXTR

HP_DET# <26>

EXTMIC_DET# <26>

R296

2.2K_0402_5%

R303

2.2K_0402_5%

+3VAMP_CODEC

12

+CODEC_REFF_EXTL

12

12

R304

2.2K_0402_5%

0208_Change SLP_S3# to SUSP#.

MIC_IN_R <26>

MIC_EXT_L <26>
MIC_EXT_R <26>SB_SPKR<20>

0212_Change to +5VALW.

W=40Mil

+5VALW

1 2

C360 0.1U_0402_16V4Z

SUSP#<30,31,33,35,36>

U11

1

VIN

2

GND
SHDN#3BP

APE8805A-33Y5P_SOT23-5

5

OUT

4

0.1U_0402_16V4Z

C362

+VDDA_CODEC

1

C361

0.1U_0402_16V4Z

2

1

2

(3.33V)
250mA

3 3

4 4

DIGITAL ANALOG

C379

0.1U_0402_16V4Z

1 2

C380

0.1U_0402_16V4Z

1 2

C381

0.1U_0402_16V4Z

1 2

C382

0_0402_5%

1 2

C383

0.1U_0402_16V4Z

1 2

R312
0_1206_5%

1 2

R313

0_1206_5%

1 2

GNDAGND

GNDA <26>

HP_DET#

0(LOW)
0(LOW)

NC
NC NC

MIC_DET

0(LOW)

NC

0(LOW)

PORT-A

LINEOUT

<Earphone OUT>

OFF
OFF

ON
ON Enable

ON
ON

OFF
OFF

MIC

ON

OFF

ON

OFF

EQ

Disable
Disable

Enable

0312_Mount C379~383, R313.

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMOM_codec

LA-3732P

E

0.2

of

24 40Wednesday, March 14, 2007

5

4

3

2

1

MQ2
MMBTA42

MR4
110

5%

Deciphered Date

5335R13-005

MFB2

1
4

ML1

Optional

@

5335R13-005

MFB1

MC10 0.01uF

cap_0603_001uf

MQ1

MMBTA42

QBASE

MR8
56

5%
RES_0603_56@

AGND_LSD

2

2
3

AGND_LSD

BRIDGE_CC

MC8

MR9
280

RES_1206_280

MQ3

MMBTA42

MR11

3.01

res_0402_301

MR7

9.1

res_1206_91

MU1

DIBN

PWR+

MC3

0.1uF

cap_0402_01uf

DIBP

DVdd

CX20548

12

TEST

16

DIBN

15

PWR

2

AVDD

14

DIBP

1

DVDD

MC2

0.1uF

cap_0402_01uf

VC

3

VC_LSD

AGND_LSD

MR3 6.81M

RAC1

4

RAC

MR1 6.81M

TAC1

5

TAC

EIC

MC11 0.1uF

11

EIC

R810 and C810 must be placed near pin 6 (RXI)
and there should be no vias on the(RXI)net.

MR2

RXI

6

RXI

EIO

EIF

TXO

TXF

GPIO

EP

17

3

237K

10

EIF

9

TXO

8

TXF

7
13

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D D

DIB_P<24>

C C

B B

DIB_N<24>

MC12

GND

150pF

MJ4@

2
1

MJ5@

1
2

GND

DIBN_HS
DIBP_HS

GND

CAP_0402_150PF

MODEM-SMAR
MC13
150pF

CAP_0402_150PF

MT1

2 3

1

MC6
47P_0402_50V8J

4

CAP_0402_47PF

MC5

0.1uF

cap_0402_01uf

MC4

0.1uF

cap_0402_01uf

AVdd

AGND_LSD

AGND_LSD

Revision History

Description

Initial Release

0

No changes to schematic. PCB updated to -003.

1

Updated footprints and corrected via spacing errors.

A A

Changed MC8 and MC9 pads. No schematic changes.

2

PCB updated to -005.

3

Added MR11 and MR12. PCB updated to -007.

4

Added MR13. PCB updated to -009.

4.01

AVL update only.

5

DateREV

April 26, 2005

August 18, 2005

November 3, 2005

November 18, 2005

January 3, 2006

April 20, 2006

4

RAC1_RING

res_0805_681m

TAC1_TIP TIP_1

cap_0402_01uf

AGND_LSD

RX1_1

MR13 100_0402_5%

RES_0402_100

MMBD3004S

MBR1

AGND_LSD

MBR2

MMBD3004S

MC1 0.047uF

100.0V

2006/02/13 2007/07/26

Compal Secret Data

RING_1

2

LA-3732P

1

MJ2

@

2
1

MJ1

@

2
1

MJ3

@

1

MRV1

MC7

MC9

470 pF470 pF

Omit

@

MR5
280

RES_1206_280

Note: MC8 and MC9 can be optionally
populated here or behind the RJ-11
connector.

GND

MR10

MR6

280

280

RES_1206_280

RES_1206_280

BRIDGE_CC2

MQ4
MMBTA42

MR12

3.01

res_0402_301

Title

Size D o c um ent Number R ev

Date: Sheet

Compal Electronics, Inc.

AMOM-CX20548

0.2

of

25 40Wednesday, March 14, 2007

A

1 1

C391 0.47U_0603_10V7K

1 2

C393 0.47U_0603_10V7K

LINE_OUTR<24>

LINE_OUTL<24>

2 2

3 3

1 2

C396 0.47U_0603_10V7K

1 2

EC_MUTE#<30>

C395 0.47U_0603_10V7K

1 2

LINE_C_OUTR

LINE_C_OUTL

EC_MUTE#

B

10U_0805_10V4Z

15

6

GND5

21

16

VDD

PVDD1

PVDD2

BYPASS

GND41GND311GND213GND1

20

7

17

9

5

19

U13

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

0310_Change to ENE AMP.

0.1U_0402_16V4Z

1

C384

C385

2

2

GAIN0

3

GAIN1

SPKR+

18

ROUT+

SPKR-

14

ROUT-

SPKL+

4

LOUT+

SPKL-

8

LOUT-

12

NC

10

2

1

P3017THF D0 TSSOP 20P

EC_MUTE#

R314
0_1206_5%

1 2

1

1

C386

2

2

0.1U_0402_16V4Z

100K_0402_5%

100K_0402_5%

Keep 10 mil width

C397

0.47U_0603_10V7K

2

@

G

C

+5VS+5VAMP

R315

R318

B+

12

R323
330K_0402_5%

13

D

S

10 dB

12

12

Q12
2N7002_SOT23-3

12

@

100K_0402_5%

12

R319
100K_0402_5%

B+

12

R324
330K_0402_5%

+5VS

R316

D

SP02000D000 S W-CONN ACES 85204-04001 4P P1.25

SPKL+
SPKL­SPKR+
SPKR-

1

1

1

C389

C388

C387

2

@

@

MIC_IN_R<24>

EXTMIC_DET#<24>

C398 47P_0402_50V8J@

MIC_EXT_L<24>
MIC_EXT_R<24>

MIC_EXT_L MICEXT_L
MIC_EXT_R MICEXT_R

R321 0_0603_5%

R322 0_0603_5%

12

12
12

12

C399 47P_0402_50V8J@

47P_0402_50V8J

C394 47P_0402_50V8J@

47P_0402_50V8J

12

R320 0_0603_5%

EXTMIC_DET#

2

2

@

47P_0402_50V8J

12

2

3

D13

@

1

SM05_SOT23

C390

@

E

1

2

47P_0402_50V8J

MIC INT In-R

MICIN_R

MIC EXT In

CONN@

SUYIN_010030FR006G105ZR

6
5

4
3
2

1

JP16

SPEAKER

JP15

1

1

2

2

3

3

4

4

E&T_3801-04

CONN@

JP28

1

1

2

2

3

G1

4

G2

ACES_85204-02001

CONN@

HeadPhone Out/Line Out

13

D

Q13

2

G

cap. high 5.7mm

C402

HP_OUTR<24>

HP_OUTL<24>

4 4

HP_OUTR

HP_OUTL

+

1 2

+

1 2

C403

100U_6.3V_M

100U_6.3V_M

1K_0402_5%

R327

12

13

D

S

HP_OUT_R

HP_OUT_L

12

Q16

2

G

2N7002_SOT23-3

13

D

S

1 3

D

D

1 3

R328
1K_0402_5%

Q17

2

2N7002_SOT23-3

G

2

G

S

S

G

2

Q14
2N7002_SOT23-3

Q15
2N7002_SOT23-3

HP_OUTR+

HP_OUTL+

2N7002_SOT23-3

S

HP_OUTR+
HP_OUTL+

R325 0_0603_5%

R326 0_0603_5%

HP_DET#<24>

C401 47P_0402_50V8J@

12

12
12

12

C404 47P_0402_50V8J @

HP_DET#

PR
PL

2

3

@

1

SM05_SOT23

CONN@

SUYIN_010030FR006G105ZR

6
5

4
3
2

1

JP17

D14

0302_Change Audio Jack.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2007/08/29

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

AMP & Audio Jack

LA-3732P

E

0.2

of

26 40Wednesday, March 14, 2007

5

4

3

2

1

0228_Add JP29 for USB card reader.

D D

JP29

USB20_P4<20>

USB Port

+5VALW

SYSON# USB_OC#2

+USB_VCCA

220U_6.3V_M

1

C C

C406

+

C407

2

0.1U_0402_16V4Z

1

2

1

C408
1000P_0402_50V7K

2

USB20_N2<20>

USB20_P2<20>

U14

1

GND

2

IN

3

IN

4

EN#

G528P1UF_SO8

@

PSOT24C_SOT23-3

D15

+USB_VCCA

8

OUT

7

OUT

6

OUT

5

FLG

0308_Change connector type.

JP19

1

1

2

2

3

3

4

4

2

3

1

5

GND

6

GND

7

GND

8

GND

SUYIN_020133MB004S580ZL-C

CONN@

DC233000U00 CONN SUYIN 020173MR004S558ZL 4P USB
SUYIN_020173MR004S558ZL_4P

USB_OC#2 <20>

USB20_N4<20>

+5VALW

+5VS

USB20_N0<20>

USB20_P0<20>

USB20_N1<20>
USB20_P1<20>
USB_OC#0<20>

SYSON#<31,35>

SYSON#

1

1

3

3

5

5

7

7

9

9

11

11

GND13GND14GND15GND16GND17GND

+5VALW

SP02000DX00 S W-CONN ACES 87213-1000G 10P P1.0
ACES_87213-1000G_10P

2
4
6

8
10
12

ACES_88020-12101

18

CONN@

JP18

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_87213-1000G

CONN@

2
4
6
8
10
12

+3VS

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

USB CONN.

LA-3732P

27 40Wednesday, March 14, 2007

1

0.2

of

5

4

3

2

1

POWER LED(Left 1)

M/BtoS/B

0301_Change Voltage from 3V to 5V.

+5VALW

+5VS

D D

NUM_LED#<29,30>
WL_BTN#<30>

Power ON/OFF

+3VALW

R330

4.7K_0402_5%

D17

ON/OFFBTN#

DAN202U_SC70

C C

EC_ON<30>

EC_ON

1

Q18
DTC124EK_SC59

+3VALW

12

R332

4.7K_0402_5%

2
3

1 2

ON/OFF
51ON#

1

O

1

G

2

1000P_0402_50V7K

3I2

ON/OFF <30>
51ON# <34>

0216_Delete D19.

C409

ON/OFFBTN_LED#<29,30>

LID_SW#<30>

M/B to SB(Caps Lock LED)

CAPS_LED#<29,30>

ON/OFFBTN#
WL_BTN#

ON/OFFBTN_LED#
WL_LED#
LID_SW#

SP01000H400 S H-CONN ACES 85201-1005N 10P P1.0
ACES_85201-1005N_10P

SP02000D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P

+5VS

10
11
12

JP20

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9
10
GND

GND

ACES_85201-1005N

CONN@

JP21

1

1

2

2

3

G1

4

G2

ACES_85204-02001

CONN@

Battery Charge LED(Left 2)

SATA_LED#<19>

Wireless ON/OFF LED(Left 4)

On (WL_ON#=L)-> Blue
Off (WL_ON#=H)-> Amber

WL_LED#<22>

ON/OFFBTN_LED#

LTST-C191TBKT-5A_BLUE_0603~D

BAT_LED#<30>

LTST-C191TBKT-5A_BLUE_0603~D

HDD LED(Left 3)

LTST-C191TBKT-5A_BLUE_0603~D

820_0402_5%

AMBER BLUE

LTST-C195TBKFKT_BLUE/ORG

WL_LED#

BLUE

D16

1 2

R329

1 2

470_0402_5%

BLUE

D18

1 2

R331

1 2

470_0402_5%

BLUE

D20

1 2

0208_Change Voltage from 3V to 5V.

+5VS

12

12

R334

2

4

D21

Orange

1

3

13

D

S

13

D

Q20

2

2N7002_SOT23-3

G

S

1 2

R335
200_0402_5%

Blue

WL_LED#_LIGHT

Q19

2

2N7002_SOT23-3

G

R333

470_0402_5%

+5VALW

+5VALW

+5VS

R336

10K_0402_5%

+5VS

12

B B

A A

0208_Change R329, R331, R333 to 470 ohm, R334 and R339 to 820 ohm, R335 and R338 to 200 ohm.
0208_Delete reserve component (D25 SW2) for 14.1".

+5VS

TouchPAD ON/OFF LED

12

12

Blue

R339
820_0402_5%

2

4

AMBERBLUE

D23

LTST-C195TBKFKT_BLUE/ORG

Orange

1

3

13

D

On (TP_LED#=L)-> Blue

S

Off (TP_LED#=H)-> Amber

13

D

TP_LED#

Q22

2

2N7002_SOT23-3

G

S

+5VS

12

R341
10K_0402_5%

TP_LED#_LIGHT

R338

200_0402_5%

Q21

2N7002_SOT23-3

5

2

G

、

TP_LED# <30>

4

D21, D25, D23 Footprint can not match part number.

TP ON/OFF

+5V

R340

SW1

SMT1-05-A_4P

3
4

5

6

SN100000F00 S TACT SW SMT1-05-A SPST HCH H1.5 4P
SW_SMT1-05-A_4P

10K_0402_5%

1 2

TP_BTN#

1
2

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T/P Board

+5V

TP_BTN# <30>

SP01000H300 S H-CONN ACES 85201-0405N 4P P1.0
ACES_85201-0405N_4P

2006/02/13 2006/07/26

3

JP22

1
2
3

4
G1
G2

ACES_85201-0405N

CONN@

Compal Secret Data

1
2
3
4
5
6

100P_0402_50V8J

Deciphered Date

1

C412

@

2

C413

@

0.1U_0402_16V4Z

1

1

C414

@

100P_0402_50V8J

2

2

TP_DATA
TP_CLK

2

3

1

D24
PSOT24C_SOT23-3

@

EMI request

TP_CLK <30>
TP_DATA <30>

0226_Change package from 0603 to 0402.

2

SYSON<30,31,35>

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LED/SW

+5VALW +5V

10K_0402_5%

SYSON

Q33

SI2301BDS-T1-E3_SOT23-3

S

G

12

2

R384

13

D

Q34

2

2N7002_SOT23-3

G

S

LA-3732P

1

D

13

0.2

of

28 40Wednesday, March 14, 2007

+3VALW+3VALW

1

C415

0.1U_0402_16V4Z

SMB_EC_CK1<30,38>
SMB_EC_DA1<30,38>

2

U16

8
7
6
5

AT24C16AN-10SI-2.7_SO8

A0

VCC

A1

WP
SCL

A2

SDA

GND

SPI ROM

+3VALW

20mils

1

C416

0.1U_0402_16V4Z

FSEL#<30>
SPI_CLK<30>

FWR# FRD#

2

1 2

R345 0_0402_5%

1 2

R346 0_0402_5%

1 2

R347 0_0402_5%

SPI_FSEL#
SPI_CLK_R

U17

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
WIESO_G6179-100000_8P

&U1

45level

45@

SST25LF080B_SO8-200mil

12

R342
100K_0402_5%

1
2
3
4

12

R343
100K_0402_5%

4

VSS

SPI_SOSPI_FWR#

2

Q

WIESON G6179 8P SPICONN@

1 2

R348 0_0402_5%

FRD# <30>FWR#<30>

+3VALW

ON/OFFBTN_LED#<28,30>

CAPS_LED#<28,30>

NUM_LED#<28,30>

VCC1_PWRGD<30>

LPC Debug Port

CLK_DEBUG_PORT<15,22,30>

LPC_FRAME#<19,22,30>

PCI_RST#<18,23,30>

LPC_AD0<19,22,30>
LPC_AD1<19,22,30>
LPC_AD2<19,22,30>
LPC_AD3<19,22,30>

SPI_CLK_JP52
SPI_CS#_JP52
SPI_SI_JP52
SPI_SO_JP52
SPI_HOLD#_0

Connect pin3 & 23
together and pin 24
to GND in 6/29.

SPI_CLK

FSEL#

FWR#

HOLD#

FRD#

R349 0_0402_5%@

1 2

R350 0_0402_5%@

1 2

R351 0_0402_5%@

1 2

R352 0_0402_5%@

1 2

R353 0_0402_5%@

1 2

1 2

R222 0_0402_5%@

1 2

R356 0_0402_5%@

1 2

R357 0_0402_5%@

1 2

R399 0_0402_5%@

Change from + 3 VL to +3VS. 6/9

Removed +3VS. 6/13

B+

JP23

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

ON/OFFBTNLED#
CAPSLED#
NUMLED#
VCC1PWRGD

SPI_CLK_JP52

SPI_CS#_JP52

SPI_SI_JP52

SPI_HOLD#_0

SPI_SO_JP52

ON/OFFBTNLED#

CAPSLED#

NUMLED#

VCC1PWRGD

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACES_87216-2404_24P

@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

BIOS ROM

LA-3732P

29 40Wednesday, March 14, 2007

of

0.2

+3VALW_EC

0.1U_0402_16V4Z

1

1

C417

2

0.1U_0402_16V4Z

+3VS +5VALW

12

R366

R365

4.7K_0402_5%

4.7K_0402_5%

EC DEBUG port

JP26

@

1

1

2

2

3

3

4

4

ACES_85205-0400

FOR LPC SIO DEBUG PORT

JP24

@

1

1

2

2

3

3

4

4

5

5

6

6

LPC_AD0

7

7

LPC_AD1

8

8

LPC_AD2

9

9

LPC_AD3

10

10

LPC_FRAME#

11

11

LPC_DRQ#0

12

12

PCI_RST#

13

13

14

14

CLK_DEBUG_PORT

15

15

SIRQ

16

16

17

17

18

18

19

19

20

20

ACES_85201-2005

1

C418

2

1000P_0402_50V7K

12

12

R363

R364

4.7K_0402_5%

4.7K_0402_5%

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

C419

2

12

0205_Add Pull down R402 for SUSP#.

+5VALW

URX

UTX

+5VS

+3VS

CLK_14M_DEBUG <15>

LPC_DRQ#0 <19>

0.1U_0402_16V4Z

1

2

1

C420

2

C424

@

1 2

15P_0402_50V8J

CLK_PCI_EC<15>

+3VALW

C425

1 2

0.1U_0402_16V4Z

+3VALW +3VS

1000P_0402_50V7K

C421

R358

@

1 2

33_0402_5%

R359

12

47K_0402_5%

12

R403
10K_0402_5%

LID_SW# WL_BTN#

12

12

R404
10K_0402_5%

J1
JOPEN

GATEA20<19>
KB_RST#<19>

SIRQ<20>

LPC_FRAME#<19,22,29>

LPC_AD3<19,22,29>
LPC_AD2<19,22,29>
LPC_AD1<19,22,29>
LPC_AD0<19,22,29>

PCI_RST#<18,23,29>
EC_SCI#<20>

0214_Add Pull high resistor for LID_SW# and WL_BTN#.

SMB_EC_CK1<29,38>
SMB_EC_DA1<29,38>
SMB_EC_CK2<4>
SMB_EC_DA2<4>

SLP_S3#<20>
SLP_S5#<20>

SUSP#

12

R402
100K_0402_5%

R383

@

10K_0402_5%

CLK_DEBUG_PORT <15,22,29>

12

1 2

10P_0402_50V8J

3

NC

2

NC

Y4

1 2

10P_0402_50V8J

EC_SMI#<20>

LID_SW#<28>

SUSP#<24,31,33,35,36>

PWRBTN_OUT#<20>

PCI_PME#<18,23>

TP_BTN#<28>

ON/OFF<28>

NUM_LED#<28,29>

C426

4

OUT

1

IN

32.768KHZ_12.5P_1TJS125DJ2A073

C427

GATEA20
KB_RST#
SIRQ
LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

CLK_PCI_EC
PCI_RST#
ECRST#
EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
SUSP#
PWRBTN_OUT#
PCI_PME#

TP_BTN#

UTX

URX

ON/OFF
NUM_LED#

CRY2

12

20M_0402_5%@

R368

CRY1

+3VALW

R382

0_0805_5%

U18

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

+3VALW_EC

+EC_AVCC

12

+3VALW_EC

12

Int. K/B
Matrix

SM Bus

L14
0_0603_5%

1 2

C428

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

PWM Output

AD Input

DA Output

PS2 Interface

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

0.1U_0402_16V4Z

Issued Date

67

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B
AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

CAPS_LED#/GPIO53
SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

KB926QFB0_LQFP128_14X14

69

ECAGND

L15

1 2

0_0603_5%

2006/02/13 2006/07/26

INV_PWM

21

FAN_PWM

23
26

ACOFF

27

63
64
65
66
75
76

DAC_BRIG

68
70

IREF

71
72

EC_MUTE#

83

ACZ_RST#

84
85

TP_LED#

86

TP_CLK

87

TP_DATA

88

97

R360 10K_0402_5%

98
99

WL_BTN#

109

FRD#

119

FWR#

120

SPI_CLK

126

FSEL#

128

73

VCC1_PWRGD

74

FSTCHG

89
90

CAPS_LED#

91

BAT_LED#

92

ON/OFFBTN_LED#

93

SYSON

95

VR_ON

121

ACIN

127

EC_RSMRST#

100

R397 0_0402_5%

101

EC_ON

102
103

PM_PWROK

104

BKOFF#

105

M_PWROK

106
107
108

SLP_S4#

110
112
114

THERM_SCI#

115
116
117
118

124

BATT_TEMP
BATT_OVP
ADP_IN
M/B_ID

CLK_ENABLE

12

CAPS_LED# <28,29>

SYSON <28,31,35>

R393 10K_0402_5%

1 2

EC_RSMRST# <20>

BKOFF# <17>
M_PWROK <7,20>

THERM_SCI# <20>

Compal Secret Data

Deciphered Date

INV_PWM <17>
FAN_PWM <4>

ACOFF <33>

BATT_TEM P <38>
BATT_OVP <33>
ADP_I <33>

DAC_BRIG <17>
IREF <33>

EC_MUTE# <26>
ACZ_RST# <19,24>

TP_LED# <28>

TP_CLK <28>
TP_DATA <28>

WL_BTN# <28>

FRD# <29>
FWR# <29>
SPI_CLK <29>
FSEL# <29>

VCC1_PWRGD <29>
FSTCHG <33>

BAT_LED# <28>
ON/OFFBTN_LED# <28,29>

VR_ON <37>
ACIN <33>

EC_ON <28>

PM_PWROK <7,20>

SLP_S4# <20>

ECAGND

1 2

C423 0.01U_0402_16V7K

CLK_ENABLE <15>

12

EC_LID_OUT# <20>

+3VALW_EC

M/B_ID

1

C422

@

0.1U_0402_16V4Z

2

VCC 3.3V+/-5%
Ra 100K+/-5%
Board ID Rb V

00V0V0V

0

8.2K+/-5%

1

18K+/-5%

2

33K+/-5%

3

56K+/-5%

4

100K+/-5%

5

200K+/-5%

6

NC

7

min V typ

AD_BID

0.216V

0.436V

0.712V

1.036V

1.453V

1.935V

2.500V

TP_CLK
TP_DATA

AD_BID

0.250V

0.503V

0.819V

1.185V

1.650V

2.200V

3.300V

For EMI

JP25

KSO15

1

1

KSO10

2

2

KSO11

3

3

KSO14

4

4

KSO13

5

5

KSO12

6

6

KSO3

7

7

KSO6

8

8

KSO8

9

9

KSO7

10

10

KSO4

11

11

KSO2

12

12

KSI0

13

13

KSO1

14

14

KSO5

15

15

KSI3

16

16

KSI2

17

17

KSO0

18

18

KSI5

19

19

KSI4

20

20

KSO9

21

21

KSI6

22

22

KSI7

23

23

KSI1

24

24

25

GND1

26

GND2

ACES_85201-24051

CONN@

SP01000FF00 85201-24051 24P P1.0
ACES_85201-24051_24P

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

EC KB926/KB conn

LA-3732P

KSO14
KSO11
KSO10
KSO15

KSO6
KSO3
KSO12
KSO13

KSO2
KSO4
KSO7
KSO8

KSI3
KSO5
KSO1
KSI0

KSI4
KSI5
KSO0
KSI2

KSI1
KSI7

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

12

Ra

R354

@

100K_0402_5%

12

Rb

R355
0_0402_5%

V

0.289V

0.538V

0.875V

1.264V

1.759V

2.341V

3.300V

12

R36110K_0402_5%

12

R36210K_0402_5%

CP1

2
3
4 5

CP2

2
3
4 5

CP3

2
3
4 5

CP4

2
3
4 5

CP5

2
3
4 5

CP6

2
3
4 5

of

30 40Wednesday, March 14, 2007

AD_BID

+5V

max

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

0.2

A

B

C

D

E

1 1

2 2

+5VALW to +5VS Transfer +3VALW to +3VS Transfer

+5VS+5VALW +3VS+3VALW

U19

D
D
D
D

AO4422_SO8

RUNON

S
S
S

G

1
2
3
4

SYSON#

SYSON

1

C431

2

0.1U_0402_16V4Z

+5VALW

12

13

2

G

1

2

R371
100K_0402_5%

D

Q24
2N7002_SOT23-3

S

C432
10U_0805_10V4Z

8
7
6

1

C429

5

2

10U_0805_10V4Z

SYSON#<27,35> SUSP<35>

R369

330K_0402_5%

SUSP

2

G

B+

12

13

D

Q23
2N7002_SOT23-3

S

SUSP#<24,30,33,35,36>SYSON<28,30,35>

1

C430

2

10U_0805_10V4Z

RUNON

SUSP

SUSP#

8

D

7

D

6

D

5

D

AO4422_SO8

12

R370
470_0402_5%

1

C435

0.01U_0402_16V7K

2

2

G

U20

S
S
S
G

+5VALW

12

R372
100K_0402_5%

13

D

S

10U_0805_10V4Z

1
2
3
4

1

C433

2

0.1U_0402_16V4Z

Q25
2N7002_SOT23-3

1

C434

2

C436

1 2

0.1U_0402_16V4Z

C437

+VCCP +1.5VS

1 2

0.1U_0402_16V4Z

+VCCP+VCC_CORE

3 3

Discharge circuit

2

G

+1.8V

12

13

D

S

B

R375
470_0402_5%

Q28
2N7002_SOT23-3

+5VS +3VS

2

G

12

R373
470_0402_5%

13

D

Q27
2N7002_SOT23-3

S

12

R374

470_0402_5%

13

2

G

D

Q26
2N7002_SOT23-3

S

SUSP SUSP SYSON# SUSP SUSP SUSP SUSP

4 4

A

2

G

+1.5VS

12

13

R376
470_0402_5%

D

Q29
2N7002_SOT23-3

S

+1.25VS +VCCP +0.9V

2

G

12

R377
470_0402_5%

13

D

Q30
2N7002_SOT23-3

S

2

G

12

R378
470_0402_5%

13

D

Q31
2N7002_SOT23-3

S

2

G

12

R379
470_0402_5%

13

D

Q32
2N7002_SOT23-3

S

For Card reade r/B stand off.

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

H24
HOLEA

1

D

H25
HOLEA

1

H26
HOLEC

1

H1
HOLEA

1

H27
HOLEA

1

Size Document Number Rev

Date: Sheet

H3

H2

HOLEA

HOLEA

1

1

H11

H12

HOLEA

HOLEA

1

1

FM2

FM1

1

1

CF1

1

Title

CF2

1

Compal Electronics, Inc.

H6

H5

HOLEA

HOLEA

1

1

H16

H15

HOLEC

HOLEC

1

1

FM4

1

CF4

CF3

1

1

1

DC/DC Interface

LA-3732P

E

H7
HOLEA

1

H17
HOLEC

1

CF5

H8
HOLEA

1

H18
HOLEC

1

1

CF6

31 40Wednesday, March 14, 2007

H9
HOLEA

H21
HOLEC

1

H10
HOLEA

1

1

H23
HOLEC

1

1

CF7

CF8

1

0.2

of

A

1 1

2 2

B

C

D

VIN

PL1

PCN1

1

1

2

2

3

3

4

4

5

5

ACES_88334-057N

ADPIN

100P_0402_50V8J

HCB4532KF-800T90_1812

PC1

12

12

PC2
1000P_0402_50V7K

1 2

PC3

100P_0402_50V8J

12

12

PC4

1000P_0402_50V7K

+3VALW

3 3

PR157

100_0402_5%

1 2

4 4

A

1 3

PQ38
TP0610K-T1-E3_SOT23

2

B

AC_LED <33>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

<Issued_Date> <Deciphered_Date>

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

DC CONN

LA-3732P

D

32 40Wednesday, March 14, 2007

of

A

3
2
16

PC6

7

P2

12

0.1U_0603_16V7K

PR146

1 2

1K_0402_5%

12

PR29
10K_0402_5%

+5VALW

0

3
2
1 6

12

PR4
200K_0402_5%

PR8
150K_0402_5%

1 2

PACIN

PR35

10K_0402_5%

1 2

PU4B
LM358ADT_SO8

8

5

P

+

6

-

G

4

PQ2
FDS4435BZ_SO8

4

MB39A126

12

12

PC15

0.01U_0402_25V7K

IREF <30>

1 2

150K_0402_1%

ACIN <30>

PACIN <34>

8
7

5

PR12
10K_0402_1%

1 2

PR15

10K_0402_1%

PR21

1

VIN

PR3

47K_0402_5%

12

1 1

PR6

47K_0402_1%

1 2

2 2

VIN

12

PR23

2.15K_0402_1%

1 2

12

12

PC26

PR28

0.047U_0402_16V7K

3 3

13

D

2

G

S

RHU002N06_SOT323-3

PACIN

ACOFF#

133K_0603_1%

PR27

10K_0603_0.1%

12

PC28

22P_0402_25V8K

PC5

1 2

47P_0402_50V8J

2

PQ6

PR11

1 2

3K_0402_5%

1 2

1SS355_SOD323-2

P2

12

PR160
47_1206_5%

8

PU2A

3

P

+

O

2

-

G

LM393DG_SO8

4

PR30

1 2

51K_0402_1%

4

5

2

13

PQ5

DTC115EUA_SC70-3

PD5

PR18

1 2

1M_0402_5%

12

PC24

0.1U_0603_25V7K

1

P2

PU3

REF

CATHODE

ANODE

LMV431ACM5X_SOT23-5

+3VALW

12

PR33

47K_0402_1%

13

PQ13
DTC115EUA_SC70-3

4 4

FSTCHG<30>

2

13

D

2

G

S

A

8
7

5

PQ4

DTA144EUA_SC70-3

1 3

2

G

PD4

3
2

NC

1

NC

CS

PQ12
RHU002N06_SOT323-3

PQ1
FDS4435BZ_SO8

4

13

D

PQ8
RHU002N06_SOT323-3

S

VIN

12

PR22

10K_0402_1%

3.2V

12

RLZ4.3B_LL34

1.24VREF

BATT_OVP<30>

ADP_I<30>

0.22U_0603_16V7K

12

PR16

34.8K_0603_1%

12

PC17

0.22U_0603_16V7K

8

0

4

B

PC11

PC12
4700P_0402_25V7K

1 2

VREF

MB39A126

12

PR24

100K_0402_1%

+5VALW

12

3

P

+

2

-

G

PU4A
LM358ADT_SO8

B

PR9

10K_0402_5%

1 2

PR14
100K_0402_1%

65W: PR46=34.8K
90W: PR46=21.0K

PC18

PR19

2200P_0402_50V7K

1K_0402_1%

12

PC29

0.01U_0402_25V7K

1 2

PC22

1U_0603_6.3V6M

12

PR31

340K_0402_1%

12

PR32

499K_0402_1%

12

PR34

105K_0402_1%

1 2

P4

12

BATT

ADP_I_A

12

PR25
10K_0402_1%

12

RHU002N06_SOT323-3

12

PC30

0.01U_0402_25V7K

C

B+

24

23

22

21

20

PC16

0.1U_0603_25V7K

19

18

PR20
47K_0402_1%

17

16

MB39A126

15

14

13

+3VALW

PL2
SMB3025500YA_2P

1 2

12

PR13

0_0402_5%

PC13

0.22U_0603_16V7K

1 2

PC14

0.1U_0603_25V7K

1 2

PC23

1500P_0402_50V7K

1 2

PC7

0.1U_0603_25V7K

12

CHG_B+

12

CS

1 2

1 2

PR26
33K_0402_1%

1 2

PC25
10P_0402_50V8J

1 2

CV=12.6V (6/12 CELLS LI-ION)
CC=3.08A (6/12 CELLS LI-ION)

PR159

100K_0402_5%

1 2

BATT_DET <38>

C

12

12

PC8

2200P_0402_50V7K

1 2

PR1

1 2

100K_0402_1%

Compal Secret Data

PR7

1 2

0.015_2512_1%

PU1
MB39A126PFV-ER_SSOP24

1

-INC2

+INC2

2

OUTC2

GND

3

+INE2

CS

4

-INE2

VCC

5

ACOK

OUT

6

VREF

VH

7

ACIN

XACOK

8

-INE1

RT

9

+INE1

-INE3

10

OUTC1

FB123

11

SEL

CTL

12

-INC1

+INC1

+3VALW

PR158

100K_0402_5%

1 2

13

D

PQ37

2

G

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC . AND CONTAINS CONFIDENT IAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PQ3
FDS4435BZ_SO8

3
2
1 6

12

PC9

PC10

4.7U_1206_25V6K

4.7U_1206_25V6K

16

578

PD2

FSTCHG

RB751V-40_SOD323-2
PD3

RB751V-40_SOD323-2

PC27

47P_0402_50V8J

1 2

Deciphered Date

4

243

16UH_SIL1045R - 160_4.1A_30%

12

PD1

8
7

5

CHG_B+

AC_LED< 32>

PQ10

FDS4435BZ_SO8

PL3

1 2

EC31QS04

SUSP# <24,30,31,35,36>

ACOFF#

PR10
100K_0402_5%

+3VLP

PACIN

2

G

PQ9

RHU002N06_SOT323-3

1 2

0.02_1206_1%

Custom

D

BATT

PR5

1 2

47K_0402_5%

PR2
10K_0402_5%

1 2

13

13

D

12

2

PQ7

G

S

13

D

S

PR17

Title

Size D oc ument Number Re v

Date: Sheet

RHU002N06_SOT323-3

12

12

PC19

PC20

10U_1206_25V6M

10U_1206_25V6M

Compal Electronics, Inc.

Charger

Wednesday, March 14, 2007

D

VIN

PQ11
DTC115EUA_SC70-3

2

12

PC21

10U_1206_25V6M

ACOFF <30>

BATT

of

4033

A

B

C

D

E

PC31

0.1U_0603_25V7K

0.1U_0603_50V4Z

578

PQ15
AO4468_SO8

3 6

241

578

PQ35
AO4468_SO8

3 6

241

VL

PR55

499K_0603_1%

1 2

DH_5V_B

1 2

2VREF_1999

MAINPW O N

12

12

PC46

0.047U_0603_16V7K

PR39

0_0402_5%

1 2

PR49

0_0402_5%

PR50

1 2

@0_0402_5%

1 2

PR52

@10K_0402_5%

2VREF_1999

MAINPWON <38>

PQ17

13

D

RHU002N06_SOT323-3

S

1 2

2

G

PR41
0_0402_5%

1 2

BST_5V
DH_5V
LX_5V

DL_5V

PR56

300K_0402_5%

12

D

S

2

3

PD6
CHP202UPT_SOT323-3

1

B++

VL

1

PC40

2

4.7U_0805_10V4Z

18

PU5

14

BST5

9
1

6
4
3

8

PC44

DH5
LX5

DL5
OUT5
FB5
N.C.

SHDN#
ON5
ON3

SKIP#
REF

0.22U_0603_10V7K

LD05

GND

23

16
15

19
21

12

VL

12

PR59
100K_0402_5%

13

2

G

PQ18

RHU002N06_SOT323-3

12

0.1U_0603_50V4Z

PC38

20

V+

LDO3

25

1

PC45

2

4.7U_0805_10V4Z

PACIN <33>

BST_3.3V_BBST_5V_B

VL

PR40

1 2

47_0402_5%

12

13

17

ILIM3

TON

VCC

ILIM5
BST3

DH3

DL3

LX3

OUT3

FB3

PGOOD

PRO#

MAX8734AEEI+_QSOP28

10

+3VLP

PR57
0_0402_5%

1 2

12

PC35

0.1U_0603_16V7K

2VREF_1999

PC39

PR43
0_0402_5%

1 2

1U_0805_16V7K

5

1 2

11

BST_3.3V

28

DH_3.3V

26

DL_3.3V2VREF_1999

24

LX_3.3V

27
22

7
2

13

D

2

G

PQ19

S

RHU002N06_SOT323-3

0_0402_5%
PR44

1 2

PR45

PR46

1 2

@499K_0402_1%

1 2

@499K_0402_1%

PR154
100K_0402_5%

PL4

FBM-L11-322513-151LMAT_1210

B+

1 1

2 2

3 3

12

B++

12

12

PC33

PC34

10U_1206_25V6M

2200P_0402_50V7K

10U_LF919AS-100M-P3_4.5A_20%

PL5

+5VALWP

PC41

1

1 2

+

2

1 2

220U_6.3VM_R15

12

PR48

@10.2K_0402_1%

PR53

0_0402_5%

B++

12

PR51

47K_0402_5%

12

PC42

PC32

0.1U_0603_50V4Z

1 2

PR42
0_0402_5%

1 2

1 2

PQ26
TP0610K-T1-E3_SOT23

1 3

B++

12

PR47

0_0402_5%

PC36

2

12

PC37

2200P_0402_50V7K

4.7U_1206_25V6K

DH_3.3V_B

PR156

100K_0402_5%

1 2

578

3 6

578

PQ16
AO4468_SO8

241

3 6

241

+3VLP

PQ36
AO4468_SO8

1 2

1 2

12

PL6

10U_LF919AS-100M-P3_4.5A_20%

+3VALWP

PR54

1

+

@3.57K_0402_1%

PC43

220U_6.3VM_R15

2

PR58

0_0402_5%

51ON#<28>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

<Issued_Date> <Deciphered_Date>

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

3.3VALWP / 5VALWP

Wednesday, March 14, 2007

E

of

4034

5

PL7

FBMA-L11-322513-151LMA50T_1210

B+

12

D D

PC47
680P_0402_50V7K

1.8V_B+

12

12

PC48

12

2200P_0402_50V7K

PC49

10U_1206_25V6M

12

PR61

10_0402_5%

4

PR62

1M_0402_5%

PC54

1000P_0402_50V7K

3

+5VALW

578

3 6

241

PQ21
AO4468_SO8

12

PD7

12

1SS355_SOD323-2

1 2

2

1

SYSON<28,30,31>

C C

B B

+5VALWP

+3VALWP

+1.8VP

+1.05V_VCCP

+1.5VSP

+0.9VP

A A

1 2

PR64

0_0402_5%

PJP1

1 2

PAD-OPEN 4x4m
PJP3

1 2

PAD-OPEN 4x4m
PJP5

1 2

PAD-OPEN 4x4m
PJP6

1 2

PAD-OPEN 4x4m
PJP7

1 2

PAD-OPEN 4x4m
PJP8

1 2

PAD-OPEN 3x3m

1U_0603_10V6K

+5VALW

(3A,120mils ,Via NO.= 6)

+3VALW

(7A,280mils ,Via NO.= 14)

+1.8V

(6A,240mils ,Via NO.=12)

+VCCP

(6A,240mils ,Via NO.=12)

+1.5VS

(2A,80mils ,Via NO.= 4)

+0.9V

@2200P_0402_25V7K

PC57

12

PC55

12

+1.25VSP

+3VLP +3VL

12

PR66

100K_0402_5%

PU6

1

VOUT

2

VCCA

3

FB

4

PGD

17

PJP2

1 2

PAD-OPEN 3x3m

PJP4

2 1

PAD-OPEN 2x2m

TP

16

TON

NC5VSSA

15

EN/PSV

6

12

BOOT_1.8V

PR65

1 2

0_0402_5%

14

13

NC

BST

12

DH

11

LX

10

ILIM

9

VDDP

PGND7DL

SC411MLTRT_MLPQ16_4X4

8

PR70

1 2

27K_0603_0.1%

1 2

PC60
33P_0402_50V8J

PR71
10K_0603_0.1%

(500mA,40mils ,Via NO.= 1)(4.5A,180mils ,Via NO.= 9)

+1.25VS

(100mA,20mils ,Via NO.= 1)

LX_1.8V

PR69

1 2

16.9K_0402_1%

12

BOOT1_1.8V

PC59
1U_0603_10V6K

1 2

PC56

0.1U_0402_16V7K

V_DDR_MCH_REF<7,13,14>

UG_1.8V

578

PQ22
FDS6690AS_NL_SO8

3 6

241

LG_1.8V

SUSP#<24,30,31,33,36>

+1.8V

12

12

PC63

10U_0805_10V4Z

SYSON#<27,31>

SUSP<31>

1 2

PR73

@0_0402_5%

RHU002N06_SOT323-3

1 2

PR60

0_0402_5%

PQ20

12

PC68
@0.1U_0402_16V7K

12

PC64

PR72

1K_0402_1%

10U_0805_10V4Z

@

12

PR67

13

D

2

G

1K_0402_1%

S

PL8

3.3UH_SIL1045R-3R3PF_8.2A_30%

1 2

12

PR68

@4.7_1206_5%

12

PC58

@680P_0603_50V7K

1 2

PR147

0_0402_5%@

1 2

PR148

0_0402_5%

PC127

0.01U_0402_16V7K@

2
3
4

12

12

PC67
10U_1206_6.3V7K

0.1U_0402_16V7K

PC66

PU13

7

POK

8

EN

12

APL5913-KAC-TRL_SO8

PU8

VIN1VCNTL
GND
VREF
VOUT

G2992F1U_SO8

+0.9VP

+1.8VP

1

12

220U_6.3VM_R15

+5VALW

12

PC126
1U_0603_6.3V6M

33.2K_0402_1%

59K_0402_1%

PC51

0.1U_0402_16V7K

PR149

PR150

12

PC52

0.1U_0402_16V7K

12

12

12

PC65
1U_0603_16V6K

12

PC128
47P_0402_50V8J

+5VALW

+1.5VS

12

PC129
10U_1206_6.3V6M

+1.25VSP

12

PC130
22U_1206_6.3V6M

+

PC50

2

6

5

VIN

9

VIN

VCNTL

3

VOUT

4

VOUT

2

FB

GND

1

6
5

NC

7

NC

8

NC

9

TP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

<Issued_Date> <Deciphered_Date>

Compal Secret Data

Deciphered Date

2

Title

Size D o c um ent Number R ev

Date: Sheet

Compal Electronics, Inc.

1.8VP/0.9VSP/2.5VSP

LA-3732P

1

35 40Wednesday, March 14, 2007

of

0.2

5

4

3

2

1

PC80

PU9

25

P PAD

7

PGOOD2

8

EN2

9

VBST2

10

DR VH2

11

LL2

12

DR VL2

15K_0402_1%

1 2

B+++

PR75

75K_0402_1%

1 2

PR78

0_0402_5%

6

VO2

PGND2

13

PR85

12

PR88

3.3_0402_5%

5

VFB2

14

1 2

3

4

GND

TONSEL

V5IN16TRIP2

15

12

12

75K_0402_1%

2

12

PC81

4.7U_1206_25V6K

PR76

1 2

VFB1

PGOOD1

TRIP117V5FILT

PR86
18K_0402_1%

29.4K_0402_1%

1

VO1

24
23

EN1

22

VBST1

UG_1.05V

21

DR VH1

20

LL1

19

DR VL1

PGND1

TPS51124RGER_QFN24_4x4

18

+5VALWP

PR77

1 2

PR81

0_0402_5%

BST_1.05V

LX_1.05V

LG_1.05V

12

PC131

1 2

0.1U_0603_16V7K

VCCP_POK

PR82

0_0402_5%

1 2

PR84

0_0402_5%

1 2

0.1U_0603_25V7K

1 2

0_0402_5%

12

PR89

PC82
@1000P_0402_50V7K

UG1_1.05V

PC78

1 2

SUSP#

578

3 6

578

3 6

241

241

PQ24
AO4468_SO8

PL10

2.2UH_PCMC063T-2R2MN_8A_20%

<BOM Structure>

1 2

4.7U_0805_6.3V6K

PQ25

FDS6690AS_NL_SO8

PC74

+1.05V_VCCP

1

12

+

2

12

12

PC69

PC70

10U_1206_25V6M

@2200P_0402_50V7K

PC73

220U_6.3VM_R15

PL9

FBMA-L11-322513-151LMA50T_1210

1 2

B+

12

12

PC72

D D

+1.5VSP

C C

1

+

PC75

2

220U_6.3VM_R15

PC71

3.3UH_SIQB74B-3R3PF_5.9A_20%

PC76

4.7U_0805_6.3V6K

1 2

4.7U_1206_25V6K

@2200P_0402_50V7K

PR79

UG1_1.5V

8
7
6
5

PR87

0_0402_5%

0_0402_5%

1 2

PR83

PC77

0_0402_5%

1 2

12

0.1U_0603_25V7K

12

12

PC79

LG_1.5V

PL14

PQ23

1

G2

D2

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

SP8K10S FD5 2N SOP8

12

SUSP#<24,30,31,33,35>

@1000P_0402_50V7K

PR74

73.2K_0402_1%

1 2

PR80

1 2

0_0402_5%

BST_1.5V

UG_1.5V

LX_1.5V

1U_0603_10V6K

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2006/11/23 2007/11/23

Compal Secret Data

Deciphered Date

2

Title

Size D o c um ent Number R ev

Date: Sheet

Compal Electronics, Inc.

1.2V_VP/1.5VSP/1.05VP

LA-3732P

1

of

36 40Wednesday, March 14, 2007

0.2

5

4

3

2

1

+5VS

12

12

PR96

200K_0402_5%

PR99 0_0402_5%

12

PC91

12

0.01U_0402_25V7K

BSTM1 CPU

PC98

1 2

1 2

BSTM2 CPU

1 2

0.22U_0603_16V7K

PR114 0_0402_5%

PC109

0.22U_0603_16V7K

1 2

NTC

1 2

PR124

20K_0402_1%

PR101 2.2_0603_5%

1 2

5

D8D7D6D

PQ28

S1S2S3G

4

FDS6676AS_SO8

1 2

PR115 @3K_0603_1%

1 2

PR118 3.65K_0402_1%

PR120
@3K_0603_1%

SI4684DY-T1-E3_SO8

PR130 2.2_0603_5%

1 2

PR94

D D

10_0402_5%

12

PR95

13K_0402_5%

@470KB_0402_5%_ERTJ0EV474J

PH4

12

CPU_VID0<5>
CPU_VID1<5>
CPU_VID2<5>
CPU_VID3<5>
CPU_VID4<5>
CPU_VID5<5>

C C

CPU_VID6<5>

DPRSLPVR<7,20>
H_DPRSTP#<5,7,19>

H_PSI#<5>

+3VS

PR119

PR125

1.91K_0402_1%

1 2

12

PR126
@10K_0402_5%

VGATE<15,20>
CLK_EN#

B B

VR_ON<30>

1 2

PR123 0_0402_5%

1 2

PR122 0_0402_5%

1 2

0_0402_5%

12

PR98 0_0402_5%

12

PR100 0_0402_5%

12

PR97 0_0402_5%

12

PR102 0_0402_5%

12

PR104 0_0402_5%

12

PR103 0_0402_5%

12

PR106 0_0402_5%

PR108 71.5K_0402_1%

1 2

PC99 470P_0402_50V8J

1 2

PC100 0.22U_0603_16V7K

1 2

PR110 499_0402_1%

1 2

PR112 0_0402_5%

1 2

PR111 0_0402_5%

12

PR117
2K_0402_1%

12

1 2

PC97

1U_0603_16V6K

PU12

VCC

19

Vcc

6

THRM

31

D0

32

D1

33

D2

34

D3

35

D4

36

D5

37

D6

7

TIME

9

CCV

11

REF

39

DPRSLPVR

40

DPRSTP

3

PSI

2

PWRGD

1

CLKEN

38

SHDN

5

VRHOT

4

POUT

MAX8770GTL+_TQFN40

H_PROCHOT#<4>

POUT

1 2

PR128 @0_0402_5%

1 2

PR129 10K_0402_5%

PC111

0.1U_0402_16V7K

1 2

VSSSENSE<5>

PC90

2.2U_0603_6.3V6K

VDD
TON

BST1

DH1

LX1

DL1

PGND1

GND

CSP1

CSN1

CCI

DH2

BST2

LX2

DL2

PGND2

CSP2

CSN2

GNDS

25
8
30
29
28
26
27
18
17
16
12

FB

10
21
20
22
24
23
14
15
13

TP

41

100_0402_5%

1 2

CSN2_CPU

12

PC105

PR127

VSSSENSE

BST1_CPU

DH11_CPU
LX1_CPU

DL1_CPU

CSP1_CPU
CSN1_CPU
FB1_CPU
CC1_CPU
DH2_CPU
BST2_CPU
LX2_CPU
DL2_CPU

CSP2_CPU

1000P_0402_50V7K

1 2

5

D8D7D6D

PQ31

S1S2S3G

4

FDS6676AS_SO8

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

DL1_CPU

1 2

PR121

@3K_0603_1%

PQ30

DL2_CPU

CPU_B+

5

D8D7D6D

SI4684DY-T1-E3_SO8

S1S2S3G

4

5

D8D7D6D

S1S2S3G

4

1 2

PC106

470P_0402_50V8J

5

4

5

4

2

PQ27

12

PQ29

FDS6676AS_SO8

12

12

PC104
4700P_0402_25V7K

D8D7D6D

S1S2S3G

D8D7D6D

PQ32

S1S2S3G

FDS6676AS_SO8

1

+

PC95

PC92

2

47U 25V M 6.3X6 ESR0.44 CE-LX

PL12

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

PR105

2.1K_0603_1%

1 2

4.7_1206_5%

PR107

1 2

PR109

3.48K_0402_1%

PC101

680P_0603_50V7K

PR116 100_0402_5%

1 2

PC102

0.22U_0603_16V7K

1 2

PC103 @0.022U_0402_16V7K

1 2

12

12

PC107

PC108

10U_1206_25V6M

10U_1206_25V6M

12

PR131

12

2.1K_0603_1%

1 2

PR132

4.7_1206_5%

PC112

680P_0603_50V7K

3.48K_0402_1%

Title

Size Document Number Rev

Custom

Date: Sheet

SMB3025500YA_2P

12

PC93

10U_1206_25V6M

12

PC94

2200P_0402_50V7K

10U_1206_25V6M

NTC

PH2

12

1 2

10KB_0603_5%_ERTJ1VR103J

CPU_B+

12

PC110

2200P_0402_50V7K

PL13

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

NTC

PH3

1 2

PR133

Compal Electronics, Inc.

1 2

10KB_0603_5%_ERTJ1VR103J

1 2

PC113 0.22U_0603_16V7K

+CPU_CORE

PL11

+VCC_CORE

VCCSENSE

1

12

+VCC_CORE

37 40Wednesda y, Marc h 14, 2007

12

PC96

VCCSENSE <5>

of

B+

1000P_0402_50V7K

0.2

A

B

C

D

VMB

PCN2

6

BATT+

SMD
SMC

1 1

2 2

RES

GND

TYCO_C-1746706_6P

TS

EC_SMD

5

EC_SMC

4
3
2

1

100_0402_5%

PR138

BATT_DET <33>

PR151

12

@1K_0402_5%

PD8 @SM05_SOT23

3

1

2

PR152

6.49K_0402_1%

1 2

12

12

12

PR153
1K_0402_5%

PR139
100_0402_5%

+3VL

SMB_EC_DA1
SMB_EC_CK1

2

3

PD9

1

@SM24.TC_SOT23-3

BATT_TEMP <30>

PL15

HCB4532KF-800T90_1812

1 2

12

PC122
1000P_0402_50V7K

SMB_EC_DA1 <29,30>
SMB_EC_CK1 <29,30>

BATT

12

PC123

0.01U_0402_50V4Z

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

+5VS

PR140

47K_0402_1%

1 2

+5VS

12

CPU

3 3

12

PC124

0.22U_0603_10V7K

4 4

A

B

PH1
10K_TH11-3H103FT_0603_1%

PR142

15K_0603_1%

1 2

+5VS

12

PR144

2.55K_0603_1%

1 2

PR143

150K_0402_1%

150K_0402_1%

PR145

12

12

PC125

1000P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

<Issued_Date> <Deciphered_Date>

8

PU2B

5

P

+

7

O

6

-

G

LM393DG_SO8

4

Compal Secret Data

Deciphered Date

C

PR141
10K_0402_5%

1 2

MAINPWON <34>

13

D

2

G

Title

Size Document Number Rev

Custom

Date: Sheet

PQ33
RHU002N06_SOT323-3

S

Compal Electronics, Inc.

BATTERY CONN

LA-3732P

D

3840Wednesday, March 14, 2007

of

5

4

3

2

Version change list (P.I.R. List) Power section Page 1 of 1

1

D D

C C

Item Reason for change PG# Modify List Date P hase

1
2
3 3/6

5 3/9
6
7
8
9

HW request.

Change PR152 from 210K to 6.49K

Follow Volga 2.0 design.

For layout concern.

Prevent S3 leakage issue.

Prevent LMV431 will oscillate.

Prevent LMV431 will oscillate.

EMI request add CPU core snabber and gate driver use 2.2_0603

Modify DC in jack LED design for energy star.

35
38
37
374
33
33 3/9
33
34
35 3/12

Modify 1.25VSP enable signal from SLP_S3# to SUSP#.

Change PR152 from 210K to 6.49K

Delete PC118,PC119,PC120,PC121,PR113,PR134.

Change PC95 location behind PL11.

Change PD3 pin 2 connect from EC_ON to SUSP#

Change PR30 from 75K to 51K.

Change PC28 from 0.022u to 22P.

Change PR101&PR130 from 0_0402 to 2.2_0603

Add PQ105.

2/13
2/13

3/8

3/9

3/12

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Changed-List History-1

LA-3732P

1

39 40Wednesday, March 14, 2007

0.2

of

5

4

Version Change List ( P. I. R. List ) for HW Circuit

3

2

1

Change item Page PhaseItem Date

1

D D

C C

B B

Change C117 from 220uF to 10uF.

2

Remove R401.

3

Change Crystal Y2 type (the same as Abita).

4

Connect LAN_RST# from EC_RAMRST# to GND.

5

Change ODD connector type.

6

Change U11 power from +5VS to +5VALW.

7

Change U11 enable signal from SLP_S3# to SUSP#.
Reverse JP19 USB Connector and

8

need to double check layout symbol.
Change Power and Battery charge LED

9

power from +3VALW to +5VALW.

10

Change HDD LED power from +3VS to +5VS.

11

Delete reserve component (D25BSW2) for 14.1".

12

Change R329, R333, R470 from 200 ohm to 470 ohm.

13

Change R334, R339 from 200 ohm to 820 ohm.

14

Add pull down resistor R402 (100k ohm) for SUSP#.

15

Change C44, C49 type from DIP to SMD.

16

Add R402 pull high resistor for LID_SW#.

17

Add R403 pull high resistor for WL_BTN#.

18

Delete D19.
Change R300 from 10 ohm to 47 ohm

19

and C374 from 10pF to 33pF.

20

Delete JP27, R317, C392.

21

Delete R297.

22

Change RTC battery and connector.

23

Change C413 and 414 package from 0603 to 0402.

24 27 2/28 DB --> SI

Add JP28 for USB card reader.

25 15 3/1 DB --> SI

Change R105 from 22 ohm to 0 ohm.

26 06 3/1 DB --> SI

Delete C49 and remount C46.

27 26 3/2 DB --> SI

Change JP16 and JP17 Audio Jack.

28

Add R405.

29 27 3/8 DB --> SI

Change USB connector (JP19) type.

10
19
19
20
22
24
24

27

28

28
28
28
28
30
06
30
30
28

24

26
24
19
28

04 3/6 DB --> SI

2/8
2/5
2/5
2/5
2/13
2/12
2/8

2/12

2/8

2/8
2/8
2/8
2/8
2/5
2/14
2/14
2/14
2/16

2/16

2/16
2/16
2/26
2/26

DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI

DB --> SI

DB --> SI

DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI

DB --> SI

DB --> SI
DB --> SI
DB --> SI
DB --> SI

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-1

LA-3732P

1

40 40Wednesday, March 14, 2007

0.2

of