Acer LA-3161P Schematics

A

Desert Eagle

B

C

D

E

1 1

LA-3161P

Compal confidential

2 2

HEL80/HEL81 Schematics Document

Mobile Yonah uFCPGA with Intel
Calistoga_GM/PM+ICH7-M

3 3

Thursday, February 23, 2006

REV:0.3

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

HEL80 LA-3161P

E

0.3

of

143

A

B

C

D

E

Compal Confidential

Model Name : HEL80

Fan Control

page 4

File Name : LA-3161P

ZZZ1

1 1

15W_PCB

LCD Conn.

page 16

CRT & TV-out

page 16

LVDS

H_A#(3..31)

Yonah

uPGA-478 Package

page 4-6

FSB

533/667MHz

Intel 945PM/GM

H_D#(0..63)

uFCBGA-1466

PCI-Express

page 7-12

Thermal Sensor

ADM1032

page 4

Memory BUS(DDRII)

Dual Channel

1.8V DDRII 400/533

nVidia G73M

VGA board Conn.

page 17

2 2

IDSEL:AD16
(PIRQE#,
GNT#0,
REQ#0)

IEEE 1394

VT6311S

page 25

1394 Conn.

page 25

3 3

IDSEL:AD20
(PIRQA/B#,
GNT#2,
REQ#2)

Slot 0

page 24

CardBus

ENE CB714

page 23

3 in 1
socket

page 24

3.3V 33 MHz

S-ATA

S-ATA Bridge

Marvell 8040

S-ATA HDD
Conn.

page 22

page 22

PCI BUS

3.3V ATA-100

IDE

CDROM
Conn.

Intel ICH7-M

page 22

PATA Conn.

page 22

DMI

BGA-652

page 18-21

LPC BUS

3.3V 24.576MHz/48Mhz

3.3V 48MHz

New Card
Socket

page 35

PCI Express

TPM1.2

SLB9635 TT 1.2

page 35

MINI CARD x2

ENE KB910L

page 31

INT KB /PWR BTN /Debug Port

page 30

D2D /CMOS /FP /LID /KILL#

4 4

page 33

Int.KBD

page 30

CIR

page 35

Touch Pad

page 34

BIOS

page 32

Clock Generator

SLG8LP465VTR

page 15

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

MDC 1.5
Conn

page 27

HD Audio

USB 2.0

USB port 1

LAN RJ45

page 27

page 26

Realtek
LAN 8111B

page 26

DC-IN'

BATT OVP

CHARGER

+3/5 VAWL

page 13,14

HD Codec

ALC883

USB Conn. x1

page 36

page 37

page 38

page 39

page 28

Audio AMP

USB port 0

Bluetooth

page 34

Conn

DC-DC

+1.05VP/+1.8VP

+0.9VPS
/+1.5VPS /

2.5VPS

VCORE

page 29

USB port5

page 27

page 33

page 40

page 41

page 42

TP /SW /USB OC /LED

A

page 34

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/06/20 2006/06/20

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

HEL80 LA-3161P

E

0.2

of

243Thursday, F e b r u a ry 23, 2006

A

Voltage Rails

+5VS

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O MEANS ON

X MEANS OFF

+B
LDO3
LDO5

S3 : STR
S4 : STD

+5VALW
+3VALW

O

O

O

O

O

O

O

O

O

X

X

XX X

+5V

O

XX

X

S5 : SOFT OFF

1 1

External PCI Devices

Device IDSEL # REQ # / GN T # Interrupts

CardBus

AD20
AD16

2
0

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

Address

0001 011X b
1010 000X b

+3VS
+2.5VS
+1.8VS
+1.5VS+1.8V
+1.2VS
+VGA_CORE
+0.9VS
+CPU_CORE
+VCCP

OO

OO

X

X

PIRQA/B

PIRQE1394

EC SM Bus2 address

Device

ADM1032

Address

1001 100X b

SKU ID Table

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

SKU ID

0

*

1
2
3
4
5
6
7

100K +/- 5%Ra

Rb V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

Vtyp

AD_BID

0 V 0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

HEL80/81 SKU
HEL80 SKU
HEL81 SKU
TEST MODE

BOM Structure USB PORT LIST

MARK FUNCTION

NC FOR ALL@

UMA@

Internal 945GM

VGA@

External G7xM
TPM1.2

TPM@

CIR

CIR@

1394

1394@

SATA HDD

SATA@

PATA HDD

8040@

IOMP

IOMP@

15W PANEL

15W@

HP out from AMP

APA@

HP out from HP AMP

HPA@
HP@ HP out from CODEC

PORT DEVICE

0

LEFT SIDE

1

BLUE TOOTH
RIGHT SIDE

2

CMOS

3
4

RIGHT SIDE

5

FINGER PRINTER

6

NEW CARD

7TV

V

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

max

+3VALW

+CPU_CORE

+VCCP

+5VS

+3VS

+2.5VS

+1.8V

+1.8VS

+0.9VREF

+0.9VS

KB910L
SB

mA

160mA

RTL8110SBL/CL

CPU

CPU
NB

EXPRESS CARD
HDD
ODD
MDC
APA2066

36A

2.5A

9.8A
(14.7A)

1A

1.5A

1.8A

300mA

1A
TPA0211 mA
AD1986
USB PORT * 6

70mA

3A

NB 480mA
EXPRESS CARD
CLK_GEN
LCDVCC

1A

200mA

1A

VGA CARD (G7XM) 655mA
SB
R5C832
BIOS ROM
KB910L

680mA

mA

15mA

200mA

CB1410 mA

VGA CARD (G7XM) 130mA
NB

(143mA)

DDR2_DIMM 8A
NB (667Mhz)

GDDR2
VGA CARD (G7XM)

DDR2_DIMM

GDDR2

3.1A

6A

4.06A

10mA

1A

DDR2_DIMM 2A

ICH7 SM Bus address

Device

Clock Generator
(SLG8LP465VTR)

DDRII DIMM0
DDRII DIMM1

Address

1101 001Xb
1010 000Xb
1010 010Xb

+1.5V

+1.5VS

SB 40mA

NB 8.9A(13.8A)
SB 3.8A
MiniCard 1A
EXPRESS CARD 0.65A
VGA CARD (G7XM)

2A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

HEL80 LA-3161P

343Thursday, F eb r u ary 23, 2006

of

0.2

5

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>

C C

R69

56_0402_5%

1 2

+VCCP

B B

H_PROCHOT#<42>

+VCCP

R68 68_0402_5%

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_PROCHOT# OCP#

H_ADSTB#1<7>

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

H_ADS#<7>
H_BNR#<7>

H_BPRI#<7>

H_DEFER#<7>

H_DRDY#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_RS#[0..2]<7>

H_TRDY#<7>

ITP_DBRESET#<20>

H_DBSY#<7>

H_DPSLP#<19>

H_DPRSTP#<19,42>

H_DPWR#<7>

H_PWRGOOD<19>

H_CPUSLP#<7,19>

R71 1K_0402_5%@

1 2

R70 51_0402_5%

1 2

H_THERMTRIP#<7,19>

+VCCP

12

R72

56_0402_5%@

B

2

E

3 1

C

Q4

MMBT3904_SOT23@

5

H_BR0#<7>

H_HIT#<7>

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

OCP# <20>

2005/11/07

Modified Q4 part number to SB039040000.

JP1A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

TYCO_1-1674770-2_Yonah~D

ME@

4

YONAH

DATA GROUP

MISC

LEGACY CPU

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

3

This shall place near CPU

H_D#[0..63] <7>

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

J26
M26
V23
AC20

H23
M24
W24
AD23
G22
N25
Y25
AE24

A6
A5
C4
B3
C6
B4

D5
A3

H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

H_A20M# <19>
H_FERR# <19>
H_IGNNE# <19>
H_INIT# <19>
H_INTR <19>
H_NMI <19>

H_STPCLK# <19>
H_SMI# <19>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

ITP_DBRESET#

R82 200_0402_5%@

1 2

2005/10/06 2006/10/06

ITP_TDI
ITP_TMS
ITP_TDO
ITP_BPM#5
ITP_TRST#
ITP_TCK

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4

Thermal Sensor ADM1032AR

2200P_0402_50V7K

+3VS

EN_FAN1<31>

Compal Secret Data

Deciphered Date

2

+VCCP

R130 56_0402_5%

1 2

R129 56_0402_1%
R128 56_0402_5%

1 2

R127 56_0402_5%

1 2

R119 56_0402_5%

1 2

R120 56_0402_5%

1 2

T14

PAD

T18

PAD

T20

PAD

T21

PAD

T17

PAD

T19

PAD

+3VS

2

C405

0.1U_0402_16V4Z

C406

1 2

R303

1 2

10K_0402_5%

+VCC_FAN1
EN_FAN1

1

U24

1

VDD

2

H_THERMDC

THERM#

Note : ADM1032 has no SO8 lead free ones.Only MSO8

+5VS

FAN_SPEED1<31>

2

D+

3

D­THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

Address:100_1100

C399 10U_1206_16V4Z

1 2

U23

1

VEN

2
3
4

GND

VIN

GND
GND

VO

GND

VSET

G993P1UF_SOP8

+3VS

1

EC_SMB_CK2

8

SCLK

SDATA

ALERT#

8
7
6
5

12

R297
10K_0402_5%

1

C402
1000P_0402_50V7K

2

Title

Size Document Number Rev

Custom

Date: Sheet

EC_SMB_DA2H_THERMDA

7
6
5

+5VS

D16

1SS355_SOD323

40mil

+VCC_FAN1

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

HEL80 LA-3161P

12

1

EC_SMB_CK2 <31>
EC_SMB_DA2 <31>

D15

1N4148_SOT23

C397

1 2

10U_1206_16V4Z

C401

1 2

1000P_0402_50V7K

1
2
3

4
5

ACES_85205-03001

1

2

3

1
2
3

GND
GND

JP2

of

443Thursday, F e b r u a ry 23, 2006

0.2

5

4

3

2

1

D D

+CPU_GTLREF

Close to CPU pin AD26
within 500mils.

+VCCP

12

R79
1K_0402_1%

12

R67
2K_0402_1%

+CPU_CORE

R126
100_0402_1%

1 2

R134
100_0402_1%

1 2

Close to CPU pin
within 500mils.

VCCSENSE

VSSENSE

+1.5VS

0.01U_0402_16V7K

C146

1

2

1

C144
10U_0805_10V4Z

2

+VCCP

VCCSENSE
VSSENSE

VCCSENSE<42>
VSSENSE<42>

Trace / Width = 4 / 25 mils Trace / Width = 18 / 50 mils

H_PSI#<42>

CPU_VID0<42>
CPU_VID1<42>
CPU_VID2<42>

C C

B B

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

0

12

R80

27.4_0402_1%

R81

12

54.9_0402_1%

R123

12

27.4_0402_1%

1

R131

COMP 0/2Trace / Width = 18 / 25 mils

CPU_BSEL0

1

1

Resistor placed within

12

0.5" of CPU pin.Trace
should be at least 25
mils away from any

54.9_0402_1%

other toggling signal.

CPU_VID3<42>
CPU_VID4<42>
CPU_VID5<42>
CPU_VID6<42>

+CPU_GTLREF

CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>

+CPU_CORE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

COMP 1/3Trace / Width = 5 / 25 mils

JP1B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

T6

VCCP

R6

VCCP

K21

VCCP

J21

VCCP

M21

VCCP

N21

VCCP

T21

VCCP

R21

VCCP

V21

VCCP

W21

VCCP

V6

VCCP

G21

VCCP

AE6

PSI#

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF2

VID5

AE2

VID6

AD26

GTLREF

B22

BSEL0

B23

BSEL1

C21

BSEL2

R26

COMP0

U26

COMP1

U1

COMP2

V1

COMP3

E7

VCC

AB20

VCC

AA20

VCC

AF20

VCC

AE20

VCC

AB18

VCC

AB17

VCC

AA18

VCC

AA17

VCC

AD18

VCC

AD17

VCC

AC18

VCC

AC17

VCC

AF18

VCC

AF17

VCC

D2

RSVD

F6

RSVD

D3

RSVD

C1

RSVD

AF1

RSVD

D22

RSVD

C23

RSVD

C24

RSVD

AA1

RSVD

AA4

RSVD

AB2

RSVD

AA3

RSVD

M4

RSVD

N5

RSVD

T2

RSVD

V3

RSVD

B2

RSVD

C3

RSVD

T22

RSVD

B25

RSVD

TYCO_1-1674770-2_Yonah~D

ME@

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

+CPU_CORE

JP1C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

TYCO_1-1674770-2_Yonah~D

ME@

YONAH

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

HEL80 LA-3161P

543Thursday, F e b r u a ry 23, 2006

1

0.2

of

5

4

3

2

1

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

C C

Place these capacitors on L8
(Sorth side,Secondary Layer)

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C411
22U_0805_6.3V6M

C416
22U_0805_6.3V6M

C207
22U_0805_6.3V6M

C174
22U_0805_6.3V6M

1

C417
22U_0805_6.3V6M

2

1

C212
22U_0805_6.3V6M

2

1

C192
22U_0805_6.3V6M

2

1

C188
22U_0805_6.3V6M

2

1

C175
22U_0805_6.3V6M

2

1

C437
22U_0805_6.3V6M

2

1

C428
22U_0805_6.3V6M

2

1

C442
22U_0805_6.3V6M

2

1

C193
22U_0805_6.3V6M

2

1

C201
22U_0805_6.3V6M

2

1

C412
22U_0805_6.3V6M

2

1

C196
22U_0805_6.3V6M

2

1

C443
22U_0805_6.3V6M

2

1

C409
22U_0805_6.3V6M

2

1

C195
22U_0805_6.3V6M

2

1

C202
22U_0805_6.3V6M

2

1

C191
22U_0805_6.3V6M

2

1

C211
22U_0805_6.3V6M

2

1

C427
22U_0805_6.3V6M

2

1

C200
22U_0805_6.3V6M

2

1

C206
22U_0805_6.3V6M

2

1

C189
22U_0805_6.3V6M

2

1

C204
22U_0805_6.3V6M

2

1

C410
22U_0805_6.3V6M

2

1

C208
22U_0805_6.3V6M

2

1

C438
22U_0805_6.3V6M

2

1

C199
22U_0805_6.3V6M

2

1

C205
22U_0805_6.3V6M

2

Mid Frequence Decoupling

+CPU_CORE

ESR <= 1.5m ohm
Capacitor > 1980uF

C431

1

+

C413

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1

1

+

+

2

C415

2

330U_D2E_2.5VM_R9

North Side Secondary

1

+

South Side Secondary

B B

C414

C198

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

+

+

C197

2

2

330U_D2E_2.5VM_R9

1

1

+VCCP

1

+

C131

220U_D2_2VMR15

A A

5

2

1

C209

0.1U_0402_16V4Z

2

1

C176

0.1U_0402_16V4Z

2

1

2

4

C178

0.1U_0402_16V4Z

1

C177

0.1U_0402_16V4Z

2

1

C210

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C213

0.1U_0402_16V4Z

2

3

Place these inside
socket cavity on L8
(North side
Secondary)

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CPU Bypass capacitors

HEL80 LA-3161P

1

of

643Thursday, F e b r u a ry 23, 2006

0.2

5

Note : 2005/12/26 modify pn

4

U22

3

2

1

PM : SA00000KDC0

H_D#[0..63]<4>

D D

C C

+VCCP

12

R30

54.9_0402_1%

R31

54.9_0402_1%

+VCCP

R34

R38

12

12

R28

24.9_0402_1%

12

100_0402_1%

12

200_0603_1%

B B

A A

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
+H_SWNG0
+H_SWNG1

12

R24

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / +H_VREF / +H_SWNG0 /
+H_SWNG1 trace width and spacing is 10/20.

+H_VREF

1

C24

2

0.1U_0402_16V4Z

5

GM : SA0000059H0

U22A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_FCBGA1466~D

UMA@

H9

HA3#

C9

HA4#

E11

HA5#

G11

HA6#

F11

HA7#

G12

HA8#

F9

HA9#

H11

HA10#

J12

HA11#

G14

HA12#

D9

HA13#

J14

HA14#

H13

HA15#

J15

HA16#

F14

HA17#

D12

HA18#

A11

HA19#

C11

HA20#

A12

HA21#

A13

HA22#

E13

HA23#

G13

HA24#

F12

HA25#

B12

HA26#

B14

HA27#

C12

HA28#

A14

HA29#

C14

HA30#

D14

HA31#

D8

HREQ#0

G8

HREQ#1

B8

HREQ#2

F8

HREQ#3

A8

HREQ#4

B9

HADSTB#0

C13

HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#
HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R25

12

R29

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

221_0603_1%

100_0402_1%

HOST

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

+H_SWNG0

1

C16

2

0.1U_0402_16V4Z

4

+VCCP+VCCP

R22

R23

12

221_0603_1%

12

100_0402_1%

H_A#[3..31] <4>

H_REQ#[0..4] <4>

H_ADSTB#0 <4>
H_ADSTB#1 <4>

CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0..3] <4>

H_DSTBP#[0..3] <4>

H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>

H_RESET# <4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
H_DEFER# <4>
H_HITM# <4>
H_HIT# <4>
H_LOCK# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4,19>

H_RS#[0..2] <4>

+H_SWNG1

1

2

0.1U_0402_16V4Z

PM

VGA@

DMI_TXN0<20>
DMI_TXN1<20>
DMI_TXN2<20>
DMI_TXN3<20>

DMI_TXP0<20>
DMI_TXP1<20>
DMI_TXP2<20>
DMI_TXP3<20>

DMI_RXN0<20>
DMI_RXN1<20>
DMI_RXN2<20>
DMI_RXN3<20>

DMI_RXP0<20>
DMI_RXP1<20>
DMI_RXP2<20>
DMI_RXP3<20>

M_CLK_DDR0<13>
M_CLK_DDR1<13>
M_CLK_DDR2<14>
M_CLK_DDR3<14>

M_CLK_DDR#0<13>
M_CLK_DDR#1<13>
M_CLK_DDR#2<14>
M_CLK_DDR#3<14>

DDR_CKE0_DIMMA<13>
DDR_CKE1_DIMMA<13>
DDR_CKE2_DIMMB<14>
DDR_CKE3_DIMMB<14>

DDR_CS0_DIMMA#<13>
DDR_CS1_DIMMA#<13>
DDR_CS2_DIMMB#<14>
DDR_CS3_DIMMB#<14>

T12
T1

+1.8V

R33 80.6_0402_1%
R32 80.6_0402_1%

R93
0_0402_5%

DPRSLPVR<20,42>

PLT_RST#<17,18,20,22,26,27,31,35>

C9

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

M_ODT0<13>
M_ODT1<13>
M_ODT2<14>
M_ODT3<14>

1 2
1 2

+DDR_MCH_REF

PM_BMBUSY#<20>
PM_EXTTS#0<13,14>

12

H_THERMTRIP#<4,19>

ICH_POK<20,31>

R60 100_0402_1%

MCH_ICH_SYNC#<18>

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

+DDR_MCH_REF PM_EXTTS#1

2005/10/06 2006/10/06

PAD
PAD

1

2

12

C14

0.1U_0402_16V4Z

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
ICH_POK
PLTRST_R#

+1.8V

12

R27
100_0402_1%

12

R26
100_0402_1%

Compal Secret Data

U22B

AE35
AF39
AG35
AH39

AC35
AE39
AF35
AG39

AE37
AF41
AG37
AH41

AC37
AE41
AF37
AG41

AY35

AR1

AW7

AW40
AW35

AT1
AY7

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20

AF10
BA13

BA12
AY20
AU21

AV9
AT9

AK1

AK41

G28

F25

H26

G6
AH33
AH34

K28

CALISTOGA_FCBGA1466~D

UMA@

Deciphered Date

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SM_RCOMPN
SM_RCOMPP

SM_VREF0
SM_VREF1

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

ICH_SYNC#

DMI

2

Description at page 11.

MCH_CLKSEL0

K16

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

DDR MUXING

PM

CLK_REQ#

NC10

NC11

NC12

NC13

NC14

NC15

NC16

NC17

NC18

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

Title

Size Document Number Rev

Custom

Date: Sheet

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

CLK_MCH_DREFCLK#

A27

CLK_MCH_DREFCLK

A26

CLK_MCH_SS CDREF CLK#

C40

CLK_MCH_SSCDREFCLK

D41

MCH_CLKREQ#

H32

A3

NC0

A39

NC1

A4

NC2

A40

NC3

AW1

NC4

AW41

NC5

AY1

NC6

BA1

NC7

BA2

NC8

BA3

NC9

BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

HEL80/81 LA-3161P

PM_EXTTS#0

Compal Electronics, Inc.

MCH_CLKSEL0 <15>
MCH_CLKSEL1 <15>
MCH_CLKSEL2 <15>

T9

PAD

T3

PAD

CFG5 <11>

T10

PAD

CFG7 <11>

T7

PAD

CFG9 <11>
CFG10 <11>
CFG11 <11>
CFG12 <11>
CFG13 <11>

T4

PAD

T8

PAD

CFG16 <11>

T2

PAD

CFG18 <11>
CFG19 <11>
CFG20 <11>

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

CLK_MCH_DREFCLK# <15>
CLK_MCH_DREFCLK <15>

CLK_MCH_SSCDREFCLK# <15>
CLK_MCH_SSCDREFCLK <15>

MCH_CLKREQ# <15>

R51

10K_0402_5%

R56

10K_0402_5%@

Calistoga (1/6)

1

+3VS

12

12

0.2

of

743Thursda y, Fe br uary 23, 2006

5

D D

4

3

2

1

DDR_A_BS#0<13>
DDR_A_BS#1<13>
DDR_A_BS#2<13>

DDR_A_DM[0..7]<13>

DDR_A_DQS[0..7]<13>

C C

DDR_A_DQS#[0..7]<13>

DDR_A_MA[0..13]<13>

B B

DDR_A_CAS#<13>
DDR_A_RAS#<13>

DDR_A_WE#<13>

T6 PAD
T13 PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

U22D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

UMA@

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>

DDR_B_BS#0<14>
DDR_B_BS#1<14>
DDR_B_BS#2<14>

DDR_B_DM[0..7]<14>

DDR_B_DQS[0..7]<14>

DDR_B_DQS#[0..7]<14>

DDR_B_MA[0..13]<14>

DDR_B_CAS#<14>

DDR_B_RAS#<14>

DDR_B_WE#<14>

T5 PAD
T11 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U22E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

UMA@

AK39

SB_DQ0

AJ37

SB_DQ1

AP39

SB_DQ2

AR41

SB_DQ3

AJ38

SB_DQ4

AK38

SB_DQ5

AN41

SB_DQ6

AP41

SB_DQ7

AT40

SB_DQ8

AV41

SB_DQ9

AU38

SB_DQ10

AV38

SB_DQ11

AP38

SB_DQ12

AR40

SB_DQ13

AW38

SB_DQ14

AY38

SB_DQ15

BA38

SB_DQ16

AV36

SB_DQ17

AR36

SB_DQ18

AP36

SB_DQ19

BA36

SB_DQ20

AU36

SB_DQ21

AP35

SB_DQ22

AP34

SB_DQ23

AY33

SB_DQ24

BA33

SB_DQ25

AT31

SB_DQ26

AU29

SB_DQ27

AU31

SB_DQ28

AW31

SB_DQ29

AV29

SB_DQ30

AW29

SB_DQ31

AM19

SB_DQ32

AL19

SB_DQ33

AP14

SB_DQ34

AN14

SB_DQ35

AN17

SB_DQ36

AM16

SB_DQ37

AP15

SB_DQ38

AL15

SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR SYS MEMORY B

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (2/6)

HEL80/81 LA-3161P

1

0.2

of

843Thursda y, Fe br uary 23, 2006

5

D D

4

3

2

1

+1.5VS_PCIE

R59

24.9_0402_1%

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PEG_RXP[0..15] <17>

PEG_RXN[0..15] <17>

2/20 modified to 0402_X7R

PEG_M_TXN0
PEG_M_TXN1
PEG_M_TXN2
PEG_M_TXN3
PEG_M_TXN4
PEG_M_TXN5
PEG_M_TXN6
PEG_M_TXN7
PEG_M_TXN8
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN11
PEG_M_TXN12
PEG_M_TXN13
PEG_M_TXN14
PEG_M_TXN15

PEG_M_TXP0
PEG_M_TXP1
PEG_M_TXP2
PEG_M_TXP3
PEG_M_TXP4
PEG_M_TXP5
PEG_M_TXP6
PEG_M_TXP7
PEG_M_TXP8
PEG_M_TXP9
PEG_M_TXP10
PEG_M_TXP11
PEG_M_TXP12
PEG_M_TXP13
PEG_M_TXP14
PEG_M_TXP15

PEG_M_TXP[0..15] <17>

PEG_M_TXN[0..15] <17>

U22C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

R58 1.5K_0402_1%

TV_COMPS
TV_LUMA
TV_CRMA

CRT_B<16>
CRT_G<16>
CRT_R<16>

12

LVDSA0+
LVDSA1+
LVDSA2+

LVDSA0­LVDSA1­LVDSA2-

LVDSB0+
LVDSB1+
LVDSB2+

LVDSB0­LVDSB1­LVDSB2-

LVDSAC+
LVDSAC­LVDSBC+
LVDSBC-

GMCH_ENBKL

EDID_CLK_LCD
EDID_DAT_LCD
GMCH_LVDDEN

R47 4.99K_0402_1%

3VDDCCL
3VDDCDA

VSYNC
HSYNC
CRT_B

CRT_G
CRT_R

CRT_IREF

10 mils

LVDSA0+<16>
LVDSA1+<16>
LVDSA2+<16>

LVDSA0-<16>
LVDSA1-<16>
LVDSA2-<16>

LVDSB0+<16>
LVDSB1+<16>
LVDSB2+<16>

LVDSB0-<16>
LVDSB1-<16>
LVDSB2-<16>

LVDSAC+<16>
LVDSAC-<16>
LVDSBC+<16>
LVDSBC-<16>

C C

TV_COMPS

R286 150_0402_1%UMA@
R287 150_0402_1%UMA@
R288 150_0402_1%UMA@

B B

R289 150_0402_1%UMA@
R290 150_0402_1%UMA@
R291 150_0402_1%UMA@

12

TV_LUMA

12

TV_CRMA

12

CRT_VSYNC<16>
CRT_HSYNC<16>

CRT_VSYNC
CRT_HSYNC

CRT_R

12

CRT_G

12

CRT_B

12

+3VS

R50 39_0402_5%UMA@
R53 39_0402_5%UMA@

GMCH_LVDDEN<16>

TV_COMPS<16>
TV_LUMA<16>
TV_CRMA<16>

1 2
1 2

GMCH_ENBKL<16>

3VDDCCL<16>

3VDDCDA<16>

R49 255_0402_1%

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

12

C35
C33
C32

A16
C18
A19

12

B16
B18
B19

K30

C26
C25

H23
G23
E23
D23
C22
B22
A21
B21

LIBG
LVBG
LVREFH
LVREFL

TVDAC_A
TVDAC_B
TVDAC_C

J20

TV_IREF
TV_IRTNA

TV_IRTNB
TV_IRTNC

J29

TV_DCONSEL1
TV_DCONSEL0

DDCCLK
DDCDATA

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

UMA@

LVDS

TV CRT

EXP_COMPI

EXP_COMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

PCI-EXPRESS GRAPHICS

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D40
D38

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

10 mils

PEGCOMP

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

C180 0.1U_0402_10V7KVGA@
C148 0.1U_0402_10V7KVGA@
C163 0.1U_0402_10V7KVGA@
C135 0.1U_0402_10V7KVGA@
C182 0.1U_0402_10V7KVGA@
C150 0.1U_0402_10V7KVGA@
C167 0.1U_0402_10V7KVGA@
C137 0.1U_0402_10V7KVGA@
C184 0.1U_0402_10V7KVGA@
C152 0.1U_0402_10V7KVGA@
C161 0.1U_0402_10V7KVGA@
C139 0.1U_0402_10V7KVGA@
C186 0.1U_0402_10V7KVGA@
C154 0.1U_0402_10V7KVGA@
C165 0.1U_0402_10V7KVGA@
C141 0.1U_0402_10V7KVGA@

C179 0.1U_0402_10V7KVGA@
C147 0.1U_0402_10V7KVGA@
C162 0.1U_0402_10V7KVGA@
C134 0.1U_0402_10V7KVGA@
C149 0.1U_0402_10V7KVGA@
C181 0.1U_0402_10V7KVGA@
C166 0.1U_0402_10V7KVGA@
C136 0.1U_0402_10V7KVGA@
C183 0.1U_0402_10V7KVGA@
C160 0.1U_0402_10V7KVGA@
C151 0.1U_0402_10V7KVGA@
C138 0.1U_0402_10V7KVGA@
C185 0.1U_0402_10V7KVGA@
C153 0.1U_0402_10V7KVGA@
C140 0.1U_0402_10V7KVGA@
C164 0.1U_0402_10V7KVGA@

12

12

R293

2.2K_0402_5%

UMA@

EDID_CLK_LCD<16>

A A

EDID_DAT_LCD<16>

5

R294

2.2K_0402_5%

UMA@

EDID_CLK_LCD

EDID_DAT_LCD

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (3/6)

HEL80/81 LA-3161P

1

0.2

of

943Thursda y, Fe br uary 23, 2006

5

4

3

2

1

+VCCP

21

D18

RB751V_SOD323

12

+2.5VS

D D

+VCCP

12/09 Modified

1

C23

2

4.7U_0805_10V4Z

1

2

C15

0.22U_0603_16V7K

C89

1

C54

2

2.2U_0805_10V6K

1

C390

2

0.47U_0603_16V4Z

1

2

+1.5VS

1

+

2

MCH_A6

MCH_D2

C8

MCH_AB1

1

2

0.47U_0603_16V4Z

+1.5VS

21

220U_D2_2VMR15

D17

RB751V_SOD323

12

+3VS

R298

10_0402_5%

C C

B B

A A

12/09 Modified

C93

0.22U_0603_16V7K

U22H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

UMA@

P O W E R

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0

VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

R299

10_0402_5%

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

1 2

C400

0.1U_0402_16V4Z

+2.5VS

W=60 mils

C130

220U_D2_2VMR15

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL
+3VS_TVBG

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS

+1.5VS_TVDAC

1

C396

2

0.1U_0402_16V4Z

+1.5VS

1

C393

2

+1.5VS_PCIE

1

+

2

1

C392

2

10U_0805_10V4Z

0.1U_0402_16V4Z

C103

1

2

+3VS

R63

0_0805_5%

12

+1.5VS

1

1

C107

2

2

10U_0805_10V4Z

10U_0805_10V4Z

L1
MBK1608301YZF_0603

1 2

1

C64

C69

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Calistoga

+2.5VS

1

+

C187
220U_D2_4VM

2

@

R285

0_0603_5%

1

1

C60

C49

2

2

0.022U_0402_16V7K

0.1U_0402_16V4Z

+3VS+3VS_TVBG

12

PCI-E/MEM/PSB PLL decoupling

+2.5VS

1

1

C398

0.01U_0402_16V7K

close pin A38

+1.5VS_DPLLA +1.5VS_DPLLB

C73

0.1U_0402_16V4Z

C96

0.1U_0402_16V4Z

+1.5VS_MPLL

C10

0.1U_0402_16V4Z

C100

2

2

MBK1608301YZF_0603

1

1

+

C394

330U_D2E_2.5VM

2

2

UMA@

MBK1608301YZF_0603

1

1

C59

C51

2

2

0.022U_0402_16V7K

MBK1608301YZF_0603

1

1

C50

C391

2

2

0.022U_0402_16V7K

1

1

C95

2

2

10U_0805_10V4Z

1

1

C6

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

close pin G41

L20

12

C99

0.1U_0402_16V4Z

L19

12

0.1U_0402_16V4Z

L18

12

0.1U_0402_16V4Z

+1.5VS+1.5VS_3GPLL

R61
0_0603_5%

12

C108

@

0.1U_0402_16V4Z

R20
0_0603_5%

12

45mA Max. 45mA Max.

+3VS_TVDACA+3VS+3VS_TVDACB

1

2

+3VS+3VS_TVDACC

+1.5VS_TVDAC +1.5VS

C65

1

2

0.1U_0402_16V4Z

1

2

+2.5VS

1

C97

2

0.1U_0402_16V4Z

MBK1608301YZF_0603

1

1

+

C98
330U_D2E_2.5VM

2

2

UMA@

MBK1608301YZF_0603

1

C43

C42

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

R292
0_0603_5%

1

C35

2

0.022U_0402_16V7K

+1.5VS_HPLL

1

C11

C7

2

0.1U_0402_16V4Z
10U_0805_10V4Z

L2

L17

R21
0_0603_5%

1

2

12

12

12

@

+3VS

1

+

C389
220U_D2_4VM

2

@

1

C395

2

10U_0805_10V4Z

12

+1.5VS+1.5VS

+1.5VS+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (4/6)

HEL80/81 LA-3161P

1

0.2

of

10 43Thursday, February 23, 2006

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

1

C47

2

0.22U_0603_16V7K

1

C45

2

10U_0805_10V4Z

C C

C18

220U_D2_2VMR15

C77

220U_D2_2VMR15

B B

@

1

C57

C22

2

2

0.22U_0603_16V7K

0.22U_0603_16V7K

1

1

C94

C29

2

2

1U_0603_10V4Z

10U_0805_10V4Z

1

+

2

1

+

2

+VCCP

U22F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

UMA@

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

+1.8V

1

1

C13

C12

2

2

0.47U_0603_16V4Z

0.47U_0603_16V4Z

Place near pin AV1 & AJ1

A A

+VCCP

AA33

AA32

AA31

AA30

AA29

AB28
AA28

AB23
AA23

AC22
AB22

AC21
AA21

AC20
AB20

AB19
AA19

U22G

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5
VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14
VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22
VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

VCC33
VCC34

Y29

VCC35

W29

VCC36

V29

VCC37

U29

VCC38

R29

VCC39

P29

VCC40

M29

VCC41

L29

VCC42
VCC43
VCC44

Y28

VCC45

V28

VCC46

U28

VCC47

T28

VCC48

R28

VCC49

P28

VCC50

N28

VCC51

M28

VCC52

L28

VCC53

P27

VCC54

N27

VCC55

M27

VCC56

L27

VCC57

P26

VCC58

N26

VCC59

L26

VCC60

N25

VCC61

M25

VCC62

L25

VCC63

P24

VCC64

N24

VCC65

M24

VCC66
VCC67
VCC68

Y23

VCC69

P23

VCC70

N23

VCC71

M23

VCC72

L23

VCC73
VCC74
VCC75

Y22

VCC76

W22

VCC77

P22

VCC78

N22

VCC79

M22

VCC80

L22

VCC81
VCC82
VCC83

W21

VCC84

N21

VCC85

M21

VCC86

L21

VCC87
VCC88
VCC89

Y20

VCC90

W20

VCC91

P20

VCC92

N20

VCC93

M20

VCC94

L20

VCC95
VCC96
VCC97

Y19

VCC98

N19

VCC99

CALISTOGA_FCBGA1466~D

UMA@

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

MCH_AT41
MCH_AM41

1

1

C102

C101

2

2

0.47U_0603_16V4Z

0.47U_0603_16V4Z

Place near pin AT41 & AM41

1

1

C17

C19

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Place near pin BA23

1

C25

2

0.47U_0603_16V4Z

1

1

C36

C76

2

2

10U_0805_10V4Z

10U_0805_10V4Z

1

C91

2

0.47U_0603_16V4Z

Place near pin BA15

1

C88

2

0.1U_0402_16V4Z

1

+

C72
220U_D2_4VM

2

@

CFG[2:0]

CFG5

CFG7

CFG9

CFG6

PSB 4X CLK Enable 1 = Calistoga

CFG[13:12]

CFG16

C44

0.1U_0402_16V4Z

CFG10 CFG18

CFG19

SDVO_CTRLDATA

1

2

CFG20

(PCIE/SDVO select)

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

(Default)

*

0 = Reserved

*

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

10 = 1.05V
01 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

R36 2.2K_0402_5%@

CFG5<7>

R44 2.2K_0402_5%@

CFG7<7>

R40 2.2K_0402_5%@

CFG9<7>
CFG10<7>
CFG11<7>
CFG12<7>
CFG13<7>
CFG16<7>

CFG18<7>
CFG19<7>
CFG20<7>

R41 2.2K_0402_5%@
R39 2.2K_0402_5%@
R37 2.2K_0402_5%@
R42 2.2K_0402_5%@
R35 2.2K_0402_5%@

R52 1K_0402_5%@
R54 1K_0402_5%@
R55 1K_0402_5%@

*

(Default)

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

(Default)

(Default)

*

(Default)

*

(Default)

(Default)

*

*

(Default)

*

+3VS

*

*

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (5/6)

HEL80/81 LA-3161P

1

0.2

of

11 43Thursday, Fe br uary 23, 2006

5

4

3

2

1

U22I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

D D

C C

B B

A A

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

UMA@

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U22J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

UMA@

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (6/6)

HEL80/81 LA-3161P

1

0.2

of

12 43Thursday, Fe br uary 23, 2006

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>
DDR_A_DM[0..7]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..13]<8>

D D

Layout Note:
Place near JP41

+1.8V

2.2U_0805_10V6K

2.2U_0805_10V6K
C84

1

2

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C70

B B

DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1

DDR_A_BS#0
DDR_A_MA10

DDR_A_MA1
DDR_A_MA3
DDR_A_MA5

A A

DDR_A_MA8

DDR_A_MA9
DDR_A_MA12
DDR_A_BS#2
DDR_CKE0_DIMMA

1

2

0.1U_0402_16V4Z

1

2

C63

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

R43

1 2

R46

1 2

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

5

2.2U_0805_10V6K

C83

0.1U_0402_16V4Z

1

2

C56

RP1

56_0402_5%

56_0402_5%

RP7

RP10

C27

1

2

0.1U_0402_16V4Z

1

2

C46

+0.9VS

2.2U_0805_10V6K

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

C90

1

2

0.1U_0402_16V4Z

1

2

C78

RP2

RP6

RP9

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

2.2U_0805_10V6K

0.1U_0402_16V4Z

C26

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C38

C31

DDR_A_RAS#

18

DDR_CS0_DIMMA#

27

M_ODT0

36

DDR_A_MA13

45

DDR_A_BS#1

45

DDR_A_MA0

36

DDR_A_MA2

27

DDR_A_MA4

18

DDR_A_MA6

45

DDR_A_MA7

36

DDR_A_MA11

27

DDR_CKE1_DIMMA

18

0.1U_0402_16V4Z

C85

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C52

+DDR_MCH_REF1<14>

0.1U_0402_16V4Z

C55

0.1U_0402_16V4Z

1

2

C61

4

0.1U_0402_16V4Z
C81

C41

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C40

C75

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

4

0.1U_0402_16V4Z

1

2

C67

+DDR_MCH_REF1

0.1U_0402_16V4Z

1

2

C34

+1.8V

12

12

R92
1K_0402_1%

R87
1K_0402_1%

+DDR_MCH_REF1

2.2U_0805_10V6K

1

C171

2

3

+1.8V

JP3

1

VREF

3

DDR_A_D4

0.1U_0402_16V4Z

1

C158

2

DDR_CKE0_DIMMA<7>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<7>

M_ODT1<7>

CLK_SMBDATA<14,15>

CLK_SMBCLK<14,15>

DDR_A_D1
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D14
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D9 DDR_A_D11

DDR_A_D15 DDR_A_D10

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D61 DDR_A_D57

DDR_A_D60
DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

11/9 Modify pn to SP070006V00

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

ME@

SO-DIMM A

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA0
SA1

2

NC

NC

A7
A6

A4
A2
A0

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

10K_0402_5%

+1.8V

Top side

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

2

DDR_A_D6
DDR_A_D0

DDR_A_DM0
DDR_A_D5

DDR_A_D7
DDR_A_D13

DDR_A_D12
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D39
DDR_A_D38

DDR_A_DM4
DDR_A_D34

DDR_A_D33
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R18

1

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

PM_EXTTS#0 <7,14>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

12

R16
10K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

HEL80 LA-3161P

1

of

13 43Thursday, Fe br uary 23, 2006

0.2

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>
DDR_B_DM[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..13]<8>

D D

C C

B B

A A

Layout Note:
Place near JP42

+1.8V

2.2U_0805_10V6K

2.2U_0805_10V6K

1

2

0.1U_0402_16V4Z

1

2

C79

R48
R45

56_0804_8P4R_5%

2.2U_0805_10V6K

C21

C87

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C74

RP3

18
27
36
45

56_0804_8P4R_5%

1 2

56_0402_5%

56_0402_5%

1 2

RP8

45
36
27
18

56_0804_8P4R_5%

RP12

18
27
36
45

5

C28

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C68

DDR_B_CAS#
DDR_B_WE#

M_ODT3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA1
DDR_B_MA3
DDR_B_MA5
DDR_B_MA9

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA8

2.2U_0805_10V6K

1

2

0.1U_0402_16V4Z

1

2

C32

+0.9VS

56_0804_8P4R_5%

2.2U_0805_10V6K

C92

0.1U_0402_16V4Z

1

2

C39

RP4

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP5

4 5
3 6
2 7
1 8

RP11

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

C20

1

2

1

2

C53

0.1U_0402_16V4Z
C66

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C80

DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#DDR_CS3_DIMMB#
DDR_B_RAS#

DDR_B_BS#1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4

DDR_B_MA7
DDR_B_MA11
DDR_B_MA6
DDR_CKE3_DIMMB

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C71

1

2

0.1U_0402_16V4Z

1

1

2

2

C58

C48

0.1U_0402_16V4Z

C86

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C62

C82

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

4

C30

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C37

C33

3

+1.8V

JP4

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB<7>

DDR_B_BS#2<8>

DDR_B_BS#0<8>
DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

CLK_SMBDATA<13,15>

CLK_SMBCLK<13,15>

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D59

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

ME@

SO-DIMM B

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

2

+1.8V

+DDR_MCH_REF1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SA1

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D21DDR_B_D17
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24DDR_B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

R19

10K_0402_5%

12

R17

1 2

10K_0402_5%

2.2U_0805_10V6K

0.1U_0402_16V4Z

C172

1

1

2

2

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

PM_EXTTS#0 <7,13>

DDR_CKE3_DIMMB <7>

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

+3VS

1

+DDR_MCH_REF1 <13>

C159

11/9 Modify pn to SP07000BY00

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

HEL80 LA-3161P

14 43Thursday, Fe br uary 23, 2006

1

0.2

5

PCI

SRC

CPU

CLKSEL1

0

1

FSLA

CLKSEL0

MHz

133

166

MHz

1000

100

MHz

33.31

33.3

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

D D

FSB Frequency Selet:

CPU Driven

(Default)

*

533MHz

667MHz

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra

CLK_Rb

CLK_Re

CLK_Re

CLK_Rb

CLK_Rf

CLK_Rb

CLK_Rc

CLK_Rf

CLK_Rf

CLK_Rc

CLK_Rc

CLK_Re

+VCCP

R398

R407

8.2K_0402_5%

CPU_BSEL0<5>

CPU_BSEL1<5>

CPU_BSEL2<5>

+3VS

12

12

CLKREF1

R425

10K_0402_5%@

PCI_1394

R424
10K_0402_5%

FSA

1 2

R393
0_0402_5%

CLK_Ra

FSB

1 2

R154
0_0402_5%

CLK_Rb

R448

8.2K_0402_5%

1 2

R449
0_0402_5%

CLK_Rc

PCI_1394 = FCTSEL1

FCTSEL1
(PIN34)

C C

B B

A A

56_0402_5%@

CLK_Rd

1 2

1 2

12

R395
1K_0402_5%

12

R394

1K_0402_5%@

+VCCP

R158

1K_0402_5%@

1 2

1 2

R157
1K_0402_5%

12

R156

1K_0402_5%@

CLK_Re

+VCCP

R430

1K_0402_5%@

1 2

1 2

12

R456
1K_0402_5%

12

R439

1K_0402_5%@

CLK_Rf

PIN43

0

1

27Mout

5

MCH_CLKSEL0 <7>

MCH_CLKSEL1 <7>

CLK_MCH_DREFCLK<7>

CLK_MCH_DREFCLK#<7>

+3VS

CLK_ENABLE#<42>

VGATE<20,31,42>

MCH_CLKSEL2 <7>

CLK_48M_ICH<20>
CLK_SD_48M<23>

CLK_14M_SIO<30>

R410 10K_0402_5%

1 2

2N7002_SOT23

+3VS

12

R419
10K_0402_5%

PCI_ICH

12

R418

10K_0402_5%@

PIN47PIN44

96/100M_TDOT96CDOT96T

SRCT027MSSout

ICH_SMBDATA<20,27,35>

ICH_SMBCLK<20,27,35>

CLK_14M_ICH<20>

CLK_PCI_1394<25>

CLK_PCI_LPC<31>
CLK_PCI_TPM<35>

CLK_PCI_PCM<23>

CLK_PCI_DB<30>

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

CLK_PCI_ICH<18>

13

D

2

G

Q5

S

+3VS

12

12

PIN48

96/100M_C

SRCC0

4

+3VS

PCI6 PCI5ITP

R429

10K_0402_5%@

PCI_DB

R438

10K_0402_5%@

4

CLK_48M_ICH
CLK_SD_48M

CLK_14M_ICH

CLK_PCI_ICH

CLK_SMBDATA<13,14>

+3VS

12

R479

2.2K_0402_5%
Q22

2N7002_SOT23

D

S

1 3

G

2

2

G

1 3

D

S

Q21
2N7002_SOT23

1 2

C505 0.1U_0402_16V4Z

1 2

C492 0.1U_0402_16V4Z

R415 12_0402_5%
R400 12_0402_5%

1 2

R409 0_0402_5%UMA@

1 2

R408 0_0402_5%UMA@

CLK_SMBCLK<13,14>

+3VS

12

12

12
12

R461 33_0402_5%

1 2

R455

10K_0402_5%@

PCI_SIO

R454

10K_0402_5%@

PCI_DB=SEL_PCI6

PCI_DB

0

CLKREQ5

1 PCICLK6

12

R468

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

+CK_VDD_MAIN1

+CK_VDD_REF
+CK_VDD_48

CLK_XTAL_IN

CLK_XTAL_OUT

FSA
FSB
CLKREF1

12

PCI_1394

R43133_0402_5%

12

PCI_LPC

R43512_0402_5%

12

R43712_0402_5%

12

PCI_PCM

R44533_0402_5%

12

PCI_DB

R45333_0402_5%

12

PCI_SIO

R46433_0402_5%

12

MCH_DREFCLK
MCH_DREFCLK#

PCI_ICH

12

R42333_0402_5%

CLK_ENABLE#

CLK_SMBCLK

CLK_SMBDATA

CLKIREF

R4830_0402_5%

PIN27

3

+CK_VDD_MAIN1

1 2

+3VS

R208 0_0805_5%

1 2

+3VS

R399 0_0805_5%

U30

1

VDDSRC

49

VDDSRC

54

VDDSRC

65

VDDSRC

30

VDDPCI

36

VDDPCI

12

VDDCPU

18

VDDREF

40

VDD48

20

X1

19

X2

41

USB_48MHz/FSLA

45

FSLB/TEST_MODE/24Mhz

23

REF0/FSLC/TEST_SEL

34

PCICLK4/FCTSEL1

33

SEL_48M/PCICLK3

32

SEL_24M/PCICLK2

27

SEL_PCI6/PCICLK1

22

SEL_PCI5/REF1

43

DOTT_96MHz/27MHz_Nonspread

44

DOTC_96MHz/27MHz_spread

37

ITP_EN/PCICLK_F0

39

VTT_PWRGD#/PD

16

SMBCLK

17

SMBDAT

9

GND

4

GNDSRC

15

GNDCPU

21

GNDREF

31

GNDPCI

35

GNDPCI

42

GND48

68

GNDSRC

73

THRM_PAD

74

THRM_PAD

75

THRM_PAD

76

THRM_PAD

ICS9LPR325AKLFT_MLF72

1

C285
10U_0805_10V4Z

2

+CK_VDD_MAIN2

1

C490
10U_0805_10V4Z

2

PCI_SRC_STOP#

CPUCLKT2_ITP/SRCCLKT10LP
CPUCLKC2_ITP/SRCCLKC10LP

CLKREQ7#/48Mhz_1

CLKREQ5#/PCICLK6

CLKREQ3#/PCICLK5

LCD100/96/SRC0_TLP
LCD100/96/SRC0_CLP

1

2

1

2

VDDA

GNDA

CPU_STOP#

CPUCLKT1LP
CPUCLKC1LP

CPUCLKT0LP
CPUCLKC0LP

SRCCLKT9LP
SRCCLKC9LP

CLKREQ9#
SRCCLKT8LP
SRCCLKC8LP

CLKREQ8#
SRCCLKT7LP
SRCCLKC7LP

SRCCLKT6LP
SRCCLKC6LP

CLKREQ6#
SRCCLKT5LP
SRCCLKC5LP

SRCCLKT4LP
SRCCLKC4LP

CLKREQ4#
SRCCLKT3LP
SRCCLKC3LP

SRCCLKT2LP
SRCCLKC2LP

CLKREQ2#
SRCCLKT1LP
SRCCLKC1LP

CLKREQ1#

ICS9LPR325CKL FT_MLF72: SA00000RE20

C263

0.1U_0402_16V4Z

C507

0.1U_0402_16V4Z

7
8

25
24

11
10

14
13

6
5

3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48

1

C264

0.1U_0402_16V4Z

2

1

C506

0.1U_0402_16V4Z

2

1

C304

0.1U_0402_16V4Z

2

H_STP_PCI#
H_STP_CPU#

MCH_BCLK

1 2

R476 0_0402_5%

MCH_BCLK#

1 2

R475 0_0402_5%

CPU_BCLK

1 2

R478 0_0402_5%

CPU_BCLK#

1 2

R477 0_0402_5%

PCIE_VGA CLK_PCIE_VGA

1 2

R473 0_0402_5%VGA@

1 2

R474 0_0402_5%VGA@

MCH_3GPLL

1 2

R472 0_0402_5%

MCH_3GPLL#

1 2

R470 0_0402_5%

CLKREQ8#

R214 0_0402_5%

PCIE_SATA

1 2

R462 0_0402_5%

PCIE_SATA#

1 2

R467 0_0402_5%

SATAREQ#

1 2

PCIE_LAN#
CLKREQ_LAN#

PCIE_ICH#
CLKREQ_ICH#
PCIE_NC1 CLK_PCIE_NC1

CLKREQ_NC#
PCIE_MCARD1
PCIE_MCARD1#
CLKREQ_MCARD1#

SSCDREFCLK#

R451 0_0402_5%

1 2

R458 0_0402_5%
R447 10K_0402_5%

1 2

R434 0_0402_5%

1 2

R441 0_0402_5%
R170 10K_0402_5%

1 2

R422 0_0402_5%

1 2

R427 0_0402_5%

1 2

R412 0_0402_5%

1 2

R411 0_0402_5%

1 2

R414 0_0402_5%UMA@

1 2

R413 0_0402_5%UMA@

SLG8LP465VTR: SA00000TS00

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

1

C494

0.1U_0402_16V4Z

2

1 2

R397 1_0603_5%

1 2

R482 2.2_0603_5%

R220 2.2_0603_5%

1 2

1

C313
10U_0805_10V4Z

2

H_STP_PCI# <20>
H_STP_CPU# <20>

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_PCIE_VGA#PCIE_VGA#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#
MCH_CLKREQ#

12

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_PCIE_LANPCIE_LAN
CLK_PCIE_LAN#

12

CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_ICH#

12

CLK_PCIE_NC1#PCIE_NC1#

CLK_PCIE_MCARD1
CLK_PCIE_MCARD1#

CLK_MCH_SSCDREFCLKSSCDREFCLK
CLK_MCH_SS CDREF CLK#

2005/11/8 modify footprint to ICS954305DKLFT_MLF72 for Thermal Pad use

2

1

C278

0.1U_0402_16V4Z

2

+CK_VDD_REF

+CK_VDD_48

+3VS

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CLK_PCIE_VGA <17>
CLK_PCIE_VGA# <17>

CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>
MCH_CLKREQ# <7>
CLK_PCIE_SATA <19>
CLK_PCIE_SATA# <19>
SATAREQ# <20>

1

1

C302

0.1U_0402_16V4Z

2

Place crystal within
500 mils of CK410

CLK_XTAL_IN
CLK_XTAL_OUT

1

C301

0.1U_0402_16V4Z

2

C499 33P_0402_50V8J

12

12

Y5

14.31818MHz_20P_1BX14318BE1A

C503 33P_0402_50V8J

12

Place near U4

Place these components
near each pin within 40
mils.

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_MCH_SSCDREFCLK
CLK_MCH_SSCDREFCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_ICH

CLK_PCIE_ICH#
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

CLK_PCIE_SATA

CLK_PCIE_SATA#

CLK_PCIE_LAN <26>
CLK_PCIE_LAN# <26>

CLK_PCIE_ICH <20>
CLK_PCIE_ICH# <20>

CLK_PCIE_NC1 <35>
CLK_PCIE_NC1# <35>
CLKREQ_NC# <35>
CLK_PCIE_MCARD1 <27>
CLK_PCIE_MCARD1# <27>
CLKREQ_MCARD1# <27>

CLK_MCH_SSCDREFCLK <7>
CLK_MCH_SSCDREF CLK# <7>

Title

Size Document Number Rev

Date: Sheet

CLK_PCIE_NC1

CLK_PCIE_NC1#

CLK_PCIE_LAN

CLK_PCIE_LAN#
CLK_PCIE_MCARD1
CLK_PCIE_MCARD1#

CLKREQ8#

SATAREQ#

CLKREQ_NC#

CLKREQ_MCARD1#

Compal Electronics, Inc.

Clock generator

HEL80 LA-3161P

1

R487 49.9_0402_1%@
R486 49.9_0402_1%@

R485 49.9_0402_1%@
R484 49.9_0402_1%@

1 2

R406 49.9_0402_1%@

1 2

R405 49.9_0402_1%@

1 2

R471 49.9_0402_1%@

1 2

R469 49.9_0402_1%@

1 2

R480 49.9_0402_1%@

1 2

R481 49.9_0402_1%@

1 2

R433 49.9_0402_1%@

1 2

R442 49.9_0402_1%@

1 2

R402 49.9_0402_1%@

1 2

R401 49.9_0402_1%@

1 2

R463 49.9_0402_1%@

1 2

R466 49.9_0402_1%@
R421 49.9_0402_1%@
R428 49.9_0402_1%@
R450 49.9_0402_1%@
R457 49.9_0402_1%@

1 2

R404 49.9_0402_1%@

1 2

R403 49.9_0402_1%@

R213 10K_0402_5%
R417 10K_0402_5%
R189 10K_0402_5%
R193 10K_0402_5%

12
12

12
12

12
12
12
12

12
12
12
12

of

15 43Thursday, F e b r u a ry 23, 2006

+3VS

0.2

A

B

C

D

E

TV-OUT Conn.

12

R11

150_0402_1%

12

R4

150_0402_1%

LUMA

CRMA

COMP

2/09 Add for Compliance Engineering request

L39 FCM1608C-121T_0603

L40 FCM1608C-121T_0603

L41 FCM1608C-121T_0603

1

C3

@

2

1

1

C1

C2

@

@

2

2

8P_0402_50V8K

8P_0402_50V8K

8P_0402_50V8K

CARD_LUMA<17>

1 1

CARD_CRMA<17>

CARD_COMP<17>

TV_LUMA<9>

TV_CRMA<9>

TV_COMPS<9>

R65 0_0402_5%VGA@

R64 0_0402_5%VGA@

R66 0_0402_5%VGA@

R301 0_0402_5%UMA@
R302 0_0402_5%UMA@
R300 0_0402_5%UMA@

12

12

12

12
12
12

@

12

12

R9

R10

@

150_0402_1%

@

150_0402_1%

Pop when with internal graphics

CRT Conn.

CARD_VGA_R<17>

2 2

CARD_VGA_G<17>

CARD_VGA_B<17>

CRT_R<9>

CRT_G<9>

CRT_B<9>

R74 0_0402_5%VGA@

R76 0_0402_5%VGA@

R78 0_0402_5%VGA@

R73 0_0402_5%UMA@

R75 0_0402_5%UMA@

R77 0_0402_5%UMA@

12

12

12

12

@

12

R3

R2

@

150_0402_1%

@

150_0402_1%

12

12

12

VGA I/O PORT Conn.

VGA_DDC_DAT
VGA_DDC_CLK
JVGA_HS
JVGA_VS

RED
GREEN

BLUE

1 2

1 2

1 2

@

1

C537

2

JP6

112
334
556
778
9910
111112
131314
151516
171718
191920

G121G2

1

C538

@

2

8P_0402_50V8K

2
4
6
8
10
12
14
16
18
20

22

ACES_87216-2016

1

C539

@

2

8P_0402_50V8K

8P_0402_50V8K

RED

GREEN

BLUE

CRMA
LUMA
COMP

+3VS
+5VS

+LCDVDD

GMCH_LVDDEN<9>

L37

(60 MIL)

LVDSA0-<9>
LVDSA0+<9>

LVDSA1-<9>
LVDSA1+<9>

LVDSA2-<9>

LVDSA2+<9>
LVDSAC-<9>

LVDSAC+<9>

12

KC FBM-L11-201209-221LMAT_0805UMA@

UMA LCD / PANEL Conn.

LVDSA0­LVDSA0+

LVDSA1­LVDSA1+

LVDSA2+

LVDSAC+

300_0402_5%

UMA@

Q14

2N7002_SOT23

UMA@

R282

+LCDVDD +5VALW

12

R278

13

D

S

12

0_0402_5%UMA@

3
5
7

13
15
17
19
21
23
25
27
29

31
32

ACES_88242-3001

Reverse pin 1 to 29

R281
100K_0402_5%

UMA@

1 2

2

G

0.047U_0402_16V7K

13

D

Q15

2

2N7002_SOT23

G

UMA@

S

JP42

112
3
5
7
9910
111112
13
15
17
19
21
23
25
27
29

GND1
GND2

4
6
8

14
16
18
20
22
24
26
28
30

C383

UMA@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

1

0.1U_0402_16V4Z

2

LVDSB0­LVDSB0+

LVDSB1­LVDSB1+

LVDSB2-LVDSA2­LVDSB2+

LVDSBC-LVDSAC­LVDSBC+

EDID_DAT_LCD
EDID_CLK_LCD

+LCDVDD

1

C381

2

UMA@

LVDSB0- <9>

LVDSB0+ <9>

LVDSB1- <9>

LVDSB1+ <9>

LVDSB2- <9>

LVDSB2+ <9>

LVDSBC- <9>

LVDSBC+ <9>

EDID_DAT_LCD <9>
EDID_CLK_LCD <9>

+3VS

Q13

UMA@

SI2301BDS_SOT23

1 3

D

1

C382

4.7U_0805_10V4Z

2

UMA@

+3VS

S

G

2

1

C384

UMA@

2

4.7U_0805_10V4Z

Pop when with internal graphics

INVERTER Conn.

JP40

1
2
3
4
5
6
7

MOLEX_53780-0790

ENBKL <31>

12

1 2

1 2

1 2

D12
RB751V_SOD323

12

R279

4.7K_0402_5%

VGA_DDC_DAT

VGA_DDC_CLK

R110K_0402_5%

JVGA_HS

JVGA_VS

21

+5VS

INVT_PWM<31>
DAC_BRIG<31>

INVPWR_B+

D13

BKOFF#<31>

GMCH_ENBKL<9>
G7X_ENBKL<17>

KC FBM-L11-201209-221LMAT_0805

KC FBM-L11-201209-221LMAT_0805@

R57 0_0402_5%UMA@
R94 0_0402_5%VGA@

L16

1 2

L15

1 2

RB751V_SOD323

DISPOFF#

+3VS

R283

4.7K_0402_5%

1 2

21
12
12

INVPWR_B+B+

DISPOFF#
ENBKL

R284
100K_0402_5%

1 2

C387

0.1U_0603_50V4Z

12

C388
68P_0402_50V8K

+3VS+3VS

+3VS

S

Q1

+5VS

C5

0.1U_0402_16V4Z

+5VS

C4

0.1U_0402_16V4Z

+3VS

G

2

4.7K_0402_5%

13

D

G

2

13

D

S

1

5

U1

P

4

OE#

A2Y

G

SN74AHCT1G125DCKR_SC70-5

3

5

1

U2

P

4

OE#

A2Y

G

SN74AHCT1G125DCKR_SC70-5

3

R280

Q2
2N7002_SOT23

R12 39_0402_5%

R15 39_0402_5%

12

12

R14

3 3

4 4

CARD_DDCDATA<17>

CARD_DDCCLK<17>

3VDDCDA<9>
3VDDCCL<9>

CARD_HSYNC<17>

CARD_VSYNC<17>

CRT_HSYNC<9>

CRT_VSYNC<9>

R89 0_0402_5%VGA@

R88 0_0402_5%VGA@

R83 0_0402_5%UMA@
R86 0_0402_5%UMA@

R91 0_0402_5%VGA@

R90 0_0402_5%VGA@

R85 0_0402_5%UMA@

R84 0_0402_5%UMA@

1 2
1 2

1 2

1 2

12

12

12

12

Pop when with internal graphics

4.7K_0402_5%

HSYNC_R

VSYNC_R

R13

4.7K_0402_5%

2N7002_SOT23

1

2

1

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

HEL80 LA-3161P

E

0.2

of

16 43Thursday, F e b r u a ry 23, 2006

5

4

3

2

1

D D

MAX. 4.06A @ 1.8V
MAX. 130mA @ 2.5V
MAX. 655mA @ 3.3V

PEG_M_TXP[0..15]
PEG_M_TXN[0..15]

JP7

1

PEG_M_TXP1
PEG_M_TXN1

PEG_M_TXP3
PEG_M_TXN3

PEG_M_TXP5
PEG_M_TXN5

PEG_M_TXP7

C C

B B

PEG_M_TXN7
PEG_M_TXP9

PEG_M_TXN9
PEG_M_TXP11

PEG_M_TXN11
PEG_M_TXP13

PEG_M_TXN13
PEG_M_TXP15

PEG_M_TXN15

+2.5VS

+3VS +5VS

+1.5VS

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

ACES_88363-08001

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

PEG_RXP1

PEG_RXN1

PEG_RXP3

PEG_RXN3

PEG_RXP5
PEG_RXN5

PEG_RXP7
PEG_RXN7

PEG_RXP9
PEG_RXN9

PEG_RXP11
PEG_RXN11

PEG_RXP13
PEG_RXN13

PEG_RXP15
PEG_RXN15

L3 KC FBM-L11-201209-221LMAT_0805VGA@

+1.8VS

12

B+

PEG_M_TXP0
PEG_M_TXN0

PEG_M_TXP2
PEG_M_TXN2

PEG_M_TXP4
PEG_M_TXN4

PEG_M_TXP6
PEG_M_TXN6

PEG_M_TXP8
PEG_M_TXN8

PEG_M_TXP10
PEG_M_TXN10

PEG_M_TXP12
PEG_M_TXN12

PEG_M_TXP14
PEG_M_TXN14

CLK_PCIE_VGA<15>

CLK_PCIE_VGA#<15>

CARD_DDCCLK<16>
CARD_DDCDATA<16> G7X_ENBKL <16>

CARD_VSYNC<16>
CARD_HSYNC<16>

CARD_VGA_R<16>
CARD_VGA_G<16>

CARD_VGA_B<16>

JP8

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

ACES_88363-08001

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

PEG_RXP0

PEG_RXN0

PEG_RXP2

PEG_RXN2

PEG_RXP4

PEG_RXN4

PEG_RXP6

PEG_RXN6

PEG_RXP8

PEG_RXN8

PEG_RXP10
PEG_RXN10

PEG_RXP12
PEG_RXN12

PEG_RXP14
PEG_RXN14

SUSP#

G7X_THER_ALERT#

PLT_RST#

SUSP# <31,32,33,35,40,41>
G7X_THER_ALERT# <20>

PLT_RST# <7,18,20,22,26,27,31,35>

CARD_COMP <16>
CARD_LUMA <16>
CARD_CRMA <16>

PEG_RXP[0..15]
PEG_RXN[0..15]

C156

VGA@

PEG_M_TXP[0..15] <9>
PEG_M_TXN[0..15] <9>

PEG_RXP[0..15] <9>
PEG_RXN[0..15] <9>

2

2

C157

1

1

VGA@

0.1U_0402_16V4Z

+3VS

1

C142

2

VGA@

+2.5VS+5VS

2

2

C132

C133

1

VGA@

0.1U_0402_16V4Z

VGA@

0.047U_0402_16V4Z

1

VGA@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C143

2

0.047U_0402_16V4Z

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

VGA/B connector

HEL80 LA-3161P

1

17 43Thursday, F eb r u ary 23, 2006

0.2

of

5

4

3

2

1

D D

C C

B B

+3VS

R343 8.2K_0402_5%

1 2

R341 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R342 8.2K_0402_5%
R337 8.2K_0402_5%
R346 8.2K_0402_5%
R361 8.2K_0402_5%
R347 8.2K_0402_5%
R350 8.2K_0402_5%
R345 8.2K_0402_5%
R344 8.2K_0402_5%

+3VS

R375 8.2K_0402_5%
R377 8.2K_0402_5%
R371 8.2K_0402_5%
R366 8.2K_0402_5%
R357 8.2K_0402_5%
R367 8.2K_0402_5%
R352 8.2K_0402_5%
R360 8.2K_0402_5%
R362 8.2K_0402_5%
R340 8.2K_0402_5%
R335 8.2K_0402_5%
R358 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ5#

PCI_AD[0..31]<23,25,30>

PCI_PIRQA#<23>
PCI_PIRQB#<23>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U4B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_BGA652~D

PCI

REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ4#
PCI_REQ5#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ0# <25>
PCI_GNT0# <25>

PCI_REQ2# <23>
PCI_GNT2# <23>

PCI_CBE#0 <23,25,30>
PCI_CBE#1 <23,25,30>
PCI_CBE#2 <23,25,30>
PCI_CBE#3 <23,25,30>

PCI_IRDY# <23,25>
PCI_PAR <23,25>

PCI_DEVSEL# <23,25>
PCI_PERR# <23,25>

PCI_SERR# <23>
PCI_STOP# <23,25>
PCI_TRDY# <23,25,30>
PCI_FRAME# <23,25,30>

CLK_PCI_ICH <15>
PCI_PME# <31>

PCI_PIRQE# <25>

MCH_ICH_SYNC# <7>

PCI_PCIRST#

PCI_PLTRST#

+3VS

5

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

12

R332 0_0402_5%

R311 0_0402_5%

+3VS

5

2

P

B

1

A

G

3

12

Y

NC7SZ08P5X_NL_SC70-5

@

Place closely pin A9

CLK_PCI_ICH

R351

10_0402_5%

@

1 2
1

C460

10P_0402_50V8K

@

2

PCI_RST#

4

U27

@

PLT_RST#

4

U26

PCI_RST# <23,25,30>

PLT_RST# <7,17,20,22,26,27,31,35>

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

ICH7-M(1/4)

HEL80 LA-3161P

18 43Thursday, Fe br uary 23, 2006

1

0.2

of

5

C215

18P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251

C214

D D

C C

B B

+RTCVCC

J1 JOPEN@

+3VS

1 2

R369
20K_0402_5%

12

C484

1U_0603_10V4Z

1 2

ICH_BITCLK_MDC<27>
ICH_SYNC_MDC<27>

ICH_RST_MDC#<27>

ICH_AC_SDIN0<28>
ICH_AC_SDIN1<27>

ICH_SDOUT_MDC<27>

18P_0402_50V8J

4

1

IN

4

PD_IORDY
PD_IRQ
SATA_LED#

PSATA_IRX_DTX_N0_C<22>
PSATA_IRX_DTX_P0_C<22>

ICH_RTCX1

ICH_RTCX2

1 2
1 2

SATA_LED#<34>

CLK_PCIE_SATA#<15>
CLK_PCIE_SATA<15>

12

R139

10M_0402_5%

R373 332K_0402_1%
R364 1M_0402_5%

R38539_0402_5%

1 2

R35439_0402_5%

1 2

R38839_0402_5%

1 2

R38939_0402_5%

1 2

PD_IORDY<22>

PD_IRQ<22>

PD_DACK#<22>

PD_IOW#<22>
PD_IOR#<22>

ICH_RTCRST#
ICH_INTVRMEN

SM_INTRUDER#

ICH_AC_BITCLK_R
ICH_AC_SYNC_R

ICH_AC_RST_R#

ICH_AC_SDIN0
ICH_AC_SDIN1

ICH_AC_SDOUT_R

SATA_LED#

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

PSATA_IRX_DTX_N2_C
PSATA_IRX_DTX_P2_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R348

1 2

24.9_0402_1%

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

12

Y2

2

NC

3

OUT

NC

12

+RTCVCC

R3394.7K_0402_5%

12

R3388.2K_0402_5%

12

R33410K_0402_5%

12

AF18

AH10
AG10

AG16
AH16
AF16
AH15
AF15

AB1
AB2

AA3

AF3
AE3
AG2
AH2

AF7
AE7
AG6
AH6

AF1
AE1

W4

Y5

W1

Y1
Y2

W3

V3
U3
U5

V4

T5

U7
V6
V7

U1
R6

R5

T2
T3
T1

T4

3

U4A

RTXC1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7_BGA652~D

RTC

GPIO49 / CPUPWRGD

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

A20M#

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

FERR#

IGNNE#

INIT3_3V#

INIT#
INTR

AC-97/AZALIA

RCIN#

SMI#

STPCLK#

THERMTRIP#

DCS1#
DCS3#

SATA

DD10
DD11
DD12
DD13

IDE

DD14
DD15

DDREQ

NMI

DA0
DA1
DA2

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

AA6
AB5
AC4
Y6

AC3
AA5

AB3

AE22
AH28

AG27
AF24

AH25
AG26
AG24
AG22

AG21
AF22
AF25

AG23
AF23

AH24
AH22
AF26

AH17
AE17
AF17

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ#0

LPC_FRAME#

GATEA20
H_A20M#

H_CPUSLP_R#
DPRSLP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR

KB_RST#
H_SMI#

H_NMI
H_STPCLK#
THRMTRIP_ICH#

PD_A0
PD_A1
PD_A2

PD_CS#1
PD_CS#3

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_DREQ

LPC_AD[0..3] <30,31,35>

R328

12

10K_0402_5%

12
12

R313

12

56_0402_5%

R325

12

10K_0402_5%

R312

1 2

24.9_0402_1%

PD_A0 <22>
PD_A1 <22>
PD_A2 <22>

PD_CS#1 <22>
PD_CS#3 <22>

PD_D[0..15]

PD_DREQ <22>

2

+3VS

R310 0_0402_5%@
R319 0_0402_5%

+VCCP

+3VS

LPC_DRQ#0 <30>

LPC_FRAME# <30,31,35>

GATEA20 <31>
H_A20M# <4>

H_CPUSLP# <4,7>
H_DPRSTP# <4,42>

H_DPSLP# <4>
H_FERR# <4>
H_PWRGOOD <4>
H_IGNNE# <4>
H_INIT# <4>

H_INTR <4>

KB_RST# <31>
H_SMI# <4>

H_NMI <4>
H_STPCLK# <4>

PD_D[0..15] <22>

+VCCP

12

R324
56_0402_5%

1

H_DPSLP#

1 2

R125

H_DPRSTP#

1 2

H_THERMTRIP# <4,7>

+VCCP

R124

56_0402_5%@

56_0402_5%@

PSATA_ITX_DRX_N0<22>

PSATA_ITX_DRX_P0<22>

PSATA_ITX_DRX_N0

PSATA_ITX_DRX_P0

C479 3900P_0402_50V7K

C480 3900P_0402_50V7K

Close to U7

ICH_AC_SDOUT_R

ICH_SDOUT_AUDIO<28>

ICH_SYNC_AUDIO<28>

A A

ICH_RST_AUDIO#<28>

ICH_BITCLK_AUDIO<28>

5

1 2

R376 39_0402_5%

ICH_AC_SYNC_R

1 2

R353 39_0402_5%

ICH_AC_RST_R#

1 2

R387 39_0402_5%

ICH_AC_BITCLK_R

1 2

R386 39_0402_5%

4

1 2

1 2

PSATA_ITX_DRX_N0_C

PSATA_ITX_DRX_P0_C

12/12 Added

R531 1K_0402_5%

1 2

R532

PSATA_IRX_DTX_P2_C

1K_0402_5%

PSATA_IRX_DTX_N2_C

1 2

SATA_RXn/p need tie to ground when SATA port no used

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+CHGRTC

+RTCVCC

C240

2

0.1U_0402_16V4Z

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

1

2

D2

2

3

BAS40-04_SOT23

BATT1

+-

BATT1.1

1

W=20mils

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

ML1220T13RE

45@

Compal Electronics, Inc.

ICH7-M(2/4)

HEL80 LA-3161P

1

of

19 43Thursday, F e b r u a ry 23, 2006

0.2

5

+3VS

SIRQ

R32610K_0402_5%

1 2

PCI_CLKRUN#

R3338.2K_0402_5%

1 2

G7X_THER_ALERT#

R32910K_0402_5%

D D

+3VALW

C C

1 2

LINKALERT#

R31810K_0402_5%

1 2

ITP_DBRESET#

R32210K_0402_5%

1 2

1 2

@

1 2

@

1 2

1 2

@

1 2

OCP#

R32310K_0402_5%

SPI_MISO

R37910K_0402_5%

SPI_CS# ICH_LOW_BAT#

R35910K_0402_5%

ICH_PCIE_W AKE#

R3301K_0402_5%

ICH_LOW_BAT#

R3278.2K_0402_5%

12

SPI_MOSI

R36810K_0402_5%

R317

10K_0402_5%

+3VALW

2/13 Add feature:
Pull high for pure IDE interface
Pull low for SATA interface

R316
10K_0402_5%

1 2

1 2

R550

PATA@

10K_0402_5%

1 2

R551

SATA@

10K_0402_5%

1 2

4

3

2

1

Place closely pin B2 Place c losely pin AC1

+3VALW+3VALW

12

12

R321

R331

1 2

8.2K_0402_5%

SB_SPKR<28>

OCP#<4>

H_STP_PCI#<15>

PAD

PAD
PAD

SIRQ<23,30,31,35>

VGATE<15,31,42>

PAD
PAD

EC_SMI#<31>

R309

2.2K_0402_5%

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

ICH_RI#
SB_SPKR

SUS_STAT#
ITP_DBRESET#

PM_BMBUSY#
OCP#
H_STP_PCI#

H_STP_CPU#
IDERST_CD#

PCI_CLKRUN#

ICH_PCIE_W AKE#

SIRQ
EC_THERM#

VGATE

EC_SMI#

U4C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_BGA652~D

GPIO21 / SATA0GP

SMB

GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

SATA

GPIO

SYS

Clocks

GPIO

GPIO16 / DPRSLPVR

TP0 / BATLOW#

POWER MGT

GPIO

GPIO35 / SATAREQ#

Need update symbol

CLK14
CLK48

SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

PWRBTN#

LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

AF19
AH18
AH19
AE19

AC1
B2

C20
B24

D23
F22

AA4
AC22
C21
C23
C19
Y4

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

R336

1 2

100_0402_5%

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

R372 10K_0402_5%

1 2

R95 100_0402_5%

1 2

PBTN_OUT#
PLT_RST#
EC_RSMRST#

R374 10K_0402_5%

1 2

EC_SCI#

EC_LID_OUT#

EC_FLASH#
SATAREQ#

G7X_THER_ALERT#

SB_INT_FLASH_SEL <32>

CLK_14M_ICH <15>
CLK_48M_ICH <15>

T37 PAD

SLP_S3# <31>
SLP_S4# <31>
SLP_S5# <31>

PBTN_OUT# <31>
PLT_RST# <7,17,18,22,26,27,31,35>
EC_RSMRST# <31>

EC_SCI# <31>
ACIN <31,36>

T36 PAD

EC_LID_OUT# <31>

T43 PAD
T32 PAD
T44 PAD

EC_FLASH# <32>

SATAREQ# <15>

G7X_THER_ALERT# <17>

T38 PAD

2.2K_0402_5%

ICH_SMBCLK<15,27,35>

ICH_SMBDATA<15,27,35>

+3VALW

SUS_STAT#<35>

ITP_DBRESET#<4>

PM_BMBUSY#<7>

H_STP_CPU#<15>

IDERST_CD#<22>

T31

PCI_CLKRUN#<31,35>

T39
T46

ICH_PCIE_W AKE#<26,27,35>

EC_THERM#<31>

T33
T40

CLK_48M_ICH

12

R380
10_0402_5%

@

1

C474
10P_0402_50V8K

@

2

ICH_POK <7,31>
DPRSLPVR <7,42>

CLK_14M_ICH

12

R381
10_0402_5%

@

1

C483
10P_0402_50V8K

@

2

PCIE_RXN1<27>
PCIE_RXP1<27>
PCIE_TXN1<27>
PCIE_TXP1<27>

PCIE_RXN3<26>
PCIE_RXP3<26>
PCIE_TXN3<26>
PCIE_TXP3<26>

B B

A A

PCIE_RXN4<35>
PCIE_RXP4<35>
PCIE_TXN4<35>
PCIE_TXP4<35>

USB_OC#0<34>

USB_OC#2<34>

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1

C4240.1U_0402_10V7K

12

PCIE_C_TXP1

C4230.1U_0402_10V7K

12

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3

C4350.1U_0402_10V7K

12

PCIE_C_TXP3

C4360.1U_0402_10V7K

12

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4

C4320.1U_0402_10V7K

12

PCIE_C_TXP4

C4390.1U_0402_10V7K

12

SPI_CS#

SPI_MOSI
SPI_MISO

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3

USB_OC#5
USB_OC#6
USB_OC#7

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U4D

F26
F25
E28
E27

H26
H25
G28
G27

K26
K25
J28
J27

M26
M25

L28
L27

P26
P25
N28
N27

T25
T24
R28
R27

R2

P6
P1

P5
P2

D3
C4
D5
D4

E5

C3

A2
B3

ICH7_BGA652~D

3

PCI-EXPRESS

SPI

USB

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN
DMI_CLKP

DIRECT MEDIA INTERFACE

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

Compal Secret Data

PERn1
PERp1
PETn1
PETp1

PERn2
PERp2
PETn2
PETp2

PERn3
PERp3
PETn3
PETp3

PERn4
PERp4
PETn4
PETp4

PERn5
PERp5
PETn5
PETp5

PERn6
PERp6
PETn6
PETp6

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

2005/10/06 2006/10/06

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

Deciphered Date

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBRBIAS

DMI_RXN0 <7>
DMI_RXP0 <7>
DMI_TXN0 <7>
DMI_TXP0 <7>

DMI_RXN1 <7>
DMI_RXP1 <7>
DMI_TXN1 <7>
DMI_TXP1 <7>

DMI_RXN2 <7>
DMI_RXP2 <7>
DMI_TXN2 <7>
DMI_TXP2 <7>

DMI_RXN3 <7>
DMI_RXP3 <7>
DMI_TXN3 <7>
DMI_TXP3 <7>

CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>

R314 24.9_0402_1%

1 2

USB20_N0 <34>
USB20_P0 <34>
USB20_N1 <27>
USB20_P1 <27>
USB20_N2 <29>
USB20_P2 <29>
USB20_N3 <33>
USB20_P3 <33>
USB20_N4 <29>
USB20_P4 <29>
USB20_N5 <33>
USB20_P5 <33>
USB20_N6 <35>
USB20_P6 <35>
USB20_N7 <27>
USB20_P7 <27>

R382 22.6_0402_1%

1 2

Within 500 mils

2

Within 500 mils

+1.5VS

Title

Size Document Number Rev

Custom

Date: Sheet

RP13

4 5

USB_OC#2

3 6

USB_OC#3

2 7

USB_OC#1

1 8

10K_1206_8P4R_5%

USB_OC#0
USB_OC#5
USB_OC#6
USB_OC#7

RP14

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

Compal Electronics, Inc.

ICH7-M(3/4)

HEL80 LA-3161P

1

+3VALW

+3VALW

20 43Thursday, Fe br uary 23, 2006

0.2

of

5

+3VS+5VS

12

R355

100_0402_5%

D D

0.1U_0402_16V4Z

R365

10_0402_5%

C C

B B

21

D23
RB751V_SOD323

C458

ICH_V5REF_RUN

1

2

1

0.1U_0402_16V4Z

2

Place close pin G10 or AD17

+3VALW+5VALW

12

21

D24
RB751V_SOD323

ICH_V5REF_SUS

1

C467

0.1U_0402_16V4Z

2

+1.5VS

Place close pin AG28 within 100mlis.

R308

0.5_0603_1%

1 2

C457

+1.5VS_DMIPLLR

220U_D2_2VMR15

R305

1 2

0_0603_5%

+1.5VS

1

+

C420

C425

2

0.1U_0402_16V4Z

+1.5VS_DMIPLL

1

1

C421

C430

2

2

0.01U_0402_16V7K

10U_0805_10V4Z

Place close pin AH5.

+1.5VS

C472

+3VS

1

2

0.1U_0402_16V4Z

1

C452

2

0.1U_0402_16V4Z

Place close pin AH9.

+3VALW

0.1U_0402_16V4Z

A A

C469

1

2

0.1U_0402_16V4Z

+1.5VS

C464

1

2

4

0.1U_0402_16V4Z

1

C434

2

Place close pin
D28,T28,AD28.

+1.5VS

0.1U_0402_16V4Z

+1.5VS

1U_0603_10V4Z

T45 PAD
T41 PAD

ICH_V5REF_RUN

ICH_V5REF_SUS

1

1

C429

2

2

0.1U_0402_16V4Z

+3VS

1

C448

2

0.1U_0402_16V4Z

+1.5VS_DMIPLL

1

C470

2

1

C461

2

+3VALW

ICH_AA2
ICH_Y7

G10

AD17

F6

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22

L23
M22
M23

N22

N23

P22

P23

R22

R23

R24

R25

R26

T22

T23

T26

T27

T28

U22

U23

V22

V23
W22
W23

Y22

Y23

B27

AG28

AB7
AC6
AC7
AD6
AE6
AF5
AF6

AG5

AH5

AD2
AH11
AB10

AB9
AC10
AD10
AE10
AF10

AF9

AG9

AH9

E3

C1

AA2

Y7
V5

V1
W2
W7

1

C445

0.1U_0402_16V4Z

2

U4F

V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]

Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]

Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]

Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2]
VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

ICH7_BGA652~D

3

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

+VCCP

0.1U_0402_16V4Z

1

C454

2

1

C466

2

0.1U_0402_16V4Z

1

C476

0.1U_0402_16V4Z

2

1

C465

0.1U_0402_16V4Z

2

1

2

1

C455

0.1U_0402_16V4Z

2

1

2

C459

1U_0603_10V4Z

Place close pin L1 & K3

+1.5VS

1 2

C444 0.1U_0402_16V4Z

ICH_K7
ICH_C28

ICH_G20

+1.5VS

1

C478

0.1U_0402_16V4Z

2

Place close pin A1

1

+

2

+3VALW

+3VS

1

C446

2

0.1U_0402_16V4Z

1

C481

0.1U_0402_16V4Z

2

1

C473

0.1U_0402_16V4Z

2

C447
220U_D2_2VMR15

+VCCP

+3VS

C433

0.1U_0402_16V4Z

+3VALW

+3VALW

T42PAD
T16PAD

T35PAD

2

C450

1 2

0.1U_0402_16V4Z

1 2

C449

0.1U_0402_16V4Z

1 2

C456

4.7U_0805_10V4Z

Place close pin
A5, B7 & C10

1

C468

2

0.1U_0402_16V4Z

+3VS

1

C453

0.1U_0402_16V4Z

2

Place close pin AH26

+RTCVCC

U4E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

E15

VSS[23]

F3

VSS[24]

F4

VSS[25]

F5

VSS[26]

F12

VSS[27]

F27

VSS[28]

F28

VSS[29]

G1

VSS[30]

G2

VSS[31]

G5

VSS[32]

G6

VSS[33]

G9

VSS[34]

G14

VSS[35]

G18

VSS[36]

G21

VSS[37]

G24

VSS[38]

G25

VSS[39]

G26

VSS[40]

H3

VSS[41]

H4

VSS[42]

H5

VSS[43]

H24

VSS[44]

H27

VSS[45]

H28

VSS[46]

J1

VSS[47]

J2

VSS[48]

J5

VSS[49]

J24

VSS[50]

J25

VSS[51]

J26

VSS[52]

K24

VSS[53]

K27

VSS[54]

K28

VSS[55]

L13

VSS[56]

L15

VSS[57]

L24

VSS[58]

L25

VSS[59]

L26

VSS[60]

M3

VSS[61]

M4

VSS[62]

M5

VSS[63]

M12

VSS[64]

M13

VSS[65]

M14

VSS[66]

M15

VSS[67]

M16

VSS[68]

M17

VSS[69]

M24

VSS[70]

M27

VSS[71]

M28

VSS[72]

N1

VSS[73]

N2

VSS[74]

N5

VSS[75]

N6

VSS[76]

N11

VSS[77]

N12

VSS[78]

N13

VSS[79]

N14

VSS[80]

N15

VSS[81]

N16

VSS[82]

N17

VSS[83]

N18

VSS[84]

N24

VSS[85]

N25

VSS[86]

N26

VSS[87]

P3

VSS[88]

P4

VSS[89]

P12

VSS[90]

P13

VSS[91]

P14

VSS[92]

P15

VSS[93]

P16

VSS[94]

P17

VSS[95]

P24

VSS[96]

P27

VSS[97]

ICH7_BGA652~D

1

P28

VSS[98]

R1

VSS[99]

R11

VSS[100]

R12

VSS[101]

R13

VSS[102]

R14

VSS[103]

R15

VSS[104]

R16

VSS[105]

R17

VSS[106]

R18

VSS[107]

T6

VSS[108]

T12

VSS[109]

T13

VSS[110]

T14

VSS[111]

T15

VSS[112]

T16

VSS[113]

T17

VSS[114]

U4

VSS[115]

U12

VSS[116]

U13

VSS[117]

U14

VSS[118]

U15

VSS[119]

U16

VSS[120]

U17

VSS[121]

U24

VSS[122]

U25

VSS[123]

U26

VSS[124]

V2

VSS[125]

V13

VSS[126]

V15

VSS[127]

V24

VSS[128]

V27

VSS[129]

V28

VSS[130]

W6

VSS[131]

W24

VSS[132]

W25

VSS[133]

W26

VSS[134]

Y3

VSS[135]

Y24

VSS[136]

Y27

VSS[137]

Y28

VSS[138]

AA1

VSS[139]

AA24

VSS[140]

AA25

VSS[141]

AA26

VSS[142]

AB4

VSS[143]

AB6

VSS[144]

AB11

VSS[145]

AB14

VSS[146]

AB16

VSS[147]

AB19

VSS[148]

AB21

VSS[149]

AB24

VSS[150]

AB27

VSS[151]

AB28

VSS[152]

AC2

VSS[153]

AC5

VSS[154]

AC9

VSS[155]

AC11

VSS[156]

AD1

VSS[157]

AD3

VSS[158]

AD4

VSS[159]

AD7

VSS[160]

AD8

VSS[161]

AD11

VSS[162]

AD15

VSS[163]

AD19

VSS[164]

AD23

VSS[165]

AE2

VSS[166]

AE4

VSS[167]

AE8

VSS[168]

AE11

VSS[169]

AE13

VSS[170]

AE18

VSS[171]

AE21

VSS[172]

AE24

VSS[173]

AE25

VSS[174]

AF2

VSS[175]

AF4

VSS[176]

AF8

VSS[177]

AF11

VSS[178]

AF27

VSS[179]

AF28

VSS[180]

AG1

VSS[181]

AG3

VSS[182]

AG7

VSS[183]

AG11

VSS[184]

AG14

VSS[185]

AG17

VSS[186]

AG20

VSS[187]

AG25

VSS[188]

AH1

VSS[189]

AH3

VSS[190]

AH7

VSS[191]

AH12

VSS[192]

AH23

VSS[193]

AH27

VSS[194]

Place close pin V1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

ICH7-M(4/4)

HEL80 LA-3161P

1

0.2

of

21 43Thursday, Fe br uary 23, 2006

5

SA880400020 Marvell 8040 TQFP64_Lead Free

PIDE_DD0
PIDE_DD1
PIDE_DD2
PIDE_DD3
PIDE_DD4
PIDE_DD5
PIDE_DD6
PIDE_DD7
PIDE_DD8
PIDE_DD9
PIDE_DD10

D D

PIDE_DD11
PIDE_DD12
PIDE_DD13
PIDE_DD14
PIDE_DD15

PIDE_DA0
PIDE_DA1
PIDE_DA2
PIDE_CS0#
PIDE_CS1#

PIDE_HIOCS16#
PIDE_INTRQ
PIDE_DMACK#
PIDE_DIORDY
PIDE_DIOR#
PIDE_DIOW#
PIDE_DREQ
PIDE_R_RESET#

T27
PAD

R212

T28
PAD

10K_0402_5%

1 2

8040@

C C

Place closed to 3811

2005/09/04

PSATA_IRX_DTX_N0_C<19>

PSATA_IRX_DTX_P0_C<19>

2005/10/19

R_PIDE_DD2 PD_D2
R_PIDE_DD12 PD_D12
R_PIDE_DD3 PD_D3
R_PIDE_DD11 PD_D11
R_PIDE_DD4
R_PIDE_DD10
R_PIDE_DD5

B B

R_PIDE_DD9
R_PIDE_DD6
R_PIDE_DD8
R_PIDE_DD7
R_PIDE_RESET#
R_PIDE_DD0
R_PIDE_DD14
R_PIDE_DD1
R_PIDE_DD13
R_PIDE_DIOR#
R_PIDE_DIOW#
R_PIDE_DREQ
R_PIDE_DD15 PD_D15
R_PIDE_DA1
R_PIDE_INTRQ
R_PIDE_DMACK#

A A

R_PIDE_DIORDY
R_PIDE_CS1#
R_PIDE_CS0#
R_PIDE_DA2
R_PIDE_DA0
R_PIDE_PDIAG# PD_DIAG#

U11

62

HDD0

64

HDD1

2

HDD2

5

HDD3

7

HDD4

11

HDD5

13

HDD6

15

HDD7

14

HDD8

12

HDD9

10

HDD10

6

HDD11

3

HDD12

1

HDD13

63

HDD14

61

HDD15

50

HDA0

51

HDA1

49

HDA2

48

HCS0#

47

HCS1#

52

HIOCS16#

53

HINTRQ

54

HDMACK#

55

HIORDY

58

HDIOR#

59

HDIOW#

60

HDMARQ

16

HRESET#

46

HPDIAG#

45

UAO

43

UAI

88SA8040_TQFP64

8040@

1 2

R113 0_0402_5%PATA@

1 2

R114 0_0402_5%PATA@

1 2

R115 0_0402_5%PATA@

1 2

R116 0_0402_5%PATA@

1 2

R137 0_0402_5%PATA@

1 2

R117 0_0402_5%PATA@

1 2

R122 0_0402_5%PATA@

1 2

R118 0_0402_5%PATA@

1 2

R136 0_0402_5%PATA@

1 2

R121 0_0402_5%PATA@

1 2

R133 0_0402_5%PATA@

1 2

R135 0_0402_5%PATA@

1 2

R108 0_0402_5%PATA@

1 2

R111 0_0402_5%PATA@

1 2

R110 0_0402_5%PATA@

1 2

R112 0_0402_5%PATA@

1 2

R106 0_0402_5%PATA@

1 2

R105 0_0402_5%PATA@

1 2

R107 0_0402_5%PATA@

1 2

R109 0_0402_5%PATA@

1 2

R101 0_0402_5%PATA@

1 2

R102 0_0402_5%PATA@

1 2

R103 0_0402_5%PATA@

1 2

R104 0_0402_5%PATA@

1 2

R97 0_0402_5%PATA@

1 2

R96 0_0402_5%PATA@

1 2

R98 0_0402_5%PATA@

1 2

R99 0_0402_5%PATA@

1 2

R100 0_0402_5%PATA@

5

SATA

Config & Debug

Parallel ATA

Power

UART

SATA_ITX_C_R_DRX_P0
SATA_ITX_C_R_DRX_N0

SATA_DTX_R_IRX_N0
SATA_DTX_R_IRX_P0

PSATA_IRX_DTX_N0_C

PD_D4
PD_D10
PD_D5
PD_D9
PD_D6
PD_D8
PD_D7
IDE_RST#
PD_D0
PD_D14
PD_D1
PD_D13
PD_IOR#
PD_IOW#
PD_DREQ

PD_A1
PD_IRQ
PD_DACK#
PD_IORDY
PD_CS#3
PD_CS#1
PD_A2
PD_A0

TXP
TXM
RXP

RXM

RST#

T0
T1
T2
T3
T4
T5
T6

T7
CNFG2
CNFG1
CNFG0

ATAIOSEL

XTLIN/OSC

XTLOUT

ISET
VDDIO_0
VDDIO_1

VDD_0
VDD_1
VDD_2

VAA1
VAA2

VSS1

VSS2
GND_0
GND_1
GND_2

SATA@
2 3
1 4

RP15 0_0404_4P2R_5%

SATA@
2 3
1 4

RP16 0_0404_4P2R_5%

1 2

C336 3900P_0402_50V7K

1 2

C331 3900P_0402_50V7K

R_PIDE_DD2
R_PIDE_DD12
R_PIDE_DD3
R_PIDE_DD11
R_PIDE_DD4
R_PIDE_DD10
R_PIDE_DD5
R_PIDE_DD9
R_PIDE_DD6
R_PIDE_DD8
R_PIDE_DD7
R_PIDE_RESET#
R_PIDE_DD0
R_PIDE_DD14
R_PIDE_DD1
R_PIDE_DD13
R_PIDE_DIOR#
R_PIDE_DIOW#
R_PIDE_DREQ
R_PIDE_DD15
R_PIDE_DA1

R_PIDE_INTRQ
R_PIDE_DMACK#
R_PIDE_DIORDY

R_PIDE_CS1#

R_PIDE_CS0#

R_PIDE_DA2

R_PIDE_DA0

R_PIDE_PDIAG#

SATA_DTX_IRX_N0

31

PSATA_ITX_DRX_P0

27

PSATA_ITX_DRX_N0

28

SATA_RESET#

17

T0

33
34

T2

35

T3

36
37

T5

38

T6

R233 10K_0402_5%

39
40
20
19

R246 10K_0402_5%

18

ATAIOSEL

21

SATA_XTALI

22

SATA_XTALO

23

R490 12.1K_0603_1%

26

1 2
44
4
9
41
56
24
29

25
30
8
42
57

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

SATA_DTX_IRX_N0

SATA_DTX_IRX_P0PSATA_IRX_DTX_P0_C

1 2

R194 0_0402_5%PATA@

1 2

R199 0_0402_5%PATA@

1 2

R205 0_0402_5%PATA@

1 2

R210 0_0402_5%PATA@

1 2

R215 0_0402_5%PATA@

1 2

R217 0_0402_5%PATA@

1 2

R218 0_0402_5%PATA@

1 2

R222 0_0402_5%PATA@

1 2

R225 0_0402_5%PATA@

1 2

R227 0_0402_5%PATA@

1 2

R231 0_0402_5%PATA@

1 2

R241 0_0402_5%PATA@

1 2

R177 0_0402_5%PATA@

1 2

R176 0_0402_5%PATA@

1 2

R175 0_0402_5%PATA@

1 2

R190 0_0402_5%PATA@

1 2

R181 0_0402_5%PATA@

1 2

R180 0_0402_5%PATA@

1 2

R179 0_0402_5%PATA@

1 2

R178 0_0402_5%PATA@

1 2

R185 0_0402_5%PATA@

1 2

R184 0_0402_5%PATA@

1 2

R183 0_0402_5%PATA@

1 2

R182 0_0402_5%PATA@

1 2

R207 0_0402_5%PATA@

1 2

R203 0_0402_5%PATA@

1 2

R187 0_0402_5%PATA@

1 2

R186 0_0402_5%PATA@

1 2

R169 0_0402_5%PATA@

SATA_DTX_IRX_P0

32

1 2

1 2

+1.8VS_VDDA

FGND

8040@

8040@

8040@

+3VS
+1.8VS

PIDE_DD2
PIDE_DD12
PIDE_DD3
PIDE_DD11
PIDE_DD4
PIDE_DD10
PIDE_DD5
PIDE_DD9
PIDE_DD6
PIDE_DD8
PIDE_DD7
PIDE_RESET#
PIDE_DD0
PIDE_DD14
PIDE_DD1
PIDE_DD13
PIDE_DIOR#
PIDE_DIOW#
PIDE_DREQ
PIDE_DD15
PIDE_DA1
PIDE_INTRQ
PIDE_DMACK#
PIDE_DIORDY
PIDE_CS1#
PIDE_CS0#
PIDE_DA2
PIDE_DA0
PIDE_PDIAG#

4

PSATA_ITX_DRX_P0 <19>
PSATA_ITX_DRX_N0 <19>

R492

0_0603_5%8040@

1 2

ICH7M
IDE

IDE

4

T0

R245 10K_0402_5%@

T2
T3
T6

ATAIOSELCNFG1

PIDE_HIOCS16#

1 2

R237 10K_0402_5%@

1 2

R226 10K_0402_5%8040@

1 2

R224 10K_0402_5%@

1 2

R247 10K_0402_5%8040@

1 2

R171 10K_0402_5%8040@

1 2

R235 33_0402_5%8040@

PLACE Close to U61

1

1

C329

C330

0.01U_0402_16V7K

2

2

8040@

8040@

0.1U_0402_16V4Z

R

SATA

Marvell 8040

R_IDE

R

ODD
Connector

SATA_XTALI SATA_XTALO

1

C339
27P_0402_50V8J

8040@

2

+1.8VS

C314

8040@

0.1U_0402_16V4Z

+3VS

C311

8040@

0.1U_0402_16V4Z

R

Y4

1 2

25MHZ_20PF_6X25000017

8040@

R250 10M_0402_5%8040@

27P_0402_50V8J

0.1U_0402_16V4Z

1

1

C498

C504

8040@

8040@

2

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

1

1

2

C501

8040@

C303

8040@

2

0.1U_0402_16V4Z

1

2

1

2

3

PIDE_RESET#PIDE_R_RESET#

12

1 2

L11 MBK1608121YZF_06038040@

1 2

L12 MBK1608121YZF_0603@

1

C344

4.7U_0805_10V4Z

2

8040@

FGND

R_SATA

SATA HDD ONLY
SATA to PATA HDD
PATA HDD ONLY

12

R248
0_0402_5%

8040@

+3VS

SATA_RESET#

1U_0603_10V4Z

SATA
HDD
Connector

PATA
HDD
Connector

R251

100K_0402_5%

@

C338

@

+3VS

+3VS
+1.8VS

12

R249

1 2

0_0402_5%

1

8040@

2

PATA HDD Conn.

Place closed to Connector

PIDE_DIORDY
PIDE_DREQ
PIDE_INTRQ
PIDE_DD7

PIDE_LED#<34>

SATA HDD Conn.

PLT_RST# <7,17,18,20,26,27,31,35>

+3VS

1 2

R206 4.7K_0402_5%8040@

1 2

R223 5.6K_0402_5%8040@

1 2

R188 10K_0402_5%8040@

1 2

R263 10K_0402_5%@

PATA ODD Conn.

1

C340

8040@

2

IDERST_CD#<20>

PLT_RST#<7,17,18,20,26,27,31,35>

+5VS

4.7U_0805_10V4Z

1

C375

8040@

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

IDE_CSEL
Grounding for Master (When use SATA HDD)
Open or Hi gh fo r Slave r (N ormal)

2005/10/06 2006/10/06

3

IDERST_CD#
PLT_RST#

NC7SZ08P5X_NL_SC70-5

1 2

R307 475_0402_1%@

1 2

R306 475_0402_1%

SATA@

Compal Secret Data

Deciphered Date

2

W=60mils at least

1

C237

@
2

10U_0805_10V4Z

10U_0805_10V4Z

W=60mils at least

+5VS

10U_0805_10V4Z

+3VS

+5VS

R320

10K_0402_5%

PIDE_LED#

+3VS

C451

0.1U_0402_16V4Z

1 2

5

2

P

B

4

Y

1

A

G

U28

3

PD_IOW#<19>

PD_IORDY<19>

PD_IRQ<19>

PD_CS#1<19> PD_CS#3 <19>

+5VS

PRI_CSEL

2

1

C236

@
2

1

C218

2

12

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1
PIDE_LED#

10U_0805_10V4Z

IDE_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

1

2005/11/4 Modified library pn:DC010003J00

Main SATA +5V Default

SATA_ITX_C_R_DRX_P0
SATA_ITX_C_R_DRX_N0

SATA_DTX_R_IRX_N0
SATA_DTX_R_IRX_P0

1

1

1

C234

@
2

1U_0603_10V4Z

0.1U_0402_16V4Z

1

1

C216

C217

2

2

1U_0603_10V4Z

2005/11/4 Modified library pn:SP01000LU00

+5VS +5VS

PIDE_DA2
PIDE_PDIAG#

T26
PAD

PCSEL

12

R198
475_0402_1%

PIDE_DD15
PIDE_DD14
PIDE_DD13
PIDE_DD12
PIDE_DD11
PIDE_DD10
PIDE_DD9
PIDE_DD8

OCTEK_CDR-50DY1G

ME@

Title

Size Document Number Rev

Custom

Date: Sheet

C243

C251

@

@

2

2

0.1U_0402_16V4Z

1

1

C222

C225

@

@

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Reverse pin 1 to 44, pin 2 to 43

JP25

SUYIN_200055FB044G202ZR_44P_P2_PATA_HDD

PATA@

(NEW)

PD_D[0..15]
PD_A[0..2]

JP10

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

Compal Electronics, Inc.

HDD & CDROM

HEL80 LA-3161P

JP9

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

SUYIN_127072FR022G210ZR_22P_SATA

SATA@

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#

PD_DACK#
PD_DIAG#

PD_A2
PD_CS#3

0.1U_0402_16V4Z

1

C441

2

10U_0805_10V4Z

1

1 2

R315 100K_0402_5%

1

C440

2

PIDE_LED#
PIDE_CS0#PIDE_CS1#
PIDE_DA0
PIDE_DA1
PIDE_INTRQ
PIDE_DMACK#
PIDE_DIORDY
PIDE_DIOR#
PIDE_DIOW#
PIDE_DREQ

PIDE_DD0
PIDE_DD1
PIDE_DD2
PIDE_DD3
PIDE_DD4
PIDE_DD5
PIDE_DD6
PIDE_DD7
PIDE_RESET#

PD_D[0..15] <19>

PD_A[0..2] <19>

PD_DREQ <19>
PD_IOR# <19>

PD_DACK# <19>

1

C426

2

10U_0805_10V4Z

22 43Thursday, F e b r u a ry 23, 2006

T30
PAD

+5VS

+5VS

1

C422

2

1U_0603_10V4Z

0.2

of

5

+3VS

40mil

0.1U_0402_16V4Z

1

D D

0.1U_0402_16V4Z

+3VS

C C

B B

A A

C258

1 2

R230 43K_0402_5%

1

2

C296

2

SM_CD#

0.1U_0402_16V4Z

1

C299

2

0.1U_0402_16V4Z

MFUNC5[3:0] = (0 1 0 1)
MFUNC5[4] = 1

1

C260

2

MS_PWREN#<24>

1

C259

2

0.1U_0402_16V4Z

PCI_AD[0..31]<18,25,30>

PCI_CBE#[0..3]<18,25,30>

12

1

2

+3VS

SDCK_XDWE#<24>

0.1U_0402_16V4Z

CLK_PCI_PCM

R204

C295

R229 10K_0402_5%

1

C283

2

10_0402_5%@

15P_0402_50V8J@

1 2

R228

0_0402_5%@

4

1

C319

2

0.1U_0402_16V4Z

PCI_AD[0..31]
PCI_CBE#[0..3]

CLK_SD_48M

12

R197

10_0402_5%@

1

C290

15P_0402_50V8J@

2

PCI_FRAME#<18,25,30>

PCI_DEVSEL#<18,25>

CLK_PCI_PCM<15>

PCI_AD20

PCI_PIRQA#<18>

1 2

PCI_PIRQB#<18>

SD_PWREN#<24>

CLK_SD_48M<15>

R209 33_0402_5%

1 2

SDCM_XDALE<24>

SDDA0_XDD7<24>
SDDA1_XDD0<24>
SDDA2_XDCL<24>
SDDA3_XDD4<24>

3

+3VS

VPPD0<24>
VPPD1<24>
VCCD0#<24>
VCCD1#<24>

PCI_RST#<18,25,30>

PCI_IRDY#<18,25>

PCI_TRDY#<18,25,30>
PCI_STOP#<18,25>

PCI_PERR#<18,25>
PCI_SERR#<18>

PCI_PAR<18,25>
PCI_REQ2#<18>
PCI_GNT2#<18>

1 2

R192 100_0402_5%

SIRQ<20,30,31,35>
3IN1_LED#<34>
SDOC#<24>

+VCC_SD

SD_CD#<24>
SD_WP#<24>

VPPD0
VPPD1
VCCD0#
VCCD1#

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10

PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

PCI_RST#

PCI_REQ2#
PCI_GNT2#
CLK_PCI_PCM

SD_PULLHIGH

SM_CD#
3IN1_LED#

SDOC#

PCI_RST#

SD_CD#
SD_WP#
SD_PWREN#

CLK_SD_48M
SD_CLK

SDCM_XDALE

SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4

U9

C2

AD31

C1

AD30

D4

AD29

D2

AD28

D1

AD27

E4

AD26

E3

AD25

E2

AD24

F2

AD23

F1

AD22

G2

AD21

G3

AD20

H3

AD19

H4

AD18

J1

AD17

J2

AD16

N2

AD15

M3

AD14

N3

AD13

K4

AD12

M4

AD11

K5

AD10

L5

AD9

M5

AD8

K6

AD7

M6

AD6

N6

AD5

M7

AD4

N7

AD3

L7

AD2

K7

AD1

N8

AD0

E1

CBE3#

J3

CBE2#

N1

CBE1#

N5

CBE0#

G4

PCIRST#

J4

FRAME#

K1

IRDY#

K3

TRDY#

L1

DEVSEL#

L2

STOP#

L3

PERR#

M1

SERR#

M2

PAR

A1

PCIREQ#

B1

PCIGNT#

H1

PCICLK

L8

RIOUT#_PME#

L11

SUSPEND#

F4

IDSEL

K8

MFUNC0

N9

MFUNC1

K9

MFUNC2

N10

MFUNC3

L10

MFUNC4

N11

MFUNC5

M11

MFUNC6

J9

MFUNC7

M10

GRST#

E7

VCC_SD

E8

SDCD#

F8

SDWP/SMWPD#

G7

SDPWREN33#

H5

SDCLKI

F6

SDCLK/SMWE#

E5

SDCMD/SMALE

E6

SDDAT0/SMDATA7

F7

SDDAT1/SMDATA0

F5

SDDAT2/SMCLE

G6

SDDAT3/SMDATA4

G5

GND_SD

+S1_VCC

N12

M12

N13

M13

VPPD0

VPPD1

VCCD0#

VCCD1#

PCI Interface

SD/MMC/MS/SM

G13

A7

VCCA1

VCCA2

GND1D3GND2H2GND3L4GND4M8GND5

G1

K2

N4

L6

C8

L9

H11

D12

B4

VCC3

VCC4

VCC5

VCC9

VCC6

VCC7

VCC8

VCC10

CAD15/IOWR#

CAD13/IORD#

CAD10/CE2#

CCBE3#/REG#

CCBE2#/A12

CCBE0#/CE1#

CARDBUS

CRST#/RESET

CFRAME#/A23

CTRDY#/A22

CDEVSEL#/A21

CSTOP#/A20
CPERR#/A14

CSERR#/WAIT#

CREQ#/INPACK#

CGNT#/WE#

CSTSCHG/BVD1_STSCHG#

CCLKRUN#/WP_IOIS16#

CBLOCK#/A19

CINT#/READY_IREQ#

CAUDIO/BVD2_SPKR#

CCD2#/CD2#
CCD1#/CD1#

MSPWREN#/SMPWREN#

MSBS/SMDATA1

MSCLK/SMRE#
MSDATA0/SMDATA2
MSDATA1/SMDATA6
MSDATA2/SMDATA5
MSDATA3/SMDATA3

GND6

GND7

GND8

CB714_LFBGA169

B6

F12

K11

C10

F3

VCC2

VCC1

CAD31/D10

CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6

CAD19/A25

CAD18/A7
CAD17/A24
CAD16/A17

CAD14/A9
CAD12/A11

CAD11/OE#

CAD9/A10

CAD8/D15

CAD7/D7

CAD6/D13

CAD5/D6

CAD4/D12

CAD3/D5

CAD2/D11

CAD1/D4
CAD0/D3

CCBE1#/A8

CIRDY#/A15

CPAR/A13

CCLK/A16

SPKROUT

CVS2/VS2#

CVS1/VS1

CRSV3/D2

CRSV2/A18

CRSV1/D14

MSINS#

SMBSY#

SMCD#

SMWP#

SMCE#

S1_D10

B2

S1_D9

C3

S1_D1

B3

S1_D8

A3

S1_D0

C4

S1_A0

A6

S1_A1

D7

S1_A2

C7

S1_A3

A8

S1_A4

D8

S1_A5

A9

S1_A6

C9

S1_A25

A10

S1_A7

B10

S1_A24

D10

S1_A17

E12

S1_IOWR#

F10

S1_A9

E13

S1_IORD#

F13

S1_A11

F11

S1_OE#

G10

S1_CE2#

G11

S1_A10

G12

S1_D15

H12

S1_D7

H10

S1_D13

J11

S1_D6

J12

S1_D12

K13

S1_D5

J10

S1_D11

K10

S1_D4

K12

S1_D3

L13

S1_REG#

B7

S1_A12

A11

S1_A8

E11

S1_CE1#

H13

S1_RST

B9

S1_A23

B11

S1_A15

A12

S1_A22

A13

S1_A21

B13

S1_A20

C12

S1_A14

C13

S1_WAIT#

A5

S1_A13

D13

S1_INPACK#

B8

S1_WE#

C11
B12

S1_BVD1

C5

S1_WP

D5

S1_A19

D11

S1_RDY#

D6

PCM_SPK#

M9

S1_BVD2

B5

S1_CD2#

A4

S1_CD1#

L12

S1_VS2

D9

S1_VS1

C6

S1_D2

A2

S1_A18

E10

S1_D14

J13

H7
J8

MSBS_XDD1

H8

MS_CLK

E9

MSD0_XDD2

G9

MSD1_XDD6

H9

MSD2_XDD5

G8

MSD3_XDD3

F9

H6
J7
J6
J5

2

S1_IOWR# <24>
S1_IORD# <24>
S1_OE# <24>

S1_CE2# <24>

S1_REG# <24>

S1_CE1# <24>
S1_RST <24>

S1_WAIT# <24>
S1_INPACK# <24>

S1_WE# <24>

1 2

R160 33_0402_5%

S1_BVD1 <24>
S1_WP <24>

S1_RDY# <24>

PCM_SPK# <28>

S1_BVD2 <24>
S1_CD2# <24>

S1_CD1# <24>
S1_VS2 <24>
S1_VS1 <24>

R161 33_0402_5%

1 2

S1_A16

S1_A[0..25]
S1_D[0..15]

MS_INS# <24>
MS_PWREN# <24>

MSBS_XDD1 <24>

MSCLK_XDRE# <24>
MSD0_XDD2 <24>
MSD1_XDD6 <24>
MSD2_XDD5 <24>
MSD3_XDD3 <24>

S1_A[0..25] <24>
S1_D[0..15] <24>

+3VS

2

C250
10P_0402_50V8K

1

1

C320

0.1U_0402_16V4Z

2

1

C292

0.1U_0402_16V4Z

2

1

C321

4.7U_0805_10V4Z

2

+S1_VCC

1

C257

0.1U_0402_16V4Z

2

S1_CD2# S1_CD1#

1

2

C323
10P_0402_50V8K

1

**CB714 use B0 version

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/20 2006/06/20

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cardbus Controller CB714
HEL80 LA-3161P

1

0.2

of

23 43Thursday, F e b r u a ry 23, 2006

5

4

3

2

1

PCMCIA Socket

Note : 11/10 modify library to meet spec

D D

W=40mil

1

C361

10U_0805_10V4Z

0.1U_0402_16V4Z

2

W=40mil

1

C356

10U_0805_10V4Z

C C

0.1U_0402_16V4Z

2

PCMCIA Power Control

U16

9

12V

+5VS

1

C360

C357

5

5V

6

+3VS

5V

3

3.3V

4

3.3V

VCCD0#
VCCD1#

GND

7

1 2

R254 10K_0402_5%

1 2

R257 10K_0402_5%

12

R253
10K_0402_5%

2

1

2

40mil

13

VCC

12

VCC

11

VCC

10

VPP

1

VCCD0

2

VCCD1

15

VPPD0

14

VPPD1

8

OC

SHDN

CP2211FD3_SSOP16

16

+S1_VCC

VCCD0#
VCCD1#
VPPD0
VPPD1

40mil

+S1_VPP

1

C359

0.1U_0402_16V4Z

2

VCCD0# <23>

VCCD1# <23>
VPPD0 <23>
VPPD1 <23>

C322

10U_0805_10V4Z

C325

10U_0805_10V4Z

S1_OE#
S1_WP
S1_RST
S1_CE1#
S1_CE2#

+S1_VCC

1

2

+S1_VPP

1

2

1 2

R443 43K_0402_5%
R503 43K_0402_5%

1 2

R491 43K_0402_5%

1 2

R426 43K_0402_5%

1 2

R432 43K_0402_5%

12

1

C317

0.1U_0402_16V4Z

2

1

C318

0.1U_0402_16V4Z

2

S1_A[0..25]<23>
S1_D[0..15]<23>

+S1_VCC
+S1_VCC
+S1_VCC
+S1_VCC
+S1_VCC

S1_A[0..25]

S1_D[0..15]

pn: SP01000IC00
02/17 modify footprint to FOX_1CA41521-EL-4F_68P_LT

JP17

1

S1_D3
S1_D4
S1_D5
S1_D6
S1_D7

S1_CE1#<23>

S1_OE#<23>

S1_WE#<23>

S1_RDY#<23>

+S1_VCC

+S1_VPP +S1_VPP

S1_WP<23>

S1_CE1#

S1_A10
S1_A11

S1_A9
S1_A8

S1_A13
S1_A14

S1_WE#

S1_RDY#

S1_A16
S1_A15
S1_A12

S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2

S1_WP

GND

2

D3

3

D4

4

D5

5

D6

6

D7

7

CE1#

8

A10

9

OE#

10

A11

11

A9

12

A8

13

A13

14

A14

15

WE#

16

IREQ#

17

VCC

18

VPP1

19

A16

20

A15

21

A12

22

A7

23

A6

24

A5

25

A4

26

A3

27

A2

28

A1

29

A0

30

D0

31

D1

32

D2

33

IOIS16#

34

GND

69

GND

70

GND

71

GND

72

GND

73

GND

74

GND

75

GND

76

GND

FOX_1CA41521-EL-4F_68P_LT

GND

CD1#

CE2#

VS1#

IORD#

IOWR#

VCC

VPP2

VS2#

RESET

WAIT#

INPACK#

REG#

SPKR#

STSCHG#

CD2#

GND
GND

GND
GND
GND
GND
GND
GND
GND

35

S1_CD1#

36

S1_D11

37

D11
D12
D13
D14
D15

A17
A18
A19
A20
A21

A22
A23
A24
A25

D8
D9

D10

38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

77
78
79
80
81
82
83
84

S1_D12
S1_D13
S1_D14
S1_D15

S1_CE2#

S1_VS1S1_OE#

S1_IORD#

S1_IOWR#

S1_A17
S1_A18
S1_A19
S1_A20
S1_A21

S1_A22
S1_A23
S1_A24

S1_A25
S1_VS2
S1_RST

S1_WAIT#

S1_INPACK#

S1_REG#
S1_BVD2
S1_BVD1

S1_D8
S1_D9

S1_D10

S1_CD2#

S1_CD1# <23>

S1_CE2# <23>
S1_VS1 <23>
S1_IORD# <23>
S1_IOWR# <23>

+S1_VCC

S1_VS2 <23>
S1_RST <23>
S1_WAIT# <23>
S1_INPACK# <23>
S1_REG# <23>
S1_BVD2 <23>
S1_BVD1 <23>

S1_CD2# <23>

+VCC_SD

1

1

B B

MS_PWREN#<23>

A A

+3VS

R265

10K_0402_5%

SD_PWREN# SDOC#

MS_PWREN#

1 2

12

R261
0_0402_5%

U17

1
2
3
4

G528_SO8

GND
IN
IN
EN#

OUT
OUT
OUT

+VCC_SD+3VS

8
7
6
5

FLG

40mil

+3VS

R264
10K_0402_5%

1 2

SDOC# <23>SD_PWREN#<23>

C371

10U_0805_10V4Z

C367

0.1U_0402_16V4Z

2

2

Reserve for SD,MS CLK.
Close to Socket

SDCK_XDWE#

C369 10P_0402_50V8K

MSCLK_XDRE#

C370 10P_0402_50V8K

1 2

1 2

1

C368

0.1U_0402_16V4Z

2

MSD1_XDD6<23>

MSCLK_XDRE#<23>

MS_INS#<23>
MSD0_XDD2<23>
MSBS_XDD1<23>
MSD3_XDD3<23>
MSD2_XDD5<23>

SDDA0_XDD7<23>

SDDA3_XDD4<23>

+VCC_SD

SDDA1_XDD0<23>
SDDA2_XDCL<23>

SDCK_XDWE#<23>

SD_WP#<23>

SDCM_XDALE<23>

SD_CD#<23>

MSD1_XDD6
MSCLK_XDRE#

MS_INS#
MSD0_XDD2
MSBS_XDD1
MSD3_XDD3
MSD2_XDD5

+VCC_SD

SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4
SDCK_XDWE#
SD_WP#
SDCM_XDALE
SD_CD#

1 2

R538 0_0402_5%

1 2

R539 0_0402_5%

1 2

R540 0_0402_5%

J3IN1

6

VDD_SD

9

DAT0_SD

10

DAT1_SD

2

DAT2_SD

3

CD/DAT3_SD

7

CLK_SD

11

WP_SD

4

CMD_SD

1

CD_SD

5

VSS_SD

8

VSS_SD

19

VCC_MS

13

VCC_MS

14

SCLK_MS

16

INS_MS

18

SDIO_MS

20

BS_MS

15

RESERVED_MS

17

RESERVED_MS

21

VSS_MS

12

VSS_MS

22

GND

23

GND

PROCO_MDR019-C0-1202

12/20 modified

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/20 2006/06/20

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCMCIA Socket

HEL80 LA-3161P

1

0.2

of

24 43Thursday, F e b r u a ry 23, 2006

5

4

3

2

1

C309

0.1U_0402_16V4Z

1394@

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10

PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_STOP#
PCI_PERR#
PCI_PAR
PCI_PIRQE#

CLK_PCI_1394

PCI_GNT0#
PCI_REQ0#
1394_IDSEL

PCI_IRDY#
PCI_TRDY#

PCI_DEVSEL#

PCI_FRAME#

12

R196

10_0402_5%@

1

C289

10P_0402_50V8K@

2

+2.5VS_1394

1

C310

0.1U_0402_16V4Z

2

1394@

U10

94
95
96
97

98
101
102
103
106
107
109
113
114
115
116
117

2
3
4
7
8

9
10
11
14
15
16
18
19
20
24
25

104
119

1
12

125
127
128

88
89
90
92
93

105

34

121
123
124
120

1

2

+2.5VS_1394

VDD446VDD330VDD221VDD1

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7

PCI I/F

AD6
AD5
AD4
AD3
AD2
AD1
AD0
CBE3#
CBE2#
CBE1#
CBE0#
STOP#
PERR#
PAR
INTA#
PCIRST#
PCICLK
GNT#
REQ#
IDSEL
PME#
IRDY#
TRDY#
DEVSEL#
FRAME#

GNDATX166GNDARX165GNDATX280GNDARX279GND19

1

2

+3VS

122

110

VCC699VCC536VCC417VCC35VCC2

C231

0.1U_0402_16V4Z

1394@

VCC1

C277

0.1U_0402_16V4Z

1394@

111

VT6311S

EEPROM

others

OSCILLATOR

PHY PORT0

PHY PORT1

GND18

GND17

GND16

GND1591GND1061GND956GND847GND738GND633GND531GND423GND322GND26GND113GND0

118

112

108

100

+1394_PLLVDD

59

PVA587PVA486PVA373PVA272PVA162PVA0

SDA/EEDI

SCL/EECK

PHYRST#

BJT_CTL

PWRDET

REG_FB

REG_OUT

XTPB0M
XTPA0M

XTPBIAS0

XTPB1M
XTPA1M

XTPBIAS1

1

C265

0.1U_0402_16V4Z

2

1394@

20mils

26

EECS

27

EEDO

28
29

55
81
43

I2CEN

32
84
85
60

XCPS

63

XREXT

57

XI

58

XO

67
68

XTPB0P

69
70

XTPA0P

71
74

75

XTPB1P

76
77

XTPA1P

78
83

NC17

82

NC16

64

NC15

54

NC14

53

NC13

52

NC12

51

NC11

50

NC10

49

NC9

48

NC8

45

NC7

44

NC6

42

NC5

41

NC4

40

NC3

39

NC2

37

NC1

35

NC0

VT6311S_LQFP128

126

1394@

0.1U_0402_16V4Z

1

2

EECS
EEDI

EECK

I2CEEN

REG_FB
REG_OUT

XREXT

10mils

1394_XI
1394_XO
TPB0-

TPB0+
TPA0­TPA0+
TPBIAS0

TPA0+
TPA0­TPB0+
TPB0-

PSOT24C_SOT23

C230

1394@

0.1U_0402_16V4Z

R162 4.7K_0402_5%@

C226 1U_0603_10V4Z1394@
R173 4.7K_0402_5%@
R147 4.7K_0402_5%1394@
R152 4.7K_0402_5%1394@

C238 0.1U_0402_16V4Z

R142 1K_0402_5%1394@
R145 6.19K_0603_1%1394@

C227 47P_0402_50V8J1394@

TPBIAS0

D21

@

1394@

2

1 2

1 2
1 2
1 2
1 2

1 2

1 2
1 2

1 2

2

3

1

2

1394@

1394@

3

1

0.1U_0402_16V4Z

1

1

C267

C284

1

C279

4.7U_0805_10V4Z

1394@

2

2

D22
PSOT24C_SOT23

@

L7

MBK1608301YZF_0603

1 2

+3VS

+3VS

15mils

12

R165

54.9_0402_1%

1394@

12

R153

54.9_0402_1%

1394@

1

C241
270P_0402_50V7K

1394@

2

1394@

+3VS

C229

10P_0402_50V8K

1 2

Y1

1394@

24.576MHZ_16P_X8A024576FG1H

1 2

1 2

C228

10P_0402_50V8K

1394@

12

R155

54.9_0402_1%

1394@

12

R149

54.9_0402_1%

1394@

12

R150

4.99K_0402_1%

1394@

1394@

VCC

SCL
SDA

+3VS

8
7

WP

6
5

2

B

EECK
EEDI

+3VS

31

E

Q6

2SB1197K_SOT23

C

@

+2.5VS_1394

U5

1

A0

2

A1

3

A2

4

GND

AT24C02N-10SU-2.7_SO8

1394@

EECK and EEDI is pull high internal
External pull h igh ci rcuit is unnecessary

When use ext er nal EEPROM
Populate U14, R246, R253
Un-populate R261

REG_OUT

REG_FB

When use external BJT
Populate Q35, R279

2/21 Add for Compliance Engineering request

L42

1

C252

0.33U_0603_10V7K

1394@

2

1

1

4

4

WCM2012F2SF-121T04_0805

1394@

R546 0_0402_5%@

1 2

R547 0_0402_5%@

1 2

R548 0_0402_5%@

1 2

R549 0_0402_5%@

1 2

L43

1

1

4

4

WCM2012F2SF-121T04_0805

1394@

2

2

3

3

2

2

3

3

12

R146
510_0402_5%

1394@

JP21

4
3
2
1

8

TPA+

GND

7

TPA-

GND

6

TPB+

GND

5

TPB-

GND

SUYIN_020115FB004S512ZL

1394@

+3VS

1

C291

0.1U_0402_16V4Z

2

1394@

D D

C C

B B

A A

1

C270

0.1U_0402_16V4Z

2

1394@

PCI_AD[0..31]<18,23,30>

IDSEL:PCI_AD16

PCI_AD16 1394_IDSEL

1 2

R219 100_0402_5%1394@

1

2

PCI_AD[0..31]

C232

0.1U_0402_16V4Z

1394@

PCI_CBE#3<18,23,30>
PCI_CBE#2<18,23,30>
PCI_CBE#1<18,23,30>
PCI_CBE#0<18,23,30>

PCI_STOP#<18,23>
PCI_PERR#<18,23>

PCI_PAR<18,23>

PCI_PIRQE#<18>

PCI_RST#<18,23,30>

CLK_PCI_1394<15>

PCI_GNT0#<18>
PCI_REQ0#<18>

PCI_IRDY#<18,23>
PCI_TRDY#<18,23,30>

PCI_DEVSEL#<18,23>

PCI_FRAME#<18,23,30>

CLK_PCI_1394

1

2

Modify WCM2012F2SF-900T04 this symbol for WCM2012F2SF-121T04

Note : This page copied from HBL50

5

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/20 2006/06/20

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

IEEE1394 VIA VT6311S

HEL80 LA-3161P

1

25

0.2

of

43T h u r s d a y, F e b r u a ry 23, 2006

5

PN : SA00000TL00 (QFN64 Lead Free)

C306 0.1U_0402_10V7K

PCIE_RXP3<20>
PCIE_RXN3<20>
PCIE_TXP3<20>

D D

C C

PCIE_TXN3<20>

+3VS

25MHZ_20PF_6X25000017

1

C254
27P_0402_50V8J

2

CLK_PCIE_LAN<15>
CLK_PCIE_LAN#<15>

ICH_PCIE_W AKE#<20,27,35>

R200 1K_0402_1%

1 2

1U_0603_10V4Z

Y3

LAN_X2LAN_X1

1 2

1

C256
27P_0402_50V8J

2

1 2

C307 0.1U_0402_10V7K

1 2

PLT_RST#<7,17,18,20,22,27,31,35>

R164 2.49K_0402_1%

R201
15K_0402_5%

2

1

C249

2

C248

0.1U_0402_16V4Z

1

@

1 2

1 2

R221 0_0603_5%

4

PCIE_PTX_IRX_P3
PCIE_PTX_IRX_N3

LAN_CTRL18
LAN_CTRL15

LAN_X1
LAN_X2

EGND

U8

29

HSOP

30

HSON

23

HSIP

24

HSIN

26

REFCLK_P

27

REFCLK_N

20

PERSTB

1

VCTRL18

63

VCTRL15

64

RSET

19

LANWAKEB

36

ISOLATEB

60

CKXTAL1

61

CKXTAL2

62

GVDD

25

EGND

31

EGND

17

NC

18

NC

35

NC

34

NC

39

NC

40

NC

42

NC

50

NC

51

NC

RTL8111B_QFN64

EEDO

EDDI/AUX

EESK
EECS

LED3
LED2
LED1
LED0

MDIP0

MDIN0

MDIP1

MDIN1

MDIP2

MDIN2

MDIP3

MDIN3

VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15

VDD33
VDD33
VDD33

VDD33
AVDD33
AVDD33

AVDD18
AVDD18
AVDD18
AVDD18

EVDD18
EVDD18

45
47
48
44

54
55
56
57

3
4
6
7

9
10
12
13

15
21
32
33
38
41
43
49
52
58

16
37
53
46

2
59

5
8
11
14

22
28

LAN_ACTIVITY#
LED_10/100
LED_1000
LAN_LINK#

LAN_MDI0+
LAN_MDI0­LAN_MDI1+
LAN_MDI1-

LAN_MDI2+
LAN_MDI2­LAN_MDI3+
LAN_MDI3-

AVDD33

AVDD18

3

R167 3.6K_0402_5%

4
3
2
1

AT93C46-10SI-2.7_SO8

T25 PAD
T24 PAD

+LAN_VDD15

+3VALW

+LAN_VDD18

AVDD33

U7

DO

GND

DI

NC

SK

NC

CS

VCC

C239

10U_0805_10V4Z

12

5
6
7
8

1

2

R144 4.7K_0402_5%

2

1

0.1U_0402_16V4Z

1 2

BLM18AG601SN1D_0603

2

C266

0.1U_0402_16V4Z

1

12

C224

L4

+3VALW

+3VALW

AVDD18

C272

0.1U_0402_16V4Z

+3VALW

2

1

2

C275

0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

2

C281

0.1U_0402_16V4Z

1

2

C297

0.1U_0402_16V4Z

1

2

C298

0.1U_0402_16V4Z

1

+3VALW +3VALW

+LAN_VDD18

2

C305

0.1U_0402_16V4Z

1

2

C269

0.1U_0402_16V4Z

1

LAN_CTRL15LAN_CTRL18

10U_0805_10V4Z

1 2

BLM18AG601SN1D_0603

2

C294

1

0.1U_0402_16V4Z

2

1

2

1

Q7

1

MMJT9435T1G_SOT223

2 3

4

40mil 40mil

2

1

C347

2

1

C352

0.1U_0402_16V4Z

1

2

C288

0.1U_0402_16V4Z

2

C308

0.1U_0402_16V4Z

1

2

C246

0.1U_0402_16V4Z

1

2

C300

0.1U_0402_16V4Z

1

1

1

2 3

4

1

C350

2

L8

0.1U_0402_16V4Z

+LAN_VDD15

C247

0.1U_0402_16V4Z

C287

0.1U_0402_16V4Z

Q8
MMJT9435T1G_SOT223

2

C315

1

2

C245

0.1U_0402_16V4Z

1

+3VALW

2

C282

0.1U_0402_16V4Z

1

2

C353

0.1U_0402_16V4Z

1

+LAN_VDD18

C531

12/09 Added

+LAN_VDD15

10U_0805_10V4Z

1

2

B B

LAN_MDI3­LAN_MDI3+

LAN_MDI2­LAN_MDI2+

LAN_MDI1­LAN_MDI1+

LAN_MDI0­LAN_MDI0+

1

1

C471

C475

0.01U_0402_16V7K

A A

0.01U_0402_16V7K

2

2

Place these components
colsed to LAN chip

5

GbE Transformer: GST5009 (SP050005610) MY

T22

C463

0.01U_0402_16V7K

1

1

C462

0.01U_0402_16V7K

2

2

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+
TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

0.5u_GST5009

4

MCT1
MX1+

MX1-

MCT2
MX2+

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

24
23
22

21
20
19

18
17
16

15
14
13

R349

75_0402_1%

LAN Conn.

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI2-

RJ45_MIDI2+

RJ45_MIDI1-

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

12

12

R356
75_0402_1%

12

12

R370

75_0402_1%

R378
75_0402_1%

RJ45_GND

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

LAN_ACTIVITY#

LAN_LINK#

2

R132 300_0402_5%

R138 300_0402_5%

RJ45_GND LANGND

12

+3VALW

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI1-

RJ45_MIDI2­RJ45_MIDI2+
RJ45_MIDI1+

RJ45_MIDI0­RJ45_MIDI0+

12

+3VALW

1000P_1206_2KV7K

Title

Size Document Number Rev

Date: Sheet

JP22 FOX_JM74113-P2101-7F

10

Green LED-

9

Green LED+

1

PR4-

2

PR4+

3

PR2-

4

PR3-

5

PR3+

6

PR2+

7

PR1-

8

PR1+

12

Yellow LED-

11

Yellow LED+

C220

1 2

1

C221

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

LAN REALTEK RTL8111B

HEL80 LA-3161P

14

SHLD2

13

SHLD1

1

C219

4.7U_0805_10V4Z

2

1

0.2

of

26 43Thursday, Fe b r u a ry 23, 2006

A

B

C

D

E

Mini-Express Card(Slot 1-WLAN)

1 1

2 2

3 3

ICH_PCIE_WAKE#<20,26,35>

WLAN_AVTIVE
BT_AVTIVE

CLKREQ_MCARD1#<15>

CLK_PCIE_MCARD1#<15>
CLK_PCIE_MCARD1<15>

R517 0_0402_5%
R518 0_0402_5%

CLK_PCIE_MCARD1#
CLK_PCIE_MCARD1

PCIE_RXN1<20>
PCIE_RXP1<20>

PCIE_TXN1<20>
PCIE_TXP1<20>

12
12

JP28

1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

FOX_AS0B226-S56N-7F

MINI_RF_OFF#

2N7002_SOT23

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

10K_0402_5%

GND2

Q33

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

R500

2

2

4

4

6

6

8

8

+3VS

D

S

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

12

13

MINI_RF_OFF#
PLT_RST#

+3VALW

ICH_SMBCLK
ICH_SMBDATA

WIRELESS_LED#

RF_ON#

2

G

RF_ON# <31>

C511

0.1U_0402_16V4Z

PLT_RST# <7,17,18,20,22,26,31,35>

ICH_SMBCLK <15,20,35>
ICH_SMBDATA <15,20,35>

10K_0402_5%

R542

+3VS
+1.5VS

C512

0.1U_0402_16V4Z

+3VS

12

WIRELESS_LED# <34>

ICH_SDOUT_MDC<19>

ICH_SYNC_MDC<19>

ICH_AC_SDIN1<19>

ICH_RST_MDC#<19>

02/06 Modified

Mini-Express Card(Slot 2-TV)

JP20

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S56N-7F

GND2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

PLT_RST#

ICH_SMBCLK
ICH_SMBDATA

USB20_N7
USB20_P7

MDC CONN.

JP23

ICH_SDOUT_MDC
ICH_SYNC_MDC

R363 33_0402_5%

1 2

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

GND13GND14GND15GND16GND17GND

Connector for MDC Rev1.5

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

18

2
4
6
8
10
12

ACES_88018-124G

20mil

ICH_BITCLK_MDCICH_RST_MDC#

+3VALW

1

C487
22P_0402_50V8J

2

C403

+3VALW

1

2

C488
1U_0603_10V4Z

0.1U_0402_16V4Z

PLT_RST# <7,17,18,20,22,26,31,35>

ICH_SMBCLK <15,20,35>
ICH_SMBDATA <15,20,35>

USB20_N7 <20>
USB20_P7 <20>

+3VALW

ICH_BITCLK_MDC <19>

+3VS
+1.5VS

C404

0.1U_0402_16V4Z

11/9 Modify pn to SP01000FE00

+3VS

+3VALW

S

Q19
SI2301BDS_SOT23

D

1 3

W=40mils

1

2

1

C486
1U_0603_10V4Z

2

+BT_VCC

C477

0.1U_0402_16V4Z

C485

BTPWR_ON#<31>

4 4

BTPWR_ON#

R384 100K_0402_5%

0.1U_0402_16V4Z

12

2

C482

4.7U_0805_10V4Z

G

BT MODULE CONN

BTON_LED#<34>

10K_0402_5%

BTON_LED#

2N7002_SOT23

12

R541

D

Q20

S

USB20_N1<20>

2

G

12

R383
10K_0402_5%

USB20_P1<20>

13

USB20_P1
USB20_N1
BTON_LED
WLAN_AVTIVE
BT_AVTIVE

12/09 Modified

+BT_VCC

JP15

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND1

10

GND2

MOLEX_53780-0870

ME@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Mini Card / MDC CONN

HEL80/81 LA-3161P

E

0.2

of

27 43Thursday, F e b r u a ry 23, 2006

A

+VDDA

12

1 1

1 2

1 2

1 2

R252

1 2

560_0402_5%

R255

1 2

560_0402_5%

R258

1 2

560_0402_5%

10K_0402_5%

R256

BEEP#<31>

PCM_SPK#<23>

SB_SPKR<20>

C337

1U_0603_10V4Z

C343

1U_0603_10V4Z

C351

1U_0603_10V4Z

12

1

C

2

B

E

3

12

2 1

B

R496
10K_0402_5%

1 2

C510 1U_0603_10V4Z

R497
10K_0402_5%

C509

1 2

1U_0603_10V4Z
Q24
2SC2411K_SC59

D3
RB751V_SOD323

1 2

R495

2.4K_0402_5%

C

D

E

28.7K for Modu le De sign (VDDA = 4.702)

U18

4

VIN

2

SENSE or ADJ

DELAY
ERROR7CNOISE

8

SD

SI9182DH-AD_MSOP8

VOUT

GND

5
6
1
3

0.1U_0402_16V4Z

1

2

C373

0.1U_0402_16V4Z

60mil

1

2

C364

L10

+5VS

MONO_IN

1 2

KC FBM-L11-201209-221LMAT_0805

L9

1 2

KC FBM-L11-201209-221LMAT_0805@

10U_0805_10V4Z

(output = 250 mA)

40mil

30K_0402_1%

1

C374

2

R262

1 2
12

R259
10K_0402_1%

+VDDA

4.85V

1

C366
10U_0805_10V4Z

2

HD Audio Codec

2 2

+VDDA

MIC1_VREFO_RMIC1_VREFO_L

12

R243

C540

C332

2.2K_0402_5%

1

2

1

2

2.2K_0402_5%

3 3

MIC1_L<29>
MIC1_R<29>

220P_0402_50V7K

SPDIF<29>

100P_0402_25V8K

12

R244

1

2

2/13 modify this symbol to
FBMA-11-100505-301T 0402

L13

1 2

FBM-L11-160808-800LMT_0603

10U_0805_10V4Z

MIC1_L
MIC1_R MIC1_C_R

C333
220P_0402_50V7K

1 2

L45 FBMA-11-100505-301T 0402

0.1U_0402_16V4Z

1

C358

C355

2

1 2

C342 1U_0603_10V4Z

1 2

C341 1U_0603_10V4Z

ICH_RST_AUDIO#<19>
ICH_SYNC_AUDIO<19>

ICH_SDOUT_AUDIO<19>

1

2

40mil

1

C378

2

0.1U_0402_16V4Z

MIC1_C_L

MONO_IN

DGND

+AVDD_AC97

U19

AVDD125AVDD2

14

LINE2_L

15

LINE2_R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1_L

22

MIC1_R

12

PCBEEP

11

RESET#

10

SYNC

5

SDATA_OUT

2

GPIO0

3

GPIO1

13

SENSE A

34

SENSE B

47

SPDIFI/EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

ALC883-LF_LQFP48

38

FRONT_OUT_L
FRONT_OUT_R

SIDESURR_OUT_L

SIDESURR_OUT_R

MIC1_VREFO_L
MIC1_VREFO_R

20mil

DVDD11DVDD2

SURR_OUT_L

SURR_OUT_R

CEN_OUT

LFE_OUT

BIT_CLK

SDATA_IN
PIN37_VREFO
LINE1_VREFO
LINE2_VREFO

MIC2_VREFO

VREF

JDREF

VAUX

AVSS1
AVSS2

0.1U_0402_16V4Z

1

C363

2

9

AMP_LEFT

35

AMP_RIGHT

36

HP_C_L

39

HP_C_R

41
45
46
43
44

6

R260 33_0402_5%

8
37
29
31

10mil

28
32
30
27
40
33
26

42

GNDA

1

1

2

0.1U_0402_16V4Z

C365 22P_0402_50V8J

1 2

1 2

AC97_VREF

12

R266
20K_0402_1%

C372

2

MIC1_VREFO_L
MIC1_VREFO_R

10mil

C376
10U_0805_10V4Z

1

2

1 2

FBM-L11-160808-800LMT_0603

C362
10U_0805_10V4Z

L44

+3VS

AMP_LEFT <29>
AMP_RIGHT <29>
HP_C_L <29>
HP_C_R <29>

ICH_BITCLK_AUDIO <19>

ICH_AC_SDIN0 <19>

2005/09/20

J3

@

2

112

JUMP_43X79
J6

@

2

112

JUMP_43X79

1 2

R515 0_0603_5%

1 2

R498 0_0603_5%@

1 2

R494 0_0603_5%@

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

D

GND

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

HD CODEC ALC883

HEL80 LA-3161P

E

GNDA

0.2

of

28 43Thursday, F e b r u a ry 23, 2006

A

PJP3

1 2

PAD-OPEN 3x3m

1 1

AMP_LEFT<28>

AMP_RIGHT<28>

2 2

C520 0.47U_0603_16V4Z
C519 0.47U_0603_16V4Z

SPDIF_PLUG#

2N7002_SOT23 @

+5VAMP+5VALW

12
12

12

R506

1K_0402_1%

@

+5VAMP

12

R505
10K_0402_5%

12

R509

@

5.1K_0402_1%

13

D

2

Q26

G

S

12

R508

1.5K_0402_1%

1 2

C514 1U_0603_10V4Z

1 2

C515 1U_0603_10V4Z

12

R507

1K_0402_1%

@

VOL_AMP

(0.65V -> 10dB )

HEAD PHONE AMP

HPF Fc = 338Hz
R=1K, C=0.22U for HBQ60

3 3

4 4

SPDIF_PLUG#

Q34
2N7002_SOT23

HPA@

EC_MUTE

Q35
2N7002_SOT23

HPA@

HP_C_R<28>

HP_C_L<28>

G

2

13

D

S

G

2

13

D

S

2005/12/12 Modified

A

C533
1U_0603_10V4ZHPA@

C534
1U_0603_10V4ZHPA@

L38

+3VS

MBK1608301YZF_0603

HPA@

+3VS

12

R537
100K_0402_5%

HPA@

EC_MUTE#

HP_RIGHT_C

12

HP_LEFT_C

12

2

C535
1U_0603_10V4ZHPA@

1

12

2

C532
1U_0603_10V4Z

1

HPA@

U38

14

SHDNR#

18

SHDNL#

15

INR

13

INL

1

C1P

3

C1N

C536

1U_0603_10V4Z

HPA@

+HP_VDD

20mil

10

19

PVDD

PVss

SVss

5

7

2

1

B

C517 0.1U_0402_16V4Z

R501 0_0402_5%

11

OUTR

SVDD

2

PGND

9

OUTL

4

NC-4

6

NC-6

8

NC-8

12

NC-12

16

NC-16

20

NC-20

SGND

MAX4411ETP+_TQFN20

17

HPA@

B

0.1U_0402_16V4Z

12

VOL_AMP
VOLMAX

12

NBA_PLUG

AMP_LEFT_RC
AMP_RIGHT_RC

1

2

EC_MUTE<31>

HP_R
HP_L

+5VAMP

1

C354

2

10
15

13

BYPASS

20mil

C513

4.7U_0805_10V4Z

W=40mil

1

C345

4.7U_0805_10V4Z

2

U34

VDD

SHUTDOWN#

VDD

7

VOLUME

8

VOLMAX
SE/BTL#

6
3

4

ROUT+
LIN­RIN-

BYPASS

APA2068KAI-TRL_SOP16

1 2

R502 10K_0402_5%

0.1U_0402_16V4Z

C

MUTE

LOUT­ROUT­LOUT+

GND
GND

1
2

9
16
11
14

5
12

2

G

C516

+5VAMP

12

13

1

2

MUTE
SHUTDOWN#

SPKL­SPKR­SPKL+
SPKR+

R504
10K_0402_5%

SHUTDOWN#

D

Q25
2N7002_SOT23

S

MUTE

SPKL+
SPKL­SPKR+
SPKR-

R514 0_0603_5%
R512 0_0603_5%
R513 0_0603_5%
R511 0_0603_5%

20mil

Speaker Conn.

NBA_PLUG

1 2
1 2
1 2
1 2

+5VAMP

12

R523
100K_0402_5%

13

D

S

Un-Plug
HP_Plug_In
SPDIF_Plug_In

Audio Jack/USB Conn.

R533

HP@

R534
R535

R536

12
12

HP@
APA@

12
12

APA@

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

HP_C_L<28>
HP_C_R<28>

SPKL+
SPKR+

2005/12/12 Modified

BOM Structure

Issued Date

HPA@

APA@

HP@

C

Head Phone
AMP

APA
AMP

C

2005/10/06 2006/10/06

HP

Compal Secret Data

Deciphered Date

ALC883

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+

1 2

C521 150U_D_6.3VM@

+

1 2

C522 150U_D_6.3VM@

12/12 Modified

INT_MIC_L

2/16 Add for EMI

D

2

G

Q28
2N7002_SOT23

1 2

D

+5VAMP

R516
100K_0402_5%

1 2

L46

8P_0402_50V8K

11/10 modify pn to SP02000G100

SPK_L+
SPK_L­SPK_R+
SPK_R-

D26

PSOT24C_SOT23

SPDIF_PLUG#

SPDIF_PLUG# NBA_PLUG

H
L
L

MIC1_L<28>
MIC1_R<28>

SPDIF<28>

USB20_N4<20>
USB20_P4<20>

+5VSPDIF
USB20_N2<20>
USB20_P2<20>

+USB_VCCB

MIC1_L
INT_MIC_L
MIC1_R

SPDIF_PLUG#
HP_L
HP_R

SPDIF

USB20_N4
USB20_P4

USB20_N2
USB20_P2

Int MIC Conn.

FBMA-11-100505-301T 0402

1

C541

@

2

1 2

L47 FBMA-11-100505-301T 0402

Title

AMP & Audio Jack

Size Document Number Rev

Custom

HEL80 LA-3161P

Date: Sheet

E

JP18

1
2
3
4

ACES_85204-0400

2

D27
PSOT24C_SOT23

G

SPDIF_PLUG#

2

Q27
SI2301BDS_SOT23

20mil

ME@

2

3

1

+5VSPDIF

3

+5VAMP

S

1

D

1 3

L
H
H

JP19

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

ACES_87213-2000

ME@

11/10 Modify pn to SP02000BJ00

15mil

MIC1

1

1

2

2

3

GND

4

GND

ACES_88231-02001

PN : SP02000EZ00

Compal Electronics, Inc.

E

0.2

of

29 43Thursday, F e b r u a ry 23, 2006

5

4

3

2

1

INT_KBD CONN.( TYPE "D" KB)

D D

C C

2005/12/21 Modified library pn:SP01000MZ00
2005/12/21 Modified footprint : ACES_88502-2501_25P

KSI[0..7]

KSO[0..15]

JP13

25

25

KSO15

24

24

KSO10

23

23

KSO11

22

22

KSO14

21

21

KSO13

20

20

KSO12

19

19

KSO3

18

18

KSO6

17

17

KSO8

16

16

KSO7

15

15

KSO4

14

14

KSO2

13

13

KSI0

12

12

KSO1

11

11

KSO5

10

10

KSI3

9

9

KSI2

8

8

KSO0

7

7

KSI5

6

6

KSI4

5

5

KSO9

4

4

KSI6

3

3

KSI7

2

2

KSI1

1

1

ACES_85202-2505L_25P_P1

KSI[0..7] <31>

KSO[0..15] <31>

KSI1
KSI7
KSI6
KSO9

KSI4
KSI5
KSO0
KSI2

KSI3
KSO5
KSO1
KSI0

KSO2
KSO4
KSO7
KSO8

KSO6

KSO3
KSO12
KSO13

KSO14
KSO11
KSO10
KSO15

C109 100P_0402_50V8J@

1 2

C114 100P_0402_50V8J@

1 2

C118 100P_0402_50V8J@

1 2

C115 100P_0402_50V8J@

1 2

C119 100P_0402_50V8J@

1 2

C120 100P_0402_50V8J@

1 2

C121 100P_0402_50V8J@

1 2

C123 100P_0402_50V8J@

1 2

C124 100P_0402_50V8J@

1 2

C127 100P_0402_50V8J@

1 2

C128 100P_0402_50V8J@

1 2

C125 100P_0402_50V8J@

1 2

C129 100P_0402_50V8J@

1 2

C126 100P_0402_50V8J@

1 2

C104 100P_0402_50V8J@

1 2

C105 100P_0402_50V8J@

1 2

C106 100P_0402_50V8J@

1 2

C110 100P_0402_50V8J@

1 2

C111 100P_0402_50V8J@

1 2

C112 100P_0402_50V8J@

1 2

C113 100P_0402_50V8J@

1 2

C116 100P_0402_50V8J@

1 2

C117 100P_0402_50V8J@

1 2

C122 100P_0402_50V8J@

1 2

ON/OFFBTN#<34>

EC_ON<31>

Power BTN

TOP Side

J2 JOPEN@
J5 JOPEN@

Bottom Side

ON/OFFBTN#

EC_ON

12
12

R268

10K_0402_5%

DAN202U_SC70

1 2

1

2N7002_SOT23

+3VALW

12

R267
100K_0402_5%

D6

ON/OFF#

2

51ON#

3

2

G

Q11

2

C377

13

D

1

1000P_0402_50V7K

S

12

D4
RLZ20A_LL34

ON/OFF# <31>
51ON# <34,36>

B B

JP16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+5VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
PCI_RST#

SIRQ

+3VS

CLK_14M_SIO <15>

LPC_FRAME# <19,31,35>
LPC_DRQ#0 <19>

PCI_RST# <18,23,25>
CLK_PCI_DB <15>

SIRQ <20,23,31,35>

FOR LPC SIO DEBUG PORT

LPC_AD[0..3]

R140 10K_0402_5%

LPC_AD[0..3] <19,31,35>

12

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

ACES_85201-2005

A A

ME@

JP24

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_85201-2005

PCI_CBE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_AD8
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_AD9

PCI_CBE#0 <18,23,25>
PCI_AD6 <18,23,25>
PCI_AD4 <18,23,25>
PCI_AD2 <18,23,25>
PCI_AD0 <18,23,25>
PCI_AD1 <18,23,25>
PCI_AD3 <18,23,25>
PCI_AD5 <18,23,25>
PCI_AD7 <18,23,25>
PCI_AD8 <18,23,25>
PCI_CBE#1 <18,23,25>
PCI_CBE#2 <18,23,25>
PCI_CBE#3 <18,23,25>

CLK_PCI_DB <15>

+5VS

PCI_RST# <18,23,25>
PCI_FRAME# <18,23,25>
PCI_TRDY# <18,23,25>
PCI_AD9 <18,23,25>

FOR PORT 80 DEBUG PORT EC DEBUG PORT

+5VALW

EC_TX<31>

EC_TX

JP26

1

1

2

2

3

3

4

4

ACES_85205-0400

ME@

Not lead free Not lead free

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

KBD,ON/OFF,T/P,LED/B,DEBUG

HEL80 LA-3161P

1

of

30 43Thursday, F e b r u a ry 23, 2006

0.2

5

C255

1 2

12

C500

1 2

+3VALW

R436

@

1 2

100P_0402_50V8J@

Pin name

2

1

ECAGND

R465 10_0402_5%@

R202

4.7K_0402_5%

@

1 2

C496

90
30
97
19

1

C261
1000P_0402_50V7K

2

12

+3VALW

1

2

+3VALW

R440

10K_0402_5%@

1 2

EC_PME#

1

C495

100P_0402_50V8J@

2

Pin number
PROGRAM_BTN#
INTERNET#
EMAIL#
USER_DEFINED#

1 2

R143 47K_0402_5%

0.1U_0402_16V4Z

KSO[0..15]<30>

KSI[0..7]<30>

USER_DEFINED#<34>

2/20 New pin define

L5
FBM-L11-160808-800LMT_0603

+3VALW +EC_AVCC

D D

C C

PCI_PME#<18>

+3VALW

RP17

1 8
2 7
3 6
4 5

100K_1206_8P4R_5%

+5VALW

1 2

R191 4.7K_0402_5%

1 2

R195 4.7K_0402_5%

B B

+3VS

1 2

R444 4.7K_0402_5%

1 2

R452 4.7K_0402_5%

A A

1 2

0.1U_0402_16V4Z
L6

FBM-L11-160808-800LMT_0603

CLK_PCI_LPC<15>

22P_0402_50V8J@

R446 0_0402_5%

FRD#
FSEL#

EC_SMB_CK1
EC_SMB_DA1

4.7K_0402_5%

EC_SMB_CK2
EC_SMB_DA2

2/20 New added

5

2

C233

1

EC_SMI#<20>

User-1
User-2
INTERNET
EMAIL

4

+3VALW

C327

0.1U_0402_16V4Z

C316

0.1U_0402_16V4Z

1

2

PCI_CLKRUN#<20,35>

PROGRAM_BTN#<34>

CHARGE_LED0#<34>
CHARGE_LED1#<34>

SCROLL_LED#<34>

EC_RSMRST#<20>
BKOFF#<16>

EC_LID_OUT#<20>

1

2

GATEA20<19>

KB_RST#<19>

LPC_FRAME#<19,30,35>

LPC_AD3<19,30,35>
LPC_AD2<19,30,35>
LPC_AD1<19,30,35>
LPC_AD0<19,30,35>

PLT_RST#<7,17,18,20,22,26,27,35>

EC_SCI#<20>

KSO[0..15]
KSI[0..7]

RCIRRX<35>

EC_SMB_DA2<4>
EC_SMB_CK2<4>

EC_SMB_DA1<32,37>
EC_SMB_CK1<32,37>

EC_TX<30>

SLP_S4#<20>

PWR_LED#<34>

NUM_LED#<34>

CAPS_LED#<34>

SYSON<33,35,40>

SLP_S3#<20>
SLP_S5#<20>

R460 0_0402_5%

LID_SWITCH#<33>

SUSP#<17,32,33,35,40,41>

PBTN_OUT#<20>

SIRQ<20,23,30,35>

1 2

C328

0.1U_0402_16V4Z

C502

0.1U_0402_16V4Z

1

2

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

EC_RST#
EC_SCI#

1 2

R148 0_0402_5%@

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
RCIRRX
PROGRAM_BTN#

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

EC_TX
PWR_LED#

NUM_LED#
CHARGE_LED0#
CHARGE_LED1#
CAPS_LED#
SCROLL_LED#
SYSON

EC_RSMRST#
BKOFF#
SLP_S3#
EC_LID_OUT#
SLP_S5#
EC_SMI#

LID_SWITCH#
SUSP#
PBTN_OUT#
EC_PME#

CRY1
CRY2

1

2

C235

1000P_0402_50V7K

C276

1000P_0402_50V7K

1

1

2

2

U13

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

63

KSI0/GPIO30

64

KSI1/GPIO31

65

KSI2/GPI032

66

KSI3/GPIO33

67

KSI4/GPIO34

68

KSI5/GPI035

69

KSI6/GPIO36

70

KSI7/GPIO37

47

KSO0/GPIO20

48

KSO1/GPIO21

49

KSO2/GPIO22

50

KSO3/GPIO23

51

KSO4/GPIO24

52

KSO5/GPIO25

53

KSO6/GPIO26

54

KSO7/GPIO27

55

KSO8/GPIO28

56

KSO9/GPIO29

57

KSO10/GPIO2A

58

KSO11/GPIO2B

59

KSO12/GPIO2C

60

KSO13/GPIO2D

61

KSO14/GPIO2E

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

INTERFACE

key Matrix

Host

scan

3

3

+EC_AVCC

127

141

75

26

37

105

11

VCC/ EC VCC

SM BUS

GND

129

139

BATTEMP/AD0/GPIO38

VCC

VCC

BATT OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD BID0/AD3/GPIO3B

VCC / EC VCC

VCC / EC VCC

VCC / EC VCC

PWR

FAN/PWM

GND13GND28GND

GND

GND

103

AD INtput or GPI

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D

EN DFAN1/DA1/GPIO3D

IREF2/DA2

EN DFAN2/DA3/ GPIO3F

DA output or GPO

INVT_PWM/GPIO0F/PWM1

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PSCLK1
PSDAT1

KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

SELIO2#/ GPIO43

SELIO#/ GPIO50

FRD#/RD#

FWR#/WR#

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ECTHERM#/GPIO11

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

AGND

77

ECAGND

PSCLK2
PSDAT2
PSCLK3
PSDAT3

ADB0/D0
ADB1/D1
ADB2/D2

ADB3/ D3

ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7

KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8
KBA9/A9

KB910L_LQFP144

Compal Secret Data

PS2 interface

Data
BUS

Address

BUS

39

2005/10/06 2006/10/06

BATT_TEMP

71

BATT_OVP

72
73

SKU_ID

74

DAC_BRIG

76

EN_FAN1

78

IREF

79
80

INVT_PWM

25

BEEP#

27

INTERNET#

30

ACOFF

31

FAN_SPEED1

32

MB_ID

33

MODE#

91

VOL_UP#

92

VOL_DN#

93

STOP#

94

TP_CLK

95

TP_DATA

96

ADB0

125

ADB1

126

ADB2

128

ADB3

130

ADB4

131

ADB5

132

ADB6

133

ADB7

134

KBA0

111

KBA1

112

KBA2

113

KBA3

114

KBA4

115

KBA5

116

KBA6

117

KBA7

118

KBA8

119

KBA9

120

KBA10

121

KBA11

122

KBA12

123

KBA13

124

KBA14

110

KBA15

109

KBA16

108

KBA17

107

KBA18

106

KBA19

98

ENBKL

84

EMAIL#

97

FRD#

135

FWR#

136

FSEL#

144

EC_ON

41

ACIN

43

EC_THERM#

29

ON/OFF#

36

ICH_POK

45

RF_ON#

46

EC_MUTE

81

FSTCHG

82

VR_ON

83

BTPWR_ON#

137

VGATE

142

KILL_SW#

143

Deciphered Date

12/9 Modified with pin 35

2

12

C268 0.01U_0402_16V7K

BATT_OVP <38>

DAC_BRIG <16>
EN_FAN1 <4>
IREF <38>

T23PAD

INVT_PWM <16>
BEEP# <28>

INTERNET# <34>
ACOFF <36,38>
FAN_SPEED1 <4>

MODE# <34>
VOL_UP# <34>
VOL_DN# <34>

STOP# <34>

TP_CLK <34>

TP_DATA <34>

KBA[0..19]<32>

ADB[0..7]<32>

ENBKL <16>
EMAIL# <34>
FRD# <32>
FWR# <32>

FSEL# <32>
EC_ON <30>

ACIN <20,36>
EC_THERM# <20>
ON/OFF# <30>
ICH_POK <7,20>

RF_ON# <27>

EC_MUTE <29>
FSTCHG <38>
VR_ON <42>
BTPWR_ON# <27>
VGATE <15,20,42>
KILL_SW# <33>

2

Analog Board ID definition,
Please see page 3.

SKU_ID

0.1U_0402_16V4Z

ECAGND

C244 0.1U_0402_16V4Z

BATT_TEMP <37>

POUT <42>

1 2

KBA[0..19]
ADB[0..7]

10P_0402_50V8K

Compal Electronics, Inc.

Title

ENE-KB910L

Size Document Number Rev

HEL80 LA-3161P

Custom

Thursday, February 23, 2006

Date: Sheet

+3VALW

R416

100K_0402_5%

1

C493

R420

2

0_0402_5%

VGA@

MB_ID

EC_MUTE

R174 10K_0402_5%

INTERNET#

R529 10K_0402_5%

EMAIL#

R530 10K_0402_5%

TP_CLK

1 2

R211 4.7K_0402_5%

TP_DATA

1 2

R216 4.7K_0402_5%

KBA1

1 2

R238 1K_0402_5%

KBA4

1 2

R239 1K_0402_5%

KBA5

1 2

R240 1K_0402_5%

CRY1 CRY2

1

C335

2

X1

32.768KHZ_12.5P_1TJS125DJ2A073

1

Ra

1 2

Rb

1 2

100K_0402_5%

1 2
1 2
1 2

R242

20M_0603_5%@

4

1

IN

OUT

NC3NC

2

1

+3VALW

R166

15W@

R159

0_0402_5%

14W@

31 43

For HEL81

R420

8.2K_0402_5%

UMA@

Ra

1 2

Rb

1 2

+3VALW

+5VS

+3VALW

1

C334
10P_0402_50V8K

2

of

0.2

FWE#

C508

1 2

0.1U_0402_16V4Z

4

NC7SZ32P5X_NL_SC70-5

U33

+3VALW

Y

GND

+5VALW

12

R488
100K_0402_5%

1

A0

2

A1

3

A2

4

12

R459
100K_0402_5%

+5VALW

C497 0.1U_0402_16V4Z

1 2

+3VALW

12

R493
100K_0402_5%

5

2

B

Vcc

A

G

3

1

2

G

1 3

D

Q23
2N7002_SOT23

S

SUSP# <17,31,33,35,40,41>

EC_FLASH# <20>

FWR# <31>

EC_SMB_CK1<31,37>
EC_SMB_DA1<31,37>

U31

8

VCC

7

WP

6

SCL

5

SDA

AT24C16N10SC-2.7_SO8

FOR DEBUG ONLY

FSEL#<31>

SN74AHCT1G125DCKR_SC70-5

+3VALW

U29

1

5

P

A2Y

G

3

1 2

R396 0_0402_5%@

INT_FLASH_EN#

4

OE#

12

+3VALW

C489 0.1U_0402_16V4Z

R391 100K_0402_5%

1 2

R392 22_0402_5%
R390
10K_0402_5%

1 2

1 2

INT_FSEL#FSEL#

12/9 Modified BOM Structure

KBA[0..19]<31>
ADB[0..7]<31>

KBA[0..19]
ADB[0..7]

FRD#<31>

1MB Flash ROM

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

INT_FSEL#
FRD#
FWE#

U32

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

SST39VF080-70_TSOP40

VCC0
VCC1

READY/BUSY#

GND0
GND1

RP#

NC0
NC1

+3VALW

31
30

ADB0

25

D0
D1
D2
D3
D4
D5
D6
D7

NC

ADB1

26

ADB2

27

ADB3

28

ADB4

32

ADB5

33

ADB6

34

ADB7

35

RESET#

10
11
12
29
38

23
39

R489

1 2

100K_0402_5%

1

C491

0.1U_0402_16V4Z

2

+3VALW

SB_INT_FLASH_SEL tie to ATI SB
GPIO1 and pull down

SB_INT_FLASH_SEL<20>

1MB ROM Socket

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
INT_FLASH_EN#
SB_INT_FLASH_SEL
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

JP27

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

SUYIN_80065AR-040G2T

KBA17

KBA19
KBA10
ADB7
ADB6
ADB5
ADB4

ADB3
ADB2
ADB1
ADB0
FRD#

FSEL#
KBA0

+3VALW

Not Lead Free

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BIOS & EC I/O Port

HEL80 LA-3161P

of

32 43Thursday, Febru a ry 23, 2006

0.2

A

B

C

D

E

F

G

H

I

J

+5VALW to +5VS Transfer +3VALW to +3VS Transfer +1.8V to +1.8VS Transfer

C346

+3VALW

1

2

1

C326

0.1U_0603_25V7K

2

U15

8

D

7

D

6

D

5

D

SI4800BDY_SO8

+3VS

1

S

2

S

3

S

G

1

4

C349
10U_0805_10V4Z

2

1

C348

0.1U_0402_16V4Z

2

10U_0805_10V4Z
R304
33K_0402_5%

13

SUSPSUSP

D

Q18

2

2N7002_SOT23

G

S

1

C408

2

1

2

8
7
6
5

C407

0.1U_0603_25V7K

U25

S

D

S

D

S

D

G

D

SI4800BDY_SO8

AOS 4422

+1.8VS

1
2
3

1

4

C145
10U_0805_10V4Z

2

1

C155

0.1U_0402_16V4Z

2

1 1

+VSB

1 2

13

D

S

10U_0805_10V4Z

Q32
2N7002_SOT23

R528

10K_0402_5%

2 2

SUSP

2

G

+5VALW +5VS +1.8V

U37

1

C529

2

1

C530

0.1U_0603_25V7K

2

8
7
6
5

AOS 4422 AOS 4422

S

D

S

D

S

D

G

D

SI4800BDY_SO8

1
2
3
4

1

C528
10U_0805_10V4Z

2

1

C527

0.1U_0402_16V4Z

2

+VSB +VSB

10U_0805_10V4Z

12

R236
47K_0402_5%

13

D

Q9

2

2N7002_SOT23

G

S

3 3

SYSON<31,35,40> SUSP#<17,31,32,35,40,41>

+5VALW +5VALW

12

R271
47K_0402_5%

SYSON#

2

G

13

D

S

Q12
2N7002_SOT23

SUSP<41>

SUSP

R525
10K_0402_5%

1 2
13

D

Q31

2

2N7002_SOT23

G

S

R527
470_0603_5%

@

1 2
13

D

S

SUSP

2

G

Q30
2N7002_SOT23

+1.8VS

R526
470_0603_5%

@

1 2
13

D

S

R295
470_0603_5%

@

1 2
13

SUSP

2

G

Q29
2N7002_SOT23

D

S

SUSP

2

G

Q17
2N7002_SOT23

R296
470_0603_5%

@

1 2
13

D

S

2

G

Q16
2N7002_SOT23

+2.5VS+1.8V+0.9VS+5VS

R62
470_0603_5%

@

1 2
13

D

S

SUSPSYSON#

2

G

Q3
2N7002_SOT23

4 4

LID Switch

CMOS Camera Conn

+3VALW

5 5

1 2

R141 0_0402_5%

0.1U_0402_16V4Z

C223

1

2

12/9 Change t o SA032120010

6 6

R151 100K_0402_5%

U6

2

VDD

3

OUTPUT

GND

1

A3212ELHLT-T_SOT23W-3

1 2

+5VS

1

C242
10P_0402_50V8K

LID_SWITCH# <31>

USB20_N3<20>
USB20_P3<20>

4.7U_0805_10V4Z

USB20_N3
USB20_P3

2

1

C385

1

C386

0.1U_0402_16V4Z

2

2

@

2

3

1

D14
PSOT24C_SOT23

@

JP11

1

1

2

2

3

3

4

4

5

5

6

GND1

7

GND2

ACES_88266-05001

ME@

Finger Print board + MP3 Module CONN.

For EMI

1

D19
PSOT24C_SOT23

@

2

C169

@

3

1

1

2

2

C170

0.1U_0402_16V4Z

+3VS

T15 PAD

USB20_P5
USB20_N5

FPR_SW

4.7U_0805_10V4Z

USB20_P5<20>

7 7

USB20_N5<20>

JP14

6

6

G2

5

5

G1

4

4

3

3

2

2

1

1

ACES_85202-0605L

8
7

KILL_SW#<31>

Kill Switch

+3VS

R269 10K_0402_5%

KILL_SW#

SW5

12

3

3

2

2

1

1

1BS003-1211L_3P

ACES

8 8

A

B

C

D

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2005/10/06 2006/10/06

F

Compal Secret Data

Deciphered Date

G

Title

Size Document Number Rev

Custom

H

Date: Sheet

Compal Electronics, Inc.

DC/DC Circuit

HEL80 LA-3161P

I

33 43Thursday, February 23, 2006

0.2

of

J

5

4

3

2

1

USB Port

+5VS

D D

C C

B B

0.1U_0402_16V4Z

USB20_N0<20>
USB20_P0<20>

4.7U_0805_10V4Z

C203

PSOT24C_SOT23

+5VS

C526

2

1

2

3

D20

@

1

1

2

U3

1

GND

2

IN

3

IN

4

EN#

G528_SO8

150U_D_6.3VM

C419

10P_0402_50V8K

U36

1

GND

2

IN

3

IN

4

EN#

G528_SO8

Switch Board CONN.

+5VS

+5VALW

PWR_LED#<31>

EMAIL#<31>

USER_DEFINED#<31>

ON/OFFBTN#<30>

PROGRAM_BTN#<31>

INTERNET#<31>

A A

SCROLL_LED#<31>

NUM_LED#<31>
CAPS_LED#<31>

5

ON/OFFBTN#

C194

0.1U_0402_16V4Z

2

1

@

+USB_VCCA

8

OUT

7

OUT

6

OUT

5

FLG

1000P_0402_50V7K

1

+

C168

2

2

C418
10P_0402_50V8K

1

@

8

OUT

7

OUT

6

OUT

5

FLG

JP12

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

ACES_85202-1405L

USB_OC#0

1

C190
1000P_0402_50V7K

2

@

2

1

1

2

+USB_VCCB

1

2

G1
G2

+USB_VCCA

C173

JP44

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004G565ZR

ME@

USB_OC#2

C525
1000P_0402_50V7K

@

15
16

USB_OC#0 <20>

USB_OC#2 <20>

4

T/P Board

JP43

1

1

2

2

3

3

4

4

5

7

5

G1

6

8

6

G2

ACES_85202-0605L

WIRELESS_LED#<27>

BTON_LED#<27>

3IN1_LED#<23>

PIDE_LED#<22>
SATA_LED#<19>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

U20

PIDE_LED#
SATA_LED#

CHARGE_LED0#<31>

CHARGE_LED1#<31>

PWR_LED#<31>

3

2
1

2
1

U21

2005/10/06 2006/10/06

B
A

+3VS

B
A

5

3

+3VS

P

G

+5VS

Y

5

P

G

3

Y

PWR_LED#

SWR# <35>
SWL# <35>

TP_CLK <31>
TP_DATA <31>

4

4

Compal Secret Data

2N7002_SOT23-3

2N7002_SOT23-3

2N7002_SOT23-3

Deciphered Date

IOMP Board

JP5

7

G1

8

G2

ACES_85202-0605L

+5VS

12

R543

10K_0402_5%

2

G

Q37

+5VS

R544

10K_0402_5%

2

G

Q39

+5VS

R545

10K_0402_5%

2

G

Q41

R273 300_0402_5%

1 2

R274 300_0402_5%

1 2

R276 300_0402_5%

1 2

13

2

G

13

D

S

12

13

2

G

13

D

S

12

13

2

G

13

D

S

2

1

1

2

2

3

3

4

4

5

5

6

6

D

Q36
2N7002_SOT23-3

S

D

Q38
2N7002_SOT23-3

S

D

Q40
2N7002_SOT23-3

S

MODE_BTN#
VOL_DN#

STOP#

R272

1 2

300_0402_5%

R277

1 2

300_0402_5%

R275

1 2

300_0402_5%

CHARGE0

CHARGE1

HT-210UD/UYG_AMB/GRN

HT-110UYG-CT_YEL/GRN

1 2

D1

1

DAN202U_SC70

IOMP@

D8

1 2

HT-110UD_1204

AMBER_LED#

D7

HT-110UYG-CT_YEL/GRN

VALUE@

D11

HT-110UYG-CT_YEL/GRN

VALUE@

D10

2

3

D9

VALUE@

Custom

1

21

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

INDICATE LED

HEL80 LA-3161P

R6 100K_0402_5%

2

51ON#VOL_UP#

3

1 2

R5 100K_0402_5%

VOL_UP# <31>

1 2

R8 100K_0402_5%

VOL_DN# <31>

1 2

R7 100K_0402_5%

STOP# <31>

+5VS

21

21

+5VALW

1

MODE# <31>
51ON# <30,36>

+3VALW

+3VALW

+3VALW

D7

White LED

HIGH@

D11

White LED

HIGH@

2/20 Modified

D9

White LED

HIGH@

of

34 43Thursday, Febru a ry 23, 2006

+3VALW

0.2

A

B

C

D

E

F

G

H

I

J

New Card Power Sw itch

1 1

+3VS

+3VALW

+1.5VS

R163 100K_0402_5%

2 2

+3VALW

3 3

10U_0805_10V4Z

1 2

R168 100K_0402_5%

1 2

SUSP#<17,31,32,33,40,41>

SYSON<31,33,40>

PLT_RST#<7,17,18,20,22,26,27,31>

+3VS +1.5VS+3VALW

C312

1

2

C271

10U_0805_10V4Z

CP_USB#
CP_PE#
SUSP#
SYSON
PLT_RST#

1

2

U12

5

3.3Vin1

6

3.3Vin2

21

3.3Vaux_in

18

1.5Vin1

19

1.5Vin2

14

CPUSB#

15

CPPE#

4

STBY#
SHDN#3RCLKEN

2

SYSRST#

GND

11

1

C273

10U_0805_10V4Z

2

3.3Vout1

3.3Vout2

Aux_out

1.5Vout1

1.5Vout2

PERST#

NC11NC210NC312NC413NC5

24

60mils

7
8

40mil

20

40mil

16
17

23

OC#

RCLKEN1

22

PERST1#

9

TPS2231PWPR_PWP24

+3VS_CARD1

+3VALW_CARD1

+1.5VS_CARD1

+3VALW_CARD1 +3VS_CARD1 +1.5VS_CARD1

1

2

+3VS

12

13

D

S

1

C280

2

0.1U_0402_16V4Z

10K_0402_5%

CLKREQ1#

Q10
2N7002_SOT23

R232

C274

10U_0805_10V4Z

10K_0402_5%

RCLKEN1

R234

2

G

1

C293

10U_0805_10V4Z

2

+3VS +3VS

12

2

B

1

A

Imax = 1.35A Imax = 0.75AImax = 0.275A

1

C286

2

0.1U_0402_16V4Z

1

C324

0.1U_0402_16V4Z

2

5

4

Vcc

Y

G

U14

3

NC7SZ32P5X_NL_SC70-5

1

C253

10U_0805_10V4Z

2

CLKREQ_NC# <15>

1

2

C262

0.1U_0402_16V4Z

New Card Socket (Left)

1

USB20_N6<20>
USB20_P6<20>

ICH_SMBCLK<15,20,27>

ICH_SMBDATA<15,20,27>

+1.5VS_CARD1

ICH_PCIE_WAKE#<20,26,27>

+3VALW_CARD1

+3VS_CARD1

CLK_PCIE_NC1#<15>
CLK_PCIE_NC1<15>

PCIE_RXN4<20>
PCIE_RXP4<20>

PCIE_TXN4<20>
PCIE_TXP4<20>

CP_USB#

PERST1#

CLKREQ1#
CP_PE#

2005/11/4 Modified library pn:SP02000JC00

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27
28

FOXCONN 1CH4310C 26P P1 EXP_RVS

JP41

GND
USB_D­USB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLK­REFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

GND
GND

(NEW)

2005/12/9 Modified footprint to FOX_1CX43201_26P_LB

4 4

CIR

5 5

6 6

SWL#

Left switch

7 7

Right Switch

8 8

A

R270

100_0805_5%

CIR@

C380

4.7U_0805_10V4Z

CIR@

2
1

21

2
1

21

+3VALW

Update Part N u m ber to SCR36236000

12

CIR

IR1

Vs3OUT

1

6

6

5

5

SW3

4
3

SW4

4
3

B

GND

TSOP36236TR_4P

CIR@

1

2

SMT1-05_4P

VALUE@

ESD4@

NOT LEAD-FREE

SMT1-05_4P

VALUE@

ESD1@

NOT LEAD-FREE

GND

4
2

SWL#

Left switch

SWR#SWR#

Right Switch

RCIRRX

1

C379
1000P_0402_50V7K

2

CIR@

SWR#<34>

C

RCIRRX <31>

SWL#
SWR#

2
1

21

SMT1-05_4P

HIGH@

ESD3@

NOT LEAD-FREE

2
1

21

SMT1-05_4P

HIGH@

ESD2@

NOT LEAD-FREE

D5

PSOT24C_SOT23

3
2

SW2

5

6

SW1

5

6

D

+3VALW

U35

LAD0
LAD1
LAD2
LAD3

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP

G

+3VS

5

19

10

VSB

VDD24VDD

VDD

TESTB1/BADD

TPM
SLB 9635 TT 1.1

GND4GND11GND18GND

25

28

LPCPD#

9

R520 0_0402_5%TPM@

8

TEST1

XTALO

XTALI

GPIO2

GPIO

SLB-9635-TT-1.2_TSSOP28

TPM@

TPM_XTALO

14

TPM_XTALI

13

2
6

1

NC

3

NC

12

NC

TPM_XTALI

TPM_XTALO

H

+3VS

12

Base I/O Address

0 = 02Eh
1 = 04Eh

*

SUS_STAT# <20>

1 2

C523

18P_0402_50V8J

1 2

TPM@

R519

12

10M_0402_5%

X2

1

IN

4

OUT

1 2

C524
18P_0402_50V8J

Title

New card

Size Document Number Rev

Custom

HEL80 LA-3161P

Date: Sheet

R524

4.7K_0402_5%

TPM@

12

R521

4.7K_0402_5%

@

12/9 Modified to @

TPM@

2

NC

3

NC

32.768KHZ_12.5P_1TJS125DJ2A073TPM@

TPM@

Compal Electronics, Inc.

I

35 43Thursday, February 23, 2006

0.2

of

J

TPM 1.2

F

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

CLK_PCI_TPM
LPC_FRAME#
PLT_RST#
SIRQ
PCI_CLKRUN#

CLK_PCI_TPM

LPC_AD0<19,30,31>
LPC_AD1<19,30,31>
LPC_AD2<19,30,31>
LPC_AD3<19,30,31>

CLK_PCI_TPM<15>

+3VS

LPC_FRAME#<19,30,31>SWL#<34>

PLT_RST#<7,17,18,20,22,26,27,31>

SIRQ<20,23,30,31>

PCI_CLKRUN#<20,31>

1 2

R522 4.7K_0402_5%TPM@

2005/10/06 2006/10/06

1

4
3

4
3

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

26
23
20
17

21
22
16
27
15

7

R510
10_0402_5%@

1 2
2

C518
15P_0402_50V8J@

1

Note : TPM IC Lead free status is MN

Compal Secret Data

Deciphered Date

A

PJP1

JST_B5B-EH-A(LF)(SN)@

1

1

2

PR21
560_0603_5%

1 2

+CHGRTC

2
3
4
5

3
4
5

12

3.3V

PR22
560_0603_5%

1 2

VIN

12

PR10

12

PR14

PC5

1000P_0402_50V7K

RTCVREF

12

PC11

PJ1
PAD-OPEN 3x3m

21

PR12

84.5K_0402_1%

22K_0402_1%

1 2

20K_0402_1%

PU2
G920AT24U_SOT89

3

OUT

4.7U_0805_6.3V6K

+1.5VS+1.5VSP

1 1

2 2

3 3

12

GND

1

PC6

0.1U_0402_16V7K

IN

+1.8VP

ADPIN

FBMA-L18-453215-900LMA90T_1812

12

PC1

560P_0402_50V7K

PR175
10K_0402_1%

1 2

PR5
1M_0402_1%

1 2

VS

8

3

P

+

2

-

G

PU1A
LM393DG_SO8

4

PR16
10K_0402_1%

12

PR23
200_0805_5%

2

12

PC10

PL17

1 2

12

PC2

100P_0402_50V8J

PC131

0.01U_0402_25V7K

1 2

1

O

RTCVREF

12

1U_0805_25V4Z

51ON#<30,34>

PJ2

PAD-OPEN 3x3m

1 2

3.3V

BATT+

CHGRTCP

PR27
22K_0402_1%

1 2

12

12

PC3

100P_0402_50V8J

VS

12

PR9

10K_0402_1%

12

PD3

RLZ4.3B_LL34

PD5
RB751V-40TE17_SOD323-2

12

12

PR26

+1.8V

(6A,240mils ,Via NO.=12) (6A,240mils ,Via NO.= 12)

PJ3
PAD-OPEN 3x3m

+5VALWP

1 2

(5A,200mils ,Via NO.= 10)

4 4

+3VALWP

PJ6
PAD-OPEN 3x3m

1 2

+5VALW

+3VALW

+0.9VSP

(0.3A,40mils ,Via NO.= 2)

+2.5VSP

PJ4
PAD-OPEN 3x3m

1 2

PJ11
PAD-OPEN 3x3m

1 2

+0.9VS

+2.5VS

(4.5A,180mils ,Via NO.= 9)

PJ7
PAD-OPEN 3x3m

+1.05VSP

1 2

(5A,200mils ,Via NO.= 10)

+VCCP

+VSBP +VSB

A

(0.3A,40mils ,Via NO.= 2)

PJ8
PAD-OPEN 3x3m

1 2

PC4

560P_0402_50V7K

PR11
0_0402_5%

1 2

PACIN

12

PR15

10K_0402_1%

PQ4
TP0610K-T1-E3_SOT23

12

PC12

100K_0402_5%

B

C

ACIN

Precharge detector
Min. typ. Max.

H-->L 14.589V 14.84V 15.243V

VIN

12

PR1

10_1206_5%

12

PD1

RLZ24B_LL34

ACIN <20,31>

PACIN <38>

L-->H 15.562V 15.97V 16.388V

PD2
RLS4148_LLDS2

VS

12

Vin Detector

High 18.764 17.901 17.063

0.22U_1206_25V7K

Low 17.745 16.9 16.03

VIN

PD4

1 2

RLS4148_LLDS2

12

12

VS

PR20

PR267

68_1206_5%

68_1206_5%

13

12

PC13

2

0.1U_0603_25V7K

PD6
RB715F_SOT323

MAINPWON<37,39>

ACON<38>

2
3

VL

12

PR19

1

12

RTCVREF

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

C

ACOFF<31,38>

100K_0402_1%

LM393DG_SO8

PC8

0.1U_0603_25V7K

PR2
1K_1206_5%

1 2

PR3
1K_1206_5%

1 2

PR4
1K_1206_5%

1 2

PR8
1K_1206_5%

1 2

DTC115EUA_SC70

7

O

PU1B

2

PR17

2.2M_0402_5%

VS

8

P

+

-

G

4

PR28
34K_0402_1%

PQ2

12

5
6

12

D

BATT ONLY

Precharge detector

Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

PQ1
TP0610K-T1-E3_SOT23

13

12

12

PR7

PR6

13

12

PC9

1000P_0402_50V7K

100K_0402_5%

100K_0402_5%

DTC115EUA_SC70

D

S

12

PR30

@

66.5K_0402_1%

Title

Size Document Number Rev

B

Date: Sheet

2

12

PR13

100K_0402_5%

13

2

PQ3

12

PR24

191K_0402_1%

PRG++

PQ5
RHU002N06_SOT323

13

2

G

PR29
47K_0402_5%

13

PQ6
DTC115EUA_SC70

2

Compal Electronics, Inc.

DCIN/DECTOR

D

12

PR18

499K_0402_1%

12

PR25

499K_0402_1%

12

B+

12

PC7

36 43Thursday, February 23, 2006

0.01U_0402_25V7K

PACIN <38>

+5VALWP

0.2

of

A

PJP2

SUYIN_200275MR009G180ZR

2
3
4
5
6

1 1

7
8

9
G1
G2

CNT1

3

CNT2

4

EC_SMCA

5

EC_SMDA

6

TS_A

7

GND

8
9
10
11

12

PR31

100_0402_1%

12

PR35

100_0402_1%

1 2

PR176

1 2

PR177

100K_0402_5%@

1K_0402_1%

+3VALWP

BATT++

1

1

2

PR268

0_0402_5%

1 2

1 2

PR178

@

100K_0402_5%

1 2

PR36

2 2

12

PR38

1K_0402_1%

6.49K_0402_1%

PQ7
TP0610K-T1-E3_SOT23

B+

12

12

PR41

PC20

PR42

VL

22K_0402_1%

1 2

100K_0402_5%

2

0.22U_1206_25V7K

3 3

SPOK<39>

PR43

1 2

100K_0402_5%

1 2

PR44
0_0402_5%

13

D

2

G

PQ8

S

12

PC22

RHU002N06_SOT323

B

+3VALWP

+3VALWP

BATT++

12

PC14

1000P_0603_50V7K

EC_SMB_CK1 <31,32>
EC_SMB_DA1 <31,32>

PJ13
PAD-OPEN 3x3m

1 2

12

PC15

1000P_0603_50V7K

BATT_TEMP <31>

BATT+

12

PC16

0.01U_0603_50V7K

C

D

PH1 under CPU botten side :

CPU thermal protection at 85 degree C
Recovery at 70 degree C

VL

12

PR33

1 2

12

12

PC18

1000P_0402_50V7K

10.7K_0402_1%

PR37

61.9K_0603_1%

TM_REF1

PH1

12

100K_0603_1%_TH11-4H104FT

12

PC19

1U_0603_6.3V6M

PC17

12

0.1U_0603_25V7K

3

+

2

-

PR39
150K_0402_1%

PR40

150K_0402_1%

VS

PR34
442K_0603_1%

1 2

8

P

1

O

G

PU3A
LM393DG_SO8

4

12

VL

VL

PR32

1 2

150K_0402_1%

MAINPWON <36,39>

VS

13

+VSBP

12

PC21

0.1U_0603_25V7K
LM393DG_SO8

5
6

PU3B

8

P

+

7

O

-

G

4

0.1U_0402_16V7K

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.
BATTERY CONN. / OTP

D

37 43Thursday, February 23, 2006

of

0.1

A

B

75W PR45=0.02_2512_1% PR54=23.7K_0402_1%
90W PR45=0.15_2512_1% PR54=28.7K_0402_1%

Iadp=0~3.71A
Iadp=0~4.3A

C

Fosc=14100/Rt=14100/47=300KHz

D

E

Charger

1
2

12

0_0402_5%

B+

FBMA-L18-453215-900LMA90T_1812

PU4
MB39A126PFV-ER_SSOP24

1

-INC2

+INC2

2

OUTC2

GND

3

+INE2

CS

4

-INE2

VCC

5

ACOK

OUT

6

VREF

VH

7

ACIN

XACOK

8

-INE1

RT

9

+INE1

-INE3

10

OUTC1

FB123

11

SEL

CTL

12

-INC1

+INC1

BATT_OVP<31>

24

23

22

21

20

PC32

0.1U_0603_25V7K

19

18

PR58
47K_0402_1%

17

16

MB39A126

15

14

13

PL18

1 2

1 2

1 2

PR62
33K_0402_1%

1 2

PC40
10P_0402_50V8J

12

12

PR59

12

PR64

PC23

4.7U_1206_25V6K

47K_0402_5%

47K_0402_5%

PC41
47P_0402_50V8J

1 2

12

P2

12

CS

1 2

PR49

0_0603_5%

PC29

0.22U_0603_16V7K

1 2

PC30

0.1U_0603_25V7K

1 2

PC35
1500P_0603_50V7K

1 2

VIN

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

VS

12

PC42

8

PU12B

5

P

+

7

0

6

-

G

LM358ADR_SO8

4

12

PC24

4.7U_1206_25V6K

36

241

PQ13
AO4407_SO8

578

PL5

LXCHRG

10U_LF919AS-100M-P3_4.5A_20%

1 2

12

12

PD10

EC31QS04

BATT+

12

PR68

340K_0402_1%

12

PR69

0.01U_0402_25V7K
499K_0402_1%

12

PR72

105K_0402_1%

CHG_B+

PC25

0.1U_0603_25V7K

PD11

EC31QS04

12

PC26

2200P_0402_50V7K

12

PC43

0.01U_0402_25V7K

PQ9

AO4407_SO8

8

PQ12

47K

2

13

PQ15
DTC115EUA_SC70

7
5

4

47K

1 3

2

G

VIN

1 1

12

PR47

47K_0402_5%

DTA144EUA_SC70

2

13

D

2

ACOFF#

PACIN<36>

G

S

PQ16
RHU002N06_SOT323

PD12
RLS4148_LLDS2

1 2

PR66
22K_0402_1%

1 2

2 2

P2

1
2
36

12

PC27

0.1U_0603_25V7K

12

PR55

150K_0402_1%

IREF <31>

13

D

PQ17

S

RHU002N06_SOT323

IREF=0.932*Icharge

ACON<36>

3 3

IREF=0.466~2.8V

12

PR46

200K_0402_1%

PR60
133K_0402_1%

1 2

FSTCHG<31>

PQ10
AO4407_SO8

1
2
3 6

4

PR51

MB39A126

12

10K_0402_1%

1 2

12

12

PR53

PC31

10K_0402_1%

0.01U_0402_25V7K

12

12

PR63

100K_0402_1%

PR54

28.7K_0402_1%

PC33

12

2

8
7

5

MB39A126

0.22U_0603_16V7K

PC39

0.01U_0402_25V7K

+3VALWP

P3

PC28
4700P_0402_25V7K

1 2

PR57
1K_0402_1%

1 2

12

PR67

47K_0402_5%

2

13

PQ19
DTC115EUA_SC70

PR45

0.015_2512_1%

4
3

PR52
100K_0402_1%

PC34
2200P_0402_50V7K

1 2

CS

13

PQ18
DTC115EUA_SC70

12

PR61
10K_0402_1%

12

PR65

VS

8

PU12A

3

P

+

1

4 4

0

2

-

G

LM358ADR_SO8

4

PQ11
AO4407_SO8

1
2
3 6

PR56

0.02_2512_1%

1
2

4

PR48
47K_0402_1%

1 2

PR50

10K_0402_1%

1 2

ACOFF#

13

2

PQ14
DTC115EUA_SC70

4
3

8
7

5

ACOFF

12

PC36

CC=3A

(100K/(100K+133K))*2.8V=1.2V

1.2/(20*0.02)=3A

CP Point=4.3A

5V*(10K/(28. 7 k+10k))=1.292V

1.292V/(15*0.02)=4.3A

Charge voltage
3S CC-CV MODE : 12.6V
SEL is L

4.7U_1206_25V6K

VIN

12

PC37

ACOFF <31,36>

BATT+

12

PC38

4.7U_1206_25V6K

4.7U_1206_25V6K

BATT+

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

PWR-Charger

38 43Thursday, Febru a ry 23, 2006

E

0.1

of

A

B+

PL19
FBMA-L18-453215-900LMA90T_1812

1 2

1 1

B+++

PC45

0.1U_0603_25V7K

1 2

5

12

PC47

2200P_0402_50V7K

12

PC48

10U_1206_25VAK

D8D7D6D

S1S2S3G

PQ21

4

5HG

5

PR78
0_0603_5%

SI4800BDY-T1-E3_SO8

1 2

DH5

LX5

D8D7D6D

S1S2S3G

PQ29

4

SI4810BDY-T1-E3_SO8

DL5

2 2

+5VALWP

1

+

PC56

2

150U_V_6.3VM_R18

+5V Ipeak = 6.66A ~ 10A

3 3

PR85

1 2

@

PR87

1 2

PL7

1 2

4.7UH_PCMC063T-4R7MN_5.5A_20%

10.2K_0402_1%

0_0402_5%

VS

PZD1
RLZ5.1B_LL34

1 2

PR88
47K_0402_5%

1 2

PR91

1 2

100K_0402_5%

12

PC57

0.047U_0603_16V7K

B

1 2

PR94
47K_0402_5%

1 2

PR74

0_0603_5%

BST5A

1 2

2VREF_1999

0_0402_5%

1 2

12

PC61

0.047U_0603_16V7K

PR86
0_0402_5%

PR89

2

3

PD13

CHP202UPT_SOT323-3

1

B+++

12

12

VL

12

PC54

4.7U_0805_6.3V6K

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

MAX8734AEEI+_QSOP28

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

12

PC59

0.22U_0603_16V7K

PR76

4.7_1206_5%

PC52

18

LD05

23

GND

1U_0805_25V4Z

20

PU6

C

PC46

1 2

0.1U_0603_25V7K

1 2

B+++

PR79

0_0603_5%

BST3A

DH3

12

PC50

2200P_0402_50V7K

12

PC51

10U_1206_25VAK

LX3

PR82

0_0603_5%

1 2

DL3

BST3BBST5B

VL

PR75

1 2

4.7_1206_5%

47_0402_5%

12

PC49

0.1U_0402_16V7K

12

PR77

@

2VREF_1999

PC55

12

V+

25

12

0.1U_0603_25V7K

13

LDO3

TON

PC60

17

VCC

OUT3

PGOOD

PRO#

10

PR92

4.7U_0805_6.3V6K

1 2

12

ILIM3

ILIM5
BST3

DH3

DL3
LX3

FB3

0_0402_5%

PC53

5

11
28

26
24
27
22

7
2

1U_0805_16V7K

SPOK<37>

PR80

1 2

200K_0402_1%

PR83

1 2

499K_0402_1%

PR81

1 2

200K_0402_1%

PR84

1 2

499K_0402_1%

3HG

1 2

1 2

PR90

PR93

5

4

5

4

3.57K_0402_1%@

0_0402_5%

D

D8D7D6D

PQ20

S1S2S3G

SI4800BDY-T1-E3_SO8

D8D7D6D

PQ30

S1S2S3G

SI4810BDY-T1-E3_SO8

PL8

1 2

+3VALWP

4.7UH_PCMC063T-4R7MN_5.5A_20%

1

+

PC58

2

150U_V_6.3VM_R18

+3.3V Ipeak = 6.66A ~ 10A

MAINPWON <36,37>

12

PC62

1U_0603_6.3V6M

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

+5VALWP/+3VALWP

D

39 43Thursday, February 23, 2006

of

0.1

5

D D

4

3

2

1

OZ813_B+

FBMA-L18-453215-900LMA90T_1812

PR262

0_0402_5%@

1 2

18
17
16
15
14
13

DH_1.05V-1

0_0603_5%

1 2

12

12

+3VALWP

12

PR261

1K_0402_1%

@

PR272

DH_1.8V-2DH_1.8V-1

PC67

0.1U_0603_25V7K
RB751V-40TE17_SOD323-2

BST_1.8V

BST_1.05V

RB751V-40TE17_SOD323-2

1 2

DL_1.8V

12

PC71
1U_0805_16V7K

PD17

1 2

PC76

0.1U_0603_25V7K

DL_1.05V

PR273

0_0603_5%

1 2

DH_1.05V-2

PD16

+5VALWP

5

4

5

4

5

D8D7D6D

PQ22

S1S2S3G

4

SI4800BDY-T1-E3_SO8

5

D8D7D6D

PQ23

S1S2S3G

4

SI4810BDY-T1-E3_SO8

12

PC156

2.2U_0603_6.3V6K

D8D7D6D

12

S1S2S3G

PQ24

SI4800BDY-T1-E3_SO8

D8D7D6D

PQ31

S1S2S3G

SI4810BDY-T1-E3_SO8

1.8VS2N

1.8VS2P

PR105

1 2

PR106
150K_0402_1%

1 2

+5VALWP

PR99

1 2

22_0402_1%

DREF

PR104

1 2

100K_0402_1%

1.05SET

PR172

61.9K_0402_1%

1 2

12

PC132

0.1U_0402_16V7K@

1.8VSET

12

PC65

1000P_0402_50V7K

PU7

24

25

GNDA

PR100

1 2

1K_0402_1%

12

12

PC74

1U_0603_6.3V6M

PC75

0.01U_0402_25V7K

1
2
3
4
5
6

12

1000P_0402_50V7K

VSET2

ON/SKIP2
VIN
VREF
TSET
VDDA
ON/SKIP1

OZ813LN_QFN24

VSET17CS1N8CS1P9PGD110LX111HDR1

PC77

21

23

22

CS2P

CS2N

@

1 2

12

+3VALWP

19

20

LX2

PGD2

12

PR263

0_0402_5%

PR264

1K_0402_1%

@

HDR2

LX_1.8V

BST2

LDR2
VDDP
GDNP

LDR1

BST1

LX1.05V

1.05VS1P

1.05VS1N

PR266

0_0402_5%

SYSON<31,33,35>

C C

12

12

PC184

0.01U_0402_25V7K

@

PR101

0_0402_5%

12

12

12

PC73

PC72

PR103

24K_0402_1%

@

1 2

0.1U_0603_25V7K

75K_0402_1%

0.022U_0402_16V7K

1.8VSET

B B

PR179

0_0402_5%

SUSP#<17,31,32,33,35,41>

1 2

PC79

PR274

4.7_1206_5%

PC185

680P_0603_50V7K

10U_1206_25VAK

12

12

+5VALWP

PR275

4.7_1206_5%

PC186

680P_0603_50V7K

12

100K_0402_1%

1 2

12

12

PC63

10U_1206_25VAK

PL10

3.3UH_MPL73-3R3_6A_20%

1 2

PR97

1 2

PC68
6800P_0402_25V7K

1.8VS2P

1.8VS2N

12

PL11

3.3UH_MPL73-3R3_6A_20%

1 2

PR108

100K_0402_1%

1 2

1.05VS1P

1.05VS1N

PL20

1 2

12

PR98
22K_0402_1%

1 2

12

PC69

22P_0402_50V8J

OZ813_B+

PR109

1 2

29.4K_0402_1%

PC80

5600P_0402_50V7K

12

12

PC81

22P_0402_50V8J

28mohm

PR95

51_0402_1%

PC70

4700P_0402_25V7K

28mohm

12

PR107

51_0402_1%

12

PC82

B+

+1.8VP

OCP=6A

1

+

PC66

2

220U_D2_4VM_R15

+1.05VSP

OCP=6A

1

+

PC78

2

220U_D2_4VM_R15

4700P_0402_25V7K

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

1.05VP/1.8VP

Thursday, February 23, 2006

0.1

of

1

40 43

5

4

3

2

1

D D

C C

B B

SUSP#,31,32,33,35,40>

A A

B+

PJ17
PAD-OPEN 3x3m

1 2

SUSP#<17,31,32,33,35,40>

33K_0402_1%

1 2

0.01U_0402_25V7K

PR121

PC100

16

PGOOD

57.6K_0402_1%

PR119

15

PHASE

PR117

12

PHASE_VCCPP

13

14

UG

8

7

12

12

SUSP<33>

PR110

1 2

0_0603_5%

BOOT_VCCPP

BOOT

12

PVCC

11

LG

10

PGND

9

ISEN

VO

PC90

0.01U_0402_25V7K

UG_VCCPP-1

1 2

PC85 0.1U_0402_16V7K

12

PR111

4.7_0603_5%

@

PR112

1 2

4.7_0603_5%

1 2

2.2U_0603_6.3V6K

LG_VCCPP

ISEN_VCCPP

1 2

PR115

8.66K_0402_1%

ISL6269CRZ-T_QFN16

PR118

1 2

4.53K_0402_1%

22U_1206_6.3V6M

PR123

0_0402_5%

1 2

PC103

0.1U_0402_16V7K @

PC94

+5VS

6269_VCC

PC86

12

+1.8VP

1

PJ9

1

JUMP_43X118

2

2

12

1K_0402_1%

RHU002N06_SOT323

13

D

PQ28

2

G

S

PR269

0_0603_5%

1 2

UG_VCCPP-2

12

PR120

12

PR124
1K_0402_1%

5

4

5

4

PC101

0.1U_0402_16V7K

PQ26

D8D7D6D

S1S2S3G

SI4800BDY-T1-E3_SO8

3.3UH_MPL73-3R3_6A_20%

PQ27

D8D7D6D

SI4810BDY-T1-E3_SO8

S1S2S3G

12

12

PL13

1 2

PU9

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

+0.9VSP

PC102
22U_1206_6.3V6M

OCP=6A

+1.5VSP

1

+

PC88
220U_D2_4VM_R15

2

6
5

NC

7

NC

8

NC

9

TP

+3VALWP

12

PC95
1U_0603_6.3V6M

PR114

1 2

47K_0402_5%

12

PC83

10U_1206_25VAK

6269_VCC

12

PC87

2.2U_0603_6.3V6K

12

PC89

0.01U_0402_25V7K

PR113

1 2

0_0402_5%

PR265

10K_0402_1%

1 2

PU8

1

VIN

2

VCC

3

FCCM

4

EN

17

GND

COMP5FB6FSET

12

12

PC91

22P_0402_50V8J

PR116

49.9K_0402_1%

12

PC92
6800P_0402_25V7K

3K_0402_1%

+3VS

+5VS

12

PC93

1U_0603_6.3V6M

6

PU10

7

POK

8

EN

12

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

1

APL5912-KAC-TRL_SO8

1

PJ10

1

JUMP_43X79

2

2

12

PC96
22U_1206_6.3V6M

PR122

2.15K_0402_1%

12

12

PR125

1K_0402_1%

12

PC99

0.01U_0402_25V7K

+2.5VSP

1

12

+

PC98

150U_D_6.3VM@

PC97

2

22U_1206_6.3V6M

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

+VCCPP/+2.5VSP/0.9VSP

Thursday, February 23, 2006

0.1

of

1

41 43

5

4

3

2

1

+5VS

DH1_CPU-2

PQ33
AO4410_SO8

241

PQ37
AO4410_SO8

CPU_B+

DL1__CPU

1 2

PR246
3K_0603_1%@

DL2__CPU

PQ32
SI7840DP-T1-E3_SO8

3 5

241

578

PQ34

3 6

241

PR237 0_0402_5%

1 2

1 2

PC173

470P_0402_50V8J

PQ35
SI7840DP-T1-E3_SO8

29.6

3 5

241

578

PQ36
AO4410_SO8

3 6

241

12

PC159

10U_1206_25VAK

4.7_1206_5%

PR224

AO4410_SO8

12

12

PC161

PC160

PC162

0.1U_0603_25V7K

10U_1206_25VAK

10U_1206_25VAK

PL15

P_0.36H_ETQP4LR36WFC_24A_20%

12

PR226

3.48K_0402_1%

1 2

2.1K_0402_1%

12

1 2

PR230

1 2

10KB_0603_5%_ERTJ1VR103J

PC167

680P_0603_50V7K

<BOM Structure>

PC172
4700P_0402_25V7K

1 2

PC169 0.22U_0603_16V7K

PC1710.022U_0402_16V7K

1 2

1 2

PR243 100_0402_5%

PC176

12

PR256

12

4.7_1206_5%

PR257

12

2.1K_0402_1%

PC182

680P_0603_50V7K

FBMA-L18-453215-900LMA90T_1812

12

12

PC163

2200P_0402_50V7K

12

NTC

PH2

1 2

CPU_VCC_SENSE

12

12

PC177

PC178

10U_1206_25VAK

10U_1206_25VAK

P_0.36H_ETQP4LR36WFC_24A_20%

3.48K_0402_1%

1 2

10U_1206_25VAK

PL16

PR258

10KB_0603_5%_ERTJ1VR103J

PR214

12

PR215
10_0402_5%

D D

PR217

13K_0402_5%

NTC

100K_0402_5%

PR218

1 2

PR219 0_0402_5%
PR221 0_0402_5%
PR222 0_0402_5%
PR223 0_0402_5%
PR225 0_0402_5%
PR227 0_0402_5%
PR228 0_0402_5%

C C

PR233 499_0402_1%
PR234 0_0402_5%
PR236 0_0402_5%

DPRSLPVR<7,20>
H_DPRSTP#<4,19>

+3VS

CPU_VID0<5>
CPU_VID1<5>
CPU_VID2<5>
CPU_VID3<5>
CPU_VID4<5>
CPU_VID5<5>
CPU_VID6<5>

H_PSI#<5>

1 2

1 2

1 2

1 2

12
12
12
12
12
12

1 2

VCC

PR232 71.5K_0402_1%

1 2

12
12

PC168470P_0402_50V8J

PC170 0.22U_0603_16V7K

PR240

10K_0402_1%

1 2

PR250

10K_0402_5%@

PR244

0_0402_5%

VGATE<15,20,31>

CLK_ENABLE#<15>

VR_ON<31>

1 2

0_0402_5%
PR247

@

1 2

1 2

PR249

0_0402_5%

1 2

B B

H_PROCHOT#<4>

POUT<31>

PR241

2K_0402_1%@

1 2

PR253 0_0402_5%

PC181

0.1U_0402_16V7K

1 2

PR252

@

56_0402_5%

1 2

1 2

PR254 10K_0402_5%

+3VS

12

5VS1

PC165
1U_0603_6.3V6M

1 2

PU11

19

Vcc

6

THRM

31

D0

32

D1

33

D2

34

D3

35

D4

36

D5

37

D6

7

TIME

9

CCV

11

REF

39

DPRSLPVR

40

DPRSTP

3

PSI

2

PWRGD

1

CLKEN

38

SHDN

5

VRHOT

4

POUT

MAX8770GTL+_TQFN40

VSSENSE<5>

12

0_1206_5%

PC164

2.2U_0603_6.3V6K

VDD

TON

BST1

DH1

LX1

DL1

PGND1

GND

CSP1

CSN1

FB

CCI

DH2

BST2

LX2

DL2

PGND2

CSP2

CSN2

GNDS

PC174

1000P_0402_50V7K

VSSENSE

12

12

PR216

1 2

200K_0402_5%

25
8
30
29
28
26

0_0603_5%

BST1_CPU BSTM1_CPU

PR220

1 2

DH1__CPU-1
LX1__CPU
DL1__CPU

27
18

CSP1__CPU

17

CSN1_CPU

16

FB_CPU

12

CCI_CPU

10

DH2_CPU-1

21

BST2_CPU

20

LX2_CPU

22

DL2__CPU

24
23

CSP2_CPU

14

CSN2__CPU

15
13

1 2

PR251

100_0402_5%

10_0402_5%

PR255

1 2

12

PC157

0.01U_0402_25V7K

0.22U_0603_16V7K

PR239

0_0603_5%

1 2

BSTM2_CPU

12

PC175

0.22U_0603_16V7K

PC166

1 2

2.2_0603_5%
PR270

1 2

PR238 3K_0603_1%

PR242 2.61K_0402_1%

1 2

NTC

PR245

3K_0603_1%@

1 2

PR248

20K_0402_1%

2.2_0603_5%
PR271

1 2

578

3 6

1 2

1 2

DH2_CPU-2

578

3 6

241

1

+

2

12

PC179

12

1 2

1 2

PC158

100U_25V_M

+CPU_CORE

12

VCCSENSE<5>

PR229 10_0402_5%@

CPU_B+

12

0.1U_0603_25V7K

NTC

PL14

+CPU_CORE

PR235
100_0402_5%

1 2

12

PC180

2200P_0402_50V7K

PH3

B+

12

PC187
680P_0402_50V7K

1 2

A A

PR260 0_0402_5%

1 2

PC183 0.22U_0603_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/10/17 2006/10/17

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

+CPU_CORE

1

0.1

of

42 43Thursday, February 23, 2006

5

D D

4

CF10

CF13

CF7

CF6

FM4

CF3

1

1

CF14

1

FM2

1

1

1

1

CF12

CF11

1

1

FM3

1

1

FM1

1

1

CF8

CF2

1

3

CF1

1

CF4

1

1

CF5

CF9

1

2

1

H1

C C

2/13 Modified

B B

HOLEA

1

H11
HOLEA

1

H21
HOLEA

1

H28
HOLEA

1

H2
HOLEA

1

H12
HOLEA

1

H22
HOLEA

1

H29
HOLEA

1

H3
HOLEA

1

H13
HOLEA

1

H23
HOLEA

1

H30
HOLEA

H4
HOLEA

1

H14
HOLEA

1

H24
HOLEA

1

1

H5
HOLEA

1

H15
HOLEA

1

H6
HOLEA

1

H7
HOLEA

1

H17
HOLEA

1

H25
HOLEA

1

H31
HOLEA

1

H8
HOLEA

1

H18
HOLEA

1

H26
HOLEA

1

H32
HOLEA

1

H9
HOLEA

1

H19
HOLEA

1

H27
HOLEA

1

H33
HOLEA

1

H10
HOLEA

1

H20
HOLEA

1

H16
HOLEA

1

H34
HOLEA

1

2/13 New added

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.
Holes

43 43Thursday, Febru a ry 23, 2006

1

0.1

of