Acer LA-2581P Schematics

5

4

3

2

1

http://hobi-elektronika.net

Project name: Bandera(EAX00)

D D

PCB Serial Number: LA-2581

C C

Intel Dothan ULV1.1G/1.2G (Celeron-M ULV1.1G/1.2G) +Alviso GMS+ICH6-M

B B

2005-06-17

REV: X5.0

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Cover Sheet

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

148Friday, June 17, 2005

X5.0

5

4

http://hobi-elektronika.net

Block Diagram

3

2

1

DC-DC

D D

page 32,33,34,35,36,37

Power
Sequence

page 40

Dothan-ULV/Celeron-M ULV

Processor Thermal
sensor ADM1032

page 5

Panel Thermal sensor
TC74A1-5.0VCT

page 14

uFCBGA CPU

VCCP&CPU_CORE

page 38,39

Clock Generator

IDT CV140

page 13

C C

Docking Conn

B B

10/100M LAN

ALS

page 31

SD Controller

RTL8101L

page 23

Magnetic

page 24

& RJ45

P.I.R List

EE: page41, 42,43,44,45
Power: page 46

AU 8.4" SVGA
TFT LCD
Module

CRT CONN

page 21

SD Socket

page 14

page 15

3.3V 33MHz

MINI PCI

LVDS

PCI Express x2

PCI BUS

page 22

SMSC
LPC47N217

HA#(3..31)

System Bus

400MHz

Intel Alviso GMS

FC-BGA840

DMI X2

ICH6-M

609 BGA

page 16,17,18,19

LPC BUS

page 30

Embedded Controller

page 8,9,10,11

1.5V
100MHz

3.3V 33MHz

page 5,6,7

HD#(0..63)

Memory BUS (DDR2)

Channel A

USB 2.0

AC-LINK

ATA100

1.8V 400MHz

IDE Bus

page 27

TPM
SLD9630TT

DDR2 Thermal
sensor ADM1032

48MHz / 480Mb

3.3V 24.576MHz

HDD 1.8"

page 5

SO-DIMM X 1

BANK 0

page 20

page 12

ENE KB910L

page 28

A A

XBUS

Ambient Light
Sensor

ROM DAUGHTER/BOARD

MXLV008BTC

page 29

Digitizer FIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

HDD Thermal sensor
conn TC74A1-5.0VCT

page 20

USBPORT0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7

JUSBP0
JUSBP1
FPR
BT
DOCK

Not connect

DOCK
DOCK

page 27

page 27

page 29

page 22

page 31

page 31

page 31

AC97 CODEC

STAC9758

page 25

AMP & Phone

MIC

page 26

Compal Electronics, Inc.(KunShan)

Title

Block diagram

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

X5.0

of

248Friday, June 17, 2005

5

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D D

+3VS

External PCI Devices

DEVICE

IDSEL #

REQ/GNT # PIRQ

State

Signal

+12VALW
+5VALW
+3VALW
+1.5VALW

+3V

+1.5VS

+2.5VS+1.8V

+CPU_CORE

+5VS

+0.9VS

+VCCP

F,B3RTL8101L AD17

W83L528D AD20 2 A

AD18

ICH6M SM Bus Address

C C

DEVICE

Clock Generator
DDR2 DIMM0 1010 001Xb

Address

1101 001Xb

1Mini-PCI

G,H

S3

S5 S4/AC

S5 S4/AC don't exist

ON

ON

OFF

ONFULL ON

ON

OFF

ON

OFF

OFFOFFON

OFF

Power Management table

Voltage Rails

PORT FUNCTION

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

MB port

MB port

FPR

BT

Docking

reserved

Docking

Docking

USB PORT TABLE

DOCK NEW CARD TBDXb

Power Plane

EC SM Bus1 Address

DEVICE

Smart Battery 1 0001 011Xb
ALS TSL2550T
CPU ADM1032
HDD TC74A1-5.0VCT 1001 0010b

Address

0111 0010b
1001 100Xb

EC SM Bus 2 Address

B B

DEVICE Address

DDR2 ADM1032 1001 100Xb
Panel TC74A1-5.0VCT 1001 0010b

VIN
B+
+CPU_CORE
+VCCP
+0.9VS
+1.5VALW
+1.5VS
+1.8V
+2.5VS
+3VALW
+3VS 3.3V switched power rail
+5VALW
+5VS
+12VALW
RTCVCC

Description

Adapter power supply (19V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH core power

0.9V switched power rail for DDRII Vtt

1.5V always on power rail

1.5V switched power rail for PCI-E interface

1.8V power rail for DDRII

2.5V switched power rail for MCH video PLL

3.3V always on power rail

5V always on power rail
5V switched power rail
12V always on power rail

S0

N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ONRTC power

S5

S3

N/A

N/A
N/A

N/A

OFF

OFF
OFFOFF

OFF

OFF

ON

ON*
OFF

OFF
ON

OFF

OFF

OFF

ON ON*

OFF

OFF
ON

ON*

OFF

OFF
ON ON*
ON

ON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Notes

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

348Friday, June 17, 2005

X5.0

5

4

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http://hobi-elektronika.net

D D

B+

ADAPTOR

VS

DOCK

DOCK_IN

BATTERY

51_ON#

FAN5234

C C

+1.5VALW

SUSP

+1.5VS

+2.5VS

ACIN

MAINPWRON

G965

+3VALW

SYSON#

SUSP

MAX1902/
SC1404

+5VALW +12VALW

+3V

SUSP#

+3VS +5VS

SYSON

SUSP#

SUSP

MAX8743EEI

1.8V +VCCP

APL5331

0.9VS

SUSP#

FSTCHG

MAX1908

B B

CHARGER

IREF

VSB

BATT+

G920AT24U

VIN

Bridge Battery

RTC BATT

PM_DPRSLPVR

H_DPSLP#

VR_ON

SYSPOK

VRMPWRGD

CLKEN#

MAX1907

VID0

VID1

VID2

VID3

VID4

RTC_VCC

A A

Power Source

Charge Source

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+VCC_CORE

Compal Electronics, Inc.(KunShan)

Title

Power rail

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

448Friday, June 17, 2005

X5.0

5

4

3

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1

H_A#[3..31]<8>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10

D D

H_REQ#[0..4]<8>

R10 0_0402_5%

CK_ITP_R#

1 2

CK_ITP_R

1 2

R11 0_0402_5%

+VCCP

+VCCP

CK_ITP<13>
CK_ITP#<13>

CLK_CPU_BCLK<13>
CLK_CPU_BCLK#<13>

R14

1 2

56_0402_5%

H_RS#[0..2]<8>

R16

1 2

200_0402_1%

C C

B B

A A

H_ADSTB0#<8>
H_ADSTB1#<8>

CK_ITP CPU_CK_ITP
CK_ITP# CPU_CK_ITP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#<8>
H_BNR#<8>
H_BPRI#<8>
H_BR0#<8>
H_DEFER#<8>
H_DRDY#<8>
H_HIT#<8>
H_HITM#<8>

H_LOCK#<8>
H_RESET#<8>

H_TRDY#<8>

ITP_DBRESET#<18>

H_DBSY#<8>
H_DPSLP#<17,39>
H_DPRSTP#<17>

H_DPWR#<8>

H_PWRGOOD<17>
H_CPUSLP#<8,17>

R171K_0402_5%@

12

TEST2 TEST2

R181K_0402_5%@

12

H_THERMTRIP#<8,17>

5

H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB0#
H_ADSTB1#

R12 0_0402_5%

1 2
1 2

R13 0_0402_5%

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5

H_PROCHOT#

H_PWRGOOD

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1TEST1

ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

H_THERMTRIP#

+VCCP

R22

56_0402_5%

12

U1A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

Dothan ULV

C0 Stepping

12

R21
56_0402_5%

GATEON

H_PROCHOT#

Dothan

ADDR GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

+3VS

12

R20
1K_0402_5%

1

C

Q2

2

B

E

2SC2411K_SC59

3

DATA GROUP

LEGACY CPU

Change to 1.2G P/N

PROCHOT#

4

PROCHOT# <28>

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

STPCLK#

http://hobi-elektronika.net

H_D#0

A19

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

H_D#1

A25

H_D#2

A22

H_D#3

B21

H_D#4

A24

H_D#5

B26

H_D#6

A21

H_D#7

B20

H_D#8

C20

H_D#9

B24

H_D#10

D24

H_D#11

E24

H_D#12

C26

H_D#13

B23

H_D#14

E23

H_D#15

C25

H_D#16

H23

H_D#17

G25

H_D#18

L23

H_D#19

M26

H_D#20

H24

H_D#21

F25

H_D#22

G24

H_D#23

J23

H_D#24

M23

H_D#25

J25

H_D#26

L26

H_D#27

N24

H_D#28

M25

H_D#29

H26

H_D#30

N25

H_D#31

K25

H_D#32

Y26

H_D#33

AA24

H_D#34

T25

H_D#35

U23

H_D#36

V23

H_D#37

R24

H_D#38

R26

H_D#39

R23

H_D#40

AA23

H_D#41

U26

H_D#42

V24

H_D#43

U25

H_D#44

V26

H_D#45

Y23

H_D#46

AA26

H_D#47

Y25

H_D#48

AB25

H_D#49

AC23

H_D#50

AB24

H_D#51

AC20

H_D#52

AC22

H_D#53

AC25

H_D#54

AD23

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AF20

H_D#59

AE21

H_D#60

AD21

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

D25

H_DINV#1

J26

H_DINV#2

T24

H_DINV#3

AD20

H_DSTBN#0

C23

H_DSTBN#1

K24

H_DSTBN#2

W25

H_DSTBN#3

AE24

H_DSTBP#0

C22

H_DSTBP#1

L24

H_DSTBP#2

W24

H_DSTBP#3

AE25

H_A20M#

C2

H_FERR#

D3

H_IGNNE#

A3

H_INIT#

B5

H_INTR

D1

H_NMI

D4

H_STPCLK#

C6

H_SMI#

B4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_A20M# <17>
H_FERR# <17>
H_IGNNE# <17>
H_INIT# <17>
H_INTR <17>
H_NMI <17>

H_STPCLK# <17>
H_SMI# <17>

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_D#[0..63] <8>

ITP700FLEX FOR Dothan

ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO_R
ITP_TRST#

RESETITP#
ITP_TCK
CK_ITP_R#

CK_ITP_R

JP1

1

TDI

2

TMS

5

TCK

7

TDO

3

TRST#

12

RESET#
FBO
BCLK#

BCLK
GND0

GND1
GND2
GND3
GND4
GND5

ITP700-FLEXCON@

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

11

8
9

10
14
16
18
20
22

+VCCP

27

VTT0

28

VTT1

26

VTAP

ITP_DBR_RST# ITP_DBRESET#

25

DBR#

24

DBA#

23
21
19
17
15
13

4

NC1

6

NC2

Processor Thermal Sensor ADM1032AR

2200P_0402_50V7K

SMB_EC_CK1<20,28,29,33>

SMB_EC_DA1<20,28,29,33>

H_DSTBN#[0..3] <8>

H_DSTBP#[0..3] <8>

3

DDR2 Thermal Sensor ADM1032AR

Q1

2

3 1

MMBT3904_SOT23

SMB_EC_CK2<14,28>

SMB_EC_DA2<14,28>

Layout notice: place the
C5 close to the U3 pin2,3

C1

1 2

0.1U_0402_16V4Z

1 2

1

C3

2

1

C5
2200P_0402_50V7K

2

R3 200_0402_1%

H_THERMDA

H_THERMDC
SMB_EC_CK1
SMB_EC_DA1

DDR_THERMDA

DDR_THERMDC
SMB_EC_CK2
SMB_EC_DA2

2

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

Layout notice: place the
C3 close to the U2 pin2,3

+VCCP +VCCP

R1

54.9_0402_1%

1 2

+VCCP

1 2

R6 39.2_0603_1%

1 2

R8 150_0402_5%

+3VS

1

C2

0.1U_0402_16V4Z

2

U2

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARM_RM8

SM BUS1 Address : 1001 100Xb

U3

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARM_RM8

SM BUS2 Address : 1001 100Xb

VDD1

ALERT#

THERM#

GND

+3VS

1

C4

0.1U_0402_16V4Z

2

VDD1

ALERT#

THERM#

GND

1
6
4
5

1
6
4
5

R2

54.9_0402_1%

RESETITP# ITP_TDO_R

12

R4

22.6_0402_1%

ITP_TMS

ITP_TDI

12

R15

@

10K_0402_5%

THERM#

ALERT# PM_EXTTS0#
DDR_THERM#

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

R19 0_0402_5%

1 2
1 2

R333 0_0402_5%

Dothan host interface

Bandera-EAX00-LA2581

1 2

ITP_TDOH_RESET#

1 2

R7 680_0402_5%

1 2

R9 27.4_0402_1%

R5

22.6_0402_1%

1

12

ITP_TRST#
ITP_TCK

PM_EXTTS0# <8>

548Friday, June 17, 2005

of

X5.0

5

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DFT

AC26

AD26

AE7
AF6

F26

P23

W4

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16

L21

M6

M22
N21

P22

R21

T22

U21

D18
D20
D22

E17
E19
E21

F18

C16
C14

P25

P26
AB2
AB1

E26
AF7
AC1

B1
N1

K6
L5

N5
P6
R5
T6

D6
D8

E5
E7
E9

F6
F8

E1
E2

F2
F3
G3
G4
H4

C3

U1B

VCCSENSE
VSSSENSE

VCCA0
VCCA1
VCCA2
VCCA3

VCCQ0
VCCQ1

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

PSI#
VID0

VID1
VID2
VID3
VID4
VID5

GTLREF

BSEL0
BSEL1

COMP0
COMP1
COMP2
COMP3

RSVD
RSVD
RSVD
RSVD

Dothan ULV

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Dothan

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

R23

@

54.9_0402_1%

D D

VL

MAX6509SET

12

R26

21K_0603_1%

100K_0402_5%

C C

MAX6509OUT#

0.1U_0402_16V4Z

U4

1

SET

2

GND

3

OUT#

MAX6509CHU-K_SOT23-5~L

VL VL

12

R361

2

G

2

C251

1

5

VCC

4

HYST

R363
47K_0402_5%

1 2

MAX6509OUT

13

D

Q4

2N7002_SOT23

S

MAX6509HYST

2

C180

0.1U_0402_16V4Z

1

2

G

12

R25
10K_0402_5%

12

R27
10K_0402_5%

13

D

Q3
2N7002_SOT23

S

T=273.15+C

@

HYST=VCC: Hysteresis is 10 degree
HYST=GND: Hysteresis is 2 degree

MAINPWRON <17,35,36>

+1.5VS

0.01U_0402_16V7K

C6

1

2

54.9_0402_1%

C89
10U_0805_6.3V6M

+VCC_CORE

1 2
1 2

R24

@

+VCCP

VCCSENSE
VSSSENSE

R26: Rset(kohm)=(83793/T)-211.3569+(129890/T^2) T--Kelvin

Check with thermal(88C)

12

PSI
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5

+CPU_GTLREF

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

+VCCP

12

R30
1K_0402_1%

B B

A A

12

R31
2K_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

1

C8
1U_0603_10V4Z

2

1

C9
220P_0402_50V7K

2

R32

27.4_0402_1%

12

12

R33

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

CPU_VID0<39>
CPU_VID1<39>
CPU_VID2<39>
CPU_VID3<39>
CPU_VID4<39>
CPU_VID5<39>

CPU_BSEL0<13>
CPU_BSEL1<13>

12

R34

27.4_0402_1%

TP1
PAD

R35

54.9_0402_1%

+VCC_CORE

AA11
AA13
AA15
AA17
AA19
AA21

AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC11
AC13
AC15
AC17
AC19

AD10
AD12
AD14
AD16
AD18

AE11
AE13
AE15
AE17
AE19

AF10
AF12
AF14
AF16
AF18

G21
H22

W21

AA5
AA7
AA9

AB6
AB8

AC9

AD8

AE9

AF8

M21
M24

N22
N23
N26

R22
R25

F20
F22

G5
H6

J5
J21
K22

U5

V6

V22

W5

Y6

Y22

M4
M5

N3
N6

P2

P5
P21
P24

R1
R4
R6

T3

T5
T21
T23

U1C

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Dothan ULV

Dothan

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Dothan power and ground

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

648Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

Intel:Mid-Frequency Decoupling (0805 MLCC>= X5R) 5m ohm (typ) /25, 0.6 nH / 25.

+VCC_CORE

D D

+VCC_CORE

+VCC_CORE

+VCC_CORE

C C

+VCC_CORE

Capacitor Height: 1.25MM+-0.2

C10
10U_0805_6.3V6M

C20
10U_0805_6.3V6M

C25
10U_0805_6.3V6M

C30
10U_0805_6.3V6M

C15
10U_0805_6.3V6M

C11
10U_0805_6.3V6M

C21
10U_0805_6.3V6M

C26
10U_0805_6.3V6M

C31
10U_0805_6.3V6M

C16
10U_0805_6.3V6M

C12
10U_0805_6.3V6M

C22
10U_0805_6.3V6M

C27
10U_0805_6.3V6M

C32
10U_0805_6.3V6M

C17
10U_0805_6.3V6M

C13
10U_0805_6.3V6M

C23
10U_0805_6.3V6M

C28
10U_0805_6.3V6M

C33
10U_0805_6.3V6M

C18
10U_0805_6.3V6M

C14
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

C29
10U_0805_6.3V6M

C34
10U_0805_6.3V6M

C19
10U_0805_6.3V6M

H1
HOLE

H7
HOLE

H11
HOLE

H16
HOLE

H18
HOLE

1

1

1

1

1

M1
HOLE

1

H3

H2

HOLE

HOLE

1

1

H8

H9

HOLE

HOLE

1

1

H12

H13

HOLE

HOLE

1

1

H17
HOLE

1

HDD conn hole

M2
HOLE

1

H4
HOLE

H10
HOLE

H14
HOLE

1

1

1

H5

H6

HOLE

HOLE

Frame hole

1

1

CPU thermal hole

H15

H11, H12 HDD upper hole

HOLE

H13 HDD conn hole
H14, H15 DOCK conn hole

1

H17 BIOS/B hole

M3
HOLE

1

M4
HOLE

1

M5
HOLE

FD2

FD1

1

1

FD3

1

1

1

1

1

1

1

1

1

FD4

1

FD5

FD6

1

FD7

FD8

1

CF1

CF2

1

CF3

CF4

1

CF6

CF5

1

CF8

CF7

1

CF10

CF9

1

Intel: Low-Frequency Decoupling : 9 m ohm (max)/3, 1.8 nH / 3

+VCC_CORE

B B

C35

@

330U_D2E_2.5VM_R9

9mOhm
7343
PS CAP

1

+

2

1

+

C36

C37

2

330U_D2E_2.5VM_R9

9mOhm

9mOhm

7343

7343

PS CAP

PS CAP

1

Near VCORE regulator.

+

2

330U_D2E_2.5VM_R9

Intel: High Frequency Decoupling (0603 MLCC, >= X7R) 16 m ohm (typ) / 10, 0.6 nH / 10

+VCCP

1

+

C38
150U_D2_4VM

2

A A

5

1

C39

0.1U_0402_16V4Z

2

1

C40

0.1U_0402_16V4Z

2

4

1

C41

0.1U_0402_16V4Z

2

1

C42

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C43

0.1U_0402_16V4Z

2

1

2

3

C44

0.1U_0402_16V4Z

1

C45

0.1U_0402_16V4Z

2

1

C46

0.1U_0402_16V4Z

2

1

C47

0.1U_0402_16V4Z

2

2

1

C48

0.1U_0402_16V4Z

2

Compal Electronics, Inc.(KunShan)

Title

Dothan decoupling cap

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

748Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

D15
E17
F15
G17
H17

H19
F29
E27
W2

J26
J27
J18
W27
W25

A22
A21
J31
H31

CFG[2:0]

CFG5

CFG6

CFG0
MCH_CLKSEL1
MCH_CLKSEL0
CFG5
CFG6

PM_BMBUSY#
PM_EXTTS0#
H_THERMTRIP#
VRMPWRGD
PLT_RST#

DREFCLK#
DREFCLK
DREF_SSCLK
DREF_SSCLK#

H_A#[3..31]<5>

D D

H_REQ#[0..4]<5>

C C

H_ADSTB0#<5>
H_ADSTB1#<5>

CLK_MCH_BCLK#<13>
CLK_MCH_BCLK<13>

H_DSTBN#[0..3]<5>

H_DSTBP#[0..3]<5>

H_DINV#0<5>
H_DINV#1<5>
H_DINV#2<5>
H_DINV#3<5>

H_RESET#<5>
H_ADS#<5>

H_TRDY#<5>
H_DPWR#<5>
H_DRDY#<5>
H_DEFER#<5>

H_HITM#<5>

B B

H_HIT#<5>
H_LOCK#<5>
H_BR0#<5>
H_BNR#<5>
H_BPRI#<5>
H_DBSY#<5>

H_RS#[0..2]<5>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB0#
H_ADSTB1#

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#

H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#

H_HITM#
H_HIT# H_VREF
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_R_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

U5A

C6

HA3#

G11

HA4#

E12

HA5#

B8

HA6#

C11

HA7#

B11

HA8#

C9

HA9#

A11

HA10#

D12

HA11#

F13

HA12#

E11

HA13#

A13

HA14#

C12

HA15#

G12

HA16#

G14

HA17#

J14

HA18#

G13

HA19#

H14

HA20#

B13

HA21#

A14

HA22#

C13

HA23#

J15

HA24#

H12

HA25#

E13

HA26#

C14

HA27#

F14

HA28#

E14

HA29#

D13

HA30#

B14

HA31#

A8

HREQ0#

B7

HREQ1#

A9

HREQ2#

A7

HREQ3#

J12

HREQ4#

F11

HADSTB0#

H15

HADSTB1#

AA3

HCLKN

Y3

HCLKP

G5

HDSTBN0#

K8

HDSTBN1#

U1

HDSTBN2#

AA4

HDSTBN3#

G4

HDSTBP0#

L9

HDSTBP1#

U2

HDSTBP2#

AA5

HDSTBP3#

J6

HDINV0#

L7

HDINV1#

R7

HDINV2#

W5

HDINV3#

F7

HCPURST#

G9

HADS#

E9

HTRDY#

G1

HDPWR#

A4

HDRDY#

E5

HDEFER#

C3

HHITM#

B2

HHIT#

C4

HLOCK#

F9

HBREQ0#

E8

HBNR#

B3

HBPRI#

F8

HDBSY#

C5

HCPUSLP#

A5

HRS0#

B5

HRS1#

C7

HRS2#

ALVISO_BGA840

Alviso

HOST

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

H_D#0

F5

H_D#1

F2

H_D#2

E2

H_D#3

J5

H_D#4

F3

H_D#5

G3

H_D#6

F4

H_D#7

E3

H_D#8

J9

H_D#9

F6

H_D#10

J7

H_D#11

J8

H_D#12

J1

H_D#13

F1

H_D#14

K9

H_D#15

G7

H_D#16

K3

H_D#17

K4

H_D#18

P1

H_D#19

R2

H_D#20

K5

H_D#21

J3

H_D#22

J2

H_D#23

L5

H_D#24

U8

H_D#25

K7

H_D#26

U9

H_D#27

V9

H_D#28

R1

H_D#29

K6

H_D#30

U3

H_D#31

R9

H_D#32

V3

H_D#33

V4

H_D#34

R6

H_D#35

P5

H_D#36

P3

H_D#37

R8

H_D#38

P7

H_D#39

P9

H_D#40

W3

H_D#41

R4

H_D#42

R3

H_D#43

R5

H_D#44

U6

H_D#45

U5

H_D#46

V5

H_D#47

V6

H_D#48

W7

H_D#49

W8

H_D#50

W1

H_D#51

V2

H_D#52

W4

H_D#53

Y2

H_D#54

Y5

H_D#55

AA9

H_D#56

AA8

H_D#57

AA1

H_D#58

V7

H_D#59

AA6

H_D#60

Y6

H_D#61

Y8

H_D#62

W9

H_D#63

Y7
J11

H_XRCOMP

K1

H_XSCOMP

E6

H_YRCOMP

L1

H_YSCOMP

K2

H_SWNG0

J13

H_SWNG1

L3

Change to C0 version

R56

H_CPUSLP#<5,17>

A A

Reserved this Resistor for CPU sleep drive by Alviso or ICH6, This resistor can be
delete after intel ensure don't change this Enhance C3 function

H_CPUSLP# H_R_CPUSLP#

0_0402_5%

1 2

H_D#[0..63] <5> DMI_TXN0<18>

+VCCP

12

R36

1

R37

2

C49

0.1U_0402_16V4Z

+VCCP

R41

1

R43

2

0.1U_0402_16V4Z

12

12

R49

54.9_0402_1%

221_0603_1%

12

100_0402_1%

12

221_0603_1%

12

100_0402_1%

1

C53

2

220P_0402_50V7K

+VCCP

12

R50

100_0402_1%

12

R51

200_0402_1%

Layout Note:
Route as short
as possible

12

@

@

R44

40.2_0402_1%

12

R45

40.2_0402_1%

12

R52

24.9_0402_1%

H_SWNG1

H_SWNG0

C50

+VCCP

R48

54.9_0402_1%

12

R53

24.9_0402_1%

DMI_TXN1<18>

DMI_TXP0<18>
DMI_TXP1<18>

DMI_RXN0<18>
DMI_RXN1<18>

DMI_RXP0<18>
DMI_RXP1<18>

DDR2_CLK0<12>
DDR2_CLK1<12>

DDR2_CLK0#<12>
DDR2_CLK1#<12>

DDR2_CKE0<12>
DDR2_CKE1<12>

DDR2_CS0#<12>
DDR2_CS1#<12>

DDR2_ODT0<12>

1 2
1 2

1

C51

2

0.1U_0402_16V4Z

DDR2_VREF<12>

DDR2_ODT1<12>

C52

0.1U_0402_16V4Z

+1.8V

R46 80.6_0402_1%
R47 80.6_0402_1%

1

2

DMI_TXN0
DMI_TXN1

DMI_TXP0
DMI_TXP1

DMI_RXN0
DMI_RXN1

DMI_RXP0
DMI_RXP1

DDR2_CLK0
DDR2_CLK1

DDR2_CLK0#
DDR2_CLK1#

DDR2_CKE0
DDR2_CKE1

DDR2_CS0#
DDR2_CS1#

M_OCDOCMP0
M_OCDOCMP1
DDR2_ODT0
DDR2_ODT1

SMRCOMPN
SMRCOMPP
DDR2_VREF

SMXSLEWIN_OUT
SMYSLEWIN_OUT

10/20 Mil
width/space ,
Length1.5''

+1.8V

12

DDR2_VREF

12

W29

W31

AE31

AJ29

AH5

AF31

AJ28

AC23
AC25
AH21

AJ21

AD11
AG13

AL14

AH12
AB27
AF12

AG12
AK13

AJ12

AD7

AA25
AC10
AD10

R54
1K_0402_1%

R55
1K_0402_1%

U5B

V24

DMI_RXN0
DMI_RXN1

U24

DMI_RXP0

V29

DMI_RXP1

V26

DMI_TXN0
DMI_TXN1

U26

DMI_TXP0

V31

DMI_TXP1

DMIDDR MUXING

SM_CK0

AF5

SM_CK1
SM_CK3

SM_CK4

SM_CK0#

AE5

SM_CK1#
SM_CK3#

AJ5

SM_CK4#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SMOCDCOMP0

AE9

SMOCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN

AE7

SMRCOMPP

Y30

SMVREF0

AE1

SMVREF1

Y24

SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

ALVISO_BGA840

Close Alviso

CFG0
CFG1
CFG2
CFG5
CFG6

RSVD23
RSVD24
RSVD25

RSVD1

CFG/RSVD

BM_BUSY#

EXT_TS0#

THRMTRIP#

PWROK

PM

RSTIN#

DREF_CLKN

CLK

DREF_CLKP
DREF_SSCLKP
DREF_SSCLKN

101(400MHz FSB)
Low = DMI x 2

High = DMI x 4
Low = DDR-II
High = DDR-I

MCH_CLKSEL1 <13>
MCH_CLKSEL0 <13>

CFG0

CFG5
CFG6

EC_EXTTS0#<28>

PM_EXTTS0#<5>

PM_BMBUSY# <18>
H_THERMTRIP# <5,17>

VRMPWRGD <13,18,28>
PLT_RST# <16,20,27,28,30>

DREFCLK# <13>
DREFCLK <13>
DREF_SSCLK <13>
DREF_SSCLK# <13>

12

R38 10K_0402_5%

1 2

R39 2.2K_0402_5%

1 2

R40 2.2K_0402_5%

1 2

*

*

R58

@

0_0402_5%

R42

10K_0402_5%

+VCCP

+2.5VS

12

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Alviso GMS host/DMI/DDR/PM/CLK

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

848Friday, June 17, 2005

X5.0

5

4

http://hobi-elektronika.net

Intel demand in

3

2

1

Soloma Platform
design guide P428

AB18

M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22

R10
R11
R12
R13
R14
R18
R19
R20
R21
R22

U10
U11
U12
U13
U14
U18
U19
U20
U21
U22

W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22

P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22

T11
T12
T13
T14
T18
T19
T20
T21

V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22

Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19

U5F

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

ALVISO_BGA840

A10

NC

A2

NC

A29

NC

A3

NC

A30

NC

A31

NC

AA10

NC

AA11

NC

AA12

NC

AA13

NC

AA14

NC

AA15

NC

AA16

NC

AA17

NC

AA18

NC

AA19

NC

AA20

NC

AA21

NC

AA22

NC

AB1

NC

AB10

NC

AB11

NC

AB12

NC

AB13

NC

AB14

NC

AB15

NC

AB17

NC

AB19

NC

AB2

NC

AB20

NC

AB21

NC

AB22

NC

AB3

NC

AB5

NC

AB6

NC

AB7

NC

AB9

NC

AC22

NC

AE22

NC

AF22

NC

AG22

NC

AJ1

NC

AJ22

NC

AJ31

NC

AK1

NC

AK22

NC

AK31

NC

AL1

NC

AL2

NC

AL22

NC

AL29

NC

AL3

NC

AL30

NC

AL31

NC

B1

NC

B10

NC

B31

NC

C1

NC

C10

NC

C31

NC

E10

NC

F10

NC

G10

NC

J10

NC

K10

NC

K11

NC

K12

NC

K13

NC

K14

NC

K15

NC

K17

NC

K18

NC

K19

NC

K20

NC

K21

NC

K22

NC

K23

NC

K25

NC

K26

NC

K27

NC

K29

NC

K30

NC

K31

NC

L10

NC

L11

NC

L12

NC

L13

NC

L14

NC

L15

NC

L16

NC

L17

NC

L18

NC

L19

NC

L20

NC

L21

NC

L22

NC

M10

NC

M11

NC

M12

NC

Y20

NC

Y21

NC

Y22

NC

AA23
AA26
AA27

AB28
AB30
AC24
AC28

AC9
AD12
AD15
AD19

AD2
AD21

AD5

AD9
AE10
AE11
AE13
AE26
AE30
AF11
AF15
AF19
AF23
AF28
AF30

AF7

AG2
AG21
AG25

AG3
AH10
AH13
AH15
AH19

AH6

AJ27

AK12
AK15
AK19
AK21
AK23
AK26
AK29

AK5

AK9

C15

C17

C19

C25

C30

D11

D14

U23

U25

U27

U5G

A15

VSS

A18

VSS

A20

VSS

A25

VSS

A27

VSS

AA2

VSS
VSS
VSS
VSS

AA7

VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B12

VSS

B15

VSS

B22

VSS

B27

VSS

B4

VSS

B6

VSS

B9

VSS
VSS
VSS
VSS

C2

VSS
VSS
VSS

C8

VSS
VSS
VSS
VSS
VSS
VSS

V28

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSW6VSS

VSS

VSS

VSS

VSS

VSSY4VSSY9VSS

U4

Y23

Y25

Y26

Y29

W30

Y31

U31

U29

W24

W26

W28

VSSALVDS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

ALVISO_BGA840

V27

B30
D18

D19
D25
E15
E21
E23
E26
E29
E30
E4
E7
F12
F17
F23
F27
G15
G2
G21
G22
G25
G29
G31
G6
G8
H11
H13
H18
H20
H23
H26
H30
J17
J20
J22
J4
L2
L25
L27
L29
L4
L6
L8
M23
M25
M27
M29
N25
N27
N29
N31
P2
P23
P25
P27
P29
P4
P6
P8
R16
R24
R25
R26
R27
R29
U15
U17
U7
V1
V25
V30
V8

+2.5VS

D D

DDR2_ABA0<12>
DDR2_ABA1<12>
DDR2_ABA2<12>
DDR2_DM[0..7]<12>

DDR2_DQS[0..7]<12>

C C

B B

A A

DDR2_DQS#[0..7]<12>

DDR2_AA[0..13]<12>

DDR2_ACAS#<12>
DDR2_ARAS#<12>

DDR2_AWE#<12>

Use for emulating source
synchronous clocking for
reads. these signal are routed
internally on the GMCH
package and can be NC.

DDR2_ABA0
DDR2_ABA1
DDR2_ABA2

DDR2_DM0
DDR2_DM1
DDR2_DM2
DDR2_DM3
DDR2_DM4
DDR2_DM5
DDR2_DM6
DDR2_DM7

DDR2_DQS0
DDR2_DQS1
DDR2_DQS2
DDR2_DQS3
DDR2_DQS4
DDR2_DQS5
DDR2_DQS6
DDR2_DQS7

DDR2_DQS#0
DDR2_DQS#1
DDR2_DQS#2
DDR2_DQS#3
DDR2_DQS#4
DDR2_DQS#5
DDR2_DQS#6
DDR2_DQS#7

DDR2_AA0
DDR2_AA1
DDR2_AA2
DDR2_AA3
DDR2_AA4
DDR2_AA5
DDR2_AA6
DDR2_AA7
DDR2_AA8
DDR2_AA9
DDR2_AA10
DDR2_AA11
DDR2_AA12
DDR2_AA13

DDR2_ACAS#
DDR2_ARAS#

DDR2_AWE#

AE15
AD13
AB25

AA31

AJ30
AF24
AK24

AJ10

AG7
AD6

AB29

AL28
AF25

AJ23
AK10

AG9
AH3
AE2

AA30
AK28
AF26

AJ24

AL10

AG5

AC21
AC20
AC19
AD20
AE19
AE20
AF20
AF21
AE21
AA24
AC11
AB23
AB24
AF13

AE12
AG15
AC27
AB26

AJ15

AJ14
AG14

AL21
AC12

AE14
AC15
AD14
AG19

AJ19

AJ20
AK20

AL19
AH20
AF14

AL20
AG20

AL13

AJ13
AH14
AK14

AL5

AF9
AF2

U5C

SA_BS0
SA_BS1
SA_BS2

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

SB_BS0
SB_BS1
SB_BS2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_WE#

ALVISO_BGA840

DDR2_

ADDR_A

SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR2_DATA

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

DDR2_ADDR_B DDR2_ADDR_A DDR2_DQS

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9

Y27
Y28
AC29
AE29
AA28
AA29
AB31
AC30
AG29
AG28
AJ26
AL26
AG30
AG31
AL27
AK27
AF29
AE28
AE25
AE24
AE27
AF27
AE23
AC26
AL25
AJ25
AG27
AG26
AK25
AL24
AG23
AG24
AK11
AL11
AJ7
AL9
AL12
AJ11
AH9
AJ9
AG10
AF10
AH7
AF6
AH11
AG11
AG6
AE6
AL7
AK7
AK2
AJ2
AK6
AJ6
AK3
AH2
AH1
AG1
AC6
AC7
AF3
AE3
AD3
AC2

DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ29
DDR2_DQ30
DDR2_DQ31
DDR2_DQ32
DDR2_DQ33
DDR2_DQ34
DDR2_DQ35
DDR2_DQ36
DDR2_DQ37
DDR2_DQ38
DDR2_DQ39
DDR2_DQ40
DDR2_DQ41
DDR2_DQ42
DDR2_DQ43
DDR2_DQ44
DDR2_DQ45
DDR2_DQ46
DDR2_DQ47
DDR2_DQ48
DDR2_DQ49
DDR2_DQ50
DDR2_DQ51
DDR2_DQ52
DDR2_DQ53
DDR2_DQ54
DDR2_DQ55
DDR2_DQ56
DDR2_DQ57
DDR2_DQ58
DDR2_DQ59
DDR2_DQ60
DDR2_DQ61
DDR2_DQ62
DDR2_DQ63

DDR2_DQ[0..63] <12>

12

R57
10K_0402_5%

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Alviso GMS DDR2/VSS

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

948Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

D D

SDVOCTRL_DATA:0=No SDVO device-have put down internal
present(default) 1=SDVO device present

U5E

H27

SDVOCTRL_DATA

G27

CLK_MCH_3GPLL#<13>
CLK_MCH_3GPLL<13>

CLK_MCH_3GPLL#
CLK_MCH_3GPLL

TV_REFSET, Intel DG
page 200 indicate
directly to GND

W23

V23

A17
C18
A19

J19
B17
B18
B19

SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

MISCTVVGALVDS

EXP_COMPI

EXP_ICOMPO

SDVO_TVCLKIN#

SDVO_INT#

SDVO_FLDSTALL#

P26
L26

M28
P28
U28

PCI Express in/out put current compensation

+1.5VS_PCIE

R59

24.9_0402_1%

EXP_COMPIO

1 2

R1152
R1153

150_0402_1%
150_0402_1%
150_0402_1%

TXA0-<14>
TXA1-<14>
TXA2-<14>

TXA0+<14>
TXA1+<14>
TXA2+<14>

3VDDCCL
3VDDCDA

12

R61

12

R332

12

CRT_VSYNC_R

R63

CRT_HSYNC_R

R64 255_0402_1%

MP BOM change

LBKLT_CRTL
ENABLT

ENVDD
LIBG

TXACLK­TXACLK+

TXA0­TXA1­TXA2-

TXA0+
TXA1+
TXA2+

CRT_B
CRT_G
CRT_R

3VDDCCL<15>
3VDDCDA<15>

CRT_B<15>

C C

CRT_VSYNC<15>
CRT_HSYNC<15>

CRT_VSYNC
CRT_HSYNC LBKLT_CRTL_PWM

CRT_G<15>
CRT_R<15>

39_0402_5%
39_0402_5%

12
12

Need tune this value

R66 100K_0402_1%

+2.5VS

Pull-up: normal-polarity inverter
Pull-down: inverted polarity inverter

B B

1 2

1 2

R68 1.5K_0402_1%

ENVDD<14>

TXACLK-<14>
TXACLK+<14>

J23

DDCCLK

J25

DDCDATA

D23

BLUE

C23

BLUE#

E22

GREEN

D22

GREEN#

F21

RED

F22

RED#

G23

VSYNC

H22

HSYNC

J21

12

REFSET

G26

LBKLT_CRTL

F26

LBKLT_EN

D26

LCTLA_CLK

C26

LCTLB_DATA

E25

LDDC_CLK

F25

LDDC_DATA

H25

LVDD_EN

F30

LIBG

G30

LVBG

J29

LVREFH

H29

LVREFL

D27

LACLKN

C27

LACLKP

F31

LADATAN0

D31

LADATAN1

D29

LADATAN2

E31

LADATAP0

D30

LADATAP1

C29

LADATAP2

ALVISO_BGA840

SDVO_TVCLKIN

SDVO_FLDSTALL

SDVOB_RED#

SDVOB_GREEN#

SDVOB_BLUE#

SDVOB_BLKN

PCI - EXPRESS GRAPHICS

SDVOB_RED

SDVOB_GREEN

SDVOB_BLUE
SDVOB_BLKP

SDVO_INT

L28
N28
R28

LBKLT_CRTL

M30
N26
P30
U30

L30
M26
N30
R30

+2.5VS +3VS

G

2

Q5

13

D

S

BSS138_SOT23

+2.5VS +3VS

G

2

Q6

13

D

S

BSS138_SOT23

12

R60

2.2K_0402_5%

12

R65

2.2K_0402_5%

ENABKLENABLT

LBKLT_CRTL_PWM <14>

ENABKL <14,28>

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Alviso GMS Display interface

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

10 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

+VCCP

U5D

L23

VCC

1

1

1

C54

C55

D D

C406 0.47U_0402_6.3V4Z

1 2

C C

2

C407 0.47U_0402_6.3V4Z

2

10U_0805_4VAM

10U_0805_4VAM

1 2

47U_1210_10V3M

C56

C57

2

10U_0805_4VAM

C368

1

2

+VCCP

+1.8V

1

2

C58

0.1U_0402_16V4Z

Place closed GMS

C401 0.47U_0402_6.3V4Z

C402 0.47U_0402_6.3V4Z

1 2

C405 0.47U_0402_6.3V4Z

1 2

B B

1 2

C403 0.47U_0402_6.3V4Z

1 2

C404 0.47U_0402_6.3V4Z

1 2

1

1

C59

2

2

C60 0.22U_0603_10V7K

C71

4.7U_0805_10V4Z

C76 0.22U_0603_10V7K

C62

0.1U_0402_16V4Z

1 2

1

1

C72

2

2

2.2U_0805_16V4Z

1 2

C61

10U_0805_6.3V6M

10U_0805_6.3V6M

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL
+1.5VS_MPLL

0.1U_0402_16V4Z

+1.5VS

M24
N23
N24

R15
R17

U16

AD18
AE17
AE18

AF1
AF17
AF18
AH17
AH18

AJ17

AJ18
AK17
AK18
AK30

AL17
AL18
AL23

AG17
AG18
AC17
AC18
AC31
AD17

AC3
AC5

AD1
AC1

L24

P24

T15
T16
T17

A6

A12

E1
M1
M2
M3
M4
M5
M6
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9

Y1

AL6

B21

J30

VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER

VCC
VCC
VCC
VCC

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

ALVISO_BGA840

VCCA_TVDACA
VCCA_TVDACA
VCCA_TVDACB
VCCA_TVDACB
VCCA_TVDACC
VCCA_TVDACC

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS
VCCD_LVDS
VCCD_LVDS

VCCA_LVDS

VCCTX_LVDS
VCCTX_LVDS

VCCA_3GPLL

VCCA_3GBG

VSSA_3GBG

VCCA_CRTDAC
VCCA_CRTDAC
VSSA_CRTDAC

VCCHV
VCCHV
VCCHV

VCCA_SM
VCCA_SM
VCCA_SM

VCC3G
VCC3G

VCC_SYNC

F18
G18
F19
G19
F20
G20

E19
E20

E18
D17

A23
B23
B25

B29
B20

C21
C22

A26
B26

AC13
AC14
AL15

P31
R31

R23

M31
L31

H21
C20

D21
D20

+1.5VS_DDRDLL

1

C74

2

0.1U_0402_16V4Z

+2.5VS_CRT_DAC

C93

0.022U_0402_16V7K

+2.5VS_CRTDAC

C90

1

+

C73

2

100U_D2_6.3VM

L5 BLM18PG600SN1_0603

1 2

1

1

C94

2

2

1

C70

2

10U_0805_6.3V6M

+1.5VS_PCIE

1

C78

2

0.1U_0402_16V4Z

+1.5VS

+2.5VS

1

1

C65

0.1U_0402_16V4Z

1

C79

2

10U_0805_4VAM

1

C95

2

Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

C66

2

2

0.01U_0402_16V7K

+1.5VS_3GPLL

1

C364

2

10U_0805_4VAM

47U_1210_10V3M

+2.5VS_3GBG

+2.5VS_CRTDAC

1

C96

2

10U_0805_4VAM

0.1U_0402_16V4Z

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Alviso.

1

C67

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C81

2

2

0.1U_0402_16V4Z

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

+2.5VS

C63

1

C68

2

10U_0805_4VAM

3GRLL_R

1 2

R73 0.5_0805_1%

C82

10U_0805_4VAM

L4

BLM18PG600SN1_0603

1

C87

0.1U_0402_16V4Z

2

1

1

C64

2

2

12

4.7U_0805_10V4Z

L1

L2

L3

C83

+2.5VS

1

C88

0.1U_0402_16V4Z

2

12

12

12

0.1U_0402_16V4Z

BLM18PG600SN1_0603

BLM18PG600SN1_0603

BLM18PG600SN1_0603

+1.5VS

+1.5VS

C77

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C75

1

2

+1.5VS

1

2

0.1U_0402_16V4Z

+1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_MPLL+1.5VS_HPLL

L6

BLM18PG600SN1_0603

1 2

+1.5VS +1.5VS +1.5VS +1.5VS

1

2

C100

5

1

2

0.1U_0402_16V4Z

C232

22U_1206_16V4Z_V1

A A

L8

BLM18PG600SN1_0603

1 2

1

C233

2

22U_1206_16V4Z_V1

1

C104

2

0.1U_0402_16V4Z

BLM18PG600SN1_0603

1 2

4

L9

C362

L7

BLM18PG600SN1_0603

1 2

1

1

C105

2

2

0.1U_0402_16V4Z

22U_1206_16V4Z_V1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C363

22U_1206_16V4Z_V1

1

2

3

1

C102

2

0.1U_0402_16V4Z

+VCCP

+2.5VS

D1

2 1

RB751V_SOD323

+VCCP_CRTDAC_D

R74

1K_0805_1%

1 2

R75

0_0805_5%

1 2

2

+2.5VS_CRTDAC

Compal Electronics, Inc.(KunShan)

Title

Alviso GMS power interface

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

11 48Friday, June 17, 2005

X5.0

5

2.2U_0805_16V4Z
C110

C109

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C117

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C123

+0.9VS

RP1

18
27
36
45

RP3

18
27
36
45

RP5

18
27
36
45

DDR2_DQS#[0..7]
DDR2_DQ[0..63]
DDR2_DM[0..7]
DDR2_DQS[0..7]
DDR2_AA[0..13]

2.2U_0805_16V4Z
C111

1

2

0.1U_0402_16V4Z

C118

1

2

0.1U_0402_16V4Z

1

1

2

2

C125

C124

RP2

56_0804_8P4R_5%

RP4

56_0804_8P4R_5%

RP6

56_0804_8P4R_5%

RP7

56_0804_8P4R_5%

2.2U_0805_16V4Z
C112

1

2

0.1U_0402_16V4Z

C119

1

2

0.1U_0402_16V4Z

1

2

C126

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

Layout Note:
Place near JP2

0.1U_0402_16V4Z

C353

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C127

DDR2_CKE0DDR2_CKE1
DDR2_ABA2
DDR2_AA12
DDR2_AA9

DDR2_AA5
DDR2_AA3
DDR2_AA1

DDR2_AA10
DDR2_ABA0
DDR2_AWE#
DDR2_ACAS#

DDR2_CS1#
DDR2_ODT1

C310

0.1U_0402_16V4Z

1

2

C128

C129

DDR2_DQS#[0..7]<9>
DDR2_DQ[0..63]<9>
DDR2_DM[0..7]<9>
DDR2_DQS[0..7]<9>
DDR2_AA[0..13]<9>

D D

C C

B B

A A

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C108

1

1

2

2

0.1U_0402_16V4Z

150U_D2_4VM

1

C116

1

+

C115

2

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C120

DDR2_AA11
DDR2_AA7
DDR2_AA6

DDR2_AA0 DDR2_AA8
DDR2_AA4
DDR2_AA2
DDR2_ABA1

DDR2_ARAS#
DDR2_AA13
DDR2_ODT0
DDR2_CS0#

1

1

2

2

C122

C121

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

5

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C130

4

0.1U_0402_16V4Z

1

2

C131

C132

Layout Note:
Place these resistor
closely JP2,all
trace length<750 mil

3

http://hobi-elektronika.net

Top view

DDR2_DQ1
DDR2_DQ5

DDR2_DQS#0
DDR2_DQS0

DDR2_DQ4

12

39 40

41 42

199 200

DDR2_CKE0<8>

DDR2_ABA2<9>

RVS TYPE

DDR2_ABA0<9>
DDR2_AWE#<9>

DDR2_ACAS#<9>

DDR2_CS1#<8>
DDR2_ODT1<8>

ICH_SMBDATA<13,18,31>
ICH_SMBCLK<13,18,31>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR2_DQ7
DDR2_DQ12

DDR2_DQ8
DDR2_DQS#1

DDR2_DQS1
DDR2_DQ10

DDR2_DQ14

DDR2_DQ20
DDR2_DQ21

DDR2_DQS#2
DDR2_DQS2

DDR2_DQ18
DDR2_DQ19

DDR2_DQ26
DDR2_DQ24

DDR2_DM3

DDR2_DQ27
DDR2_DQ31

DDR2_CKE0

DDR2_ABA2
DDR2_AA12

DDR2_AA9
DDR2_AA8

DDR2_AA5
DDR2_AA3
DDR2_AA1

DDR2_AA10
DDR2_ABA0
DDR2_AWE#

DDR2_ACAS#

DDR2_ODT1
DDR2_DQ37

DDR2_DQ32
DDR2_DQS#4

DDR2_DQS4
DDR2_DQ39

DDR2_DQ38
DDR2_DQ41

DDR2_DQ40
DDR2_DM5
DDR2_DQ42

DDR2_DQ46
DDR2_DQ48

DDR2_DQ52

DDR2_DQS#6
DDR2_DQS6

DDR2_DQ50
DDR2_DQ51

DDR2_DQ60
DDR2_DQ56

DDR2_DM7
DDR2_DQ63

DDR2_DQ58
ICH_SMBDATA

ICH_SMBCLK

+3VS

C133

0.1U_0402_16V4Z

+1.8V

1

2

JP2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2R-TR

SO-DIMM0
REVERSE

2

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

1

2

12

R77
10K_0402_5%

1

DDR2_VREF <8>

1

C107

0.1U_0402_16V4Z

2

1

X5.0

of

12 48Friday, June 17, 2005

+1.8V

DDR2_VREF

2

DDR2_DQ0

4

DDR2_DQ6

6
8

DDR2_DM0

10
12

DDR2_DQ2

14

DDR2_DQ3

16
18

DDR2_DQ13

20

DDR2_DQ9

22
24

DDR2_DM1

26
28

DDR2_CLK0

30

DDR2_CLK0#

32
34

DDR2_DQ15

36

DDR2_DQ11

38
40

42

DDR2_DQ23

44

DDR2_DQ17

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

DDR2_DM2

52
54

DDR2_DQ16

56

DDR2_DQ22

58
60

DDR2_DQ28

62

DDR2_DQ29

64
66

DDR2_DQS#3

68

DDR2_DQS3

70
72

DDR2_DQ25

74

DDR2_DQ30

76
78

DDR2_CKE1

80
82
84
86
88

DDR2_AA11

90

DDR2_AA7

92

DDR2_AA6

94
96

DDR2_AA4

98

DDR2_AA2

100

DDR2_AA0

102
104

DDR2_ABA1

106

DDR2_ARAS#

108

DDR2_CS0#

110
112

DDR2_ODT0

114

DDR2_AA13DDR2_CS1#

116
118
120
122

DDR2_DQ36

124

DDR2_DQ33

126
128

DDR2_DM4

130
132

DDR2_DQ35

134

DDR2_DQ34

136
138

DDR2_DQ45

140

DDR2_DQ44

142
144

DDR2_DQS#5

146

DDR2_DQS5

148
150

DDR2_DQ47

152

DDR2_DQ43

154
156

DDR2_DQ49

158

DDR2_DQ53

160
162

DDR2_CLK1

164

DDR2_CLK1#

166
168

DDR2_DM6

170
172

DDR2_DQ54

174

DDR2_DQ55

176
178

DDR2_DQ61

180

DDR2_DQ57

182
184

DDR2_DQS#7

186

DDR2_DQS7

188
190

DDR2_DQ62

192

DDR2_DQ59

194
196
198
200

R76
10K_0402_5%

1 2

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

C106

2.2U_0805_16V4Z

DDR2_CLK0 <8>
DDR2_CLK0# <8>

DDR2_CKE1 <8>

DDR2_ABA1 <9>
DDR2_ARAS# <9>
DDR2_CS0# <8>

DDR2_ODT0 <8>

DDR2_CLK1 <8>
DDR2_CLK1# <8>

DDR2-SODIMM0

Bandera-EAX00-LA2581

5

CLKSEL1CLKSEL0

FS_C FS_B FS_A

101

D D

CPU_BSEL0<6>

CPU_BSEL1<6>

C C

Use 12.1ohm+/- 1%
series resistor if the

+3VS BCLK

R346

0_0402_5%

CLKSEL0

12

R345

0_0402_5%

CLKSEL1

12

100X4=400

+VCCP

R78

@

1K_0402_5%

1 2

R171 1K_0402_5%

R347

@

0_0402_5%

1 2

+VCCP

R307
1K_0402_5%

1 2

R306 1K_0402_5%
R79

@

0_0402_5%

1 2

12

MCH_CLKSEL0 <8>

@

12

MCH_CLKSEL1 <8>

33P_0402_50V8J

33P_0402_50V8J

CLK_48M_ICH<18>

clock signal is shared
bewteen two devices.

SS frequency selection

96*_100MSEL

LOW
HIGH

B B

A A

96_100MSST/C

+3VS

R117
10K_0402_5%

1 2

96*_100MSEL

R123
10K_0402_5%

1 2

5

96 MHZ
100 MHZ

@

2N7002_SOT23

@

CLKEN_R#

13

D

Q17

VRMPWRGD

2

G

S

CLK_PCI_SD<21>
CLK_PCI_MINI<22>
CLK_PCI_TPM<27>
CLK_PCI_SIO<30>
CLK_PCI_LAN<23>
CLK_PCI_ICH<16>

CLK_PCI_EC<28>

VRMPWRGD <8,18,28>

+3VS

12

12

0.1U_0402_16V4Z

C148

12

C149

12

+3VS

+3VS

R217
10K_0402_5%

PCICLK2

R209

@

10K_0402_5%

4

+3VS

1 2

CHB2012U121_0805

1

C139

2

1 2

CHB2012U121_0805

Place crystal within
500 mils of CK410M

12

CLK_48M_ICH

CLK_PCI_SD
CLK_PCI_MINI
CLK_PCI_TPM
CLK_PCI_SIO
CLK_PCI_LAN
CLK_PCI_ICH

CLK_PCI_EC

4

CK_XTAL_IN

Y1

14.31818MHZ_20P_6X1430004201

R85 10K_0402_5%
R89 33_0402_5%

R185 12_0402_5%
R94 12_0402_5%
R98 33_0402_5%
R101 33_0402_5%
R104 33_0402_5%
R106 33_0402_5%

1 2

R110 10K_0402_5%
R109 33_0402_5%

ICH_SMBCLK<12,18,31>

ICH_SMBDATA<12,18,31>

1 2

R112 475_0402_1%

3

http://hobi-elektronika.net

L10

CK_VDD_MAIN2

L11

12
12

12
12
12
12
12
12

12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FS_A
CLKSEL0

CLKSEL1

PCICLK5
PCICLK4
PCICLK3
PCICLK2
96*_100MSEL

PCICLKF0
ICH_SMBCLK

ICH_SMBDATA

CLKIREF

Width=40mils

C85
10U_0805_6.3V6M

1

C140
1U_0603_10V4Z

2

Width=40mils

C86
10U_0805_6.3V6M

U40

21

VDDSRC_0

28

VDDSRC_1

34

VDDSRC_2

1

VDDPCI_0

7

VDDPCI_1

42

VDDCPU

48

VDDREF

11

VDD48

50

XIN

49

XOUT

12

FS_A/USB_48MHz

53

FS_C/TEST_SEL/REF1

16

FS_B/TEST_MODE

5

PCICLK5

4

PCICLK4

3

PCICLK3

56

PCICLK2/SEL_CLKREQ

9

PCICLK_F1/96*_100MSEL

8

PCICLK_F0/ITP_EN

46

SCLK

47

SDATA

39

IREF

13

GND_0

29

GND_1

2

GND_2

45

GND_3

51

GND_4

6

GND_5

IDTCV140PAG_TSSOP56

3

1

C135

0.047U_0402_16V4Z

2

1

C141

0.047U_0402_16V4Z

2

1

C145

0.047U_0402_16V4Z

2

CPUCLKT2_ITP/SRCCLKT_7

CPUCLKC2_ITP/SRCCLKC_7

96_100MSST/SRCCLKT0

96_100MSSC/SRCCLKC0

1

C136

0.047U_0402_16V4Z

2

1

C142

0.047U_0402_16V4Z

2

1

C146

0.047U_0402_16V4Z

2

VDDA
GNDA

PCI/SRC_STOP#

CPU_STOP#

CPUCLKT1
CPUCLKC1

CPUCLKT0
CPUCLKC0

SRCCLKT6/CLKREQA#

SRCCLKC6/CLKREQB#

SRCCLKT5
SRCCLKC5

SRCCLKT4_SATA
SRCCLKC4_SATA

SRCCLKT3

SRCCLKC3

SRCCLKT2

SRCCLKC2

SRCCLKT1

SRCCLKC1

DOTT_96MHz
DOTC_96MHz

VTT_PWRGD#/PD

REF0/FS_D

1

C137

0.047U_0402_16V4Z

2

1

C143

0.047U_0402_16V4Z

2

1

C147

0.047U_0402_16V4Z

2

37
38

PM_STP_PCI#

55

PM_STP_CPU#

54

CK_CPU2 CK_ITP

41

CK_CPU2#

40

CK_CPU0CK_XTAL_OUT

44

CK_CPU0#

43

CK_CPU1

36

CK_CPU1#

35

SRC6

33

SRC6#

32

SRC5

31

SRC5#

30

SRC4

26

SRC4#

27

24
25

SSCLK

22

SSCLK#

23

SRC1

19

SRC1#

20

SRC0

17

SRC0#

18

DOT96

14
15

CLKEN_R#

10

REFOUT CLK_14M_SIO

52

2

1

C138

0.047U_0402_16V4Z

2

Model

Signal

IDT CV140

SLG84443

Comments

1 2

R92 33_0402_5%

1 2

R95 33_0402_5%

1 2

R84 33_0402_5%

1 2

R88 33_0402_5%

1 2

R80 33_0402_5%

1 2

R82 33_0402_5%

1 2

R216 10K_0402_5%@

1 2

R208 0_0402_5%

1 2

R389 0_0402_5%@

1 2

R405 10K_0402_5%

1 2

R99 33_0402_5%

1 2

R102 33_0402_5%

1 2

R168 33_0402_5%

1 2

R163 33_0402_5%

1 2

R118 33_0402_5%

1 2

R120 33_0402_5%

1 2

R105 33_0402_5%

1 2

R107 33_0402_5%

1 2

R113 33_0402_5%

1 2

R115 33_0402_5%

1 2

R122 33_0402_5%

1 2

R124 33_0402_5%

1 2

R127 10K_0402_5%

1 2

R350 0_0402_5%

1 2

R128 12_0402_5%

1 2

R129 12_0402_5%

1 2

R91 12_0402_5%

2

1

CLKREQB#

CLKREQA#

SRC4/4#
NewCard

0

1
0
0
1
1

Main source IDT CV140 SRC1~7/1~7# can control by
CLKREQA# or CLKREQB#, in MP use CLKREQA# control;
2nd source Silego SLG84443 SRC1,3,4/1#,3#,4# can control
by CLKREQB# and SRC2,5/2#,5# can control by CLKREQA#

CK_ITP# CK_ITP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLKREQA#
CLKREQB#

CLK_PCIE_P0
CLK_PCIE_N0

CLK_PCIE_P2
CLK_PCIE_N2

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_ICH
CLK_PCIE_ICH#

DREF_SSCLK
DREF_SSCLK#

DREFCLK
DREFCLK#DOT96#

+3VS

CLKEN#

CLK_14M_CODEC
CLK_14M_ICH

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

0

1

0

1

PM_STP_PCI# <18>
PM_STP_CPU# <18>

CK_ITP <5>
CK_ITP# <5>

CLK_CPU_BCLK <5>
CLK_CPU_BCLK# <5>

CLK_MCH_BCLK <8>
CLK_MCH_BCLK# <8>

+3VS

CLKREQA# <15,31>
CLKREQB# <31>

+3VS

CLK_PCIE_P0 <31>
CLK_PCIE_N0 <31>

CLK_PCIE_P2 <31>
CLK_PCIE_N2 <31>

CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>

CLK_PCIE_ICH <18>
CLK_PCIE_ICH# <18>

DREF_SSCLK <8>
DREF_SSCLK# <8>

DREFCLK <8>
DREFCLK# <8>

CLKEN# <39>
CLK_14M_SIO <30>
CLK_14M_CODEC <25>

CLK_14M_ICH <18>

CK_ITP

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLKREQA#

SRC6#

CLK_PCIE_P0
CLK_PCIE_N0

CLK_PCIE_P2
CLK_PCIE_N2

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_ICH
CLK_PCIE_ICH#

DREF_SSCLK
DREF_SSCLK#

DREFCLK
DREFCLK#

12

Clock generator-CV140

Bandera-EAX00-LA2581

1

R218

@

0_0402_5%

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

SRC5/5#
GigaLAN

12

R9349.9_0402_1%

12

R9749.9_0402_1%

12

R8649.9_0402_1%

12

R9049.9_0402_1%

12

R8149.9_0402_1%

12

R8349.9_0402_1%

R10049.9_0402_1%
R10349.9_0402_1%

R18049.9_0402_1%
R20749.9_0402_1%

R11449.9_0402_1%
R11649.9_0402_1%

R10849.9_0402_1%
R11149.9_0402_1%

R11949.9_0402_1%
R12149.9_0402_1%

R12549.9_0402_1%
R12649.9_0402_1%

of

13 48Friday, June 17, 2005

X5.0

5

4

3

2

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http://hobi-elektronika.net

PID1 PID0 Vendor

PDCT
DTRB#
RTSB#

DIG_TXD_R
DIG_RXD_T

DIGISUSP
DIGRST#

PID0
PID1

TXACLK+
TXACLK-

TXA2+
TXA2-

TXA1+
TXA1-

TXA0+
TXA0-

AU-B084SN02

JP32

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31
32
33
34

IPEX_20143-030E

Top view

00

PDCT<28>
DTRB#<30>
RTSB#<30>

DIGISUSP<28>
DIGRST#<28>

PID0<18>

PID1<18>
TXACLK+<10>

TXACLK-<10>
TXA2+<10>

TXA2-<10>
TXA1+<10>

TXA1-<10>
TXA0+<10>

TXA0-<10>

001
1
11

AO3402_SOT23

D

1 3

Q7

S

R407

G

2

DIGI_FWE<18>

Digitizer pin CTS Connects to Hostˇs RTS for Plug & Play
Digitizer pin DSR Connects to Hostˇs DTR for Plug & Play

DIGI_FWE DIGI_FWE_C

+3VS

C155

10U_0805_16V3M

EMI request

R352

+LCDVDD

1 2

0_0805_5%

10U_0805_16V3M

C150

1

2

1 2

1

2

+LCD_VDD

@

0_0402_5%

2

C156

0.1U_0402_16V4Z

1

2

C151

0.1U_0402_16V4Z

1

12

R408
0_0402_5%

12

R132
100K_0402_5%

13

Q10
DTC124EK_SOT23

+12VALW

2

G

R231
10K_0402_5%

1 2

PID0
PID1

12

R130
100K_0402_5%

LCDPWR_ENGATE

13

D

Q9

2N7002_SOT23

S

0.1U_0402_16V4Z

D D

R131

470_0402_5%

Q8

2N7002_SOT23

ENVDD

ENVDD<10>

C C

12

13

D

S

2

22K

+3VS

+12VALW+LCDVDD

LCDPWR_ENGATE#

2

G

22K

R228
10K_0402_5%

1 2

C152

1

C179

0.01U_0402_16V7K

2

+3VS

1

1

C153

0.1U_0402_16V4Z

2

2

12

R133
150K_0402_5%

+LCDVDD

B+

12

B B

SIO_TXD<30>

SIO_RXD<30>

SIO_TXD
SIO_RXD

1 2

R334 0_0402_5%

1 2

R335 0_0402_5%

LCD/Inverter temperature monitor

SMB_EC_CK2<5,28>

SMB_EC_DA2<5,28>

A A

SMB_EC_CK2
SMB_EC_DA2

5

U36

4

SCLK

5

SDA

TC74A1-5.0VCT_SOT23-5

SM BUS Address : 1001 001

VDD

GND

3
2
1

NC

DIG_RXD_T
DIG_TXD_R

+5VS

1

2

C113

0.1U_0402_16V4Z

4

+3VS

R285

12

R329

4.7K_0402_5%

D18

BKOFF#<28>

ENABKL<10,28>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RB751V_SOD323

D20

RB751V_SOD323

21

21

3

@

0_0402_5%

1 2

Q16
2N7002_SOT23

D

1 3

G

2

1

C159

0.1U_0402_16V4Z

2

S

100K_0402_5%

1 2

R260

EMI request

DPST2.0

LBKLT_CRTL_PWM<10>

EC_INVT_PWM<28>

+5VS

2

R134
0_0402_5%

1 2

R135
0_0402_5%

1 2

R351
0_0805_5%

1

C157

0.01U_0603_50V4Z

2

@

DAC_BRIG<28>

1

C158

0.1U_0603_25V7K

2

INVT_PWM
DISPOFF#
DAC_BRIG

2

3

D27

PSOT24C_SOT23

1

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

INV_B+

JP4

1
2
3
4
5
6
7
8

MOLEX_53780-0890

LCD Conn/Inverter Conn

Bandera-EAX00-LA2581

1

X5.0

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14 48Friday, June 17, 2005

5

4

3

2

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http://hobi-elektronika.net

+2.5VS

2

3

D D

C162

10P_0402_50V8J

R139

150_0402_5%

1

C163

2

10P_0402_50V8J

L12

1 2

FBM-11-201209-170T (0805)
L13

1 2

FBM-11-201209-170T (0805)
L14

1 2

FBM-11-201209-170T (0805)

1 2

CRT_G_MB

150_0402_5%

R137

1

C161

2

150_0402_5%

1 2

1

2

10P_0402_50V8J

R138

1 2

D3

DAN217_SC59

1

1

C164

2

2

3

DAN217_SC59

1

1

C165

2

18P_0603_50V

D4

2

3

DAN217_SC59

1

1

C166

2

18P_0603_50V

D5

CRTR

CRTG

CRTB

3VDDCDA<10>

3VDDCCL<10>

18P_0603_50V

Notices: C164,C165,C166 change material in MP

C C

+5VS

CRT_HSYNC<10>

B B

CRT_HSYNC

R145

1K_0402_5%

1

5

P

CRT_HSYNCMB

4

OE#

A2Y

U8

G

SN74AHCT1G125GW_SOT353-5

3

5

P

A2Y

G

3

R146

1K_0402_5%

1

CRT_HSYNCDOCK

4

OE#

U9

SN74AHCT1G125GW_SOT353-5

Need tune this value

CRT_HSYNC_MB

12

R1154

39_0402_5%

CRT_HSYNC_DOCK

12

R1155

39_0402_5%

CRT_HSYNC_DOCK <31>

3VDDCDA

3VDDCCL

0.1U_0402_16V4Z

CRT_R<10>
CRT_G<10>
CRT_B<10>

+2.5VS

R141

2.2K_0402_5%

1 2

To DOCK

C168

CRT_R
CRT_G
CRT_B

R136

10K_0402_5%

1

2

16

+3VS

1 2

TOP VIEW

1

5

1617

JP5

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070112FR015S222XU

6
11
7
12
8
13
9
14
10
15

+3VS +5VS CRTVCC

R140

VCC

DA
DB
DC
DD

GND

3VDDCDA_R<31>

3VDDCCL_R<31>

10K_0402_5%

1 2

G

2

Q11

S

2N7002_SOT23

DOCKEN

EN

IN

S1A
S2A
S1B
S2B
S1C
S2C
S1D
S2D

R142

2.2K_0402_5%

1 2

+5VS

1

2

U11

16

4
7
9

12

8

PI5V330Q_QSOP16

13

D

G

S

2N7002_SOT23

15
1

2
3
5
6
11
10
14
13

12

R143

4.7K_0402_5%

3VDDC_GATE_EN

2

Q12

13

D

M_SEN#<18,31>

1: TO DOCK
0: TO MB

CRT_R_DOCK
CRT_G_DOCK
CRT_B_DOCK

12

C230

0.1U_0402_16V4Z

DOCKEN
CRT_R_MB
CRT_G_MB

CRT_B_MB

1.1A_6VDC_FUSE

R144

4.7K_0402_5%

1

2

DOCKEN <28>

F1

R395

1 2

100_0402_1%

CRT_R_DOCK <31>
CRT_G_DOCK <31>
CRT_B_DOCK <31>

RB491D_SOT23

21

0.1U_0402_16V4Z

CRT_M_SEN#M_SEN#

D2

2 1

C160

CRT_M_SEN#
CRTR

3VDDCDA_RCRT_R_MB
CRTG

CRT_HSYNC_MB
CRTB

CRT_VSYNC_MBCRT_B_MB

3VDDCCL_R

100P_0402_50V8J

1

2

C167

17

+5VS

5

CRT_VSYNC

A2Y

A2Y

CRT_VSYNC<10>

A A

R147

1K_0402_5%

1

5

P

CRT_VSYNCMB

4

OE#

U10

G

SN74AHCT1G125GW_SOT353-5

3

5

3

R148

1K_0402_5%

1

P

CRT_VSYNCDOCK

4

OE#

U12

G

SN74AHCT1G125GW_SOT353-5

R1156

39_0402_5%

R1157

39_0402_5%

CRT_VSYNC_MB

12

CRT_VSYNC_DOCK

12

4

+3VS

R399
10K_0402_5%

1 2

Q35

2N7002_SOT23

DOCKEN

CRT_VSYNC_DOCK <31>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

G

CLKREQA#

13

D

S

CLKREQA# <13,31>

2

OUTER Line

17 16

Compal Electronics, Inc.(KunShan)

Title

CRT interface

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

15 48Friday, June 17, 2005

X5.0