Acer LA-2581P Schematics

5

4

3

2

1

http://hobi-elektronika.net

Project name: Bandera(EAX00)

D D

PCB Serial Number: LA-2581

C C

Intel Dothan ULV1.1G/1.2G (Celeron-M ULV1.1G/1.2G) +Alviso GMS+ICH6-M

B B

2005-06-17

REV: X5.0

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Cover Sheet

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

148Friday, June 17, 2005

X5.0

5

4

http://hobi-elektronika.net

Block Diagram

3

2

1

DC-DC

D D

page 32,33,34,35,36,37

Power
Sequence

page 40

Dothan-ULV/Celeron-M ULV

Processor Thermal
sensor ADM1032

page 5

Panel Thermal sensor
TC74A1-5.0VCT

page 14

uFCBGA CPU

VCCP&CPU_CORE

page 38,39

Clock Generator

IDT CV140

page 13

C C

Docking Conn

B B

10/100M LAN

ALS

page 31

SD Controller

RTL8101L

page 23

Magnetic

page 24

& RJ45

P.I.R List

EE: page41, 42,43,44,45
Power: page 46

AU 8.4" SVGA
TFT LCD
Module

CRT CONN

page 21

SD Socket

page 14

page 15

3.3V 33MHz

MINI PCI

LVDS

PCI Express x2

PCI BUS

page 22

SMSC
LPC47N217

HA#(3..31)

System Bus

400MHz

Intel Alviso GMS

FC-BGA840

DMI X2

ICH6-M

609 BGA

page 16,17,18,19

LPC BUS

page 30

Embedded Controller

page 8,9,10,11

1.5V
100MHz

3.3V 33MHz

page 5,6,7

HD#(0..63)

Memory BUS (DDR2)

Channel A

USB 2.0

AC-LINK

ATA100

1.8V 400MHz

IDE Bus

page 27

TPM
SLD9630TT

DDR2 Thermal
sensor ADM1032

48MHz / 480Mb

3.3V 24.576MHz

HDD 1.8"

page 5

SO-DIMM X 1

BANK 0

page 20

page 12

ENE KB910L

page 28

A A

XBUS

Ambient Light
Sensor

ROM DAUGHTER/BOARD

MXLV008BTC

page 29

Digitizer FIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

HDD Thermal sensor
conn TC74A1-5.0VCT

page 20

USBPORT0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7

JUSBP0
JUSBP1
FPR
BT
DOCK

Not connect

DOCK
DOCK

page 27

page 27

page 29

page 22

page 31

page 31

page 31

AC97 CODEC

STAC9758

page 25

AMP & Phone

MIC

page 26

Compal Electronics, Inc.(KunShan)

Title

Block diagram

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

X5.0

of

248Friday, June 17, 2005

5

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D D

+3VS

External PCI Devices

DEVICE

IDSEL #

REQ/GNT # PIRQ

State

Signal

+12VALW
+5VALW
+3VALW
+1.5VALW

+3V

+1.5VS

+2.5VS+1.8V

+CPU_CORE

+5VS

+0.9VS

+VCCP

F,B3RTL8101L AD17

W83L528D AD20 2 A

AD18

ICH6M SM Bus Address

C C

DEVICE

Clock Generator
DDR2 DIMM0 1010 001Xb

Address

1101 001Xb

1Mini-PCI

G,H

S3

S5 S4/AC

S5 S4/AC don't exist

ON

ON

OFF

ONFULL ON

ON

OFF

ON

OFF

OFFOFFON

OFF

Power Management table

Voltage Rails

PORT FUNCTION

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

MB port

MB port

FPR

BT

Docking

reserved

Docking

Docking

USB PORT TABLE

DOCK NEW CARD TBDXb

Power Plane

EC SM Bus1 Address

DEVICE

Smart Battery 1 0001 011Xb
ALS TSL2550T
CPU ADM1032
HDD TC74A1-5.0VCT 1001 0010b

Address

0111 0010b
1001 100Xb

EC SM Bus 2 Address

B B

DEVICE Address

DDR2 ADM1032 1001 100Xb
Panel TC74A1-5.0VCT 1001 0010b

VIN
B+
+CPU_CORE
+VCCP
+0.9VS
+1.5VALW
+1.5VS
+1.8V
+2.5VS
+3VALW
+3VS 3.3V switched power rail
+5VALW
+5VS
+12VALW
RTCVCC

Description

Adapter power supply (19V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH core power

0.9V switched power rail for DDRII Vtt

1.5V always on power rail

1.5V switched power rail for PCI-E interface

1.8V power rail for DDRII

2.5V switched power rail for MCH video PLL

3.3V always on power rail

5V always on power rail
5V switched power rail
12V always on power rail

S0

N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ONRTC power

S5

S3

N/A

N/A
N/A

N/A

OFF

OFF
OFFOFF

OFF

OFF

ON

ON*
OFF

OFF
ON

OFF

OFF

OFF

ON ON*

OFF

OFF
ON

ON*

OFF

OFF
ON ON*
ON

ON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Notes

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

348Friday, June 17, 2005

X5.0

5

4

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http://hobi-elektronika.net

D D

B+

ADAPTOR

VS

DOCK

DOCK_IN

BATTERY

51_ON#

FAN5234

C C

+1.5VALW

SUSP

+1.5VS

+2.5VS

ACIN

MAINPWRON

G965

+3VALW

SYSON#

SUSP

MAX1902/
SC1404

+5VALW +12VALW

+3V

SUSP#

+3VS +5VS

SYSON

SUSP#

SUSP

MAX8743EEI

1.8V +VCCP

APL5331

0.9VS

SUSP#

FSTCHG

MAX1908

B B

CHARGER

IREF

VSB

BATT+

G920AT24U

VIN

Bridge Battery

RTC BATT

PM_DPRSLPVR

H_DPSLP#

VR_ON

SYSPOK

VRMPWRGD

CLKEN#

MAX1907

VID0

VID1

VID2

VID3

VID4

RTC_VCC

A A

Power Source

Charge Source

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+VCC_CORE

Compal Electronics, Inc.(KunShan)

Title

Power rail

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

448Friday, June 17, 2005

X5.0

5

4

3

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1

H_A#[3..31]<8>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10

D D

H_REQ#[0..4]<8>

R10 0_0402_5%

CK_ITP_R#

1 2

CK_ITP_R

1 2

R11 0_0402_5%

+VCCP

+VCCP

CK_ITP<13>
CK_ITP#<13>

CLK_CPU_BCLK<13>
CLK_CPU_BCLK#<13>

R14

1 2

56_0402_5%

H_RS#[0..2]<8>

R16

1 2

200_0402_1%

C C

B B

A A

H_ADSTB0#<8>
H_ADSTB1#<8>

CK_ITP CPU_CK_ITP
CK_ITP# CPU_CK_ITP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#<8>
H_BNR#<8>
H_BPRI#<8>
H_BR0#<8>
H_DEFER#<8>
H_DRDY#<8>
H_HIT#<8>
H_HITM#<8>

H_LOCK#<8>
H_RESET#<8>

H_TRDY#<8>

ITP_DBRESET#<18>

H_DBSY#<8>
H_DPSLP#<17,39>
H_DPRSTP#<17>

H_DPWR#<8>

H_PWRGOOD<17>
H_CPUSLP#<8,17>

R171K_0402_5%@

12

TEST2 TEST2

R181K_0402_5%@

12

H_THERMTRIP#<8,17>

5

H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB0#
H_ADSTB1#

R12 0_0402_5%

1 2
1 2

R13 0_0402_5%

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5

H_PROCHOT#

H_PWRGOOD

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1TEST1

ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

H_THERMTRIP#

+VCCP

R22

56_0402_5%

12

U1A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

Dothan ULV

C0 Stepping

12

R21
56_0402_5%

GATEON

H_PROCHOT#

Dothan

ADDR GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

+3VS

12

R20
1K_0402_5%

1

C

Q2

2

B

E

2SC2411K_SC59

3

DATA GROUP

LEGACY CPU

Change to 1.2G P/N

PROCHOT#

4

PROCHOT# <28>

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

STPCLK#

http://hobi-elektronika.net

H_D#0

A19

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

H_D#1

A25

H_D#2

A22

H_D#3

B21

H_D#4

A24

H_D#5

B26

H_D#6

A21

H_D#7

B20

H_D#8

C20

H_D#9

B24

H_D#10

D24

H_D#11

E24

H_D#12

C26

H_D#13

B23

H_D#14

E23

H_D#15

C25

H_D#16

H23

H_D#17

G25

H_D#18

L23

H_D#19

M26

H_D#20

H24

H_D#21

F25

H_D#22

G24

H_D#23

J23

H_D#24

M23

H_D#25

J25

H_D#26

L26

H_D#27

N24

H_D#28

M25

H_D#29

H26

H_D#30

N25

H_D#31

K25

H_D#32

Y26

H_D#33

AA24

H_D#34

T25

H_D#35

U23

H_D#36

V23

H_D#37

R24

H_D#38

R26

H_D#39

R23

H_D#40

AA23

H_D#41

U26

H_D#42

V24

H_D#43

U25

H_D#44

V26

H_D#45

Y23

H_D#46

AA26

H_D#47

Y25

H_D#48

AB25

H_D#49

AC23

H_D#50

AB24

H_D#51

AC20

H_D#52

AC22

H_D#53

AC25

H_D#54

AD23

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AF20

H_D#59

AE21

H_D#60

AD21

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

D25

H_DINV#1

J26

H_DINV#2

T24

H_DINV#3

AD20

H_DSTBN#0

C23

H_DSTBN#1

K24

H_DSTBN#2

W25

H_DSTBN#3

AE24

H_DSTBP#0

C22

H_DSTBP#1

L24

H_DSTBP#2

W24

H_DSTBP#3

AE25

H_A20M#

C2

H_FERR#

D3

H_IGNNE#

A3

H_INIT#

B5

H_INTR

D1

H_NMI

D4

H_STPCLK#

C6

H_SMI#

B4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_A20M# <17>
H_FERR# <17>
H_IGNNE# <17>
H_INIT# <17>
H_INTR <17>
H_NMI <17>

H_STPCLK# <17>
H_SMI# <17>

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_D#[0..63] <8>

ITP700FLEX FOR Dothan

ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO_R
ITP_TRST#

RESETITP#
ITP_TCK
CK_ITP_R#

CK_ITP_R

JP1

1

TDI

2

TMS

5

TCK

7

TDO

3

TRST#

12

RESET#
FBO
BCLK#

BCLK
GND0

GND1
GND2
GND3
GND4
GND5

ITP700-FLEXCON@

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

11

8
9

10
14
16
18
20
22

+VCCP

27

VTT0

28

VTT1

26

VTAP

ITP_DBR_RST# ITP_DBRESET#

25

DBR#

24

DBA#

23
21
19
17
15
13

4

NC1

6

NC2

Processor Thermal Sensor ADM1032AR

2200P_0402_50V7K

SMB_EC_CK1<20,28,29,33>

SMB_EC_DA1<20,28,29,33>

H_DSTBN#[0..3] <8>

H_DSTBP#[0..3] <8>

3

DDR2 Thermal Sensor ADM1032AR

Q1

2

3 1

MMBT3904_SOT23

SMB_EC_CK2<14,28>

SMB_EC_DA2<14,28>

Layout notice: place the
C5 close to the U3 pin2,3

C1

1 2

0.1U_0402_16V4Z

1 2

1

C3

2

1

C5
2200P_0402_50V7K

2

R3 200_0402_1%

H_THERMDA

H_THERMDC
SMB_EC_CK1
SMB_EC_DA1

DDR_THERMDA

DDR_THERMDC
SMB_EC_CK2
SMB_EC_DA2

2

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

Layout notice: place the
C3 close to the U2 pin2,3

+VCCP +VCCP

R1

54.9_0402_1%

1 2

+VCCP

1 2

R6 39.2_0603_1%

1 2

R8 150_0402_5%

+3VS

1

C2

0.1U_0402_16V4Z

2

U2

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARM_RM8

SM BUS1 Address : 1001 100Xb

U3

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARM_RM8

SM BUS2 Address : 1001 100Xb

VDD1

ALERT#

THERM#

GND

+3VS

1

C4

0.1U_0402_16V4Z

2

VDD1

ALERT#

THERM#

GND

1
6
4
5

1
6
4
5

R2

54.9_0402_1%

RESETITP# ITP_TDO_R

12

R4

22.6_0402_1%

ITP_TMS

ITP_TDI

12

R15

@

10K_0402_5%

THERM#

ALERT# PM_EXTTS0#
DDR_THERM#

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

R19 0_0402_5%

1 2
1 2

R333 0_0402_5%

Dothan host interface

Bandera-EAX00-LA2581

1 2

ITP_TDOH_RESET#

1 2

R7 680_0402_5%

1 2

R9 27.4_0402_1%

R5

22.6_0402_1%

1

12

ITP_TRST#
ITP_TCK

PM_EXTTS0# <8>

548Friday, June 17, 2005

of

X5.0

5

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DFT

AC26

AD26

AE7
AF6

F26

P23

W4

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16

L21

M6

M22
N21

P22

R21

T22

U21

D18
D20
D22

E17
E19
E21

F18

C16
C14

P25

P26
AB2
AB1

E26
AF7
AC1

B1
N1

K6
L5

N5
P6
R5
T6

D6
D8

E5
E7
E9

F6
F8

E1
E2

F2
F3
G3
G4
H4

C3

U1B

VCCSENSE
VSSSENSE

VCCA0
VCCA1
VCCA2
VCCA3

VCCQ0
VCCQ1

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

PSI#
VID0

VID1
VID2
VID3
VID4
VID5

GTLREF

BSEL0
BSEL1

COMP0
COMP1
COMP2
COMP3

RSVD
RSVD
RSVD
RSVD

Dothan ULV

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Dothan

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

R23

@

54.9_0402_1%

D D

VL

MAX6509SET

12

R26

21K_0603_1%

100K_0402_5%

C C

MAX6509OUT#

0.1U_0402_16V4Z

U4

1

SET

2

GND

3

OUT#

MAX6509CHU-K_SOT23-5~L

VL VL

12

R361

2

G

2

C251

1

5

VCC

4

HYST

R363
47K_0402_5%

1 2

MAX6509OUT

13

D

Q4

2N7002_SOT23

S

MAX6509HYST

2

C180

0.1U_0402_16V4Z

1

2

G

12

R25
10K_0402_5%

12

R27
10K_0402_5%

13

D

Q3
2N7002_SOT23

S

T=273.15+C

@

HYST=VCC: Hysteresis is 10 degree
HYST=GND: Hysteresis is 2 degree

MAINPWRON <17,35,36>

+1.5VS

0.01U_0402_16V7K

C6

1

2

54.9_0402_1%

C89
10U_0805_6.3V6M

+VCC_CORE

1 2
1 2

R24

@

+VCCP

VCCSENSE
VSSSENSE

R26: Rset(kohm)=(83793/T)-211.3569+(129890/T^2) T--Kelvin

Check with thermal(88C)

12

PSI
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5

+CPU_GTLREF

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

+VCCP

12

R30
1K_0402_1%

B B

A A

12

R31
2K_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

1

C8
1U_0603_10V4Z

2

1

C9
220P_0402_50V7K

2

R32

27.4_0402_1%

12

12

R33

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

CPU_VID0<39>
CPU_VID1<39>
CPU_VID2<39>
CPU_VID3<39>
CPU_VID4<39>
CPU_VID5<39>

CPU_BSEL0<13>
CPU_BSEL1<13>

12

R34

27.4_0402_1%

TP1
PAD

R35

54.9_0402_1%

+VCC_CORE

AA11
AA13
AA15
AA17
AA19
AA21

AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC11
AC13
AC15
AC17
AC19

AD10
AD12
AD14
AD16
AD18

AE11
AE13
AE15
AE17
AE19

AF10
AF12
AF14
AF16
AF18

G21
H22

W21

AA5
AA7
AA9

AB6
AB8

AC9

AD8

AE9

AF8

M21
M24

N22
N23
N26

R22
R25

F20
F22

G5
H6

J5
J21
K22

U5

V6

V22

W5

Y6

Y22

M4
M5

N3
N6

P2

P5
P21
P24

R1
R4
R6

T3

T5
T21
T23

U1C

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Dothan ULV

Dothan

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Dothan power and ground

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

648Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

Intel:Mid-Frequency Decoupling (0805 MLCC>= X5R) 5m ohm (typ) /25, 0.6 nH / 25.

+VCC_CORE

D D

+VCC_CORE

+VCC_CORE

+VCC_CORE

C C

+VCC_CORE

Capacitor Height: 1.25MM+-0.2

C10
10U_0805_6.3V6M

C20
10U_0805_6.3V6M

C25
10U_0805_6.3V6M

C30
10U_0805_6.3V6M

C15
10U_0805_6.3V6M

C11
10U_0805_6.3V6M

C21
10U_0805_6.3V6M

C26
10U_0805_6.3V6M

C31
10U_0805_6.3V6M

C16
10U_0805_6.3V6M

C12
10U_0805_6.3V6M

C22
10U_0805_6.3V6M

C27
10U_0805_6.3V6M

C32
10U_0805_6.3V6M

C17
10U_0805_6.3V6M

C13
10U_0805_6.3V6M

C23
10U_0805_6.3V6M

C28
10U_0805_6.3V6M

C33
10U_0805_6.3V6M

C18
10U_0805_6.3V6M

C14
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

C29
10U_0805_6.3V6M

C34
10U_0805_6.3V6M

C19
10U_0805_6.3V6M

H1
HOLE

H7
HOLE

H11
HOLE

H16
HOLE

H18
HOLE

1

1

1

1

1

M1
HOLE

1

H3

H2

HOLE

HOLE

1

1

H8

H9

HOLE

HOLE

1

1

H12

H13

HOLE

HOLE

1

1

H17
HOLE

1

HDD conn hole

M2
HOLE

1

H4
HOLE

H10
HOLE

H14
HOLE

1

1

1

H5

H6

HOLE

HOLE

Frame hole

1

1

CPU thermal hole

H15

H11, H12 HDD upper hole

HOLE

H13 HDD conn hole
H14, H15 DOCK conn hole

1

H17 BIOS/B hole

M3
HOLE

1

M4
HOLE

1

M5
HOLE

FD2

FD1

1

1

FD3

1

1

1

1

1

1

1

1

1

FD4

1

FD5

FD6

1

FD7

FD8

1

CF1

CF2

1

CF3

CF4

1

CF6

CF5

1

CF8

CF7

1

CF10

CF9

1

Intel: Low-Frequency Decoupling : 9 m ohm (max)/3, 1.8 nH / 3

+VCC_CORE

B B

C35

@

330U_D2E_2.5VM_R9

9mOhm
7343
PS CAP

1

+

2

1

+

C36

C37

2

330U_D2E_2.5VM_R9

9mOhm

9mOhm

7343

7343

PS CAP

PS CAP

1

Near VCORE regulator.

+

2

330U_D2E_2.5VM_R9

Intel: High Frequency Decoupling (0603 MLCC, >= X7R) 16 m ohm (typ) / 10, 0.6 nH / 10

+VCCP

1

+

C38
150U_D2_4VM

2

A A

5

1

C39

0.1U_0402_16V4Z

2

1

C40

0.1U_0402_16V4Z

2

4

1

C41

0.1U_0402_16V4Z

2

1

C42

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C43

0.1U_0402_16V4Z

2

1

2

3

C44

0.1U_0402_16V4Z

1

C45

0.1U_0402_16V4Z

2

1

C46

0.1U_0402_16V4Z

2

1

C47

0.1U_0402_16V4Z

2

2

1

C48

0.1U_0402_16V4Z

2

Compal Electronics, Inc.(KunShan)

Title

Dothan decoupling cap

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

748Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

D15
E17
F15
G17
H17

H19
F29
E27
W2

J26
J27
J18
W27
W25

A22
A21
J31
H31

CFG[2:0]

CFG5

CFG6

CFG0
MCH_CLKSEL1
MCH_CLKSEL0
CFG5
CFG6

PM_BMBUSY#
PM_EXTTS0#
H_THERMTRIP#
VRMPWRGD
PLT_RST#

DREFCLK#
DREFCLK
DREF_SSCLK
DREF_SSCLK#

H_A#[3..31]<5>

D D

H_REQ#[0..4]<5>

C C

H_ADSTB0#<5>
H_ADSTB1#<5>

CLK_MCH_BCLK#<13>
CLK_MCH_BCLK<13>

H_DSTBN#[0..3]<5>

H_DSTBP#[0..3]<5>

H_DINV#0<5>
H_DINV#1<5>
H_DINV#2<5>
H_DINV#3<5>

H_RESET#<5>
H_ADS#<5>

H_TRDY#<5>
H_DPWR#<5>
H_DRDY#<5>
H_DEFER#<5>

H_HITM#<5>

B B

H_HIT#<5>
H_LOCK#<5>
H_BR0#<5>
H_BNR#<5>
H_BPRI#<5>
H_DBSY#<5>

H_RS#[0..2]<5>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB0#
H_ADSTB1#

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#

H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#

H_HITM#
H_HIT# H_VREF
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_R_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

U5A

C6

HA3#

G11

HA4#

E12

HA5#

B8

HA6#

C11

HA7#

B11

HA8#

C9

HA9#

A11

HA10#

D12

HA11#

F13

HA12#

E11

HA13#

A13

HA14#

C12

HA15#

G12

HA16#

G14

HA17#

J14

HA18#

G13

HA19#

H14

HA20#

B13

HA21#

A14

HA22#

C13

HA23#

J15

HA24#

H12

HA25#

E13

HA26#

C14

HA27#

F14

HA28#

E14

HA29#

D13

HA30#

B14

HA31#

A8

HREQ0#

B7

HREQ1#

A9

HREQ2#

A7

HREQ3#

J12

HREQ4#

F11

HADSTB0#

H15

HADSTB1#

AA3

HCLKN

Y3

HCLKP

G5

HDSTBN0#

K8

HDSTBN1#

U1

HDSTBN2#

AA4

HDSTBN3#

G4

HDSTBP0#

L9

HDSTBP1#

U2

HDSTBP2#

AA5

HDSTBP3#

J6

HDINV0#

L7

HDINV1#

R7

HDINV2#

W5

HDINV3#

F7

HCPURST#

G9

HADS#

E9

HTRDY#

G1

HDPWR#

A4

HDRDY#

E5

HDEFER#

C3

HHITM#

B2

HHIT#

C4

HLOCK#

F9

HBREQ0#

E8

HBNR#

B3

HBPRI#

F8

HDBSY#

C5

HCPUSLP#

A5

HRS0#

B5

HRS1#

C7

HRS2#

ALVISO_BGA840

Alviso

HOST

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

H_D#0

F5

H_D#1

F2

H_D#2

E2

H_D#3

J5

H_D#4

F3

H_D#5

G3

H_D#6

F4

H_D#7

E3

H_D#8

J9

H_D#9

F6

H_D#10

J7

H_D#11

J8

H_D#12

J1

H_D#13

F1

H_D#14

K9

H_D#15

G7

H_D#16

K3

H_D#17

K4

H_D#18

P1

H_D#19

R2

H_D#20

K5

H_D#21

J3

H_D#22

J2

H_D#23

L5

H_D#24

U8

H_D#25

K7

H_D#26

U9

H_D#27

V9

H_D#28

R1

H_D#29

K6

H_D#30

U3

H_D#31

R9

H_D#32

V3

H_D#33

V4

H_D#34

R6

H_D#35

P5

H_D#36

P3

H_D#37

R8

H_D#38

P7

H_D#39

P9

H_D#40

W3

H_D#41

R4

H_D#42

R3

H_D#43

R5

H_D#44

U6

H_D#45

U5

H_D#46

V5

H_D#47

V6

H_D#48

W7

H_D#49

W8

H_D#50

W1

H_D#51

V2

H_D#52

W4

H_D#53

Y2

H_D#54

Y5

H_D#55

AA9

H_D#56

AA8

H_D#57

AA1

H_D#58

V7

H_D#59

AA6

H_D#60

Y6

H_D#61

Y8

H_D#62

W9

H_D#63

Y7
J11

H_XRCOMP

K1

H_XSCOMP

E6

H_YRCOMP

L1

H_YSCOMP

K2

H_SWNG0

J13

H_SWNG1

L3

Change to C0 version

R56

H_CPUSLP#<5,17>

A A

Reserved this Resistor for CPU sleep drive by Alviso or ICH6, This resistor can be
delete after intel ensure don't change this Enhance C3 function

H_CPUSLP# H_R_CPUSLP#

0_0402_5%

1 2

H_D#[0..63] <5> DMI_TXN0<18>

+VCCP

12

R36

1

R37

2

C49

0.1U_0402_16V4Z

+VCCP

R41

1

R43

2

0.1U_0402_16V4Z

12

12

R49

54.9_0402_1%

221_0603_1%

12

100_0402_1%

12

221_0603_1%

12

100_0402_1%

1

C53

2

220P_0402_50V7K

+VCCP

12

R50

100_0402_1%

12

R51

200_0402_1%

Layout Note:
Route as short
as possible

12

@

@

R44

40.2_0402_1%

12

R45

40.2_0402_1%

12

R52

24.9_0402_1%

H_SWNG1

H_SWNG0

C50

+VCCP

R48

54.9_0402_1%

12

R53

24.9_0402_1%

DMI_TXN1<18>

DMI_TXP0<18>
DMI_TXP1<18>

DMI_RXN0<18>
DMI_RXN1<18>

DMI_RXP0<18>
DMI_RXP1<18>

DDR2_CLK0<12>
DDR2_CLK1<12>

DDR2_CLK0#<12>
DDR2_CLK1#<12>

DDR2_CKE0<12>
DDR2_CKE1<12>

DDR2_CS0#<12>
DDR2_CS1#<12>

DDR2_ODT0<12>

1 2
1 2

1

C51

2

0.1U_0402_16V4Z

DDR2_VREF<12>

DDR2_ODT1<12>

C52

0.1U_0402_16V4Z

+1.8V

R46 80.6_0402_1%
R47 80.6_0402_1%

1

2

DMI_TXN0
DMI_TXN1

DMI_TXP0
DMI_TXP1

DMI_RXN0
DMI_RXN1

DMI_RXP0
DMI_RXP1

DDR2_CLK0
DDR2_CLK1

DDR2_CLK0#
DDR2_CLK1#

DDR2_CKE0
DDR2_CKE1

DDR2_CS0#
DDR2_CS1#

M_OCDOCMP0
M_OCDOCMP1
DDR2_ODT0
DDR2_ODT1

SMRCOMPN
SMRCOMPP
DDR2_VREF

SMXSLEWIN_OUT
SMYSLEWIN_OUT

10/20 Mil
width/space ,
Length1.5''

+1.8V

12

DDR2_VREF

12

W29

W31

AE31

AJ29

AH5

AF31

AJ28

AC23
AC25
AH21

AJ21

AD11
AG13

AL14

AH12
AB27
AF12

AG12
AK13

AJ12

AD7

AA25
AC10
AD10

R54
1K_0402_1%

R55
1K_0402_1%

U5B

V24

DMI_RXN0
DMI_RXN1

U24

DMI_RXP0

V29

DMI_RXP1

V26

DMI_TXN0
DMI_TXN1

U26

DMI_TXP0

V31

DMI_TXP1

DMIDDR MUXING

SM_CK0

AF5

SM_CK1
SM_CK3

SM_CK4

SM_CK0#

AE5

SM_CK1#
SM_CK3#

AJ5

SM_CK4#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SMOCDCOMP0

AE9

SMOCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN

AE7

SMRCOMPP

Y30

SMVREF0

AE1

SMVREF1

Y24

SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

ALVISO_BGA840

Close Alviso

CFG0
CFG1
CFG2
CFG5
CFG6

RSVD23
RSVD24
RSVD25

RSVD1

CFG/RSVD

BM_BUSY#

EXT_TS0#

THRMTRIP#

PWROK

PM

RSTIN#

DREF_CLKN

CLK

DREF_CLKP
DREF_SSCLKP
DREF_SSCLKN

101(400MHz FSB)
Low = DMI x 2

High = DMI x 4
Low = DDR-II
High = DDR-I

MCH_CLKSEL1 <13>
MCH_CLKSEL0 <13>

CFG0

CFG5
CFG6

EC_EXTTS0#<28>

PM_EXTTS0#<5>

PM_BMBUSY# <18>
H_THERMTRIP# <5,17>

VRMPWRGD <13,18,28>
PLT_RST# <16,20,27,28,30>

DREFCLK# <13>
DREFCLK <13>
DREF_SSCLK <13>
DREF_SSCLK# <13>

12

R38 10K_0402_5%

1 2

R39 2.2K_0402_5%

1 2

R40 2.2K_0402_5%

1 2

*

*

R58

@

0_0402_5%

R42

10K_0402_5%

+VCCP

+2.5VS

12

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Alviso GMS host/DMI/DDR/PM/CLK

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

848Friday, June 17, 2005

X5.0

5

4

http://hobi-elektronika.net

Intel demand in

3

2

1

Soloma Platform
design guide P428

AB18

M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22

R10
R11
R12
R13
R14
R18
R19
R20
R21
R22

U10
U11
U12
U13
U14
U18
U19
U20
U21
U22

W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22

P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22

T11
T12
T13
T14
T18
T19
T20
T21

V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22

Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19

U5F

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

ALVISO_BGA840

A10

NC

A2

NC

A29

NC

A3

NC

A30

NC

A31

NC

AA10

NC

AA11

NC

AA12

NC

AA13

NC

AA14

NC

AA15

NC

AA16

NC

AA17

NC

AA18

NC

AA19

NC

AA20

NC

AA21

NC

AA22

NC

AB1

NC

AB10

NC

AB11

NC

AB12

NC

AB13

NC

AB14

NC

AB15

NC

AB17

NC

AB19

NC

AB2

NC

AB20

NC

AB21

NC

AB22

NC

AB3

NC

AB5

NC

AB6

NC

AB7

NC

AB9

NC

AC22

NC

AE22

NC

AF22

NC

AG22

NC

AJ1

NC

AJ22

NC

AJ31

NC

AK1

NC

AK22

NC

AK31

NC

AL1

NC

AL2

NC

AL22

NC

AL29

NC

AL3

NC

AL30

NC

AL31

NC

B1

NC

B10

NC

B31

NC

C1

NC

C10

NC

C31

NC

E10

NC

F10

NC

G10

NC

J10

NC

K10

NC

K11

NC

K12

NC

K13

NC

K14

NC

K15

NC

K17

NC

K18

NC

K19

NC

K20

NC

K21

NC

K22

NC

K23

NC

K25

NC

K26

NC

K27

NC

K29

NC

K30

NC

K31

NC

L10

NC

L11

NC

L12

NC

L13

NC

L14

NC

L15

NC

L16

NC

L17

NC

L18

NC

L19

NC

L20

NC

L21

NC

L22

NC

M10

NC

M11

NC

M12

NC

Y20

NC

Y21

NC

Y22

NC

AA23
AA26
AA27

AB28
AB30
AC24
AC28

AC9
AD12
AD15
AD19

AD2
AD21

AD5

AD9
AE10
AE11
AE13
AE26
AE30
AF11
AF15
AF19
AF23
AF28
AF30

AF7

AG2
AG21
AG25

AG3
AH10
AH13
AH15
AH19

AH6

AJ27

AK12
AK15
AK19
AK21
AK23
AK26
AK29

AK5

AK9

C15

C17

C19

C25

C30

D11

D14

U23

U25

U27

U5G

A15

VSS

A18

VSS

A20

VSS

A25

VSS

A27

VSS

AA2

VSS
VSS
VSS
VSS

AA7

VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B12

VSS

B15

VSS

B22

VSS

B27

VSS

B4

VSS

B6

VSS

B9

VSS
VSS
VSS
VSS

C2

VSS
VSS
VSS

C8

VSS
VSS
VSS
VSS
VSS
VSS

V28

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSW6VSS

VSS

VSS

VSS

VSS

VSSY4VSSY9VSS

U4

Y23

Y25

Y26

Y29

W30

Y31

U31

U29

W24

W26

W28

VSSALVDS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

ALVISO_BGA840

V27

B30
D18

D19
D25
E15
E21
E23
E26
E29
E30
E4
E7
F12
F17
F23
F27
G15
G2
G21
G22
G25
G29
G31
G6
G8
H11
H13
H18
H20
H23
H26
H30
J17
J20
J22
J4
L2
L25
L27
L29
L4
L6
L8
M23
M25
M27
M29
N25
N27
N29
N31
P2
P23
P25
P27
P29
P4
P6
P8
R16
R24
R25
R26
R27
R29
U15
U17
U7
V1
V25
V30
V8

+2.5VS

D D

DDR2_ABA0<12>
DDR2_ABA1<12>
DDR2_ABA2<12>
DDR2_DM[0..7]<12>

DDR2_DQS[0..7]<12>

C C

B B

A A

DDR2_DQS#[0..7]<12>

DDR2_AA[0..13]<12>

DDR2_ACAS#<12>
DDR2_ARAS#<12>

DDR2_AWE#<12>

Use for emulating source
synchronous clocking for
reads. these signal are routed
internally on the GMCH
package and can be NC.

DDR2_ABA0
DDR2_ABA1
DDR2_ABA2

DDR2_DM0
DDR2_DM1
DDR2_DM2
DDR2_DM3
DDR2_DM4
DDR2_DM5
DDR2_DM6
DDR2_DM7

DDR2_DQS0
DDR2_DQS1
DDR2_DQS2
DDR2_DQS3
DDR2_DQS4
DDR2_DQS5
DDR2_DQS6
DDR2_DQS7

DDR2_DQS#0
DDR2_DQS#1
DDR2_DQS#2
DDR2_DQS#3
DDR2_DQS#4
DDR2_DQS#5
DDR2_DQS#6
DDR2_DQS#7

DDR2_AA0
DDR2_AA1
DDR2_AA2
DDR2_AA3
DDR2_AA4
DDR2_AA5
DDR2_AA6
DDR2_AA7
DDR2_AA8
DDR2_AA9
DDR2_AA10
DDR2_AA11
DDR2_AA12
DDR2_AA13

DDR2_ACAS#
DDR2_ARAS#

DDR2_AWE#

AE15
AD13
AB25

AA31

AJ30
AF24
AK24

AJ10

AG7
AD6

AB29

AL28
AF25

AJ23
AK10

AG9
AH3
AE2

AA30
AK28
AF26

AJ24

AL10

AG5

AC21
AC20
AC19
AD20
AE19
AE20
AF20
AF21
AE21
AA24
AC11
AB23
AB24
AF13

AE12
AG15
AC27
AB26

AJ15

AJ14
AG14

AL21
AC12

AE14
AC15
AD14
AG19

AJ19

AJ20
AK20

AL19
AH20
AF14

AL20
AG20

AL13

AJ13
AH14
AK14

AL5

AF9
AF2

U5C

SA_BS0
SA_BS1
SA_BS2

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

SB_BS0
SB_BS1
SB_BS2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_WE#

ALVISO_BGA840

DDR2_

ADDR_A

SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR2_DATA

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

DDR2_ADDR_B DDR2_ADDR_A DDR2_DQS

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9

Y27
Y28
AC29
AE29
AA28
AA29
AB31
AC30
AG29
AG28
AJ26
AL26
AG30
AG31
AL27
AK27
AF29
AE28
AE25
AE24
AE27
AF27
AE23
AC26
AL25
AJ25
AG27
AG26
AK25
AL24
AG23
AG24
AK11
AL11
AJ7
AL9
AL12
AJ11
AH9
AJ9
AG10
AF10
AH7
AF6
AH11
AG11
AG6
AE6
AL7
AK7
AK2
AJ2
AK6
AJ6
AK3
AH2
AH1
AG1
AC6
AC7
AF3
AE3
AD3
AC2

DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ29
DDR2_DQ30
DDR2_DQ31
DDR2_DQ32
DDR2_DQ33
DDR2_DQ34
DDR2_DQ35
DDR2_DQ36
DDR2_DQ37
DDR2_DQ38
DDR2_DQ39
DDR2_DQ40
DDR2_DQ41
DDR2_DQ42
DDR2_DQ43
DDR2_DQ44
DDR2_DQ45
DDR2_DQ46
DDR2_DQ47
DDR2_DQ48
DDR2_DQ49
DDR2_DQ50
DDR2_DQ51
DDR2_DQ52
DDR2_DQ53
DDR2_DQ54
DDR2_DQ55
DDR2_DQ56
DDR2_DQ57
DDR2_DQ58
DDR2_DQ59
DDR2_DQ60
DDR2_DQ61
DDR2_DQ62
DDR2_DQ63

DDR2_DQ[0..63] <12>

12

R57
10K_0402_5%

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Alviso GMS DDR2/VSS

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

948Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

D D

SDVOCTRL_DATA:0=No SDVO device-have put down internal
present(default) 1=SDVO device present

U5E

H27

SDVOCTRL_DATA

G27

CLK_MCH_3GPLL#<13>
CLK_MCH_3GPLL<13>

CLK_MCH_3GPLL#
CLK_MCH_3GPLL

TV_REFSET, Intel DG
page 200 indicate
directly to GND

W23

V23

A17
C18
A19

J19
B17
B18
B19

SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

MISCTVVGALVDS

EXP_COMPI

EXP_ICOMPO

SDVO_TVCLKIN#

SDVO_INT#

SDVO_FLDSTALL#

P26
L26

M28
P28
U28

PCI Express in/out put current compensation

+1.5VS_PCIE

R59

24.9_0402_1%

EXP_COMPIO

1 2

R1152
R1153

150_0402_1%
150_0402_1%
150_0402_1%

TXA0-<14>
TXA1-<14>
TXA2-<14>

TXA0+<14>
TXA1+<14>
TXA2+<14>

3VDDCCL
3VDDCDA

12

R61

12

R332

12

CRT_VSYNC_R

R63

CRT_HSYNC_R

R64 255_0402_1%

MP BOM change

LBKLT_CRTL
ENABLT

ENVDD
LIBG

TXACLK­TXACLK+

TXA0­TXA1­TXA2-

TXA0+
TXA1+
TXA2+

CRT_B
CRT_G
CRT_R

3VDDCCL<15>
3VDDCDA<15>

CRT_B<15>

C C

CRT_VSYNC<15>
CRT_HSYNC<15>

CRT_VSYNC
CRT_HSYNC LBKLT_CRTL_PWM

CRT_G<15>
CRT_R<15>

39_0402_5%
39_0402_5%

12
12

Need tune this value

R66 100K_0402_1%

+2.5VS

Pull-up: normal-polarity inverter
Pull-down: inverted polarity inverter

B B

1 2

1 2

R68 1.5K_0402_1%

ENVDD<14>

TXACLK-<14>
TXACLK+<14>

J23

DDCCLK

J25

DDCDATA

D23

BLUE

C23

BLUE#

E22

GREEN

D22

GREEN#

F21

RED

F22

RED#

G23

VSYNC

H22

HSYNC

J21

12

REFSET

G26

LBKLT_CRTL

F26

LBKLT_EN

D26

LCTLA_CLK

C26

LCTLB_DATA

E25

LDDC_CLK

F25

LDDC_DATA

H25

LVDD_EN

F30

LIBG

G30

LVBG

J29

LVREFH

H29

LVREFL

D27

LACLKN

C27

LACLKP

F31

LADATAN0

D31

LADATAN1

D29

LADATAN2

E31

LADATAP0

D30

LADATAP1

C29

LADATAP2

ALVISO_BGA840

SDVO_TVCLKIN

SDVO_FLDSTALL

SDVOB_RED#

SDVOB_GREEN#

SDVOB_BLUE#

SDVOB_BLKN

PCI - EXPRESS GRAPHICS

SDVOB_RED

SDVOB_GREEN

SDVOB_BLUE
SDVOB_BLKP

SDVO_INT

L28
N28
R28

LBKLT_CRTL

M30
N26
P30
U30

L30
M26
N30
R30

+2.5VS +3VS

G

2

Q5

13

D

S

BSS138_SOT23

+2.5VS +3VS

G

2

Q6

13

D

S

BSS138_SOT23

12

R60

2.2K_0402_5%

12

R65

2.2K_0402_5%

ENABKLENABLT

LBKLT_CRTL_PWM <14>

ENABKL <14,28>

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Alviso GMS Display interface

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

10 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

+VCCP

U5D

L23

VCC

1

1

1

C54

C55

D D

C406 0.47U_0402_6.3V4Z

1 2

C C

2

C407 0.47U_0402_6.3V4Z

2

10U_0805_4VAM

10U_0805_4VAM

1 2

47U_1210_10V3M

C56

C57

2

10U_0805_4VAM

C368

1

2

+VCCP

+1.8V

1

2

C58

0.1U_0402_16V4Z

Place closed GMS

C401 0.47U_0402_6.3V4Z

C402 0.47U_0402_6.3V4Z

1 2

C405 0.47U_0402_6.3V4Z

1 2

B B

1 2

C403 0.47U_0402_6.3V4Z

1 2

C404 0.47U_0402_6.3V4Z

1 2

1

1

C59

2

2

C60 0.22U_0603_10V7K

C71

4.7U_0805_10V4Z

C76 0.22U_0603_10V7K

C62

0.1U_0402_16V4Z

1 2

1

1

C72

2

2

2.2U_0805_16V4Z

1 2

C61

10U_0805_6.3V6M

10U_0805_6.3V6M

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL
+1.5VS_MPLL

0.1U_0402_16V4Z

+1.5VS

M24
N23
N24

R15
R17

U16

AD18
AE17
AE18

AF1
AF17
AF18
AH17
AH18

AJ17

AJ18
AK17
AK18
AK30

AL17
AL18
AL23

AG17
AG18
AC17
AC18
AC31
AD17

AC3
AC5

AD1
AC1

L24

P24

T15
T16
T17

A6

A12

E1
M1
M2
M3
M4
M5
M6
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9

Y1

AL6

B21

J30

VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER

VCC
VCC
VCC
VCC

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

ALVISO_BGA840

VCCA_TVDACA
VCCA_TVDACA
VCCA_TVDACB
VCCA_TVDACB
VCCA_TVDACC
VCCA_TVDACC

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS
VCCD_LVDS
VCCD_LVDS

VCCA_LVDS

VCCTX_LVDS
VCCTX_LVDS

VCCA_3GPLL

VCCA_3GBG

VSSA_3GBG

VCCA_CRTDAC
VCCA_CRTDAC
VSSA_CRTDAC

VCCHV
VCCHV
VCCHV

VCCA_SM
VCCA_SM
VCCA_SM

VCC3G
VCC3G

VCC_SYNC

F18
G18
F19
G19
F20
G20

E19
E20

E18
D17

A23
B23
B25

B29
B20

C21
C22

A26
B26

AC13
AC14
AL15

P31
R31

R23

M31
L31

H21
C20

D21
D20

+1.5VS_DDRDLL

1

C74

2

0.1U_0402_16V4Z

+2.5VS_CRT_DAC

C93

0.022U_0402_16V7K

+2.5VS_CRTDAC

C90

1

+

C73

2

100U_D2_6.3VM

L5 BLM18PG600SN1_0603

1 2

1

1

C94

2

2

1

C70

2

10U_0805_6.3V6M

+1.5VS_PCIE

1

C78

2

0.1U_0402_16V4Z

+1.5VS

+2.5VS

1

1

C65

0.1U_0402_16V4Z

1

C79

2

10U_0805_4VAM

1

C95

2

Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

C66

2

2

0.01U_0402_16V7K

+1.5VS_3GPLL

1

C364

2

10U_0805_4VAM

47U_1210_10V3M

+2.5VS_3GBG

+2.5VS_CRTDAC

1

C96

2

10U_0805_4VAM

0.1U_0402_16V4Z

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Alviso.

1

C67

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C81

2

2

0.1U_0402_16V4Z

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

+2.5VS

C63

1

C68

2

10U_0805_4VAM

3GRLL_R

1 2

R73 0.5_0805_1%

C82

10U_0805_4VAM

L4

BLM18PG600SN1_0603

1

C87

0.1U_0402_16V4Z

2

1

1

C64

2

2

12

4.7U_0805_10V4Z

L1

L2

L3

C83

+2.5VS

1

C88

0.1U_0402_16V4Z

2

12

12

12

0.1U_0402_16V4Z

BLM18PG600SN1_0603

BLM18PG600SN1_0603

BLM18PG600SN1_0603

+1.5VS

+1.5VS

C77

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C75

1

2

+1.5VS

1

2

0.1U_0402_16V4Z

+1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_MPLL+1.5VS_HPLL

L6

BLM18PG600SN1_0603

1 2

+1.5VS +1.5VS +1.5VS +1.5VS

1

2

C100

5

1

2

0.1U_0402_16V4Z

C232

22U_1206_16V4Z_V1

A A

L8

BLM18PG600SN1_0603

1 2

1

C233

2

22U_1206_16V4Z_V1

1

C104

2

0.1U_0402_16V4Z

BLM18PG600SN1_0603

1 2

4

L9

C362

L7

BLM18PG600SN1_0603

1 2

1

1

C105

2

2

0.1U_0402_16V4Z

22U_1206_16V4Z_V1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C363

22U_1206_16V4Z_V1

1

2

3

1

C102

2

0.1U_0402_16V4Z

+VCCP

+2.5VS

D1

2 1

RB751V_SOD323

+VCCP_CRTDAC_D

R74

1K_0805_1%

1 2

R75

0_0805_5%

1 2

2

+2.5VS_CRTDAC

Compal Electronics, Inc.(KunShan)

Title

Alviso GMS power interface

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

11 48Friday, June 17, 2005

X5.0

5

2.2U_0805_16V4Z
C110

C109

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C117

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C123

+0.9VS

RP1

18
27
36
45

RP3

18
27
36
45

RP5

18
27
36
45

DDR2_DQS#[0..7]
DDR2_DQ[0..63]
DDR2_DM[0..7]
DDR2_DQS[0..7]
DDR2_AA[0..13]

2.2U_0805_16V4Z
C111

1

2

0.1U_0402_16V4Z

C118

1

2

0.1U_0402_16V4Z

1

1

2

2

C125

C124

RP2

56_0804_8P4R_5%

RP4

56_0804_8P4R_5%

RP6

56_0804_8P4R_5%

RP7

56_0804_8P4R_5%

2.2U_0805_16V4Z
C112

1

2

0.1U_0402_16V4Z

C119

1

2

0.1U_0402_16V4Z

1

2

C126

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

Layout Note:
Place near JP2

0.1U_0402_16V4Z

C353

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C127

DDR2_CKE0DDR2_CKE1
DDR2_ABA2
DDR2_AA12
DDR2_AA9

DDR2_AA5
DDR2_AA3
DDR2_AA1

DDR2_AA10
DDR2_ABA0
DDR2_AWE#
DDR2_ACAS#

DDR2_CS1#
DDR2_ODT1

C310

0.1U_0402_16V4Z

1

2

C128

C129

DDR2_DQS#[0..7]<9>
DDR2_DQ[0..63]<9>
DDR2_DM[0..7]<9>
DDR2_DQS[0..7]<9>
DDR2_AA[0..13]<9>

D D

C C

B B

A A

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C108

1

1

2

2

0.1U_0402_16V4Z

150U_D2_4VM

1

C116

1

+

C115

2

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C120

DDR2_AA11
DDR2_AA7
DDR2_AA6

DDR2_AA0 DDR2_AA8
DDR2_AA4
DDR2_AA2
DDR2_ABA1

DDR2_ARAS#
DDR2_AA13
DDR2_ODT0
DDR2_CS0#

1

1

2

2

C122

C121

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

5

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C130

4

0.1U_0402_16V4Z

1

2

C131

C132

Layout Note:
Place these resistor
closely JP2,all
trace length<750 mil

3

http://hobi-elektronika.net

Top view

DDR2_DQ1
DDR2_DQ5

DDR2_DQS#0
DDR2_DQS0

DDR2_DQ4

12

39 40

41 42

199 200

DDR2_CKE0<8>

DDR2_ABA2<9>

RVS TYPE

DDR2_ABA0<9>
DDR2_AWE#<9>

DDR2_ACAS#<9>

DDR2_CS1#<8>
DDR2_ODT1<8>

ICH_SMBDATA<13,18,31>
ICH_SMBCLK<13,18,31>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR2_DQ7
DDR2_DQ12

DDR2_DQ8
DDR2_DQS#1

DDR2_DQS1
DDR2_DQ10

DDR2_DQ14

DDR2_DQ20
DDR2_DQ21

DDR2_DQS#2
DDR2_DQS2

DDR2_DQ18
DDR2_DQ19

DDR2_DQ26
DDR2_DQ24

DDR2_DM3

DDR2_DQ27
DDR2_DQ31

DDR2_CKE0

DDR2_ABA2
DDR2_AA12

DDR2_AA9
DDR2_AA8

DDR2_AA5
DDR2_AA3
DDR2_AA1

DDR2_AA10
DDR2_ABA0
DDR2_AWE#

DDR2_ACAS#

DDR2_ODT1
DDR2_DQ37

DDR2_DQ32
DDR2_DQS#4

DDR2_DQS4
DDR2_DQ39

DDR2_DQ38
DDR2_DQ41

DDR2_DQ40
DDR2_DM5
DDR2_DQ42

DDR2_DQ46
DDR2_DQ48

DDR2_DQ52

DDR2_DQS#6
DDR2_DQS6

DDR2_DQ50
DDR2_DQ51

DDR2_DQ60
DDR2_DQ56

DDR2_DM7
DDR2_DQ63

DDR2_DQ58
ICH_SMBDATA

ICH_SMBCLK

+3VS

C133

0.1U_0402_16V4Z

+1.8V

1

2

JP2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2R-TR

SO-DIMM0
REVERSE

2

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

1

2

12

R77
10K_0402_5%

1

DDR2_VREF <8>

1

C107

0.1U_0402_16V4Z

2

1

X5.0

of

12 48Friday, June 17, 2005

+1.8V

DDR2_VREF

2

DDR2_DQ0

4

DDR2_DQ6

6
8

DDR2_DM0

10
12

DDR2_DQ2

14

DDR2_DQ3

16
18

DDR2_DQ13

20

DDR2_DQ9

22
24

DDR2_DM1

26
28

DDR2_CLK0

30

DDR2_CLK0#

32
34

DDR2_DQ15

36

DDR2_DQ11

38
40

42

DDR2_DQ23

44

DDR2_DQ17

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

DDR2_DM2

52
54

DDR2_DQ16

56

DDR2_DQ22

58
60

DDR2_DQ28

62

DDR2_DQ29

64
66

DDR2_DQS#3

68

DDR2_DQS3

70
72

DDR2_DQ25

74

DDR2_DQ30

76
78

DDR2_CKE1

80
82
84
86
88

DDR2_AA11

90

DDR2_AA7

92

DDR2_AA6

94
96

DDR2_AA4

98

DDR2_AA2

100

DDR2_AA0

102
104

DDR2_ABA1

106

DDR2_ARAS#

108

DDR2_CS0#

110
112

DDR2_ODT0

114

DDR2_AA13DDR2_CS1#

116
118
120
122

DDR2_DQ36

124

DDR2_DQ33

126
128

DDR2_DM4

130
132

DDR2_DQ35

134

DDR2_DQ34

136
138

DDR2_DQ45

140

DDR2_DQ44

142
144

DDR2_DQS#5

146

DDR2_DQS5

148
150

DDR2_DQ47

152

DDR2_DQ43

154
156

DDR2_DQ49

158

DDR2_DQ53

160
162

DDR2_CLK1

164

DDR2_CLK1#

166
168

DDR2_DM6

170
172

DDR2_DQ54

174

DDR2_DQ55

176
178

DDR2_DQ61

180

DDR2_DQ57

182
184

DDR2_DQS#7

186

DDR2_DQS7

188
190

DDR2_DQ62

192

DDR2_DQ59

194
196
198
200

R76
10K_0402_5%

1 2

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

C106

2.2U_0805_16V4Z

DDR2_CLK0 <8>
DDR2_CLK0# <8>

DDR2_CKE1 <8>

DDR2_ABA1 <9>
DDR2_ARAS# <9>
DDR2_CS0# <8>

DDR2_ODT0 <8>

DDR2_CLK1 <8>
DDR2_CLK1# <8>

DDR2-SODIMM0

Bandera-EAX00-LA2581

5

CLKSEL1CLKSEL0

FS_C FS_B FS_A

101

D D

CPU_BSEL0<6>

CPU_BSEL1<6>

C C

Use 12.1ohm+/- 1%
series resistor if the

+3VS BCLK

R346

0_0402_5%

CLKSEL0

12

R345

0_0402_5%

CLKSEL1

12

100X4=400

+VCCP

R78

@

1K_0402_5%

1 2

R171 1K_0402_5%

R347

@

0_0402_5%

1 2

+VCCP

R307
1K_0402_5%

1 2

R306 1K_0402_5%
R79

@

0_0402_5%

1 2

12

MCH_CLKSEL0 <8>

@

12

MCH_CLKSEL1 <8>

33P_0402_50V8J

33P_0402_50V8J

CLK_48M_ICH<18>

clock signal is shared
bewteen two devices.

SS frequency selection

96*_100MSEL

LOW
HIGH

B B

A A

96_100MSST/C

+3VS

R117
10K_0402_5%

1 2

96*_100MSEL

R123
10K_0402_5%

1 2

5

96 MHZ
100 MHZ

@

2N7002_SOT23

@

CLKEN_R#

13

D

Q17

VRMPWRGD

2

G

S

CLK_PCI_SD<21>
CLK_PCI_MINI<22>
CLK_PCI_TPM<27>
CLK_PCI_SIO<30>
CLK_PCI_LAN<23>
CLK_PCI_ICH<16>

CLK_PCI_EC<28>

VRMPWRGD <8,18,28>

+3VS

12

12

0.1U_0402_16V4Z

C148

12

C149

12

+3VS

+3VS

R217
10K_0402_5%

PCICLK2

R209

@

10K_0402_5%

4

+3VS

1 2

CHB2012U121_0805

1

C139

2

1 2

CHB2012U121_0805

Place crystal within
500 mils of CK410M

12

CLK_48M_ICH

CLK_PCI_SD
CLK_PCI_MINI
CLK_PCI_TPM
CLK_PCI_SIO
CLK_PCI_LAN
CLK_PCI_ICH

CLK_PCI_EC

4

CK_XTAL_IN

Y1

14.31818MHZ_20P_6X1430004201

R85 10K_0402_5%
R89 33_0402_5%

R185 12_0402_5%
R94 12_0402_5%
R98 33_0402_5%
R101 33_0402_5%
R104 33_0402_5%
R106 33_0402_5%

1 2

R110 10K_0402_5%
R109 33_0402_5%

ICH_SMBCLK<12,18,31>

ICH_SMBDATA<12,18,31>

1 2

R112 475_0402_1%

3

http://hobi-elektronika.net

L10

CK_VDD_MAIN2

L11

12
12

12
12
12
12
12
12

12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FS_A
CLKSEL0

CLKSEL1

PCICLK5
PCICLK4
PCICLK3
PCICLK2
96*_100MSEL

PCICLKF0
ICH_SMBCLK

ICH_SMBDATA

CLKIREF

Width=40mils

C85
10U_0805_6.3V6M

1

C140
1U_0603_10V4Z

2

Width=40mils

C86
10U_0805_6.3V6M

U40

21

VDDSRC_0

28

VDDSRC_1

34

VDDSRC_2

1

VDDPCI_0

7

VDDPCI_1

42

VDDCPU

48

VDDREF

11

VDD48

50

XIN

49

XOUT

12

FS_A/USB_48MHz

53

FS_C/TEST_SEL/REF1

16

FS_B/TEST_MODE

5

PCICLK5

4

PCICLK4

3

PCICLK3

56

PCICLK2/SEL_CLKREQ

9

PCICLK_F1/96*_100MSEL

8

PCICLK_F0/ITP_EN

46

SCLK

47

SDATA

39

IREF

13

GND_0

29

GND_1

2

GND_2

45

GND_3

51

GND_4

6

GND_5

IDTCV140PAG_TSSOP56

3

1

C135

0.047U_0402_16V4Z

2

1

C141

0.047U_0402_16V4Z

2

1

C145

0.047U_0402_16V4Z

2

CPUCLKT2_ITP/SRCCLKT_7

CPUCLKC2_ITP/SRCCLKC_7

96_100MSST/SRCCLKT0

96_100MSSC/SRCCLKC0

1

C136

0.047U_0402_16V4Z

2

1

C142

0.047U_0402_16V4Z

2

1

C146

0.047U_0402_16V4Z

2

VDDA
GNDA

PCI/SRC_STOP#

CPU_STOP#

CPUCLKT1
CPUCLKC1

CPUCLKT0
CPUCLKC0

SRCCLKT6/CLKREQA#

SRCCLKC6/CLKREQB#

SRCCLKT5
SRCCLKC5

SRCCLKT4_SATA
SRCCLKC4_SATA

SRCCLKT3

SRCCLKC3

SRCCLKT2

SRCCLKC2

SRCCLKT1

SRCCLKC1

DOTT_96MHz
DOTC_96MHz

VTT_PWRGD#/PD

REF0/FS_D

1

C137

0.047U_0402_16V4Z

2

1

C143

0.047U_0402_16V4Z

2

1

C147

0.047U_0402_16V4Z

2

37
38

PM_STP_PCI#

55

PM_STP_CPU#

54

CK_CPU2 CK_ITP

41

CK_CPU2#

40

CK_CPU0CK_XTAL_OUT

44

CK_CPU0#

43

CK_CPU1

36

CK_CPU1#

35

SRC6

33

SRC6#

32

SRC5

31

SRC5#

30

SRC4

26

SRC4#

27

24
25

SSCLK

22

SSCLK#

23

SRC1

19

SRC1#

20

SRC0

17

SRC0#

18

DOT96

14
15

CLKEN_R#

10

REFOUT CLK_14M_SIO

52

2

1

C138

0.047U_0402_16V4Z

2

Model

Signal

IDT CV140

SLG84443

Comments

1 2

R92 33_0402_5%

1 2

R95 33_0402_5%

1 2

R84 33_0402_5%

1 2

R88 33_0402_5%

1 2

R80 33_0402_5%

1 2

R82 33_0402_5%

1 2

R216 10K_0402_5%@

1 2

R208 0_0402_5%

1 2

R389 0_0402_5%@

1 2

R405 10K_0402_5%

1 2

R99 33_0402_5%

1 2

R102 33_0402_5%

1 2

R168 33_0402_5%

1 2

R163 33_0402_5%

1 2

R118 33_0402_5%

1 2

R120 33_0402_5%

1 2

R105 33_0402_5%

1 2

R107 33_0402_5%

1 2

R113 33_0402_5%

1 2

R115 33_0402_5%

1 2

R122 33_0402_5%

1 2

R124 33_0402_5%

1 2

R127 10K_0402_5%

1 2

R350 0_0402_5%

1 2

R128 12_0402_5%

1 2

R129 12_0402_5%

1 2

R91 12_0402_5%

2

1

CLKREQB#

CLKREQA#

SRC4/4#
NewCard

0

1
0
0
1
1

Main source IDT CV140 SRC1~7/1~7# can control by
CLKREQA# or CLKREQB#, in MP use CLKREQA# control;
2nd source Silego SLG84443 SRC1,3,4/1#,3#,4# can control
by CLKREQB# and SRC2,5/2#,5# can control by CLKREQA#

CK_ITP# CK_ITP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLKREQA#
CLKREQB#

CLK_PCIE_P0
CLK_PCIE_N0

CLK_PCIE_P2
CLK_PCIE_N2

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_ICH
CLK_PCIE_ICH#

DREF_SSCLK
DREF_SSCLK#

DREFCLK
DREFCLK#DOT96#

+3VS

CLKEN#

CLK_14M_CODEC
CLK_14M_ICH

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

0

1

0

1

PM_STP_PCI# <18>
PM_STP_CPU# <18>

CK_ITP <5>
CK_ITP# <5>

CLK_CPU_BCLK <5>
CLK_CPU_BCLK# <5>

CLK_MCH_BCLK <8>
CLK_MCH_BCLK# <8>

+3VS

CLKREQA# <15,31>
CLKREQB# <31>

+3VS

CLK_PCIE_P0 <31>
CLK_PCIE_N0 <31>

CLK_PCIE_P2 <31>
CLK_PCIE_N2 <31>

CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>

CLK_PCIE_ICH <18>
CLK_PCIE_ICH# <18>

DREF_SSCLK <8>
DREF_SSCLK# <8>

DREFCLK <8>
DREFCLK# <8>

CLKEN# <39>
CLK_14M_SIO <30>
CLK_14M_CODEC <25>

CLK_14M_ICH <18>

CK_ITP

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLKREQA#

SRC6#

CLK_PCIE_P0
CLK_PCIE_N0

CLK_PCIE_P2
CLK_PCIE_N2

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_ICH
CLK_PCIE_ICH#

DREF_SSCLK
DREF_SSCLK#

DREFCLK
DREFCLK#

12

Clock generator-CV140

Bandera-EAX00-LA2581

1

R218

@

0_0402_5%

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

SRC5/5#
GigaLAN

12

R9349.9_0402_1%

12

R9749.9_0402_1%

12

R8649.9_0402_1%

12

R9049.9_0402_1%

12

R8149.9_0402_1%

12

R8349.9_0402_1%

R10049.9_0402_1%
R10349.9_0402_1%

R18049.9_0402_1%
R20749.9_0402_1%

R11449.9_0402_1%
R11649.9_0402_1%

R10849.9_0402_1%
R11149.9_0402_1%

R11949.9_0402_1%
R12149.9_0402_1%

R12549.9_0402_1%
R12649.9_0402_1%

of

13 48Friday, June 17, 2005

X5.0

5

4

3

2

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http://hobi-elektronika.net

PID1 PID0 Vendor

PDCT
DTRB#
RTSB#

DIG_TXD_R
DIG_RXD_T

DIGISUSP
DIGRST#

PID0
PID1

TXACLK+
TXACLK-

TXA2+
TXA2-

TXA1+
TXA1-

TXA0+
TXA0-

AU-B084SN02

JP32

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31
32
33
34

IPEX_20143-030E

Top view

00

PDCT<28>
DTRB#<30>
RTSB#<30>

DIGISUSP<28>
DIGRST#<28>

PID0<18>

PID1<18>
TXACLK+<10>

TXACLK-<10>
TXA2+<10>

TXA2-<10>
TXA1+<10>

TXA1-<10>
TXA0+<10>

TXA0-<10>

001
1
11

AO3402_SOT23

D

1 3

Q7

S

R407

G

2

DIGI_FWE<18>

Digitizer pin CTS Connects to Hostˇs RTS for Plug & Play
Digitizer pin DSR Connects to Hostˇs DTR for Plug & Play

DIGI_FWE DIGI_FWE_C

+3VS

C155

10U_0805_16V3M

EMI request

R352

+LCDVDD

1 2

0_0805_5%

10U_0805_16V3M

C150

1

2

1 2

1

2

+LCD_VDD

@

0_0402_5%

2

C156

0.1U_0402_16V4Z

1

2

C151

0.1U_0402_16V4Z

1

12

R408
0_0402_5%

12

R132
100K_0402_5%

13

Q10
DTC124EK_SOT23

+12VALW

2

G

R231
10K_0402_5%

1 2

PID0
PID1

12

R130
100K_0402_5%

LCDPWR_ENGATE

13

D

Q9

2N7002_SOT23

S

0.1U_0402_16V4Z

D D

R131

470_0402_5%

Q8

2N7002_SOT23

ENVDD

ENVDD<10>

C C

12

13

D

S

2

22K

+3VS

+12VALW+LCDVDD

LCDPWR_ENGATE#

2

G

22K

R228
10K_0402_5%

1 2

C152

1

C179

0.01U_0402_16V7K

2

+3VS

1

1

C153

0.1U_0402_16V4Z

2

2

12

R133
150K_0402_5%

+LCDVDD

B+

12

B B

SIO_TXD<30>

SIO_RXD<30>

SIO_TXD
SIO_RXD

1 2

R334 0_0402_5%

1 2

R335 0_0402_5%

LCD/Inverter temperature monitor

SMB_EC_CK2<5,28>

SMB_EC_DA2<5,28>

A A

SMB_EC_CK2
SMB_EC_DA2

5

U36

4

SCLK

5

SDA

TC74A1-5.0VCT_SOT23-5

SM BUS Address : 1001 001

VDD

GND

3
2
1

NC

DIG_RXD_T
DIG_TXD_R

+5VS

1

2

C113

0.1U_0402_16V4Z

4

+3VS

R285

12

R329

4.7K_0402_5%

D18

BKOFF#<28>

ENABKL<10,28>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RB751V_SOD323

D20

RB751V_SOD323

21

21

3

@

0_0402_5%

1 2

Q16
2N7002_SOT23

D

1 3

G

2

1

C159

0.1U_0402_16V4Z

2

S

100K_0402_5%

1 2

R260

EMI request

DPST2.0

LBKLT_CRTL_PWM<10>

EC_INVT_PWM<28>

+5VS

2

R134
0_0402_5%

1 2

R135
0_0402_5%

1 2

R351
0_0805_5%

1

C157

0.01U_0603_50V4Z

2

@

DAC_BRIG<28>

1

C158

0.1U_0603_25V7K

2

INVT_PWM
DISPOFF#
DAC_BRIG

2

3

D27

PSOT24C_SOT23

1

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

INV_B+

JP4

1
2
3
4
5
6
7
8

MOLEX_53780-0890

LCD Conn/Inverter Conn

Bandera-EAX00-LA2581

1

X5.0

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14 48Friday, June 17, 2005

5

4

3

2

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http://hobi-elektronika.net

+2.5VS

2

3

D D

C162

10P_0402_50V8J

R139

150_0402_5%

1

C163

2

10P_0402_50V8J

L12

1 2

FBM-11-201209-170T (0805)
L13

1 2

FBM-11-201209-170T (0805)
L14

1 2

FBM-11-201209-170T (0805)

1 2

CRT_G_MB

150_0402_5%

R137

1

C161

2

150_0402_5%

1 2

1

2

10P_0402_50V8J

R138

1 2

D3

DAN217_SC59

1

1

C164

2

2

3

DAN217_SC59

1

1

C165

2

18P_0603_50V

D4

2

3

DAN217_SC59

1

1

C166

2

18P_0603_50V

D5

CRTR

CRTG

CRTB

3VDDCDA<10>

3VDDCCL<10>

18P_0603_50V

Notices: C164,C165,C166 change material in MP

C C

+5VS

CRT_HSYNC<10>

B B

CRT_HSYNC

R145

1K_0402_5%

1

5

P

CRT_HSYNCMB

4

OE#

A2Y

U8

G

SN74AHCT1G125GW_SOT353-5

3

5

P

A2Y

G

3

R146

1K_0402_5%

1

CRT_HSYNCDOCK

4

OE#

U9

SN74AHCT1G125GW_SOT353-5

Need tune this value

CRT_HSYNC_MB

12

R1154

39_0402_5%

CRT_HSYNC_DOCK

12

R1155

39_0402_5%

CRT_HSYNC_DOCK <31>

3VDDCDA

3VDDCCL

0.1U_0402_16V4Z

CRT_R<10>
CRT_G<10>
CRT_B<10>

+2.5VS

R141

2.2K_0402_5%

1 2

To DOCK

C168

CRT_R
CRT_G
CRT_B

R136

10K_0402_5%

1

2

16

+3VS

1 2

TOP VIEW

1

5

1617

JP5

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070112FR015S222XU

6
11
7
12
8
13
9
14
10
15

+3VS +5VS CRTVCC

R140

VCC

DA
DB
DC
DD

GND

3VDDCDA_R<31>

3VDDCCL_R<31>

10K_0402_5%

1 2

G

2

Q11

S

2N7002_SOT23

DOCKEN

EN

IN

S1A
S2A
S1B
S2B
S1C
S2C
S1D
S2D

R142

2.2K_0402_5%

1 2

+5VS

1

2

U11

16

4
7
9

12

8

PI5V330Q_QSOP16

13

D

G

S

2N7002_SOT23

15
1

2
3
5
6
11
10
14
13

12

R143

4.7K_0402_5%

3VDDC_GATE_EN

2

Q12

13

D

M_SEN#<18,31>

1: TO DOCK
0: TO MB

CRT_R_DOCK
CRT_G_DOCK
CRT_B_DOCK

12

C230

0.1U_0402_16V4Z

DOCKEN
CRT_R_MB
CRT_G_MB

CRT_B_MB

1.1A_6VDC_FUSE

R144

4.7K_0402_5%

1

2

DOCKEN <28>

F1

R395

1 2

100_0402_1%

CRT_R_DOCK <31>
CRT_G_DOCK <31>
CRT_B_DOCK <31>

RB491D_SOT23

21

0.1U_0402_16V4Z

CRT_M_SEN#M_SEN#

D2

2 1

C160

CRT_M_SEN#
CRTR

3VDDCDA_RCRT_R_MB
CRTG

CRT_HSYNC_MB
CRTB

CRT_VSYNC_MBCRT_B_MB

3VDDCCL_R

100P_0402_50V8J

1

2

C167

17

+5VS

5

CRT_VSYNC

A2Y

A2Y

CRT_VSYNC<10>

A A

R147

1K_0402_5%

1

5

P

CRT_VSYNCMB

4

OE#

U10

G

SN74AHCT1G125GW_SOT353-5

3

5

3

R148

1K_0402_5%

1

P

CRT_VSYNCDOCK

4

OE#

U12

G

SN74AHCT1G125GW_SOT353-5

R1156

39_0402_5%

R1157

39_0402_5%

CRT_VSYNC_MB

12

CRT_VSYNC_DOCK

12

4

+3VS

R399
10K_0402_5%

1 2

Q35

2N7002_SOT23

DOCKEN

CRT_VSYNC_DOCK <31>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

G

CLKREQA#

13

D

S

CLKREQA# <13,31>

2

OUTER Line

17 16

Compal Electronics, Inc.(KunShan)

Title

CRT interface

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

15 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

D D

+3VS

+3VS

+3VS

C C

+3VS

+3VS

+3VS

RP8

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP9

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP10

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP11

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP12

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP13

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

PCI_PIRQF#
PCI_PIRQG#
PCI_DEVSEL#
PCI_PLOCK#

PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_REQ#2
PCI_PIRQH#
PCI_PIRQA#
PCI_PIRQC#

PCI_REQ#1
PCI_IRDY#
PCI_REQ#6
PCI_REQ#3

PCI_PIRQB#
PCI_PIRQD#
PCI_REQ#0
PCI_SERR#

PCI_REQ#4
PCI_REQ#5
PCI_PERR#
PCI_PIRQE#

PCI_AD[0..31]<21,22,23>

PCI_FRAME#<21,22,23>

PCI_PIRQA#<21>

PCI_PIRQB#<23>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_FRAME#

PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U13B

E2

AD[0]

E5

AD[1]

C2

AD[2]

F5

AD[3]

F3

AD[4]

E9

AD[5]

F2

AD[6]

D6

AD[7]

E6

AD[8]

D3

AD[9]

A2

AD[10]

D2

AD[11]

D5

AD[12]

H3

AD[13]

B4

AD[14]

J5

AD[15]

K2

AD[16]

K5

AD[17]

D4

AD[18]

L6

AD[19]

G3

AD[20]

H4

AD[21]

H2

AD[22]

H5

AD[23]

B3

AD[24]

M6

AD[25]

B2

AD[26]

K6

AD[27]

K3

AD[28]

A5

AD[29]

L1

AD[30]

K4

AD[31]

J3

FRAME#

Interrupt I/F

N2

PIRQ[A]#

L2

PIRQ[B]#

M1

PIRQ[C]#

L3

PIRQ[D]#

AC5

SATA[1]RXN/RSVD[1]

AD5

SATA[1]RXP/RSVD[2]

AF4

SATA[1]TXN/RSVD[3]

AG4

SATA[1]TXP/RSVD[4]

AC9

SATA[3]RXN/RSVD[5]

AD9

SATA[3]RXP/RSVD[6]

AF8

SATA[3]TXN/RSVD[7]

AG8

SATA[3]TXP/RSVD[8]

U3

TP[3]/RSVD[9]

ICH6_BGA609

PCI

REQ[4]#/GPI[40]

GNT[4]#/GPO[48]

REQ[5]#/GPI[1]

GNT[5]#/GPO[17]

REQ[6]#/GPI[0]

GNT[6]#/GPO[16]

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]

PIRQ[G]#GPI[4]

PIRQ[H]#/GPI[5]

RESERVED

REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#

C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#
TRDY#

PLTRST#

PCICLK

PME#

PCI_REQ#0

L5
C1

PCI_REQ#1

B5

PCI_GNT#1

B6

PCI_REQ#2

M5

PCI_GNT#2

F1

PCI_REQ#3

B8

PCI_GNT#3

C8

PCI_REQ#4

F7
E7

PCI_REQ#5

E8
F6

PCI_REQ#6

B7
D8

PCI_C/BE#0

J6

PCI_C/BE#1

H6

PCI_C/BE#2

G4

PCI_C/BE#3

G2

PCI_IRDY#

A3

PCI_PAR

E1

ICH_PCIRST#

R2

PCI_DEVSEL#

C3

PCI_PERR#

E3

PCI_PLOCK#

C5

PCI_SERR#

G5

PCI_STOP#

J1

PCI_TRDY#

J2

PLTRST#

R5

CLK_PCI_ICH

G6

PCI_PME#

P6

PCI_PIRQE#PCI_PIRQA#

D9

PCI_PIRQF#

C7

PCI_PIRQG#

C6

PCI_PIRQH#

M3

PCI_REQ#1 <22>
PCI_GNT#1 <22>
PCI_REQ#2 <21>
PCI_GNT#2 <21>
PCI_REQ#3 <23>
PCI_GNT#3 <23>

PCI_C/BE#0 <21,22,23>
PCI_C/BE#1 <21,22,23>
PCI_C/BE#2 <21,22,23>
PCI_C/BE#3 <21,22,23>

PCI_IRDY# <21,22,23>
PCI_PAR <21,22,23>

PCI_DEVSEL# <21,22,23>
PCI_PERR# <21,22,23>

PCI_SERR# <21,22,23>
PCI_STOP# <21,22,23>
PCI_TRDY# <21,22,23>

CLK_PCI_ICH <13>
PCI_PME# <29>

PCI_PIRQF# <23>
PCI_PIRQG# <22>
PCI_PIRQH# <22>

B2 Stepping

1

IN1

2

IN2

0_0402_5%

+3VS

R151

5

P

G

3

1

C170

@

0.1U_0402_16V4Z

2

U14

@

SN74AHC1G08DCKR_SC70

4

O

12

4

PCIRST# <21,22,23>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

1

C171

0.1U_0402_16V4Z

2

U15

5

PLTRST#PCIRST#

1
2

P

IN1
IN2

G

3

R150
0_0402_5%

3

SN74AHC1G08DCKR_SC70

PLT_RST#

4

O

@

12

PLT_RST# <8,20,27,28,30>

CLK_PCI_ICH

2

R149

@

10_0402_5%

1 2
1

C169

@

10P_0402_50V8J

2

Compal Electronics, Inc.(KunShan)

Title

PCI/SATA interface

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

16 48Friday, June 17, 2005

X5.0

B B

ICH_PCIRST#

A A

5

5

4

3

2

1

http://hobi-elektronika.net

D D

32.768KHZ_12.5P_1TJS125DJ2A073

+RTCVCC

CHGRTC

12

D19

2

3

BAS40-04_SOT23

1

BATT1

45@

1 2

ML1220T13RE

AC97_BITCLK<25>

AC97_SYNC<25>
AC97_RST#<25>

AC97_SDIN0<25>

AC97_SDOUT<25>

+RTCVCC

R69
1K_0402_5%

2

C315

0.1U_0402_16V4Z

C C

B B

1

C172

15P_0402_50V8J

12

Y2

2

IN

NC

3

OUT

NC

C173

15P_0402_50V8J

12

1 2

R153 20K_0402_5%

1 2

R154 1M_0402_1%

CMOS_CLR1

@

SHORT PADS

INTVRMEN: Enables
integrated VccSus1_5 VRM
when sampled high.

C175
10P_0402_50V8J

1 2

1 2

R164 33_0402_5%

1 2

R165 33_0402_5%

1 2

R169 33_0402_5%

1 2

R170 33_0402_5%

PDIORDY<20>
IDEIRQ<20>
PDDACK#<20>
PDIOW#<20>
PDIOR#<20>

ICH_RTCX1

1
4

ICH_RTCX2

1U_0402_6.3V4Z

1 2

<>

R162

@

@

10_0402_5%

AC97_BITCLK
AC97_SYNC_R

AC97_RST_R#
AC97_SDIN0_R

AC97_SDOUT_R

PDIORDY
IDEIRQ
PDDACK#
PDIOW#
PDIOR#

12

R152

10M_0402_5%

ICH_RTCRST#
INTRUDER#

1

C174

2

12

AC19

AG11
AF11

AF16
AB16
AB15
AC14
AE16

AA2
AA3

AA5

D12
B12
D11

B11
E12

E11
C13

C12
C11
E13

C10

A10

B10

AE3
AD3
AG2
AF2

AD7
AC7
AF6
AG6

AC2
AC1

Y1
Y2

F13
F12

B9

F11
F10

C9

U13A

RTCX1
RTCX2

RTCRST#
INTRUDER#

INTVRMEN

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LANRXD[0]

LANRXD[1]
LANRXD[2]

LANTXD[0]
LANTXD[1]
LANTXD[2]

ACZ_BIT_CLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN[0]

ACZ_SDIN[1]
ACZ_SDIN[2]

ACZ_SDO

SATALED#

SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP

SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#
SATARBIAS

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH6_BGA609

RTC

LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]

LPC

LDRQ[0]#

LDRQ[1]#/GPI[41]
LFRAME#/FWH[4]

A20GATE

A20M#

LAN

CPUSLP#

CPU

DPRSLP#/TP[4]

DPSLP#/TP[2]

FERR#

CPUPWRGD/GPO[49]

IGNNE#

INIT3_3V#

INIT#

INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

DA[0]
DA[1]
DA[2]

DCS1#
DCS3#

SATAAC-97/AZALIA

DD[0]
DD[1]
DD[2]
DD[3]

PIDE

DD[4]
DD[5]
DD[6]
DD[7]
DD[8]

DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]

DDREQ

LPC_AD0

P2

LPC_AD1

N3

LPC_AD2

N5

LPC_AD3

N4

LPC_DRQ#0

N6
P4

LPC_FRAME#

P3

GATEA20

AF22

H_A20M#

AF23

CPUSLP#

AE27
AE24

H_DPSLP#

AD27

FERR_R# H_FERR#

AF24

H_PWRGOOD

AG25

H_IGNNE#

AG26
AE22

H_INIT#

AF27

H_INTR

AG24

KBRST#

AD23

H_NMI

AF25

NMI

AG27
AE26
AE23

AC16
AB17
AC17

AD16
AE17

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

AB14

H_SMI#
H_STPCLK#
THRMTRIP#

PDA0
PDA1
PDA2

PDCS1#
PDCS3#

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDDREQ

LPC_AD0 <27,28,30>
LPC_AD1 <27,28,30>
LPC_AD2 <27,28,30>
LPC_AD3 <27,28,30>

LPC_DRQ#0 <30>

LPC_FRAME# <27,28,30>

GATEA20 <28>
H_A20M# <5>

Ra

R158 0_0402_5%@
R159 0_0402_5%

R160 56_0402_5%

12

Rb

12

Rc

1 2

H_PWRGOOD <5>
H_IGNNE# <5>
H_INIT# <5>

H_INTR <5>

KBRST# <28>
H_NMI <5>

H_SMI# <5>
H_STPCLK# <5>

PDA0 <20>
PDA1 <20>
PDA2 <20>

PDCS1# <20>
PDCS3# <20>

PDDREQ <20>

H_CPUSLP#
H_DPRSTP#DPRSTP#

PDD[0..15] <20>

H_CPUSLP# <5,8>
H_DPRSTP# <5>

H_DPSLP# <5,39>
H_FERR# <5>

+VCCP

+VCCP

R161

@

330_0402_5%

1 2

1 2

C176
1U_0603_10V6K

1 2

R166
75_0402_1%

@

H_FERR#

H_DPRSTP#

C

2

B

E

+VCCP

12

R155
56_0402_5%

1

Q13

@

2SC2411K_SC59

3

R167

56_0402_5%

H_THERMTRIP#

THRMTRIP#

12

+VCCP

12

R156

@

56_0402_5%

MAINPWRON <6,35,36>

H_THERMTRIP# <5,8>

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

ICH6-RTC/AC97/SATA/PIDE/CPU Sideband

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

17 48Friday, June 17, 2005

X5.0

5

4

3

2

1

+3VALW

R172

R173

1 2

1 2

10K_0402_5%

D D

+3VS

+3VS

12

12

R176

R175

2.2K_0402_5%

2.2K_0402_5%

ICH_SMBDATA<12,13,31>

ICH_SMBCLK<12,13,31>

C C

ICH_SMBDATA

ICH_SMBCLK

GPIO[25]: 0= Enable internal 2.5V

G

2

S

2N7002_SOT23

Q14

2N7002_SOT23

VRM. 1= Disable internal 2.5V VRM,
Internal PU with 20K.

+3VALW

LINKALERT#

R17910K_0402_5%

1 2
1 2
1 2

B B

VRMPWRGD_P<39>

+3VS

GPI[7] are in the Main Power Well (Vcc3_3).
Pull-ups must use the VCC3_3 plane.

A A

VRMPWRGD_P VRMPWRGD

+5VS

1 2
1 2
1 2
1 2
1 2

ITP_DBRESET#

R18210K_0402_5%

PM_BATLOW#

R1848.2K_0402_5%

Q40

1 3

BSS138_SOT23

2

PM_CLKRUN#

R1868.2K_0402_5%

SB_THRM#

R18710K_0402_5%

MCH_SYNC#

R18810K_0402_5%

USB2P0_SMI#

R18910K_0402_5%

SIRQ

R19010K_0402_5%

WL_EN

R3671K_0402_5%

12

10K_0402_5%

ICH_SMLINK0
ICH_SMLINK1

+3VALW

12

12

R178

R177

2.2K_0402_5%

2.2K_0402_5%

13

D

VRMPWRGD <8,13,28>

SMBDATA

SMBCLK

13

D

G

2

Q15

S

ICH_SPKR<25>
SUS_STAT#<27,30>
ITP_DBRESET#<5>
PM_BMBUSY#<8>
M_SEN#<15,31>

EC_SMI#<28>
EC_SCI#<28>

EC_SWI#<28>
PM_STP_PCI#<13>
BT_PWR_ON<22>
PM_STP_CPU#<13>

WL_EN<22>
IDERST_HD#<20>

DIGI_FWE<14>

EC_FLASH#<29>

PM_CLKRUN#<21,22,23,27,30>

PID0<14>
PID1<14>

LAN_WAKE<31>
SIRQ<27,28,30>

EC_THRM#<28>

CLK_14M_ICH<13>
CLK_48M_ICH<13>

EC_SLP_S3#<28>
EC_SLP_S4#<28>
EC_SLP_S5#<28>

ICH_PWRGD<28,29>
PM_DPRSLPVR<39>
PM_BATLOW#<28>
EC_PBTNOUT#<28>
LAN_RST#<28>
EC_RSMRST#<28>

Affected Stepping: A0,A1,B0,B1,B2

http://hobi-elektronika.net

+3VALW

12

R174

+3VALW

TP2
PAD

10K_0402_5%

R197 0_0402_5%@

EC_THRM#

ICH_RI#

RP14 100_1206_8P4R_5%

1 8
2 7
3 6
4 5

SMBCLK
SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
MCH_SYNC#
ICH_SPKR

SUS_STAT#
ITP_DBRESET#
PM_BMBUSY#
M_SEN#

EC_SMI#

EC_SCI#
USB2P0_SMI#

EC_SWI#
PM_STP_PCI#
BT_PWR_ON
PM_STP_CPU#

WL_EN
IDERST_HD#

DIGI_FWE

1 2

EC_FLASH#
PM_CLKRUN#

PID0

PID1

R183 1K_0402_5%

12

SIRQ

D8 RB751V_SOD323

VRMPWRGD
CLK_14M_ICH
CLK_48M_ICH
SUSCLK
EC_SLP_S3#

EC_SLP_S4#
EC_SLP_S5#

ICH_PWRGD
PM_DPRSLPVR
PM_BATLOW#
EC_PBTNOUT#
LAN_RST#
EC_RSMRST#

SB_THRM#

21

1 2

R353 100K_0402_1%

R192 10K_0402_5%

12

T2

AF17
AE18
AF18
AG18

Y4

W5

Y5

W4

U6

AG21

F8

W3

U2
AD19
AE19

R1

W6

M2

R6
AC21
AB21
AD22

AD20
AD21

V3
P5

R3

T3
AF19
AF20
AC18

U5
AB20
AC20
AF21

E10
A27

V6
T4

T5
T6

AA1

AE20

V2

U1

V5
Y3

12

R193 10K_0402_5%

U13C

RI#
SATA[0]GP/GPI[26]

SATA[1]GP/GPI[29]
SATA[2]GP/GPI[30]
SATA[3]GP/GPI[31]

SMBCLK
SMBDATA
LINKALERT#
SMLINK[0]
SMLINK[1]
MCH_SYNC#
SPKR

SUS_STAT#/LPCPD#
SYS_RESET#
BM_BUSY#/GPI[6]
GPI[7]

GPI[8]
SMBALERT#/GPI[11]
GPI[12]

GPI[13]
STP_PCI#/GPO[18]
GPO[19]
STP_CPU#/GPO[20]

GPO[21]
GPO[23]

GPIO[24]
GPIO[25]

GPIO[27]
GPIO[28]
CLKRUN#/GPIO[32]
GPIO[33]
GPIO[34]

WAKE#
SERIRQ
THRM#
VRMPWRGD
CLK14
CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK
DPRSLPVR/TP[1]
BATLOW#/TP[0]
PWRBTN#
LAN_RST#
RSMRST#

ICH6_BGA609

PERn[1]
PERp[1]
PETn[1]
PETp[1]

PERn[2]
PERp[2]
PETn[2]
PETp[2]

PERn[3]
PERp[3]
PETn[3]
PETp[3]

GPIO

PERn[4]
PERp[4]
PETn[4]

PCI-EXPRESSDIRECT MEDIA INTERFACE

PETp[4]

DMI[0]RXN
DMI[0]RXP

DMI[0]TXN
DMI[0]TXP

DMI[1]RXN
DMI[1]RXP

DMI[1]TXN
DMI[1]TXP

DMI[2]RXN
DMI[2]RXP

DMI[2]TXN
DMI[2]TXP

DMI[3]RXN
DMI[3]RXP

DMI[3]TXN
DMI[3]TXP

DMI_CLKN
DMI_CLKP

DMI_ZCOMP
DMI_IRCOMP
OC[4]#/GPI[9]

OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]

OC[0]#
OC[1]#
OC[2]#
OC[3]#

USBP[0]N
USBP[0]P
USBP[1]N

CLOCK

USBP[1]P
USBP[2]N
USBP[2]P
USBP[3]N
USBP[3]P

USB

USBP[4]N
USBP[4]P
USBP[5]N
USBP[5]P
USBP[6]N
USBP[6]P
USBP[7]N

POWER MGT

USBP[7]P

USBRBIAS#

USBRBIAS

H25
H24
G27
G26

K25
K24
J27
J26

M25
M24
L27
L26

P24
P23
N27
N26

T25
T24
R27
R26

V25
V24
U27
U26

Y25
Y24
W27
W26

AB24
AB23
AA27
AA26

AD25
AC25

F24
F23
C23

D23
C25
C24

C27
B27
B26
C26

C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14

A22
B22

PCIE_RXN0
PCIE_RXP0
PCIE_TX0­PCIE_TX0+

C178 0.1U_0402_16V4Z

PCIE_RXN2
PCIE_RXP2
PCIE_TX2­PCIE_TX2+

C227 0.1U_0402_16V4Z

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB_OC#4

USB_OC#5
USB_OC#6
USB_OC#7

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3

USBP0­USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+

USBP6­USBP6+
USBP7­USBP7+

USBRBIAS

1 2

1 2

R181

24.9_0402_1%

1 2

1 2

R191

22.6_0402_1%

12

C177 0.1U_0402_16V4Z

12

C228 0.1U_0402_16V4Z

DMI_RXN0 <8>
DMI_RXP0 <8>
DMI_TXN0 <8>
DMI_TXP0 <8>

DMI_RXN1 <8>
DMI_RXP1 <8>
DMI_TXN1 <8>
DMI_TXP1 <8>

CLK_PCIE_ICH# <13>
CLK_PCIE_ICH <13>

USB_OC#4 <31>
USB_OC#6 <31>

USB_OC#7 <31>
USB_OC#0 <27>

USB_OC#1 <27>

USBP0- <27>
USBP0+ <27>
USBP1- <27>
USBP1+ <27>
USBP2- <29>
USBP2+ <29>
USBP3- <22>
USBP3+ <22>
USBP4- <31>
USBP4+ <31>

USBP6- <31>
USBP6+ <31>
USBP7- <31>
USBP7+ <31>

+1.5VS

PCIE_RXN0 <31>
PCIE_RXP0 <31>
PCIE_TXN0 <31>
PCIE_TXP0 <31>

PCIE_RXN2 <31>
PCIE_RXP2 <31>
PCIE_TXN2 <31>
PCIE_TXP2 <31>

CLK_14M_ICH

12

R194
10_0402_5%

1

C181

4.7P_0402_50V8C

2

USB_OC#2
USB_OC#1
USB_OC#3
USB_OC#0

USB_OC#4
USB_OC#6
USB_OC#7
USB_OC#5

@

@

RP15

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP16

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

Place closely pin A27Place closely pin E10

12

1

2

CLK_48M_ICH

R195

@

10_0402_5%

C182

@

4.7P_0402_50V8C

+3VALW

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

ICH6-DMI/PCIE/USB/PM/CLK/GPIO

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

18 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

Near PIN F27(C277),

2

C189

1

220U_D2_4VM

P27(C278), AB27(C279)

2

2

C190

C191

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

L15

BLM21PG600SN1D_0805

1 2

+1.5VS

D D

R67

20_1206_5%

12

+5VS

12

R62
20_1206_5%

ICH_V5REF_RUN

+3VS

21

D6
RB751V_SOD323

2

C192
1U_0603_10V4Z

1

C183

2

C193

0.1U_0402_16V4Z

1

1

+

2

Intel recomend 0.68W rating.

+5VALW

12

12

C C

B B

R72

20_1206_5%

+1.5VS

R198

0.5_0603_1%

1 2

1

C208
10U_0805_6.3V6M

2

R71
20_1206_5%

ICH_V5REF_SUS

+3VALW

21

2

1

L16

BLM11A601S_0603

1 2

C209

D7
RB751V_SOD323

C199
1U_0603_10V4Z

2

1

C210

1

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

Near PIN
AC27

2

C200

0.1U_0402_16V4Z

1

+1.5VS_VCCDMIPLL

+3VS

Near PIN
E26, E27

2

C212

1

0.1U_0402_16V4Z

+1.5VS

Near PIN AG5

+1.5VS

Near PIN AG9

C213

0.1U_0402_16V4Z

+3VALW

+3VALW

+1.5VS

2

1

2

C203

1

2

C207

1

2

C214

0.1U_0402_16V4Z

1

2

C216

0.1U_0402_16V4Z

1

2

C221

C220

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS+3VS

2

1

0.1U_0402_16V4Z

U13E

AA22

VCC1_5[1]

AA23

VCC1_5[2]

AA24

VCC1_5[3]

AA25

VCC1_5[4]

AB25

VCC1_5[5]

AB26

VCC1_5[6]

AB27

VCC1_5[7]

F25

VCC1_5[8]

F26

VCC1_5[9]

F27

VCC1_5[10]

G22

VCC1_5[11]

G23

VCC1_5[12]

G24

VCC1_5[13]

G25

VCC1_5[14]

H21

VCC1_5[15]

H22

VCC1_5[16]

J21

VCC1_5[17]

J22

VCC1_5[18]

K21

VCC1_5[19]

K22

VCC1_5[20]

L21

VCC1_5[21]

L22

VCC1_5[22]

M21

VCC1_5[23]

M22

VCC1_5[24]

N21

VCC1_5[25]

N22

VCC1_5[26]

N23

VCC1_5[27]

N24

VCC1_5[28]

N25

VCC1_5[29]

P21

VCC1_5[30]

P25

VCC1_5[31]

P26

VCC1_5[32]

P27

VCC1_5[33]

R21

VCC1_5[34]

R22

VCC1_5[35]

T21

VCC1_5[36]

T22

VCC1_5[37]

U21

VCC1_5[38]

U22

VCC1_5[39]

V21

VCC1_5[40]

V22

VCC1_5[41]

W21

VCC1_5[42]

W22

VCC1_5[43]

Y21

VCC1_5[44]

Y22

VCC1_5[45]

AA6

VCC1_5[46]

AB4

VCC1_5[47]

AB5

VCC1_5[48]

AB6

VCC1_5[49]

AC4

VCC1_5[50]

AD4

VCC1_5[51]

AE4

VCC1_5[52]

AE5

VCC1_5[53]

AF5

VCC1_5[54]

AG5

VCC1_5[55]

AA7

VCC1_5[56]

AA8

VCC1_5[57]

AA9

VCC1_5[58]

AB8

VCC1_5[59]

AC8

VCC1_5[60]

AD8

VCC1_5[61]

AE8

VCC1_5[62]

AE9

VCC1_5[63]

AF9

VCC1_5[64]

AG9

VCC1_5[65]

AC27

VCCDMIPLL

E26

VCC3_3[1]

AE1

VCCSATAPLL

AG10

VCC3_3[22]

A13

VCCLAN3_3/VCC3_3[1]

F14

VCCLAN3_3/VCC3_3[2]

G13

VCCLAN3_3/VCC3_3[3]

G14

VCCLAN3_3/VCC3_3[4]

A11

VCCSUS3_3[1]

U4

VCCSUS3_3[2]

V1

VCCSUS3_3[3]

V7

VCCSUS3_3[4]

W2

VCCSUS3_3[5]

Y7

VCCSUS3_3[6]

A17

VCCSUS3_3[7]

B17

VCCSUS3_3[8]

C17

VCCSUS3_3[9]

F18

VCCSUS3_3[10]

G17

VCCSUS3_3[11]

G18

VCCSUS3_3[12]

ICH6_BGA609

PCIE

SATA

PCI/IDE RBP

VCCLAN1_5/VCC1_5[2]
VCCLAN1_5/VCC1_5[1]

VCC1_5[98]
VCC1_5[97]
VCC1_5[96]
VCC1_5[95]
VCC1_5[94]
VCC1_5[93]
VCC1_5[92]
VCC1_5[91]
VCC1_5[90]
VCC1_5[89]
VCC1_5[88]
VCC1_5[87]
VCC1_5[86]

COREIDE

VCC1_5[85]
VCC1_5[84]
VCC1_5[83]
VCC1_5[82]
VCC1_5[81]
VCC1_5[80]
VCC1_5[79]

VCC3_3[21]
VCC3_3[20]
VCC3_3[19]
VCC3_3[18]
VCC3_3[17]
VCC3_3[16]
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]

VCC3_3[11]
VCC3_3[10]

VCC3_3[9]
VCC3_3[8]
VCC3_3[7]
VCC3_3[6]
VCC3_3[5]
VCC3_3[4]

PCIUSB

VCC3_3[3]
VCC3_3[2]

VCCSUS1_5[3]
VCCSUS1_5[2]

VCCSUS1_5[1]

VCC1_5[78]
VCC1_5[77]
VCC1_5[76]
VCC1_5[75]
VCC1_5[74]
VCC1_5[73]
VCC1_5[72]
VCC1_5[71]
VCC1_5[70]
VCC1_5[69]

USB CORE

VCC1_5[68]
VCC1_5[67]

VCC2_5[4]
VCC2_5[2]

V5REF[2]
V5REF[1]

V5REF_SUS

VCCUSBPLL

VCCSUS3_3[20]

VCCRTC

V_CPU_IO[3]
V_CPU_IO[2]
V_CPU_IO[1]

VCCSUS3_3[19]
VCCSUS3_3[18]
VCCSUS3_3[17]
VCCSUS3_3[16]
VCCSUS3_3[15]
VCCSUS3_3[14]
VCCSUS3_3[13]

F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19

AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12

P1
M7
L7
L4
J7
H7
H1
E4
B1
A6

U7
R7

G19
G20

F20
E24
E23
E22
E21
E20
D27
D26
D25
D24

G8
AB18

P7
AA18

A8
F21
A25

A24
AB3
G11

G10
AG23

AD26
AB22

G16
G15
F16
F15
E16
D16
C16

2

2

C184

1

1

0.01U_0402_16V7K

2

C195

C194

1

0.1U_0402_16V4Z

2

C196

C197

1

0.1U_0402_16V4Z

+1.5VALW

1

2

C204

0.1U_0402_16V4Z

R196 0_0603_5%

ICH_V5REF_RUN

ICH_V5REF_SUS

+3VALW

+1.5VS

+VCCP

1

C219

2

0.1U_0402_16V4Z

Near PIN AG23

C185

0.1U_0402_16V4Z

2

1

2

1

Near PIN U7

1 2

2

2

C186

C187

1

1

0.1U_0402_16V4Z

+3VS

Near PIN
AG13, AG16

0.1U_0402_16V4Z

+3VS

2

C198

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Near PIN
A2-A6, D1-H1

1

2

2

1

C201

0.1U_0402_16V4Z

2

C215

0.01U_0402_16V7K

1

+1.5VS

2

C188

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VALW

C202

0.1U_0402_16V4Z

+2.5VS

+1.5VS

Near PIN AB18

+RTCVCC

1

C217

2

0.1U_0402_16V4Z

1

C376

+

2

220U_D2_4VM

+1.5VS

2

2

C206

C205

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C211

2

0.1U_0402_16V4Z

1

C218

2

0.1U_0402_16V4Z

Stuff use external +2.5V,
No stuff use internal +2.5V

W25
W24
W23

M27
M26
M23
M16
M15
M14
M13
M12

E27

Y6
Y27
Y26
Y23

W7

W1

V4
V27
V26
V23
U25
U24
U23
U15
U13

T7
T27
T26
T23
T16
T15
T14
T13
T12

T1

R4
R25
R24
R23
R17
R16
R15
R14
R13
R12
R11
P22
P16
P15
P14
P13
P12

N7
N17
N16
N15
N14
N13
N12
N11

N1

M4

L25
L24
L23
L15
L13

K7
K27
K26
K23

K1

J4
J25
J24
J23

H27
H26
H23

G9

G7
G21
G12

G1

U13D

VSS[172]
VSS[171]
VSS[170]
VSS[169]
VSS[168]
VSS[167]
VSS[166]
VSS[165]
VSS[164]
VSS[163]
VSS[162]
VSS[161]
VSS[160]
VSS[159]
VSS[158]
VSS[157]
VSS[156]
VSS[155]
VSS[154]
VSS[153]
VSS[152]
VSS[151]
VSS[150]
VSS[149]
VSS[148]
VSS[147]
VSS[146]
VSS[145]
VSS[144]
VSS[143]
VSS[142]
VSS[141]
VSS[140]
VSS[139]
VSS[138]
VSS[137]
VSS[136]
VSS[135]
VSS[134]
VSS[133]
VSS[132]
VSS[131]
VSS[130]
VSS[129]
VSS[128]
VSS[127]
VSS[126]
VSS[125]
VSS[124]
VSS[123]
VSS[122]
VSS[121]
VSS[120]
VSS[119]
VSS[118]
VSS[117]
VSS[116]
VSS[115]
VSS[114]
VSS[113]
VSS[112]
VSS[111]
VSS[110]
VSS[109]
VSS[108]
VSS[107]
VSS[106]
VSS[105]
VSS[104]
VSS[103]
VSS[102]
VSS[101]
VSS[100]
VSS[99]
VSS[98]
VSS[97]
VSS[96]
VSS[95]
VSS[94]
VSS[93]
VSS[92]
VSS[91]
VSS[90]
VSS[89]
VSS[88]
VSS[87]

ICH6_BGA609

VSS[86]
VSS[85]
VSS[84]
VSS[83]
VSS[82]
VSS[81]
VSS[80]
VSS[79]
VSS[78]
VSS[77]
VSS[76]
VSS[75]
VSS[74]
VSS[73]
VSS[72]
VSS[71]
VSS[70]
VSS[69]
VSS[68]
VSS[67]
VSS[66]
VSS[65]
VSS[64]
VSS[63]
VSS[62]
VSS[61]
VSS[60]
VSS[59]
VSS[58]
VSS[57]
VSS[56]
VSS[55]
VSS[54]
VSS[53]
VSS[52]
VSS[51]
VSS[50]
VSS[49]
VSS[48]
VSS[47]
VSS[46]
VSS[45]
VSS[44]
VSS[43]
VSS[42]
VSS[41]

GROUND

VSS[40]
VSS[39]
VSS[38]
VSS[37]
VSS[36]
VSS[35]
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]

VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]

F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1

Near PIN A17

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

ICH6-Power

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

19 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

D D

PDD8

PDD9
PDD10
PDD11
PDD12
PDD13

PDD14

PDD15

PDDREQ<17>
PDIOR#<17>

PDDACK#<17>

PDA1<17>

+3VS

500mA

1

C224

1000P_0402_50V7K

C C

2

PDA0<17>
PDCS3#<17>

1

C225
10U_0805_10V4Z

2

PDDREQ

PDIOR#

1 2

R203 470_0402_5%

PDDACK#

PDA1

PDA0 PDA2

PDCS3#

1

C226

0.1U_0402_16V4Z

2

PCSEL

JP6

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

SUYIN_127212FA040G200ZX

R199

22_0402_5%

1 2

PDD7
PDD6

PDD5
PDD4
PDD3

PDD2
PDD1
PDD0
PDIOW#

PDIORDY
IDEIRQ

PDCS1#
PHDD_LED#

PIDERST#

12

R200

@

10K_0402_5%

PDIOW# <17>
PDIORDY <17>

IDEIRQ <17>
PDA2 <17>

PDCS1# <17>
PHDD_LED# <29>

R312

@

10K_0402_5%

1 2

+3VS

PDD[0..15]<17>

33P_0402_50V8J

+3VS

PDD[0..15]

R202

@

5.6K_0402_5%

C223

12

R204 4.7K_0402_5%

1 2

R205 8.2K_0402_5%

1 2

PDDREQ

12

PDIORDY
IDEIRQ

PLT_RST#<8,16,27,28,30>

IDERST_HD#<18>

Fan Control Circuit

+5VS

+3VS

12

R467

@

10K_0402_5%

FAN_SPEED2<28>

B B

+3VS

12

R468

@

10K_0402_5%

EN_DFAN2<28>

<>

R215 100_0402_1% @

1

C97
1000P_0402_50V7K

2

1 2

D13

@

CH355_SC76

2 1

@

2

G

1

C84
47U_1210_10V3M

2

13

D

Q36
FDN359AN_SOT23

S

2

@

@

C98

@

0.1U_0402_16V4Z

1

JP8

1

1

2

2

3

3

MOLEX_53780-0310

@

SMB_EC_CK1<5,28,29,33>

SMB_EC_DA1<5,28,29,33>

SMB_EC_CK1_C
SMB_EC_DA1_C

SMB_EC_CK1

SMB_EC_DA1

Q51

D

S

SMB_EC_CK1_C

1 3

2N7002_SOT23

G

2

+5VS

Q52

D

S

SMB_EC_DA1_C

1 3

2N7002_SOT23

G

2

+5VS

JP25

1

1

1A

2

2

2A

3

3

3A

444A

ACES_85203-0402

+5VS

1A
2A
3A
4A

SMB_EC_CK1_C
SMB_EC_DA1_C

C222

0.1U_0402_16V4Z

12

1
2

1 2

+5VS

12

R410
10K_0402_5%

+5VS

12

R411
10K_0402_5%

+3VS

U16

5

SN74AHC1G08DCKR_SC70

P

IN1

4

O

IN2

G

3

R201

@

0_0402_5%

PIDERST#

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PIDE/FAN Control Interface

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

20 48Friday, June 17, 2005

X5.0

5

D D

C C

R96

SDC_PME#

SDC_PME#<29>

For B version change

B B

SD_CLK_OE#<28>
CLK_PCI_SD<13>

A A

SD_CLK_OE#
CLK_PCI_SD

SN74CBTD1G125_SC70-5

10K_0402_5%

SDPWR#

5

1 2

0_0402_5%

U39

1

OE#

VCC

2

A

B

3

GND

+3VS

12

R342

RT9701_CE

13

D

2

G

2N7002_SOT23

S

5

CLK_SD_CHIP

4

1

C236

0.1U_0402_10V6K

2

Q18

+5VS

PCI_AD[0..31]<16,22,23>

PCI_C/BE#0<16,22,23>
PCI_C/BE#1<16,22,23>
PCI_C/BE#2<16,22,23>
PCI_C/BE#3<16,22,23>

PCI_AD20

PCI_PAR<16,22,23>
PCI_FRAME#<16,22,23>
PCI_IRDY#<16,22,23>
PCI_TRDY#<16,22,23>
PCI_DEVSEL#<16,22,23>
PCI_STOP#<16,22,23>
PCI_PERR#<16,22,23>
PCI_SERR#<16,22,23>

PCI_REQ#2<16>

PCI_GNT#2<16>

PCI_PIRQA#<16>

PCIRST#<16,22,23>

R343 100_0402_5%

CLK_PCI_SD

CLK_SD_CHIP

U18

3

VIN

4

VIN/CE

2

GND

RT9701-CB_SOT23-5

1U_0603_10V4Z

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#2
PCI_GNT#2
PCI_PIRQA#
SD_PME#
PCIRST#
CLK_SD_CHIP

VOUT
VOUT

4

12

12

R412
0_0402_5%

1
5

4

1

C421

2

100

@

SD_3VCC_CardPWR

1

C240

2

4.7U_0805_6.3V6K

1

C388

0.1U_0402_10V6K

2

U41

39

AD0

38

AD1

37

AD2

36

AD3

35

AD4

34

AD5

33

AD6

32

AD7

30

AD8

29

AD9

28

AD10

27

AD11

26

AD12

25

AD13

24

AD14

23

AD15

10

AD16

9

AD17

8

AD18

7

AD19

6

AD20

5

AD21

4

AD22

3

AD23
AD24

99

AD25

98

AD26

97

AD27

96

AD28

95

AD29

94

AD30

93

AD31

31

C/BE#0

21

C/BE#1

12

C/BE#2

1

C/BE#3

2

IDSEL

20

PAR

13

FRAME#

14

IRDY#

15

TRDY#

16

DEVSEL#

17

STOP#

18

PERR#

19

SERR#

92

REQ#

91

GNT#

88

INTA#

87

RSV/PME#

89

PCIRST#

90

PCICLK

W83L528D

1

C242

2

0.1U_0402_10V6K

3

http://hobi-elektronika.net

+3VS

1

1

C422

0.1U_0402_10V6K

52

3VCC223VCC

83

3VSB

MS/MS Pro I/F

MSDSB#/MSPWR#

SD/MMC I/F

SDEXCLK

SDLED/SDWP

SDDSB#/SDPWR#

SDEXCD#

PCI Interface

SM/xD I/F

XDCD1/CLKRUN#
SMLED/SMEXWP#
SMDSB#/SMPWR#

XDLED/LED

VSS11VSS

Signal XDPWR# pull up support
MMC, pull down disable MMC

62

SD_3VCC_CardPWR

R379 4.7K_0402_5%

CARD_DET_W#
SDD1

SDD0
SDCLK_W

SDCMD_W
SDD3

SDD2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

MSD0
MSD1
MSD2
MSD3
MSBS

MSCLK

MSNSEL

MSLED

MSINS#

SDD0
SDD1
SDD2
SDD3

SDCMD

SDCLK

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7

SMCE#

SMWP#

SMRB
SMRE#
SMCLE
SMALE

SMWE#

SMCD#

XDCE#

XDWP#

XDCD2#

XDPWR#

R383 4.7K_0402_5%

1 2

1 2

R348

10_0402_5%

1

C241

22P_0402_25V8K

2

C423
1U_0603_10V4Z

2

RP19

47K_0804_8P4R_5%

MSD0

64

MSD1

65

MSD2

67

MSD3

68
66
69

EXTROMSEL

63
70
71
82

73
74
76
77
75
78
72
79
80
81

53
54
55
56
57
58
59
60
42
43
45
46
48
49
50
84
47
51
85
86
41
40
44
61

R384 4.7K_0402_5%

1 2

R376 4.7K_0402_5%

1 2

R214 4.7K_0402_5%

SDD0
SDD1
SDD2
SDD3
SDCMD_W
SDCLK

SDLED_SDWP#
SDPWR#
CARD_DET_W#

1 2

R211 4.7K_0402_5%

1 2

R212 4.7K_0402_5%

1 2

R213 4.7K_0402_5%

XDLED

1 2

R394 4.7K_0402_5%

R396

4.7K_0402_5%

1 2

R385 4.7K_0402_5%

R392 4.7K_0402_5%

1 2

1 2

1 2

3

1 8

2 7

3 6

4 5

1 2

R418 33_0402_5%

1 2

R338 4.7K_0402_5%

1 2

R323 0_0402_5%

@

R220

0_0402_5%

R386

4.7K_0402_5%

1 2

+3VS

1 2

12

+3VS

+3VALW

1 2

8
7
6
5
4
3
2
1

9

R344

@

1M_0402_5%

+3VS

SDCLK_W

CARD_DET_W_EC#

+3VS

+3VS

+3VS

12

R397

4.7K_0402_5%

R393

@

0_0402_5%

JP7

MMC_DET#10Wr_Pt_Vss
SD4

SD3
Vss2
SDCLK
Vdd
Vss1
SD2
SD1

SD5

MOLEX_67993-0002

+3VS

Vss3
Vss4

Wr_Pt
IOGND1
IOGND2

R378

4.7K_0402_5%

1 2

2

XDLED

SDLED_SDWP#

CARD_DET_W_EC# <28>

R210 0_0402_5%

For B version change

R377

4.7K_0402_5%

1 2

11

12
13
14
15
16

2

1 2

R406 1K_0402_5%@

1 2

R375 10K_0402_5%@

1 2

R87 1K_0402_5%

Notes: This signal high voltage level valid

PM_CLKRUN#

1 2

@

+3VS

1 2

R387

4.7K_0402_5%

WR_PT#

PM_CLKRUN# <18,22,23,27,30>

EXTROMSEL

12

1

2

Compal Electronics, Inc.(KunShan)

Title

SD Controller-W83L518D

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

SDLED

WR_PT#

CLK_PCI_SD

R349

@

22_0402_5%

C420

@

15P_0402_50V8D

1

SDLED <29>

+3VS

R381

4.7K_0402_5%

1 2

R382

4.7K_0402_5%

1 2

1

@

X5.0

of

21 48Friday, June 17, 2005

5

4

3

2

1

http://hobi-elektronika.net

PJP18

@

2 1

PAD-SHORT 2x2m

Q42

+3VS +3VS_WL

D D

WLOFF# RFOFF#

D12 RB751V_SOD323

1

2

CLK_PCI_MINI

C399

0.1U_0402_16V4Z

1

2

0.01U_0402_25V4Z

1

C400

2

4.7U_0805_10V6K

WLOFF#<28>

12

R221
22_0402_5%

1

C250

22P_0402_50V8J

2

C C

+3VS_WL

C408

B B

BOM change in MP

A A

PJP17

2 1

PAD-SHORT 2x2m

WLAN_ACTIVE_WL<28>

21

W=60mils

+5VS

PCI_PIRQG#<16>

PCI_REQ#1<16>

PCI_C/BE#3<16,21,23>

PCI_C/BE#2<16,21,23>
PCI_IRDY#<16,21,23>

PCI_SERR#<16,21,23>
PCI_PERR#<16,21,23>

PCI_C/BE#1<16,21,23>

CLK_PCI_MINI<13>

PM_CLKRUN#<18,21,23,27,30>

+5VS

W=20mils

1

C383

0.1U_0402_16V4Z

2

1

2

WLAN_ACTIVE_WL

PCI_PIRQG#

CLK_PCI_MINI
PCI_REQ#1
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25
WLAN_ACTIVE
PCI_C/BE#3
PCI_AD23

PCI_AD21
PCI_AD19

PCI_AD17
PCI_C/BE#2
PCI_IRDY#

PM_CLKRUN#
PCI_SERR#

PCI_PERR#
PCI_C/BE#1
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3
PCI_AD1

W=20mils

C410

0.1U_0402_16V4Z

JP27

1

TIP

3

8PMJ-3

5

8PMJ-6

7

8PMJ-7

9

8PMJ-8

11

LED1_GRNP

13

LED1_GRNN

15

CHSGND

17

INTB#

19

3.3V

21

RESERVED

23

GROUND

25

CLK

27

GROUND

29

REQ#

31

3.3V

33

AD31

35

AD29

37

GROUND

39

AD27

41

AD25

43

RESERVED

45

C/BE3#

47

AD23

49

GROUND

51

AD21

53

AD19

55

GROUND

57

AD17

59

C/BE2#

61

IRDY#

63

3.3V

65

CLKRUN#

67

SERR#

69

GROUND

71

PERR#

73

C/BE1#

75

AD14

77

GROUND

79

AD12

81

AD10

83

GROUND

85

AD8

87

AD7

89

3.3V

91

AD5

93

RESERVED

95

AD3

97

5V

99

AD1

101

GROUND

103

AC_SYNC

105

AC_SDATA_IN

107

AC_BIT_CLK

109

AC_CODEC_ID1#

111

MOD_AUDIO_MON

113

AUDIO_GND

115

SYS_AUDIO_OUT

117

SYS_AUDIO_OUT GND

119

AUDIO_GND

121

RESERVED

123

VCC5A

TYCO_1470459-3~D

PCI_AD[0..31]

PCI_AD[0..31] <16,21,23>

RING

8PMJ-1
8PMJ-2
8PMJ-4

8PMJ-5
LED2_YELP
LED2_YELN
RESERVED

5V

INTA#

RESERVED

3.3VAUX
RST#

3.3V

GNT#

GROUND

PME#

RESERVED

AD30

3.3V
AD28
AD26
AD24

IDSEL

GROUND

AD22
AD20

PAR
AD18
AD16

GROUND

FRAME#

TRDY#
STOP#

3.3V
DEVSEL#
GROUND

AD15
AD13
AD11

GROUND

AD9

C/BE0#

3.3V

AD6
AD4
AD2

AD0
RESERVED
RESERVED

GROUND

M66EN

AC_SDATA_OUT

AC_CODEC_ID0#

AC_RESET#

RESERVED

GROUND

SYS_AUDIO_IN

SYS_AUDIO_IN GND

AUDIO_GND

MCPIACT#

3.3VAUX

2

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

MINIPCI P#36 BT_ACTIVE: Channel_CLK BT_Priority
MINIPCI P#43 WLAN_ACTIVE: Channel_DATA

WLAN_LINK_WL

W=20mils

PCI_PIRQH#

W=20mils

PCIRST#
PCI_GNT#1
WLANPME#

BT_ACTIVE
PCI_AD30

PCI_AD28
PCI_AD26
PCI_AD24
IDSEL18

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_C/BE#0

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

W=20mils

1

C409

0.1U_0402_16V4Z

2

BT Power Control

WLAN_LINK_WL <28>

PCI_PIRQH# <16>

+3VALW

PCIRST# <16,21,23>
PCI_GNT#1 <16>
WLANPME# <29>

PCI_PAR <16,21,23>

PCI_FRAME# <16,21,23>

PCI_TRDY# <16,21,23>

PCI_STOP# <16,21,23>

PCI_DEVSEL# <16,21,23>

PCI_C/BE#0 <16,21,23>

+3VALW

R402

100K_0402_5%

BT_PWR_ON<18>

BTDIS#-BTON

W=60mils

IDSEL : AD18

0.1U_0402_16V4Z

1

C417
1000P_0402_50V7K

2

1 2

R403

@

1 2

0_0402_5%

1

C380

0.01U_0402_25V4Z

2

WL_EN<18>

+3VS_BT

1

C365

2

AO3413_SOT23

S

G

2

12

13

D

2

G

S

1

C381

0.1U_0402_16V4Z

2

1

C324

0.01U_0402_25V4Z

2

R368 100_0402_1%

WL_EN

BTDIS#-BTON<28>

D

13

R404
10K_0402_5%

Q47

2N7002_SOT23

1

C382

4.7U_0805_10V6K

2

1

C367

0.1U_0402_16V4Z

2

1 2

R369 1K_0402_5%@

BT MODULE CONN

BT_LED<29>

USBP3-<18>
USBP3+<18>

R409
0_0402_5%

1 2

MMBT3904_SOT23

12

BT_LED
WLAN_ACTIVE

BTDIS#-BTON
BT_ACTIVE
USBP3­USBP3+

Q32

+3VS_BT+3VS

+5VS

+3VS_WL

1

2

@

31

2

C379

4.7U_0805_10V6K

IDSEL18PCI_AD18

MOLEX_53780-0890

JP16

1
2
3
4
5
6
7
8

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

MINIPCL Slot/BT

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

22 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

+3VALW

D D

R414

100K_0402_5%

LAN_PWR_ON<28>

PCI_AD[0..31]<16,21,22>

C C

PCI_C/BE#0<16,21,22>
PCI_C/BE#1<16,21,22>
PCI_C/BE#2<16,21,22>
PCI_C/BE#3<16,21,22>

B B

CLK_PCI_LAN

12

R227

@

22_0402_5%

1

@

C267
15P_0402_50V8D

2

PCI_PAR<16,21,22>
PCI_FRAME#<16,21,22>
PCI_IRDY#<16,21,22>
PCI_TRDY#<16,21,22>
PCI_DEVSEL#<16,21,22>
PCI_STOP#<16,21,22>

PCI_PERR#<16,21,22>
PCI_SERR#<16,21,22>

PCI_REQ#3<16>
PCI_GNT#3<16>

PCI_PIRQF#<16>
PCI_PIRQB#<16>

LAN_PME#<29>
PCIRST#<16,21,22>

CLK_PCI_LAN<13>
PM_CLKRUN#<18,21,22,27,30>

LAN_PWR_ON

R224 100_0402_5%

+3VLAN

1 2

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#

PCI_PERR#
PCI_SERR#

PCI_REQ#3
PCI_GNT#3

PCI_PIRQF#
PCI_PIRQB#
LAN_PME#

PCIRST#
CLK_PCI_LAN
PM_CLKRUN#

PJP19

@

2 1

PAD-SHORT 2x2m

Q54
AO3413_SOT23

S

1

C424

G

2

1000P_0402_50V7K

2

G

IDSELPCI_AD17

12

D

13

2

12

R421
10K_0402_5%

13

D

Q55

2N7002_SOT23

S

47
46
45
43
42
41
40
39
36
35
34
33
32
30
29
28
15
14
13
12
11
10

9

8
96
93
92
91
89
87
86
85

38
27
17
84

98
24

18
19
20
21
23

25
26

83
82

80
79
57

81
97
50

6
22
37
49
90
95

U19

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE#0
C/BE#1

PCI I/F

C/BE#2
C/BE#3

IDSEL
PAR

FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#

PERR#
SERR#

REQ#
GNT#

INTA#
INTB#
PME#

RST#
PCICLK
CLKRUN#

VDD
VDD
VDD

Power

VDD
VDD
VDD

RTL8101L_LQFP100

L17

1 2

FBM-L11-201209-170LMT

48

VDD25

94

VDD25

58

AVDD25

59

AVDD

70

AVDD

75

AVDD

Power

52

EEDO

53

EEDI

54

EESK

55

EECS

78

LED0

77

LED1

76

LED2

72

TXD+

71

TXD-

68

RXIN+

67

RXIN-

61

X1

60

X2

64

LWAKE

LAN I/F

74

ISOLATE#

65

RTSET

63

RTT3

56

VCTRL

1

AC_RST#

3

AC_SYNC

4

AC_DOUT

5

AC_DIN

7

AC_BCK

AC-Link

100

GPIO0

99

GPIO1

51

ROMCS/OE#

69

NC

2

DGND1

16

DGND2

31

DGND3

44

DGND4

88

DGND5

62

AGND1

66

AGND2

73

AGND3

+3VLAN

1

C252

0.1U_0402_10V6K

VDD2.5V

0.1U_0402_10V6K

EE_DOUT
EE_DIN
EE_CLK
EE_CS

TXD+
TXD-

RXIN+
RXIN-

LAN_ISOLATE#

1 2

R225 5.6K_0603_1%

0.1U_0402_10V6K

2

1

C257

0.1U_0402_10V6K

2

C261

1

C253

0.1U_0402_10V6K

2

1

C258

0.1U_0402_10V6K

2

1

1

C262

2

0.1U_0402_10V6K

5.6K_0603_5%

TXD+ <24>
TXD- <24>

RXIN+ <24>
RXIN- <24>

1

C263

2

2

R223

12

25MHZ_20P_1BX25000CK1A

C254

AVDD33

1

2

0.1U_0402_10V6K

+3VLAN

LAN_X1

Y4

LAN_X2

1

0.1U_0402_10V6K

2

R222

0_0805_5%

1 2

L18

1 2

FBM-L11-201209-170LMT

C154

4.7U_0805_10V6K

22P_0402_50V8J

12

22P_0402_50V8J

ORG(pin6): Pull-up to Vcc 64x16
Pull-down to GND 128x8

C265

C266

EE_CS
EE_CLK
EE_DIN
EE_DOUT

C255

600mA

12

12

1

0.1U_0402_10V6K

2

+2.5VLAN

1

C256

2

+3VLAN

C259

U20

1

CS

VCC

2

SK

NC

3

DI

NC

4

DO

GND

AT93C46-10SI-2.7_SO8

1

C260

2

0.1U_0402_10V6K

SUSP#<25,28,32,33,37,38>

8
7
6
5

+2.5VLAN

1

2

10U_0805_10V4Z

LAN_PWR_ON
SUSP#

+3VLAN

1 2

R226 10K_0402_5%

+3VALW

5

U17

1

P

B

4

Y

2

A

G

TC7SH08FU_SSOP5

3

1 2

R274 0_0402_5%

@

LAN_ISOLATE#

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

RTL8101L

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

23 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

D D

RXIN+

RXIN-

RXIN-

TXD+

TXD-

RXIN+

TXD­TXD+

R339

NS0013_CT3

12

12

1

C385

0.1U_0402_10V6K

2

TXD+<23>

TXD-<23>

R371

49.9_0603_1%

1 2

12

12

R229

49.9_0603_1%

C C

B B

1

C269

0.1U_0402_10V6K

2

C268 0.1U_0402_10V6K

R230

49.9_0603_1%

49.9_0603_1%

RXIN+ <23>

RXIN- <23>

T2

1

RD+

RX+

2

RD-

RX-

3

CT

CT

6

CT

CT

7

TD+

TX+

TD-8TX-

NS0013_16P

C271

0.001U_0402_50V7M

16
15
14

11
10
9

NS0013_CT2

R232

75_0603_1%

RJ45_RXD­RJ45_RXD+
NS0013_CT1

RJ45_TXD­RJ45_TXD+

12

R233

75_0603_1%

12

2

C270
1000P_1206_2KV7K

1

RJ45_RXD-

RJ45_RXD+
RJ45_TXD­RJ45_TXD+

R234

75_0603_1%

RJ45_COMP1

12

75_0603_1%

T=10mil

R235

10

RJ45_COMP2

12

9
8
7
6
5
4
3
2
1

JP9

BOSS1
PR4­PR4+
PR2­PR3­PR3+
PR2+
PR1­PR1+
BOSS2

SUYIN_100198FB008G100ZL

SHLD1

SHLD2

11

12

Top view

18

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Magnetics/RJ45

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

24 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

PJP21

L19

@

1 2

CHB2012U121_0805

+5VS VDDA

D D

4.7U_0805_10V4Z

AUDIO_PWR_ON<28>

SUSP#<23,28,32,33,37,38>

SUSP#

C C

SUSP#<23,28,32,33,37,38>

2

G

1

C276

2

AUDIO_PWR_ON

SUSP#

12

R240
10K_0402_5%

SUSP_T

13

D

Q20
2N7002_SOT23

S

0.1U_0402_16V4Z

2

G

For STAC9758 from DOCK

For STAC9200 from DOCK

MONO_IN

B B

12

R246

4.7K_0402_5%

12

R245

51K_0402_5%

C297

0.022U_0402_25V4Z

1 2

1

C299
2700P_0603_50V7K

2

From ducking connector

R236

2K_0402_5%

BEEP#<28>

ICH_SPKR<18>

A A

R238

2K_0402_5%

BEEP_R#

12

ICHSPKR

12

C272

1U_0603_10V4Z

1 2

C273

1U_0603_10V4Z

1 2

1SS355_SOD323

MONO_IN

D9

w=40mil

1

C277

2

1 2

R419 0_0402_5%

1 2

R415 0_0402_5%@

VDDA+5VS

12

R239
100_0402_5%

13

D

Q19
2N7002_SOT23

S

DOCK_MIC<31>

12

INT_MIC1<29>
INT_MIC2<29>

AC97_SYNC<17>
AC97_SDOUT<17>

HP_PLUG#<26,31>

VDDA

12

R237
100K_0402_5%

1

C278

0.1U_0402_16V4Z

2

DOCK_MIC

C294 0.1U_0402_16V4Z

VDDA

VDDC

DOCK_MIC<31>

INT_SPK<26>

U21

1

VIN

3

EN

TPS793475DBV_SOT23-5

0.1U_0402_16V4Z

1

C281

C280

2

STAC9758_NOUSEIN

1 2

C286 0.1U_0402_16V4Z

1 2

C289 0.22U_0603_10V7K

1 2

C291 0.1U_0402_16V4Z

DOCK_MIC

1 2

INT_SPK

1 2

INT_MIC1
INT_MIC2
STAC9758_PHONE
PC_BEEP

AC97_CHIP_RST#
AC97_SYNC
AC97_SDOUT

1 2

R247 4.7K_0402_5%

HP_PLUG#

1 2

R248 4.7K_0402_5%

1 2

R341 0_0402_5%

VOUT

BYPASS

GND

w=30mil

0.1U_0402_16V4Z

1

2

12

C3720.22U_0603_10V7K @

C3870.1U_0402_16V4Z

STAC9758_SPDIF

5

TPS793475_BYPASS

4

2

Iin= 80mA

1

C282

2

Io= 200mA
Vo= 4.65V ~ 4.85V
w=30mil

C279

VDDA VDDC

10U_0805_10V4Z

0_0402_5%

R273

1 2

U22

AVDD125AVDD2

14

AUX_L

15

AUX_R

16

FP_MIC_L

17

FP_MIC_R

23

LINE_IN/SUR_L

24

LINE_IN/SUR_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1/CTR

22

MIC2/LFE

13

PHONE

12

PC_BEEP

11

RESET#

10

SYNC

5

SDATA_OUT

46

CID1#

47

EAPD/SPDIF_IN

48

SPDIF/ADAT

4

DVSS1

7

DVSS2

STAC9758T-CB!_TQFP48

1

2

0.1U_0402_16V4Z

38

R298

C274

1

2

4.7U_0805_10V4Z

Iin= 35mA

0_0402_5%

1 2

9

DVDD11DVDD2
FRONT_L

FRONT_R

MONO

REAR_L

REAR_R

BIT_CLK

SDATA_IN

XTL_IN

XTL_OUT

AFILT1
AFILT2

VREFOUT

VREF
CAP2

GPIO0
GPIO1
GPIO2
GPIO3

CENTER

LFE

AVSS1
AVSS2
AVSS3

1

C275

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C283

2

35
36
37
39
41

6

AC97_SDIN0

8
2

XTL_OUT

3

AFILT1

29

AFILT2

30
28

STAC9758_VREF

27

STAC9758_CAP2

32

GPIO0_9758

31

GPIO1_9200

33

GPIO2

34

DIS_INTMIC

45
43
44

26
42
40

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C284

2

DOCKHP_OUT_L1
DOCKHP_OUT_R1

MBHP_OUT_L
MBHP_OUT_R

R242

33_0402_5%

1 2

R340 0_0402_5%
R370 0_0402_5% @

1 2

R372 0_0402_5%

R241

0_0603_5%

+3VS_VDDC

1 2

1

C285

2

1 2

R286 0_0402_5%@

1 2

R287 0_0402_5%@

C287 0.1U_0402_16V4Z
C371 0.1U_0402_16V4Z

C290 1000P_0402_50V7K @

1 2

C288 1000P_0402_50V7K@

1 2

C292 27P_0402_50V8J

1 2

R243 0_0402_5%@

1 2

R244 0_0402_5%@

1 2

C295 820P_0603_50V7K

1 2

C298 820P_0603_50V7K

C300 1U_0603_10V4Z

1 2

C301 1U_0603_10V4Z

1 2

1 2
1 2

1 2

AC97_BITCLKBITCLK

CLK_14M_CODECXTL_IN

R413

100K_0402_5%

AUDIO_PWR_ON

12
12

AC97_BITCLK <17>
AC97_SDIN0 <17>
CLK_14M_CODEC <13>

GPIO0 <26>
GPIO2 <26>

DIS_INTMIC <31>

From ducking
connector

1 2

@

2 1

PAD-SHORT 2x2m

Q53
AO3413_SOT23

S

1

C419

G

2

1000P_0402_50V7K

2

G

DOCKHP_OUT_L
DOCKHP_OUT_R

R288
0_0402_5%

1 2

D

13

2

12

R417
10K_0402_5%

13

D

Q56

2N7002_SOT23

S

AC97_RST#<17>

1 2

+3VS_VDDC+3VS

AC97_RST#

AC97_RST_ON#

R398
0_0402_5%

XTL_IN

XTL_OUT

R340,C289

R370,C372

R341,R372

R273

DOCKHP_OUT_L <31>
DOCKHP_OUT_R <31>

MBHP_OUT_L <26>
MBHP_OUT_R <26>

22P_0402_50V8J

Y5

24.576MHz_16P_3XG-24576-43E1

1 2

22P_0402_50V8J

Item

R298

EAPD PIN47

H

L

LINE_IN_L PIN23
LINE_IN_R PIN24

ENABLE

DISABLE

5

DIS_INTMIC DOCK_MIC
(PIN 45) (PIN 16)

H

L ENABLE

INT_MIC1
INT_MIC2

DISABLE ENABLE

DISABLE

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Title

Size Document Number Rev

Custom

2

Date: Sheet

R416

@

0_0402_5%

1 2

3

U25

R400

1K_0402_5%

C293

1 2

1 2

C296

A2Y

+5VS

G

OE#

P

1

5

AC97_CHIP_RST#

4

SN74AHCT1G125GW_SOT353-5

STAC9200STAC9758

POP

DE_POP
Connect

to GND
Connect

to VDDA
Connect

to VDDC

DE_POP

POP

NC

NC

NC

Compal Electronics, Inc.(KunShan)

STAC9758T

Bandera-EAX00-LA2581

1

of

25 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

AMP. FOR INTERNAL SPEAKER

L20

BLM21A05_0805

D D

1 2

VDDA

1

C304

2

L21

CHB1608B121_0603

1 2

L22

CHB1608B121_0603

1 2

HP OUT/MIC IN

GPIO2<25>
GPIO0<25>

4.7K_0402_5%

C313

1

C303

0.1U_0402_16V4Z

2

IN+

IN-

GPIO2
GPIO0

R251

2

2

C314
330P_0603_50V8J

1

1

1

C308

0.47U_0603_16V7K

2

C309

12

6

U23

3

IN+

VDD

5

4

1
2

1

2

1000P_0402_50V7K

VO+

IN-

SHUTDOWN
BYPASS

1 2

C348 330P_0603_50V8J @

1 2

C386 330P_0603_50V8J@

1

2

8

VO-

GND

TPA6211A1DGNR_PMSOP8

7

VDDA

12

R252

4.7K_0402_5%

1 2

L23 FBM-11-160808-700T_0603

1 2

L24 FBM-11-160808-700T_0603

1 2

L25 FBM-11-160808-700T_0603

C312

0.1U_0402_16V4Z

10U_0805_10V4Z

V0+

V0-

HPOUTL

1

C302

0.1U_0402_16V4Z

INT_SPK<25>

Please keep EAPD at High level

C C

B B

MBHP_OUT_R<25>
MBHP_OUT_L<25>

MBHP_OUT_L OUTL

1 2

R253 4.99_0402_1%

1 2

R254 4.99_0402_1%

INT_SPK

MUTE#<28>

HP_PLUG#<25,31>

OUTRMBHP_OUT_R

1 2

C306 0.1U_0402_16V4Z

1 2

C307 0.1U_0402_16V4Z

MUTE#
HP_PLUG#

+5VALW

U24

5

1

A

2

B

3

C384 47U_1210_10V3M

1 2

C311 47U_1210_10V3M

1 2

P

4

O

G

NC7ST08P5X_SC70-5

20K_0402_5%

R249 20K_0402_5%

R250 20K_0402_5%

R255

2

1 2

1 2

SHUTDOWN

HP_OUTR HPOUTR
HP_OUTL

12

12

R256
20K_0402_5%

330P_0603_50V8J

1

C305

0.1U_0402_16V4Z

2

SPK++

SPK--

JP20

5
4
3

6
2
1

7
8

FOX_JA6333L-6S0-TR

Speaker

JP10

2

2

1

1

MOLEX_53780-0290

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

AMP/JACK

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

26 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

500mA

USB_1S

USB_0S

D D

C318

+5VS

4.7U_0805_10V4Z

1

2

C319

W=40mils

0.1U_0402_16V4Z

1

2

U33

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

USBPWREN#

R362

0_0603_5%

OC1#
OUT1
OUT2
OC2#

R364
0_0603_5%

1 2

USBEN#

12

8
7
6
5

@

USBEN# <28>

USB Over Current

USB_OC#1

USB_OC#0

1

2

1

C323

0.1U_0402_16V4Z

2

C322

0.1U_0402_16V4Z

USB_OC#1 <18>

USB_OC#0 <18>

USB_0S USB_0

L27

1 2

FBM-11-451616-800T

0.1U_0402_16V4Z

USBP0-<18>
USBP0+<18>

USBP0­USBP0+

W=40mils

1

1

+

C325

C92
150U_D2_6.3VM

2

2

1 2

R261 0_0402_5%

1 2

R262 0_0402_5%

2

C326

0.001U_0402_50V7M

1

4
3

PRTR5V0U2X_SOT143

1

C327

@

3.3P_0402_50V8J

2

D25

2

IO1

VIN

1

GND

IO2

USB20_N1_R
USB20_P1_R

1

C328

3.3P_0402_50V8J

2

USB Port 0

SUYIN_2569A-04G3T

@

JP22

56

1
2
3
4

C C

L26

1 2

FBM-11-451616-800T

TPM

U26

LPC_AD0<17,28,30>
LPC_AD1<17,28,30>

B B

A A

+3VS

R268

4.7K_0402_5%

R269

@

4.7K_0402_5%

Base I/O Address

0 = 02Eh

* 1 = 04Eh

12

12

LPC_AD2<17,28,30>
LPC_AD3<17,28,30>

CLK_PCI_TPM<13>
LPC_FRAME#<17,28,30>
PLT_RST#<8,16,20,28,30>

PM_CLKRUN#<18,21,22,23,30>

PACCESS: The standard should connect to GND, if the pin is connected to
VDD, the Force_Clear command is enable. and also used for other features,
fefer to the TCG.

9/22 is reserved pin. connect to GND

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

CLK_PCI_TPM
LPC_FRAME#
PLT_RST#
SIRQ

SIRQ<18,28,30>

PM_CLKRUN#
BADDR

13
27
12
23
20

2
3
6
7

8

LAD0
LAD1
LAD2
LAD3

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
BADDR

+3VS

11

25

19

VDD5VDD

VDD

VDDC

PACCESS
PENABLE

TPM
SLD 9630 TT 1.1

GND4GND10GND18GND

SLD9630TT_TSSOP28

24

1

C329

0.1U_0402_16V4Z

2

LPCPD#

TESTEN

TESTIO

CLKOVD

NC
NC
NC
NC

1

C330

0.1U_0402_16V4Z

2

26
17
16
21
22
9

1
14
15
28

PACCEE
PENABLE

300_0402_5%

+3VS

12

R266

1

2

R263
10K_0402_5%

LPCPD#

12

C331

0.1U_0402_16V4Z

R267

10K_0402_5%

+3VS

12

12

1

2

R264
10K_0402_5%

C332

0.1U_0402_16V4Z

@

USBP1-<18>
USBP1+<18>

22P_0402_50V8J

CLK_PCI_TPM

R265

@

33_0402_5%

C333

@

0.1U_0402_16V4Z

USBP1­USBP1+

12

1

2

USB_1USB_1S

W=40mils

1

1

+

C316

C91
150U_D2_6.3VM

2

2

1 2

R257 0_0402_5%

1 2

R258 0_0402_5%

SUS_STAT#<18,30>
TPM_LPCPD#<28>

2

C317

0.001U_0402_50V7M

1

SUS_STAT#
TPM_LPCPD#

4
3

PRTR5V0U2X_SOT143

1

C320

@

3.3P_0402_50V8J

2

1 2

1
2

D26

IO1

VIN

GND

IO2

R401

@

0_0402_5%

+3VS

5

B
A

3

2
1

U28

P

4

Y

G

TC7SH08FU_SSOP5

LPCPD#

USB20_N0_R
USB20_P0_R

1

C321

@

3.3P_0402_50V8J

2

USB Port1

JP19

1
2
3

SUYIN_2569A-04G3T

4

56

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

USB PORT/TPM

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

27 48Friday, June 17, 2005

X5.0

5

4

3

2

1

L28

FBM-L11-160808-601LMT_200mA_10%

1 2

L29

ECAGND

12

D D

KSI0
KSI1

2

3

D21

PSOT24C_SOT23

1

C C

B B

A A

KSI4
KSI5

2

3

D23

PSOT24C_SOT23

1

TP_TEST: Clock Test Mode/ Low: Test Mode/ High:
32KHz clock in normal running
TP_PLL: DPLL Test Mode/ Low: Test Mode/ High:
Normal operation
R272 and R323 is unnecessary, because KB910L
pin 47 and 48 are pull-up internally04/11/30

10K_0402_5%

TP3
PAD

TP4
PAD

+5VS

FBM-L11-160808-601LMT_200mA_10%

CLK_PCI_EC

R281
33_0402_5%

1 2
2

C345
15P_0402_50V8D

1

2

3

1

2

3

1

+3VALW+3VALW

12

12

R391

JP11

E&T_96212-1011S

R390
10K_0402_5%

RP44

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

@

1 2

R331 10K_0402_5%

@

1 2

R330 10K_0402_5%

@

1

1

2

2

3

3

EC_TXD

4

4

5

5

6

6

7

7

8

8

9

9

10

10

5

@

@

KSI2
KSI3

D22

PSOT24C_SOT23

KSI6
KSI7

D24

PSOT24C_SOT23

EC_TXD

EC_RXD

@

WLAN_LINK_WL
WLAN_ACTIVE_WL
WLAN_LED
LAN_PWR_ON

TPM_LPCPD#

CARD_DET_W_EC#

EC_AVCC+3VALW

2

C337

0.1U_0402_16V4Z

1

R276
47K_0402_5%

1 2

+3VALW

0.1U_0402_16V4Z

HW STRAP PIN(910L only 2 pin)
pin47: TP_TEST, Low active
pin48: TP_PLL, low active
For normal application, no
application component is
required to select the normal
mode because kb910L has an
internally build-in pull up
resistor that automatically
selects the suitable operation
mode.

+3VALW +3VALW

12

R293
10K_0402_5%

+5VALW

KSI_USER#

12

R380
10K_0402_5%

WL_BTN#

C344

+3VALW

R271

10K_0402_5%

1

2

+3VS

R272
10K_0402_5%

1 2

1 2

GATEA20<17>
KBRST#<17>
SIRQ<18,27,30>

LPC_FRAME#<17,27,30>

LPC_AD3<17,27,30>
LPC_AD2<17,27,30>
LPC_AD1<17,27,30>

LPC_AD0<17,27,30>
CLK_PCI_EC<13>
PLT_RST#<8,16,20,27,30>

EC_SCI#<18>

PM_BATLOW#<18>

SD_CLK_OE#<21>
EC_DIS_INTMIC<29>

EC_EXTTS0#<8>
VCCP_PWRGD<38>
DIGRST#<14>
SSBTN#<29>
DIGISUSP<14>
USBEN#<27>
EC_SLP_S4#<18>
FPR_PWRON#<29>
GIGALAN_RST#<31>

PRSNT1#<31>
PRSNT2#<31>

SMB_EC_DA2<5,14>
SMB_EC_CK2<5,14>
SMB_EC_DA1<5,20,29,33>
SMB_EC_CK1<5,20,29,33>

AUDIO_PWR_ON<25>
PWR_LED#<29>
KSI_USER#<29>
CHARGE_LED#<29>
BATT_LED#<29>
MUTE#<26>

WL_BTN#<29>

SYSON<32,38>
EC_RSMRST#<18>

BKOFF#<14>
EC_SLP_S3#<18>
ICH_PWRGD<18,29>
EC_SLP_S5#<18>
EC_SMI#<18>
EC_SWI#<18>
BTDIS#-BTON<22>
SUSP#<23,25,32,33,37,38>
EC_PBTNOUT#<18>
PME#<29>

RP18

10K_0804_8P4R_5%

+3VALW

0.1U_0402_16V4Z

1

C338

2

0.1U_0402_16V4Z

KSI0<29>
KSI1<29>
KSI2<29>
KSI3<29>
KSI4<29>
KSI5<29>
KSI6<29>
KSI7<29>

18
27
36
45

R28210K_0402_5%

12

R33710K_0402_5%

12

R36010K_0402_5%

12

R30010K_0402_5%

12

R32210K_0402_5%

12

4

EC_AVCC

11

127

141

26

37

105

VCC

VCC

VCC/ EC VCC

VCC / EC VCC

VCC / EC VCC

VCC / EC VCC

PWR

FAN/PWM

INVT_PWM/GPIO0F/PWM1

OUT BEEP/GPIO12/PWM3

FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PS2 interface

Address

SM BUS

GND13GND28GND

GND

GND

GND

39

103

129

139

R2774.7K_0402_5%

12

R2784.7K_0402_5%

12

R2794.7K_0402_5%

12

R2804.7K_0402_5%

12

3

75

BATTEMP/AD0/GPIO38
BATT OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD BID0/AD3/GPIO3B

AD INtput or GPI

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D
EN DFAN1/DA1/GPIO3D

IREF2/DA2

EN DFAN2/DA3/ GPIO3F

DA output or GPO

BEEP#/GPIO10/PWM2

ACOFF/GPIO18/PWM4

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

ADB0/D0
ADB1/D1
ADB2/D2

Data

ADB3/ D3

BUS

ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7

KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6

KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

SELIO2#/ GPIO43

SELIO#/ GPIO50

FRD#/RD#

FWR#/WR#

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ECTHERM#/GPIO11

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

AGND

KB910L_LQFP144

77

ECAGND

KBA7/A7
KBA8/A8
KBA9/A9

BUS

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

71
72
73
74

76
78
79
80

25
27
30
31
32
33

91
92
93
94
95
96

125
126
128
130
131
132
133
134
111
112
113
114
115
116
117
118
119
120
121
122
123
124
110
109
108
107
106
98

84
97
135
136
144

41
43
29
36
45
46

81
82
83
137
142
143

1

C339

2

1000P_0402_50V7K

0.1U_0402_16V4Z

C340

1

2

GATEA20
KBRST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
PM_BATLOW#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

SD_CLK_OE#
EC_DIS_INTMIC

EC_EXTTS0#
VCCP_PWRGD
DIGRST#
SSBTN#
DIGISUSP
USBEN#
EC_SLP_S4#
FPR_PWRON#
GIGALAN_RST#
BDID0
BDID1
BDID2
PROJECTID
PRSNT1#
PRSNT2#

SMB_EC_DA2
SMB_EC_CK2
SMB_EC_DA1
SMB_EC_CK1

EC_TXD
AUDIO_PWR_ON
PWR_LED#
KSI_USER#
CHARGE_LED#
BATT_LED#
MUTE#
WL_BTN#
SYSON

EC_RSMRST#
BKOFF#
EC_SLP_S3#
ICH_PWRGD
EC_SLP_S5#
EC_SMI#
EC_SWI#
BTDIS#-BTON
SUSP#
EC_PBTNOUT# WLOFF#
PME#

CRY2

FSEL#
FRD#

EC_SMI#

KBA1
KBA4
KBA5

PRSNT1#
PRSNT2#

1000P_0402_50V7K

1

1

C341

2

U27

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

63

KSI0/GPIO30

64

KSI1/GPIO31

65

KSI2/GPI032

66

KSI3/GPIO33

67

KSI4/GPIO34

68

KSI5/GPI035

69

KSI6/GPIO36

70

KSI7/GPIO37

47

KSO0/GPIO20

48

KSO1/GPIO21

49

KSO2/GPIO22

50

KSO3/GPIO23

51

KSO4/GPIO24

52

KSO5/GPIO25

53

KSO6/GPIO26

54

KSO7/GPIO27

55

KSO8/GPIO28

56

KSO9/GPIO29

57

KSO10/GPIO2A

58

KSO11/GPIO2B

59

KSO12/GPIO2C

60

KSO13/GPIO2D

61

KSO14/GPIO2E

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

+5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C342

2

Host

INTERFACE

key Matrix

scan

BATT_TEMP
BATT_OVP
DS_DOCKED_ID
CHARGER_THERM

DAC_BRIG
EN_DFAN1
IREF
EN_DFAN2

EC_INVT_PWM
BEEP#
PDCT
ACOFF
FAN_SPEED1
FAN_SPEED2

WLAN_LINK_WL
WLAN_ACTIVE_WL
WLAN_LED
LAN_PWR_ON
TPM_LPCPD#
CARD_DET_W_EC#

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

SYSPOK
PROCHOT#
FRD#
FWR#
FSEL#

EC_ON
ACIN
EC_THRM#
ON/OFF
DOCKEN

LAN_RST#
FSTCHG
VR_ON
ENABKL
VRMPWRGDCRY1
ROTA90#

ROTA90#

BATT_TEMP <33>
BATT_OVP <37>
DS_DOCKED_ID <31>
CHARGER_THERM <37>

DAC_BRIG <14>
EN_DFAN1 <31>
IREF <34>
EN_DFAN2 <20>

EC_INVT_PWM <14>
BEEP# <25>
PDCT <14>
ACOFF <34>
FAN_SPEED1 <31>
FAN_SPEED2 <20>

WLAN_LINK_WL <22>
WLAN_ACTIVE_WL <22>
WLAN_LED <29>
LAN_PWR_ON <23>
TPM_LPCPD# <27>
CARD_DET_W_EC# <21>

SYSPOK <39>
PROCHOT# <5>
FRD# <29>
FWR# <29>
FSEL# <29>

EC_ON <29>
ACIN <34,35>
EC_THRM# <18>
ON/OFF <29>
DOCKEN <15>
WLOFF# <22>

LAN_RST# <18>
FSTCHG <34>
VR_ON <39>
ENABKL <10,14>
VRMPWRGD <8,13,18>
ROTA90# <31>

+3VALW

12

R275
10K_0402_5%

2

ADB[0..7]

KBA[0..19]

C346

12

10P_0402_50V8J

C347

10P_0402_50V8J

Y6

32.768K +-10PPM Q13MC20610009

1 2

12

R284
0_0603_5%

1 2

BATT_TEMP
BATT_OVP ECAGND

DS_DOCKED_ID

ADB[0..7] <29>

1 2

C334

1 2

C335

1 2

C336

1 2

R270 4.7K_0402_5%

CRY1

12

R283
20M_0603_5%

CRY2

ECAGND

0.01U_0402_16V7K

0.01U_0402_16V7K

ECAGNDDS_DOCKED_ID

0.01U_0402_16V7K

+3VALW

12

R326

R327

10K_0402_5%

@

Version5 is MP Board ID

BDID0

KBA[0..19] <29>

BDID1
BDID2
PROJECTID

R316

R259

1K_0402_5%

@

1 2

1K_0402_5%

1 2

R157

BDID2 BDID1 BDID0 Version

000
00
00

1

0

11
00

1

01

1
11
111

Project ID PecosBandera

0

1

1
2
3
4
5
6

0

7

0
1

Compal Electronics, Inc.(KunShan)

Title

ENEKB910L

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

@

12

R325

10K_0402_5%

R70

1K_0402_5%

@

1 2

Phase

EVT1

EVT2

DVT1

DVT2

PVT

MP

28 48Friday, June 17, 2005

12

10K_0402_5%

1K_0402_5%

1 2

of

X5.0

http://hobi-elektronika.net

5

4

3

2

1

TOP VIEW(HSS111)

http://hobi-elektronika.net

+3VS

HSS110 reverse with HSS111

1234

PHDD_LED#<20>

D D

common open

SW1

1 2

HSS111_4P

22K_0402_5%

EC_ON<28>

C C

SMB_EC_CK1<5,20,28,33>

SMB_EC_DA1<5,20,28,33>

ON/OFFBTN#

+3VALW

12

R294

R295

EC_ON ECON

22K_0402_5%

1 2

C351

0.1U_0402_16V4Z

1 2

SMB_EC_CK1
SMB_EC_DA1

+3VALW

+3VALW

12

R290

D10

1

DAN202U_SC70

8
7
6
5

AT24C16AN-10SI-2.7_SOP

EC I2C Bus Address:
24C164: 1011xxx R/W#
24C16: 1010xxx R/W#

100K_0402_5%

ON/OFF

3

51_ON#

2

13

Q22

22K

2

22K

DTC124EK_SOT23

WHEN R=33K,Vbe=0.8V

WHEN R=0,Vbe=1.35V

16K

U29

A0

VCC

A1

WC
SCL

A2

SDA

GND

1
2
3
4

+3VALW

Power BTN

1

C350
1000P_0402_50V7K

2

12

R296
100K_0402_5%

ON/OFF <28>
51_ON# <33>

12

D11
RLZ20A_LL34

PME#<28>

WLANPME#<22>

LAN_PME#<23>

SDC_PME#<21>

INT_MIC2

INT_MIC2<25>

1000P_0402_50V7K

1 2

R336 100_0402_5%

1 2

R291 100_0402_5%

1 2

R292 100_0402_5%

1 2

R388 100_0402_5%

C349

2.2U_0805_16V4Z

1 2

C391

+3VALW

12

R289

@

10K_0402_5%

PCIPME#

1

1

2

2

R319

1 2

0_0402_5%

L33

FCM2012C-800_0805

1 2

C231
100P_0402_50V8J

R420

1K_0402_5%

1 2

1

C234
1U_0603_10V4Z

2

INT_MIC2_C INT_MIC2_L

FBM-11-160808-700T_0603

ICH_PWRGD<18,28>

EC_FLASH#<18>PCI_PME# <16>

FWR#<28>

47K

10K

Q23

S

Q29

DTA114YKA_SC59

1 3

EC_DIS_INTMIC

G

2

13

D

+3VALW

1 2

R374
0_0402_5%

1 2

1 3

R297
100K_0402_5%

2

L30

1 2

EC_DIS_INTMIC<28>

ICH_PWRGD

EC_FLASH# EC_FLASH_T#

2N7002_SOT23

FWR#

D

@

Q21

S

AO3413_SOT23

G

2

+3VALW

2

I0

1

I1

1 2

R373 0_0402_5%@

KSI0<28>
BATT_LED#<28>
KSI1<28>
CHARGE_LED#<28>
KSI2<28>

KSI3<28>
PWR_LED#<28>
KSI4<28>
WLAN_LED<28>
KSI5<28>
BT_LED<22>
KSI6<28>
KSI7<28>

KSI_USER#<28>
SDLED<21>

INTMIC2

5

U30

P

4

O

G

TC7SH32FU_SSOP5

3

+3VALW
VDDA

ALS/MIC1/FPR/irDA/WLBTN/SSBTN CONN.

JP15

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21
22

R308
0_0402_5%

1 2

EC_DIS_INTMIC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21
22

IPEX_20143-020E

@

Q24

D

S

1 3

INTMIC1

AO3413_SOT23

G

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C366

1 2

C361

Q34

AO3413_SOT23

S

G

1

1

2

2

D

+3VS_FPR

13

2

L32

1 2

FCM2012C-800_0805
C229
100P_0402_50V8J

+3VS

B B

FPR_PWRON#<28>

INT_MIC1<25>

A A

2.2U_0805_16V4Z

INT_MIC1

1000P_0402_50V7K

5

FPR_PWRON#

+3VS

VDDA

SMB_EC_DA1<5,20,28,33>

SMB_EC_CK1<5,20,28,33>

USBP2+<18>
USBP2-<18>

WL_BTN#<28>

SSBTN#<28>
IRRX<30>

IRTXOUT<30>
IRMODE<30>

R206

1K_0402_5%

1 2

1

C144
1U_0603_10V4Z

2

USBP2+
USBP2-

WL_BTN#
SMB_EC_DA1

SMB_EC_CK1
SSBTN#
IRRX

IRTXOUT
IRMODE

INTMIC1

L31

1 2

FBM-11-160808-700T_0603

EC_DIS_INTMIC<28>

4

BIOS/B Conn

JP30

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#

BIOS_RST#

KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1 KBA0

@

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

HRS_DF23C-40DS-0.5V

TOP View

3

KBA17

KBA19
KBA10

ADB7
ADB6
ADB5
ADB4

ADB3
ADB2
ADB1
ADB0
FRD#

FSEL#

KBA[0..19]<28>

+3VALW

FSEL#<28>

139

FRD#<28>

240

POP in 43132626003

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#
FRD#
FWE#

U31

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

MX29LV008BBTC-70_TSOP40

2

1@

VCC0
VCC1

READY/BUSY#

GND0
GND1

RP#

NC0
NC1

31
30

ADB0

25

D0

ADB1

26

D1

ADB2

27

D2

ADB3

28

D3

ADB4

32

D4

ADB5

33

D5

ADB6

34

D6

ADB7

35

D7

10
11

NC

12
29
38

23
39

1 2

R299 10K_0402_5%

BIOS_RST#

Compal Electronics, Inc.(KunShan)

Title

BIOS ROM/IO PORT

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

FWE#

ADB[0..7] <28>

SW/LED/MIC2

KSI0
BATT_LED#
KSI1
CHARGE_LED#
KSI2
HDD_LED#
KSI3
PWR_LED#
KSI4

WLAN_LED

KSI5
BT_LED
KSI6
KSI7

KSI_USER#
SDLED

Top view

JP14

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

23

23

24

24

25

25

26

26

IPEX_20143-020E

+3VALW

1

C352

0.1U_0402_16V4Z

2

1

1

20

X5.0

of

29 48Friday, June 17, 2005

5

4

3

2

1

http://hobi-elektronika.net

D D

+3VS

+3VS

1

C354

0.1U_0402_16V4Z

C C

0.1U_0402_16V4Z

2

33_0402_5%

22P_0402_50V8J

Strap pin Pin # Description

BADDR 33

1

C355

1000P_0402_50V7K

2

12

R303

@

1

C358

@

2

22P_0402_50V8J

1

C356

4.7U_0805_10V4Z

2

PLT_RST#<8,16,20,27,28>

CLK_PCI_SIOCLK_14M_SIO

12

R304

@

33_0402_5%

1

C359

@

2

BASE Address Selection

"0": 2E~2F (Default)

"1": 4E~4F

1

C357

2

PLT_RST# PLT_RST_R#

R301 22_0402_5%

1 2

LPC_AD0<17,27,28>
LPC_AD1<17,27,28>
LPC_AD2<17,27,28>
LPC_AD3<17,27,28>

LPC_FRAME#<17,27,28>

LPC_DRQ#0<17>

SUS_STAT#<18,27>
PM_CLKRUN#<18,21,22,23,27>

CLK_PCI_SIO<13>

CLK_14M_SIO<13>

4.7K_0402_5%

SIRQ<18,27,28>

R305

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ#0

SUS_STAT#
PM_CLKRUN#

CLK_PCI_SIO
SIRQ

CLK_14M_SIO

LPC47N217_SYSOPT

12

U32

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLOCK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217_STQFP64

LPC I/F

GPIO

POWER

RXD1

TXD1

DSR1#

RTS1#
CTS1#

DTR1#

RI1#

SERIAL I/F

DCD1#

IRRX2

FIR

IRTX2

IRMODE/IRRX3

INIT#

SLCTIN#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

PE

BUSY

PARALLEL I/F

ACK#

ERROR#

ALF#

STROBE#

VTR
VCC
VCC
VCC
VCC

SIO_RXD

62

SIO_TXD

63

DSR1#

64

RTSB#

1
2

DTRB#

3

RI1#

4

DCD1#

5

IRRX

37

IRTXOUT

38

IRMODE

39
41

42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

7
11
26
45
54

+3VALW

+3VS

SIO_RXD <14>
SIO_TXD <14>

RTSB# <14>
DTRB# <14>

IRTXOUT <29>
IRMODE <29>

R302

DSR1#

R318 10K_0402_5%

RI1#

R365 10K_0402_5%

DCD1#

R366 10K_0402_5%

IRRX <29>

1K_0402_5%@

12
12
12

+3VS

B B

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

LPC47N217/FIR

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

30 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

DOCK_IN

L47

D D

C C

DOCKHP_OUT_L<25>
DOCKHP_OUT_R<25>

1 2

FBM-L18-453215-900LMA90T_1812

DOCKHP_OUT_L HP_OUT_L_R
DOCKHP_OUT_R

DOCK_MIC<25>

1

C373

2

1 2

R29 5.1K_0402_5%

R357 0_0603_5%
R358 0_0603_5%

R359 0_0603_5%

DOCK_CINDOCK_IN

1

C411

2

0.1U_0603_25V7K

3VDDCDA_R<15>

3VDDCCL_R<15>

FAN_SPEED1<28>
EN_DFAN1<28>
CLKREQB#<13>

PRSNT2#<28>
PRSNT1#<28>

ROTA90#<28>
LAN_WAKE<18>

GIGALAN_RST#<28>

DIS_INTMIC<25>

HP_PLUG#<25,26>
DS_DOCKED_ID<28>

+5VS

0.1U_0603_25V7K

+3VALW

1 2
1 2

EMI request

Dock covert board

B B

DOCKING BTB Conn

JP29

1 2
3 4
5 6
7 8
9 10

12

11

14

13

16

15

18

17

20

19

222421
23
25

26
27

28
29

30
31

32
33

34
35

36
37

38
39

40
41

42
43

44
45

46
47

48
49

50
51

52
53

54
55

56
57

58
59

60
61

62
63

64
65

66
67

68
69

70
71

72
73

74

7675

78

77

80

79

82

81

84

83

86

85

88

87

90

89

92

91

94

93

96

95
979998

100

HANNS_802PVS-100415R-P

VDDA

3VDDCDA_R
3VDDCCL_R

FAN_SPEED1
EN_DFAN1
CLKREQB#

PRSNT2#
PRSNT1#

LAN_WAKE
GIGALAN_RST#
DIS_INTMIC

HP_PLUG#
DS_DOCKED_ID

HP_OUT_R_R
DOCK_MIC_RDOCK_MIC

12

ICH_SMBDATA
ICH_SMBCLK

CLKREQA#
PCIE_TXP2

PCIE_TXN2
PCIE_RXP2

PCIE_RXN2
CLK_PCIE_P2

CLK_PCIE_N2
CLK_PCIE_P0

CLK_PCIE_N0
PCIE_TXN0

PCIE_TXP0
PCIE_RXN0

PCIE_RXP0
USBP7-

USBP7+
USBP4+

USBP4­USBP6-

USBP6+
USB_OC#7

USB_OC#6ROTA90#
USB_OC#4

CRT_B_DOCK_R
CRT_HSYNC_DOCK
CRT_VSYNC_DOCK
M_SEN#

ICH_SMBDATA <12,13,18>

ICH_SMBCLK <12,13,18>

+3VS

CLKREQA# <13,15>
PCIE_TXP2 <18>

PCIE_TXN2 <18>
PCIE_RXP2 <18>

PCIE_RXN2 <18>
CLK_PCIE_P2 <13>

CLK_PCIE_N2 <13>
CLK_PCIE_P0 <13>

CLK_PCIE_N0 <13>
PCIE_TXN0 <18>

PCIE_TXP0 <18>
PCIE_RXN0 <18>

PCIE_RXP0 <18>

USBP7- <18>
USBP7+ <18>

USBP4+ <18>
USBP4- <18>

USBP6- <18>
USBP6+ <18>

USB_OC#7 <18>
USB_OC#6 <18>
USB_OC#4 <18>

R356 0_0603_5%
R355 0_0603_5%
R354 0_0603_5%

12
12
12

CRT_HSYNC_DOCK <15>
CRT_VSYNC_DOCK <15>
M_SEN# <15,18>

CRT_R_DOCKCRT_R_DOCK_R
CRT_G_DOCKCRT_G_DOCK_R
CRT_B_DOCK

CRT_R_DOCK <15>
CRT_G_DOCK <15>
CRT_B_DOCK <15>

VDDA

1

C414

0.1U_0402_16V4Z

2

1

C415

0.1U_0402_16V4Z

2

Dock BTB conn(MB side)

TOP VIEW

2 100

199

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+3VALW

1

C412

0.1U_0402_16V4Z

2

+5VS

1

C369

0.1U_0402_16V4Z

2

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

1

C413

0.1U_0402_16V4Z

2

1

C370

0.1U_0402_16V4Z

2

Docking conn/other conn

Bandera-EAX00-LA2581

1

of

31 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

D D

1

C249
22U_1206_16V4Z_V1

2

C C

B B

1

C343
22U_1206_16V4Z_V1

2

1

C360
22U_1206_16V4Z_V1

2

+1.5VALW +1.5VS

U34

8

D

7

D

6

D

5

D

AO4422_SO8

1

C377
10U_1206_6.3V7K

2

+3VALW

U37

8

D

7

D

6

D

5

D

1

AO4422_SO8
C392
10U_1206_6.3V7K

2

U38

8

D

7

D

6

D

5

D

AO4422_SO8

1

C397
10U_1206_6.3V7K

2

1.35A

1

S

2

S

3

S

4

G

1

C378

0.1U_0402_16V4Z

2

+3VALW to +3VS Transfer

+3VS

1

S

2

S

3

S

4

G

1

C393

0.1U_0402_16V4Z

2

+5VALW to +5VS Transfer

+5VS+5VALW

1

S

2

S

3

S

4

G

1

C398

0.1U_0402_16V4Z

2

+1.5VALW to +1.5VS Transfer

1

C374

10U_0805_10V4Z

2

1

C389
10U_0805_10V4Z

2

1

C394

0.1U_0402_16V4Z

2

1

C375

0.1U_0402_16V4Z

2

R315 100K_0402_5%

13

D

Q25

2

G

2N7002_SOT23

S

1

C390

0.1U_0402_16V4Z

2

1 2

R324 100K_0402_5%

13

D

Q39

SUSP

2

G

2N7002_SOT23

S

1

C69

+

220U_D2_6.3VM_R25

2

1 2

R328 100K_0402_5%

13

D

Q43

SUSP

2

G

2N7002_SOT23

S

1 2

SUSP

+12VALW

+12VALW

+12VALW

+5VS +3VS +2.5VS

12

R309
470_0402_5%

13

D

Q26

SUSP SUSP SUSP

2

G

2N7002_SOT23

S

12

R317
470_0402_5%

13

D

Q33

2

G

2N7002_SOT23

S

+12VALW

12

R321
100K_0402_5%

SYSON#

13

D

Q38

SYSON<28,38> SUSP#<23,25,28,33,37,38>

2

2N7002_SOT23

G

S

12

13

D

S

+1.5VS

12

13

D

S

R310
470_0402_5%

Q27

2

G

2N7002_SOT23

R313
470_0402_5%

Q30

SUSP

2

G

2N7002_SOT23

SUSP<37>

SUSP

2

G

+12VALW

12

13

D

S

12

R311
470_0402_5%

13

D

Q28

2

G

2N7002_SOT23

S

+0.9VS+1.8V

12

R314
470_0402_5%

13

D

Q31

2

G

2N7002_SOT23

S

R320
100K_0402_5%

Q37
2N7002_SOT23

SUSPSYSON#

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

DC-DC

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

32 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

BATT+

12

PR2

10_1206_5%

12

PD4
RLZ24B_LL34

S

G

2

D

13

DOCK_IN

PD5

RB160L-40_SOD106

12

B+

VSB

PC1

0.01U_0603_50V7K

HCB4532K-800T90_1812

12

BATT+

PL2

1 2

1000P_0402_50V7K

VSB

PR131
200_0805_5%

PC2

250263MR007G102ZL_7P

1N4148_SOD80

1N4148_SOD80

12

51_ON#<29>

2

12

PC119
1U_0805_25V4Z

12

PJP1

PD41

PD19

PR133

100K_0402_5%

1 2

PR134

22K_0402_5%

PU11
G920AT24U_SOT89

IN

PC3

560P_0402_50V7K

+12VALW

PR9

1 2

PQ3

2

G

1 2

PR21

100K_0402_5%

2

PQ6

DTC115EUA_SC70

P1

12

PR8

22.1K_0402_1%

1 2

PR13

57.6K_0402_1%

1 2
13

D

S

PR19

10K_0402_5%

12

PC4

12P_0402_50V8J

PJPC1

MOLEX_53780-0290

12

13

PJPD1

D D

C C

B B

1

3

2

SINGA_2DC-S026-B07

4 5

PR11

43.2K_0402_1%

12

PR12

40.2K_0402_1%

12

PH1

100K_0603_1%_TH11-4H104FT

2

1

3

PD13

DAN217_SC59

0.1U_0603_25V7K

SPOK<35>

SUSP#<23,25,28,32,37,38>

P1

22.1K_0402_1%

12

RHU002N06_SOT323

PC9

SPOK

SUSP#

PL1

FBM-L18-453215-900LMA90T_1812

1 2

12

12

PC5

12P_0402_50V8J

12

PC6

560P_0402_50V7K

Bridge Battery charge circuit

PR22
442_0402_1%

1 2
31

1
2

2

B

2

B

E

PQ1

C

2SA1037AK_SC59

1

C

PQ2
2SC2412K_SC59

E

3

PD6
1SS355_SOD323

1 2

PACIN<34,36>

100K_0402_5%

2

G

PR10

7.32K_0402_1%

1 2

PR15

2

13

D

PQ7
RHU002N06_SOT323

S

IRLML5103_SOT23

1 2

13

DTC115EUA_SC70

PQ4

PQ5

BATT_A+

BATT_A+

1
2
3
4
5
6
7

12

12

1538VCC

1 2

3

OUT

GND

1

PJPB1 battery connector
SMART

Battery:

1.BAT+

2.ID

3.B/I

4.TS

5.SMD

6.SMC

7.GND

PR4
1K_0402_5%

12

PC121

0.22U_1206_25V7K

RTCVREF

12

PC120

4.7U_1206_25V6K

1K_0402_5%

1 2

12

PR5 6.49K_0402_1%
PR6 100_0402_5%
PR7 100_0402_5%

PQ27
TP0610K_SOT23

2

1 2

PR132

560_0402_5%

PR3

1 2
1 2
1 2

13

BATT_TEMP

DOCK_IN

1 2

BATT_TEMP <28>

PD20
1N4148_SOD80

1 2
12

PR130
33_1206_5%

VS

12

PC118

0.1U_0603_25V7K

RTC charge circuit

PR129

560_0402_5%

CHGRTC

+3VALW

SMB_EC_DA1 <5,20,28,29>

SMB_EC_CK1 <5,20,28,29>

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Vin detec and bridge BATT

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

33 48Friday, June 17, 2005

X5.0

5

19V/2.63A(50W)
Iadp=2.63A*0.9 = 2.37A

1
2
36

4

12

PC141

0.1U_0603_25V7K

12

13

D

S

ACON <36>

@

158K_0603_1%

P2

PACIN

PR175

12

PR167

100K_0402_1%

AO4407_SO8

1
2
3 6

4

PR159

200K_0402_1%

215K_0402_1%

PR164

12

12

PC144

0.1U_0402_16V7K

PR172

10K_0402_5%

12

PQ40

DTC115EUA_SC70

DOCK_IN

D D

12

47K_0402_5%

13

D

PQ37

RHU002N06_SOT323

S

ACOFF#

PACIN<33,36>

ACIN

DTA144EUA_SC70

2

1SS355_SOD323

1 2

1 2

PR30

47K_0402_5%

13

PR158

2

G

C C

ACIN<28,35>

B B

PQ18

47K

2

47K

PQ25

DTC115EUA_SC70

RHU002N06_SOT323

PD28

PR171

22K_0402_5%

1 2

12

PD31
RLZ4.3B_LL34

PQ11
AO4407_SO8

8
7

5

1 3

150K_0402_5%

PQ39

PR162

2

G

CC:1.8A

1.8A=VICTL/Vrefin * 0.075/RS2 (PR165)

1.8A=VICTL/3.33V * 0.075/0.015

->VICTL=1.198V
EC setting IREF=3.3V
ICTL_V=3.3V*34.8K/(61.9K+34.8K)=1.188V

PQ16

PC142

12

1908LDO

4

8
7

5

12

1U_0603_10V6K

IREF<28>

12

13

3

Vcls=Vref*PR167/(PR167+PR164)= 4.096V*100K/157.6K= 1.3V
Iadp=(Vcls/Vref)*0.075/R_sense

http://hobi-elektronika.net

= 1.3V/4.096V * 0.075/0.01ohm
=2.38A

P3

DOCK_IN

1SS355_SOD323

PR150

12

0_0402_5%

56.2K_0603_1%

34.8K _0402_1%

1908LDO

12

PR173

100K_0402_1%

2

FSTCHG<28>

PACIN

12

PC158

0.1U_0603_25V7K

@

PD25

PR166

1 2

9.31K_0402_1%

PR168

12

PR190

PR180

150K_0402_1%

1 2

PR194

681K_0603_1%

12

12

12

PR177

0_0402_5%

1 2

100K_0402_5%

DOCK_IN

12

12

PR135

1 2

0.01_2512_1%

12

PC143

0.1U_0603_25V7K

15K_0402_1%

1 2

PR151

@

0_0402_5%

PC149

0.01U_0402_16V7K

PR193

1 2

PR183
20K_0402_1%

12

PR184

0_0402_5%

B+

12

PC159

0.1U_0603_25V7K

@

VCTL

12

PR169

1 2

12

PC154

0.1U_0402_16V7K

HCB4532K-800T90_1812

1 2

PU13
MAX1908ETI_QFN28

1

DCIN

17

CELLS

4

REF

3

CLS

12

REFIN

15

VCTL

13

ICTL

11

ACOK#

8

SHDN#

10

ACIN

9

ICHG

28

IINP

7

CCV

CCI

6

PR174

1K_0402_1%

12

PC152

0.001U_0402_50V7M

PL16

CCS

5

MAX1908-CCS

PC153

0.001U_0402_50V7M

1 2

12

PGND

GND

20

14

CV:12.6V
CELLS setting Float = 3 cells
GND= 2 celss
Vrefin= 4 celss
VCTL= 1908LDO, setting Vbatt =4.2V x number of cells, 4.2V x 3 = 12.6V

PR178

1 2

10K_0402_5%

12

PC155

0.1U_0402_16V7K

L->H (PR194//PR183)=19.43K
Vin*19.43K/(PR180+19.43K)>2.048V, Vin>17.858V (typ.)

H->L hysteres 20mV

12

PC160

PC139

4.7U_1206_25V6K

27

CSSP

26

CSSN

25

DHI

23

LX

21

DLO

24

BST

22

DLOV

2

LDO

19

CSIP

18

CSIN

16

BATT

12

PC140

4.7U_1206_25V6K

4.7U_1206_25V6K

1908LDO

1 2

BATT+

PC151

1U_0603_10V6K

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

AO4912_SO8

1 2

PR14 0_0402_5%

33_1206_5%

PQ17

S1/A

12

PR170

2

1

Charger

PQ15
AO4407_SO8

1
2
3 6

PR161

10K_0402_5%

ACOFF#

PQ36

1

D2

2

D2

3

G1

DTC114EKA_SC59

4

16UH_D104C-919AS-160M_3.7A_20%

PC145

0.1U_0603_25V7K

1 2
12

PD27
1SS355_SOD323

PC150

1 2

1U_0805_25V4Z

1 2

4

47K_0402_5%

1 2

1 2
13

10K

10K

PL17

PR160

2

8
7

5

12

PD32
RLZ22B_LL34

PD24
1SS355_SOD323

PD26

1 2

1 2

1SS355_SOD323

PR165

0.015_2512_1%

1 2

DOCK_IN

ACOFF <28>

BATT+

12

12

PC146

PC147

4.7U_1206_25V6K

12

PC148

4.7U_1206_25V6K

4.7U_1206_25V6K

a). PR180//PR183=17.65K, Va=3.5V*17.65K/(681K+17.65K)=0.088V

A A

b).PR194//PR183=19.43K, Vin*19.43K/(150K+19.43K)<4.096V/2-20mV-0.088V (ACOK# L->H)
Vin< 16.92V (tpy.)

L->H 17.858V(typ.)
H->L 16.92V(typ.)

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Charger

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

34 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

B+

D D

PJP10

@

3MM

2 1

B+++

@

12

12

PC36

PC37

2200P_0402_50V7K

C C

10UH_D104C-919AS-100M_4.5A_20%

+3VALWP

PC48

1

B B

+

2

220U_D2_6.3VM_R25

12

PC263

PD10

2 1

1U_0603_16V6K

PL6

PR55

SKUL30-02AT_SMA

1 2

3.16K_0402_1%

+3VALWP Choke DCR = 26.5m .
DCR'=26.5m *1.27K/(1.27+1.27)K=13.25m

Current limit Threshold Min.=80 mV Mx.=120mV.

T off=1/333k*(1-3.3V/19V)=2.48us
Delta_I=3.3V*2.48us/10uH=0.818A

OCP Min.= 80mV/13.25m - 0.409A= 5.63A min
OCP Max.=120mV/13.25m - 0.409A = 8.65A Max

PC34

4.7U_1206_25V6K

12

PR48

12

PC47

100P_0402_50V8J

12

PR395
10K_0402_5%

12

PC44

47P_0402_50V8J

1 2

PR46 1.27K_0603_1%

1.27K_0603_1%

1M_0402_1%

1 2

PQ12

1

D2

2

D2

3

G1

4

S1/A

AO4912_SO8

ACIN<28,34>

0.1U_0603_25V7K

D1/S2/K
D1/S2/K
D1/S2/K

PR47

47K_0402_5%

1 2

G2

12

PC45

0.47U_0603_16V7K

620_0402_5%

1 2

PR52

10K_0402_5%

@

300K_0402_5%

PR59

BST31

8
7
6
5

LX3

12

PR51

1 2

PR54

VS

12

12

PR390

0_0402_5%

DL3

12

PC54

@

0.047U_0805_50V0K

1SS355_SOD323

12

12

PR44
0_0402_5%

12

PC49
680P_0402_50V7K

PD9

PR381

10_1206_5%

12

PC41

0.1U_0603_25V7K
PU4

25

BST3

27

DH3

26

LX3

24

DL3

1

CSH3

2

CSL3

3

FB3

10

SKIP#

23

SHDN#

7

TIME/ON5

28

RUN/ON3

PR382

220K_0402_5%

12

PC53
1U_0603_16V6M

VS

1 2
12

22

V+

VL

12

2

3

PD8

DAP202U_SOT323

1

VL +12VALWP

12

PC38

4.7U_0805_10V4Z

21

4

12OUT

VL

5

VDD

18

BST5

16

DH5

17

LX5

19

DL5

20

PGND

14

CSH5

13

CSL5

12

FB5

15

SEQ

9

REF

6

SYNC

11

RST#

GND

MAX1902EAI_SSOP28

8

MAINPWRON <6,17,36>

BST51

12

PC42

4.7U_1206_25V6K

1 2

PR389

@

0_0402_5%

PR56
0_0402_5%

1 2

SPOK <33>

0_0402_5%

VL

12

0.1U_0603_25V7K

PR45

1 2

BST5

2.5VREF

PC50

4.7U_0805_10V4Z

PC35

1 2

12

DH5

PR391
0_0603_5%

LX5

DL5

PC46

0.47U_0603_16V7K

8
7
6
5

12

PR57

PVT->MP Material Change:
PT1 from SH136100020
change to SH000004V80

PQ13

G2
D1/S2/K
D1/S2/K
D1/S2/K

AO4912_SO8

10K_0402_1%

D2
D2
G1

S1/A

12

PR53
698_0402_1%

12

12

PR396
10K_0402_5%

1
2
3
4

1 2

1.54K_0402_1%

12

PC52
100P_0402_50V8J

PC33
470P_0805_100V7K

1 2

PR43

22_1206_5%

SNB FLYBACK

12

PR50

T off=1/333k*(1-5V/19V)=2.21us
Delta_I=5v*2.21us/4.7uH=2.35A

B+++

12

PC39

2200P_0402_50V7K@

SKS10-04AT_TSMA

12

PC40

4.7U_1206_25V6K

PD11

+3.3V/+5V/+12V

PC32

10U_1210_25V6K

1 2

12

PD7
EC11FS2_SOD106

PT1

1 4

12

PC43
47P_0402_50V8J

12

PR49
2M_0402_1%

2 1

10UH_SDT-1050P-100-118_3.5A_30%

3 2

PC51

12

PC264

1U_0603_16V6K

+5VALWP

1

+

2

220U_D2_6.3VM_R25

Current limit Threshold Min.=80 mV Mx.=120mV.

A A

OCP Min.= 80mV/11.12m-2.35A/2=6.02A min
OCP Max.=120mV/11.12m-2.35A/2= 9.62A Max

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+3V/+5V/+12VALW

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

35 48Friday, June 17, 2005

X5.0

5

4

3

2

1

@

PJP11

3MM

PC249

560P_0603_50V7K

21

12

PR318

10K_0603_0.1%

1 2

PC260

@

12

PC250

2200P_0402_50V7K

PR314
91K_0402_5%

12

PR317
0_0402_5%

0.01U_0402_16V7K

1 2

1

PC251
10U_1206_25V6M

2

PC253

0.1U_0603_25V7K

12

12

PC259

B+

0.1U_0603_25V7K

D D

+3VALWP

C C

Iimit=9.6/RILIM*(100+Rsense)/Rds (on)
Toff=T(1-Vo/Vin)=3.33us(1-1.5V/19V)=3.067us

http://hobi-elektronika.net

12

PR313
10_1206_5%

12

1

PU16

VIN

4

ILIM

16

FPWM

3

EN

7

SS

2

PGOOD

VCC

BOOT

HDRV

LDRV

SW

ISNS

PGND

VSEN

VOUT

AGND

FAN5234QSCX_QSOP16

8

11

15

14

10

13

12

9

6

5

10_0402_5%

PC252
1U_0603_10V6K

1 2

0_0603_5%

PR340

2.74K_0603_1%

PR315

PR376

12

+5VALWP

12

21

PD47

EP10QY03

PC254

0.1U_0603_25V7K

12

1 2

PQ24

1

D2

2

D2

3

G1

4

S1/A

AO4912_SO8

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

4.7UH_FDV0630-4R7M_3.3A_20%

1 2

PL13

12

PC255

0.1U_0603_25V7K

12

PR316

680_0402_1%

12

PR320
1K_0402_1%

+1.5VALWP

1

+

PC257

2

220U_D2_4VM

Delta_I=Vo/L*Toff=1.5V/4.7uH*3.067us=0.9788A, 1/2*Delta_I=0.489A
Rsense=2k, RILM=100k, Rds (on) typ.=19.7m ohm, Max=24m ohm
Iimit min = 9.6/100k*(100+24m ohm * 1.3)-1/2 Delta_I=5.97A
Iimit Max = 9.6/100k*(100+19.7m ohm)-1/2 Delta_I=9.74A

12

1

O

PR18

2.2M_0402_5%

VS

LM393M_SO8

8

P

+

-

G

4

PR23

34K_0402_1%

66.5K_0402_1%

12

PU1A

3
2

12

12

PC13

1000P_0402_50V7K

PR26

B+

PR31

12

PR17
412K_0402_1%

PR24
47K_0402_5%

13

12

PR20
634K_0402_1%

12

PQ9
DTC115EUA_SC70

2

12

PC12
1000P_0402_50V7K

PACIN <33,34>

+5VALWP

12

PR25
140K_0402_1%

PRG++

PQ8

13

D

RHU002N06_SOT323

2

G

S

12

3

DOCK_IN

2

PD14

1N4148_SOD80

VIN+

12

1.5K_1206_5%

1 2

PR32

1.5K_1206_5%

1 2

PR33

1.5K_1206_5%

1 2

PR34

1.5K_1206_5%

1 2

Compal Electronics, Inc.(KunShan)

Title

+1.5VALWP

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

B+

of

1

36 48Friday, June 17, 2005

X5.0

VL

B B

100K_0402_1%

PD21

MAINPWRON<6,17,35>

ACON<34>

2
3

RB715F_SOT323

ACIN

PR16

1

12

PC10

12

PC11

0.1U_0603_25V7K

0.01U_0402_25V7Z

Precharge detector

Min. typ. Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

BATT ONLY

Precharge detector

Min. typ. Max.

A A

H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

5

VS

LM393M_SO8

8

P

+

7

O

-

G

4

4

PU1B

5
6

VL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

1

http://hobi-elektronika.net

+1.8VP

12

PR66

0_0402_5%

1 2

PC56
10U_1206_6.3V7K

2

G

LM358A_SO8

13

D

PQ14
RHU002N06_SOT323

S

PU14A

1

D D

SUSP<32>

C C

B B

BATT_OVP<28>

1K_0402_1%

8

P

0

G

4

PR65

220U_B2_2.5VM

VS

3

+

2

-

12

PR63
1K_0402_1%

12

PC60

@

12

PC156

0.01U_0402_25V4Z

12

PC59

0.1U_0603_25V7K

1

+

2

BATT+

12

12

OVP voltage
Li-3S : 13.5V
Batt-OVP=13.5v* 102K/(102K+357K)=3V

2
3
4

12

PC61
10U_1206_6.3V7K

PR181
357K_0603_0.5%

PR185
102K_0603_0.1%

PU5

VIN1VCNTL

NC

GND
VREF

NC

VOUT

NC

TP

APL5331KAC-TR_SO8

+0.9VSP

12

PC157

0.01U_0402_25V4Z

6
5
7
8
9

+3VALW

12

PC55
1U_0603_16V6K

+0.9VSP/2A

+3VALW

12

PC57

10U_1206_6.3V7K

SUSP#<23,25,28,32,33,38>

VL

PR152

PR394

47K_0603_5%

CHARGER_THERM<28>

1 2

10K_0402_1%

12

PC161

1000P_0603_50V7K

10KB_0603_1%_TH11-3H103FT

VS

PU14B

LM358A_SO8

5

+

0

6

-

PH2

7

PU6

VIN2VO

1

EN

5

GND

6

GND

G965-18P1U_SO8

12

12

GND
GND

3
4

ADJ

7
8

Del CPU OTP circuit , cause H/W implement this function

12

PR62

11K_0402_1%

12

PR64

10K_0402_1%

+2.5VSP/ 1A

+2.5VSP

12

PC58
22U_1206_6.3V6M

PJP2

@

2MM

+12VALWP

PJP3

@

+5VALWP

+3VALWP +3VALW

+1.8VP +1.8V

+2.5VSP

+VCCPP +VCCP

+0.9VSP

+1.5VALWP

3MM

PJP4

@

3MM

PJP5

@

3MM

PJP6

@

3MM

PJP7

@

3MM

PJP8

@

3MM

PJP9

@

3MM

21

+12VALW

21

+5VALW

21

21

21

+2.5VS

21

+0.9VS

21

21

+1.5VALW

Del PR377,PR378,PR379, PQ41,PR380

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

0.9VSP/1.5ALW/2.5V

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

37 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

12

@

PL10

1 2

@

PJP12

3MM

12

PC87

2200P_0402_50V7K

1 2

1 2

21

12

PC88

4.7U_1206_25V6K

12

PC99

@

4.7U_0805_6.3V6K

PR94
300_0402_1%

PR96

10K_0402_1%

PC89

4.7U_1206_25V6K

1

+

2

B+

+VCCPP

PC97

220U_D2_4VM

12

PC91

0.1U_0603_25V7K

25

BST1

26

DH1

27

LX1

24

DL1

28

CS1

1

OUT1

2

FB1

MAX8743EEI_QSOP28

11

ON1

8

B++++

MAX8743_VCC

PC92
1U_0805_50V4Z

4

V+

PU8

GND

OVP

23

12

6

SKIP

22

9

VCC

PGOOD

10

12

+5VALWP

1 2

PR86

20_0603_5%

21

VDD

UVP

19

BST2

18

DH2

17

LX2

20

DL2

16

CS2

15

OUT2

14

FB2

12

ON2

7
5

TON

13

ILIM2

3

ILIM1

REF

PR98

13.7K_0402_1%

PR100

13.3K_0603_1%

PC101

0.22U_0603_16V7K

12

PC86

4.7U_0805_6.3V6K

PR89

0_0402_5%

1 2

BST2.5A

12

12

BST2.5B

PR392

0_0603_5%

1 2

12

PR99

PC94

0.1U_0603_25V7K

12

12

PR182

100K_0402_1%

DL2.5

PR93 0_0402_5%

12

VCCP_PWRGD

100K_0402_1%

PQ20

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

AO4912_SO8

LX2.5

SUSP# <23,25,28,32,33,37>

+3VALWP

D2
D2
G1

S1/A

PR136
10K_0402_5%

1 2

1
2
3
4

VCCP_PWRGD <28>

4.7UH_FDV0630-4R7M_3.3A_20%

D D

12

12

S1/A

D2
D2
G1

PC81

4.7U_1206_25V6K

1
2
3
4

SYSON<28,32>

2

PC93

1 2

12

0.1U_0603_25V7K

PD15

1

DAP202U_SOT323

3

PR88

0_0402_5%

PR393

0_0603_5%

1 2

PR90

0_0402_5%

1 2

PC82

4.7U_1206_25V6K

PQ19

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

AO4912_SO8

+1.8VP

2 1

EP10QY03

+1.8VP OCP

1

+

2

PC95

220U_D2_4VM

12

PC96

@

4.7U_0805_6.3V6K

PR95

8.06K_0402_1%

1 2

12

PR97
10K_0402_1%

C C

PD48

@

B B

PL9

4.7UH_FDV0630-4R7M_3.3A_20%

1 2

Iimit=(VILM*0.1)/Rds(on) Delta I=1.155A
VILM=1.765V Rds(on) typ=19.7mOhm, max=24mOhm
Iimit Min=(1.765*0.1)*0.9/(24mOhm*1.3)+1/2 Delta I=5.66A
Iimit Max=(1.765*0.1)*1.1/(19.7mOhm*1.3)+1/2 Delta I=8.15A

VCCP OCP
Delta I= Vo/L*Toff, Toff=T*(1-Vo/Vin), T=1/255Khz
Toff= 1/255Khz * (1-1.05V/19V)=3.7uS
Delta I= 1.05V/4.7uH * 3.7uS =0.826A
Iimit=(VILM*0.1)/Rds(on)
VILM=2V Rds(on) typ=15.5mOhm, max=20mOhm
Iimit Min=(1.76*0.1)*0.85/(20mOhm*1.3)+1/2 Delta I=6.16A
Iimit Max=(1.76*0.1)*1.15/(19.7mOhm*1.3)+1/2 Delta I=8.31A

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

VCCP/1.8VP

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

38 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

CPU-CORE

PR103

NEG

VCC

10

VCC

BST

TON

TIME

DDO

PGND

GND

OAIN+

OAIN-

CSP

CSN

ILIM

9

PR128
10K_0603_1%

1 2

12

V+

DH

LX

DL

FB

10_0402_5%

1 2

PC102

0.22U_0402_10V4Z

30

1SS355_SOD323

VDD

31

1 2

PR108

2.2_0402_5%

34
33

32

40

29
39

27

28
11

17

100P_0402_50V8K

16
15
18

4700P_0402_25V7K

19

+VCC_CORE

26

D0

25

D1

24

D2

23

D3

22

D4

21

D5

4

S0

5

S1

6

S2

1

B0

2

B1

3

B2

35

SUS

20

DPSLP

7

SHDN

37

IMVPOK

36

SYSPOK

38

CLKEN

PR105

1.05K_0603_1%

1 2

13

POS

PU10

MAX1907EGL_QFN40

REF

CC

8

12

90.9K_0603_1%

REF

1 2

12

12

PC116

0.22U_0402_10V4Z

14

PR127

PR104

D D

PR106 0_0402_5%

PM_DPRSLPVR<18>
H_DPSLP#<5,17>

VR_ON<28>

SYSPOK<28>

CLKEN#<13>

1 2

PR107 0_0402_5%

1 2

PR109 0_0402_5%

1 2

PR110 0_0402_5%

1 2

PR111 0_0402_5%

1 2

PR114 0_0402_5%

1 2

PR117 0_0402_5%

1 2

PR118 0_0402_5%

1 2

PR120 0_0402_5%

1 2

PR121 0_0402_5%

1 2
1 2

PR124 0_0402_5%

PR80

1 2

0_0402_5%@

PR81

1 2

0_0402_5%

PR82

1 2

0_0402_5%@

CPU_VID0<6>
CPU_VID1<6>

CPU_VID2<6>
CPU_VID3<6>

CPU_VID4<6>

CPU_VID5<6>

C C

VRMPWRGD_P<18>

B B

PR119

10K_0402_5%

+3VS

1 2

100K_0603_1%

REF

47P_0402_50V8J

1 2

VCC

PC117

+5VS

12

PC103
1U_0603_16V6K

PD16

1 2
12

PC112

0.1U_0603_25V7K

1 2

CPULX

PR397 200K_0402_5%

1 2

PR398 200K_0402_5% @

1 2

PR115

1 2

100K_0603_1%

12

PC114

PC115

12

PR123

1K_0603_1%

1 2

200_0603_1%

200_0603_1%

CPU_B+

PR112
0_0402_5%

VCC
REF

12

PC113

2200P_0402_50V7K

12

PR125

12

PR126

12

PC108

0.1U_0603_25V7K

@

PJP13

3MM

RB051L-40_SOD106

10U_1206_25V6M

1

2

12

PC105

1

2

PL12

1 2

PD17
EC31QS04

PR116

510_0603_1%

PR122
1K_0603_1%

1 2

10U_1206_25V6M

PC104

10U_1206_25V6M

5

PQ21

D8D7D6D

S1S3G

S

IRF7821_S08

4

2

0.56UH_MPC1040LR56 23_21A_20%

5

PQ22

D8D7D6D

S1S3G

S

IRF7832_SO8

4

2

2200P_0402_50V7K

1

2

PC106

0.0015_2512_1%

12

PC107

12

PR113

12

Delta I=0.0528A REF MAX=2.01V*10K/(10K+90.2K)=0.2005V
REF Min=1.99V*10K/(10K+90.2K)=0.1986V
Iimit Max=0.2005V*10/1.485m +1/2
Delta=13.528

Iimit Max=0.1986V*10/1.515m +1/2
Delta=13.135

A A

B+

21

+VCC_CORE

12

PD18

D4

D2

D1

D3 D5 = 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

1

0

0

0

0

1

0

1

0

0

0

1

0

1

1

11

0

1

0

0

0

0

1

1

1

1

0

1

1

0

1

0

1

1

1

1

1

1

1

0

0

0

0

0

0

0

1

0

1

0

0

0

1

0

0

0

1

1

0

1

0

11

1

0

0

1

0

0

1

1

0

1

1

0

1

1

1

0

1

1

1

1

1

1

D5 = 1

D0

0

1.196

1.180

1

0

1.164

1

1.148

1.132

0

1

1.116

1.100

0

1.084

1

1.068

0

1

1.052

1.036

010

1

1.020

1.004

0

1

0.988

0.972

0

0.956

1

0

0.940

1

0.924

0

0.908

1

0.892

0.876

0

0.860

1

0.844

0

1

0.828

0.812

0

0.796

1

0.780

010

1

0.764

0.748

0

1

0.732

0.716

0

1

0.700

1.708

1.692

1.676

1.660

1.644

1.628

1.612

1.596

1.580

1.564

1.548

1.532

1.516

1.500

1.484

1.468

1.452

1.436

1.420

1.404

1.388

1.372

1.356

1.340

1.324

1.308

1.292

1.276

1.260

1.244

1.228

1.212

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

CPU-CORE

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

39 48Friday, June 17, 2005

X5.0

5

4

3

2

1

Bandera Platform power up sequence with AC

10.88ms

http://hobi-elektronika.net

DOCK_IN

D D

+3/5/12/1.5VALW
ON/OFF#

EC_RSMRST#

6.82ms

97.6ms

SUSCLK

SLP_S5#
SLP_S3#

SYSON

124ms

110ms

+1.2V/+1.8V/+3V/+5V
SUSP#
+0.9/1.5/1.8/2.5/3/5VS
+VCCP
VID[5..0]

C C

61us

2.216ms

2.44ms

162.4ms

32ms

VCCP_PWRGD
SYSPOK

VR_ON

Boot voltage 1.2V

+VCC_CORE

CLKEN#

19.2ms

29.6ms

756us

62.2ms

BCLK

VRMPWRGD

3.52ms

H_PWRGOOD
ICH_PWRGD(PWROK)

B B

SUS_STAT#
PLTRST#/PCIRST#

RSTIN#

H_RST#

61ms

996us

61.2us

1000us

STPCLK#
CPUSLP#

2.24ms

DPSLP#
DPRSTP#
STP_CPU#

2.08ms

STP_PCI#

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Power Sequence

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

40 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

HW P.I.R LIST---EVT2

Change item Change reason Date Revision

1. ADD C113 C114 R29 Q29 U6 Motion asked add thermal sensor to monitor Panel and inverter temperature 9/30/04 X09D->X1.0

D D

C C

2. Route SMB_EC_CK2, SMB_EC_DA2 to dock Motion asked to reading dock temperature

3. Route EN_DFAN1 and FAN_SPEED1 to dock Motion asked to add this function to control dock fan

4. Swap dock pin To layout as easily and well as enough

5. Add R319 Per EC team asked reserve ICH6M PME# funtion

6. Connect U5D.Y1 to VCCP Net connect error

7. Delete SMB_EC_CK2, SMB_EC_DA2 from dock connector Per Motion asking no need to read dock temperature. 10/12/04 X1.0->X1.1

7. Swap PRSNT1# and PRSNT2# on dock connector For layout trace to route. 10/12/04 X1.0->X1.1

8. Delete USB port 5 over current signal from dock Route USB port 4 over current signal to dock 10/12/04 X1.0->X1.1

9. Swap BATT1 PIN RTC BATT PIN error 10/12/04 X1.0->X1.1

10. Add put down resister R353

Solve the DPRSLPVR signal may not be properly initialized until ICH6-M's core well power rails(Vcc1_5, Vcc3_3)
became stable and ICH6-M receives PCI clock issue

11. Add signal EC_SLP_S4# Add the EC_SLP_S4# function 11/01/04 X1.0->X1.1

12. Change PCI_PIRQA# to PCI_PIRF#

13. Change USBEN# connect point from GPO21 to GPO23

Sync up with Pecos 11/01/04 X1.0->X1.1

Meet customer specification P18

14. Add R368,R369,Q32; Delete R340; connect WL_EN# control signal to GPO21 Meet customer specification

15. Delete C251,C264,C80,C99,C84,C98,C103,C372,C101,C371, R1158,R1159,Q54,Q55

16. Add U36; delete Q29, C114, R29, U6

Meet customer specification P10,P32

Motion asked add thermal sensor to monitor Panel and inverter temperature

Page#

P14

P32

P32

P32

P30

P11

P32

P32

P32

P17

P18

P18,P28,P29

P16, P23

P18, P22

P14

9/30/04

9/30/04

9/30/04

9/30/04

X09D->X1.0

X09D->X1.0

X09D->X1.0

X09D->X1.0

9/30/04 X09D->X1.0

11/01/04 X1.0->X1.1

11/01/04

11/01/04

11/01/04

11/01/04

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

17. Change PHDD_LED# control signal from SW/LED board to M/B and add Q29

18. Change U4 Power plane from +3VALW/+3VS to VL power plane

19. Change U36 power from +5VS to +3.3VS and will change the U36 to 3.3VCT

20. Change R216 from 4.7ohm to 4.7Kohm

B B

21. Change R242 from 22ohm to 33ohm

22. Add R240 to GPIO0

23. Add R370 to GPIO1

23. Add C371 to FRONT_R

24. Add C372 to FRONT_L

25. Change net name

26. Delete signal WRBT_ICH

27. Delete R185

28. Move signal

29. Delete R163

30. Delete R180

A A

5

4

SW/LED board do not have +3VS power plane and the signal PHDD_LED# need +3VS as power supplier

EE change request

Layout need change the power +5VS plane to +3VS plane

EE change request, change material but reserve locatioin

EE change request, for impedance matching. Change material but reserve locatioin

EE change request

EE change request for STAC9200 select

EE change request

EE change request

EE change request

EE change request

It is the signal WRBT_ICH pull up resister, it should delete together with WRBT_ICH

Move signal M_SEN# from U13.R3(GPIO27) to U13.AE19(GPI7)

Signal KBRST# pull up resister have reduplicate

Signal EC_SMI# pull up resister have reduplicate

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

P30

P6

P14

P21

P25

P25

P25

P25

P25

P14/P31

P18

P18

P18

P17

P18

2

11/08/04 X1.0->X1.1
11/08/04

11/08/04

11/09/04

11/09/04

11/09/04

11/09/04

11/09/04

11/09/04

11/10/04

11/10/04

11/10/04

11/10/04

11/10/04

11/10/04

Compal Electronics, Inc.(KunShan)

Title

HW change list

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

of

1

41 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

HW P.I.R LIST---EVT2

Change item Change reason Date Revision

D D

31. Delete R168

32. Move control signal

33. Add control signal

34. Change material P/N

35. Add FPR power control MOS

36. Move control signal

37. Add C251

38. Change R54,R55 resistance from 10K ohm to 1K ohm

39. Delete R44, R45

40.Change signal WL_EN# to WL_EN

41. Delete signal EC_RXD

C C

42. Move signal EC_TXD

43. Move signal PRST1#

44. Move signal PRST2#

45. Add control signal

46. Update Power Sequence Update power sequence

47. Add GigaLAN_RST# to Dock board EE change request

48. Add R339, R371, C385

49. Delete C228,C230,C229,C231,R213,R341,R214,
C235,U17,R209,R212,Q18,U18,C236

50. Change R28: 1K_0402_5%--->1M_0402_5%

51. Change R216: 4.7K_0402_5%--->100K_0402_5%

B B

52. Change R219: 1M_0402_5%--->10K_0402_5%~D

53. Change RP17: 4.7K_0804_8P4R_5%--->10K_1206_8P4R_5%

54. Add R180,Y3,C80,C84,L32,L33,U6,Q35,C391,C396,C416,C417C361,
C386,C387,C418,R372,R341,R168,Q16,C264,R163

55. Delete SD Clock signal: CLK_48M_SD&CLK_PCI_SD and its serial resistor: R87,R96

56. Connect USB5+- to SD controller

57. Delete SD signal SDC_PME#

58. Delete SD control signal: LPC_DRQ1#

59. Add PQ26,PQ23,PC162,PR187,PR163

60. Add SD controller W83L528D circuit

A A

Signal AC97_RST_R# pull up resister have reduplicate

Sync up with Pecos, move USBEN# signal from ICH6 to EC

Add signal DIGI_FWE to U13.V3(GPIO24) and connect to JP32.9

Change U33 P/N from SA02026000L to SA020620000

Add FPR power control MOS Q34 and FPR_PWRON control signal connect to EC

Move control signal SSBTN from U28.98 to U28.90

Add C251 to net MAX6509OUT#

Change R54,R55 resistance from 10K ohm to 1K ohm but do not change they location

EE change request

WL_EN signal valid should active high

EE change request

EE change request

Move signal PRST1# from U27.34 to U27.89

Move signal PRST2# from U27.35 to U27.90

Add control signal EC_DIS_INTMIC

Signal TXD+- EA test fail and Realtech suggest add these components P24 11/17/04 X1.0->X1.1

Change the SD controller from W83L518D to Alcor 6369 and circuit need change

Change the SD controller from W83L518D to Alcor 6369 and circuit need change P21

Change the SD controller from W83L518D to Alcor 6369 and circuit need change

Change the SD controller from W83L518D to Alcor 6369 and circuit need change

Change the SD controller from W83L518D to Alcor 6369 and circuit need change

Change the SD controller from W83L518D to Alcor 6369 and circuit need change

Change the SD controller from W83L518D to Alcor 6369 and circuit need change P21

Change the SD controller from W83L518D to Alcor 6369 and circuit need change P18/P21

Change the SD controller from W83L518D to Alcor 6369 and circuit need change

Change the SD controller from W83L518D to Alcor 6369 and circuit need change

Add DOCK_IN power control fucction P32

Add the W83L528D as the SD card controller

Page#

P17

P18/P28/P29

P14/P18

P27

P28/P29/P30

P29

P6

P8

P8

P18/P22

P28

P28

P28

P28

P28

11/10/04

11/10/04

11/10/04

11/10/04

11/10/04

11/10/04

11/11/04 X1.0->X1.1

11/11/04

11/13/04

11/13/04

11/13/04

11/13/04

11/13/04

11/13/04

11/13/04

11/13/04P42

P32/P28/P29 11/16/04

P21 11/19/04 X1.0->X1.1

11/19/04

P21

P21

P21

11/19/04

11/19/04

11/19/04

P21 11/19/04 X1.0->X1.1

11/19/04 X1.0->X1.1

11/19/04

P30

P17

11/19/04

11/19/04

11/19/04

P22

11/23/04 X1.0->X1.1

P14/P23/P31 11/23/04 X1.0->X1.162.Change LCD_Digitizer_cable;BlueTooth_Cable; FPR_Mic_Cable pin define For the cable wire can be more tidiness and some signal define change

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.1

X1.0->X1.111/23/04P2261.Delete the Touch Screen function, please refer the attached Word file For the following reason:1. PCB do not have enough space to placement and layout; 2. not use this function

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

HW change list

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

42 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

HW P.I.R LIST---DVT1

Change item Change reason Date Revision

1. Change R89 Resistance from 12ohm to 33ohm but location do not change According to the Intel Design Guide the clock USB_48MHz should serial a 33ohm resistor 04-12-13 X1.1A->X02

D D

C C

B B

A A

2. Add pull up resistor R293 to KSI_USER

3. ADD R374

4. Change R373 net connect

5. Delete:U6,Q16,Q35,R219,R28,R168,R341,R372,R29,R163,C391,C396,C416,
C417,C361,C386,C264,C387,C80,C84,C418

6. Change USB5+_ net to NC

7.Delete: R180,R207,R389,R391,R393,R395,R397,R399,R401

8.Add R298,R341,R273,R372

10.Change U11 PCB Footprint from TPS2043A_SO16 to PI5V330Q_QSOP16

11.Add Bridge Battery Power net: Bridge_PWR

12.Change JP32 pin31,pin32,pin33,pin34 from DUMMY to GND and
add these pin define to the schematic

13.Change JP15 pin21,pin22 from DUMMY to GND and add these pin define to the schematic

14.Change JP14 pin23,pin24,pin25,pin26 from DUMMY to GND and
add these pin define to the schematic

15.Add CLK_PCIE_P2/N2 signal from U40 toDock; add the clock serial resistor R168,
R163 and pull high resistor R180,R207

This signal is high level voltage valid and should pull up so that the EC do not submit miss order

For cost down concern (after test verify try to remove Q21)

EC Team suggest change the schematic for cost down (after test verify try to remove U30)

After verify the AU6369 function and delete this USB SD controller interface

Due to the USB5+_ net connect to AU6369 and should delete together with AU6369
Due to these select resistor only connect SD controller AU6369 to SD card socket and

should delete together with AU6369

1.Add R298 to pin1:STAC9758 need connect to GND but STAC9200 NC;

2.Add R341to pin4:STAC9758 need connect to GND but STAC9200 NC;

3.Add R273 to pin25:STAC9758 need connect to GND but STAC9200 NC.

4. Add R372 to pin40:STAC9758 need connect to GND but STAC9200 NC;

Because the material have change but the PCB Footprint error and need change

Layout request

Layout request

Layout request

Layout request

The new added pair PCIE need clock signal

16.Add PCIE_RXN2,PCIE_RXP2; PCIE_TXN2,PCIE_TXP2 from ICH6 to DOCK DOCK board need add one pair PCIE signal for transmit and receive

17.Change the H2,H6 PCB footprint from H_S315D110 to H_S354B315D110 Layout request

18.Change the H7,H8,H9,H10 PCB footprint from H_S315D154 to H_S315B184D154

19.Change the H11 PCB footprint from H_S276D98 to H_T138B275D98

20.Change the H16 PCB footprint from H_S276D150 to H_S276D98

21.Add H18

22.Change SRCCLKT5/SRCCLKT5# net name from SRC6/SRC6# to SRC5/SRC5#

23.Change SRCCLKT6/SRCCLKT6# net name from SRC5/SRC5# to SRC6/SRC6#

24.Add FD1,FD2,FD3,FD4,FD5,FD6,FD7,FD8

Layout request

Layout request

Layout request

Layout request

Net name not match and need change

Net name not match and need change

Per DFX and SMT engineer request

25.Change JP5 pin16,pin17 from DUMMY to GND and add these pin define to the schematic Layout request P15 04-12-16 X1.1A->X02

26.Change PJPD1 pin4,pin5 from DUMMY to GND and add these pin define to the schematic

27.Change PCIE_TXP2 from JP29.22 to JP29.16

28.Change PCIE_TXN2 from JP29.24 to JP29.18

29.Change PCIE_RXP2 from JP29.28 to JP29.22

30.Change PCIE_RXN2 from JP29.30 to JP29.24

31.Change CLK_PCIE_P2 from JP29.22 to JP29.28

32.Change CLK_PCIE_N2 from JP29.22 to JP29.30

Layout request P34

Layout request

Layout request

Layout request

Layout request

Layout request

Layout request

Page#

P13

P28

P30

P30

The page have
been deleted

P18

P21

P25

P21 04-12-139.Delete R206,R208,R390,R392,R394,R396,R398 Because only use W83L528D as SD card controller and do not need this select resistor

P15

P33 X1.1A->X0204-12-13

P14

P30

P30

P13/P32

P18/P32

P7

P7

P7

P7

P7

P13

P13

P7

P31

P31

P31

P31

P31

P31

04-12-13

04-12-13

04-12-13

04-12-13

04-12-13

04-12-13

04-12-13

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

04-12-13

04-12-15

04-12-15

04-12-15

04-12-15

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

04-12-15 X1.1A->X02

04-12-15 X1.1A->X02

04-12-15

04-12-15

04-12-15

04-12-15

04-12-15

04-12-15

04-12-15

04-12-16

04-12-16

04-12-16

04-12-16

04-12-16

04-12-16

04-12-16

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

HW change list

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

43 48Friday, June 17, 2005

X5.0

5

4

3

2

1

HW P.I.R LIST DVT1

Change item Change reason Date Revision

http://hobi-elektronika.net

Page#

33.Change JP15 P/N fom SP010002100 to SP010002800 Material P/N error according to EVT2 BOM P30 04-12-18 X1.1A->X02

34.Add WL_BTN pull high resistor R380 to +3VS

D D

35.Change R329 pull up power plane from +3VS to +3VALW

36.Change LAN_WAKE pull up resistor R183 value from

5.1Kohm to 1Kohm and do not change the location

37.Add Q35 to control the PQ23, PQ26 gate through PRSNT2# control Q35's gate

38.Change the C366 value from 0.22U to 2.2U and the location do not change

39.Add R206,C144

40.Add ICH_SMBDATA and ICH_SMBCLK to DOCK

Because the WL_BTN signal is low voltage valid and need pull high to prevent the signal misact

After verify this action can solve the LCD flash when the AC adaptor plug in issue

Meet Intel specification

Solve the DOCK_IN power work abnormal issue

To improve the INT_MIC1 tone quality

To improve the INT_MIC1 tone quality

DOCK test board new design need add this signal

P28

P14

P18

P32

P30

P30

P32

04-12-18

04-12-18

04-12-18

04-12-18

04-12-20

04-12-20

04-12-20

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

41.Add ,R215R467,R468,C84,C97,C98,JP8,Q36,D13 To solve the EAX00 thermal issue P20 04-12-22 X1.1A->X02

42.Change PM_BATLOW# signal connection from KB910L pin80 KB910L pin44

43.Change WL_BTN# signal connection from KB910L pin33 to pin102

44.Add FAN_SPEED2 signal to 910L pin33/910Q pin176

C C

45.Add EN_DFAN2 signal to 910L pin80/910Q pin102

46.Change U4 P/N from SA06509000L to SA065090000

47.Change U1 P/N from SA805360220(1.1G) to SA000008800(1.2G)

48.Change WL_BTN#,KSI_USER#,GATEA20,KBRST#
pull high power plane from +3VS to +3VALW

49.Change DOCK CRT net name from 3VDDCDA/3VDDCCL to
3VDDCDA_R/3VDDCCL_R

50.Add CLKREQ# signal from DOCK new card to U40 pin33 (SRCCLKT6/CLKREQA#)
and add this signal serial resistor R208 and pull high resistor R216

51.Change the SD connector from SP07M001500(14pin) to SP070005P00(16pin)

52.Delete Q35;add Q40,Q41,R389,C99

53.Delete the R400

54.Add U40 pin56 PCICLK2/SEL_CLKREQ pull high select resistor R217 or
pull down select resistor R209

55.Delete the HOT_PLUG control signal

B B

56.Move signal EC_DIS_INTMIC from KB910L pin35 to pin49

57.Move signal EC_DIS_INTMIC from KB910Q pin43 to pin4

58.Add signal EC_RXD to KB910L pin35 and KB910Q pin106

59.Move DREF_SSCLK/SSCLK# from U40 pin17/18 to pin22/23

60.Move CLK_MCH_3GPLL/3GPLL# from U40 pin19/20 to pin17/18

61.Move CLK_PCIE_ICH/ICH# from U40 pin33/32 to pin19/20

62.Move CLK_PCIE_P2/N2 from U40 pin24/25 to pin26/27

63.Add L32,C361,C229

64.SD card controller signal SDD3 need pull up to +3VS

65.Change R376,R378 resistance from 47Kohm to 4.7Kohm

66.Add R218,R219 to control W83L528D power plane select

A A

67.Add R220,R293 to control CARD_DET_W# pull up power plane selection

68.Add pull up resistor R394 to U41 pin61

Need KB910L pin80 to control FAN circuit

Need these KB910L pin33 to control FAN circuit

The FAN need speed feedback signal to let EC know the FAN speed

The EC need a FAN enable signal to control FAN speed

The material need change from for Dell only to normal material

New material try run

Meet the EC specification

DOCK test board new circuit design need change these signals net name to match the circuit

The DOCK new card need this signal to request clock generator submit clock signal to new card

Old SD connector do not support SDIO and need change to new connector to support SDIO

Solve the DOCK power control MOS Q35 no control function issue

It is used to select W83L528D signal WR_PT# in EVT2, should delete because the AU6369 is removed

The PCICLK2/SEL_CLKREQsignal need double check and we keep this two selection

The signal HOT_PLUG do not use and the GPIO pin can be used for other function

KB910L pin35 need reserver for other function

Match the KB910L and KB910Q pin definition

Add this signal for EC test

Layout requestion

Layout requestion

Layout requestion

Layout requestion

To improve the INT_MIC1 tone quality

According to the W83L528D new version design guide need add this pull high resistor connect to +3VS

According to the W83L528D new version design guide need change R376 and R378 resistance
Use these two resistor to control W83L528D power plane select

and will verify the SD card function in DVT1
Use these two resistor to control CARD_DET_W# pull up power plane select and will verify the
SD card function in DVT1

According to the W83L528D new version design guide need add this resistor to pull high U41 pin61

P28

P28

P28/P29

P28/P29

P6

P5/P6/P7

P28

P15/P32

P13/P32

P21

P32

P21

P13

P28/P29

P28

P29

P28/P29

P13

P13

P13

P13

P30

P21

P21

P21

P21

P21

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-22

04-12-23

04-12-23

04-12-23

04-12-23

04-12-23

04-12-23

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

X1.1A->X02

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

HW change list

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

44 48Friday, June 17, 2005

X5.0

5

4

3

2

1

HW P.I.R LIST DVT2

Change item Change reason Date Revision

1. Delete C35

2. Change net DREF_SSCLK connect from R118.2 to R113.2;

D D

C C

B B

Change net DREF_SSCLK# connect from R120.2 to R115.2;
Change net CLK_MCH_3GPLL connect from R113.2 to R118.2;
Change net CLK_MCH_3GPLL# connect from R115.2 to R120.2

3. Change GATE20 and KBRST# pull up power plane from +3VALW to +3VS

4. Change L12,L13,L14 value from 80 Ohm@100MHz to 11 Ohm@100MHz;
Change C164,C165,C166 value from 10pF to 6.8pF

5. Change R389 resistance from 100Kohm to 300Kohm and the location not change;
Add R395 to add another control selection and this resistor can keep DEPOP;
Add PR176 to load voltage for the Q42 gate open or close

6. Change SRC3/SRC3# net name to SRC4/SRC4#

7. Change board ID from version2(for DVT1) to version3(for DVT2)

8. EC part: Change signal PSCLK1 net name to WLAN_LINK_WL,
Change signal PSDAT1 net name to WLAN_ACTIVE_WL,
Change signal PSCLK2 net name to WLAN_LED;
MiniPCI conn JP27 part: pin11 net name change from WL_LED to WL_ACTIVE_WL;
pin12 connect to WL_LINK_WL;
SW/LED conn JP14: pin10 net name change from WL_LED to WLAN_LED.

9. U41pin61 signal XDPWR# add pull down resistor R396

10. Change signal EXTROMSEL# pull up (R381) or pull down (R382) select resistor
resistance from 100K to 4.7K ohm and the location do not change

11. Change R377 resistance value from 47K to 4.7Kohm According to the W83L528D B version design guide need change these resistor resistance

12. Add D14,D15,D16,D17 as USB port0 and port1 signal Switching diode

13. Delete KB910Q

14. Add +3VS power to DOCK conn(JP29 PIN10)

15. Add Q16,R260,R285,C159; change DISPOFF# pull up power plan
from +3VALW to +3VS

16. Add L19 and this location not populate

17. 1. Change C161, C162, C163 value from 22PF to 10PF

2. Change C164, C165, C166 value from 6PF to 10PF

3. Change L12, L13. L14 value from 11ohm@100MHz to 40ohm@100MHz

4. Change REFSET pull down resistor from 255ohm to 232ohm

18. 1. Change C306/C307 value from 1uF to 0.1uF

2. Change R249 value from 34.8Kohm to 20Kohm

3. Change R250 value from 1Kohm to 20Kohm

4. Add C348&C386 and do not populate in DVT2

19. Add Q35, R399 to switch DOCKEN signal to CLKREQB# used as
quick switch control and Giga LAN clock request signal

20. Add 5.1Kohm pull down resister on MB,1Kohm pull up to VDDA on Dock

21. Add JP25 on MB

22. Dispart MB/DOCK co-use signal HP_OUT_L/R

1. U22 pin39/41 as MBHP_OUT_L/R connect to MB HP OUT/MIC IN

2. U22 pin35/36 as DOCKHP_OUT_L/R connect to DOCK HP
OUT/MIC IN and add 0ohm resister R286,R287,R288,R398

3. Signal DOCK_MIC connect to U22 pin18/19 and add C387

http://hobi-elektronika.net

According to Power consideration that how many bulk caps of bulk caps needed depend on the measurement
of load-line and power team suggest to delete C35 after test verify.

According to Intel Datasheet 915g_gv_gl_p the clock signal CLK_MCH_3GPLL/3GPLL# should
sync with SRCCLK and CV140 pin17/18 is LVDS signal and not sync with SRCCLK,
so need change the relative signal connection.

According to Intel ICH6 datasheet the ICH6 signal A20GATE and RCIN should connect to +3VS
so that S3cold and S4/S5 can work normally

After test verify the VGA RGB filter component value change can improve the VGA signal quality

This design change can solve the DOCK power control circuit can not work normally issue after test verify.

Net name not match the clock generator pin name and need change

New version build need change new board ID control

Solve the Wireless LAN LED does not operate properly issue

Add MMC select solution: signal XDPWR# pull up support MMC; signal XDPWR# pull down disable MMC
According to the W83L528D B version design guide need change these resistor resistance

(signal EXTROMSEL# pull up select EEPROM;signal EXTROMSEL# pull down do not select EEPROM)

USB signal need add Switching diode to keep it in a stable voltage range when the USB device plug or evulse.

After confirm with customer delete the KB910Q and only use KB910L in DVT2

LS2584 quick switch need +3VS power supply

Solve the LCD flash when plug in AC addaptor issue

For save power consumption and cost down concern

According to Customer test this change can improve the VGA signal quality

After test verify the circuit change can improve the speaker volume

Add quick switch to solve the USB show over current message when plug DOCK test board issue,
need add thissignal to control quick switch; BIOS asked add clock request function for Giga LAN.

Sync with Pecos design change
Add thermal sensor to monitor the HDD temperature and

connect the sensor signal through FFC to MB connector

Reserve FRONT_L/FRONT_R for Dock Headphone.

Page#

P7

P13

P28

P15

P32

P13

P29

P28/P29/ P30

P21

P21

P21

P27

The page have
been deleted

P31

P14

P25

P15/P10

P26

P13/P15/
P28/P31

P31

P20

P25

05-01-04 DVT1
MEMO CHANGE

05-01-07

05-01-07

05-01-18

05-01-20

05-01-20

05-01-20

05-01-24

05-01-24

05-01-24

05-01-24

05-01-26

05-02-04

05-02-04

05-02-19

05-02-20

05-03-08

05-03-08

05-03-08

05-03-09

05-03-10

05-03-12

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

23. Add PJP14 and not populate in DVT2

24. Add F1

A A

25. Add Q44, Q48, R400, C264, PJP19

26. Add Q45, Q46, R401, C416, PJP17

5

4

Reserve for cost down

Compal safty engineer request

Control LAN power gate to reduce power consumption

Control Wirelesse LAN power gate to reduce power consumption

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

P31

P15

P23

P22

2

05-03-12

05-03-15

05-03-15

05-03-25

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

HW change list

Bandera-EAX00-LA2581

1

X5.0

of

45 48Friday, June 17, 2005

5

4

3

2

1

HW P.I.R LIST DVT2

Change item Change reason Date Revision

27. Add Q42, Q47, R402, R403, R404, C417, PJP18 Control BT power gate to reduce power consumption 05-03-15

28. Add Q49. Q50, R405, C418, PJP20

D D

29. Chang C172, C173 value from 12pF to 15pF

30. +5VS power plane add C69 (220uF); delete C395(10uF)

31. Add C406

http://hobi-elektronika.net

Control SD chip power gate to reduce power consumption

After verify this action can solve the RTC time issue

Solve trinity cold dock re-booting issue

According to the W83L528D B version design guide need use XDLED as SD LED signal

Page#

P22

P21

P17

P32

P21

05-03-16

05-03-17

05-03-17

05-03-17

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

X02->X3.0

HW P.I.R LIST PVT

Page#Change item Change reason Date Revision

1. Delete D14, D15, D16, D17; Add D25, D26 (Change material)

2. Add R407, R408

3. Add Q51, Q52, R410, R411

4. Add R409 connect PCI_AD18 to IDSEL16

C C

5. Change Q16 power from +LCDVDD (3V) to +5VS

6. Add U39, R412

7. Delete Q48, R400, C264, Q44;Add Q54, R414, R421, C424, Q55; U17, R274

8. Add R419, R415 to control VDDA power;
Add PJP21, Q53, Q56, R413, R417, C419 to control +3VS_VDDC power;
Add U25, R416 to control signal AC97_RST#

9. Change U24 power from VDDA to +5VALW

10. Add Q44, R418, C101, PR179

11. Add R395, C230

12. Add C391, C231, C234, C33, R420 and change C349 value from 0.22U to 2.2U

13. Add D27

14. Connect signal CARD_DET_W# from SD controller to EC (U27.48)

B B

15. Delete Q45, Q46, R401, C416

16. Add U28

To improve USB ESD protect

Solve the signal Digi_FWE leak power issue

Solve battery can not charge normally when system is shut down issue.
(Because the HDD thermal monitor used SMBus is same as battery SMBus --> SMB_EC_CK1/DA1,
when the system is shut down the HDD thermal monitor cause the battery SMBus error)"

BIOS team can control this signal directly
Solve Q16 can not fully turn on issue

For save SD controller power consumption concern (when do not use SD card to cut off the signal
CLK_PCI_SD to SD controller chip can save much SD controller power consumption)

To improve LAN power consumption function

For save Audio power consumption concern

Solve signal MUTE#/HP_PLUG# leak power to VDDA issue

Solve gain chager can not chager issue

To improve this signal quality

To improve this signal quality and balance it with INT_MIC1

Add ESD protect diode to prevent ESD damage EC

EC can use signal CARD_DET_W# to control SD controller
Do not need this control circuit to control W/L power because cut off the W/L power

can cause system hang up
To save power when system do not use TPM function

P27

P14

P20

P22

P14

P21

P23

P25

P26

P31

P15

P29

P14

P21/P28

P22

P28

05-04-25

05-04-25

05-04-25

05-05-25

05-04-29

05-05-06

05-05-06

05-05-06

05-05-06

05-05-09

05-05-09

05-05-09

05-05-09

05-05-09

05-05-09

05-05-09

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

X3.0->X4.0

HW P.I.R LIST MP

1. Delete: PJP20,Q50,Q49,R405,C418;Change all +3VS_SD to +3VS power plan

2. Add R323

3. Swap CARD_DET_W_EC# from EC pin48 to EC PIN96

4. Connect JP29 un-connect pin to GND

5. Delete: PJP14,PQ26,PQ23,PC162,PR187,PR163,R389,Q41,C99,PR176,
Q40,Q44,C101,R418,PR179

6. Change SRC5/5# control signal from CLKREQB# to CLKREQA#;
Add R389, R405, R218; Swap JP29 CLKREQA# and CLKREQB# signal name
for these two signal control function change.

A A

7. Add Q40

8. Delete R218, R219

9. Add R418

5

4

SD controller power save can be controlled by enable/disable SD clock and do not need
this power control circuits

Reserver the 0ohm resistor for debug
910L pin48 is HW strap pin, low active, SD card detect signal pull low this pin while boot

so that make EC go into test mode.
Connect JP29 un-connect pin to GND can improve DOCK EMI.

After verify found these circuits no need.
Main source IDT CV140 SRC1~7/1~7# can control by CLKREQA# or CLKREQB#, MP use CLKREQA#

control; 2nd source Silego SLG84443 SRC1,3,4/1#,3#,4# can control by CLKREQB# and SRC2,5/2#,5#
can control by CLKREQA#.Use CLKREQA# control SRC5/5# can meet CV140 and SLG84443 specification.

Found glitch on VRMPWRGD, so add MOS gating this glitch.
Winbond B2 and up no support standby power, all power pins are connected inner the chip, so delete

standby power. And large power trace in the same time.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

P21

P21

P28

P31

P31

P13/P15/P31

P18

P21

05-05-27

05-05-27 X4.0->X5.0

05-05-27

05-05-27

05-05-31

05-06-10

05-06-13

05-06-13

P21 05-06-13To improve the signal SDCLK quality X4.0->X5.0

Compal Electronics, Inc.(KunShan)

Title

HW change list

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

2

Date: Sheet

X4.0->X5.0

X4.0->X5.0

X4.0->X5.0

X4.0->X5.0

X4.0->X5.0

X4.0->X5.0

X4.0->X5.0

1

46 48Friday, June 17, 2005

X5.0

of

5

4

3

2

1

PWR P.I.R LIST

http://hobi-elektronika.net

Change item Change reason Date Revision

1. PC262 from SE071101K10 change to SE071101K00

D D

C C

2. PR98 from SD034715200(71.5K) change to SD034137200(13.7K)
Add PR182 SD034100300(100K)

3. PR46 from SD014113100(1.13K) change to SD013820000(820)
PR47 from SD014402000(402) change to SD014732000(732)

4. PR50 from SD014113100(1.13K) change to SD034124100(1.24K)
PR53 from SD014402000(402) change to SD014442000(442)

5. PC53 from SE026474KT6(0.47uF)change to SE135105M00(1uF/16V)
PR382 from SD028470200(47K) change to SD028220300(220K)
Del PC54 SE033105Z08

6. PR190 from SD034324200(32.4K) change to SD034348200(34.8k)
PC161 from SE074102K00(1000P/50V) change to SE025102K04(1000P/50V)

7. Del PR377 SD034169200(16.9K),PR378 SD034100300(100K),
PR379 SD028200400(2M),PR380 SD02847020(47K),PQ41 SB301150000(DTC115EA)
Add PR394 SD0134702T5(47K)

8. PC48 from SGA20151320(150U/18mOhm) change to SGA20221210(220U/25mOhm)
PC51 from SGA20151320(150U/18mOhm) change to SGA20221210(220U/25mOhm)

9. Del PR151 SD028000000

10. PC61 from SE142475K00(4.7U/25V) change to SE114106K00(10U/6.3V)
PC57 from SE142475K00(4.7U/25V) change to SE114106K00(10U/6.3V)
PC58 from SE021226Z00(22U/16V) change to SE077226M10(22U/6.3V)

11. PR99 from SD034499000(449) change to SD034300000(300)

12. PU4 from SA000009700(SC1404) change to SA019020000(MAX1902)
PR46 from SD013820000(820) change to SD014127100(1.27K)
Add PC44 SE071470J00(47P/50V)
Add PR48 SD034100400(1M)
PR47 from SD014732000(732) change to SD014127100(1.27K)
PC45 from SE135105M00(1U/16V) change to SE026474KT6(0.47U/16V)
PR51 from SD028000000(0) change to SD028620000(620)

B B

A A

Add PC47 SE071101J00(100P/50V)
Add PR55 SD034332100(3.32K)
Del PC261 SE068101K00(100P/25V)
Add PR395 SD028100200(10K)
PR59 from SD028100300(100K) change to SD028470200(47K)
Del PR58 SD028200300(200K)
Del PR67 SD028200400(2M)
PC49 from SE074102K00(1000P/50V) change to SE074681K00(680P/50V)
Del PR389 SD028000000(0)
Add PR56 SD028000000(0)
Add PC43 SE071470J00(47P/50V)
Add PR49 SD034200400(2M)
PR50 from SD034124100(1.24K) change to SD034154100(1.54K)
PR53 from SD014442000(442) change to SD034698000(698)
PC46 from SE135105M00(1U/16V) change to SE026474KT6(0.47U/16V)
Add PC52 SE071101J00(100P/50V)
Add PR57 SD028102200(10.2K)
Del PC262 SE071101K00(100P/50V)
Add PR396 SD028100200(10K)
PC48, PC51 from SGA20221210(220U/25m) change to SG020151330(150U/45m)
Add PR43 SD011220AT7(22)
Add PC33 SE028471K01(470P/100V)

SE071101K10 is A34 part.

Improve Vccp O.C.P to 8.5A.

Improve +3VALW O.C.P to 6.2A

Improve +5VALW O.C.P to 7.2A

Improve +5VALW/+3VALW turn on timing.

Improve charge current to 1.68A.

Del Power CPU O.T.P circuit that H/W has built by U4 Max6509

SGA20221210 (220U/6V 25M OHM) cheaper than
SGA20151320 (150u/6V 18m ohm)

Improve charge voltage to 12.6V.

For cost down

Improve VCCP voltage to 1.05V

04-12-28

3V/5V/12V PWM IC from SC1404 change to MAX1902,
need change these componemts

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Power change list

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

47 48Friday, June 17, 2005

X5.0

5

4

3

2

1

http://hobi-elektronika.net

PWR P.I.R LIST

Change item Change reason Date Revision

13. PC48 from SG020151330(150uF/45mOhm) change to SGA20221210(220uF/25mOhm)

D D

PR55 from SD034332100(3.32K) change to SD000006500(3.16K)

14. PC51 from SG020151330(150uF/45mOhm) change to SGA20221210(220uF/25mOhm)
PR57 from SD034105200(10.5K) change to SD034100200(10K)

15. PC32 from SE142475K00(4.7uF/1206) change to SE065106K00(10uF/1210)

16. PR168 from SD014634200(63.4K) change to SD014562207(56.2K)

17. PR132 and PR129 from SD028300000(300/0603/5%) change to
SD028560000(560/0603/5%)

18. PR17 from SD034499300(499K) change to SD034412300(412K)
PR20 from SD034499300(499K) change to SD034634300(634K)
PR25 from SD034191300(191K) change to SD034140300(140K)

PWR P.I.R LIST MP

C C

1. PT1 from SH136100020 (N1:N2 =1:1.8) change to SH000004V80 (N1:N2 =1:2)

2. PR119 pull high voltage source from +3VALW change to +3VS. To solve VRMPWRGD 430mV of back drive with system off.

To improve battery mode 3.3VALWP dynamic ripple voltage.
( Cut in MAX1902 on DVT-1)

05-03-07

To improve battery mode 5VALWP dynamic ripple voltage.
( Cut in MAX1902 on DVT-1)

To improve 12VALW boost ceramic capacitor PC32 4.7uf/25v 1206
resonance when battery light load.

05-03-07

05-03-07

Battery cell capacity from 2400mAh change to 2600mAh that
charge current need to modify from 1.68A to 1.8A.

For meet RTC battery charge current specification.
(3.3V-0.2V-2V)/ 1.2K (560 ohm * 2) <=1mA

05-03-10

05-03-07

To improve Bridge Battery turn off voltage from 6.5V to 5.5V 05-03-10

Reduce power consumption about 0.13W when battery only on S3 mode.

05-06-13

05-06-13

B B

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Power change list

Size Document Number Rev

Custom

Bandera-EAX00-LA2581

Date: Sheet

1

of

48 48Friday, June 17, 2005

X5.0