Acer LA-1761 Schematics
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COMPAL CONFIDENTIAL
1 1
COMPAL P/N :
PCB NO :
Revision :
LA-1761
2.0
DATE :
2 2
LA-1761 Schematics Document
uFCBGA/uFCPGA Northwood
2003-03-12
3 3
REV: 2.0
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Title
Size Do cum e nt Number R e v
401248
Dat e : Sheet
Com pal Electronics, Inc.
SCH E MATIC, M/B LA-1761
期四 三月
2A
of
147¬P , 27, 2003
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Compal confidential
DT Northwood
1 1
File Name : LA-1761
CPUVID
page 7
CPU Bypass &
Fan Control
page 6
uFCBGA/uFCPGA CPU
page 4,5
System Bus
533/400MHz
HD#(0..63)HA#(3 ..31)
Memory
2 2
3 3
4 4
IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)
5 5
6 6
CRT Connector
page 15
VGA
Board
Mini PCI
Conn.
IDSEL:AD18/22
(PIRQC/D#,GNT#1/4,REQ#1/4)
VT1307S
1394
page 25
DC/DC Interface
Suspend
page 37
Power Circuit
AGP Conn
page 34
PCI BUS
IDSEL:AD20
(PIRQA#,GNT#2,REQ#2)
CardBus Controller
AGP4X(1.5V)
page 15
RJ45
LAN
RTL 8100BL
IDSEL:AD17
(PIRQB#,GNT#3,REQ#3)
3.3V 33MHz
OZ-6912
page 22
Slot 0
page 23
14M_5V
EC 87591L
page 24
page 24
page 29
Broo kdale-PE
760 BGA
ICH4
421 BGA
LPC BUS
3.3V 33MHz
Card Reader
W83L 518D
HUB Link
1.5V 66MHz
page 16,17,18
page 26
page 8,9,10
SMsC
LPC47N227
BUS(DDR)
2.5V 333MHz
USB interface
3.3V 480MHz
3.3V 24.576MHz
3.3V ATA100
page 27
DC/DC
page
38,39,40,41,42,43,44,45
7 7
SPR
Conn.
B
page 33
C
8 8
A
Touch Pad
page 28
EC Ext. I/O
page 30
BIOS
page 30
Int.KBD
page 32
D
MS CARD
page 26
SD/MMC
page 26
CARD
LPT
Port.
FIR
page 28
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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FDD
G
Therma l Sensor
page 28
page 19
Clock Generator
ADM1032 ICS950211
page 5
SO-DIMM X2
BANK 0, 1, 2, 3
page 11,12,13
page 14
Bluetooth
page 31
USB 2.0
page 31
AC-LINK
AC97
HDD
Connector
page 19
Audio DJ
O2 163
page 35
Codec
ALC202
AMP& Phone
Jack
CD-ROM
Connector
page 19
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1761
Size Do cum e nt Number R e v
401248
Custom
Dat e : Sheet
H
期四 三月
I
page 20
page 21
MDC
page 31
247¬P , 27, 2003
2A
of
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1
SCHEMATICS VERSION LIST
VERSION ISSUE DATE REMARK
D D
Power Managment table
Signal
State
+3VALW
+5VALW
+12VALW
+3V
+5V
+2.5V
+3VS
+5VS
+1.5VS
+1.2VP
+CPU_CORE
SST-Build
PT-Build
PCB Rev CHIPS Rev
0.1
+1.25VS
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
ON
ON ON
ON ON ON
ON ON
ON OFF
OFF
OFF
OFF OFF OFF
ST-Build
QT-Build
Ceramic Capacitor Spec Guide:
C C
Temperature Characteristics:
Z5V
J
SL
1
Z5P
A
BJ
Symbol
CODE
0
Z5U
8
NP0 SH
H
UJ
9
C0G SJ
I
UK
3
2
Y5U X7R
C
B
CH
Y5V
CJ
4
5
Y5P
E
D
CK
X5R
6
7
F
G
Tolerance:
F
V
+20,-10%
K
A
+-0.05PF
M
+-20%
Symbol
B B
CODE
+-10%
B
+-0.1PF
N
+-30%
C
+-0.25PF
P
+100,-0%
D
+-0.5PF +-1PF
Q
+30,-10%
G
+-2%
X
+40,-20%
H
+-3%
Z
+80,-20%
J
+-5%
SMBUS Control Table
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
A A
SMB_CLK
SMB_DATA
NS 87591
NS 87591
ICH4
5
INVERTER BATT
SERIAL SENSOR
EEPROM
(1010)
THERMAL
(U43) (U91)
4
THERMAL
SENSOR
SODIMM CLK CHIP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MINI PCI
NOTE1:
@XX : Depop component
Compal Electronics, Inc.
Title
SCHEM A T I C , M / B L A -1761
Size Do cum e nt Number R e v
401248
3
2
Dat e : Sheet
期四 三月
347¬P , 27, 2003
1
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of
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1 1
+CPU_CORE
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
D9
A10
A12
A14
A16
A18
A20
AA10
AA12
AA14
VCC_3
VCC_4
VCC_5
VCC_6A8VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56B7VCC_57B9VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65C8VCC_66
DeskTop
NorthWood
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12A3VSS_13A9VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
F9
F11
F13
F15
F17
A11
A13
A15
A17
A19
A21
A24
H23
H26
A26
AA1
AA11
AA13
AA4
AA7
AA15
AA17
AA9
AA19
AA23
AA26
AB10
AB12
AB14
AB3
AB6
AB16
AB8
AB18
AB20
AB21
AB24
AC2
AC5
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AD1
AC22
AC25
AD10
AD12
AD4
AD14
AD16
AD18
AD21
AD23
AD8
F19
K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1
J1
K5
J4
J3
H3
G1
AC1
V5
AA3
AC3
H6
D2
G2
G4
AF22
AF23
F3
E3
E2
DTNorthWood
U32A
A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#
AP#0
AP#1
BINIT#
IERR#
BR0#
BPRI#
BNR#
LOCK#
BCLK0
BCLK1
HIT#
HITM#
DEFER#
VCC_0
VCC_1
VCC_2
VSS_0H1VSS_1H4VSS_2
HA#[3..31]<8>
2 2
3 3
4 4
H_REQ#[0..4]<8>
H_ADS#<8>
5 5
6 6
+CPU_CORE
H_BREQ0#<8>
H_BPRI#<8>
H_BNR#<8>
H_LOCK#<8>
CLK_CPU_BCLK<14>
CLK_CPU_BCLK#<14>
H_HIT#<8>
H_HITM#<8>
H_DEFER#<8>
HA#[3..31]
H_REQ#[0..4]
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
12
R316 200_0402_5%
CLK_CPU_BCLK
CLK_CPU_BCLK#
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
E10
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71D7VCC_72
VCC_73
D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79E8VCC_80
E12
E14
E16
E18
E20
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HD#[0..63]
HD#[0..63] <8>
7 7
+CPU_CORE
FD11
1
8 8
FIDUCIAL MARK
A
FD9
1
FIDUCIAL MARK
B
FD1
1
FIDUCIAL MARK
FD12
1
FIDUCIAL MARK
C
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
E
F
G
H
SCHEMATIC, M/B LA-1761
Size Do cum e nt Number R e v
401248
Custom
Dat e : Sheet
期四 三月
I
of
447¬P , 27, 2003
J
2A
A
B
C
U32B
D
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AE7
AE9
E
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
AF26
B23
F
B26
C11
C13
C15
C17
C19
C22
C25
D10
D12
D14
D16
G
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
H
F10
F12
F14
F16
F18
F22
F25
F5
I
J
1 1
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125F2VSS_126
VSS_127
NC5
NC6
AF24
AE21
CPU_VID4 <7,43>
CPU_VID3 <7,43>
CPU_VID2 <7,43>
CPU_VID1 <7,43>
CPU_VID0 <7,43>
1 2
3 1
H
VSS_128
J26
DP#0
K25
DP#1
K26
DP#2
DP#3
GTLREF0
GTLREF1
GTLREF2
GTLREF3
NC1
NC2
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
ITPCLKOUT0
ITPCLKOUT1
TESTHI8
TESTHI9
TESTHI10
GHI#
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
PROCHOT#
MCERR#
SLP#
VSSA
VSSSENSE
NC3
NC4
VCCVID
AF4
R117
@470_0402
2
1 2
R104 @820_0402
Q8
@3904
+H_GTLREF1
L25
AA21
AA6
F20
F6
A22
A7
TESTTHI0_1
AD24
AA2
TESTTHI2_7
AC21
AC20
AC24
AC23
AA20
AB22
TESTTHI8_10
U6
W4
Y3
H_GHI#
A6
H_DSTBN#0
E22
H_DSTBN#1
K22
H_DSTBN#2
R22
H_DSTBN#3
W22
H_DSTBP#0
F21
H_DSTBP#1
J23
H_DSTBP#2
P23
H_DSTBP#3
W23
L5
R5
H_DBI#0
E21
H_DBI#1
G25
H_DBI#2
P26
H_DBI#3
V21
AE25
H_PROCHOT#
C3
V6
H_SLP#
AB26
H_VSSA
AD22
A4
AD2
AD3
+1.2VP
C184
.1U_0402_16V4Z
R504 @820_0402
12
C711
@.47UF_0603
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1761
Size Document N umber Re v
401248
Custom
星期四 三月
Date: Sheet
R90 56_0402_5%
R26 56_0402_5%
R91 56_0402_5%
R77 56_0402_5%
H_DSTBN#[0..3]
H_DSTBP#[0..3]
H_DBI#[0..3]
R20 @0_0402_5%
1
TP12
H_PROCHOT#
R323 62_0402_5%
H_THERMTRIP#
1 2
27, 2003
I
+CPU_CORE
1 2
1 2
1 2
1 2
12
1 2
H_DSTBN#[0..3] <8>
H_DSTBP#[0..3] <8>
H_ADSTB#0 <8>
H_ADSTB#1 <8>
H_DBI# [0 ..3 ] <8>
SYSRST# <17>
H_PROCHOT# <41>
H_SLP# <16>
+CPU_CORE
H_THERMTRIP# <17>
of
547,
J
2A
SKTOCC#
DeskTop
NorthWood
VID0
VID1
VID2
VID3
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
VSS_144
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
VSS_156
VSS_157P5VSS_158R1VSS_159
VSS_160
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
VSS_181
L23
L26
K24
12
12
M22
M25
GTL Reference Vol tage
Layout note :
1. Place R_A and R_B near CPU (Within 1.5").
2. Place decoupling cap 220PF near CPU.(Within
500mils )
R300
49.9_0603_1%
Trace width>=7mil
R302
100_0603_1%
1U_0603_10V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C485
P22
N21
N24
E
P25
R23
R26
C490
220P_0603_50V8J
T21
T24
+H_GTLREF1
F
V23
V26
U22
U25
W21
MAINPWON<37,38,40>
Y5
Y22
Y25
W24
PCIRST#<9,15,16,19,22,24,25,27,34>
1 3
Q11
@2N7002
G
VID4
AE5
AE4
AE3
AE2
AE1
+5VS
2
G
@300_5%_0402
1 2
D
S
3 1
R116
Q7
@3904
2
R92
51.1_0603_1%
1 2
AB23
AD25
AB25
AD20
AE23
AF25
AC26
AD26
F1
G5
F4
AB2
J6
C6
B6
B2
B5
Y4
D1
E5
W5
H5
H2
AD6
AD5
B3
C4
A2
AC6
AB5
AC4
Y6
AA5
AB4
D4
C1
D5
F7
E6
A5
AF3
L24
P1
RS#0
RS#1
RS#2
RSP#
TRDY#
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
DPSLP#
LINT0
LINT1
INIT#
RESET#
DBSY#
DRDY#
BSEL0
BSEL1
THERMDA
THERMDC
THERMTRIP#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
TCK
TDI
TDO
TMS
TRST#
VCCA
VCCSENSE
VCCIOPLL
NC7
NC8
ITP_CLK0
ITP_CLK1
COMP0
COMP1
DTNorthWood
VSS_129F8VSS_130
G21
VSS_131
VSS_132G3VSS_133G6VSS_134J2VSS_135
G24
VSS_136
VSS_137J5VSS_138
J22
J25
K21
H_RS#0<8>
H_RS#1<8>
H_RS#2<8>
H_TRDY#<8>
TP11
1
C37
1U_0603_10V4Z
R19
51.1_0603_1%
H_A20M#
H_FERR#
H_IGNNE#
H_SMI#
H_PWRGD
H_STPCLK#
H_GHI#
H_INTR
H_NMI
H_INIT#
H_RESET#
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM0
ITP_BPM1
ITP_BPM2
ITP_BPM3
ITP_PRDY#
ITP_PREQ#
ITP_TCK
ITP_TDI
ITP_TMS
ITP_TRST#
H_VCCA
H_VCCIOPLL
CLK_CPU_ITP
CLK_CPU_ITP#
1 2
near CPU
H_A20M#<16>
+CPU_CORE
2 2
R14 300_0402_5%
R12 51.1_0603_1%
Place resistor <100mils from
CPU pin
3 3
+CPU_CORE
4 4
5 5
6 6
24 mil
+CPU_CORE
Murata LQG21F4R7N00
R96 51_0402_5%
R315
R95
R97 51_0402_5%
R94 51_0402_5%
R314 51_0402_5%
1 2
R328 1.5K_0402_5%
1 2
R311 1.5K_0402_5%
1 2
R321 680_0402_5%
1 2
R79 1.5K_0402_5%
12
12
L22
1 2
L21
1 2
12
12
51_0402_5%
12
51_0402_5%
12
12
12
H_PWRGD
H_RESET#
4.7UH_80mA
4.7UH_80mA
12
22U_1206_10V4Z
ITP_PREQ#
ITP_PRDY#
ITP_BPM0
ITP_BPM1
ITP_BPM2
ITP_BPM3
ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK
+CPU_CORE
C36
H_FERR#<16>
H_IGNNE#<16>
H_SMI#<16>
H_PWRGD<16>
H_STPCLK#<16>
H_INTR<16>
H_INIT#<16>
H_RESET#<8>
H_DBSY#<8>
H_DRDY#<8>
H_BSEL0<9,14>
near CPU
1 2
R327 62_0402_5%
12 mil
12 mil
12
C39
22U_1206_10V4Z
H_VSSA
CLK_CPU_ITP<14>
CLK_CPU_ITP#<14>
H_NMI<16>
If used ITP port must depop
+5VALW
7 7
THERMDA_591<29>
THERMDC_591<29>
EC_SMC2<29,35>
8 8
EC_SMD2<29,35>
R99 @0_0402
12
C205
2200P_0603_50V7K
12
R98 @0_0402
EC_SMC2
EC_SMD2
12
Width 10mil , Spacing 10mil
parallel and close
H_THERMDA
H_THERMDC
2
3
8
7
12
U8
VDD1
D+
ALERT
D-
THERM
SCLK
GND
SDATA
ADM1032ARM_RM8
C208
.1U_0402_16V4Z
1
6
4
5
12
R105
@10K_0402_5%
+CPU_CORE
R_A
R_B
CPU Temperature Sensor
A
B
C
D
A
B
C
D
E
F
G
H
I
J
1
7
12
12
+CPU_CORE
12
C464
+
@470U_D2_2.5V_15m
+CPU_CORE
12
C526
+
470U_D2_2.5V_15m
+CPU_CORE
12
C38
+
@470U_D2_2.5V_15m
+CPU_CORE
12
C512
.22U_0603_10V7K
+12VS
R399
3.48K_1%
1 2
21
D16
1N4148
31
Q54
2
2SA1036K
+12VS
R119
3.48K_1%
1 2
21
D11
1N4148
31
2
.22U_0603_10V7K
1 2
1 2
Q9
2SA1036K
12
+
470U_D2_2.5V_15m
12
+
12
+
12
C509
.22U_0603_10V7K
Q14
FMMT619
2
C579
2.2UF_16V_0805
Q13
FMMT619
2
C265
2.2UF_16V_0805
12
C471
C534
@470U_D2_2.5V_15m
C53
470U_D2_2.5V_15m
C482
+
470U_D2_2.5V_15m
12
C452
+
470U_D2_2.5V_15m
12
C156
+
470U_D2_2.5V_15m
PLACE ON CPU SIDE
.22U_0603_10V7K
12
12
C506
C499
.22U_0603_10V7K
D14
1SS355
3 1
2 1
C578
D15
33PF_0402
1N4148
2 1
C279 220PF_0402
D12
1SS355
3 1
2 1
D13
C562
1N4148
33PF_0402
2 1
C268 220PF_0402
.22U_0603_10V7K
12
C83
C266
1000PF_0402
+5VFAN1
C577
.1uF_0402
C250
1000PF_0402
+5VFAN2
C563
.1uF_0402
12
C505
12
C510
+
@470U_D2_2.5V_15m
12
C450
+
470U_D2_2.5V_15m
12
C157
+
470U_D2_2.5V_15m
12
C508
.22U_0603_10V7K
.22U_0603_10V7K
12
C511
+
+
12
C494
.22U_0603_10V7K
12
C501
470U_D2_2.5V_15m
12
C52
470U_D2_2.5V_15m
.22U_0603_10V7K
12
C498
Fan1 Control circuit
+5VS
JP26
1
2
3
53398-0310
+3VS
12
R156
10K_0402
FAN_SPEED <29>
Fan2 Control circuit
+5VS
JP25
1
2
3
53398-0310
+3VS
12
R151
10K_0402
FAN_SPEED2 <29>
Layout note :
Place close to CPU, Use 2~3 vias per PAD.
1 1
Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.
Please place these cap in the socket cavity area
+CPU_CORE
12
2 2
3 3
4 4
5 5
C487
10U_1206_6.3V7K
+CPU_CORE
12
C518
10U_1206_6.3V7K
Please place these cap on the socket north side
+CPU_CORE
12
C74
10U_1206_6.3V7K
+CPU_CORE
12
C119
10U_1206_6.3V7K
+CPU_CORE
12
C145
10U_1206_6.3V7K
12
C484
10U_1206_6.3V7K
12
C517
10U_1206_6.3V7K
12
C73
10U_1206_6.3V7K
12
C131
10U_1206_6.3V7K
12
C132
10U_1206_6.3V7K
12
C93
10U_1206_6.3V7K
12
C516
10U_1206_6.3V7K
12
C40
10U_1206_6.3V7K
12
C144
10U_1206_6.3V7K
12
C120
10U_1206_6.3V7K
12
C527
10U_1206_6.3V7K
12
C94
10U_1206_6.3V7K
12
C473
10U_1206_6.3V7K
12
C148
10U_1206_6.3V7K
12
C107
10U_1206_6.3V7K
12
C519
10U_1206_6.3V7K
12
C82
10U_1206_6.3V7K
12
C106
10U_1206_6.3V7K
12
C149
10U_1206_6.3V7K
EN_FAN1<29>
Layout note :
Place close to CPU power and
ground pin as possible
(<1inch)
For Desktop's CPU:
ESR total=0.75m ohm
C total=6350uF
For Mo b i l e 's CPU:
ESR total=1.875m ohm
C total=2590uF
+12VS
C212 .1UF_0402
84
U10A
3
+
2
-
LM358
Please place these cap on the socket south side
+CPU_CORE
12
C67
10U_1206_6.3V7K
6 6
7 7
+CPU_CORE
12
10U_1206_6.3V7K
+CPU_CORE
12
10U_1206_6.3V7K
C150
C504
12
C84
10U_1206_6.3V7K
12
C159
10U_1206_6.3V7K
12
C507
10U_1206_6.3V7K
12
C96
10U_1206_6.3V7K
12
C477
10U_1206_6.3V7K
12
C513
10U_1206_6.3V7K
12
C109
10U_1206_6.3V7K
12
C486
10U_1206_6.3V7K
12
C520
10U_1206_6.3V7K
12
C136
10U_1206_6.3V7K
12
C495
10U_1206_6.3V7K
EN_FAN2<29>
12
12
R137
13K_1%
R112
13K_1%
R136 7.32K_1%
+12VS
84
U10B
5
+
6
-
LM358
R111 7.32K_1%
8 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
F
G
H
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1761
Size Document N umber Re v
401248
Custom
星期四 三月
Date: Sheet
27, 2003
I
of
647,
J
2A
10
H H
9
8
7
6
5
4
3
2
1
Desktop CPU
VID
01234
VCC
G G
1.750V
1.700V
1.650V
1.600V
1.550V
1.500V
1.450V
F F
+3VS
CPU_VID0<5,43>
CPU_VID1<5,43>
E E
CPU_VID2<5,43>
CPU_VID3<5,43>
CPU_VID4<5,43>
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
R352 1K_0402_5%
R357 1K_0402_5%
R359 1K_0402_5%
R362 1K_0402_5%
R366 1K_0402_5%
12
12
12
12
12
1.400V
1.350V
1.300V
1.250V
1.200V
1.150V
1.100V
1.050V
1.000V
0.975V
0.950V
0.925V
0.900V
0.875V
D D
0.850V XXXXX
0.825V
0.800V
0.775V
0.750V
0.725V
0.700V
C C
0.675V
0.650V
0.625V
0.600V
VRM output off1111
00 01
00011
1
0
0
0
0
1
1
1
1
1
1
1
1
0
11
11
1
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
11
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
XXXXX
XXXXX
X
X
X
X
XXX
XXXXX
X
XX
XXXX
X
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
1
B B
Compal Electronics, Inc.
A A
10
9
8
7
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
6
5
4
Title
SCHEM A T I C , M / B L A -1761
Size Do cum e nt Number R e v
401248
Custom
Dat e : Sheet
3
期四 三月
2
747¬P , 27, 2003
2A
of
1
5
4
3
2
1
DDR_SDQ[0..63]<11>
HD#[0..63]
HA#[3..31]
U31A
BROOKDALE-GL/PE
T30
HD#0
R33
HD#1
R34
HD#2
N34
HD#3
R31
HD#4
L33
HD#5
L36
HD#6
P35
HD#7
J36
HD#8
K34
HD#9
K36
HD#10
M30
HD#11
M35
HD#12
L34
HD#13
K35
HD#14
H36
HD#15
G34
HD#16
G36
HD#17
J33
HD#18
D35
HD#19
F36
HD#20
F34
HD#21
E36
HD#22
H34
HD#23
F35
HD#24
D36
HD#25
H35
HD#26
E33
HD#27
E34
HD#28
B35
HD#29
G31
HD#30
C36
HD#31
D33
HD#32
D30
HD#33
D29
HD#34
E31
HD#35
D32
HD#36
C34
HD#37
B34
HD#38
D31
HD#39
G29
HD#40
C32
HD#41
B31
HD#42
B32
HD#43
B30
HD#44
B29
HD#45
E27
HD#46
C28
HD#47
B27
HD#48
D26
HD#49
D28
HD#50
B26
HD#51
G27
HD#52
H26
HD#53
B25
HD#54
C24
HD#55
B23
HD#56
B24
HD#57
E23
HD#58
C22
HD#59
G25
HD#60
B22
HD#61
D24
HD#62
G23
HD#63
L31
HDSTBP0#
J34
HDSTBP1#
E29
HDSTBP2#
E25
HDSTBP3#
N31
HDSTBN0#
G33
HDSTBN1#
C30
HDSTBN2#
D25
HDSTBN3#
D22
CPURST#
K30
HCLK
J31
HCLK#
D27
HD_VREF2
H24
HD_VREF1
H30
HD_VREF0
AD30
HA_VREF
P30
HCC_VREF
HOST,HUB
BROOKDALE-GL/PE_760P
C66
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
12
12
C95
.1U_0402_10V6K
D D
C C
B B
H_DSTBP#0<5>
H_DSTBP#1<5>
H_DSTBP#2<5>
H_DSTBP#3<5>
H_DSTBN#0<5>
H_DSTBN#1<5>
H_DSTBN#2<5>
H_DSTBN#3<5>
H_RESET#<5>
CLK_MCH_BCLK<14>
CLK_MCH_BCLK#<14>
CLK /# 10us > RSTIN#
MCH_GTLREF<10>
A A
.1U_0402_10V6K
HD#[0..63] <4>
HA#[3..31] <4>
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HADSTB0#
HADSTB1#
HIT#
HITM#
ADS#
BNR#
BPRI#
BREQ0#
DBSY#
DEFER#
DRDY#
HTRDY#
HLOCK#
DINV3
DINV2
DINV1
DINV0
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HI10
HI9
HI8
HI7
HI6
HI5
HI4
HI3
HI2
HI1
HI0
HI_STBS
HI_STBF
RS2#
RS1#
RS0#
HX_RCOMP
HY_RCOMP
HX_SWING
HY_SWING
HI_VREF
HI_RCOMP
HI_SWING
W31
AA33
AB30
V34
Y36
AC33
Y35
AA36
AC34
AB34
Y34
AB36
AC36
AC31
AF35
AD36
AD35
AE34
AD34
AE36
AF36
AE33
AF34
AG34
AG36
AE31
AH35
AG33
AG31
AB35
AF30
P36
M36
T36
T34
M34
U33
U31
N36
U36
V30
T35
C26
B33
C35
N33
V36
AA31
W33
AA34
W35
AF2
AE2
AF3
AE5
AE4
AF4
AD8
AC5
AC7
AB8
AA7
AD4
AC4
P34
U34
R36
B28
V35
H28
Y30
AD3
AC2
AD2
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HI10
HI9
HI8
HI7
HI6
HI5
HI4
HI3
HI2
HI1
HI0
HX_RCOMP
HY_RCOMP
R59
1 2
68_0603_1%
12
C134
.1U_0402_10V6K
H_ADSTB#0 <5>
H_ADSTB#1 <5>
H_HIT# <4>
H_HITM# <4>
H_ADS# <4>
H_BNR# <4>
H_BPRI# <4>
H_BREQ0# <4>
H_DBSY# <5>
H_DEFER# <4>
H_DRDY# <5>
H_TRDY# <5>
H_LOCK# <4>
H_DBI#3 <5>
H_DBI#2 <5>
H_DBI#1 <5>
H_DBI#0 <5>
H_REQ#0 <4>
H_REQ#1 <4>
H_REQ#2 <4>
H_REQ#3 <4>
H_REQ#4 <4>
HI[0..10] <16>
HUB_PSTRB <16>
HUB_PSTRB# <16>
H_RS#2 <5>
H_RS#1 <5>
H_RS#0 <5>
10 mil
10 mil
H_XY_SW ING <10>
HUB_VREF <10,16>
HUB_VSWING <10,16>
12
1 2
R292 24.9_0603_1%
1 2
R308 24.9_0603_1%
+1.5VS
C60
.1U_0402_10V6K
DDR_SDQS[0..7]<11>
DDR_SDM[0..7]<11>
DDR_SMA[0..12]<11>
DDR_CLK2#<11>
DDR_CLK2<11>
DDR_CLK1#<11>
DDR_CLK1<11>
DDR_SDQ0
DDR_SDQ1
DDR_SDQ2
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQ10
DDR_SDQ11
DDR_SDQ12
DDR_SDQ13
DDR_SDQ14
DDR_SDQ15
DDR_SDQ16
DDR_SDQ17
DDR_SDQ18
DDR_SDQ19
DDR_SDQ20
DDR_SDQ21
DDR_SDQ22
DDR_SDQ23
DDR_SDQ24
DDR_SDQ25
DDR_SDQ26
DDR_SDQ27
DDR_SDQ28
DDR_SDQ29
DDR_SDQ30
DDR_SDQ31
DDR_SDQ32
DDR_SDQ33
DDR_SDQ34
DDR_SDQ35
DDR_SDQ36
DDR_SDQ37
DDR_SDQ38
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ45
DDR_SDQ46
DDR_SDQ47
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ51
DDR_SDQ52
DDR_SDQ53
DDR_SDQ54
DDR_SDQ55
DDR_SDQ56
DDR_SDQ57
DDR_SDQ58
DDR_SDQ59
DDR_SDQ60
DDR_SDQ61
DDR_SDQ62
DDR_SDQ63
Layout note :
1. HX _R COM P , HY_RCOMP T race width 10 mil.
2. Terminator Max 500 mil .
Close to H28 Close to Y30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
DDR_SDQ[0..63]
DDR_SDQS[0..7]
DDR_SDM[0..7]
DDR_SMA[0..12]
U31B
AN4
SDQ_0
AP2
SDQ_1
AT3
SDQ_2
AP5
SDQ_3
AN2
SDQ_4
AP3
SDQ_5
AR4
SDQ_6
AT4
SDQ_7
AT5
SDQ_8
AR6
SDQ_9
AT9
SDQ_10
AR10
SDQ_11
AT6
SDQ_12
AP6
SDQ_13
AT8
SDQ_14
AP8
SDQ_15
AP10
SDQ_16
AT11
SDQ_17
AT13
SDQ_18
AT14
SDQ_19
AT10
SDQ_20
AR12
SDQ_21
AR14
SDQ_22
AP14
SDQ_23
AT15
SDQ_24
AP16
SDQ_25
AT18
SDQ_26
AT19
SDQ_27
AR16
SDQ_28
AT16
SDQ_29
AP18
SDQ_30
AR20
SDQ_31
AR22
SDQ_32
AP22
SDQ_33
AP24
SDQ_34
AT26
SDQ_35
AT22
SDQ_36
AT23
SDQ_37
AT25
SDQ_38
AR26
SDQ_39
AP26
SDQ_40
AT28
SDQ_41
AR30
SDQ_42
AP30
SDQ_43
AT27
SDQ_44
AR28
SDQ_45
AT30
SDQ_46
AT31
SDQ_47
AR32
SDQ_48
AT32
SDQ_49
AR36
SDQ_50
AP35
SDQ_51
AP32
SDQ_52
AT33
SDQ_53
AP34
SDQ_54
AT35
SDQ_55
AN36
SDQ_56
AM36
SDQ_57
AK36
SDQ_58
AJ36
SDQ_59
AP36
SDQ_60
AM35
SDQ_61
AK35
SDQ_62
AK34
SDQ_63
BROOKDALE-GL/PE_760P
AK22
AP11
AL33
AN21
AN9
AL21
AN11
AM34
SCMD_CLK0
SCMD_CLK1
SCMD_CLK2
SCMD_CLK0#
SCMD_CLK1#
AN34
AP21
AP9
AP33
SCMD_CLK3
SCMD_CLK4
SCMD_CLK5
SCMD_CLK2#
SCMD_CLK3#
SCMD_CLK4#
BROOKDALE-GL/PE
DDR
DDR_CLK4 <12>
DDR_CLK4# <12>
DDR_CLK5 <12>
DDR_CLK5# <12>
DDR_SMA12
SMAB5
SMAB4
SMAB2
SMAB1
SBA1
SBA0
SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDM0
SDM1
SDM2
SDM3
SDM4
SDM5
SDM6
SDM7
SM_VREF
AN15
AL15
AK26
AK16
AN17
AP17
AP19
AL17
AL19
AK20
AP23
AN25
AL25
AK18
AN19
AN23
AP25
AP27
AN27
AR2
AT7
AT12
AT17
AR24
AT29
AT34
AL36
AP4
AR8
AP12
AR18
AT24
AP28
AR34
AL34
AL13
AK14
AN13
AP13
AL29
AP31
AK30
AN31
AK28
AN29
AP29
AK24
AL23
AJ34
AM2
DDR_SMA11
DDR_SMA10
DDR_SMA9
DDR_SMA8
DDR_SMA7
DDR_SMA6
DDR_SMA5
DDR_SMA4
DDR_SMA3
DDR_SMA2
DDR_SMA1
DDR_SMA0
DDR_SMAB5
DDR_SMAB4
DDR_SMAB2
DDR_SMAB1
DDR_SBS1
DDR_SBS0
DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDM0
DDR_SDM1
DDR_SDM2
DDR_SDM3
DDR_SDM4
DDR_SDM5
DDR_SDM6
DDR_SDM7
DDR_CKE3
DDR_CKE2
DDR_CKE1
DDR_CKE0
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
DDR_SRAS#
DDR_SCAS#
DDR_SWE#
RDCLKO
RDCLKI
SMY_RCOMP
12 mil
12 mil
12
C194
.1U_0402_10V6K
DDR_SMAB5 <12>
DDR_SMAB4 <12>
DDR_SMAB2 <12>
DDR_SMAB1 <12>
DDR_SBS1 <11>
DDR_SBS0 <11>
DDR_CKE3 <12>
DDR_CKE2 <12>
DDR_CKE1 <11>
DDR_CKE0 <11>
DDR_SCS#0 <11>
DDR_SCS#1 <11>
DDR_SCS#2 <12>
DDR_SCS#3 <12>
DDR_SRAS# <11>
DDR_SCAS# <11>
DDR_SWE# <11>
12
R80 @0_0603_5%
R326 60.4_0603_1%
SDREF
12
R322
60.4_0603_1%
RDCLKI & RDCLKO 100mils
LENGTH 5mils WIDTH
12
+2.5V
12
C537
.1U_0402_10V6K
SMAA12/BS0
SMAA11/DQS8
SMAA10/DQ31
SMAA9/SMA3
SMAA8/SMA4
SCMD_CLK5#
SMAA7/SMA6
SMAA6/SDQ29
SMAA5/SMA8
SMAA4/SMA11
SMAA3/SMA7
SMAA2/SMA9
SMAA1/SDQ19
SMAA0/SMA12
SCKE3/SCK#5
SCKE2/RSVD
SCKE1/SDQ58
SCKE0/RSVD
SCS#0/SCKE2
SCS#1/RSVD
SCS#2/SCK#2
SCS#3/SCAS#
SRAS#/SCKE0
SCAS#/RSVD
SWE#/SDQ5
SRCVEN_OUT#
SRCVEN_IN#
SMY_RCOMP
near MCH/PE < 1"
Title
Size Do cum e nt Number R e v
401248
2
Dat e : Sheet
Com pal Electronics, Inc.
SCHEMATIC, M/B LA-1761
期四 三月
2A
of
847¬P , 27, 2003
1
A
40.2_1%__0603
AGP_ADSTB0
12
AGP_ADSTB1
12
12
AGP_ADSTB0#
12
AGP_ADSTB1#
12
AGP_SBSTB#
12
+1.5VS
12
R41
1K_1%
12
R44
1K_1%
A
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_PIPE#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_C/BE#3
AGP_C/BE#2
AGP_C/BE#1
AGP_C/BE#0
R27
AGP_SBSTB
< 0.5'
12
U31C
H8
C3
C2
D3
D2
E4
E2
F3
F2
G5
G7
C4
B4
B3
V8
U7
M8
L7
F4
E5
M4
N7
N5
P2
N2
D5
P4
B5
H2
M2
N4
R4
L2
W2
B7
C6
D7
C7
B16
BROOKDALE-GL/PE_760P
12
C125
.1U_0402_10V6K
AGP_FRAME#
AGP_TRDY#
AGP_PAR
AGP_STOP#
AGP_GNT#
AGP_REQ#
AGP_IRDY#
AGP_DEVSEL#
AGP_WBF#
AGP_PIPE#
AGP_RBF#
AGP_ST0
AGP_ST1
AGP_ST2
GPIPE#
GSBA0/ADDIN0
GSBA1/ADDIN1
GSBA2/ADDIN2
GSBA3/ADDIN3
GSBA4/ADDIN4
GSBA5/ADDIN5
GSBA6/ADDIN6
GSBA7/ADDIN7
GWBF#
GRBF#
GST0
GST1
GST2
GAD_STB0/DVOBCLK
GAD_STB0#/DVOBCLK#
GAD_STB1/DVOCCLK
GAD_STB1#/DVOCCLK#
GSBSTB
GSBSTB#
G_FRAME#/MDVI DATA
G_IRDY#/MI2C CLK
G_TRDY#/MDVI CLK
G_STOP#/MDDC DATA
G_DEVSEL#/MI2C DATA
G_REQ#
G_PAR/ADD_DETECT
G_GNT#
GCBE3#/DVOCD5
GCBE2#
GCBE1#/DVOBBLANK#
GCBE0#/DVOBD7
AGP RCOMP/DVOBCRCOMP
AGP_VREF
HSYNC
VSYNC
DDCA_CLK
DDCA_DATA
REFSET
RP2 @8P4R_8.2K
RP1 @8P4R_8.2K
RP65 @8P4R_8.2K
R296 6.2K_0402
R295 6.2K_0402
AGP/DVO
BROOKDALE-GL/PE
ANALOG DISPLAY
+1.5VS
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
12
12
AGP_AD[0..31]<15>
AGP_SBA[0..7]<15>
A A
AGP_WBF#<15>
AGP_RBF#<15>
AGP_ST0<15>
AGP_ST1<15>
AGP_ST2<15>
AGP_ADSTB0<15>
AGP_ADSTB0#<15>
AGP_ADSTB1<15>
AGP_ADSTB1#<15>
AGP_SBSTB<15>
AGP_SBSTB#<15>
AGP_FRAME#<15>
AGP_IRDY#<15>
AGP_TRDY#<15>
AGP_STOP#<15>
AGP_DEVSEL#<15>
AGP_REQ#<15>
AGP_PAR<15>
AGP_GNT#<15>
AGP_C/BE#3<15>
AGP_C/BE#2<15>
AGP_C/BE#1<15>
AGP_C/BE#0<15>
B B
C C
D D
+AGP_NBREF
+1.5VS
R39 8.2K_0402
R29 8.2K_0402
R25 8.2K_0402
R37 8.2K_0402
R28 8.2K_0402
R21 8.2K_0402
+AGP_NBREF
B
GAD0/DVOBHSYNC
GAD1/DVOBVSYNC
GAD2/DVOBD1
GAD3/DVOBD0
GAD4/DVOBD3
GAD5/DVOBD2
GAD6/DVOBD5
GAD7/DVOBD4
GAD8/DVOBD6
GAD9/DVOBD9
GAD10/DVOBD8
GAD11/DVOBD11
GAD12/DVOBD10
GAD13/DVOBCCLKINT#
GAD14/DVOBFLDSTL
GAD15/MDDC CLK
GAD16/DVOCVSYNC
GAD17/DVOCHSYNC
GAD18/DVOCBLANK#
GAD19/DVOCD0
GAD20/DVOCD1
GAD21/DVOCD2
GAD22/DVOCD3
GAD23/DVOCD4
GAD24/DVOCD7
GAD25/DVOCD6
GAD26/DVOCD9
GAD27/DVOCD8
GAD28/DVOCD11
GAD29/DVOCD10
GAD30/DVOBCINTR#
GAD31/DVOCFLDSTL
GCLKIN
RSTIN#
DREFCLK
PWROK
PSBSEL
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
*
+1.5VS
RSTIN#
B
AGP_AD0
V4
AGP_AD1
V2
AGP_AD2
W4
AGP_AD3
W5
AGP_AD4
U5
AGP_AD5
U4
AGP_AD6
U2
AGP_AD7
V3
AGP_AD8
T2
AGP_AD9
T3
AGP_AD10
T4
AGP_AD11
R2
AGP_AD12
R5
AGP_AD13
R7
AGP_AD14
T8
AGP_AD15
P3
AGP_AD16
P8
AGP_AD17
K4
AGP_AD18
K2
AGP_AD19
J2
AGP_AD20
M3
AGP_AD21
L5
AGP_AD22
L4
AGP_AD23
H4
AGP_AD24
G2
AGP_AD25
K3
AGP_AD26
J4
AGP_AD27
J5
AGP_AD28
J7
AGP_AD29
H3
AGP_AD30
K8
AGP_AD31
G4
GCLKIN 10us > PWROK
AE7
RSTIN#
AJ31
D14
E7
Y3
G15
H16
E15
F16
C15
D16
1 2
R47 8.2K_0402_5%
12
R46
8.2K_0402_5%
Place close to pin AE7
CLK_MCH_66M
@10_0402_5%
@10P_0402_50V8K
R67
C155
12
12
PSBSEL FSB FREQUENCY
12
12
C528
1 2
10P_0402_50V8J
400 MHZ
533 MHZ
VCCA_FSB
12
C444
22U_1206_10V4Z
PCIRST# <5,15,16,19,22,24,25,27,34>
0
1
0.82uH
L45 BLM21A601SPT
1 2
C459
.1U_0402_10V6K
R319 0_0402_5%
CLK_MCH_66M <14>
PM_PWROK <17,32>
H_BSEL0 <5,14>
+1.5VS
12
C460
.1U_0402_10V6K
C
+1.5VS
+CPU_CORE
12
R309 1.5K_0402_5%
U31D
Y19
VCC1
AA19
VCC2
W20
VCC3
U21
VCC4
W21
VCC5
AA21
VCC6
A9
VCC7
B9
VCC8
C9
VCC9
D9
VCC10
E9
VCC11
B10
VCC12
C10
VCC13
D10
VCC14
F10
VCC15
H10
VCC16
A11
VCC17
B11
VCC18
C11
VCC19
D11
VCC20
E11
VCC21
G11
VCC22
J11
VCC23
B12
VCC24
C12
VCC25
D12
VCC26
F12
VCC27
H12
VCC28
G13
VCC29
J13
VCC30
H14
VCC31
J15
VCC32
AA17
VCC33
W17
VCC34
U17
VCC35
W18
VCC36
V19
VCC37
U19
VCC38
K10
VCC39
K12
VCC40
K14
VCC41
K16
VCC42
W19
VCC43
B18
VTTFSB0
C18
VTTFSB1
D18
VTTFSB2
H18
VTTFSB3
B19
VTTFSB4
C19
VTTFSB5
D19
VTTFSB6
E19
VTTFSB7
G19
VTTFSB8
J19
VTTFSB9
B20
VTTFSB10
C20
VTTFSB11
D20
VTTFSB12
F20
VTTFSB13
H20
VTTFSB14
F18
VTTFSB15
K18
VTTFSB16
K20
VTTFSB17
K22
VTTFSB18
K26
VTTFSB19
M28
VTTFSB20
T28
VTTFSB21
Y28
VTTFSB22
AD28
VTTFSB23
AB2
TESTIN#
Y2
MEM_SEL
A37
RSVD0
AB3
RSVD1
AA2
RSVD2
AA3
RSVD3
AA4
RSVD4
AA5
RSVD5
Y4
RSVD6
Y8
RSVD7
W7
RSVD8
AU37
NC
AU36
NC
AT37
NC
AU2
NC
AU1
NC
AT1
NC
AJ35
NC
AH34
NC
BROOKDALE-GL/PE_760P
+1.5VS
.1U_0402_10V6K
VCCAGP0A3VCCAGP1A7VCCAGP2C1VCCAGP3D4VCCAGP4D6VCCAGP5G1VCCAGP6K6VCCAGP7L1VCCAGP8L9VCCAGP9
BROOKDALE-GL/PE
VCCHI
12
C137
P6
POWER
VCCAGP10R1VCCAGP11R9VCCAGP12W9VCCAGP13
D
V6
P10
V10
AB10
VCCAGP14
VCCAGP15
VCCAGP16
12
C117
.1U_0402_10V6K
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCA_SM0
VCCA_SM1
VCCQSM0
VCCQSM1
VCCQSM2
VTTDECAP0
VTTDECAP1
VTTDECAP2
VTTDECAP3
VTTDECAP4
VCCA_FSB
VCCA_HI
VCCHI0
VCCHI1
VCCHI2
VCCHI3
VCCA_DPLL
VCCGPIO
VCCA_DAC0
VCCA_DAC1
SMX_RCOMP
NC
NC
NC
NC
NEAR AA1 NEAR AE1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
E
+2.5V
AH8
AK8
AG9
AJ9
AL9
AM22
AJ23
AL37
AU9
AK10
AJ11
AL11
AU25
AM26
AU13
AM14
AJ27
AJ1
AL1
AJ15
AP15
AU29
AH2
AJ2
AK2
AL2
AM30
AH3
AJ3
AK3
AL3
AH4
AJ4
AK4
AL4
AU17
AJ5
AL5
AU5
AM18
AJ19
AK32
AU33
AH6
AK6
AP20
AG7
AJ7
AL7
AP7
AH10
AH12
AH14
AH18
AH22
AH26
AG1
AG2
AT20
AT21
AU21
A31
AC37
R37
L37
G37
A17
AD10
AD6
AC9
AC1
AE3
A13
B6
B14
A15
AF10
A2
A36
B37
B1
VCCA_FSB
SMX_RCOMP
12 mil
100U_D_6.3VM
+1.5VS
12
R50
60.4_0603_1%
12
12
+
12
C191
+
100U_D_6.3VM
C203
.1U_0402_10V6K
VCCA_SM
.1U_0402_10V6K
C206
C529
5 trace no vias
.1U_0402_10V6K
12
C472
.1U_0402_10V6K
12
R60 60.4_0603_1%
12
12
C211
+
100U_D_6.3VM
12
L27
0.68uH
BLM21A601SPT
12
C207
4.7U_0805_10V4Z
12
R101
1_0402_5%
12
.1U_0402_10V6K
12
C483
.1U_0402_10V6K
+2.5V
C154
.1U_0402_10V6K
12
+1.5VS
C497
12
near MCH/PE < 1"
Title
Size Document N umber Re v
Date: Sheet
Compal E l e c t r onics, Inc.
SCHEM AT IC , M/ B LA- 1761
401248
星期四 三月
27, 2003
E
12
L53
1uH
FBM-L11-201209-221-LMAT
12
C531
+
100U_D_6.3VM
12
12
C514
.1U_0402_10V6K
+3VS
C41
.1U_0402_10V6K
of
947,
C461
2A
5
4
3
2
1
10 mil Trace,
12
C521
.01U_0402_25V4Z
Within 250milWithin 250mil
+CPU_CORE
+CPU_CORE
12
.1U_0402_10V6K
12
.1U_0402_10V6K
12
.1U_0402_10V6K
12
.1U_0402_10V6K
7mil Space
NEAR ICH
.1U_0402_10V6K
C179
.1U_0402_10V6K
C163
.1U_0402_10V6K
C141
.1U_0402_10V6K
C47
12
C264
.01U_0402_25V4Z
12
12
12
12
C62
.1U_0402_10V6K
C76
.1U_0402_10V6K
.1U_0402_10V6K
.1U_0402_10V6K
.1U_0402_10V6K
R336 100_0603_1%
1 2
12
C547
.1U_0402_10V6K
PLACE NOTE: CAP PLACE
AT MIDPOINT OF THE BUS.
12
C69
12
C70
.1U_0402_10V6K
12
100_0603_1%
.1U_0402_10V6K
12
C68
AL37 AU5 AU9 AU13 AU17 AU25 AU29 AU33
.1U_0402_10V6K
12
12
C160
C167
12
C170
.1U_0402_10V6K
12
C166
A5 E1 J1 N1 U1 VCC1-43
.1U_0402_10V6K
12
12
C113
C55
12
C124
.1U_0402_10V6K
12
C139
R338
12
.1U_0402_10V6K
12
.1U_0402_10V6K
12
.1U_0402_10V6K
12
.1U_0402_10V6K
12
C549
.1U_0402_10V6K
12
C85
.1U_0402_10V6K
.1U_0402_10V6K
C178
.1U_0402_10V6K
C165
.1U_0402_10V6K
C104
.1U_0402_10V6K
C146
NEAR MCH
12
C171
12
C164
12
C142
12
C44
R313 226_0603_1%
+1.5VS
U31E
AM10
VSS0
AR23
D D
C C
B B
A A
VSS1
AU23
VSS2
F24
VSS3
AM24
VSS4
A25
VSS5
C16
VSS6
N37
VSS7
U18
VSS8
V18
VSS9
Y18
VSS10
AA18
VSS11
AL31
VSS12
AR31
VSS13
AU31
VSS14
F32
VSS15
H32
VSS16
K32
VSS17
M32
VSS18
P32
VSS19
T32
VSS20
V32
VSS21
Y32
VSS22
AB32
VSS23
AD32
VSS24
AF32
VSS25
AH32
VSS26
AM4
VSS27
A5
VSS28
C5
VSS29
AG5
VSS30
AN5
VSS31
AR5
VSS32
AR19
VSS33
AM32
VSS34
A33
VSS35
C33
VSS36
AJ33
VSS37
AN33
VSS38
AR33
VSS39
F6
VSS40
H6
VSS41
M6
VSS42
T6
VSS43
Y6
VSS44
AB6
VSS45
AF6
VSS46
AM6
VSS47
U20
VSS48
V20
VSS49
Y20
VSS50
AA20
VSS51
AM20
VSS52
A21
VSS53
B21
VSS54
C21
VSS55
D21
VSS56
E21
VSS57
G21
VSS58
J21
VSS59
D34
VSS60
W34
VSS61
A35
VSS62
E35
VSS63
G35
VSS64
J35
VSS65
L35
VSS66
AN7
VSS67
AR7
VSS68
AU7
VSS69
B8
VSS70
C8
VSS71
D8
VSS72
F8
VSS73
V21
VSS74
Y21
VSS75
AJ21
VSS76
AR21
VSS77
F22
VSS78
H22
VSS79
M10
VSS80
T10
VSS81
Y10
VSS82
AH16
VSS83
AH20
VSS84
AH24
VSS85
BROOKDALE-GL/PE_760P
AR9
AR17
AJ17
Y17
AG4
AB4
AU3
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
BROOKDALE-GL/PE
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
N35
R35
U35
AL35
AA35
AE35
AC35
AN35
AR35
AG35
VSS117
VSS95
AR3
VSS118
VSS
VSS96
AU35
AN3
B36
AM3
AG3
AC3
C31
AH30
V17
J17
G17
E17
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSSA_DAC0
VSS97
VSS98
VSS99
VSS100
VSS101G9VSS102J9VSS103N9VSS104U9VSS105
VSS106
VSS107
AF8
W36
AM8
A23
C23
AA9
AE9
VSSA_DAC1
VSS108
VSS109
VSS110
J23
D23
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
C17
B17
AM16
W3
U3
R3
D17
N3
L3
J3
G3
E3
AT2
F30
AR29
AJ29
AG29
AE29
AC29
AA29
W29
R29
U29
N29
L29
J29
C29
A29
AU15
AR15
D15
B2
AR1
AN1
AE1
AA1
U1
N1
J1
E1
AM28
F28
AU27
AR27
AL27
F14
AR13
AJ13
J27
C27
A27
E13
D13
C13
B13
AM12
AK12
F26
AR25
AJ25
J25
AU11
AR11
AR37
AN37
C25
AJ37
AG37
AE37
AA37
U37
AH28
AF28
AB28
V28
P28
K28
K24
J37
E37
C37
AT36
AH36
B15
C14
1 2
.01U_0402_25V4Z
+CPU_CORE
12
C455
10U_1206_6.3V7K
12
C105
.1U_0402_10V6K
+2.5V
.1U_0402_10V6K
12
C176
.1U_0402_10V6K
12
C172
.1U_0402_10V6K
+1.5VS
12
C64
.1U_0402_10V6K
12
C92
.1U_0402_10V6K
12
C515
NEAR MCH NEAR ICH
FSB DEC O UPLING
10U_1206_6.3V7K
12
C456
.1U_0402_10V6K
.1U_0402_10V6K
12
C152
.1U_0402_10V6K
12
C177
.1U_0402_10V6K
.1U_0402_10V6K
12
C169
.1U_0402_10V6K
.1U_0402_10V6K
12
C71
.1U_0402_10V6K
.1U_0402_10V6K
12
C80
.1U_0402_10V6K
12
C273
.01U_0402_25V4Z
.1U_0402_10V6K
C63
C75
12
.1U_0402_10V6K
12
12
12
SYSTEM MEMORY DECOUPLING
.1U_0402_10V6K
12
12
C185
C181
12
C162
.1U_0402_10V6K
12
C168
GMCH DECOUPLING
.1U_0402_10V6K
C65
C98
12
C81
.1U_0402_10V6K
12
C130
12
12
HUB_VSWING <8,16>
To device is 4" less
HUB_VREF <8,16>
R32 49.9_0603_1%
1 2
R33
100_0603_1%
NEAR MCH
R53 301_0603_1%
12
R54
150_0603_1%
12
C198
C190
C140
C46
C202
.1U_0402_10V6K
12
C180
.1U_0402_10V6K
12
C123
.1U_0402_10V6K
12
C99
.1U_0402_10V6K
10 mil Trace,
7mil Space
12
12
C61
.1U_0402_10V6K
10 mil Trace,
7mil Space
12
C151
.01U_0402_25V4Z
1 2
.1U_0402_10V6K
12
C201
.1U_0402_10V6K
12
C173
.1U_0402_10V6K
12
C112
.1U_0402_10V6K
12
C78
12
C200
.1U_0402_10V6K
12
C186
.1U_0402_10V6K
12
.1U_0402_10V6K
12
.1U_0402_10V6K
MCH_GTLREF <8>
H_XY_SWING <8>
.1U_0402_10V6K
12
C199
C133
C143
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document N umber Re v
Date: Sheet
Compal E l e c t r onics, Inc.
SCHEM AT IC , M/ B LA- 1761
401248
星期四 三月
27, 2003
2A
of
10 47,
1
A
DDR_SDQ4
DDR_SDQ0
DDR_SDQ1
DDR_SDQ5
DDR_SDQ6
1 1
2 2
3 3
4 4
A
DDR_SDQ2
DDR_SDQ3
DDR_SDQ7
DDR_SDQ9 DDR_DQ9
DDR_SDQ8
DDR_SDQ13 DDR_DQ13
DDR_SDQ12
DDR_SDQ15 DDR_DQ15
DDR_SDQ14 DDR_DQ14
DDR_SDQ11
DDR_SDQ10
DDR_SDQ16
DDR_SDQ20
DDR_SDQ17 DDR_DQ17
DDR_SDQ22 DDR_DQ22
DDR_SDQ18
DDR_SDQ28 DDR_DQ28
DDR_SDQ24
DDR_SDQ25 DDR_DQ25
DDR_SDQ29
DDR_SDQ[0..63]<8>
DDR_SDQS[0..7]<8>
DDR_SMA[0..12]<8>
DDR_SDM[0..7]<8>
DDR_SDQ57
DDR_SDQ61
DDR_SDQ56 DDR_DQ56
DDR_SDQ60
DDR_SDQ58
DDR_SDQ63 DDR_DQ63
DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
B
RP77 10_0402_4P2R_5%
1 4
2 3
RP87 10_0402_4P2R_5%
1 4
2 3
RP71 10_0402_4P2R_5%
1 4
2 3
RP88 10_0402_4P2R_5%
1 4
2 3
RP72 10_0402_4P2R_5%
1 4
2 3
RP89 10_0402_4P2R_5%
1 4
2 3
RP73 10_0402_4P2R_5%
1 4
2 3
RP90 10_0402_4P2R_5%
1 4
2 3
RP74 10_0402_4P2R_5%
1 4
2 3
RP91 10_0402_4P2R_5%
1 4
2 3
RP75 10_0402_4P2R_5%
1 4
2 3
RP92 10_0402_4P2R_5%
1 4
2 3
RP76 10_0402_4P2R_5%
1 4
2 3
RP93 10_0402_4P2R_5%
1 4
2 3
DDR_SDQ[0..63]
DDR _ S DQS[0..7]
DDR_SMA[0..12]
DDR_SDM[0..7]
RP101 10_0402_4P2R_5%
1 4
2 3
RP85 10_0402_4P2R_5%
1 4
2 3
RP102 10_0402_4P2R_5%
1 4
2 3
R378 10_0402_5%
R379 10_0402_5%
R380 10_0402_5%
R381 10_0402_5%
DDR_DQ57
DDR_DQ61
DDR_DQ60
DDR_DQ58 DDR_SDQ59 DDR_DQ59
DDR_DQS0
12
DDR_DQS1
12
DDR_DQS2
12
DDR_DQS3
12
B
DDR_DQ4
DDR_DQ0
DDR_DQ1
DDR_DQ5
DDR_DQ6
DDR_DQ2
DDR_DQ3
DDR_DQ7
DDR_DQ8
DDR_DQ12
DDR_DQ11
DDR_DQ10
DDR_DQ16
DDR_DQ20
DDR_DQ21DDR_SDQ21
DDR_DQ18
DDR_DQ23DDR_SDQ23
DDR_DQ19DDR_SDQ19
DDR_DQ24
DDR_DQ29
C
DDR_SDQ30 DDR_DQ30
DDR_SDQ26 DDR_DQ26
DDR_SDQ31
DDR_SDQ27
DDR_SDM0
DDR_SDM1
DDR_SDM2 DDR_DM2
DDR_SDM3
DDR_SDM4 DDR_DM4
DDR_SDM5
DDR_SDM6 DDR_DM6
DDR_SDM7
DDR_SDQ37 DDR_DQ37
DDR_SDQ32
DDR_SDQ36 DDR_DQ36
DDR_SDQ33
DDR_SDQ38
DDR_SDQ34
DDR_SDQ35
DDR_SDQ39
DDR_SDQ44
DDR_SDQ40
DDR_SDQ41
DDR_SDQ45
DDR_SDQ46
DDR_SDQ42
DDR_SDQ47
DDR_SDQ43
DDR_SDQ49
DDR_SDQ48
DDR_SDQ53
DDR_SDQ52
DDR_SDQ55
DDR_SDQ54
DDR_SDQ50 DDR_DQ50
DDR_SDQ62
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
RP78 10_0402_4P2R_5%
1 4
2 3
RP94 10_0402_4P2R_5%
1 4
2 3
R390 10_0402_5%
R397 10_0402_5%
R391 10_0402_5%
R392 10_0402_5%
R393 10_0402_5%
R394 10_0402_5%
R384 10_0402_5%
R385 10_0402_5%
RP95 10_0402_4P2R_5%
1 4
2 3
RP79 10_0402_4P2R_5%
1 4
2 3
RP80 10_0402_4P2R_5%
1 4
2 3
RP96 10_0402_4P2R_5%
1 4
2 3
RP81 10_0402_4P2R_5%
1 4
2 3
RP97 10_0402_4P2R_5%
1 4
2 3
RP82 10_0402_4P2R_5%
1 4
2 3
RP98 10_0402_4P2R_5%
1 4
2 3
RP83 10_0402_4P2R_5%
1 4
2 3
RP99 10_0402_4P2R_5%
1 4
2 3
RP100 10_0402_4P2R_5%
1 4
2 3
RP84 10_0402_4P2R_5%
1 4
2 3
RP86 10_0402_4P2R_5%
1 4
2 3
R382 10_0402_5%
R383 10_0402_5%
R395 10_0402_5%
R396 10_0402_5%
C
DDR_DQ31
DDR_DQ27
DDR_DM0
12
DDR_DM1
12
12
DDR_DM3
12
12
DDR_DM5
12
12
DDR_DM7
12
DDR_DQ32
DDR_DQ33
DDR_DQ38
DDR_DQ34
DDR_DQ35
DDR_DQ39
DDR_DQ44
DDR_DQ40
DDR_DQ41
DDR_DQ45
DDR_DQ46
DDR_DQ42
DDR_DQ47
DDR_DQ43
DDR_DQ49
DDR_DQ48
DDR_DQ53
DDR_DQ52
DDR_DQ55
DDR_DQ54
DDR_DQ51DDR_SDQ51
DDR_DQ62
DDR_DQS4
12
DDR_DQS5
12
DDR_DQS6
12
DDR_DQS7
12
D
DDR_DQ5
DDR_DQ1
DDR_DQS0
DDR_DQ2
DDR_DQ6
DDR_DQ8
DDR_DQS1
DDR_DQ14
DDR_DQ15
DDR_CLK1<8>
DDR_CLK1#<8>
DDR_DQ20 DDR_DQ17
DDR_DQ16 DDR_DQ21
DDR_DQS2
DDR_DQ18
DDR_DQ22 DDR_DQ23
DDR_DQ24
DDR_DQS3
DDR_DQ26
DDR_DQ30
DDR_CKE1<8> DDR_CKE0 <8>
DIMM_SMDATA<12,14,16>
DIMM_SMCLK<12,14,16>
Layout note
Place these resistors
close to DIMM0,
all trace length<500 mil
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
DDR_CKE1 DDR_CKE0
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMAA5
DDR_SMA3
DDR_SMAA1
DDR_SMA10
DDR_SBS0
DDR_SWE#
DDR_SCS#0 DDR_SCS#1
DDR_DQ36
DDR_DQS4
DDR_DQ34
DDR_DQ40
DDR_DQ44
DDR_DQS5
DDR_DQ42
DDR_DQ46
DDR_DQ48
DDR_DQ49
DDR_DQS6
DDR_DQ54
DDR_DQ55
DDR_DQ60
DDR_DQ56
DDR_DQS7
DDR_DQ63
DDR_DQ58
+3VS
+2.5V
E
JP29
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
DDR-SODIMM_200_Normal
DIMM0
Front side / H=5.2mm
E
VREF
VDD
DM0
DQ12
VDD
DQ13
DM1
DQ14
DQ15
VDD
VDD
DQ20
DQ21
VDD
DM2
DQ22
DQ23
DQ28
VDD
DQ29
DM3
DQ30
DQ31
VDD
DM8
VDD
DU/RESET#
VDD
VDD
CKE0
DU/BA2
VDD
RAS#
CAS#
DQ36
DQ37
VDD
DM4
DQ38
DQ39
DQ44
VDD
DQ45
DM5
DQ46
DQ47
VDD
CK1#
DQ52
DQ53
VDD
DM6
DQ54
DQ55
DQ60
VDD
DQ61
DM7
DQ62
DQ63
VDD
VSS
DQ4
DQ5
DQ6
VSS
DQ7
VSS
VSS
VSS
VSS
VSS
CB4
CB5
VSS
CB6
CB7
VSS
VSS
VSS
BA1
VSS
VSS
VSS
CK1
VSS
VSS
VSS
SA0
SA1
SA2
F
SDREF+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
F
12 mil
DDR_DQ0
DDR_DQ4
DDR_DM0
DDR_DQ7
DDR_DQ3
DDR_DQ12
DDR_DQ13DDR_DQ9
DDR_DM1
DDR_DQ10
DDR_DQ11
DDR_DM2
DDR_DQ19
DDR_DQ29
DDR_DQ25DDR_DQ28
DDR_DM3
DDR_DQ27
DDR_DQ31
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMAA4
DDR_SMAA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_DQ32DDR_DQ33
DDR_DQ37
DDR_DM4
DDR_DQ39
DDR_DQ35DDR_DQ38
DDR_DQ45
DDR_DQ41
DDR_DM5
DDR_DQ43
DDR_DQ47
DDR_DQ52
DDR_DQ53
DDR_DM6
DDR_DQ51
DDR_DQ50
DDR_DQ61
DDR_DQ57
DDR_DM7
DDR_DQ62
DDR_DQ59
DDR_SBS0<8>
DDR_SWE#<8>
DDR_SRAS#<8>
DDR_SCAS#<8>
DDR_SBS1<8>
12
C295
.1U_0402_16V4Z
G
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]
DDR_SMAA[0..12]
RP21 0_0402_4P2R_5%
1 4
2 3
RP10 0_0402_4P2R_5%
1 4
2 3
RP12 0_0402_4P2R_5%
1 4
2 3
RP22 0_0402_4P2R_5%
1 4
2 3
RP23 0_0402_4P2R_5%
1 4
2 3
RP20 0_0402_4P2R_5%
1 4
2 3
R201 0_0402_5%
H
DDR_DQ[0..63] <12>
DDR_DQS[0..7] <12>
DDR_DM[0..7] <12>
DDR_SMAA[0..12] <12>
DDR_SMAA3DDR_SMA3
DDR_SMAA10DDR_SMA10
DDR_SMAA4DDR_SMA4
DDR_SMAA2DDR_SMA2
DDR_SMAA5DDR_SMA5
DDR_SMAA1DDR_SMA1
DDR_SMAA9DDR_SMA9
DDR_SMAA7DDR_SMA7
DDR_SMAA11DDR_SMA11
DDR_SMAA8DDR_SMA8
DDR_SMAA6DDR_SMA6
DDR_SMAA0DDR_SMA0
DDR_SMAA12DDR_SMA12
12
Note:
Place Close to DIMM0
Layout note
Place these resistor
close by DIMM0,
all trace length
Max=1.4"
DDR_SCS#1 <8>DDR_SCS#0<8>
DDR_CLK2# <8>
DDR_CLK2 <8>
DDR_CKE0
DDR_CKE1
DDR_SCS#1
DDR_SCS#0
RP39 56_0402_4P2R_5%
1 4
2 3
RP36 56_0402_4P2R_5%
1 4
2 3
+1.25VS
Place Close to DIMM0Note:
RP19 0_0402_4P2R_5%
DDR_SBS0
DDR_SWE#
DDR_SRAS#
DDR_SCAS#
DDR_SBS1
R196 0_0402_5%
Title
Size Document N umber Re v
401248
Date: Sheet
星期四 三月
G
DDR_D0_SBS0
1 4
DDR_D0_SWE#
2 3
RP18 0_0402_4P2R_5%
DDR_D0_SRAS#
1 4
DDR_D0_SCAS#
2 3
DDR_D0_SBS1
12
Compal E l e c t r onics, Inc.
SCHEM AT IC , M/ B LA- 1761
27, 2003
DDR_D0_SBS0 <12>
DDR_D0_SWE# <12>
DDR_D0_SRAS# <12>
DDR_D0_SCAS# <12>
DDR_D0_SBS1 <12>
of
11 47,
H
2A
A
+1.25VS +1.25VS
RP60 56_0402_4P2R_5%
DDR_DQ0
1 4
DDR_DQ4
2 3
RP57 56_0402_4P2R_5%
DDR_DQ2
1 1
2 2
3 3
1 4
DDR_DQ6
2 3
RP59 56_0402_4P2R_5%
DDR_DQ5
1 4
DDR_DQ1
2 3
RP56 56_0402_4P2R_5%
DDR_DQ7
1 4
DDR_DQ3
2 3
RP55 56_0402_4P2R_5%
DDR_DQ8
1 4
DDR_DQ9
2 3
RP52 56_0402_4P2R_5%
DDR_DQ10
1 4
DDR_DQ11
2 3
RP54 56_0402_4P2R_5%
DDR_DQ12
1 4
DDR_DQ13
2 3
RP51 56_0402_4P2R_5%
DDR_DQ14
1 4
DDR_DQ15
2 3
RP50 56_0402_4P2R_5%
DDR_DQ20
1 4
DDR_DQ16
2 3
RP49 56_0402_4P2R_5%
DDR_DQ17
1 4
DDR_DQ21
2 3
RP47 56_0402_4P2R_5%
DDR_DQ18
1 4
DDR_DQ22
2 3
RP46 56_0402_4P2R_5%
DDR_DQ19
1 4
DDR_DQ23
2 3
RP45 56_0402_4P2R_5%
DDR_DQ24
1 4
DDR_DQ28
2 3
RP42 56_0402_4P2R_5%
DDR_DQ26
1 4
DDR_DQ30
2 3
RP44 56_0402_4P2R_5%
DDR_DQ29
1 4
DDR_DQ25
2 3
RP41 56_0402_4P2R_5%
DDR_DQ27
1 4
DDR_DQ31 DDR_DQ63
2 3
RP34 56_0402_4P2R_5%
DDR_DQ32
14
DDR_DQ37
23
RP31 56_0402_4P2R_5%
DDR_DQ34
14
DDR_DQ38
23
RP33 56_0402_4P2R_5%
DDR_DQ33
14
DDR_DQ36
23
RP30 56_0402_4P2R_5%
DDR_DQ39
14
DDR_DQ35
23
RP113 56_0402_4P2R_5%
DDR_DQ41
14
DDR_DQ45
23
RP116 56_0402_4P2R_5%
DDR_DQ46
14
DDR_DQ42
23
RP114 56_0402_4P2R_5%
DDR_DQ44
14
DDR_DQ40
23
RP117 56_0402_4P2R_5%
DDR_DQ47
14
DDR_DQ43
23
RP29 56_0402_4P2R_5%
DDR_DQ48
14
DDR_DQ49
23
RP26 56_0402_4P2R_5%
DDR_DQ50
14
DDR_DQ51
23
RP28 56_0402_4P2R_5%
DDR_DQ52
14
DDR_DQ53
23
RP25 56_0402_4P2R_5%
DDR_DQ54
14
DDR_DQ55
23
RP119 56_0402_4P2R_5%
DDR_DQ56
14
DDR_DQ60
23
RP122 56_0402_4P2R_5%
DDR_DQ59
14
DDR_DQ62
23
RP118 56_0402_4P2R_5%
DDR_DQ57
14
DDR_DQ61
23
RP121 56_0402_4P2R_5%
DDR_DQ58
14
23
Layout note
Place these resistor
closely DIMM1,
all trace
length<=800mil
4 4
B
RP58 56_0402_4P2R_5%
14
23
RP53 56_0402_4P2R_5%
14
23
RP48 56_0402_4P2R_5%
14
23
RP43 56_0402_4P2R_5%
14
23
RP32 56_0402_4P2R_5%
14
23
RP115 56_0402_4P2R_5%
14
23
RP27 56_0402_4P2R_5%
14
23
RP120 56_0402_4P2R_5%
14
23
DDR_DQS[0..7]
DDR_DQ[0..63]
DDR_SMAA[0..12]
DDR_DM[0..7]
DDR_SMAB4<8>
DDR_SMAB2<8>
DDR_SMAB5<8>
DDR_SMAB1<8>
DDR_DQS0
DDR_DM0
DDR_DQS1
DDR_DM1
DDR_DQS2
DDR_DM2
DDR_DQS3
DDR_DM3
DDR_DQS4
DDR_DM4
DDR_DM5
DDR_DQS5
DDR_DQS6
DDR_DM6
DDR_DQS7
DDR_DM7
DDR_DQS[0..7] <11>
DDR_DQ[0..63] <11>
DDR_SMAA[0..12] <11>
DDR_DM[0..7] <11>
RP11 0_0402_4P2R_5%
DDR_SMMAB4DDR_SMAB4
1 4
DDR_SMMAB2DDR_SMAB2
2 3
RP9 0_0402_4P2R_5%
DDR_SMMAB5DDR_SMAB5
1 4
DDR_SMMAB1DDR_SMAB1
2 3
C
DDR_CLK4<8>
DDR_CLK4#<8>
DDR_D0_SBS0<11>
DDR_D0_SWE#<11>
DIMM_SMDATA<11,14,16>
DIMM_SMCLK<11,14,16>
+2.5V
DDR_DQ5 DDR_DQ0
DDR_DQ1
DDR_DQS0
DDR_DQ2
DDR_DQ6 DDR_DQ3
DDR_DQ8
DDR_DQS1
DDR_DQ14
DDR_DQ15
DDR_DQ20 DDR_DQ17
DDR_DQS2
DDR_DQ18
DDR_DQ22
DDR_DQ24
DDR_DQ28 DDR_DQ25
DDR_DQS3
DDR_DQ26
DDR_DQ30
DDR_CKE3 DDR_CKE2
DDR_SMAA12
DDR_SMAA9
DDR_SMAA7
DDR_SMMAB5
DDR_SMAA3
DDR_SMMAB1
DDR_SMAA10
DDR_D0_SBS0 DDR_D0_SRAS#
DDR_D0_SWE#
DDR_SCS#2 DDR_SCS#3
DDR_DQ33
DDR_DQ36
DDR_DQS4
DDR_DQ34
DDR_DQ38
DDR_DQ40
DDR_DQS5
DDR_DQ42
DDR_DQ46
DDR_DQ48
DDR_DQ49
DDR_DQS6
DDR_DQ54
DDR_DQ55
DDR_DQ60
DDR_DQ56
DDR_DQS7
DDR_DQ63
DDR_DQ58
+3VS
JP32
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
DDR-SODIMM_200_Normal
DIMM1
Back side / H=9.2mm
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
BA1
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
D
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
12 mil
DDR_DQ4
DDR_DM0
DDR_DQ7
DDR_DQ12
DDR_DQ13DDR_DQ9
DDR_DM1
DDR_DQ10
DDR_DQ11
DDR_DQ21DDR_DQ16
DDR_DM2
DDR_DQ19
DDR_DQ23
DDR_DQ29
DDR_DM3
DDR_DQ27
DDR_DQ31
DDR_SMAA11
DDR_SMAA8
DDR_SMAA6
DDR_SMMAB4
DDR_SMMAB2
DDR_SMAA0
DDR_D0_SBS1
DDR_D0_SCAS#
DDR_DQ32
DDR_DQ37
DDR_DM4
DDR_DQ39
DDR_DQ35
DDR_DQ45
DDR_DQ41DDR_DQ44
DDR_DM5
DDR_DQ43
DDR_DQ47
DDR_DQ52
DDR_DQ53
DDR_DM6
DDR_DQ50
DDR_DQ51
DDR_DQ61
DDR_DQ57
DDR_DM7
DDR_DQ62
DDR_DQ59
+3VS
SDREF
12
C325
.1U_0402_16V4Z
DDR_CKE2 <8>DDR_CKE3<8>
DDR_D0_SBS1 <11>
DDR_D0_SRAS# <11>
DDR_D0_SCAS# <11>
DDR_SCS#3 <8>DDR_SCS#2<8>
DDR_CLK5# <8>
DDR_CLK5 <8>
E
+1.25VS
R432 56_0402_5%
R433 56_0402_5%
DDR_CKE2
DDR_CKE3
DDR_SCS#2
DDR_SCS#3
DDR_SMAA12
1 2
RP105 56_0402_4P2R_5%
DDR_SMAA8
14
DDR_SMAA11
23
RP106 56_0402_4P2R_5%
DDR_SMAA7
14
DDR_SMAA9
23
RP108 56_0402_4P2R_5%
DDR_SMAA10
14
DDR_SMAA3
23
RP110 56_0402_4P2R_5%
DDR_SMAA0
14
DDR_SMAA6
23
RP37 33_0402_4P2R_5%
DDR_SMAA5
14
DDR_SMAA1
23
RP109 33_0402_4P2R_5%
DDR_SMMAB2
14
DDR_SMMAB4
23
RP38 33_0402_4P2R_5%
DDR_SMAA4
14
DDR_SMAA2
23
RP107 33_0402_4P2R_5%
DDR_SMMAB1
14
DDR_SMMAB5
23
RP111 56_0402_4P2R_5%
DDR_D0_SWE#
14
DDR_D0_SBS0
23
RP112 56_0402_4P2R_5%
DDR_D0_SCAS#
14
DDR_D0_SRAS#
23
DDR_D0_SBS1
1 2
RP40 56_0402_4P2R_5%
1 4
2 3
RP35 56_0402_4P2R_5%
1 4
2 3
Layout note
Place these resistor
close by DIMM1,
all trace length
Max=0.8"
+1.25VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Title
Size Document N umber Re v
Date: Sheet
Compal E l e c t r onics, Inc.
SCHEM AT IC , M/ B LA- 1761
401248
星期四 三月
27, 2003
2A
of
12 47,
E
A
B
C
D
E
Layout note :
Distribute as close as possible
to DDR-SODIMM0.
+2.5V
1 1
12
C322
+
220U_D2_6.3V
12
C590
.1U_0402_10V6K
12
C589
.1U_0402_10V6K
12
C588
.1U_0402_10V6K
12
C587
.1U_0402_10V6K
12
C586
.1U_0402_10V6K
12
C585
.1U_0402_10V6K
12
C584
.1U_0402_10V6K
12
C583
.1U_0402_10V6K
Layout note :
Distribute as close as possible
to DDR-SODIMM1.
+2.5V
12
C309
+
220U_D2_6.3V
12
C334
.1U_0402_10V6K
12
C333
.1U_0402_10V6K
12
C332
.1U_0402_10V6K
12
C331
.1U_0402_10V6K
12
C330
.1U_0402_10V6K
12
C327
.1U_0402_10V6K
12
C329
.1U_0402_10V6K
12
C328
.1U_0402_10V6K
Layout note :
Place one cap close to every 2 pull up resistors termination to
2 2
+1.25VS
12
C386
.1U_0402_10V6K
+1.25VS
12
C375
.1U_0402_10V6K
+1.25VS
12
C385
.1U_0402_10V6K
12
C374
.1U_0402_10V6K
12
C384
.1U_0402_10V6K
12
C373
.1U_0402_10V6K
12
C383
.1U_0402_10V6K
12
C372
.1U_0402_10V6K
12
C382
.1U_0402_10V6K
12
C371
.1U_0402_10V6K
50 mil plane
12
C381
.1U_0402_10V6K
12
C370
.1U_0402_10V6K
12
C380
.1U_0402_10V6K
12
C369
.1U_0402_10V6K
12
C379
.1U_0402_10V6K
12
C368
.1U_0402_10V6K
12
C378
.1U_0402_10V6K
12
C609
.1U_0402_10V6K
12
C376
.1U_0402_10V6K
12
C610
.1U_0402_10V6K
+1.25VS
12
3 3
4 4
C611
.1U_0402_10V6K
+1.25VS
12
C360
.1U_0402_10V6K
+1.25VS
12
C352
.1U_0402_10V6K
+1.25VS
12
C617
.1U_0402_10V6K
12
C377
.1U_0402_10V6K
12
C359
.1U_0402_10V6K
12
C622
.1U_0402_10V6K
12
C363
.1U_0402_10V6K
A
12
C613
.1U_0402_10V6K
12
C358
.1U_0402_10V6K
12
C623
.1U_0402_10V6K
12
C364
.1U_0402_10V6K
12
C614
.1U_0402_10V6K
12
C357
.1U_0402_10V6K
12
C624
.1U_0402_10V6K
12
C367
.1U_0402_10V6K
12
C619
.1U_0402_10V6K
12
C620
.1U_0402_10V6K
12
C625
.1U_0402_10V6K
12
C362
.1U_0402_10V6K
12
C361
.1U_0402_10V6K
12
C621
.1U_0402_10V6K
12
C626
.1U_0402_10V6K
12
C618
.1U_0402_10V6K
B
12
C612
.1U_0402_10V6K
12
C356
.1U_0402_10V6K
12
C366
.1U_0402_10V6K
12
C387
.1U_0402_10V6K
12
C355
.1U_0402_10V6K
12
C615
.1U_0402_10V6K
12
C354
.1U_0402_10V6K
12
C365
.1U_0402_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
C353
.1U_0402_10V6K
12
C616
.1U_0402_10V6K
C
D
Title
Size Document N umber Re v
Date: Sheet
Compal E l e c t r onics, Inc.
SCHEM AT IC , M/ B LA- 1761
401248
星期四 三月
27, 2003
of
13 47,
E
2A
A
B
C
D
E
F
G
H
+3VS
12
C122
.1U_0402_16V4Z
1 2
1 2
+3V_48Mhz
12
12
1 1
H_BSEL0<5,9>
2 2
CLK_ICH_48M<17>
3 3
CLK_SD48<26>
CLK_ICH_14M<17>
CLK_CODEC_14M<20>
CLK_14M_SIO<27>
+3VS
R78
1.5K_0402_5%
5W10S +-0.5"
+3VS
12
12
C135
@10P_0402_50V8K
R35
4.7U_0805_10V4Z
12
R89
1K_0402_5%
CK408_PWRGD#<32>
DIMM_SMDATA<11,12,16>
DIMM_SMCLK<11,12,16>
10_0603_5%
C103
+3VS
+3VS
12
C128
@10P_0402_50V8K
12
C188 @10P_0402_50V8K
C189 @10P_0402_50V8K
1 2
R51 1K_0402_5%
1 2
R40 1K_0402_5%
1 2
R63 10K_0402_5%
1 2
R56 475_0402_1%
R52 27_0402
R45 27_0402
1 2
R87 33_0402_5%
1 2
R86 33_0402_5%
1 2
R88 33_0402_5%
XTALIN
12
Y2
14.318MHZ
XTALOUT
ICH_48M
CLK_SD48M
ICH_14M
300 ohm
1 2
L25 BLM21A601SPT
U5
2
3
54
55
40
25
34
53
28
43
29
30
33
35
42
39
38
56
ICS950211_BG
+3V_CLK
1
XTAL_IN
VDD_REF
XTAL_OUT
SEL0
SEL1
SEL2
PWR_DWN#
PCI_STOP#
CPU_STOP#
VTT_PWRGD#
MULT0
SDATA
SCLK
3V66_0
3V66_1/VCH_CLK/SEL4
IREF
48MHZ_USB/SEL3
48MHZ_DOT
REF
GND_REF4GND_PCI_09GND_PCI_115GND_3V66_020GND_3V66_131GND_48MHZ36GND_IREF41GND_CPU
Width=40 mils
10U_1206_10V4Z
50
37
32
14
VDD_PCI_08VDD_PCI_1
VDD_CPU_046VDD_CPU_1
VDD_48MHZ
VDD_3V66_019VDD_3V66_1
WDEN/PCICLK0
47
12
C100
VDDA
VSSA
CPUCLKT2
CPU_CLKC2
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
3V66_5
3V66_4
3V66_3
3V66_2
PCICLK_F2
PCICLK_F1
PCICLK_F0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
.1U_0402_16V4Z
12
C158
26
27
CPU_BCLK
45
CPU_BCLK#
44
MCH_BCLK
49
MCH_BCLK#
48
CPU_ITP
52
CPU_ITP#
51
24
AGP_66M
23
MCH_66M
22
ICH_66M
21
PCI_ICH
7
6
5
PCI_SD
18
PCI_1394
17
PCI_LAN
16
PCI_PCM
13
PCI_MINI
12
PCI_LPC
11
PCI_SIO
10
12
C115
.1U_0402_16V4Z
+3V_VDD
12
C108
.1U_0402_16V4Z
.1U_0402_16V4Z
.1U_0402_16V4Z
R74
1 2
12
C138
+3VS
1 2
R64 49.9_0402_1%
1 2
R57 49.9_0402_1%
1 2
R75 49.9_0402_1%
1 2
R71 49.9_0402_1%
1 2
R84 @49.9_0402_1%
1 2
R82 @49.9_0402_1%
@10P_0402_50V8K
12
C182
1 2
L26 BLM21A601SPT
12
C97
10U_1206_10V4Z
1 2
R65 27.4_0402_1%
1 2
R58 27.4_0402_1%
1 2
R76 27.4_0402_1%
1 2
R72 27.4_0402_1%
1 2
R85 @27.4_0402_1%
1 2
R83 @27.4_0402_1%
R38 33_0402_5%
1 2
R42 33_0402_5%
1 2
R48 33_0402_5%
1 2
R81 33_0402_5%
1 2
R55 SD@33_0402_5%
1 2
R62 33_0402_5%
1 2
R61 33_0402_5%
1 2
R66 33_0402_5%
1 2
R69 33_0402_5%
1 2
R70 33_0402_5%
1 2
R73 33_0402_5%
1 2
10K_0402_5%
.1U_0402_16V4Z
12
C153
12
C129
@10P_0402_50V8K
12
C175
.1U_0402_16V4Z
12
C126
.1U_0402_16V4Z
12
C193
12
C116
@10P_0402_50V8K
CLK_CPU_BCLK <4>
7W8S 2-12" +-10mil CPU+100 mil=MCH
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <8>
CLK_MCH_BCLK# <8>
CLK_CPU_ITP <5>
CLK_CPU_ITP# <5>
CLK_AGP <15>
CLK_MCH_66M <9>
CLK_ICH_66M <16>
CLK_PCI_ICH <16>
CLK_PCI_SD <26>
CLK_PCI_1394 <25>
CLK_PCI_LAN <24>
CLK_PCI_PCM <22>
CLK_PCI_MIN <34>
CLK_PCI_LPC <29>
CLK_PCI_SIO <27>
Clock G enerator
12
C90
.1U_0402_16V4Z
5W15S MCH-4"
5W20S 4-8.5" ICH+-100mil=MCH
5W15S 4-8.5" +-100mil
-2.5" +-500mil
watch dog disable
CPU Frequency Select Table
SEL[2:0] CK-408 Speed
B
100 MHZ
133 MHZ
C
001
4 4
A
011
*
ground plane inside the part pads
one power plane inside the part pads
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
E
F
Title
Size Do cum e nt Number R e v
401248
Dat e : Sheet
Com pal Electronics, Inc.
SCHEMATIC, M/B LA-1761
期四 三月
G
of
14 47¬P , 27, 2003
H
2A
A
1 1
2 2
3 3
4 4
+AGP_NBREF
12
C466
.1UF _ 0 402
5 5
6 6
TV_LUMA
7 7
TV_CRMA
TV_COMPS
75_0402
12
R10
8 8
A
MEDIA_LED#<26>
MAIL_LED #<29>
R9
75_0402
B
INT_MIC<21>
CRT_R<33>
CRT_G<33>
CRT_B<33>
PID0<27>
PID1<27>
PID2<27>
PID3<27>
PID4<27>
NUMLED#<29>
CAPSLED#<29>
+AGP_NBREF
+1.8VS
+1.5VS
12
C51
.1UF _ 0 402
+5VS
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT _VSYNC
3VDDCDA
3VDDCCL
PID0
PID1
PID2
PID3
PID4
12
C56
22UF_ 1 0V_1206
GNDB
+1.8VS
12
C465
.1UF _ 0 402
TV_OUT CONNECTOR
D3
@DAN217
2
FBM-11-160808-121
12
12
R11
75_0402
B
12
270PF_0402
C29
270PF_0402
12
C28
12
C30
270PF_0402
C
JP5
1
GND
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
GND
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
GND
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
GND
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
GND
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
GND99GND
FOXCONN-100P
+2.5VS
12
C442
.1UF _ 0 402
1
3
L42
1 2
FBM-11-160808-121
L44
1 2
L43
1 2
FBM-11-160808-121
C
GND
GND
GND
GND
GND
D2
@DAN217
2
330PF_0402
10
12
14
16
18
20
24
26
28
30
32
34
36
38
40
44
46
48
50
52
54
56
58
60
64
66
68
70
72
74
76
78
80
84
86
88
90
92
94
96
98
4
6
8
+3VS
1
12
12
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
C467
.1UF _ 0 402
3
C26
330PF_0402
12
C25
TV_LUMA
TV_CRMA
TV_COMPS
12
C468
.1UF _ 0 402
D4
@DAN217
12
C27
330PF_0402
D
E
AGP 100X2 Pin connector
INV_B+
JP20
1
2
3
4
5
6
7
S CONN.
AGP_ST[0..2]<9>
AGP_SBA[0..7]<9>
AGP_AD[0..31]<9>
AGP_C/BE#[0..3]<9>
B++
Width=60 mils
M_SEN#
CRT_R
CRT_G
CRT_B
E
L29 FBM-L11-201209-221
75_0402
EC_SM C 1 <29,30,38>
EC_SM D 1 <29,30,38>
SUS_STAT# < 17,27>
TV_LUMA <33>
TV_CRMA <33>
KSO16 <29>
KSI0 <28,29,32>
KSI1 <28,29,32>
KSI2 <28,29,32>
KSI3 <28,29,32>
KSI4 <28,29,32>
LID _ SW# <29>
DR V 0 # <19, 27>
ON/OFFBTN# <32>
+3VS
+1.25VS_VGA
+12VALW+1.5VS +5VS
12
C443
.1UF _ 0 402
+3VS
1
M_SEN#<29,30,33>
2
3
TV_LUMAL
TV_CRMAL
TV_COMPSL
D
F
AGP_ST[0..2]
AGP_SBA[0..7]
AGP_AD[0..31]
AGP_C/BE#[0..3]
AGP_ADSTB1#<9>
AGP_ADSTB1<9>
AGP_ADSTB0<9>
AGP_ADSTB0#<9>
CLK_AGP<14>
AGP_PAR<9>
AGP_IRDY#<9>
AGP_TRDY#<9>
AGP_GNT#<9>
AGP_REQ#<9>
AGP_BUSY#<17>
AGP_WBF#<9>
+12VALW
+2.5VS
Q23
1
2
3 6
12
12
C321
.1UF _ 0 402
R205
100K_0402
4
FDS4435
CRT CONNECTOR
R7
1 2
10PF_ 0402
12
12
C24
C32
R17
1 2
75_0402
10PF_0402
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
75_0402
R13
1 2
10PF_0402
F
AGP_ST0
AGP_ST2
AGP_SBA0
AGP_SBA2
AGP_SBA4
AGP_SBA6
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24
AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
AGP_AD6
AGP_AD4
AGP_AD2
AGP_AD0
8
7
5
FDS4435: P CHANNAL
1 2
R206 75K
1 2
FCM2012C80_0805
1 2
FCM2012C80_0805
1 2
FCM2012C80_0805
12
C35
CRT_HSYNCRFL<33>
CRT_VSYNCRFL<33>
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
Width=60 mils
+5VS
13
D
Q20
2
G
S
2N7002
D5
@DAN217
2
L18
CRTL_R
L19
CRTL_G
L20
CRTL_B
12
C9
22PF_ 0402
CRT_HSYNC
CRT _VSYNC
G
JP3
1
GND
3
3
5
5
7
7
9
9
11
13
15
17
19
GND
23
25
27
29
31
33
35
37
39
GND
43
45
47
49
51
53
55
57
59
GND
63
65
67
69
71
73
75
77
79
GND
83
85
87
89
919192
939394
959596
979798
GND99GND
FOXCONN-100P
INVPWR_B+
1
3
1 2
CHB1608B121
1 2
CHB1608B121
CRT_ HSYNCRFL
CRT_VSYNCRFL
G
GND
GND
GND
GND
GND
D7
12
C11
22PF_0402
L41
L40
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
64
64
66
66
68
68
70
70
72
72
74
74
76
76
78
78
80
80
82
84
84
86
86
88
88
90
90
92
94
96
98
100
1
@DAN217
2
CRT_ HSYNCRFL
CRT_VSYNCRFL
H
AGP_ST1
AGP_SBA1
AGP_SBA3
AGP_SBA5
AGP_SBA7
AGP_C/BE#3
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25
AGP_C/BE#2
AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17
AGP_C/BE#1
AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_C/BE#0
AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1
M_SEN#
LVDS_BLON#
1
D8
@DAN217
3
2
3
12
C12
22PF_0402
22PF_0402
+3VS
12
+5VS
C438
+2.5VS
D29
2 1
RB411D
C437
12
22PF_0402
AGP_SBSTB <9>
AGP_SBSTB# <9>
PM_C3_STAT# <17>
PCIR ST# <5 , 9,16,1 9,22,24,25,27,34>
AGP_DEVSEL# <9>
AGP_STOP# <9>
AGP_FRAME# <9>
PIRQA # <16,22,25>
AGP_RBF# <9>
BKOFF#<29>
ENABLT<29>
LVDS_BLON#
F2
FUSE_1A
.1UF _ 0 402
C8
12
220PF_0402
220PF_0402
H
I
INVPWR_B+
INVT_PWM<29>
DAC_BRIG<29>
+3VS
12
R283
10K_0402_5%
13
Q32
2
2N7002
CRT_VCCR_CRT_VCC
21
12
C436
R279
4.7K_0402
1 2
CRT_VCC
C13
C10
12
12
220PF_0402
Compal El ectroni cs, In c.
Title
SCHEMATIC , M/B LA-1761
Size Document Number Re v
401248
C
Date: Sheet
三月
I
R280
4.7K_0402
1 2
1 3
Q34
2N7002
2
Q33
2N7002
D1
RB751V
D6
RB751V
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
1 3
2
INVT_PWM
DISPOFF#
DAC_BRIG
21
21
+3VS
1 2
JP19
CRT CONN.
J
JP1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
HEADER 7
R278
4.7K_0402_5%
DISPOFF#
3VDDCDA
3VDDCCL
R29 0 4.7K_0402
12
R28 9 4.7K_0402
12
R29 1 4.7K_0402
DOCK_DDCDA <33>
DOCK_DDCCL <33>
of
15 47星期|, 27, 2003
J
+3VS
2A
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