Acer Geode LX EPIC RDK RevD Schematic

5

4

3

2

1

AMD Geode™ LX EPIC RDK Reference

D D

NOTES:

1) UNLESS OTHERWISE SPECIFIED RESISTORS HAVE 5% TOLERANCE.

2) UNLESS OTHERWISE SPECIFIED CAPACITORS HAVE 20% TOLERANCE.

C C

B B

IMPORTANT NOTICE:

1. THIS DOCUMENT MAY NOT REFLECT THE MOST RECENT CHANGES IN BOARD DEVELOPMENT
AND DEBUG. ANY DEVELOPER INTENDING TO USE THIS SCHEMATIC AS A REFERNCE SHOULD
CONTACT THEIR LOCAL FIELD APPLICATIONS ENGINEER, REGIONAL SALES OFFICE , O R
PROGRAM MANAGER FOR SCHEMATIC UPDATES, DESIGN RECOM MENDA TION S AND PCB L AYOU T
GUIDELINES. AMD ALSO RECOMMENDS A DESIGN REVIEW OF BOTH THE SCHEMATIC DIAGRAM
AND PCB LAYOUT BEFORE CONSIDERING PRODUC TIO N.

2. AMD RESERVES THE RIGHT TO CHANGE DESIGNS OR SPECIFICATIONS WITHOU T NO TICE .
CUSTOMERS ARE ADVISED TO OBTAIN THE LATEST VERSIONS OF PRODUCT SPECIFICATIONS,
WHICH SHOULD BE CONSIDERED IN EVALUATING A PRODUCT'S APPROPRIATENESS FOR A
PARTICULAR USE.

3. AMD MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, FOR MERCHANTABILITY OR FITNESS
FOR A PARTICULAR APPLICATION. IN NO EVENT SHALL AMD BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES AS A RESULT OF THE PE RFOR MAN CE,

A A

OR FAILURE TO PEFORM, OF ANY AMD PRODUCT OR DOCUMENTATION.

© 2007 ADVANCED MICRO DEVICES, INC. ALL RIGHTS RESERVED. AMD, THE AMD ARROW LOGO,
AMD GEODE, AND COMBINATIONS THEREOF ARE TRADEMARKS OF ADVANCED MICRO DEVICES,
INC. OTHER NAMES USED IN THIS PUBLICATION ARE FOR IDENTIFICATION PURPOSES ONLY
AND MAY BE TRADEMARKS OF THEIR RESPECTIVE COMPANIES.

5

4

Schematic

Page Index

------- ------------------------

1
2
3
4
5
6
7
8
9

10

11

12
13

IMPORTANT NOTES ABOUT
THIS SCHEMATIC

DESIGN NOTE: Example
text for the design note to
show the note inside the
colored box.

DESIGN NOTE: Example
text for the design note to
show the note inside the
colored box.

DESIGN NOTE: Example
text for the design note to
show the note inside the
colored box.

COVER PAGE
REVISION HISTORY
BLOCK DIAGRAM
POWER ON & RESET SEQUENCE
PCI & JTAG BLOCK DIAGRAM
LX PROCESSOR DDR MEMORY
DDR SODIMM CONNECTOR
LX PROCESSOR VGA
LX PROCESSOR PCI / SYSTEM
LX PROCESSOR POWER
CS5536 PCI / SYSTEM / PM / FWH
CS5536 IDE / USB / AC97 / LPC
CS5536 POWER & CLOCK GENERATOR

3

1) DESIGN NOTES in
grey are information
notes.

2) DESIGN NOTES in
yellow are notes of
caution.

3) DESIGN NOTES in
red are critical, and
must be understood and
followed.

Page Index

------- ------------------------

14
15
16
17
18
19
20
21
22
23
24
25

26 TFT & LVDS CONNECTORS

VGA CONNECTOR
ETHERNET - 10 / 100 MICREL KSZ8842
AUDIO CODEC REALTEK ALC655
SUPER IO ITE IT8712F & SPI BOOT FLASH
ETHERNET CONN / USB CONN & PWR / uDOC
MINI PCI
PCI TO ISA BRIDGE ITE IT8888G
IDE CONNECTOR
UART & FLOPPY CONNECTORS
PARALLEL PORT, KEYBOARD, & MOUSE
PC104 CONNECTORS
POWER SUPPLIES

*AMD CONFIDENTIAL*

Advanced Micro Devices

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REVISION HISTORY:

REV DATE NOTES

------- ------------------ ---------------------------------------------------------------------------------------

A Initial Release

07-09-2006
12-04-2006

C 01-19-2007

D Page 13 - Added design note regarding USB VCORE supply.

04-10-2007

C C

*

Page 8 - Changed LX symbol - DRG B 6 p i n f r om Y32 to AH8B

*

Page 10 - Connected C102-C108 to Ground

*

Page 13 - Connected C133-C137 and C149-C152 to Ground

*
*

B B

A A

5

4

3

2

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MONITOR

D D

LVDS

HD/CD

C C

X2

HOST
X1

PRIMARY IDE ATA-100

CRT

TFT

USB2.0

AMD Geode™
LX Processor

PCI BUS (33MHz)

AMD Geode™
CS5536

MEMORY BUS

PCI TO ISA
BRIDGE

10 / 100
ETHERNET
2 PORT

SODIMM200
DDR

FULL ISA

Companion

uDOC FLASH
STORAGE

CLIENT
X1

B B

14.318 MHz
Crystal

Clock

Synthesizer
(MK1491-09F)

PCI(33 MHz)

66 MHz

48 MHz

REFCLK

Device

SIO

SPI

AC97

AUDIO CODEC

5.1 SUPPORT

BIOS
FLASH

LEGACY

PARALLEL
SERIAL
KB/MS

VCORE(1.25V)

VMEM (2.6V)

A A

VCC5

VCC5SB

5

DC/DC

VCC3 (3.3V)

VCORESB (1.225V)

VCC3SB (3.3V)

4

BASEBOARD ONLY

3

2

*AMD CONFIDENTIAL*

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5VSB

VMEM @ 2A Max

DC/DC

AOZ1012

D D

WORKING

EN

AMD
Geode™ LX

5V

DC/DC

AOZ1012

WORK AUX

5V

EN

DC/DC

AOZ1012

C C

WORK AUX

5VSB

EN

VCC3 @ 2A Max

VCORE @ 2A Max

VCC3SB

DESIGN NOTE: This design uses
LVD to generate system reset.
Since LVD only monitors Vcore ,
the designer must guarantee that
Vio and other required voltages
are valid at or before Vcore. If this
cannot be guaranteed, then
RESET_WORK# must be used to
hold system in reset until Vio and
Vcore and any other requir ed
voltages are valid.

Processor

AMD
Geode™
CS5536

LVD_EN#

PCIRST#

WORKING
PWRBTN#

LINEAR
LM317

B B

VCC3SB

470

VCORESB

LM4041

5VSB

1.225VSB

Power On and Reset Sequence - Cold start

3.3VSB
PWRBTN# WORKING

5V

VCC3

VCORE

VMEM

LVD

SYS_RST#

SYSTEM POWER

VCC=+5.0V
VCC3=+3.30V - BASEBOARD
VCC3_EXT=+3.30V - PC104 SLOTS

AMD Geode™ LX
Processor

VCORE=+1.25V
VCCMEM=+2.60V
MVREF=+1.3V
VIO=+3.30V

AMD Geode™
CS5536

VCORE=+1.25V
VCORESB=+1.225V
VIO=+3.30V

MEMORY

VMEM=+2.60V
MVREF=+1.3V

PCIRST#

VCCMEM MVREF

A A

10K

5

10K

4

3

2

*AMD CONFIDENTIAL*

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PCI MASTER SETTING

REQ2#/GNT#2

D D

AMD

REQ1#/GNT#1

Expander

Geode™ LX

REQ_EXT0#/GNT_EXT0#

REQ_EXT1#/GNT_EXT1#

REQ_EXT2#/GNT_EXT2#

Processor

PC_REQ0#/PC_GNT0#

REQ0#/GNT#0

Expander

PC_REQ1#/PC_GNT1#

PC_REQ2#/PC_GNT2#

AMD Geode™ CS5536
PCI to ISA Bridge

Mini PCI
Ethernet Controller

PC104 Slot 3
PC104 Slot 0
PC104 Slot 1
PC104 Slot 2

Jumpers to select
2 of the 3 devices

C C

B B

PCI CLOCK SETTING

CLOCK

GENERATOR

SEL66_33#

MK1491-09

CLK_EXT

PC_CLK

CLK_CPU

CLK_IOC

Expander

Expander

CLK_EXT0

CLK_EXT1

CLK_EXT2

CLK_EXT3

PC_CLK0

PC_CLK1

PC_CLK2

PC_CLK3

AMD Geode™ LX Processor
AMD Geode™ CS5536
PCI to ISA Bridge
Mini PCI
Ethernet Controller
Not Used
PC104 Slot 0
PC104 Slot 1
PC104 Slot 2
PC104 Slot 3

JTAG DAISY CHAIN MODE WITH AMD GEODE™
CS5536 COMPANION DEVICE

TCK
TMS

TDI
TDO

TDEBUG_OUT

TDEBUG_IN

FS2 HEADER

TCK
TMS

TDI
TDO
TDEBUG_OUT
TDEBUG_IN

AMD GEODE™ LX PROCESSOR

TCK
TMS

TDI
TDO
TDEBUG_OUT
TDEBUG_IN

AMD GEODE™ CS5536

FunctionSEL66_33#

A A

1

PCI 66 MHz

PCI 33 MHz0

5

4

3

2

*AMD CONFIDENTIAL*

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DESIGN NOTE: See LX
layout guidelines for
latest recommendations
on memory routing.

D D

C C

DESIGN NOTE:
Use SDCLK
pairs that are
most convient
for clean routing.

B B

A A

SDCLK0#7
SDCLK2#7
SDCLK4#7

QM0

MD

M1

MDQM1
MDQM2
MDQM3
MDQM4
MDQM5
MDQM6
MDQM7

MCS0#
MCS1#

MCKE0

MWE#

MCAS#
MRAS#

SDCLK07
SDCLK27
SDCLK47

MDQS0
MDQS1
MDQS2
MDQS3
MDQS4
MDQS5
MDQS6
MDQS7

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13

DQM0

G2

DQM1

A6 D26

DQM2 BA0

A19

DQM4

C24

DQM5

H29

DQM6

N30

DQM7

B28

CS0#

F28

CS1#

F29

CS2#

D30

CS3#

E4

CKE0

F4

CKE1

C27

WE0#

A28

WE1#

E28

CAS0#

E29

CAS1#

C26

RAS0#

D27

RAS1#

M4

SDCLK0P

J4

SDCLK1P

M28

SDCLK2P

J28

SDCLK3P

D23

SDCLK4P

D20

SDCLK5P

L4

SDCLK0N

H4

SDCLK1N

L28

SDCLK2N

H28

SDCLK3N

D24

SDCLK4N

D21

SDCLK5N

M2

DQS0

H3

DQS1

C6

DQS2

A10

DQS3

C19

DQS4

B23

DQS5

J29

DQS6

N31

DQS7

C16

MA0

C17

MA1

C15

MA2

C13

MA3

D13

MA4

D11

MA5

D12

MA6

D8

MA7

D9

MA8

D6

MA9

D19

MA10

D5

MA11

C5

MA12

F30

MA13

U1A

AMD GEODE™

LX PROCESSOR

5

BA1DQM3

TLA0
TLA1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

MVREF

4

DESIGN NOTE: BA0,BA1
must be trace length
matched to within 50 mils.

MBA0
MBA1

C20B10

TLA0

B15

TLA1

B13

MD0

P2

MD1

N2

MD2

M3

MD3

K2

MD4

P3

MD5

N1

MD6

L3

MD7

K1

MD8

J2

MD9

J1

MD10

F3

MD11

E3

MD12

J3

MD13

G1

MD14

F2

MD15

F1

MD16

D2

MD17

B4

MD18

B6

MD19

C8

MD20

D1

MD21

A4

MD22

A7

MD23

B7

MD24

B9

MD25

C10

MD26

A12

MD27

B12

MD28

A9

MD29

C9

MD30

C11

MD31

A13

MD32

A15

MD33

B17

MD34

B19

MD35

B22

MD36

B16

MD37

A17

MD38

B20

MD39

A20

MD40

A22

MD41

A23

MD42

A25

MD43

A26

MD44

C22

MD45

C23

MD46

B25

MD47

B26

MD48

D31

MD49

F31

MD50

K30

MD51

K31

MD52

G30

MD53

G31

MD54

J31

MD55

J30

MD56

M31

MD57

M30

MD58

R30

MD59

R31

MD60

L29

MD61

M29

MD62

P30

MD63

R29

MVREF

P1

1

C2
100nF

DGND

4

RN1
33

RN2
33

RN3
33

RN4
33

RN5
33

RN6
33

RN7
33

RN8
33

RN9
33

RN10
33

RN11
33

RN12
33

RN13
33

RN15
33

RN17
33

RN19
33

MD5
MD1
MD4
MD0

MD6
MD2
MDQM0
MDQS0

MD12
MD8
MD7
MD3

MDQM1
MDQS1
MD13
MD9

MD15
MD11
MD14
MD10

MD21
MD17
MD20
MD16

MD22
MD18
MDQM2
MDQS2

MD28
MD24
MD23
MD19

MDQM3
MDQS3
MD29
MD25

MD31
MD27
MD30
MD26

TLA0
TLA1

MD37
MD33
MD36
MD32

MD38
MD34
MDQM4
MDQS4

MD44
MD40
MD39
MD35

MDQM5
MDQS5
MD45
MD41

MD47
MD43
MD46
MD42

3

1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45

RMD5 7
RMD1 7
RMD4 7
RMD0 7

RMD6 7

RMD2 7
RMDQM0 7
RMDQS0 7

RMD12 7

RMD8 7

RMD7 7

RMD3 7
RMDQM1 7

RMDQS1 7

RMD13 7

RMD9 7

RMD15 7

RMD11 7

RMD14 7

RMD10 7

RMD21 7

RMD17 7

RMD20 7

RMD16 7

RMD22 7

RMD18 7
RMDQM2 7
RMDQS2 7

RMD28 7

RMD24 7

RMD23 7

RMD19 7
RMDQM3 7

RMDQS3 7

RMD29 7

RMD25 7

RMD31 7

RMD27 7

RMD30 7

RMD26 7
RTLA0 7

RTLA1 7

RMD37 7

RMD33 7

RMD36 7

RMD32 7

RMD38 7

RMD34 7
RMDQM4 7
RMDQS4 7

RMD44 7

RMD40 7

RMD39 7

RMD35 7
RMDQM5 7

RMDQS5 7

RMD45 7

RMD41 7

RMD47 7

RMD43 7

RMD46 7

RMD42 7

3

DESIGN NOTE:
Swap series
resistors on the
DQS lines in
order minimize
the number of
vias.

DESIGN
NOTE: Swap
series
resistors on
the address
lines in order
minimize the
number of
vias.

DESIGN NOTE:
Do not swap
series resistors
on the DQS,
DQM or Data
lines with the
Address or
control lines.

DESIGN
NOTE: Swap
series
resistors on
the data lines
in order
minimize the
number of
vias.

DESIGN
NOTE: Place
data bus
series
resistors as
close to the
memory
devices as
possible.

RN21
33

RN23
33

RN24
33

RN26
33

RN27
33

RN14
22

RN16
22

RN18
22

RN20
22

RN22
22

RN25
22

MD53
MD49
MD52
MD48

MD54
MD50
MDQM6
MDQS6

MD60
MD56
MD55
MD51

MDQM7
MDQS7

MD61
MD57

MD63
MD59
MD62
MD58

MA11

MA12
MCKE0
MA6

MA7
MA8
MA9

MA2
MA3
MA4
MA5

MBA1

MA10
MA0
MA1

MCAS#
MWE#
MRAS#

MB

A0

MCS1#
MCS0#

MA13

2

1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45

1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45
1

8

2

7

3

6

45

RMD53 7
RMD49 7
RMD52 7
RMD48 7

RMD54 7

RMD50 7
RMDQM6 7
RMDQS6 7

RMD60 7

RMD56 7

RMD55 7

RMD51 7
RMDQM7 7

RMDQS7 7

RMD61 7

RMD57 7

RMD63 7

RMD59 7

RMD62 7

RMD58 7

RMA11 7
RMA12 7

RMCKE0 7
RMA6 7

RMA7 7
RMA8 7
RMA9 7

RMA2 7
RMA3 7
RMA4 7
RMA5 7

RMBA1 7
RMA10 7
RMA0 7
RMA1 7

RMCAS# 7
RMWE# 7
RMRAS# 7
RMBA0 7

RMCS1# 7
RMCS0# 7
RMA13 7

DESIGN NOTE: Place DQS and
DQM series resistors as close
to the SODIMM connector as
possible.

DESIGN NOTE: This schematic shows a
non-parallel terminated DDR solution.
There may be restrictions as to the total
number of DRAMS and the number of
banks supported on the SODIMM. See LX
layout guidelines for current restrictions.

DESIGN NOTE: Place address
and control series resistors as
close to the processor as
possible.

1

VCCMEM

1

R1
10K

1

R2
10K

DGND DGND

Vout = 1.30

MVREF

1

C1
100nF

*AMD CONFIDENTIAL*

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Title

AMD GEODE™ LX EPIC RDK Reference Schematic

Document Number Rev
Size

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Date: Sheet

Wednesday, April 11, 2007

1

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SDCLK06
SDCLK0#6
SDCLK26
SDCLK2#6

RMCKE06

D D

C C

B B

A A

RMRAS#6
RMCAS#6

RMWE#6

RMCS0#6
RMCS1#6

RMDQS06
RMDQS16
RMDQS26
RMDQS36
RMDQS46
RMDQS56
RMDQS66
RMDQS76

RMA06
RMA16
RMA26
RMA36
RMA46
RMA56
RMA66
RMA76
RMA86
RMA96
RMA106
RMA116
RMA126

RMDQM06
RMDQM16
RMDQM26
RMDQM36
RMDQM46
RMDQM56
RMDQM66
RMDQM76

RMBA06
RMBA16

SMB_SDA12

SMB_SCL12

RTLA16

RTLA06

SDCLK46
SDCLK4#6

VCCMEM

5

RMA136

1

R3 10K

DGND

4

J1A

35

CK0

37

CK0#

160

CK1

158

CK1#

96

CKE0

95

CKE1

118

RAS#

120

CAS#

119

WE#

121

S0#

122

S1#

11

DQS0

25

DQS1

47

DQS2

61

DQS3

133

DQS4

147

DQS5

169

DQS6

183

DQS7

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10/AP

100

A11

99

A12

12

DM0

26

DM1

48

DM2

62

DM3

134

DM4

148

DM5

170

DM6

184

DM7

117

BA0

116

BA1

194

SA0

196

SA1

198

SA2

193

SDA

195

SDL

85

RFU

86

RFU/RESET

71

CB0

72

CB4

73

CB1

74

CB5

77

DQS8

78

DM8

79

CB2

80

CB6

83

CB3

84

CB7

89

CK2

91

CK2

97

RFU

98

RFU

123

RFU/A13

124

RFU

199

VddID

200

RFU

SODIMM

DDR-SODIMM-200P-RVS

4

DQ00
DQ01
DQ02
DQ03
DQ04
DQ05
DQ06
DQ07
DQ08
DQ09
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

3

5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190

RMD0 6
RMD1 6
RMD2 6
RMD3 6
RMD4 6
RMD5 6
RMD6 6
RMD7 6
RMD8 6
RMD9 6
RMD10 6
RMD11 6
RMD12 6
RMD13 6
RMD14 6
RMD15 6
RMD16 6
RMD17 6
RMD18 6
RMD19 6
RMD20 6
RMD21 6
RMD22 6
RMD23 6
RMD24 6
RMD25 6
RMD26 6
RMD27 6
RMD28 6
RMD29 6
RMD30 6
RMD31 6
RMD32 6
RMD33 6
RMD34 6
RMD35 6
RMD36 6
RMD37 6
RMD38 6
RMD39 6
RMD40 6
RMD41 6
RMD42 6
RMD43 6
RMD44 6
RMD45 6
RMD46 6
RMD47 6
RMD48 6
RMD49 6
RMD50 6
RMD51 6
RMD52 6
RMD53 6
RMD54 6
RMD55 6
RMD56 6
RMD57 6
RMD58 6
RMD59 6
RMD60 6
RMD61 6
RMD62 6
RMD63 6

MVREF

VCCMEM

J1B

1

VREF

2

VREF

9

VDD

10

VDD

21

VDD

22

VDD

33

VDD

34

VDD

36

VDD

45

VDD

46

VDD

57

VDD

58

VDD

69

VDD

70

VDD

81

VDD

82

VDD

92

VDD

93

VDD

94

VDD

113

VDD

114

VDD

131

VDD

132

VDD

143

VDD

144

VDD

155

VDD

156

VDD

157

VDD

167

VDD

168

VDD

179

VDD

180

VDD

191

VDD

192

VDD

197

VDDSPD

SODIMM

DDR-SODIMM-200P-RVS

2

VCCMEM

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

C3
22uF

1

C10
22uF

1

C17
1nF

1

C24
1nF

1

1

1

1

1

1

1

C5

C4

100pF

22uF

1

1

C11

C12

22uF

100pF

1

1

C18

C19

1nF

1nF

1

1

C26

C25

1nF

1nF

3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186

DGND

DESIGN NOTE: This schematic
shows a non-parallel terminated
DDR solution. There may be
restrictions as to the total number
of DRAMS and the number of banks
supported on the SODIMM. See LX
layout guidelines for current
restrictions.

C6
100pF

1

C13
100pF

1

C20
10nF

1

C27
10nF

C7
100pF

1

C14
100pF

1

C21
10nF

1

C28
10nF

C8
100pF

1

C15
100pF

1

C22
10nF

1

C29
10nF

C9
1nF

1

C16
1nF

1

C23
10nF

1

C30
10nF

DGND

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

3

2

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

726

of

5

DESIGN NOTE: 8-bit Data Streaming

VCC3VCC5

HSIP_CLK
HSIP_D0
HSIP_D1

D D

HSIP_D2
HSIP_D3
HSIP_D4
HSIP_D5
HSIP_D6
HSIP_D7
HSIP_D8
HSIP_D9
HSIP_D10
HSIP_D11
HSIP_D12
HSIP_D13
HSIP_D14
HSIP_D15

LDEMOD_HSIP_VSYNC

PFL-2x20-2M0-SMD-S

Mode is the simplest data input mode,
but is limited to 8-bits.

J3

1
3
5
7

9
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

2
4
6
8
10

DGND

HSIP_SYNC

HSIP_HSYNC

High Speed
Input Port

C C

B B

A A

DESIGN NOTE: When using 16 data capture
mode (Mode 4 - BT.601), the TFT interface
cannot be used due to pin sharing conflicts.

DESIGN NOTE: There are two conventions
for connecting 24 bit panels. One is backward
compatible with 18 bit panels. The connections
defined here are backwards compatible.

TFT_R2
TFT_R3
TFT_R4
TFT_R5
TFT_R6
TFT_R1
TFT_R7
TFT_G2
TFT_G3
TFT_G4
TFT_G0
TFT_G1
TFT_G5
TFT_G6
TFT_G7
TFT_B2
TFT_B0
TFT_B1
TFT_B3
TFT_B4
TFT_B5
TFT_B6
TFT_B7

HSYNC_C
VSYNC_C
LDEMOD_HSIP_VSYNC
TFT_R0

TFTCLK
R_F_CLK
DISPEN

51
52
54
55
56

2
3
4
6
7

8
10
11
12
14
15
16
18
19
20
22
23
24
25
27
28
30
50

31
17
32

U2

IN00
IN01
IN02
IN03
IN04
IN05
IN06
IN07
IN08
IN09
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
IN19
IN20
IN21
IN22
IN23
IN24
IN25
IN26
IN27

CLKIN
R_FB
PD

DS90C385

CLKO-

CLKO+

OUT0-

OUT0+

OUT1-

OUT1+

OUT2-

OUT2+

OUT3-

OUT3+

TSSOP56 Package

24-bit LVDS Transmitter

5

VCC
VCC
VCC

LVCC
PVCC

LGND
LGND
LGND

PGND
PGND

GND
GND
GND
GND
GND

1
9
26
44

34

40
39

48
47

46
45

42
41

38
37

36
43
49

33
35
5
13
21
29
53

VCC3

LVDS_AVCC3

TXCLKOUT- 26
TXCLKOUT+ 26

TXOUT0- 26
TXOUT0+ 26

TXOUT1- 26
TXOUT1+ 26

TXOUT2- 26
TXOUT2+ 26

TXOUT3- 26
TXOUT3+ 26

LVDS_PGND

DGND

LVDS_PVCC3

LDVS_AGND

R_F_CLK

4

TFT_R4

TFT_R426

TFT_R3

TFT_R326

TFT_R2

TFT_R226

TFT_R0

TFT_B6

TFT_B626

TFT_B7

TFT_B726

TFT_R6

TFT_R626

TFT_R5

TFT_R526

TFT_B0
TFT_B3

TFT_B326

TFT_B4

TFT_B426

TFT_B5

TFT_B526

TFT_B2

TFT_B226

TFT_G7

TFT_G726

TFT_B1
TFT_G5

TFT_G526

TFT_G1
TFT_G4

TFT_G426

TFT_G3

TFT_G326

TFT_G6

TFT_G626

TFT_G2

TFT_G226

TFT_R7

TFT_R726

TFT_G0
TFT_R1

DESIGN NOTE: The LSB's for
each color (R0,R1,G0,G1,B0,B1)
are not used in by 18-bit panels.

1

R10 0_NL

4

RN69 22

8
7
6

RN70 22

8
7
6

RN71 22

8
7
6

RN72 22

8
7
6

RN73 22

8
7
6

RN74 22

8
7
6

DESIGN NOTE: For 18-bit panels use OUT0,
OUT1, and OUT2. For 24-bit panels use
OUT0, OUT1, OUT2, and OUT3.

VCC3

3

U26C

HSIP_CLK
HSIP_SYNC
TFTCLK

T_R4

1

T_R3

2

T_R2

3

T_R

45

T_B6

1

T_B7

2

T_R6

3

T_R5

45

T_B0

1

T_B3

2

T_B4

3

T_B5

45

T_B2

1

T_G7

2

T_B1

3

T_G5

45

T_G1

1

T_G4

2

T_G3

3

T_G6

45

T_G2

1

T_R7

2

T_G0

3

T_R1

45

TFTCLK26

0

HSIP_D8
HSIP_D9
HSIP_D10
HSIP_D11
HSIP_D12
HSIP_D13
HSIP_D14
HSIP_D15

HSIP_D0
HSIP_D1
HSIP_D2
HSIP_D3
HSIP_D4
HSIP_D5
HSIP_D6
HSIP_D7

VCC3

FB1

1 2

BLM18PG600SN1

1

R8 0

DGND LVDS_PGND

T_B0
T_B1
T_B2
T_B3
T_B4
T_B5
T_B6
T_B7
T_G0
T_G1
T_G2
T_G3
T_G4
T_G5
T_G6
T_G7
T_R0
T_R1
T_R2
T_R3
T_R4
T_R5
T_R6
T_R7

1

C36
10uF

AL12
AL14

AH11

AJ11

AK10

AL10
AJ10

AH10

AJ15

AK15

AL15

AH13

AJ13

AK13

AL13

AK12

3

VIPCLK
VIPSYNC

AE1

DOTCLK/VOPCLK

AH7

DRGB0/VOP7

AK6

DRGB1/VOP6

AL6

DRGB2/VOP5

AJ7

DRGB3/VOP4

AK7

DRGB4/VOP3

AL7

DRGB5/VOP2

AH8

DRGB6/VOP1

AJ8

DRGB7/VOP0

AJ2

DRGB8/VOP15

AK3

DRGB9/VOP14

AL3

DRGB10/VOP13

AH5

DRGB11/VOP12

AJ4

DRGB12/VOP11

AL4

DRGB13/VOP10

AK4

DRGB14/VOP9

AJ5

DRGB15/VOP8

AF2

DRGB16_VOP23

AF1

DRGB17_VOP22

AG3

DRGB18_VOP21

AG4

DRGB19_VOP20

AH1

DRGB20_VOP19

AH2

DRGB21_VOP18

AH3

DRGB22_VOP17

AJ1

DRGB23_VOP16
DRGB24/VID8
DRGB25/VID9
DRGB26/VID10
DRGB27/VID11
DRGB28/VID12
DRGB29/VID13

AL9

DRGB30/VID14

AK9

DRGB31/VID15
VID0

VID1
VID2
VID3
VID4
VID5
VID6
VID7

LVDS_PVCC3

1

C38
100nF

1

C39
10nF

LDEMOD/VIP_VSYNC

DISPEN/VOP_BLANK

VDDEN/VIP_HSYNC

VSYNC/VOP_VSYNC
HSYNC/VOP_HSYNC

AMD GEODE™

LX PROCESSOR

VCC3

1 2

BLM18PG600SN1

1

R9 0

DGND

FB2

RED

GREEN

BLUE

DAVDD
DAVDD
DAVDD
DAVDD

DAVSS
DAVSS
DAVSS
DAVSS

DVREF
DRSET

1

C37
10uF

2

LDEMOD_HSIP_VSYNC

AD4
AE4
AE2

AD3
AE3

W3

V2

U2

W4
V4
U1
V1

W2
Y2
U3
V3

W1
Y1

1

R6

1.2K

1

R601
10

AGND_VGA

LVDS_AVCC3

1

1

C40

C41

100nF

10nF

LDVS_AGND

2

1

DISPEN

HSIP_HSYNC

VSYNC_C

1

R30 22

HSYNC_C

1

R29 22

RED 14

GREEN 14 VSYNC 14

BLUE 14

DACVDD

1

1

C34

C33

10nF

10uF

AGND_VGA

D1

LM4041AIM3-1.2

2 1

1

R7 0

LDEMOD_HSIP_VSYNC 26
DISPEN 26
HSIP_HSYNC 26

1

1

C35

3

10nF

AGND_VGA

DGND

VSYNC_C 26
HSYNC_C 26

VCC3

53

1

VSYNC_C

VCC3

1

R4 1

R5
10K

DESIGN NOTE: AGND_VGA should be an
island with single point connection to the
full ground plane to reduce noise content.
Zero ohm resistor can be removed as
long as above condition is met.

HSYNC_C

2 4

DGND

VCC3

53

1

2 4

DGND

DGND

U22
NC7SZ125/SC70

DGND

U23
NC7SZ125/SC70

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

826

HSYNC 14

of

5

DESIGN NOTE: There are 8 PCI

U1B

devices in this design requireing REQ
/ GNT pairs. Two 1 to 3 expanders
are provided, giving a total of 7 pairs.
Two pairs are mapped to the following
three devices: Ethernet, MiniPCI and
PC104 slot 3. Jumpers are provided

D D

to select.

PCI_C/BE0#11,15,19,20,24
PCI_C/BE1#11,15,19,20,24
PCI_C/BE2#11,15,19,20,24
PCI_C/BE3#11,15,19,20,24

PCI_DEVSEL#11,15,19,20,24

PCI_FRAME#11,15,19,20,24

PCI_IRDY#11,15,19,20,24

REQ_EXT0#
REQ_EXT1#
REQ_EXT2#
PW1

AL18
AJ17

AB1
Y31

AB29
AD28

AE29
AC31

AL17

AK17

AB2
AB4

5

PCI_TRDY#11,15,19,20,24

PCI_STOP#11,15,19,20,24

PCI_RST#11,12,15,16,17,19,20,24,25

PW0
PW1

DOTREF
SYSREF

IRQ13
INTA#

CIS
SUSPA#

TDP
TDN

TDBGI
TDBGO

C C

PW0

PW1

B B

CLK_48_DOT12

CLK_CPU13

IRQ13

IRQ1311

PCI_INTA#11,19,24

CIS11

SUSPA#

SUSPA#11

TDP17
TDN17

TDBGI_CPU

A A

TDBGO_CPU

GNT0#
GNT1#
GNT2#

8
7
6

AA28
AB30
AC30

AA29
AB31
AB28

AJ22

AL26
AH27
AH31

AK25

AL28

AH25
AK26

AJ25

Y30

CLPF

MLPF

VLPF

CAVDD
CAVSS

MAVDD

MAVSS

VAVDD
VAVSS

VCC3

DGND

GNT0#
GNT1#
GNT2#

REQ0#
REQ1#
REQ2#

CBE0#
CBE1#
CBE2#
CBE3#

DEVSEL#
FRAME#

IRDY#
TRDY#

STOP#
RESET#

W29
V29
AA3

W31
W30

V31
V30

AA1
AA2

LX PROCESSOR

COREPLLVDD

GNT0#24
GNT2#11

REQ0#

REQ0#24

REQ1#
REQ2#

REQ2#11

PCI_DEVSEL#
PCI_FRAME#

PCI_IRDY#
PCI_TRDY#

PCI_STOP# PCI_AD30

PCI_RST#

RN68 10K

1
2
3
4 5

U1D

AMD GEODE™

LX PROCESSOR

TMS
TDO

TCLK

AB3

TDI

AA4
AC1
AC2

4

AJ27

PAR

PCI_AD0

AJ19

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29

AMD GEODE™

PCI_DEVSEL#
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#

PCI_STOP#
REQ0#
REQ1#
REQ2#

GLPLLVDD COREPLLVDD

DOTPLLVDD

JTAGTDI
JTAGTMS

JTAGTCK

4

AD30
AD31

RN44 10K

1
2
3
4 5

RN54 10K

1
2
3
4 5

1

C45
220pF

CPLLGND

GLPLLGND

TDO_CPU 12

CPLLGND DGND

DPLLGND

GLPLLGND

1

C46
220pF

AH19
AL20
AK20
AK19
AH21
AJ21
AL19
AK22
AL22
AK23
AH22
AL23
AL25
AH24
AJ24
AJ28
AK28
AL29
AJ30
AK29
AJ31
AH30
AH29
AG29
AG28
AF30
AE28
AF31
AE30
AE31
AD29

8
7
6

8
7
6

1

DPLLGND

1

1

1

PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29

PCI_AD31

VCC3

DESIGN NOTE: CLKFB output
is used internally by the 8209 to
produce the zero delay.

C47
220pF

R35 0

R36 0

DGND

R38 0

DGND

PCI_PAR 11,15,19,20,24

PCI_AD[31:0] 11,15,19,20,24

--- --- --- --- --- --- ---

Off On Off Off Off 500 400
Off On Off Off On 500 333
Off On On On On 433 333
On On On On On Bypass Bypass

REQ_EXT0#20

CLK_EXT13

CLKFB_EXT

DOTPLLVDD

GLPLLVDD

3

5 4 3 2 1 CORE MEM

VCC3

VCC3_EXT1

U3

21

28

96

13

REQ_EXT0#
REQ_EXT1#
REQ_EXT2#

GNT1#
PCI_FRAME#

PCI_STOP#

PCI_RST#

1

C48
10nF

CPLLGND VCC3

1

C51
10nF

DPLLGND VCC3

1

C54
10nF

GLPLLGND

3

NC

5

REQ1

8

REQ2

11

REQ3

1

FRAME

2

STOP

26

RESET

27

CLKIN

14 15

NC NC

1

R31 10K

DGND

1

R33 1

1

R34 1

1

R37 1

1

C49
10nF

1

C52
10nF

1

C55
10nF

VCCVSS

172425

VCC

VSS

NC

AVCC

GNT1
GNT2
GNT3

S_REQS_GNT

CLKFB

CLK1
CLK2
CLK3
CLK4

VSS

AVSS

IT8209R

GND_EXT1

VCC3

1

C50
10uF

1

C53
10uF

1

C56
10uF

PW0

5

SUSPA#

4

GNT2#

3

GNT1#

2

GNT0#

1

Debug
Stall

IRQ13

16
7

GNT_EXT1#

10

GNT_EXT2#

12

REQ1#

34

CLKFB_EXT

23
22
20
19
18

VCC3

BLM18PG600SN1

DGND GND_EXT1

DESIGN NOTE:
COREPLLGND, DOTPLLGND
and GLPLLGND should each
be an island with single point
connection to the full ground
plane to reduce noise content.
Zero ohm resistor can be
removed as long as above
condition is met.

CLK_EXT0 20
CLK_EXT1 19
CLK_EXT2 15

FB3

1 2

1

R32 0

JP-1x2_NL

1

R21 1K_NL

1

R22 10K

GNT_EXT0# 20

1

C42
10uF

2

1

R11 10K_NL

1

R12 1K

1

R13 10K_NL

1

R14 1K

1

R15 10K_NL

1

R16 1K

1

R17 10K_NL

1

R18 1K

1

R19 10K_NL

1

R20 1K

Normal
Setting

2

VCC3

Off
On
Off
On
Off
On

JTAGTCK
TDBGI_CPU
JTAGTDI
JTAGTMS

Off
On

J4

1

1

C43
100nF

2

DGND

VCC3_EXT1

1

C44
10nF

TDBGI_CPU
TDBGO_CPU

Off
On

REQ_EXT1#

REQ_EXT2#

GNT_EXT1#

GNT_EXT2#

DESIGN NOTE: Two REQ/GNT pairs are mapped
to the following three devices: Ethernet, MiniPCI
and PC104 slot 3. Jumpers are provided to select.

DGND DGND

11
13

1
3
5
7
9

J7

PFL-7X2

J5

1
3
5
7
9

11 12

PFL-2x6-2M0-SMD-S

J6

1
3
5
7
9

11 12

PFL-2x6-2M0-SMD-S

2
4
6
8
10
12
14

JTAG HEADER

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Schematic

Document Number Rev
Size

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

RN28

1
2
3
4 5

4.7K

2
4
6
8
10

2
4
6
8
10

VCC3

JTAGTDI

1

VCC3

8
7
6

REQ#_LAN 15
REQ#_MPCI 19
REQ#_PC3 24

GNT#_LAN 15
GNT#_MPCI 19
GNT#_PC3 24

JTAGTCK 12
JTAGTMS 12

JTAGTDO 12
SYS_RST# 11,17,25

DESIGN NOTE: Add
"JTAG HEADER" to
the silkscreen

926

of

5

VCC3

D D

C C

VCCMEM

B B

A A

5

AL11
AG31
AA31
AC29
AD31

AJ3
AD1
AC3

AJ6

AJ9

AJ12

AG1

AF29

AJ14
AJ18
AJ20
AJ23
AJ26

AK1

AJ29

AF3

AK31

AL2

AL8

AL24
AL21

AL5

AL27
AL30

B11

A14

B31
C29

P29
C14
C18

A18

B24
C25

B27
D28

E30
G29

B21
H31

K29

L31

A30
N29

VCORE

P13

P14

D15

P18

P19

R28

U28

U29

U30

U31

V13

V14

V18

V19

V28T1T3

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

Y3

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

D4

VMEM

C7

VMEM

N4

VMEM
VMEM

H1

VMEM

L1

VMEM

B8

VMEM
VMEM
VMEM
VMEM
VMEM

B5

VMEM
VMEM

K3

VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM

C3

VMEM

A2

VMEM

B1

VMEM

E2

VMEM

G3

VMEM

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AK27

AK30

AL1

AL16

AH16B3C1P4R2

AL31

AK8

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AK18

AK16

AK14

AK11

AK21

AK24

4

N13

N14T4N18

N19

VDD

VDD

VDD

VDD

VDD

VDD

VDD

AMD GEODE™

LX PROCESSOR

VSS

VSS

VSS

VSS

VSS

VSS

VSS

U19

C12

AH23

AH26

AF4

AH18

4

U1E

U18

VDD

VSS

U17

VDD

VSS

U16

VDD

VSS

AH15U4AH17T2Y28

U15

VDD

VSS

W19

U14

VDD

VSS

W18

U13

VDD

VSS

W14

T31

VDD

VSS

W13

T30

VDD

VSS

D17

VDD

VSS

VSS

AF28

VSS

VSS

T29N3K4

3

VCORE

W17A1E1B2R4

AH28

D10

VSS

VSS

A3

VSS

VSS

VSS

VSS

VSS

VSS

B14

VSS

A16

VSS

D18

VSS

AJ16

VSS

V17

VSS

AK2

VSS

V16

VSS

V15

VSS

R15

VSS

R14

VSS

R13

VSS

P28

VSS

L2

VSS

N16

VSS

A31

VSS

A27

VSS

N15

VSS

D16

VSS

D7

VSS

N17

VSS

N28

VSS

P15

VSS

P16

VSS

P17

VSS

H2

VSS

A11

VSS

R16

VSS

R17

VSS

R18

VSS

AH12

VSS

Y29

VSS

AA30

VSS

AD30

VSS

AG2

VSS

AH9

VSS

AH4

VSS

AH6

VSS

AG30

VSS

R19

VSS

AH20

VSS

C2

VSS

C4

VSS

A8

VSS

W16

VSS

W15

VSS

D25

VSS

B18

VSS

AH14

VSS

A24

VSS

A29

VSS

B29

VSS

B30

VSS

C28

VSS

C30

VSS

C31

VSS

D29

VSS

E31

VSS

G28

VSS

K28

VSS

P31

VSS

W28

VSS

AC28

VSS

D3

VSS

A5

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

G4

AC4

AD2R1Y4

H30

T13

VCC3

VCCMEM

D14

D22

C21

A21

AK5

R3

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

L30

T14

T15

T16

T17

T18

T19

T28

1

C57
22uF

1

C64
1nF

1

C72
22uF

1

C79
1nF

1

C87
22uF

1

C94
100pF

1

C102
22uF

1

C109
100pF

1

C65
1nF

1

C80
1nF

1

C95
100pF

1

C110
100pF

2

1

C58
22uF

1

C73
22uF

1

C88
22uF

1

C103
22uF

1

C66
1nF

1

C81
1nF

1

C96
100pF

1

C111
100pF

1

C59
22uF

1

C74
22uF

1

C89
22uF

1

C104
22uF

1

C67
1nF

1

C82
1nF

1

C97
100pF

1

C112
100pF

1

C60
10nF

1

C75
10nF

1

C90
10nF

1

C105
10nF

1

C68
100pF

1

C83
100pF

1

C98
100pF

1

C113
100pF

1

C61
10nF

1

C69
100pF

1

C76
10nF

1

C84
100pF

1

C91
10nF

1

C99
100pF

1

C106
10nF

1

C114
100pF

1

C70
100pF

1

C85
100pF

1

C100
10nF

1

C115
10nF

1

C62
10nF

1

C77
10nF

1

C92
10nF

1

C107
10nF

1

C71
100pF

1

C86
100pF

1

C101
10nF

1

C116
10nF

1

C93
10nF

1

C63
10nF

1

C78
10nF

1

C108
10nF

1

DGND

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.
Longmont CO 80501

DGND

3

2

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

10 26

of

5

PCI_AD[31:0]9,15,19,20,24

D D

DESIGN NOTE: Any
GPIO can be used as
an IRQx or INT#x.
There are significant
bootloader configuration
changes required if
selection is different than
shown. Changes are
highly discouraged.

C C

PCI_PAR9,15,19,20,24

PCI_C/BE0#9,15,19,20,24
PCI_C/BE1#9,15,19,20,24
PCI_C/BE2#9,15,19,20,24
PCI_C/BE3#9,15,19,20,24

PCI_FRAME#9,15,19,20,24

PCI_IRDY#9,15,19,20,24

PCI_DEVSEL#9,15,19,20,24

PCI_TRDY#9,15,19,20,24
PCI_INTA#9,19,24
PCI_STOP#9,15,19,20,24

GNT2#9
REQ2#9

B B

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6

PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_INTA#

R17
T17
R16
T16
P16
T15
R15
P15
T14
R14
U13
T13
R13
U12
T12
R12

U10
U14

U11

R10
R11
T10

T11

U8
R8

U7
R7

U6
U5
R5
R4

U3
U1

R6
U9

R2

R1

T8

T7

T6
T5
T4

T3

T9

T1

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PAR
C/BE0#

C/BE1#
C/BE2#
C/BE3#

FRAME#
IRDY#
DEVSEL#
TRDY#
GPIO0
STOP#

GNT#
REQ#

U4A

GPIO6/MFGPT0_RS/MFGPT1_C1/MFGPT2_C2

GPIO11/SLP_CLK_EN#/MFGPT1_C2

AMD GEODE™

CS5536

COMPANION
DEVICE

4

PCI_CLK

WORKING

GPIO28/PWR_BUT#

GPIO5/MFGPT1_RS/MFGPT0_C1

GPIO7/MFGPT2_C1/SLEEP_X

GPIO8/UART1_TX/UART1_IR_TX

GPIO9/UART1_RX/UART1_IR_RX

GPIO10/THRM_ALRM#

GPIO24/WORK_AUX

GPIO25/LOW_BAT#/MFGPT7_C2

GPIO26/MFGPT7_RS

GPIO27/MFGPT7_C1/32KHZ

GPIO13/SLEEP_BUT

GPIO12/AC_S_IN2/SLEEP_Y

RESET_OUT#

RESET_STAND#

RESET_WORK#

SUSP#/CIS

SUSPA#

IRQ13

MHZ14_CLK

KHZ32_XCI

KHZ32_XCO

USB_PTEST

TEST_MODE

LVD_TEST

FUNC_TEST

U4
C5
A8

D3
D2

C2
E3

D1
C3

A1
C9

A9
B7

C8
F2

J3
A5

B8
C6

P3
N1

K2
C1

A4
B3

G15

A6
B9

F3

WORKING
PWRBTN#

IDE_CABLEID#
5536_GPIO6

PCI_INTB#PCI_AD7

WORK_AUX
CS5536_GPIO25

PME#
MFGPT7_C1

PCI_INTD#
PCI_INTC#

RST_STB#
SYS_RST#

TEST_MODE

FUNC_TEST

3

CLK_IOC 13

WORKING 25

PWRBTN# 25
IDE_CABLEID# 21

PCI_INTB# 15,19,24

CS5536_GPIO8 17
CS5536_GPIO9 17

OT_ALARM 17
SLP_CLK# 13

WORK_AUX 25
CS5536_GPIO25 17

PME# 15,17,19,25

PCI_INTD# 24
PCI_INTC# 24

PCI_RST# 9,12,15,16,17,19,20,24,25
RST_STB# 25
SYS_RST# 9,17,25

CIS 9

SUSPA# 9

IRQ13 9
CLK_14_IOC 13

RTCXIN
RTCXOUT

DESIGN NOTE:
LED is optional.

5536_GPIO6

MFGPT7_C1

WORK_AUX
PME#
MFGPT7_C1

PWRBTN#
WORKING
CS5536_GPIO25
RST_STB#

SLP_CLK#
IDE_CABLEID#
SYS_RST#

PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#

TEST_MODE
FUNC_TEST

1

R94 0_NL

1

R95 0

PWR MANAGEMENT

RED

D2

1

12

LTST-C190EKT

R46 560

1

R39 1K

1

R40 5.6K

1

R41 5.6K

RN29 10K

1
2
3
4 5

RN30 10K

1
2
3
4 5

RN31 10K

1
2
3
4 5

1

R42 1K

1

R43 1K

LAN_PD# 15
CS5536_GPIO6 17

VCC5SB

2

8
7
6

8
7
6

8
7
6

VCC3SB

DGND

RTCXIN

RTCXOUT

VCC3

1

R441M

1

C119
22pF

DGND DGND

C117

1

1pF

1

R4522M

1 4

Y1

32.768KHz

ABS13-32.768KHz-12.5pF - T

C118
22pF

1

1

VCC3

1

1

R91

R93

330R

VCC3SB

DESIGN NOTE: GPIO24/WORK_AUX is an
open drain output, which requires a pullup
resistor to achieve a high state. At initial
standby power application the
GPIO24/WORK_AUX pin defaults to GPIO24
and the GPIO24 defaults as an input. This

A A

default combination will leave the pin in a
high state due to the pullup which is
normally connected to VCC3SB. This circuit
works aournd that behaviour so that Save to
RAM will function correctly.

5

1

C120
100nF

DGND

WORK_AUX
WORKING

1
2

SAVE TO RAM SUPPORT

53

U5

4

NC7SZ08/SC70

DGND

4

1

R48 10K

INVERTER

1

C122

4.7uF

DGND

VCC3SB

1

R47
10K

DGND

Q1
BSS138/SOT

3

1

C121
100nF

PS_ON# 25

2

MFGPT7_C1

IDE_LED21

EXT_PWRBTN#25

EXT_RST#25

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

Date: Sheet

B

J31

2

1

4

3

6

5

8

7

PFL-2x4-2M0-SMD-S

DGND

40744 D

Wednesday, April 11, 2007

330R

1

11 26

of

5

IDE_D[15:0]21

D D

C C

B B

A A

IDE_RST#21

IDE_D7
IDE_D8
IDE_D6

IDE_D9
IDE_D5
IDE_D10
IDE_D4

IDE_D11
IDE_D3
IDE_D12
IDE_D2

IDE_D13
IDE_D1
IDE_D14
IDE_D0

IDE_D15

IDE_DRQ#21

IDE_RDY#21
IDE_ACK#21

DESIGN NOTE: Place series R
near the audio CODEC.

SDATA_IN

BITCLK

DESIGN NOTE: USBPWR_EN1/2 and
USB_OC# are used for a fully compliant
USB design. See Option Schematics for
fully compliant USB design.

IDE_DRQ#

IDE_IOW#21
IDE_IOR#21

IDE_RDY#
IDE_IRQ

IDE_IRQ21

IDE_A121

IDE_A021

IDE_A221
IDE_CS0#21
IDE_CS1#21

1

R65 22

1

R63 22

5

RN32 22

1
2
3
4 5

RN34 22

1
2
3
4 5

RN36 22

1
2
3
4 5

RN37 22

1
2
3
4 5

RN38 22

1
2
3
4 5

RN39 22

1
2
3
4 5

RN40 22

1
2
3
4 5

AC97_DATA_IN 16
AC97_BITCLK 16

I_RST#

8

I_D7

7

I_D8

6

I_D6

I_D9

8

I_D5

7

I_D10

6

I_D4

I_D11

8

I_D3

7

I_D12

6

I_D2

I_D13

8

I_D1

7

I_D14

6

I_D0

I_D15

8

I_DRQ#

7

I_IOW#

6

I_IOR#

I_RDY#

8

I_ACK#

7

I_IRQ

6

I_A1

I_A0

8

I_A2

7

I_CS0#

6

I_CS1#

SDATA_IN
SDATA_OUT_BOS1

PCBEEP16

CLK_48_DOT9

USB_PWR_EN118
USB_PWR_EN218

USB_OC#18

USB0+18

USB0-18

USB1+18

USB1-18

USB2+18

USB2-18

USB3+18

USB3-18

CLK_IDE13

BITCLK

SYNC_BOS0

I_IRQ
I_RST#

I_A0
I_A1
I_A2
I_ACK#
I_DRQ#
I_IOR#
I_IOW#
I_RDY#
I_CS0#
I_CS1#

I_D0
I_D1
I_D2
I_D3
I_D4
I_D5
I_D6
I_D7
I_D8
I_D9
I_D10
I_D11
I_D12
I_D13
I_D14
I_D15

4

B12

GPIO2/IDE_IRQ0

F15

IDE_RESET#

A10

MHZ66_CLK

A11

IDE_AD0/FLASH_AD25/AD0/FLASH_CLE

A12

IDE_AD1/FLASH_AD26/AD1

B11

IDE_AD2/FLASH_AD27/AD2

C12

IDE_DACK0#/FLASH_CS3#/FLASH_CE3#

A14

IDE_DREQ0/FLASH_CS2#/FLASH_CE2#

B13

IDE_IOR0#/FLASH_RE#

C13

IDE_IOW0#/FLASH_WE#

A13

IDE_RDY0/FLASH_IOCHRDY/FLASH_RDY/BUSY#

B10

IDE_CS0#/FLASH_CS0#/FLASH_CE0#

C10

IDE_CS1#/FLASH_CS1#/FLASH_CE1#

B14

IDE_DATA0/FLASH_AD10/IO0

A15

IDE_DATA1/FLASH_AD11/IO1

C15

IDE_DATA2/FLASH_AD12/IO2

C16

IDE_DATA3/FLASH_AD13/IO3

B17

IDE_DATA4/FLASH_AD14/IO4

D15

IDE_DATA5/FLASH_AD15/IO5

E15

IDE_DATA6/FLASH_AD16/IO6

E16

IDE_DATA7/FLASH_AD17/IO7

E17

IDE_DATA8/FLASH_AD18/AD3

D17

IDE_DATA9/FLASH_AD19/AD4

D16

IDE_DATA10/FLASH_AD20/AD5

C17

IDE_DATA11/FLASH_AD21/AD6

A17

IDE_DATA12/FLASH_AD22/AD7

B16

IDE_DATA13/FLASH_AD23/AD8

B15

IDE_DATA14/FLASH_AD24/AD9

C14

IDE_DATA15/FLASH_ALE

K3

GPIO1/AC_BEEP/MFGPT0_C2

M1

AC_CLK

L3

AC_S_SYNC/BOS0

L1

AC_S_IN

L2

AC_S_OUT/BOS1

N17

MHZ48_CLK

P17

USB_PWR_EN1

N16

USB_PWR_EN2

N15

USB_OC_SENS#

K16

USB1_DATPOS

K17

USB1_DATNEG

L16

USB2_DATPOS

L17

USB2_DATNEG

H17

USB3_DATPOS

H16

USB3_DATNEG

G17

USB4_DATPOS

G16

USB4_DATNEG

SDATA_OUT_BOS1
SYNC_BOS0

BOS1

BOS0

4

1

R64 22

1

R66 22

DESIGN NOTE: Place
series R near the IOC.

1

R67 10K_NL

1

R68 1K

1

R69 10K_NL

1

R70 1K

U4B

LPC_SERIRQ/GPIO21/MFGPT2_RS

AMD GEODE™

CS5536

COMPANION
DEVICE

AC97_DATA_OUT 16
AC97_SYNC 16

VCC3

DGND

3

LPC_CLK
LPC_AD0/GPIO16
LPC_AD1/GPIO17
LPC_AD2/GPIO18
LPC_AD3/GPIO19

LPC_DRQ#/GPIO20

LPC_FRAME#/GPIO22

GPIO14/SMB_CLK

GPIO15/SMB_DATA

GPIO3/UART2_RX

GPIO4/UART2_TX

TCK
TDO

TMS

T_DEBUG_IN

T_DEBUG_OUT

LVD_EN#

USB_REXT
USB_VBUS

MHZ48_XCO

MHZ48_XCI

MHZ48_XCEN

BOS10BOS0

0
1
0
1

3

2

LPC Header

VCC3 VCC3

J8

1
3
5
7

9
11
13
15
17
19

DGND

CLK_LPC_IOC

H1

LAD0

H2

LAD1

J2

LAD2

J1

LAD3

K1

LDRQ#

G1

LFRAME#

H3

SERIRQ

G2

SMB_SCL

G3

SMB_SDA

F1

CRT_SCL

E1

CRT_SDA

E2

N2
P1

TDI

P2
N3

TDBGI_IOC

M2
M3

LVD_EN#

C7

CLK_LPC_IOC 13
LAD0 17
LAD1 17
LAD2 17
LAD3 17
LDRQ# 17
LFRAME# 17
SERIRQ 17,20

CRT_SCL 14,26
CRT_SDA 14,26

JTAGTCK 9
TDO_CPU 9
JTAGTDO 9
JTAGTMS 9

PFL-2x10

SMB_SCL 7
SMB_SDA 7

2
4
6
8
10
12
14
16
18
20

PCI_RST# 9,11,15,16,17,19,20,24,25

CLK_LPC_IOC
LAD3
LAD2
LAD1
LAD0
LFRAME#
SERIRQ
LDRQ#

DESIGN NOTE: This design uses LVD (LVD_EN# tied
low) to generate system reset. Since LVD only monit ors
Vcore in the working domain, the designer must

LAD0
LAD1
LAD2
LAD3

LDRQ#
SERIRQ
LFRAME#

XCEN
SMB_SCL
SMB_SDA
TDBGI_IOC
IDE_RDY#
IDE_IRQ
USB_OC#
PCBEEP
IDE_D7
IDE_DRQ#
LVD_EN#

CRT_SCL
CRT_SDA

1

RN33 10K

1
2
3
4 5

RN35 10K

1
2
3
4 5

1

R49 1K

1

R50 2.2K

1

R51 2.2K

1

R52 4.7K

1

R53 10K

1

R54 10K

1

R55 10K

1

R56 10K_NL

1

R57 10K

1

R58 10K

1

R59 10K

1

R60 2.2K

1

R61 2.2K

VCC3

8
7
6

8
7
6

DGND

VCC5

guarantee that Vio and other required voltages are

USB_REXT

K15
M15

XTALO_48

J15

XTALI_48

H15

XCEN

F17

BOOT STRAP OPTIONS

LPC ROM OFF LPC
NOR FLASH OFF IDE INTERFACE

0

RESERVED

1

SST FWH OFF LPC (DEFAULT)

1

1

DGND

R62

3.4K,1%

valid at or before Vcore. If this cannot be guaranteed,
then RESET_WORK# must be used to hold system in
reset until Vio and Vcore and any other required
voltages are valid.

XTALO_48
XTALI_48

*AMD CONFIDENTIAL*

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Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

2

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

C123
18pF

Y2

1 2

48.0000MHz

1

1

C124
18pF

DGNDDGND

12 26

of

5

DESIGN NOTE: If this schematic is used

DESIGN NOTE: Without UL approval
of the internal VBAT circuity, a 47 ohm
resistor (R1) is required. UL approval
is in process and is expected. With

D D

UL approval R1 can be removed.

J1

1-2

2-3 Clear CMOS

C C

B B

A A

VCC3

1

C157
22uF

DGND

Normal

1

C158
100nF

5

VCC3SB

VCC5

1

C162
18pF

DGND

1

C159
100nF

SLP_CLK#11

1 2

14.31818MHz

1

R75 10M_NL

for future designs, R72 should be replaced
with a 220_2A ferrite bead.

R1

1

R71 47

12

BT1

+

J1

VBH2032-1

DGND

330_NL

1

R213

DGND

1

C161
100nF

DGND

CLKX1

CLKX2

1

C163
18pF

1 2

1

R215
1K_NL

D19

BAS40_NL

U6

17

10

2

3

330_NL

1

R214

1

C160
100nF

Y3

DGND

J9

PFL-1x3

DGND

PD#

SEL66/33#

XTALIN

XTALOUT

1

C222
220M_NL

1

1
2
3

D17

1 2

BAS40_NL

D18

1 2

BAS40_NL

1211

87

19

VDDGND

VDDGND

VDD

VDD

GND

GND

15

4

1

R73
1K

DGND

VBAT

25428

VDD

VDD

REFCLK1

REFCLK0/SP#

48MHz

48MHz/TS#

66MHz

LCLK2
LCLK1
LCLK0

PCICLK0
PCICLK1
PCICLK2
PCICLK3

GND

GND

MK1491-09F

22

21

DGND

4

1

C127
100nF

26
27

13
14

16

9
6
5

18
20
23
24

VCC3SB

1

C128
22uF

DGND

VCC3

1

FB4

HI1206N101R-00

14_318MHZ0
14_318MHZ1

48MHZ

IDE_CLK

PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3

LCLK0
LCLK1

VCORESB

1

C129
10nF

VCC3USB

1

C143
22uF

DGND

VCORE

3

VBAT

1

R72 4.7R

1

C130
10nF

1

C144
10nF

14_318MHZ0
14_318MHZ1

IDE_CLK

PCI_CLK3
PCI_CLK2
PCI_CLK1
PCI_CLK0

48MHZ

LCLK0
LCLK1

1

1

C132

C131

100nF

1uF

VCORE

1

1

C146

C145

100pF

10nF

VCC3

DESIGN NOTE: Enables
spread spectrum. EMI
mitigation technique

RN41

1
2
3
4 5

22

1

R23 22

RN42

1
2
3
4 5

22

RN43

1
2
3
4 5

22

DESIGN NOTE: Swap series resistors
on the clock lines in order minimize
the number of vias.

3

M14

K14
H14

D10

P10

P14
F14

D14

D12

P12

8
7
6

8
7
6

8
7
6

A3

A7
B6

D8
H4
K4
P8

D9
D6
D4
F4

M4

P4
P6
P9

VBAT

VCORE_VSB
VIO_VSB

VDDC_USB1
VDDC_USB0

VCORE
VCORE
VCORE
VCORE
VCORE
VCORE

VDDIO_USB0
VDDIO_USB1
VDDIO_USB2
VDDIO_USB3

VIO
VIO
VIO
VIO
VIO
VIO
VIO
VIO
VIO
VIO

U4C

AMD GEODE™

CS5536

COMPANION
DEVICE

1

R74 10K

DGND

CLK_14_CODEC 16
CLK_14_ISA 24
CLK_14_IOC 11

CLK_IDE 12

PC_CLK 24
CLK_EXT 9
CLK_IOC 11
CLK_CPU 9

SIO_CLK_48 17
CLK_LPC_SIO_EXT 17

CLK_LPC_IOC 12

VSSIO_USB0
VSSIO_USB1
VSSIO_USB2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

L15

NC

R9

NC

U17

NC

U16

NC

F16

NC

J16

NC

M16

NC

U15

NC

C11

NC

A16

NC

R3

NC

M17

NC

J17

NC

B5

NC

B4

NC

B1

NC

T2

NC

U2

NC

A2

NC

C4

NC

B2

NC

L14
J14
G14

N14
E14
D13
D11
D7
D5
E4
G4
J4
L4
N4
P5
P7
P11
P13

DGND

VCC3

1

C125
22uF

1

C133
10nF

1

C138
100pF

VCORE

1

C147
22uF

1

C149
10nF

1

C154
100pF

1

C134
10nF

1

C139
100pF

1

C126
22uF

1

C135
10nF

1

C140
100pF

1

C148
22uF

1

C150
10nF

1

C155
100pF

1

1

1

C136

C137

10nF

10nF

1

1

C142

C141

100pF

100pF

1

1

C151

C152

10nF

10nF

1

C156
100pF

DGND

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

2

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

13 26

of

5

4

3

2

1

D D

L1

RED8

GREEN8

C C

BLUE8 CRT_SCL 12,26

1

B B

R80
75

1

R81
75

1

R82
75

1

C164

4.7pF

1

1

C165

4.7pF

22nH

L2

1

22nH

INDUCTOR, 22NH, 5%, 0603, 0.48A

L3

1

22nH

INDUCTOR, 22NH, 5%, 0603, 0.48A

1

C166

4.7pF

AGND_VGA

INDUCTOR, 22NH, 5%, 0603, 0.48A

1

C167

4.7pF

VCC3

DGND

1

C168

4.7pF

D4

BAV99/SOT

1

C169

4.7pF

VCC5

1

1

C171
100nF

DGND

D5

BAV99/SOT

F1

1.10A, 16V

D3

BAV99/SOT

MRED
MGREEN MDDAT_UART_TX

MBLUE

DESIGN NOTE: Place
the ESD protection
components as close to
the VGA connector as

VCC3

D6

possible.

BAV99/SOT

DGND

C6
C1
C7
C2
C8
C3
C9
C4

C10

C5

P1C CON-COMBO-DB9-15-25-TRIPLEPORT

VGA

MTG5

MTG6

VGA_CHASSIS

C11
C12
C13
C14
C15

DGND

C170

1

100nF

FB5

BLM18PG600SN1

1

D7

BAV99/SOT

VGA_CHASSIS

D8

BAV99/SOT

D9

BAV99/SOT

MCRT_HSYNC
MCRT_VSYNC
MDDCLK_UART_RX

R76 0
R77 0
R78 0
R79 0

CRT_SDA 12,26
HSYNC 8
VSYNC 8

A A

5

4

3

2

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

14 26

of

5

D D

1 2

1

C187
22uF

1

C191
100nF

V_LAN_12A

1

C183
22uF

1

C188
100nF

1

C192
100nF

V_LAN_12

V_LAN_12

BLM18PG600SN1

FB8

1 2

1

C181
100nF

VCC3V_LAN

1

C180
22uF

DGND

C C

VCC3

BLM18PG600SN1

B B

A A

1

C182
100nF

FB7

1 2

1

C190
22uF

DGND

FB6
BLM18PG600SN1

V_LAN_12A_PLL

DGND

5

PCI_AD[31:0]9,11,19,20,24

1

1

C185
100nF

1

C186
100nF

PCI_C/BE0#9,11,19,20,24
PCI_C/BE1#9,11,19,20,24
PCI_C/BE2#9,11,19,20,24
PCI_C/BE3#9,11,19,20,24

GNT#_LAN9

REQ#_LAN9

PCI_DEVSEL#9,11,19,20,24

PCI_STOP#9,11,19,20,24
PCI_TRDY#9,11,19,20,24
PCI_IRDY#9,11,19,20,24

PCI_FRAME#9,11,19,20,24

PCI_PAR9,11,19,20,24

PCI_INTC#11,19,24

PCI_RST#9,11,12,16,17,19,20,24,25
CLK_EXT29

C184
100nF

VCC3

1

1

R88

R87

10K

10K

PME#11,17,19,25

25MHZ Crystal

Y4

1

C194
22pF

DGND

4

V_LAN_12A

V_LAN_12

U7

PCI_AD0

128

PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_AD24

100R90

1

1

C195
22pF

4

PAD0

127

PAD1

126

PAD2

122

PAD3

121

PAD4

120

PAD5

119

PAD6

118

PAD7

117

PAD8

116

PAD9

115

PAD10

114

PAD11

113

PAD12

112

PAD13

111

PAD14

110

PAD15

109

PAD16

106

PAD17

105

PAD18

104

PAD19

103

PAD20

102

PAD21

101

PAD22

100

PAD23

99

PAD24

98

PAD25

97

PAD26

96

PAD27

95

PAD28

94

PAD29

93

PAD30

89

PAD31

88

CBE0#

87

CBE1#

86

CBE2#

85

CBE3#

80

SERR#

77

PERR#

76

GNT#

75

REQ#

74

DEVSEL#

73

IDSEL

72

STOP#

71

TRDY#

70

IRDY#

69

FRAME#

68

PAR

14

PME#

16

INTR

67

RST#

12

PCLK

65

X1

66

X2

V_LAN_12A_PLL

24

91

4357386310791085150

VDDA

VDDA

VDDA

VDDC

VDDCO

DGND

DGND

DGND

DGND

9237890107

34

35

VDDIO

VDDAP

DGND

DGND

DGND

DGND

DGND

1233739424754586264

124

3

VCC3V_LAN

VCC3

125

33

921732

VDDIO

AGND

VDDIO

VDDIO

AGND

AGND

VDDATX

VDDARX

FXSD1/NC

TESTEN

SCANEN

P1LED0
P1LED1
P1LED2
P1LED3
P2LED0
P2LED1
P2LED2
P2LED3

PWRDN

AGND

AGND

KSZ88XX-PMQL

DGND

3

TXP1
TXM1
RXP1
RXM1

TXP2
TXM2
RXP2
RXM2

ISET

EEEN
EECS
EEDO
EESK

EEDI

49
45
46

56
55
53
52

44
61

59

NC

60

NC

1
2
40

NC

41

NC

5
4
3
27
8
7
6
22

26
19
28
29
30

81

NC

82

NC

83

NC

84

NC

11

NC

13

NC

15

NC
NC

18

NC

20

NC

21

NC
NC
NC

VCC3

25
31

36

VDDIO

VDDIO

VDDIO

AGND

AGND

AGND

48

R83 1K
R84 3K,1%

R85 1K
R86 1K

R89 10K

1

R92
10K

TXP1 18
TXM1 18
RXP1 18
RXM1 18

TXP2 18
TXM2 18
RXP2 18
RXM2 18

VCC3

EECS
EEDO
EESK
EEDI

L
H

LAN_PD# 11

DGND

DefinitionPWRDN
Powerdown

Normal

2

P1LED2 18
P1LED3 18

P2LED2 18
P2LED3 18

2

VCC3

1

1

C173
100nF

VCC

ORG

1

C174
100nF

8
7

NC

6

C175
100nF

VCC3

DGND

1

C176
100nF

EECS
EESK
EEDO
EEDI

1

C172
22uF

DGND

U8

1

CS

2

SK

3

DI

4 5

DO GND

AT93LC46 MSOP8

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Schematic

Document Number Rev
Size

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

C193
100nF

1

1

1

C177
100nF

15 26

1

C178
100nF

1

C179
100nF

of

5

J10A

L1

Red Mic In

D D

Green Line Out

C C

B B

Blue Line In

1

FB34

BLM18PG600SN1

1

DGND AUD_CHASSIS

R1
R2

AGND

AJ3595

5

GND_AUD

J10B

R1
R2

SHLD

SHLD

AJ3595

14

15

AUD_CHASSIS

J10C

R1
R2

SHLD

SHLD

AJ3595

16

17

AUD_CHASSIS

C189
100nF

L2

L1
L2

L1
L2

Buzzer

PCBEEP12

A A

R202 10K

5

1
2
3
4

FRONT_OUT_L

6
7
8

FRONT_OUT_R

9

LINE_IN_LLINE_IN_L

10
11
12

LINE_IN_RLINE_IN_R

13

JD1

1

C341
100nF

MIC1
JD0

MIC2

JD2

DGND

VCC3

1

R203
1K

MIC2
MIC1

1

R109
10K_NL

JD2
JD1 JD_1

LINE_IN_R
LINE_IN_L

1

C214
220pF

DGND

1

100nFC342

10KR197
10KR198
10KR199

1

C207
100pF

GND_AUD GND_AUD

1 2

FERR

FB14 FB/120

1 2

FERR

FB15 FB/120

1

C215
220pF

GND_AUD GND_AUD

10K

Q2
BSS138/SOT NL

R108 22_NL

AC97_PCBEEP

1
1
1

R130

1

C208
100pF

4

1

C201

3.3uF

1 2

FERR

FB10 FB/120

1 2

FERR

FB11 FB/120

1

R102

4.7K

1

R106
22K

1

4

1

R103

4.7K

1

R107
22K

VCC3

1

C202

3.3uF

VREFOUT

12

+-

1

4

3

R127
22K

0R104
0R105

NC
NC

1
1

VCC5

JD_2

JD_0JD0

1

C203

3.3uF

GND_AUD

1

R126
22K

1uFC213

BUZ1
DET801H_NL

1

0R96

1

0R97

1

1uFC212

1

1 2

FERR

FB9

FB/120

1uFC205

JD_1
JD_2

GND_AUD

3

1

1

C197

C198

100nF

22uF

GND_AUD

VREFOUT

1

1uFC204

1

1

C338
100nF

AC97_SYNC12

AC97_DATA_IN12

AC97_DATA_OUT12

AC97_BITCLK12

24

LINE-IN-R

23

LINE-IN-L

22

MIC2

21

MIC1

20

CD-R

19

CD-GND

18

CD-L

17

JD1

16

JD2

15

AUX-R

14

AUX-L

13

PHONE

1

C337
100nF

AC97_PCBEEP

VCC3

1

1

C216
22uF

DGND DGND

PCI_RST#9,11,12,15,17,19,20,24,25

C217
100nF

3

VCC_AUD

1nFC196

1

1nFC199

1

1

C200
1uF

2526272829303132333435

VREF

AVSS1

AVDD1

GND_AUD

AFILT1

AFILT2

VREFOUT

VREFOUT2

VRDA/VRAD

FRONT-MIC2/VRDA

SURR-OUT -L/HP-OUT-L

SURR-OUT -L/HP-OUT-R

REALTEK

ALC655

DVSS1

SDATA-OUT

BIT-CLK

DVSS2

SDATA-IN

DVDD2

SYNC

RESET#

PC-BEEP

4

5

6

7

8

9

10

11

12

DGND DGND

1

C218
22pF

DGND

CLK_14_CODEC13

DESIGN NOTE: Use

14.318MHz external
clock

FRONT-MIC1

FRONT-OUT-L

CENTER-OUT

XTLSEL/ID1#

SPDIFI/EAPD

XTL-IN

XTL-OUT

2

3

36

MONO-O

FRONT-OUT-R

AVDD2

NC

AVSS2

LFE-OUT

JD0/GPIO0

SPDIFO

DVDD1

1

ALC655

2

U9

37
38
39
40
41
42
43
44
45
46
47
48

2

1

R100
22K

DGND

Ground

1 2

1 2

1

R101
22K

GND_AUD

FERR

FB12 FB/120

FERR

FB13 FB/120

1

0R196

GND_AUD

GND_AUD

JD_0

DGND

Left Channel

1

1uFC206

1

1uFC209

Right Channel

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Schematic

Document Number Rev
Size

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

C210
100pF

1

1

FRONT_OUT_L

FRONT_OUT_R

1

C211
100pF

GND_AUD

16 26

of

5

CLK_LPC_SIO_EXT13

D D

DESIGN NOTE: The 8 bit ADC has a
conversion rate of 8Hz. Use of the ADC
feature is limited to applications that can
accept this frequency.

C C

DESIGN NOTE: The 8 bit ADC has a 16mV
LSB, with a 0V to 4.096V input range. If
negative voltage is to be measured use
VREF in a divider to produce a positive
range. A seperate low impedance ground
plane should be used to achieve accurat e
measurements.

VCC3

B B

R209 10K

SIO_GPIO10

WD_ACTIVE

A A

R28
10K

C153

1uF

VCC5

DGND

1

1

R211 0

R212 0_NL

SIO_GPIO62

SIO_GPIO10/WD_ACTIVE

VCC5SB

2
1

6

5

U24

D
CLK

CL#

NC7SZ74

SIO_CLK_4813

PCI_RST#9,11,12,15,16,19,20,24,25

LDRQ#12

SERIRQ12,20

LFRAME#12

LAD012
LAD112
LAD212
LAD312

SIO_GPIO45
SIO_GPIO44

PME#11,15,19,25

SIO_GPIO43
SIO_GPIO42
SIO_GPIO53

SIO_BOARDTEMP
TDP

SIO_ADC_VREF
SIO_ADC7
SIO_ADC6
SIO_ADC5
SIO_ADC4
SIO_ADC3
SIO_ADC2
SIO_ADC1
SIO_ADC0

S_FLASH_DIN
S_FLASH_CLK
SIO_GPIO21
SIO_GPIO20
SIO_GPIO17
S_FLASH_DOUT
S_FLASH_CE#
SIO_GPIO14

RS485_EN222
RS485_EN122

VCC

Q

Q#

GNDPR#

SIO_GPIO13

SIO_GPIO62
SIO_GPIO50

SIO_GPIO41
SIO_GPIO40

SIO_GPIO10/WD_ACTIVE

OT_ALARM11

MOT0#22

DSA#22

WDATA#22

DIR#22

STEP#22

HDSEL#22

WGATE#22

RDATA#22

TRK0#22

INDEX#22

WP#22

DSKCHG#22

VCC5SB

8

WD_ACTIVE

5
3

47

DGND

47

PCICLK

49

CLKIN

37

LRESET#

38

LDRQ#

39

SERIRQ

40

LFRAME#

41

LAD0

42

LAD1

43

LAD2

44

LAD3

71

SUSB#/GP45

72

PWRON#/GP44

73

PME#/GP54

75

PANSWH#/GP43

76

PSON#/GP42

77

SUSC#/GP53

87

TMPIN3/SO1

88

TMPIN2

89

TMPIN1

90

VREF

91

VIN7/PCIRSTIN#

92

VIN6

93

VIN5

94

VIN4

95

VIN3/ATXPG

96

VIN2

97

VIN1

98

VIN0

24

JSAB2/GP23/SI

25

JSAB1/GP22/SCK

26

JSACY/GP21

27

JSACX/GP20

28

MIDI_OUT/GP17

29

MIDI_IN/GP16/SO2

30

RESETCON#/CIRTX/GP15/CE_N

31

PCIRST1#/SCRRST/GP14

32

PWROK1/SCRPFET#/GP13

33

PCIRST2#/SCRIO/GP12

34

PCIRST3#/SCRCLK/GP11

45

KRST#/GP62

46

GA20

48

PCIRST5#/GP50

78

PWROK2/GP41

79

3VSBSW#/GP40

84

PCIRST4#/SCRPSNT#/GP10

85

RSMRST#/CIRRX/GP55

68

COPEN#

51

DENSEL#

52

MTRA#

53

ETS_DAT/MTRB#

54

DRVA#

55

EST_CLK/DRVB#

56

WDATA#

57

DIR#

58

STEP#

59

HDSEL#

60

WGATE#

61

RDATA#

62

TRK0#

63

INDEX#

64

WPT#

65

DSKCHG#

IT8712F

SIO_GPIO62

U11

4

VCC5

DGND

VCC3

415

3550

99

67

VCC

VCCGNDD

VCCGNDD

VCCH

FAN_TAC4/JSBCY/GP25
FAN_TAC5/JSBCX/GP24

FAN_CTL4/JSBB2/GP27
FAN_CTL5/JSBB1/GP26

GNDD

GNDD

74

117

SIO_AGND

D16 MMBD4148

WATCHDOG OUT

4

VCC3SB

69

36

VBAT

VIDVCC

SOUT1/JP3

DSR1#

RTS1#/JP2

DTR1#/JP1

CTS1#

DCD1#

SIN2/GP63

SOUT2/JP6

DSR2#/GP64

RTS2/JP5

DTR2#/JP4
CTS2#/GP65
DCD2#/GP67

RI2#/GP67

IRRX/GP46

IRTX/GP47

VID0/GP30
VID1/GP31
VID2/GP32
VID3/GP33
VID4/GP34
VID5/GP35

FAN_TAC1
FAN_TAC2/GP52
FAN_TAC3/GP37

FAN_CTL1

FAN_CTL2/GP51
FAN_CTL3/GP36

MCLK/GP56

MDAT/GP57

KCLK/GP60

KDAT/GP61

GNDA

128 pin QFP

86

AC

SYS_RST# 9,11,25

SIN1

RI1#

SLCT

BUSY

ACK#

SLIN#

INIT#

ERR#

AFD#
STB#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

3

12V

125
124
123
122
121
120
118
119

6
5
3
2
1
128
126
127

70
66

100
101

PE

102
103
104
105
106
107
108

PD0

109

PD1

110

PD2

111

PD3

112

PD4

113

PD5

114

PD6

115

PD7

116
19

18
17
16
14
13

7
9
11
22
23
8
10
12
20
21

83
82
81
80

RI1#

RI2#

SIO_GPIO46
SIO_GPIO47

SIO_GPIO30
SIO_GPIO31
SIO_GPIO32
SIO_GPIO33
SIO_GPIO34
SIO_GPIO35

FAN_TAC
SIO_GPIO52
SIO_GPIO37
SIO_GPIO25
SIO_GPIO24

FAN_CNTL

SIO_PWM2

SIO_PWM3

SIO_PWM4

SIO_PWM5

RXD1 22
TXD1 22
DSR1# 22

RTS1# 22
DTR1# 22

CTS1# 22

DCD1# 22

RXD2 22
TXD2 22
DSR2# 22

RTS2# 22
DTR2# 22

CTS2# 22

DCD2# 22

MSCLK 23
MSDAT 23
KBCLK 23
KBDAT 23

SLCT 23
PE 23
BUSY 23
ACK# 23
SLIN# 23

PRNINIT# 23

ERR# 23
AFD# 23
STB# 23

PD[0:7] 23

TDP9

TDN9

3

J27

VCC5

1
3

PFL-1x3

FAN_CNTL

BSS138/SOT

SIO_ADC_VREF

SIO_BOARDTEMP

SIO_ADC_VREF

R195 30K

1 2

BLM18PG600SN1

DGND SIO_AGND

R190

Fan Control

2

1

R194
470

Q5

DGND DGND

SIO_PWM2
SIO_PWM3
SIO_PWM4
SIO_PWM5
SIO_ADC0
SIO_ADC1
SIO_ADC2
SIO_ADC3
SIO_ADC4
SIO_ADC5
SIO_ADC6
SIO_ADC7
SIO_ADC_VREF

VCC3

1

C336

1.5nF
Q11

MMBT3904/SOT

SIO_AGND

1

220pFC219

FB16

R125 30K

1

1

C221

C220

1nF

1nF

0

Q6
SI2307DS

1

C335
1uF

PFL-2x20-2M0-SMD-S

DGND SIO_AGND DGND

TDP

SIO_AGND

2

J11

FAN_TAC

3
2
1

AMP-640456-3

DGND

VCC5

1

S1
S2
S3
S4
S5
S6

2
4
6
8
10

RI1#

RI2#

DTR1#
RTS1#
TXD1
DTR2#
RTS2#
TXD

D15
MMBD4148

A C

VCC5VCC5

2

R193

10K

FAN_TAC

J12

1
3
5
7

9
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

SIO STRAPING

2

1

VCC3

R110 10K

1

1

1
1
1
1
1
1
1

S_FLASH_DIN
S_FLASH_DOUT
S_FLASH_CE#
S_FLASH_CLK

DGND

VCC5

10KR192

10KR191

1KR128
10KR113

10K_NLR114

10K_NLR115
10K_NLR116
10K_NLR117
10K_NLR118

DGND

R111 10K

R112 10K_NL

VCC3SB

VCC3

SIO_GPIO10
SIO_GPIO13
SIO_GPIO14
SIO_GPIO17
SIO_GPIO20
SIO_GPIO21
SIO_GPIO24

SIO_GPIO25
SIO_GPIO30
SIO_GPIO31
SIO_GPIO32
SIO_GPIO33
SIO_GPIO34
SIO_GPIO35
SIO_GPIO37

DGND DGND

DRB

JP-1x2_NL

J18

1

2

DESIGN NOTE: Explanation of straps on SIO
S1 - SPI Flash - 0=enable, 1=disable, Default= 0
S2 - SPI Flash Data out - 0=SD1, 1=SD2, De fau lt=1
S3 - See chip ID Byte 2, Not used, Defau lt=1
S4 - Not used, Default=1
S5 - Fan Control EC index - 0=00h, 1=40h, Default=1
S6 - Not used, Default=1

U10

5

SI

2

SO

1

CE#

6

CLK

3

WP#

7

HLD#

GND

SST25LF080A

VCC5

J13

1
3
5
7

9
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

PFL-2x20-2M0-SMD-S

VCC5

2
4
6
8
10

DESIGN NOTE: Install DRB jumper
when booting from Disaster Recovery
Board. Install the DRB into J8, LPC
Header.

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Schematic

Document Number Rev
Size

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

VCC3

8

Vcc

SPI FLASH

4

DGND

SIO_GPIO40
SIO_GPIO41
SIO_GPIO42
SIO_GPIO43
SIO_GPIO44
SIO_GPIO45
SIO_GPIO46
SIO_GPIO47
SIO_GPIO50

SIO_GPIO52
SIO_GPIO53

CS5536_GPIO25 11
CS5536_GPIO9 11
CS5536_GPIO8 11
CS5536_GPIO6 11

17 26

of

5

4

3

2

1

DESIGN NOTE:
Reg. SGCR5 bit [15,9] =[1,0]
LED3 = Act

12

LED2 = Link

FB1000
MLB-201209-0120P-N2

1

C1000
100nF_NL

1

FB21

MLB-201209-0120P-N2

1 2

DGND

C230
220pF

LAN_CHASSIS

VCC3

USB_PWR_EN112

USB_OC#12

SHD
SHD
SHD
SHD
SHD
SHD
SHD
SHD

VCC3V_LAN

DGND

26
25
24
23
22
21
20
19

LAN_CHASSIS

TXP115
TXM115

RXP115
RXM115

D D

L4

CMF-3216-0090A-N2

USB0+12

USB0-12

USB1+12

C C

USB1-12

1 2

4 3

L5

CMF-3216-0090A-N2

1 2

4 3

1

R119

49.9,1%

1

R120

49.9,1%

DGND

1

C224
100nF

1

SS2

1

R122

49.9,1%

1

SS1

1

1

C225
100nF

DGND

1

SS4

R121

49.9,1%

VCC3

VCC_USB0

VCC_USB1

1

SS3

R1001 220

R1002 220

P1LED215

P1LED315

J14

10

+TX

9

TCT

11

-TX

12

+RX

14

RCT

13

-RX

16

+LED1

15

-LED1

18

+LED2

17

-LED2

1

VCC1

3

+DATA1

2

-DATA1

4

GND1

5

VCC2

7

+DATA2

6

-DATA2

8

GND2

CON-COMBO-USB2-ETH1

DESIGN NOTE: Place
ESD protection
components as close to
the USB/Ethernet
connector as possible.

DGND

1

FB19

HI1206N101R-00

1

FB20

HI1206N101R-00

DGND

USB_PWR_EN212

DESIGN NOTE: When
uDOC is used USB2 is
not available.

SHD
SHD
SHD
SHD
SHD
SHD
SHD
SHD

VCC3V_LAN

DGND

26
25
24
23
22
21
20
19

LAN_CHASSIS

12

FB1001
MLB-201209-0120P-N2

1

C1002
100nF_NL

DESIGN NOTE: Do not
violate USB 2.0 routing
requirements when
routing USB2.

USB2-12
USB2+12

M-Systems uDOC Connector

DESIGN NOTE: Jumper
pins 3 & 4, 5 & 6 when
uDOC is not used.

VCC5

DGND

TXP215
TXM215

RXP215

USB2_CON+

USB2_CON-

USB3+12

USB3-12

RXM215

L6

CMF-3216-0090A-N2

1 2

4 3

L7

CMF-3216-0090A-N2

1 2

4 3

1

R131

49.9,1%

1

R132

49.9,1%

1

C237
100nF

1

SS6

1

R133

49.9,1%

1

SS5

DGNDDGND

1

R134

49.9,1%

1

C238
100nF

1

SS8

VCC3

VCC_USB2

VCC_USB3

1

SS7

R1003 220

R1004 220

P2LED215

P2LED315

B B

A A

J15

10

+TX

9

TCT

11

-TX

12

+RX

14

RCT

13

-RX

16

+LED1

15

-LED1

18

+LED2

17

-LED2

1

VCC1

3

+DATA1

2

-DATA1

4

GND1

5

VCC2

7

+DATA2

6

-DATA2

8

GND2

CON-COMBO-USB2-ETH1

DESIGN NOTE: Pin 9

1

FB24

HI1206N101R-00

5

1

FB25

HI1206N101R-00

DGNDDGND

4

3

on header should be
cut off.

1

R123
10K

VCC3

1

R129
10K

1

R124
10K

J16

1

VCC5

3

IIO

5
7

GND

9

KEY

VCC5

VCC5

USB­USB+

uDOC

NC

NC
NC

2

DGND

DGND

O

1

C223
100nF

7
4

3
1

2

1

C231
100nF

7
4

3
1

2

2
4
6
8
10

FB18

U12

IN
ENB

FLGB
ENA

FLGA

LM3526H

U13

IN
ENB

FLGB
ENA

FLGA

LM3526H

USB2_CON­USB2_CON+

OUTB
OUTA

GND

OUTB
OUTA

GND

5
8

6

5
8

6

HI1206N101R-00

1

DGND

FB23

HI1206N101R-00

1

DGND

DGND

DGND

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Schematic

Document Number Rev
Size

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

C226
100uF

1

C233
100uF

VCC_USB1

1

1

C227
470pF

VCC_USB3

1

1

C234
470pF

FB17

HI1206N101R-00

FB22

HI1206N101R-00

18 26

1

1

C228
100uF

1

C235
100uF

VCC_USB0

VCC_USB2

of

1

C229
470pF

1

C236
470pF

5

4

3

2

1

DESIGN NOTE: Route PCI CLOCK trace 1.5

VCC3VCC5

VCC3

inches shorter than other PCI clocks. Length
of PCI clock on MiniPCI cards will typically
be 1.5 inches. Confirm with card

D D

C C

B B

A A

manufacturer.

PCI_AD[31:0]9,11,15,20,24

5

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_INTA#9,11,24

CLK_EXT19

REQ#_MPCI9 GNT#_MPCI 9

PCI_C/BE3#9,11,15,20,24

PCI_C/BE2#9,11,15,20,24
PCI_IRDY#9,11,15,20,24

PCI_C/BE1#9,11,15,20,24

4

PCI_AD31
PCI_AD29

PCI_AD27
PCI_AD25

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_SERR#
PCI_PERR#

PCI_AD14
PCI_AD12

PCI_AD10
PCI_AD8

PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1

J17

1 2

TIP RING

3 4

RD+ TD+

5 6

RD- TD-

7 8

TERMINATION TERMINATION

9 10

TERMINATION TERMINATION

11 12

LED1_GRNP LED2_YELP

13 14

LED1_GRNN LED2_YELN

15 16

CHSGND RESERVED

17 18

INTB# 5V

19 20

3.3V INTA#

21 22

RESERVED RESERVED

23 24

GND 3.3VAUX

25 26

CLK RESET#

27 28

GND 3.3V

29 30

REQ# GNT#

31 32

3.3V GND

33 34

AD31 PME#

35 36

AD29 RESERVED

37 38

GND AD30

39 40

AD27 3.3V

41 42

AD25 AD28

43 44

RESERVED AD26

45 46

C/BE3# AD24

47 48

AD23 IDSEL

49 50

GND GND

51 52

AD21 AD22

53 54

AD19 AD20

55 56

GND PAR

57 58

AD17 AD18

59 60

C/BE2# AD16

61 62

IRDY# GND

63 64

3.3V FRAME#

65 66

CLKRUN# TRDY#

67 68

SERR# STOP#

69 70

GND 3.3V

71 72

PERR# DEVSEL#

73 74

C/BE1# GND

75 76

AD14 AD15

77 78

GND AD13

79 80

AD12 AD11

81 82

AD10 GND

83 84

GND AD9

85 86

AD8 C/BE0#

87 88

AD7 3.3V

89 90

3.3V AD6

91 92

AD5 AD4

93 94

RESERVED AD2

95 96

AD3 AD0

97 98

5V RESERVED_WIP

101 102

GND GND

103 104

AC_SYNC M66EN

105 106

AC_SDATA_IN AC_SDATA_OUT

107 108

AC_BIT_CLK AC_CODEC_ID0#

109 110

AC_CODEC_ID1# AC_RESET#

111 112

MOD_AUDIO_MON RESERVED

113 114

AUDIO_GND GND

115 116

SYS_AUDIO_OUT SYS_AUDIO_IN

117 118

SYS_AUDIO_OUT_GND SYS_AUDIO_IN_GND

119 120

AUDIO_GND AUDIO_GND

121 122

RESERVED MPCIACT#

123 124

VCC5VA 3.3VAUX

PCITYPEIII

RESERVED_WIPAD1

10099

DESIGN NOTE: Consult MiniPCI card
manufacturer for any special design or
layout considerations of MiniPCI slot to
accomidate a particular MiniPCI card.

3

DGNDDGND

VCC3SB

PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24

R135 100

PCI_AD22
PCI_AD20

PCI_AD18
PCI_AD16

PCI_AD15
PCI_AD13
PCI_AD11

PCI_AD9

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

PCI_INTB# 11,15,24

PCI_RST# 9,11,12,15,16,17,20,24,25

PME# 11,15,17,25

PCI_AD23

PCI_PAR 9,11,15,20,24

PCI_FRAME# 9,11,15,20,24
PCI_TRDY# 9,11,15,20,24
PCI_STOP# 9,11,15,20,24

PCI_DEVSEL# 9,11,15,20,24

PCI_C/BE0# 9,11,15,20,24

VCC3SB

Title
Document Number Rev
Size

2

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

B

1

C239
22uF

PCI_PERR#
PCI_SERR#

*AMD CONFIDENTIAL*

AMD GEODE™ LX EPIC RDK Reference Sc hematic

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

C244
22uF

1

C240
100nF

1

C241
100nF

1

C245
100nF

1

C242
100nF

1

C246
100nF

R136 10K
R137 10K

1

1

C243
100nF

DGND

VCC5

1

C247
100nF

DGND

VCC3

19 26

of

National Semiconductor Confidential

5

PCI_AD22

R139 33

ISA_IRQ[7:3]24

ISA_IRQ[12:9]24

ISA_IRQ[15:14]24

5

PCI_AD[31:0]9,11,15,19,24

VCC3

1

R208
10K_NL

PCI_C/BE0#9,11,15,19,24
PCI_C/BE1#9,11,15,19,24
PCI_C/BE2#9,11,15,19,24
PCI_C/BE3#9,11,15,19,24

REQ_EXT0#9
GNT_EXT0#9

PCI_DEVSEL#9,11,15,19,24
PCI_FRAME#9,11,15,19,24

PCI_IRDY#9,11,15,19,24
PCI_TRDY#9,11,15,19,24
PCI_STOP#9,11,15,19,24

PCI_PAR9,11,15,19,24
PCI_RST#9,11,12,15,16,17,19,24,25
CLK_EXT09

SERIRQ12,17

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

ISA_IRQ3
ISA_IRQ4
ISA_IRQ5
ISA_IRQ6
ISA_IRQ7
ISA_IRQ9
ISA_IRQ10
ISA_IRQ11
ISA_IRQ12
ISA_IRQ14
ISA_IRQ15

M1

G1
G2
G3

M8

M7

M6

L1
K3
K2
K1
J3
J2

J1
H2
H1

F1
F2
F3
A1
C3
B3
A2
A3
C4
C5
B4
A5
C6
B6
A6
C7
B7
A7
A8
B5

H3
E1
B2
A4

C8
B8

D3
C2
B1
E4
D2
E2

A9
C9

P9
N8

P8
N7
P7

P6
N6

P5

L2
K4

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
IDSEL

CBE0#
CBE1#
CBE2#
CBE3#

IREQ#
IGNT#

DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCIRST
PCICLK

SERIRQ

IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15

SDATA
SCLK

D D

DESIGN NOTE: Install in order
to disable the bridge. This is a
temporary measure.

C C

B B

A A

4

VCC3 VCC5

D7D8G4D9D10

F4

VCC3

VCC3

VCC3

VCC3

LOCK#

SERR#

PERR#

CLKRUN#

C1

E3

D1B9A10

BRDG_LOCK#

BRDG_SERR#

BRDG_CLKRUN#

BRDG_PERR#

4

VCC5

B10

BRDG_PPREQ#

J11L5L6D4

VCC5

VCC5

PPREQ#

PPGNT#

A11

BRDG_PPGNT#

M2L3L4M3N2P2P1

VCC5

VCC5GND

DACK7#

U14

IT8888G

GND

GND

GND

GND

D5D6G11H4H11J4L7L8L9

DACK6#

GND

DACK5#

GND

DACK3#

GND

DACK2#

GND

DACK1#

GND

DGND

DACK0#

MEMR#

MEMW#

SMEMR#

SMEMW#

SBHE#

MEMCS16#

IOCS16#

IOCHRDY

IOCHK#

MASTER#

REFRESH#

RSTDRV

NOWS#

GND

L10

SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8

SD9
SD10
SD11
SD12
SD13
SD14
SD15

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19

LA20
LA21
LA22
LA23

IOR#

IOW#

BALE

AEN

BCLK

DRQ7
DRQ6
DRQ5
DRQ3
DRQ2
DRQ1
DRQ0

TC

DACK7# 24
DACK6# 24
DACK5# 24
DACK3# 24
DACK2# 24
DACK1# 24
DACK0# 24

F14
F13
F12
E14
E13
D14
F11
D13
A14
C12
B12
A13
A12
C11
C10
B11

L12
L13
M14
L14
K12
K13
K14
J12
J13
J14
H12
H13
H14
G14
G13
G12
E12
B14
C14
E11

D12
B13
C13
D11

P14
N14
L11
M11
K11
M13
M12
M9
N10
P12
P13
N12
P11
N11
P10
N1
N13
N9
M10

M4
N3
N4
P3
P4
M5
N5

3

ISA_SD0
ISA_SD1
ISA_SD2
ISA_SD3
ISA_SD4
ISA_SD5
ISA_SD6
ISA_SD7
ISA_SD8
ISA_SD9
ISA_SD10
ISA_SD11
ISA_SD12
ISA_SD13
ISA_SD14
ISA_SD15

ISA_SA0
ISA_SA1
ISA_SA2
ISA_SA3
ISA_SA4
ISA_SA5
ISA_SA6
ISA_SA7
ISA_SA8
ISA_SA9
ISA_SA10
ISA_SA11
ISA_SA12
ISA_SA13
ISA_SA14
ISA_SA15
ISA_SA16
ISA_SA17
ISA_SA18
ISA_SA19

ISA_LA20
ISA_LA21
ISA_LA22
ISA_LA23

ISA_MEMR#
ISA_MEMW#
ISA_SMEMR#
ISA_SMEMW#
ISA_SBHE#
ISA_IOR#
ISA_IOW#
ISA_MEMCS16#
ISA_IOCS16#
ISA_IOCHRDY
ISA_BALE
ISA_AEN
ISA_IOCHCK#
ISA_MASTER#
ISA_REFRESH#
ISA_RSTDRV
ISA_NOWS#
ISA_TC
ISA_BCLK

DRQ7
DRQ6
DRQ5
DRQ3
DRQ2
DRQ1
DRQ0

3

ISA_SD[15:0] 24

ISA_SA[19:0] 24

ISA_AEN

ISA_BALE
ISA_TC

ISA_LA[23:20] 24

ISA_MEMR# 24
ISA_MEMW# 24
ISA_SMEMR# 24
ISA_SMEMW# 24
ISA_SBHE# 24
ISA_IOR# 24
ISA_IOW# 24
ISA_MEMCS16# 24
ISA_IOCS16# 24
ISA_IOCHRDY 24
ISA_BALE 24
ISA_AEN 24
ISA_IOCHCK# 24
ISA_MASTER# 24
ISA_REFRESH# 24
ISA_RSTDRV 24

ISA_TC 24
ISA_BCLK 24

DRQ[7:5] 24

DRQ[3:0] 24

R138 10K
R140 10K
R141 10K

VCC3

VCC5

1

C254
22uF

1

C249
22uF

2

1

1

C256

C255

10nF

10nF

1

1

C251

C250

10nF

10nF

DESIGN NOTE: Configuration Straps
AEN - 1 = Factory Test
0 = Normal operation
BALE - 1 = Positive decode on BIOS address range
0 = BIOS address range disabled
TC - 1 = Enable SMB Boot ROM Configuration
0 = Disabe SMB Boot ROM Configuration

DGND

DRQ1

1

DRQ3

2

DRQ0

3

DRQ5

4 5

1
2

DRQ7

3
4 5

DRQ2

2

1

ISA_SA1
ISA_SA0
ISA_SA3
ISA_SA2

ISA_SA5
ISA_SA4
ISA_SA7
ISA_SA6

ISA_SA9
ISA_SA8
ISA_SA11
ISA_SA10

ISA_SA12
ISA_MEMW#
ISA_MASTER#
ISA_MEMR#

ISA_SA14
ISA_SA13
ISA_SA16
ISA_SA15

ISA_LA20
ISA_SA17
ISA_IOR#
ISA_IOW#

ISA_SA18
ISA_LA21
ISA_LA22
ISA_SA19

ISA_SMEMR#
ISA_IOCS16#
ISA_LA23
ISA_SMEMW#

ISA_MEMCS16#
ISA_SBHE#
ISA_IOCHRDY
ISA_IOCHCK#

ISA_NOWS#

BRDG_SERR#
BRDG_PERR#
BRDG_LOCK#

BRDG_CLKRUN#
BRDG_PPREQ#DRQ6
BRDG_PPGNT#

RN5010K

RN5310K

R149 10K

1

C257
10nF

1

C252
10nF

8
7
6

8
7
6

DGND

1

C258
10nF

DGND

1

C253
10nF

DGND

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

RN5510K

1

8

2

7

3

6

4 5

RN5110K

1

8

2

7

3

6

4 5

RN5710K

1

8

2

7

3

6

4 5

RN5210K

1

8

2

7

3

6

4 5

RN4910K

1

8

2

7

3

6

4 5

RN4810K

1

8

2

7

3

6

4 5

RN4710K

1

8

2

7

3

6

4 5

RN4610K

1

8

2

7

3

6

4 5

RN4510K

1

8

2

7

3

6

4 5

R210 10K

RN5610K

1

8

2

7

3

6

4 5

RN5810K

1

8

2

7

3

6

4 5

20 26

of

VCC5

VCC3

5

D D

4

3

2

1

IDE_D[15:0]12

C C

VCC5VCC3

1

1

R142

R143

0_NL

0

B B

A A

5

IDE_D7
IDE_D5

IDE_D4
IDE_D3 IDE_D12

IDE_D1
IDE_D0

IDE_DRQ#12

IDE_IOW#12

IDE_IOR#12
IDE_RDY#12

IDE_ACK#12

IDE_IRQ12

IDE_CS0#12

IDE CONNECTOR

IDE_RST#12

IDE_A112

IDE_LED

JHDD1

1

RST

3

D7

5

D6

7

D5

9

D4

11

D3

13

D2

15

D1

17

D0

19

GND

21

DRQ

23

IOW

25

IOR

27

NC

29

DACK

31

IRQ

33

A1

35

A0

37

CS0

39

LED

41 42

VCC VCC

43 44

GND NC

PFL-2x22-2M0-SMD-S

4

IOCS16

GND

D10
D11
D12
D13
D14
D15

GND
GND
GND

ALE

GND

CS1

GND

UDMA
YELLOW

2
4

D8

6

D9

8
10
12
14
16
18
20

NC

22
24
26
28
30
32
34

NC

36

A2

38
40

DGNDDGND

IDE_D8
IDE_D9IDE_D6
IDE_D10
IDE_D11

IDE_D13IDE_D2
IDE_D14
IDE_D15

R188 470

IDE_A2 12IDE_A012
IDE_CS1# 12

1

R144
10K_NL

1

C259
47nF_NL

DGND

IDE_CABLEID# 11

VCC5

1

12

R189
560

D11

LTST-C190YKT

IDE_LED 11

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Schematic

Document Number Rev
Size

3

2

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

21 26

of

5

VCC5

U15

1

C260

NRX1

100nF

NDSR1#
NCTS1#

NDCD1#

1

C263
100nF

1

C264
100nF

1

C284
100nF

1

C285
100nF

1

DGND

1

DGND

1

5

DGND

R187
10K

DGND

R145
1K

DGND

1

C273
100nF

R186

10K

TXD117
RTS1#17

DTR1#17

VCC5

1

1

C262

C261

100nF

100nF

NRX2
NDSR2#

NCTS2#
NDCD2#

TXD217
RTS2#17

DTR2#17

VCC5

1

1

C275

C274

100nF

100nF

R182 120
R183 120
R184 120
R185 120

1

R146
1K

DESIGN NOTE: Jumpers for RS485 termination
Install jumpers on 1-2 and 3-4 for COM1
Install jumpers on 5-6 and 7-8 for COM2

D D

RS485_EN117

C C

B B

RS485_EN217

NTX1

A A

NRX1
NTX2
NRX2

26

4

A1

5

VCC

B1

13

A2

12

B2

22

DY1

23

DZ1/DE1

19

DY2

1

C1+

2

C1-

28

C2+

27

C2-

3

VDD

15

VEE

21

LB

20

ON/OFF

8

SEL1

9

SEL2

14

LTC1334

DGND

VCC5

U16

26

4

A1

5

B1

VCC

13

A2

12

B2

22

DY1

23

DZ1/DE1

19

DY2

1

C1+

2

C1-

28

C2+

27

C2-

3

VDD

15

VEE

21

LB

20

ON/OFF

8

SEL1

9

SEL2

14

LTC1334

DGND

J26

1
3
5
7

PFL-2x4-2M0-SMD-S

2
4
6
8

RA1
RB1

RA2
RB2

GND

RA1
RB1

RA2
RB2

GND

Y1
Z1

Y2
Z2DZ2/DE2

Y1
Z1

Y2
Z2DZ2/DE2

1

24
25

17
16

6
7

11
1018

24
25

17
16

6
7

11
1018

R147
1K

VCC5

4

NDTR1#
NRTS11#

NDTR2#
NRTS22#

1

R148
1K

4

RXD1 17
DSR1# 17

CTS1# 17
DCD1# 17

NTX1

NRTS1#

RXD2 17
DSR2# 17

CTS2# 17
DCD2# 17

NTX2

NRTS2#

NRTS1#
NDSR1#
NRTS2#
NDSR2#

3

C339

1

220pF

FB35

BLM18PG600SN1

1

DGND C_CHASSIS

VCC5

R154 4.7K
R153 4.7K
R152 4.7K
R151 4.7K
R150 4.7K

INDEX#17
DSA#17
DSKCHG#17

MOT0#17

DIR#17
STEP#17
WDATA#17

WGATE#17
TRK0#17
WP#17
RDATA#17

HDSEL#17

3

COM1

NRTS11#
NDTR1#
NCTS1#
NTX1
NRTS1#
NRX1
NDSR1#
NDCD1#

1

1

C266

C265

220pF

220pF

DGND

COM2

NRTS22#
NDTR2#
NCTS2#
NTX2
NRTS2#
NRX2
NDSR2#
NDCD2#

1

1

C276

C277

220pF

220pF

DGND

FDD CNT

VCC5

DGND

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

HRS-FH10-26

J20

1

C267
220pF

1

C278
220pF

2

1

C268
220pF

1

C279
220pF

1

C269
220pF

1

C280
220pF

1

C270
220pF

1

C281
220pF

1

C271
220pF

1

C282
220pF

1

C272
220pF

DGND C_CHASSIS

1

C283
220pF

1

P1B

CON-COMBO-DB9-15-25-TRIPLEPORT
B5
B9
B4
B8
B3
B7
B2
B6
B1

MTG3

MTG4

VCC5

J19

1
3
5
7
9

PFL-5x2-2M54-SMD-S

DGND

2
4
6
8
10

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Schematic

Document Number Rev
Size

2

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

22 26

of

5

D D

SUPER I/O
KEYBOARD/MOUSE

C C

B B

VCC5SB

KBDAT17

KBCLK17

MSDAT17

MSCLK17

VCCKBVCC5

R156 0
R157 0_NL

FB27 BLM18PG600SN1

1

FB28 BLM18PG600SN1

1

FB29 BLM18PG600SN1

1

FB30 BLM18PG600SN1

1

F2 1.10A, 33V

1

R27

4.7K

2

R26

4.7K

2

FB26

HI1206N101R-00

1

R24

R25

4.7K

4.7K

2

2

DGND

1

C286
22uF

4

1

C287
100nF

PD[0:7]17

P2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

CON-MINI-6P/2-C

violet

green

DESIGN NOTE:
Place these three series resistor
components close to the Super IO.

PD[0:7]

13

SHLD

14

SHLD

15

SHLD

16

SHLD

17

SHLD

KB_CHASSIS

3

VCC5

D12

1 2

MBRS340T3

123

SLCT17
PE17

BUSY17

ACK#17

RN65

PD7

4 5

PD6

3
2
1

33

RN64

4 5
3
2
1

33

RN63

4 5
3
2
1

33

6
7
8

6
7
8

6
7
8

C288180pF

C319180pF

PD5
PD4

SLIN#17

PRNINIT#17

ERR#17

AFD#17

PD3
PD2

PD1
PD0

STB#17

678

C320180pF

C321180pF

RN59

4.7K

4 5

2

123

C323180pF

C324180pF

678

C325180pF

RN60

4.7K

4 5

C326180pF

123

C327180pF

C331180pF

678

C328180pF

C332180pF

RN61

4.7K

4 5

123

C329180pF

C330180pF

678

C333180pF

RN62

4.7K

4 5

C334180pF

2

C322180pF

DGND

R155

4.7K

1

DGND

A13
A25
A12
A24
A11
A23
A10
A22

A21
A20
A19
A18
A17
A16
A15
A14

P_CHASSIS

MTG1

MTG2

A9
A8
A7
A6
A5
A4
A3
A2
A1

CON-COMBO-DB9-15-25-TRIPLEPORT

P1A

C290

1

DGND

1

220pF

FB32

BLM18PG600SN1

3

KB_CHASSIS P_CHASSISDGND

1

1

C294

C293

220pF

220pF

A A

5

1

C292
220pF

1

C291
220pF

DGND

4

1

FB31

BLM18PG600SN1

1

C289
220pF

2

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

B

40744

Date: Sheet

Wednesday, April 11, 2007

1

D

23 26

of

5

ISA_IOCHCK#20

ISA_IOCHRDY20

ISA_AEN20

ISA_SA[19:0]

ISA_MEMR#20
ISA_MEMW#20

ISA_SD[15:0]

ISA_SD[15:0]

ISA_SBHE#20

ISA_IRQ3
ISA_IRQ4
ISA_IRQ5
ISA_IRQ6
ISA_IRQ7
ISA_IRQ9
ISA_IRQ10
ISA_IRQ11
ISA_IRQ12
ISA_IRQ14
ISA_IRQ15

5

ISA_SD7
ISA_SD6
ISA_SD5
ISA_SD4
ISA_SD3
ISA_SD2
ISA_SD1
ISA_SD0

ISA_SA19
ISA_SA18
ISA_SA17
ISA_SA16
ISA_SA15
ISA_SA14
ISA_SA13
ISA_SA12
ISA_SA11
ISA_SA10
ISA_SA9
ISA_SA8
ISA_SA7
ISA_SA6
ISA_SA5
ISA_SA4
ISA_SA3
ISA_SA2
ISA_SA1
ISA_SA0

DGND

ISA_LA23
ISA_LA22
ISA_LA21
ISA_LA20
ISA_SA19
ISA_SA18
ISA_SA17

ISA_SD8
ISA_SD9
ISA_SD10
ISA_SD11
ISA_SD12
ISA_SD13
ISA_SD14
ISA_SD15

DRQ[7:5]20

DRQ[3:0]20

ISA_SD[15:0]20

D D

C C

ISA_SA[19:0]20

ISA_LA[23:20]20

B B

ISA_IRQ[7:3]20

A A

ISA_IRQ[12:9]20

ISA_IRQ[15:14]20

C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32

A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

C0
C1
C2
C3
C4
C5
C6
C7
C8
C9

J21A

reserved
IOCHCHK#
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
GND

PC-104

J21B

GND
SBHE#
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MEMR#
MEMW#
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
KEY
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

PC-104

DRQ7
DRQ6
DRQ5
DRQ3
DRQ2
DRQ1
DRQ0

reserved

GND

RESETDRV

VCC5

IRQ9

VCC5NEG

DRQ2

V12NEG

ENDXFR#

V12POS

KEY

SMEMW#

SMEMR#

IOW#

IOR#

DACK3#

DRQ3

DACK1#

DRQ1

REFRESH#

SYSCLK

IRQ7
IRQ6
IRQ5
IRQ4
IRQ3

DACK2#

BALE
VCC5

OSC
GND
GND

GND

MEMCS16#

IOCS16#

IRQ10
IRQ11
IRQ12
IRQ15
IRQ14

DACK0#

DRQ0

DACK5#

DRQ5

DACK6#

DRQ6

DACK7#

DRQ7

VCC5

MASTER#

GND

GND
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

TC

B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32

VCC5

4

-12V

DGND

DACK7#20
DACK6#20
DACK5#20
DACK3#20
DACK2#20
DACK1#20
DACK0#20

4

12V

ISA_IRQ9

DACK3#

DRQ3

DACK1#

DRQ1

ISA_IRQ7
ISA_IRQ6
ISA_IRQ5
ISA_IRQ4
ISA_IRQ3
DACK2#

ISA_IRQ10
ISA_IRQ11
ISA_IRQ12
ISA_IRQ15
ISA_IRQ14

DACK0#

DRQ0

DACK5#

DRQ5

DACK6#

DRQ6

DACK7#

DRQ7

ISA_RSTDRV 20

DRQ2

ISA_SMEMW# 20
ISA_SMEMR# 20
ISA_IOW# 20
ISA_IOR# 20

ISA_REFRESH# 20
ISA_BCLK 20

ISA_TC 20
ISA_BALE 20

CLK_14_ISA 13

ISA_MEMCS16# 20
ISA_IOCS16# 20

ISA_MASTER# 20

DACK7#
DACK6#
DACK5#
DACK3#
DACK2#
DACK1#
DACK0#

PC_CLKFB

BLM18PG600SN1

PC_REQ0#
PC_REQ1#
PC_REQ2#

GNT0#9

PCI_STOP#
PCI_RST#

PC_CLK13

PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18

PCI104_LOCK#
PCI104_PERR#
PCI104_SERR#

PC_REQ2#
PC_REQ1#
PC_REQ0#

PCI_AD[31:0]9,11,15,19,20

3

DESIGN NOTE: PC_CLK3 trace must
be ~17mm less than PC_CLK2.
PC_CLK2 trace must be ~17mm less
than PC_CLK1. PC_CLK1 trace must
be ~17mm less than PC_CLK0.

VCC3

FB33

1 2

R159 10K

3

1

C295
10uF

R158 0

VCC3 VCC3_EXT2

U17

21

28

96

13

NC

VCC

VCCVSS

5
8

11

1
2

26
27

14 15

AVCC

REQ1

GNT1

REQ2

GNT2

REQ3

GNT3

S_REQS_GNT

FRAME

CLKFB

STOP

CLK1
CLK2

RESET

CLK3

CLKIN

CLK4

NC NC

VSS

VSS

172425

DGND GND_EXT2

RN6633

1
2
3
4 5

RN6710K

1
2
3
4 5

R207 10K
R180 10K
R181 10K

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10

PCI_AD12
PCI_AD13
PCI_AD14

1

C296
100nF

GND_EXT2DGND

NC

AVSS

ITE IT8209R

8
7
6

VCC3

8
7
6

VCC3_EXT2

1

C297
100nF

16
7

10
12
34

23
22
20
19
18

PC_IDSEL0
PC_IDSEL1
PC_IDSEL2
PC_IDSEL3

PC_GNT0#
PC_GNT1#
PC_GNT2#

REQ0# 9

PC_CLKFBPCI_FRAME#
PC_CLK0
PC_CLK1
PC_CLK2
PC_CLK3

PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27PCI_AD11
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31PCI_AD15

-12V

2

VCC3_EXT VCC3_EXT

PCI_AD5

PCI_C/BE0#9,11,15,19,20

PCI_AD11
PCI_AD14

PCI104_SERR#

PCI_STOP#9,11,15,19,20

PCI_FRAME#9,11,15,19,20

PCI_AD18
PCI_AD21

PC_IDSEL0
PCI_AD24

PCI_AD29
PC_REQ0#
PC_GNT1#

12V

PC_CLK2

VCC5

PCI_AD1
PCI_AD4

PCI_AD8
PCI_AD10

PCI_AD15

PCI104_LOCK#

PCI_IRDY#9,11,15,19,20

PCI_AD17
PCI_AD22

PC_IDSEL1 PC_IDSEL2
PCI_AD25

PCI_AD28
PC_REQ1#
PC_GNT2#
PC_CLK3

PCI_INTB#11,15,19

GNT#_PC39

DGND DGND

A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30

C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30

J22A

A1

GND

A2

VI/O

A3

AD05

A4

C/BE0#

A5

GND

A6

AD11

A7

AD14

A8

VCC3

A9

SERR#
GND
STOP#
VCC3
FRAME#
GND
AD18
AD21
VCC3
IDSEL0
AD24
GND
AD29
VCC5
REQ0#
GND
GNT1#
VCC5
CLK2
GND
V12POS
V12NEG

PCI-104

J22B

C1

VCC5

C2

AD01

C3

AD04

C4

GND

C5

AD08

C6

AD10

C7

GND

C8

AD15

C9

reserved
VCC3
LOCK#
GND
IRDY#
VCC3
AD17
GND
AD22
IDSEL1
VI/O
AD25
AD28
GND
REQ1#
VCC5
GNT2#
GND
CLK3
VCC5
INTB#
GNT3#

PCI-104

reserved

AD02

GND
AD07
AD09

VI/O

AD13

C/BE1#

GND

PERR#

VCC3

TRDY#

GND
AD16

VCC3

AD20
AD23

GND

C/BE3#

AD26

VCC5

AD30

GND

REQ2#

VI/O

CLK0

VCC5

INTD#

INTA#

REQ3#

AD00

VCC5

AD03
AD06

GND

M66EN

AD12

VCC3

PAR

reserved

GND

DEVSEL#

VCC3

C/BE2#

GND
AD19

VCC3
IDSEL2
IDSEL3

GND
AD27
AD31

VI/O

GNT0#

GND
CLK1

GND
RST#

INTC#

GND

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30

D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

2

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

PCI_AD2
PCI_AD7

PCI_AD9
PCI_AD13

PCI_C/BE1# 9,11,15,19,20

PCI104_PERR#

PCI_TRDY# 9,11,15,19,20

PCI_AD16
PCI_AD20

PCI_AD23

PCI_C/BE3# 9,11,15,19,20

PCI_AD26
PCI_AD30
PC_REQ2#
PC_CLK0

PCI_INTD# 11
PCI_INTA# 9,11,19
REQ#_PC3 9

VCC5

PCI_AD0
PCI_AD3

PCI_AD6

PCI_AD12

PCI_PAR 9,11,15,19,20

PCI_DEVSEL# 9,11,15,19,20
PCI_C/BE2# 9,11,15,19,20

PCI_AD19

PC_IDSEL3
PCI_AD27

PCI_AD31
PC_GNT0#
PC_CLK1

PCI_RST# 9,11,12,15,16,17,19,20,25
PCI_INTC# 11

24 26

1

of

5

VCC5

WORK_AUX11

D D

WORK_AUX

R160 10K

1

C303
1uF

1

C304
100nF

1

C300
47uF

R161 75K

1

C305
1nF

DESIGN NOTE: For TFT
support, VCORE must power
up before VCC3. With this
design, a simple RC is on the
enable to the VCC3 regulator
delays VCC3 relative to

WORK_AUX

1

C309
100nF

1

C307
47uF

R1009

10K

R166 27K

1

C310

1.5nF

VCORE.

C C

VCC5SB

WORKING11

1

1

C313

C315

47uF

100nF

B B

VCC3_EXT

12V VCC5 -12V

J25

PS_ON#11

A A

1

PS_ON

2

GND

3

GND

4

+12V

5

+3.3V

MINI-ATX POWER

1106
27
38
49
5

+5VSB

+5V
+5V

-12V

GND

6
7
8
9
10

VCC5SB

DGNDDGND

R171 24K

1

C316

2.2nF

10 Pin ATX Type Power Connector

5

DGND

U18

1

VIN

6

EN

AOZ1012

U20

1

VIN

6

EN

AOZ1012

U21

1

VIN

6

EN

AOZ1012

4

L8 4.7uH

8

LX

7

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

9
45
23

8
7
9

45
23

8
7
9

45
23

DGND

DGNDDGND

DGNDDGND

1

L9 4.7uH

1

L10 4.7uH

1

1

1

1

1

1

1

1

1

1

VCORESB

VCORE

VCCMEM

VCC3SB

VCC3

VCC5SB

VCC5

VBAT

MVREF

1

C301
NL

1

C308
NL

1

C314
NL

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

LX

THRM

FBCOMP

PGNDAGND

GND

10

LX
LX

THRM

FBCOMP

PGNDAGND

GND

10

LX
LX

THRM

FBCOMP

PGNDAGND

GND

10

4

3

3.30V@3A

1

R162
30K

1

R176

1.1K
R164 10K

DGND

1.25V@3A

1

R167

5.6K

1

R177
22

R168 10K

DGND

2.6V@2A

1

R172
22K

1

R178
470

R173 10K

DGND

1

1

1

1

1

1

1

1

1

DGND

3

1

C298
100uF

1

C306
100uF

1

C312
100uF

VCC3

VCOREVCC5

DESIGN NOTE: OPN's for the LX
processor have a specified Vcore
voltage of 1.25V or 1.20V. If using
an OPN that has a Vcore of 1.2V
then R3 should be 10K ohms.

VCCMEM

TP19

TP20

TP21

TP22

TP23

TP24

1

1

1

1

1

1

WORKING

WORK_AUX

SYS_RST#

2

POWER
GREEN

VCC5

1

DESIGN NOTE:

R170

LED is optional.

560

12

D14
LTST-C190GKT

DGND

RST_STB# 11

PCI_RST# 9,11,12,15,16,17,19,20,24

PME# 11,15,17,19

2

1

VCC5SB

1

C302
1uF

DGND

EXT_PWRBTN#11

1 2
5

PWRBTN#11

EXT_RST#11

SYS_RST#9,11,17

U19

LM317L

VIN VOUT
NC

ADJ

4

1

C317
1uF

DGND

1

C318
1uF

DGND

VOUT
VOUT
VOUTVIN

VCC3SB

1

R169
470

LM4041AIM3-1.2

2 1

DGND

3
6
78

D13

3

R174 22

R175 22

1

R179
270

1

R163
1K

1

R165
2K

DGND

PWRBTN

1 3

PTS453SL38

RESET

1 3

PTS453SL38

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

3.30V

VCC3SB

1

C299
22uF

DGND

1.225V

VCORESB

1

C311
1uF

DGND

SW1

42

DGND

SW2

42

DGND

25 26

of

5

J2

VCC_LCD

1

1

C31

C32

D D

C C

100nF

22uF

DGND

LDEMOD_HSIP_VSYNC8

TFTCLK8
HSYNC_C8
VSYNC_C8

TFT_R28

TFT_R38

TFT_R48

TFT_R58

TFT_R68

TFT_R78

TFT_G28

TFT_G38

TFT_G48

TFT_G58

TFT_G68

TFT_G78

TFT_B28

TFT_B38

TFT_B48

TFT_B58

TFT_B68

TFT_B78

TFT Connector LVDS Connector

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

HIROSE-DF14-30PIN-1M25

DGND

4

VCC_LCD

TXOUT3-8
TXOUT3+8

TXCLKOUT-8
TXCLKOUT+8

TXOUT2-8
TXOUT2+8

TXOUT1-8
TXOUT1+8

TXOUT0-8

TXOUT0+8
CRT_SCL12,14
CRT_SDA12,14

J28

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

HIROSE-DF14-20PIN-1M25

DGND

3

2

1

12VVCC5 VCC5 VCC3

B B

J29

2

1

4

3

6

5

PFL-2x3-2M0-SMD-S

DESIGN NOTE: J29: SET
VOLTAGES FOR LCD AND
BACKLIGHT:

DEFAULT LCD: JUMPER
PIN2 TO PIN4 = VCC

DEFAULT BACKLIGHT:
JUMPER PIN1 TO PIN3 = 12V

ROUTE WIDTH=20mil ROUTE WIDTH=20mil

1

R201 10K

HSIP_HSYNC8

1

ROUTE WIDTH=20mil ROUTE WIDTH=20mil

OPTIONAL: ON-BOARD SWITCHING OF VBKL

1

R206 10K

DISPEN8

A A

5

1

4

Q7

SI2305DS

R200
47K

Q8
BC846B

DGND DGND DGND

Q9

SI2307DS

R205
47K

Q10
BC846B

DGND DGND DGND

1

C343
100nF

1

C345
100nF

VCC_LCD

1

C344
10uF

1

C346
10uF

R204 0

1

VCC5 12V

DISPEN8

ROUTE WIDTH=20mil

DGND

J30

1
2
3
4
5
6
7
8

HIROSE-DF13-8PIN-1M25

*AMD CONFIDENTIAL*

Advanced Micro Devices

1351 South Sunset St.

Longmont CO 80501

Title

AMD GEODE™ LX EPIC RDK Reference Sc hematic

Document Number Rev
Size

3

2

B

40744 D

Date: Sheet

Wednesday, April 11, 2007

1

26 26

of