Acer Geode LX EPIC RDK RevD Schematic
5
4
3
2
1
AMD Geode™ LX EPIC RDK Reference
D D
NOTES:
1) UNLESS OTHERWISE SPECIFIED RESISTORS HAVE 5% TOLERANCE.
2) UNLESS OTHERWISE SPECIFIED CAPACITORS HAVE 20% TOLERANCE.
C C
B B
IMPORTANT NOTICE:
1. THIS DOCUMENT MAY NOT REFLECT THE MOST RECENT CHANGES IN BOARD DEVELOPMENT
AND DEBUG. ANY DEVELOPER INTENDING TO USE THIS SCHEMATIC AS A REFERNCE SHOULD
CONTACT THEIR LOCAL FIELD APPLICATIONS ENGINEER, REGIONAL SALES OFFICE , O R
PROGRAM MANAGER FOR SCHEMATIC UPDATES, DESIGN RECOM MENDA TION S AND PCB L AYOU T
GUIDELINES. AMD ALSO RECOMMENDS A DESIGN REVIEW OF BOTH THE SCHEMATIC DIAGRAM
AND PCB LAYOUT BEFORE CONSIDERING PRODUC TIO N.
2. AMD RESERVES THE RIGHT TO CHANGE DESIGNS OR SPECIFICATIONS WITHOU T NO TICE .
CUSTOMERS ARE ADVISED TO OBTAIN THE LATEST VERSIONS OF PRODUCT SPECIFICATIONS,
WHICH SHOULD BE CONSIDERED IN EVALUATING A PRODUCT'S APPROPRIATENESS FOR A
PARTICULAR USE.
3. AMD MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, FOR MERCHANTABILITY OR FITNESS
FOR A PARTICULAR APPLICATION. IN NO EVENT SHALL AMD BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES AS A RESULT OF THE PE RFOR MAN CE,
A A
OR FAILURE TO PEFORM, OF ANY AMD PRODUCT OR DOCUMENTATION.
© 2007 ADVANCED MICRO DEVICES, INC. ALL RIGHTS RESERVED. AMD, THE AMD ARROW LOGO,
AMD GEODE, AND COMBINATIONS THEREOF ARE TRADEMARKS OF ADVANCED MICRO DEVICES,
INC. OTHER NAMES USED IN THIS PUBLICATION ARE FOR IDENTIFICATION PURPOSES ONLY
AND MAY BE TRADEMARKS OF THEIR RESPECTIVE COMPANIES.
5
4
Schematic
Page Index
------- ------------------------
1
2
3
4
5
6
7
8
9
10
11
12
13
IMPORTANT NOTES ABOUT
THIS SCHEMATIC
DESIGN NOTE: Example
text for the design note to
show the note inside the
colored box.
DESIGN NOTE: Example
text for the design note to
show the note inside the
colored box.
DESIGN NOTE: Example
text for the design note to
show the note inside the
colored box.
COVER PAGE
REVISION HISTORY
BLOCK DIAGRAM
POWER ON & RESET SEQUENCE
PCI & JTAG BLOCK DIAGRAM
LX PROCESSOR DDR MEMORY
DDR SODIMM CONNECTOR
LX PROCESSOR VGA
LX PROCESSOR PCI / SYSTEM
LX PROCESSOR POWER
CS5536 PCI / SYSTEM / PM / FWH
CS5536 IDE / USB / AC97 / LPC
CS5536 POWER & CLOCK GENERATOR
3
1) DESIGN NOTES in
grey are information
notes.
2) DESIGN NOTES in
yellow are notes of
caution.
3) DESIGN NOTES in
red are critical, and
must be understood and
followed.
Page Index
------- ------------------------
14
15
16
17
18
19
20
21
22
23
24
25
26 TFT & LVDS CONNECTORS
VGA CONNECTOR
ETHERNET - 10 / 100 MICREL KSZ8842
AUDIO CODEC REALTEK ALC655
SUPER IO ITE IT8712F & SPI BOOT FLASH
ETHERNET CONN / USB CONN & PWR / uDOC
MINI PCI
PCI TO ISA BRIDGE ITE IT8888G
IDE CONNECTOR
UART & FLOPPY CONNECTORS
PARALLEL PORT, KEYBOARD, & MOUSE
PC104 CONNECTORS
POWER SUPPLIES
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
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Title
AMD GEODE™ LX EPIC RDK Reference Sc hematic
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Date: Sheet
Wednesday, April 11, 2007
126
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REVISION HISTORY:
REV DATE NOTES
------- ------------------ ---------------------------------------------------------------------------------------
A Initial Release
07-09-2006
12-04-2006
C 01-19-2007
D Page 13 - Added design note regarding USB VCORE supply.
04-10-2007
C C
*
Page 8 - Changed LX symbol - DRG B 6 p i n f r om Y32 to AH8B
*
Page 10 - Connected C102-C108 to Ground
*
Page 13 - Connected C133-C137 and C149-C152 to Ground
*
*
B B
A A
5
4
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2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
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Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number Rev
Size
B
40744 D
Date: Sheet
Wednesday, April 11, 2007
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MONITOR
D D
LVDS
HD/CD
C C
X2
HOST
X1
PRIMARY IDE ATA-100
CRT
TFT
USB2.0
AMD Geode™
LX Processor
PCI BUS (33MHz)
AMD Geode™
CS5536
MEMORY BUS
PCI TO ISA
BRIDGE
10 / 100
ETHERNET
2 PORT
SODIMM200
DDR
FULL ISA
Companion
uDOC FLASH
STORAGE
CLIENT
X1
B B
14.318 MHz
Crystal
Clock
Synthesizer
(MK1491-09F)
PCI(33 MHz)
66 MHz
48 MHz
REFCLK
Device
SIO
SPI
AC97
AUDIO CODEC
5.1 SUPPORT
BIOS
FLASH
LEGACY
PARALLEL
SERIAL
KB/MS
VCORE(1.25V)
VMEM (2.6V)
A A
VCC5
VCC5SB
5
DC/DC
VCC3 (3.3V)
VCORESB (1.225V)
VCC3SB (3.3V)
4
BASEBOARD ONLY
3
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
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Date: Sheet
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5VSB
VMEM @ 2A Max
DC/DC
AOZ1012
D D
WORKING
EN
AMD
Geode™ LX
5V
DC/DC
AOZ1012
WORK AUX
5V
EN
DC/DC
AOZ1012
C C
WORK AUX
5VSB
EN
VCC3 @ 2A Max
VCORE @ 2A Max
VCC3SB
DESIGN NOTE: This design uses
LVD to generate system reset.
Since LVD only monitors Vcore ,
the designer must guarantee that
Vio and other required voltages
are valid at or before Vcore. If this
cannot be guaranteed, then
RESET_WORK# must be used to
hold system in reset until Vio and
Vcore and any other requir ed
voltages are valid.
Processor
AMD
Geode™
CS5536
LVD_EN#
PCIRST#
WORKING
PWRBTN#
LINEAR
LM317
B B
VCC3SB
470
VCORESB
LM4041
5VSB
1.225VSB
Power On and Reset Sequence - Cold start
3.3VSB
PWRBTN# WORKING
5V
VCC3
VCORE
VMEM
LVD
SYS_RST#
SYSTEM POWER
VCC=+5.0V
VCC3=+3.30V - BASEBOARD
VCC3_EXT=+3.30V - PC104 SLOTS
AMD Geode™ LX
Processor
VCORE=+1.25V
VCCMEM=+2.60V
MVREF=+1.3V
VIO=+3.30V
AMD Geode™
CS5536
VCORE=+1.25V
VCORESB=+1.225V
VIO=+3.30V
MEMORY
VMEM=+2.60V
MVREF=+1.3V
PCIRST#
VCCMEM MVREF
A A
10K
5
10K
4
3
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
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AMD GEODE™ LX EPIC RDK Reference Schematic
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Date: Sheet
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1
PCI MASTER SETTING
REQ2#/GNT#2
D D
AMD
REQ1#/GNT#1
Expander
Geode™ LX
REQ_EXT0#/GNT_EXT0#
REQ_EXT1#/GNT_EXT1#
REQ_EXT2#/GNT_EXT2#
Processor
PC_REQ0#/PC_GNT0#
REQ0#/GNT#0
Expander
PC_REQ1#/PC_GNT1#
PC_REQ2#/PC_GNT2#
AMD Geode™ CS5536
PCI to ISA Bridge
Mini PCI
Ethernet Controller
PC104 Slot 3
PC104 Slot 0
PC104 Slot 1
PC104 Slot 2
Jumpers to select
2 of the 3 devices
C C
B B
PCI CLOCK SETTING
CLOCK
GENERATOR
SEL66_33#
MK1491-09
CLK_EXT
PC_CLK
CLK_CPU
CLK_IOC
Expander
Expander
CLK_EXT0
CLK_EXT1
CLK_EXT2
CLK_EXT3
PC_CLK0
PC_CLK1
PC_CLK2
PC_CLK3
AMD Geode™ LX Processor
AMD Geode™ CS5536
PCI to ISA Bridge
Mini PCI
Ethernet Controller
Not Used
PC104 Slot 0
PC104 Slot 1
PC104 Slot 2
PC104 Slot 3
JTAG DAISY CHAIN MODE WITH AMD GEODE™
CS5536 COMPANION DEVICE
TCK
TMS
TDI
TDO
TDEBUG_OUT
TDEBUG_IN
FS2 HEADER
TCK
TMS
TDI
TDO
TDEBUG_OUT
TDEBUG_IN
AMD GEODE™ LX PROCESSOR
TCK
TMS
TDI
TDO
TDEBUG_OUT
TDEBUG_IN
AMD GEODE™ CS5536
FunctionSEL66_33#
A A
1
PCI 66 MHz
PCI 33 MHz0
5
4
3
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
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Title
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Date: Sheet
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DESIGN NOTE: See LX
layout guidelines for
latest recommendations
on memory routing.
D D
C C
DESIGN NOTE:
Use SDCLK
pairs that are
most convient
for clean routing.
B B
A A
SDCLK0#7
SDCLK2#7
SDCLK4#7
QM0
MD
M1
MDQM1
MDQM2
MDQM3
MDQM4
MDQM5
MDQM6
MDQM7
MCS0#
MCS1#
MCKE0
MWE#
MCAS#
MRAS#
SDCLK07
SDCLK27
SDCLK47
MDQS0
MDQS1
MDQS2
MDQS3
MDQS4
MDQS5
MDQS6
MDQS7
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
DQM0
G2
DQM1
A6 D26
DQM2 BA0
A19
DQM4
C24
DQM5
H29
DQM6
N30
DQM7
B28
CS0#
F28
CS1#
F29
CS2#
D30
CS3#
E4
CKE0
F4
CKE1
C27
WE0#
A28
WE1#
E28
CAS0#
E29
CAS1#
C26
RAS0#
D27
RAS1#
M4
SDCLK0P
J4
SDCLK1P
M28
SDCLK2P
J28
SDCLK3P
D23
SDCLK4P
D20
SDCLK5P
L4
SDCLK0N
H4
SDCLK1N
L28
SDCLK2N
H28
SDCLK3N
D24
SDCLK4N
D21
SDCLK5N
M2
DQS0
H3
DQS1
C6
DQS2
A10
DQS3
C19
DQS4
B23
DQS5
J29
DQS6
N31
DQS7
C16
MA0
C17
MA1
C15
MA2
C13
MA3
D13
MA4
D11
MA5
D12
MA6
D8
MA7
D9
MA8
D6
MA9
D19
MA10
D5
MA11
C5
MA12
F30
MA13
U1A
AMD GEODE™
LX PROCESSOR
5
BA1DQM3
TLA0
TLA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
MVREF
4
DESIGN NOTE: BA0,BA1
must be trace length
matched to within 50 mils.
MBA0
MBA1
C20B10
TLA0
B15
TLA1
B13
MD0
P2
MD1
N2
MD2
M3
MD3
K2
MD4
P3
MD5
N1
MD6
L3
MD7
K1
MD8
J2
MD9
J1
MD10
F3
MD11
E3
MD12
J3
MD13
G1
MD14
F2
MD15
F1
MD16
D2
MD17
B4
MD18
B6
MD19
C8
MD20
D1
MD21
A4
MD22
A7
MD23
B7
MD24
B9
MD25
C10
MD26
A12
MD27
B12
MD28
A9
MD29
C9
MD30
C11
MD31
A13
MD32
A15
MD33
B17
MD34
B19
MD35
B22
MD36
B16
MD37
A17
MD38
B20
MD39
A20
MD40
A22
MD41
A23
MD42
A25
MD43
A26
MD44
C22
MD45
C23
MD46
B25
MD47
B26
MD48
D31
MD49
F31
MD50
K30
MD51
K31
MD52
G30
MD53
G31
MD54
J31
MD55
J30
MD56
M31
MD57
M30
MD58
R30
MD59
R31
MD60
L29
MD61
M29
MD62
P30
MD63
R29
MVREF
P1
1
C2
100nF
DGND
4
RN1
33
RN2
33
RN3
33
RN4
33
RN5
33
RN6
33
RN7
33
RN8
33
RN9
33
RN10
33
RN11
33
RN12
33
RN13
33
RN15
33
RN17
33
RN19
33
MD5
MD1
MD4
MD0
MD6
MD2
MDQM0
MDQS0
MD12
MD8
MD7
MD3
MDQM1
MDQS1
MD13
MD9
MD15
MD11
MD14
MD10
MD21
MD17
MD20
MD16
MD22
MD18
MDQM2
MDQS2
MD28
MD24
MD23
MD19
MDQM3
MDQS3
MD29
MD25
MD31
MD27
MD30
MD26
TLA0
TLA1
MD37
MD33
MD36
MD32
MD38
MD34
MDQM4
MDQS4
MD44
MD40
MD39
MD35
MDQM5
MDQS5
MD45
MD41
MD47
MD43
MD46
MD42
3
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
RMD5 7
RMD1 7
RMD4 7
RMD0 7
RMD6 7
RMD2 7
RMDQM0 7
RMDQS0 7
RMD12 7
RMD8 7
RMD7 7
RMD3 7
RMDQM1 7
RMDQS1 7
RMD13 7
RMD9 7
RMD15 7
RMD11 7
RMD14 7
RMD10 7
RMD21 7
RMD17 7
RMD20 7
RMD16 7
RMD22 7
RMD18 7
RMDQM2 7
RMDQS2 7
RMD28 7
RMD24 7
RMD23 7
RMD19 7
RMDQM3 7
RMDQS3 7
RMD29 7
RMD25 7
RMD31 7
RMD27 7
RMD30 7
RMD26 7
RTLA0 7
RTLA1 7
RMD37 7
RMD33 7
RMD36 7
RMD32 7
RMD38 7
RMD34 7
RMDQM4 7
RMDQS4 7
RMD44 7
RMD40 7
RMD39 7
RMD35 7
RMDQM5 7
RMDQS5 7
RMD45 7
RMD41 7
RMD47 7
RMD43 7
RMD46 7
RMD42 7
3
DESIGN NOTE:
Swap series
resistors on the
DQS lines in
order minimize
the number of
vias.
DESIGN
NOTE: Swap
series
resistors on
the address
lines in order
minimize the
number of
vias.
DESIGN NOTE:
Do not swap
series resistors
on the DQS,
DQM or Data
lines with the
Address or
control lines.
DESIGN
NOTE: Swap
series
resistors on
the data lines
in order
minimize the
number of
vias.
DESIGN
NOTE: Place
data bus
series
resistors as
close to the
memory
devices as
possible.
RN21
33
RN23
33
RN24
33
RN26
33
RN27
33
RN14
22
RN16
22
RN18
22
RN20
22
RN22
22
RN25
22
MD53
MD49
MD52
MD48
MD54
MD50
MDQM6
MDQS6
MD60
MD56
MD55
MD51
MDQM7
MDQS7
MD61
MD57
MD63
MD59
MD62
MD58
MA11
MA12
MCKE0
MA6
MA7
MA8
MA9
MA2
MA3
MA4
MA5
MBA1
MA10
MA0
MA1
MCAS#
MWE#
MRAS#
MB
A0
MCS1#
MCS0#
MA13
2
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
1
8
2
7
3
6
45
RMD53 7
RMD49 7
RMD52 7
RMD48 7
RMD54 7
RMD50 7
RMDQM6 7
RMDQS6 7
RMD60 7
RMD56 7
RMD55 7
RMD51 7
RMDQM7 7
RMDQS7 7
RMD61 7
RMD57 7
RMD63 7
RMD59 7
RMD62 7
RMD58 7
RMA11 7
RMA12 7
RMCKE0 7
RMA6 7
RMA7 7
RMA8 7
RMA9 7
RMA2 7
RMA3 7
RMA4 7
RMA5 7
RMBA1 7
RMA10 7
RMA0 7
RMA1 7
RMCAS# 7
RMWE# 7
RMRAS# 7
RMBA0 7
RMCS1# 7
RMCS0# 7
RMA13 7
DESIGN NOTE: Place DQS and
DQM series resistors as close
to the SODIMM connector as
possible.
DESIGN NOTE: This schematic shows a
non-parallel terminated DDR solution.
There may be restrictions as to the total
number of DRAMS and the number of
banks supported on the SODIMM. See LX
layout guidelines for current restrictions.
DESIGN NOTE: Place address
and control series resistors as
close to the processor as
possible.
1
VCCMEM
1
R1
10K
1
R2
10K
DGND DGND
Vout = 1.30
MVREF
1
C1
100nF
*AMD CONFIDENTIAL*
Advanced Micro Devices
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Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number Rev
Size
2
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40744 D
Date: Sheet
Wednesday, April 11, 2007
1
626
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SDCLK06
SDCLK0#6
SDCLK26
SDCLK2#6
RMCKE06
D D
C C
B B
A A
RMRAS#6
RMCAS#6
RMWE#6
RMCS0#6
RMCS1#6
RMDQS06
RMDQS16
RMDQS26
RMDQS36
RMDQS46
RMDQS56
RMDQS66
RMDQS76
RMA06
RMA16
RMA26
RMA36
RMA46
RMA56
RMA66
RMA76
RMA86
RMA96
RMA106
RMA116
RMA126
RMDQM06
RMDQM16
RMDQM26
RMDQM36
RMDQM46
RMDQM56
RMDQM66
RMDQM76
RMBA06
RMBA16
SMB_SDA12
SMB_SCL12
RTLA16
RTLA06
SDCLK46
SDCLK4#6
VCCMEM
5
RMA136
1
R3 10K
DGND
4
J1A
35
CK0
37
CK0#
160
CK1
158
CK1#
96
CKE0
95
CKE1
118
RAS#
120
CAS#
119
WE#
121
S0#
122
S1#
11
DQS0
25
DQS1
47
DQS2
61
DQS3
133
DQS4
147
DQS5
169
DQS6
183
DQS7
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10/AP
100
A11
99
A12
12
DM0
26
DM1
48
DM2
62
DM3
134
DM4
148
DM5
170
DM6
184
DM7
117
BA0
116
BA1
194
SA0
196
SA1
198
SA2
193
SDA
195
SDL
85
RFU
86
RFU/RESET
71
CB0
72
CB4
73
CB1
74
CB5
77
DQS8
78
DM8
79
CB2
80
CB6
83
CB3
84
CB7
89
CK2
91
CK2
97
RFU
98
RFU
123
RFU/A13
124
RFU
199
VddID
200
RFU
SODIMM
DDR-SODIMM-200P-RVS
4
DQ00
DQ01
DQ02
DQ03
DQ04
DQ05
DQ06
DQ07
DQ08
DQ09
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
3
5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190
RMD0 6
RMD1 6
RMD2 6
RMD3 6
RMD4 6
RMD5 6
RMD6 6
RMD7 6
RMD8 6
RMD9 6
RMD10 6
RMD11 6
RMD12 6
RMD13 6
RMD14 6
RMD15 6
RMD16 6
RMD17 6
RMD18 6
RMD19 6
RMD20 6
RMD21 6
RMD22 6
RMD23 6
RMD24 6
RMD25 6
RMD26 6
RMD27 6
RMD28 6
RMD29 6
RMD30 6
RMD31 6
RMD32 6
RMD33 6
RMD34 6
RMD35 6
RMD36 6
RMD37 6
RMD38 6
RMD39 6
RMD40 6
RMD41 6
RMD42 6
RMD43 6
RMD44 6
RMD45 6
RMD46 6
RMD47 6
RMD48 6
RMD49 6
RMD50 6
RMD51 6
RMD52 6
RMD53 6
RMD54 6
RMD55 6
RMD56 6
RMD57 6
RMD58 6
RMD59 6
RMD60 6
RMD61 6
RMD62 6
RMD63 6
MVREF
VCCMEM
J1B
1
VREF
2
VREF
9
VDD
10
VDD
21
VDD
22
VDD
33
VDD
34
VDD
36
VDD
45
VDD
46
VDD
57
VDD
58
VDD
69
VDD
70
VDD
81
VDD
82
VDD
92
VDD
93
VDD
94
VDD
113
VDD
114
VDD
131
VDD
132
VDD
143
VDD
144
VDD
155
VDD
156
VDD
157
VDD
167
VDD
168
VDD
179
VDD
180
VDD
191
VDD
192
VDD
197
VDDSPD
SODIMM
DDR-SODIMM-200P-RVS
2
VCCMEM
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
C3
22uF
1
C10
22uF
1
C17
1nF
1
C24
1nF
1
1
1
1
1
1
1
C5
C4
100pF
22uF
1
1
C11
C12
22uF
100pF
1
1
C18
C19
1nF
1nF
1
1
C26
C25
1nF
1nF
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
DGND
DESIGN NOTE: This schematic
shows a non-parallel terminated
DDR solution. There may be
restrictions as to the total number
of DRAMS and the number of banks
supported on the SODIMM. See LX
layout guidelines for current
restrictions.
C6
100pF
1
C13
100pF
1
C20
10nF
1
C27
10nF
C7
100pF
1
C14
100pF
1
C21
10nF
1
C28
10nF
C8
100pF
1
C15
100pF
1
C22
10nF
1
C29
10nF
C9
1nF
1
C16
1nF
1
C23
10nF
1
C30
10nF
DGND
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Sc hematic
Document Number Rev
Size
3
2
B
40744 D
Date: Sheet
Wednesday, April 11, 2007
1
726
of
5
DESIGN NOTE: 8-bit Data Streaming
VCC3VCC5
HSIP_CLK
HSIP_D0
HSIP_D1
D D
HSIP_D2
HSIP_D3
HSIP_D4
HSIP_D5
HSIP_D6
HSIP_D7
HSIP_D8
HSIP_D9
HSIP_D10
HSIP_D11
HSIP_D12
HSIP_D13
HSIP_D14
HSIP_D15
LDEMOD_HSIP_VSYNC
PFL-2x20-2M0-SMD-S
Mode is the simplest data input mode,
but is limited to 8-bits.
J3
1
3
5
7
9
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
2
4
6
8
10
DGND
HSIP_SYNC
HSIP_HSYNC
High Speed
Input Port
C C
B B
A A
DESIGN NOTE: When using 16 data capture
mode (Mode 4 - BT.601), the TFT interface
cannot be used due to pin sharing conflicts.
DESIGN NOTE: There are two conventions
for connecting 24 bit panels. One is backward
compatible with 18 bit panels. The connections
defined here are backwards compatible.
TFT_R2
TFT_R3
TFT_R4
TFT_R5
TFT_R6
TFT_R1
TFT_R7
TFT_G2
TFT_G3
TFT_G4
TFT_G0
TFT_G1
TFT_G5
TFT_G6
TFT_G7
TFT_B2
TFT_B0
TFT_B1
TFT_B3
TFT_B4
TFT_B5
TFT_B6
TFT_B7
HSYNC_C
VSYNC_C
LDEMOD_HSIP_VSYNC
TFT_R0
TFTCLK
R_F_CLK
DISPEN
51
52
54
55
56
2
3
4
6
7
8
10
11
12
14
15
16
18
19
20
22
23
24
25
27
28
30
50
31
17
32
U2
IN00
IN01
IN02
IN03
IN04
IN05
IN06
IN07
IN08
IN09
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
IN19
IN20
IN21
IN22
IN23
IN24
IN25
IN26
IN27
CLKIN
R_FB
PD
DS90C385
CLKO-
CLKO+
OUT0-
OUT0+
OUT1-
OUT1+
OUT2-
OUT2+
OUT3-
OUT3+
TSSOP56 Package
24-bit LVDS Transmitter
5
VCC
VCC
VCC
LVCC
PVCC
LGND
LGND
LGND
PGND
PGND
GND
GND
GND
GND
GND
1
9
26
44
34
40
39
48
47
46
45
42
41
38
37
36
43
49
33
35
5
13
21
29
53
VCC3
LVDS_AVCC3
TXCLKOUT- 26
TXCLKOUT+ 26
TXOUT0- 26
TXOUT0+ 26
TXOUT1- 26
TXOUT1+ 26
TXOUT2- 26
TXOUT2+ 26
TXOUT3- 26
TXOUT3+ 26
LVDS_PGND
DGND
LVDS_PVCC3
LDVS_AGND
R_F_CLK
4
TFT_R4
TFT_R426
TFT_R3
TFT_R326
TFT_R2
TFT_R226
TFT_R0
TFT_B6
TFT_B626
TFT_B7
TFT_B726
TFT_R6
TFT_R626
TFT_R5
TFT_R526
TFT_B0
TFT_B3
TFT_B326
TFT_B4
TFT_B426
TFT_B5
TFT_B526
TFT_B2
TFT_B226
TFT_G7
TFT_G726
TFT_B1
TFT_G5
TFT_G526
TFT_G1
TFT_G4
TFT_G426
TFT_G3
TFT_G326
TFT_G6
TFT_G626
TFT_G2
TFT_G226
TFT_R7
TFT_R726
TFT_G0
TFT_R1
DESIGN NOTE: The LSB's for
each color (R0,R1,G0,G1,B0,B1)
are not used in by 18-bit panels.
1
R10 0_NL
4
RN69 22
8
7
6
RN70 22
8
7
6
RN71 22
8
7
6
RN72 22
8
7
6
RN73 22
8
7
6
RN74 22
8
7
6
DESIGN NOTE: For 18-bit panels use OUT0,
OUT1, and OUT2. For 24-bit panels use
OUT0, OUT1, OUT2, and OUT3.
VCC3
3
U26C
HSIP_CLK
HSIP_SYNC
TFTCLK
T_R4
1
T_R3
2
T_R2
3
T_R
45
T_B6
1
T_B7
2
T_R6
3
T_R5
45
T_B0
1
T_B3
2
T_B4
3
T_B5
45
T_B2
1
T_G7
2
T_B1
3
T_G5
45
T_G1
1
T_G4
2
T_G3
3
T_G6
45
T_G2
1
T_R7
2
T_G0
3
T_R1
45
TFTCLK26
0
HSIP_D8
HSIP_D9
HSIP_D10
HSIP_D11
HSIP_D12
HSIP_D13
HSIP_D14
HSIP_D15
HSIP_D0
HSIP_D1
HSIP_D2
HSIP_D3
HSIP_D4
HSIP_D5
HSIP_D6
HSIP_D7
VCC3
FB1
1 2
BLM18PG600SN1
1
R8 0
DGND LVDS_PGND
T_B0
T_B1
T_B2
T_B3
T_B4
T_B5
T_B6
T_B7
T_G0
T_G1
T_G2
T_G3
T_G4
T_G5
T_G6
T_G7
T_R0
T_R1
T_R2
T_R3
T_R4
T_R5
T_R6
T_R7
1
C36
10uF
AL12
AL14
AH11
AJ11
AK10
AL10
AJ10
AH10
AJ15
AK15
AL15
AH13
AJ13
AK13
AL13
AK12
3
VIPCLK
VIPSYNC
AE1
DOTCLK/VOPCLK
AH7
DRGB0/VOP7
AK6
DRGB1/VOP6
AL6
DRGB2/VOP5
AJ7
DRGB3/VOP4
AK7
DRGB4/VOP3
AL7
DRGB5/VOP2
AH8
DRGB6/VOP1
AJ8
DRGB7/VOP0
AJ2
DRGB8/VOP15
AK3
DRGB9/VOP14
AL3
DRGB10/VOP13
AH5
DRGB11/VOP12
AJ4
DRGB12/VOP11
AL4
DRGB13/VOP10
AK4
DRGB14/VOP9
AJ5
DRGB15/VOP8
AF2
DRGB16_VOP23
AF1
DRGB17_VOP22
AG3
DRGB18_VOP21
AG4
DRGB19_VOP20
AH1
DRGB20_VOP19
AH2
DRGB21_VOP18
AH3
DRGB22_VOP17
AJ1
DRGB23_VOP16
DRGB24/VID8
DRGB25/VID9
DRGB26/VID10
DRGB27/VID11
DRGB28/VID12
DRGB29/VID13
AL9
DRGB30/VID14
AK9
DRGB31/VID15
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
LVDS_PVCC3
1
C38
100nF
1
C39
10nF
LDEMOD/VIP_VSYNC
DISPEN/VOP_BLANK
VDDEN/VIP_HSYNC
VSYNC/VOP_VSYNC
HSYNC/VOP_HSYNC
AMD GEODE™
LX PROCESSOR
VCC3
1 2
BLM18PG600SN1
1
R9 0
DGND
FB2
RED
GREEN
BLUE
DAVDD
DAVDD
DAVDD
DAVDD
DAVSS
DAVSS
DAVSS
DAVSS
DVREF
DRSET
1
C37
10uF
2
LDEMOD_HSIP_VSYNC
AD4
AE4
AE2
AD3
AE3
W3
V2
U2
W4
V4
U1
V1
W2
Y2
U3
V3
W1
Y1
1
R6
1.2K
1
R601
10
AGND_VGA
LVDS_AVCC3
1
1
C40
C41
100nF
10nF
LDVS_AGND
2
1
DISPEN
HSIP_HSYNC
VSYNC_C
1
R30 22
HSYNC_C
1
R29 22
RED 14
GREEN 14 VSYNC 14
BLUE 14
DACVDD
1
1
C34
C33
10nF
10uF
AGND_VGA
D1
LM4041AIM3-1.2
2 1
1
R7 0
LDEMOD_HSIP_VSYNC 26
DISPEN 26
HSIP_HSYNC 26
1
1
C35
3
10nF
AGND_VGA
DGND
VSYNC_C 26
HSYNC_C 26
VCC3
53
1
VSYNC_C
VCC3
1
R4 1
R5
10K
DESIGN NOTE: AGND_VGA should be an
island with single point connection to the
full ground plane to reduce noise content.
Zero ohm resistor can be removed as
long as above condition is met.
HSYNC_C
2 4
DGND
VCC3
53
1
2 4
DGND
DGND
U22
NC7SZ125/SC70
DGND
U23
NC7SZ125/SC70
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Sc hematic
Document Number Rev
Size
B
40744 D
Date: Sheet
Wednesday, April 11, 2007
1
826
HSYNC 14
of
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