How it Works
Acer
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FERRARI 1100
User Manual [bg]
83 pgs2.76 Mb0
User Manual [ru]
81 pgs2.61 Mb0
User Manual [ru]
116 pgs3.04 Mb0
User Manual [es]
114 pgs3.56 Mb0
User Manual
112 pgs7.28 Mb0
Service Manual
180 pgs26.33 Mb0
User Manual [fr]
116 pgs3.41 Mb0
Schematics
47 pgs2.01 Mb0
Schematics FINGERPRINT TCS4BA
2 pgs175.45 Kb0
User Manual [it]
114 pgs3.58 Mb0
Schematics USB CardReader
2 pgs180.95 Kb0
User Manual [de]
124 pgs3.68 Mb0
User Manual [pt]
122 pgs3.87 Mb0
Schematic
37 pgs1.23 Mb0
User Manual [el]
83 pgs3.27 Mb0
User Manual [cz]
76 pgs2.64 Mb0
User Manual [tr]
83 pgs2.59 Mb0
User Manual [sv]
79 pgs2.4 Mb0
User Manual [ro]
81 pgs2.54 Mb0
User Manual [pl]
82 pgs2.56 Mb0
User Manual [zh]
72 pgs2.62 Mb0
User Manual [no]
78 pgs2.4 Mb0
User Manual [da]
79 pgs2.4 Mb0
User Manual [fi]
77 pgs2.39 Mb0
User Manual [hu]
81 pgs2.47 Mb0
User Manual [nl]
80 pgs2.42 Mb0

Acer Ferrari 1100 Schematics

5
4
3
2
1
PAGE3;RESERVE RN65~71 P/L 49.9ohms for ICS951464
PAGE3;CHANGE R107,R108 from 47.5 ohms TO 0ohm;Need CHECK!!
PAGE14;CHANGE LCD1;PIN27 TO TP105;RESERVE FOR LIGHT_SENSOR PAGE14;CHANGE LCD1;PIN24 TO 5V POWER RAIL FOR LED DRIVER BOARD IC ENABLE PIN(HIGH ACTIVE) PAGE14;CHANGE F1 TO 4A
PAGE14;P/U TMDS_DDC_DAT TO 3D3V_S0,ADD R471 PAGE15;CHANGE R184,R185,R188 FROM 75ohms TO 150 ohms
PAGE19;SWAP USB PAIR OF FT AND MINICARD
D D
PAGE27;CHANGE Q11 TO 84.00143.B1K
PAGE30;CHANGE C389,C390 TO 1uF,X5R PAGE30;CHANGE R450,R453 TO 14Kohms PAGE30;CHANGE R459,R463 TO 40.2ohms PAGE30;CHANGE R458,R462 TO 33ohms
PAGE31;ADD R472 AND P/H TO 3D3V_S0 FOR CAPA_INT# PAGE31;CHANGE R347 TO 4.7Kohms(E51_TxD P/L)
PAGE31
1.KBC Beep change from A_PWM0(32) to GPIO56(31)
2.Power LED change from GPIO32(65) to A_PWM0(32)
3.e-Button LED change from GPIO43(20) to A_PWM1(118)
C C
B B
LAYOUT
LAYOUT
LAYOUT
Wistron Incorporated
Wistron Incorporated
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
21F, 88, Hsin Tai Wu Rd
A A
Title
Title
Title
Change List
Change List
Change List
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A
A
A
Date: Sheet
Date: Sheet
5
4
3
Date: Sheet
Ferrari 7
Ferrari 7
Ferrari 7
2
21F, 88, Hsin Tai Wu Rd Hsichih, Taipei
Hsichih, Taipei
Hsichih, Taipei
of
of
of
147Thursday, August 02, 2007
147Thursday, August 02, 2007
147Thursday, August 02, 2007
1
5
Ferrari 7 Block Diagram
D D
DIMM1
DDR2 SODIMM
DDR II 533/667/800
4
AMD
3
2006/04/17
Ver:
2
Friday Practice (SA)
Saturday Practice (SB) Qualifying(SC) Race(-1)
1
PCB Layer Stackup
L1: Component L2: GND L3: Signal L4: VCC L5: Signal L6: Signal
DDR2 SODIMM
Power Switch
P2231NFC1
Mini Card
DIMM2
New card
802.11a/b/g/n
DDR II 533/667/800
HyperTransport
PCI-E x 1
PCI-E x 1
K8 Rev.G S1g1 Socket
16x16
OUT
IN
Project code: PCB P/N : REVISION :
SidePort
DDR2 128MB
64MB x16
AMD
C C
RJ45
B B
A A
XFORM
INT. MIC Array
Line In
MIC In
AMP
G1431
INT.SPKR
Line Out (No-SPDIF)
RJ11
5
LAN
Broadcom 5787MKMLG
25MHz
AMP G1412
MDC Card
Codec
ALC268
MODEM
HDD
CDROM
PCI-E x 1
G792
AZALIA
AZALIA
SATA
PATA
RS690T
A-Link
SB600
USB 3 Port
4
PCI-E x 4
AMD
16/17/18/19/20
USB x 3
USB
MINI USB BlueTooth
LVDS
USB
PCI BUS
24.576MHz
25MHz
32.768KHz
LPC BUS
USB
USB
CCD 0.3M
3
S-Vedio
CRT
12.1" LCD
RTL5158
TI
TSB43AB23PDT
SIO
FIR
USB
Finger print
ICS 9LPRS502 (RTM875T-605)
Touch Pad
ezDockII/II+
USB/Express Card/MediaBay/1394*2port
RJ45/RJ11/PS2*2/Serial Port/Parallel Port/CRT/TV/DVI-D/SPDIF/MIC in/Line in/Line out/AC Jack
CLK GEN.
MS/MS Pro/xD/ MMC/SD
32.768KHz
KBC
Winbond
WPC8768
INT. KB
2
14.318MHz
5 in 1
1394 CONN
SPI
BIOS
W25X80-VSS
LAYOUT
LAYOUT
LAYOUT
Title
Title
Title
Interactive Circuit Map
Interactive Circuit Map
Interactive Circuit Map
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Ferrari 7
Ferrari 7
Date: Sheet
Date: Sheet of
Date: Sheet of
Ferrari 7
L7: GND L8: Component
CPU V_CORE
ISL6264
INPUT
DCBATOUT
SYSTEM DC/DC
INPUT
DCBATOUT
SYSTEM DC/DC
INPUT
DCBATOUT 5V_S5
SYSTEM LDO
INPUT
1D8V_S3
SYSTEM LDO
INPUT
3D3V_S5 3D3V_S0 3D3V_S0
SYSTEM LDO
INPUT
DCBATOUT
Battery Charger
INPUTS
AD+ BAT+
1
OUTPUT
VCC_CORE_S0
TPS51124
OUTPUT
1D2V_S0 1D8V_S3
ISL6236
3D3V_S5
TPS51100
OUTPUT
0D9V_S3
APL5915
ISL6236
OUTPUT
5V_AUX_S5 3D3V_AUX_S5
ISL6255
OUTPUTS
DCBATOUT
Wistron Incorporated
Wistron Incorporated
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
21F, 88, Hsin Tai Wu Rd
21F, 88, Hsin Tai Wu Rd Hsichih, Taipei
Hsichih, Taipei
Hsichih, Taipei
247Thursday, August 02, 2007
247Thursday, August 02, 2007
247Thursday, August 02, 2007
38/39
OUTPUT
OUTPUT
1D2V_S5 2D5V_S0 1D5V_S0
of
47
46
48
48
46
42
SA
SA
SA
5
3D3V_S0 3D3V_CLK_VDD
R105
R105
0R3-0-U-GP
0R3-0-U-GP
1 2
D D
1- PLACE ALL SERIAL TERMINATION RESISTORS CLOSE TO U800
2- PUT DECOUPLING CAPS CLOSE TO U800 POWER PIN
C C
3D3V_S0
12
R127
R127
0R3-0-U-GP
0R3-0-U-GP
1 2
RN29
RN29
SRN10KJ-6-GP
SRN10KJ-6-GP
C259
C259
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3000mA.80ohm
3D3V_CLK_VDD
678
4 5
12
C617
C617
123
12
C618
C618
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C621
C621
3D3V_S0
12
C616
C616
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
R130
R130
1 2
2D2R3J-2-GP
2D2R3J-2-GP
SB
R350
CLK14_SIO28
NB_OSC12
R350
0R3-0-U-GP
0R3-0-U-GP
1 2
R103
R103
49D9R2F-GP
49D9R2F-GP
R106
R106
1 2
12
33R2F-3-GP
33R2F-3-GP
1 2
3D3V_S0 3D3V_CLK_VDDA
C289
C289 SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
HTREF_CLK12
SB_OSC_CLK20
SB
CPUCLK6
CPUCLK#6
NBSRC_CLK12
NBSRC_CLK#12
CLK48_USB20
B B
Check SLGO EXT CLK XSL84606 (56 Pin) or XSL84605 (64 Pin) pin to pin compatable with ICS951464
EXT CLK FREQUENCY SELECT TABLE(MHZ)
FS2
0 0 0
A A
0 0 1
0 1 0 0 1 1 1 0 0 1 0 1 1 1 1
CPUFS1
Hi-Z X
180.00
220.00
100.00
133.33
200.00
5
SRCCLK
[2:1]
100.00
100.00
100.00
100.00
100.00
100.00
HTTFS0 PCI
Hi-Z Hi-Z100.00 Reserved
36.56 73.12
66.66 33.33
66.66 33.33
66.66 33.33 Normal ATHLON64 operation
USB
COMMENT
48.00
X/6X/3
48.00
Reserved Reserved
48.00
30.0060.00
48.00
Reserved Reserved
48.00 Reserved
48.00
48.00
C285
C285
12
C257
C257
1 2
R35522R2F-1-GP R35522R2F-1-GP
R35633R2F-3-GP R35633R2F-3-GP
SRN33J-5-GP-U
SRN33J-5-GP-U
TP31TPAD30 TP31TPAD30
4
C287
C287
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
3D3V_48MPWR_S0
12
C286
C286
DY
DY
SC1U16V3ZY-GP
SC1U16V3ZY-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
R35233R2F-3-GP R35233R2F-3-GP
12
R104261R2F-GP R104261R2F-GP
4
RN28
RN28
33R2F-3-GP
33R2F-3-GP
4
C288
C288
12
C262
C262
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
FS2
FS1
FS0
1 23
R358
R358
12
SMBD0_SB9,20 SMBC0_SB9,20
12 12
R10747D5R2F-1-GP R10747D5R2F-1-GP R10847D5R2F-1-GP R10847D5R2F-1-GP
CLK48_USB_R
3D3V_CLK_VDD
GAP-CLOSE-PWR-2U
GAP-CLOSE-PWR-2U GAP-CLOSE-PWR-2U
GAP-CLOSE-PWR-2U
G96
G96
1 2
G97
G97
1 2
HTREF_CLK_R
CPUCLK_R CPUCLK#_R
NBSRC_CLK_R
NBSRC_CLK#_R
SB
36 26 23 14
46 33
52 42
10
51
54 55 56
44 43
48 47
31 30
35 34
CLK_PCIE_NEW# CLK_PCIE_NEW
SBLINK_CLK# SBLINK_CLK
SBSRC_CLK# SBSRC_CLK
NBSRC_CLK# NBSRC_CLK
CLK_PCIE_MINI1# CLK_PCIE_MINI1
CLK_PCIE_LAN# CLK_PCIE_LAN
CLK_PCIE_DOCK# CLK_PCIE_DOCK
3
VDDSRC VDDSRC VDDSRC VDDSRC
VDDCPU VDDATIG
2
VDDREF VDDHTT
5
VDD48 VDDA
SMBDAT
9
SMBCLK HTTCLK0
FS2/REF2 FS1/REF1 FS0/REF0
CPUCLK8T1 CPUCLK8C1
CPUCLK8T0 CPUCLK8C0
ATIGCLKT1 ATIGCLKC1
ATIGCLKT0 ATIGCLKC0
6
48MHZ_0
7
48MHZ_1
3
1 2 3
2 3 1
1 2 3
2 3 1
1 2 3
2 3 1
2 3 1
ICS9LPR464GLFT-GP
ICS9LPR464GLFT-GP
GNDATIG
RESET_IN#
CLKREQC# CLKREQB# CLKREQA#
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
SRCCLKT2
SRCCLKC2
SRCCLKT1
SRCCLKC1
SRCCLKT0
SRCCLKC0
71.95146.C0W
71.95146.C0W
RN65 SRN49D9F-GPRN65 SRN49D9F-GP
4
RN66
RN66
RN67 SRN49D9F-GPRN67 SRN49D9F-GP
RN68
RN68
RN69 SRN49D9F-GPRN69 SRN49D9F-GP
RN70
RN70
RN71
RN71
SRN49D9F-GP
SRN49D9F-GP
4
4
SRN49D9F-GP
SRN49D9F-GP
4
4
4
SRN49D9F-GP
SRN49D9F-GP
4
SRN49D9F-GP
SRN49D9F-GP
GNDSRC GNDSRC GNDSRC GNDSRC
GNDCPU GNDREF
GNDHTT
GND48
GNDA
NC#40
2
37 27 22 15
45 32 1 50 8 41
CLK_IREF
40 11
53
PD
29 28 49
12 13
16 17
18 19
20 21
24 25
39 38
4
X2
3
X1
U35
U35
CLK48_USB
R486
R486
1 2
475R2F-L1-GP
475R2F-L1-GP
R129
R129
10KR2J-3-GP
10KR2J-3-GP
1 2
DY
DY
CLK_REQA#
CLK_PCIE_DOCK_R CLK_PCIE_DOCK#_R CLK_PCIE_MINI_R CLK_PCIE_MINI#_R
SBSRC_CLK_R SBSRC_CLK#_R CLK_PCIE_NEW_R CLK_PCIE_NEW#_R
SBLINK_CLK_R SBLINK_CLK#_R
CLK_PCIE_LAN_R CLK_PCIE_LAN#_R
1MR2J-L2-GP
1MR2J-L2-GP
12
EC82
EC82
DY
DY
2
12
R359
R359
R115
R115
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
10KR2J-3-GP
10KR2J-3-GP
12
DY
DY
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
HOSONIC
SC
TP79
TP79
1
TPAD28
TPAD28
2 3 1
2 3 1
2 3 1
2 3 1
1 2 3
1 2 3
12
X2
X2 X-14D31818M-35GP
X-14D31818M-35GP
1 2
C278
C278
12
LAYOUT
LAYOUT
LAYOUT
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
SRN33J-5-GP-U
SRN33J-5-GP-U
RN32
RN32
4
SRN33J-5-GP-U
SRN33J-5-GP-U
RN33
RN33
4
SRN33J-5-GP-U
SRN33J-5-GP-U
RN34
RN34
4
SRN33J-5-GP-U
SRN33J-5-GP-U
RN35
RN35
4
SRN33J-5-GP-U
SRN33J-5-GP-U
4
RN30
RN30
SRN33J-5-GP-U
SRN33J-5-GP-U
4
RN27
RN27
C270SC33P50V2JN-3GP C270SC33P50V2JN-3GP
CLKGEN_ICS951464
CLKGEN_ICS951464
CLKGEN_ICS951464
Ferrari 7
Ferrari 7
Ferrari 7
1
CLK_PCIE_DOCK 28 CLK_PCIE_DOCK# 28
CLK_PCIE_MINI1 29 CLK_PCIE_MINI1# 29
SBSRC_CLK 17 SBSRC_CLK# 17
CLK_PCIE_NEW 29 CLK_PCIE_NEW# 29
SBLINK_CLK 12 SBLINK_CLK# 12
CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
of
of
of
347Thursday, August 02, 2007
347Thursday, August 02, 2007
347Thursday, August 02, 2007
1
SB
SB
SB
5
D D
NB0HTTCLKOUT110 NB0HTTCLKOUTJ110 NB0HTTCLKOUT010 NB0HTTCLKOUTJ010
4
NB0HTTCTLOUT10 NB0HTTCTLOUTJ10
1 2 3
SRN51J-GP
SRN51J-GP
NB0CADOUT[15..0]10 NB0CADOUTJ[15..0]10
SB
RN26
RN26
1D2V_S0
C C
B B
4
NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0
CPUHTTCTLIN1 CPUHTTCTLINJ1 NB0HTTCTLOUT NB0HTTCTLOUTJ
NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8
NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
N5
L0_CADIN_H15
P5
L0_CADIN_L15
M3
L0_CADIN_H14
M4
L0_CADIN_L14
L5
L0_CADIN_H13
M5
L0_CADIN_L13
K3
L0_CADIN_H12
K4
L0_CADIN_L12
H3
L0_CADIN_H11
H4
L0_CADIN_L11
G5
L0_CADIN_H10
H5
L0_CADIN_L10
F3
L0_CADIN_H9
F4
L0_CADIN_L9
E5
L0_CADIN_H8
F5
L0_CADIN_L8
N3
L0_CADIN_H7
N2
L0_CADIN_L7
L1
L0_CADIN_H6
M1
L0_CADIN_L6
L3
L0_CADIN_H5
L2
L0_CADIN_L5
J1
L0_CADIN_H4
K1
L0_CADIN_L4
G1
L0_CADIN_H3
H1
L0_CADIN_L3
G3
L0_CADIN_H2
G2
L0_CADIN_L2
E1
L0_CADIN_H1
F1
L0_CADIN_L1
E3
L0_CADIN_H0
E2
L0_CADIN_L0
62.10055.111
62.10055.111
HYPERTRANSPORT
HYPERTRANSPORT
3
U53A
U53A
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
CPUHTTCLKOUT1
Y4
CPUHTTCLKOUTJ1
Y3
CPUHTTCLKOUT0
Y1
CPUHTTCLKOUTJ0
W1 T5
R5
CPUHTTCTLOUT0
R2
CPUHTTCTLOUTJ0
R3
CPUCADOUT15
T4
CPUCADOUTJ15
T3
CPUCADOUT14
V5
CPUCADOUTJ14
U5
CPUCADOUT13
V4
CPUCADOUTJ13
V3
CPUCADOUT12
Y5
CPUCADOUTJ12
W5
CPUCADOUT11
AB5
CPUCADOUTJ11
AA5
CPUCADOUT10
AB4
CPUCADOUTJ10
AB3
CPUCADOUT9
AD5
CPUCADOUTJ9
AC5
CPUCADOUT8
AD4
CPUCADOUTJ8
AD3
CPUCADOUT7
T1
CPUCADOUTJ7
R1
CPUCADOUT6
U2
CPUCADOUTJ6
U3
CPUCADOUT5
V1
CPUCADOUTJ5
U1
CPUCADOUT4
W2
CPUCADOUTJ4
W3
CPUCADOUT3
AA2
CPUCADOUTJ3
AA3
CPUCADOUT2
AB1
CPUCADOUTJ2
AA1
CPUCADOUT1
AC2
CPUCADOUTJ1
AC3
CPUCADOUT0
AD1
CPUCADOUTJ0
AC1
CPUHTTCLKOUT1 10 CPUHTTCLKOUTJ1 10 CPUHTTCLKOUT0 10 CPUHTTCLKOUTJ0 10
CPUHTTCTLOUT0 10 CPUHTTCTLOUTJ0 10
2
CPUCADOUT[15..0] 10 CPUCADOUTJ[15..0] 10
1
LAYOUT
LAYOUT
A A
5
4
3
2
LAYOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
CPU(1/4)_HyperTransport I/F
CPU(1/4)_HyperTransport I/F
CPU(1/4)_HyperTransport I/F
Ferrari 7
Ferrari 7
Ferrari 7
1
of
of
of
447Thursday, August 02, 2007
447Thursday, August 02, 2007
447Thursday, August 02, 2007
SB
SB
SB
5
D D
U53B
U53B
MEMORY
MEMORY
INTERFACE
INTERFACE
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
MA_DQS_H7 MA_DQS_H6 MA_DQS_H5 MA_DQS_H4 MA_DQS_H3 MA_DQS_H2 MA_DQS_H1 MA_DQS_H0
M_A_DQ[63..0]9
C C
B B
M_A_DQ63 M_A_DQ62 M_A_DQ61 M_A_DQ60 M_A_DQ59 M_A_DQ58 M_A_DQ57 M_A_DQ56 M_A_DQ55 M_A_DQ54 M_A_DQ53 M_A_DQ52 M_A_DQ51 M_A_DQ50 M_A_DQ49 M_A_DQ48 M_A_DQ47 M_A_DQ46 M_A_DQ45 M_A_DQ44 M_A_DQ43 M_A_DQ42 M_A_DQ41 M_A_DQ40 M_A_DQ39 M_A_DQ38 M_A_DQ37 M_A_DQ36 M_A_DQ35 M_A_DQ34 M_A_DQ33 M_A_DQ32 M_A_DQ31 M_A_DQ30 M_A_DQ29 M_A_DQ28 M_A_DQ27 M_A_DQ26 M_A_DQ25 M_A_DQ24 M_A_DQ23 M_A_DQ22 M_A_DQ21 M_A_DQ20 M_A_DQ19 M_A_DQ18 M_A_DQ17 M_A_DQ16 M_A_DQ15 M_A_DQ14 M_A_DQ13 M_A_DQ12 M_A_DQ11 M_A_DQ10 M_A_DQ9 M_A_DQ8 M_A_DQ7 M_A_DQ6 M_A_DQ5 M_A_DQ4 M_A_DQ3 M_A_DQ2 M_A_DQ1 M_A_DQ0
AA12 AB12 AA14 AB14
W11
AD13 AB13 AD15 AB15 AB17
W14 W16
AD17 AD19
AD21 AB21 AB18 AA18 AA20
AA22
W21
W22 AA21 AB22 AB24
Y12
Y17 Y14
Y18
Y20 Y22
Y24 H22 H20 E22 E21 J19 H24 F22 F20 C23 B22 F18 E18 E20 D22 C19 G18 G17 C17 F14 E14 H17 E17 E15 H15 E13 C13 H12 H11 G14 H14 F12 G12
MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10 MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0
MA0_CS_L3 MA0_CS_L2 MA0_CS_L1 MA0_CS_L0
MA0_ODT1 MA0_ODT0
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK2 MA_BANK1 MA_BANK0
MA_CKE1 MA_CKE0
MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10
MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0
MA_DQS_L7 MA_DQS_L6 MA_DQS_L5 MA_DQS_L4 MA_DQS_L3 MA_DQS_L2 MA_DQS_L1 MA_DQS_L0
MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0
4
M_B_DQ[63..0]9
Y16 AA16 E16 F16
V19 J22 V22 T19
V20 U19
U20 U21 T20
K22 R20 T22
J20 J21
K19 K20 V24 K24 L20 R19 L19 L22 L21 M19 M20 M24 M22 N22 N21 R21
W12 W13 Y15 W15 AB19 AB20 AD23 AC23 G22 G21 C22 C21 G16 G15 G13 H13
Y13 AB16 Y19 AC24 F24 E19 C15 E12
M_A_A15 M_A_A14 M_A_A13 M_A_A12 M_A_A11 M_A_A10 M_A_A9 M_A_A8 M_A_A7 M_A_A6 M_A_A5 M_A_A4 M_A_A3 M_A_A2 M_A_A1 M_A_A0
M_A_DQS7 M_A_DQS#7 M_A_DQS6 M_A_DQS#6 M_A_DQS5 M_A_DQS#5 M_A_DQS4 M_A_DQS#4 M_A_DQS3 M_A_DQS#3 M_A_DQS2 M_A_DQS#2 M_A_DQS1 M_A_DQS#1 M_A_DQS0 M_A_DQS#0
M_A_DM7 M_A_DM6 M_A_DM5 M_A_DM4 M_A_DM3 M_A_DM2 M_A_DM1 M_A_DM0
M_A_CLK_DDR2 9 M_A_CLK_DDR2# 9 M_A_CLK_DDR1 9 M_A_CLK_DDR1# 9
M_A_CS3# 8,9 M_A_CS2# 8,9 M_A_CS1# 8,9 M_A_CS0# 8,9
M_A_ODT1 8,9 M_A_ODT0 8,9
M_A_CAS# 8,9 M_A_WE# 8,9 M_A_RAS# 8,9
M_A_BS#2 8,9 M_A_BS#1 8,9 M_A_BS#0 8,9
M_A_CKE1 8,9 M_A_CKE0 8,9
M_A_DQS[7..0] 9
M_A_DQS#[7..0] 9
M_A_DM[7..0] 9
M_A_A[15..0] 8,9
3
U53C
U53C
M_B_DQ63
AD11 AF11 AF14 AE14
AB11 AC12 AF13 AF15 AF16 AC18 AF19 AD14 AC14 AE18 AD18 AD20 AC20 AF23 AF24 AF20 AE20 AD22 AC22 AE25 AD26 AA25 AA26 AE24 AD24 AA23 AA24
Y11
G24 G23 D26 C26 G26 G25 E24 E23 C24 B24 C20 B20 C25 D24 A21 D20 D18 C18 D14 C14 A20 A19 A16 A15 A13 D12 E11 G11 B14 A14 A11 C11
MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10 MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0
M_B_DQ62 M_B_DQ61 M_B_DQ60 M_B_DQ59 M_B_DQ58 M_B_DQ57 M_B_DQ56 M_B_DQ55 M_B_DQ54 M_B_DQ53 M_B_DQ52 M_B_DQ51 M_B_DQ50 M_B_DQ49 M_B_DQ48 M_B_DQ47 M_B_DQ46 M_B_DQ45 M_B_DQ44 M_B_DQ43 M_B_DQ42 M_B_DQ41 M_B_DQ40 M_B_DQ39 M_B_DQ38 M_B_DQ37 M_B_DQ36 M_B_DQ35 M_B_DQ34 M_B_DQ33 M_B_DQ32 M_B_DQ31 M_B_DQ30 M_B_DQ29 M_B_DQ28 M_B_DQ27 M_B_DQ26 M_B_DQ25 M_B_DQ24 M_B_DQ23 M_B_DQ22 M_B_DQ21 M_B_DQ20 M_B_DQ19 M_B_DQ18 M_B_DQ17 M_B_DQ16 M_B_DQ15 M_B_DQ14 M_B_DQ13 M_B_DQ12 M_B_DQ11 M_B_DQ10 M_B_DQ9 M_B_DQ8 M_B_DQ7 M_B_DQ6 M_B_DQ5 M_B_DQ4 M_B_DQ3 M_B_DQ2 M_B_DQ1 M_B_DQ0
MEMORY
MEMORY
INTERFACE
INTERFACE
2
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
MB0_CS_L3 MB0_CS_L2 MB0_CS_L1 MB0_CS_L0
MB0_ODT1 MB0_ODT0
MB_CAS_L
MB_WE_L
MB_RAS_L MB_BANK2
MB_BANK1 MB_BANK0
MB_CKE1 MB_CKE0
MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10
MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0
AF18 AF17 A17 A18
Y26 J24 W24 U23
W23 W26
V26 U22 U24
K26 T26 U26
H26 J23
J25 J26 W25 L23 L25 U25 L24 M26 L26 N23 N24 N25 N26 P24 P26 T24
AF12 AE12 AE16 AD16 AF21 AF22 AC25 AC26 F26 E26 A24 A23 D16 C16 C12 B12
AD12 AC16 AE22 AB26 E25 A22 B16 A12
M_B_A15 M_B_A14 M_B_A13 M_B_A12 M_B_A11 M_B_A10 M_B_A9 M_B_A8 M_B_A7 M_B_A6 M_B_A5 M_B_A4 M_B_A3 M_B_A2 M_B_A1 M_B_A0
M_B_DQS7 M_B_DQS#7 M_B_DQS6 M_B_DQS#6 M_B_DQS5 M_B_DQS#5 M_B_DQS4 M_B_DQS#4 M_B_DQS3 M_B_DQS#3 M_B_DQS2 M_B_DQS#2 M_B_DQS1 M_B_DQS#1 M_B_DQS0 M_B_DQS#0
M_B_DM7 M_B_DM6 M_B_DM5 M_B_DM4 M_B_DM3 M_B_DM2 M_B_DM1 M_B_DM0
M_B_CLK_DDR2 9 M_B_CLK_DDR2# 9 M_B_CLK_DDR1 9 M_B_CLK_DDR1# 9
M_B_CS3# 8,9 M_B_CS2# 8,9 M_B_CS1# 8,9 M_B_CS0# 8,9
M_B_ODT1 8,9 M_B_ODT0 8,9
M_B_CAS# 8,9 M_B_WE# 8,9 M_B_RAS# 8,9
M_B_BS#2 8,9 M_B_BS#1 8,9 M_B_BS#0 8,9
M_B_CKE1 8,9 M_B_CKE0 8,9
M_B_A[15..0] 8,9
M_B_DQS[7..0] 9
M_B_DQS#[7..0] 9
M_B_DM[7..0] 9
1
A A
5
4
3
2
LAYOUT
LAYOUT
LAYOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet
Date: Sheet
CPU(2/4)_DDR
CPU(2/4)_DDR
CPU(2/4)_DDR
Ferrari 7
Ferrari 7
Ferrari 7
of
of
547Thursday, August 02, 2007
547Thursday, August 02, 2007
547Thursday, August 02, 2007
1
SB
SB
SB
5
D D
IF 0 ohm IS NOT GOOD ENOUGH, TRY 68.00082.491
R336
R336
0R3-0-U-GP
0R3-0-U-GP
1 2
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
CPUCLK3
CPUCLK#3
C C
R91
CPU_TEST25_H
CPU_TEST26
CPU_TEST18
R91
1 2
300R2J-4-GP
300R2J-4-GP
510R2F-L-GP
510R2F-L-GP
R279
R279
12
300R2J-4-GP
300R2J-4-GP
R79
R79
12
12
C600
C600
C602
C602
1 2
SC3900P50V2KX-2GP
SC3900P50V2KX-2GP
C603
C603
1 2
SC3900P50V2KX-2GP
SC3900P50V2KX-2GP
Near To CPU
1D8V_S3
Remove these resistor
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
100R3J-4-GP
100R3J-4-GP
COREFB38 COREFB#38
100R3J-4-GP
100R3J-4-GP
2D5V_VDDA_S02D5V_S0
C599
C599
VCC_CORE_S0
R77
R77
R88
R88
12
12
12
12
R332
R332 169R2F-GP
169R2F-GP
1D8V_S3
when using
CPU_TEST19
B B
CPU_TEST21
CPU_TEST25_L
CPU_SIC
1 2
1 2
1 2
R81
R81
12
300R2J-4-GP
300R2J-4-GP
R65
R65
300R2J-4-GP
300R2J-4-GP
R89
R89
510R2F-L-GP
510R2F-L-GP
R282
R282
300R2J-4-GP
300R2J-4-GP
EVT CPU
Change;Add
H_THERMDA
H_THERMDC
4
LYAOUT:ROUTE VDDA TRACE APPROX. 50mils WIDE(USE 2X25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.
12
12
C211
C211
SC3300P50V2KX-1GP
SC3300P50V2KX-1GP
SC10U10V5ZY-1GP
CLKCPU_IN
CLKCPU#_IN
CPU_PRESENT#38
COREFB COREFB#
1 2
R280 39D2R2F-L-GPR280 39D2R2F-L-GP
1 2
R284 39D2R2F-L-GPR284 39D2R2F-L-GP
12
SC10U10V5ZY-1GP
TP8TPAD30 TP8TPAD30 TP9TPAD30 TP9TPAD30
VREF_DDR_CLAW
H_THERMDC36 H_THERMDA36
C104
C104 SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
C601
C601
TP11TPAD30 TP11TPAD30 TP16TPAD30 TP16TPAD30 TP18TPAD30 TP18TPAD30 TP21TPAD30 TP21TPAD30
TP30TPAD30 TP30TPAD30
TP20TPAD30 TP20TPAD30
TP73TPAD30 TP73TPAD30 TP74TPAD30 TP74TPAD30 TP28TPAD30 TP28TPAD30 TP76TPAD30 TP76TPAD30 TP17TPAD30 TP17TPAD30
1 1
CPU_SIC CPU_SID
12
C598
C598
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SB_CPUPWRGD LDT_STP# LDT_RST#
CPU_PRESENT#
TDI
1
TRST_L
1
TCK
1
TMS
1
DBREQJ
1
VTT_SENSE
1
MEMZN MEMZP
CPU_TEST25_H CPU_TEST25_L CPU_TEST19 CPU_TEST18
CPU_TEST17
1
CPU_TEST16
1
CPU_TEST15
1
CPU_TEST14
1
CPU_TEST12
1
AC6
AF4 AF5
AF9 AD9 AC9 AA9
W17
AE10
AF10
H10 AA7
AC8
AA6
AB6
F10
E10
Y10
F8 F9
A9 A8
A7 B7
F6 E6
E9 E8
G9
C2 D7
E7 F7 C7
C3
W7 W8
Y6
VDDA1 VDDA2
CLKIN_H CLKIN_L
PWROK LDTSTOP_L RESET_L
CPU_PRESENT_L
SIC SID
TDI TRST_L
MISC
MISC
TCK TMS
DBREQ_L VDD_FB_H
VDD_FB_L VTT_SENSE M_VREF
M_ZN M_ZP
TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9
TEST17 TEST16 TEST15 TEST14 TEST12
TEST7 TEST6 THERMDC THERMDA TEST3 TEST2
3
P20
RSVD_MA0_CLK_H3
P19
RSVD_MA0_CLK_L3
N20
RSVD_MA0_CLK_H0
N19
RSVD_MA0_CLK_L0
R26
RSVD_MB0_CLK_H3
R25
RSVD_MB0_CLK_L3
P22
RSVD_MB0_CLK_H0
R22
RSVD_MB0_CLK_L0
THERMTRIP_L
PROCHOT_L
DBRDY
VDDIO_FB_H
VDDIO_FB_L
PSI_L
HTREF1 HTREF0
TEST29_H
TEST29_L
TEST24 TEST23 TEST22 TEST21 TEST20
TEST28_H
TEST28_L
TEST27 TEST26 TEST10
TEST8
RSVD_MA_RESET_L RSVD_MB_RESET_L
RSVD_VIDSTRB1 RSVD_VIDSTRB0
RSVD_VDDNB_FB_H RSVD_VDDNB_FB_L
RSVD_CORE_TYPE
MISC
MISC
INTERNAL
INTERNAL
U53D
U53D
A5
VID5
C6
VID4
A6
VID3
A4
VID2
C5
VID1
B5
VID0
AF6 AC7
AE9
TDO
G10 W9
Y9 A3
CPU_HTREF1
P6
CPU_HTREF0
R6
C9 C8
AE7 AD7 AE8 AB8 AF7
J7 H8 AF8 AE6 K8 C4
U53E
U53E
H16 B18
B3 C1
H6 G6 D5
R24
FREE5
W18
FREE6
R23
FREE4
AA8
FREE1
H18
FREE2
H19
FREE3
1D8V_S3
12
R95
R95 300R2J-4-GP
300R2J-4-GP
TP14 TPAD30TP14 TPAD30
TP27 TPAD30TP27 TPAD30
TP23 TPAD30TP23 TPAD30 TP22 TPAD30TP22 TPAD30
PSI# 38
1 2 1 2
1 2
TP12 TPAD30TP12 TPAD30 TP15 TPAD30TP15 TPAD30 TP13 TPAD30TP13 TPAD30
TP10 TPAD30TP10 TPAD30
VID[5..0] 38
80D6R2F-L-GP
80D6R2F-L-GP
VID5 VID4 VID3 VID2 VID1 VID0
THERMTRIP# PROCHOT#
TDO
VDDIO_FB VDDIO_FB#
CPU_TEST29H CPU_TEST29L
CPU_TEST24 CPU_TEST23 CPU_TEST22 CPU_TEST21 CPU_TEST20
CPU_TEST26
1
DBRDY
1
1 1
PSI#
R93 44D2R2F-GPR93 44D2R2F-GP R68 44D2R2F-GPR68 44D2R2F-GP
R94
LAYOUT: Route FBCLKOUT_H/L
R94
differentially impedance 80
1 1 1
1
2
R281
R281
300R2J-4-GP
300R2J-4-GP
THERMTRIP#
1D2V_S0
SB_CPUPWRGD
1D8V_S3
12
2K2R2J-2-GP
2K2R2J-2-GP
PROCHOT#
12
R61
R61
C75
C75
1 2
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3
2
MMBT3904-U1
MMBT3904-U1
Q14
Q14
2ND = 84.03904.T11
2ND = 84.03904.T11
1D8V_S3 3D3V_S0
12
R62
R62
300R2J-4-GP
300R2J-4-GP
KBC_THERMTRIP# 32
12
VREF_DDR_CLAW
1D8V_S3
DELETE C71 FOR LAYOUT ROUTING,C125 CLOSE TO RN6
SRN1KJ-7-GP
SRN1KJ-7-GP
2 3 1
4
RN6
RN6
LAYOUT: Locate close to CPU.
C74
C74
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
1
-1
R146
R146 4K7R2J-2-GP
4K7R2J-2-GP
ALERT# 18,36
VREF_DDR_CLAW
12
C105
C105
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
LDT_RST#17
LDT_STP#12,17
A A
SB_CPUPWRGD17
5
4
3
12
12
12
R333
R333 680R2F-GP
680R2F-GP
R82
R82 680R2F-GP
680R2F-GP
R334
R334 680R2F-GP
680R2F-GP
LAYOUT
LAYOUT
LAYOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
2
Date: Sheet
CPU(3/4)_Control & Debug
CPU(3/4)_Control & Debug
CPU(3/4)_Control & Debug
Ferrari 7
Ferrari 7
Ferrari 7
647Thursday, August 02, 2007
647Thursday, August 02, 2007
647Thursday, August 02, 2007
1
SB
SB
SB
of
of
of
5
1D2V_S0
D4
VLDT_A4
D3
VLDT_A3
D2
VLDT_A2
D1
0D9V_S3
D D
1D8V_S3
C C
0D9V_S3 1D8V_S3
B B
VLDT_A1
D10
VTT8
C10
VTT7
B10
VTT6
AD10
VTT5
W10
VTT9
H25
VDDIO23
J17
VDDIO1
K18
VDDIO2
K21
VDDIO3
K23
VDDIO4
K25
VDDIO5
L17
VDDIO6
M18
VDDIO7
M21
VDDIO8
M23
VDDIO9
M25
VDDIO10
N17
VDDIO11
P18
VDDIO12
P21
VDDIO13
P23
VDDIO14
P25
VDDIO15
R17
VDDIO16
T18
VDDIO17
T21
VDDIO18
T23
VDDIO19
T25
VDDIO20
U17
VDDIO21
V18
VDDIO22
V21
VDDIO24
V23
VDDIO25
V25
VDDIO26
Y25
VDDIO27
1 2
C226
C226
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
I O
I O
POWER
POWER
VLDT_B4 VLDT_B3 VLDT_B2 VLDT_B1
VTT4 VTT3 VTT2 VTT1
VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90
U53H
U53H
LAYOUT: Place on backside of processor.
VCC_CORE_S0
12
C178
C178
12
10u x 9
C165
C165
0.22u x 2
12
12
12
12
12
12
C115
C115
C166
C166
C145
C145
C129
C129
C128
C128
C179
C179
12
C144
C144
AE5 AE4 AE3 AE2
AC10 AB10 AA10 A10
D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 M11
12
1D2V_S0
C114
C114
4
12
C175
C175
1 2
0D9V_S3
0.01u x 2
12
C113
C113
C81
C81 SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1D8V_S3
12
C162
C162
12
12
C126
C126
C164
C164
0.22u X 6
12
12
C125
C125
C177
C177
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
180p x 4
12
C127
C127
12
12
C146
C146
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
12
12
C171
C171
C159
C159
12
C116
C116
C147
C147
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
3
1D8V_S3
12
C172
C172
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
VCC_CORE_S0
10u x 4
12
12
C196
C196
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AC4
VDD1
AD2
VDD2
G4
VDD3
H2
VDD4
J9
VDD5
J11
VDD6
J13
VDD7
K6
VDD8
K10
VDD9
K12
VDD10
K14
VDD11
L4
VDD12
L7
VDD13
L9
VDD14
L11
VDD15
L13
VDD16
M2
VDD17
M6
VDD18
M8
VDD19
M10
VDD20
N7
VDD21
N9
VDD22
N11
VDD23
P8
VDD24
P10
VDD25
R4
VDD26
R7
VDD27
R9
VDD28
R11
VDD29
T2
VDD30
T6
VDD31
T8
VDD32
T10
VDD33
T12
VDD34
T14
VDD35
U7
VDD36
U9
VDD37
U11
VDD38
U13
VDD39
V6
VDD40
V8
VDD41
V10
VDD42
V12
VDD43
V14
VDD44
W4
VDD45
Y2
VDD46
C100
C100
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
0D9V_S3
VDD
VDD
12
C185
C185
0.22u X 2
12
C236
C236
U53F
U53F
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46
4.7u x 6
12
C148
C148
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
0D9V_S3
12
C597
C597
2
AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17
12
C133
C133
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
12
C241
C241
12
C193
C193
12
C605
C605
12
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
12
C109
C109
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
4.7u x 4
12
C604
C604
VCC_CORE_S0
180P x 2 0.01u X 2
12
C212
C212
C155
C155
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
0D9V_S3
12
12
C240
C240
C98
C98
1
U53G
U53G
J15
VDD47
K16
VDD48
L15
VDD49
M16
VDD50
P16
VDD51
T16
VDD52
U15
VDD53
V16
VDD54
VDD
VDD
1D8V_S3
12
12
C204
C204
C106
C106
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
Place near to CPU
VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS130 VSS131 VSS132 VSS133
12
C187
C187
SCD01U50V2ZY-1GP
SCD01U50V2ZY-1GP
M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
12
C176
C176
SCD01U50V2ZY-1GP
SCD01U50V2ZY-1GP
180P x 6
12
C96
C96
12
12
C229
C229
C232
C232
12
12
C102
C102
C219
C219
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
A A
5
SC10U10V5ZY-1GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
4
SCD01U50V2ZY-1GP
SCD01U50V2ZY-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
12
C586
C586
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
12
C529
C529
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
4.7u x 4
12
C593
C593
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
12
C528
C528
1D2V_S0
12
C86
C86
SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
3
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
0.1u x 3 0.22u X 2
12
12
C590
C590
C591
C591
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C588
C588
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
180p x 2
12
C84
C84
SC180P50V2JN-1GP
SC180P50V2JN-1GP
12
C85
C85
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
12
C592
C592
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
2
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
12
C82
C82
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
LAYOUT
LAYOUT
LAYOUT
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet
Date: Sheet
SC180P50V2JN-1GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
CPU(4/4)_Power
CPU(4/4)_Power
CPU(4/4)_Power
Ferrari 7
Ferrari 7
Ferrari 7
SC180P50V2JN-1GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
SC180P50V2JN-1GP
SC180P50V2JN-1GP
747Thursday, August 02, 2007
747Thursday, August 02, 2007
747Thursday, August 02, 2007
SC180P50V2JN-1GP
SC180P50V2JN-1GP
of
of
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SB
SB
SB
5
4
3
2
1
PARALLEL TERMINATION
Decoupling Capacitor
Put decap near power(0.9V) and pull-up resistor
0D9V_S3
RN17
RN17
1 2 3
D D
C C
B B
A A
4 5
SRN47J-4-GP
SRN47J-4-GP RN11
RN11
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
RN9
RN9
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN19
RN19
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN13
RN13
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN7
RN7
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN12
RN12
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN15
RN15
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN16
RN16
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN14
RN14
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN21
RN21
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
M_A_A11
8
M_A_A4
7
M_A_A6
6
M_A_A2
M_A_A10
8 7
M_A_A3
6
M_A_A1
8 7 6
M_B_A3
8
M_B_A9
7
M_B_A12
6
M_B_A8
8
M_B_A10
7
M_B_A1
6
M_B_A5
8 7 6
8 7 6
M_A_A8
8
M_A_A9
7
M_A_A5
6
M_A_A12
M_B_A7
8
M_B_A11
7
M_B_A6
6
M_B_A4
M_B_A2
8
M_B_A0
7 6
8 7
M_B_A14
6
M_B_A15
5
RN8
RN8
1 2 3 4 5
RN23
RN23
1 2 3 4 5
M_A_BS#0 5,9
SRN47J-4-GP
SRN47J-4-GP
8 7 6
SRN47J-4-GP
SRN47J-4-GP
8 7 6
M_B_ODT1 5,9 M_B_WE# 5,9 M_B_CS1# 5,9 M_B_CAS# 5,9
M_B_BS#0 5,9
M_A_A13 5,9 M_A_ODT0 5,9 M_A_CS3# 5,9
M_A_A0 5,9 M_A_BS#1 5,9 M_A_CS0# 5,9 M_A_RAS# 5,9
M_B_RAS# 5,9 M_B_BS#1 5,9
M_B_CKE1 5,9
0D9V_S3
M_A_A[15..0] 5,9 M_B_A[15..0] 5,9
M_A_CS1# 5,9 M_A_ODT1 5,9 M_A_WE# 5,9 M_A_CAS# 5,9
M_B_CKE0 5,9 M_B_BS#2 5,9 M_B_CS2# 5,9
RN22
RN22
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN24
RN24
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN10
RN10
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
8 7 6
M_A_A14
8 7
M_A_A15
6
M_A_A7
8
M_B_A13
7 6
4
M_A_BS#2 5,9 M_A_CS2# 5,9 M_A_CKE0 5,9
M_A_CKE1 5,9
M_B_CS0# 5,9 M_B_ODT0 5,9
M_B_CS3# 5,9
0D9V_S3
1D8V_S3
1D8V_S3
12
12
12
C167
C167
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C143
C143
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Put decap near power(0.9V) and pull-up resistor
12
C234
C234
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C134
C134
SC1000P50V3JN-GP
SC1000P50V3JN-GP
12
C565
C565 SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
C228
C228
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
12
C200
C200
12
C157
C157
12
C111
C111
SC1000P50V3JN-GP
SC1000P50V3JN-GP
12
C559
C559 SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C191
C191
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C208
C208
SC180P50V2JN-1GP
SC180P50V2JN-1GP
12
C224
C224
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C221
C221
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3
12
12
C130
C130
SC1000P50V3JN-GP
SC1000P50V3JN-GP
Place these Caps near DM1
C137
C137
Place these Caps near DM2
C566
C566 SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
Place these Caps near PARALLEL TERMINATION
12
C233
C233
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C121
C121
SC1000P50V3JN-GP
SC1000P50V3JN-GP
12
C562
C562 SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
C154
C154
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C217
C170
C170
12
12
C217
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
12
C195
C195
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C189
C189
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C579
C579 SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C160
C160
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C218
C218
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C132
C132
12
C557
C557 SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
C184
C184
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C181
C181
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C122
C122
SCD1U16V2ZY-2GP
C230
C230
SC10P50V2JN-4GP
SC10P50V2JN-4GP
12
C190
C190
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C197
C197
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C161
C161
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C215
C215
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C570
C570 SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
C220
C220
2
12
12
C149
C149
SC10P50V2JN-4GP
SC10P50V2JN-4GP
12
C567
C567 SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1D8V_S3
1D8V_S30D9V_S3
12
C214
C214
LAYOUT
LAYOUT
LAYOUT
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
12
C139
C139
C235
C235
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C213
C213 SC680P50V2KX-2GP
SC680P50V2KX-2GP
A3
A3
A3
12
C152
C152
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C153
C153 SC680P50V2KX-2GP
SC680P50V2KX-2GP
12
C227
C227 SC680P50V2KX-2GP
SC680P50V2KX-2GP
Cross Moat Cap
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
DDR DAMPING & TERMINATION
DDR DAMPING & TERMINATION
DDR DAMPING & TERMINATION
Ferrari 7
Ferrari 7
Ferrari 7
847Thursday, August 02, 2007
847Thursday, August 02, 2007
847Thursday, August 02, 2007
1
SB
SB
SB
of
of
of
5
DM1
DM1
MH1
M_B_A[15..0]5,8
D D
M_B_BS#25,8
M_B_BS#05,8 M_B_BS#15,8
M_B_DQ[63..0]5
C C
M_B_CS2#5,8
VREF_DDR_MEM
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
M_B_CS3#5,8
M_B_CS0#5,8 M_B_CS1#5,8 M_B_CKE05,8 M_B_CKE15,8
C272
C272
B B
M_B_RAS#5,8 M_B_CAS#5,8
M_B_WE#5,8
12
M_B_ODT05,8 M_B_ODT15,8
12
C275
C275 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
SMBC0_SB SMBD0_SB
MH1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16_BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
50
NC#50
69
NC#69
83
NC#83
120
NC#120
163
NC#163/TEST
110
CS0#
115
CS1#
79
CKE0
80
CKE1
108
RAS#
113
CAS#
109
WE#
197
SCL
195
SDA
114
ODT0
119
ODT1
1
VREF
201
GND
SKT-SODIMM20020U3GP
SKT-SODIMM20020U3GP
62.10017.661
62.10017.661
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
VDD_SPD
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
MH2
MH2
M_B_DQS0
13
M_B_DQS1
31
M_B_DQS2
51
M_B_DQS3
70
M_B_DQS4
131
M_B_DQS5
148
M_B_DQS6
169
M_B_DQS7
188
M_B_DQS#0
11
M_B_DQS#1
29
M_B_DQS#2
49
M_B_DQS#3
68
M_B_DQS#4
129
M_B_DQS#5
146
M_B_DQS#6
167
M_B_DQS#7
186
M_B_DM0
10
DM0
M_B_DM1
26
DM1
M_B_DM2
52
DM2
M_B_DM3
67
DM3
M_B_DM4
130
DM4
M_B_DM5
147
DM5
M_B_DM6
170
DM6
M_B_DM7
185
DM7
30
CK0
32
CK0#
164
CK1
166
CK1#
DIMM2_SA0
198
SA0
200
SA1
199
81
VDD
82
VDD
87
VDD
88
VDD
95
VDD
96
VDD
103
VDD
104
VDD
111
VDD
112
VDD
117
VDD
118
VDD
2
VSS
3
VSS
8
VSS
9
VSS
12
VSS
15
VSS
18
VSS
21
VSS
24
VSS
27
VSS
28
VSS
33
VSS
34
VSS
39
VSS
40
VSS
41
VSS
42
VSS
47
VSS
48
VSS
53
VSS
54
VSS
59
VSS
60
VSS
65
VSS
66
VSS
71
VSS
72
VSS
77
VSS
78
VSS
121
VSS
122
VSS
127
VSS
128
VSS
132
VSS
133
VSS
138
VSS
139
VSS
144
VSS
145
VSS
149
VSS
150
VSS
155
VSS
156
VSS
161
VSS
162
VSS
165
VSS
168
VSS
171
VSS
172
VSS
177
VSS
178
VSS
183
VSS
184
VSS
187
VSS
190
VSS
193
VSS
196
VSS
202
GND
R60
R60
10KR2J-3-GP
10KR2J-3-GP
1D8V_S3
Place near CPU Place near CPU
1D8V_S3
4
M_A_A[15..0]5,8
M_B_DQS[7..0] 5
M_B_DQS#[7..0] 5
M_B_DM[7..0] 5
M_B_CLK_DDR1 5 M_B_CLK_DDR1# 5 M_B_CLK_DDR2 5 M_B_CLK_DDR2# 5
12
12
C76
C76
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_B_CLK_DDR1
12
C231
C231 SC1D5P50V2CN-1GP
SC1D5P50V2CN-1GP
M_B_CLK_DDR1# M_B_CLK_DDR2 M_A_CLK_DDR2
12
C83
C83 SC1D5P50V2CN-1GP
SC1D5P50V2CN-1GP
M_B_CLK_DDR2#
3D3V_S0
12
C72
C72
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
M_A_BS#25,8 M_A_BS#05,8
M_A_BS#15,8
M_A_DQ[63..0]5
M_A_DQS#[7..0]5
M_A_DQS[7..0]5
DDR_VREF
VREF_DDR_MEM
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
C271
C271
RN31
RN31
1 2 3
SRN1KJ-7-GP
SRN1KJ-7-GP
4
12
C273
C273 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
VREF_DDR_MEM
12
C276
C276 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
M_A_ODT05,8 M_A_ODT15,8
12
3
C274
C274 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DQS0#
29
DQS1#
49
DQS2#
68
DQS3#
129
DQS4#
146
DQS5#
167
DQS6#
186
DQS7#
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
OTD0
119
OTD1
1
VREF
2
VSS
202
GND
MH1
MH1
DM2
DM2
DDR2-200P-22-GP-U2
DDR2-200P-22-GP-U2
VDDSPD
NC#50 NC#69 NC#83
NC#120
NC#163/TEST
RAS# CAS# CS0#
CS1# CKE0
CKE1
CK0#
CK1#
GND
108 109
WE#
113 110
115 79
80 30
CK0
32 164
CK1
166
M_A_DM0
10
DM0
M_A_DM1
26
DM1
M_A_DM2
52
DM2
M_A_DM3
67
DM3
M_A_DM4
130
DM4
M_A_DM5
147
DM5
M_A_DM6
170
DM6
M_A_DM7
185
DM7
195
SDA
197
SCL
199 198
SA0
200
SA1
50 69 83 120 163
81
VDD
82
VDD
87
VDD
88
VDD
95
VDD
96
VDD
103
VDD
104
VDD
111
VDD
112
VDD
117
VDD
118
VDD
3
VSS
8
VSS
9
VSS
12
VSS
15
VSS
18
VSS
21
VSS
24
VSS
27
VSS
28
VSS
33
VSS
34
VSS
39
VSS
40
VSS
41
VSS
42
VSS
47
VSS
48
VSS
53
VSS
54
VSS
59
VSS
60
VSS
65
VSS
66
VSS
71
VSS
72
VSS
77
VSS
78
VSS
121
VSS
122
VSS
127
VSS
128
VSS
132
VSS
133
VSS
138
VSS
139
VSS
144
VSS
145
VSS
149
VSS
150
VSS
155
VSS
156
VSS
161
VSS
162
VSS
165
VSS
168
VSS
171
VSS
172
VSS
177
VSS
178
VSS
183
VSS
184
VSS
187
VSS
190
VSS
193
VSS
196
VSS
201 MH2
MH2
SMBC0_SB 3,20
1D8V_S3
2
M_A_CS0# 5,8 M_A_CS1# 5,8
M_A_CKE0 5,8 M_A_CKE1 5,8
M_A_CLK_DDR1 5 M_A_CLK_DDR1# 5
M_A_CLK_DDR2 5 M_A_CLK_DDR2# 5
SMBD0_SB 3,20
M_A_CLK_DDR1
12
C216
C216 SC1D5P50V2CN-1GP
SC1D5P50V2CN-1GP
M_A_CLK_DDR1#
12
C97
C97 SC1D5P50V2CN-1GP
SC1D5P50V2CN-1GP
M_A_CLK_DDR2#
M_A_RAS# 5,8 M_A_WE# 5,8 M_A_CAS# 5,8
M_A_DM[7..0] 5
M_A_CS2# 5,8 M_A_CS3# 5,8
1
3D3V_S0
12
12
C65
C65
C62
C62
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
2ND = 62.10017.D91
2ND = 62.10017.D91
A A
5
LAYOUT: Locate close to DIMM
4
3
High 5.2mm
Main Source: 62.10017.A61
LAYOUT
LAYOUT
LAYOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet
Date: Sheet
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
DDR SO-DIMM SKT
DDR SO-DIMM SKT
DDR SO-DIMM SKT
Ferrari 7
Ferrari 7
Ferrari 7
1
SB
SB
947Thursday, August 02, 2007
947Thursday, August 02, 2007
947Thursday, August 02, 2007
SB
of
of
of
5
D D
4
3
2
1
CLAW HAMMER TO NB NB TO CLAW HAMMER
CPUCADOUT[15..0]4 CPUCADOUTJ[15..0]4
C C
B B
VDDHT_PKG
CPUHTTCLKOUT14 CPUHTTCLKOUTJ14
CPUHTTCLKOUT04 CPUHTTCLKOUTJ04
CPUHTTCTLOUT04 CPUHTTCTLOUTJ04
1 2 3
RN50 SRN49D9F-GPRN50 SRN49D9F-GP
Close to NB ball
CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8
CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0
CPUHTTCLKOUT1 CPUHTTCLKOUTJ1
CPUHTTCLKOUT0 CPUHTTCLKOUTJ0
CPUHTTCTLOUT0 CPUHTTCTLOUTJ0
4
HT_RXCALP
HT_RXCALN
W19
W20 AC21 AB22 AB20 AA20 AA19
AA25 AA24 AB23 AA23 AB24 AB25 AC24 AC25
W21
W22
W25
R19 R18 R21 R22 U22 U21 U18 U19
Y19 T24
R25 U25 U24 V23 U23 V24 V25
Y24
P24 P25
A24 C24
U52A
U52A
HT_RXCAD15P HT_RXCAD15N HT_RXCAD14P HT_RXCAD14N HT_RXCAD13P HT_RXCAD13N HT_RXCAD12P HT_RXCAD12N HT_RXCAD11P HT_RXCAD11N HT_RXCAD10P HT_RXCAD10N HT_RXCAD9P HT_RXCAD9N HT_RXCAD8P HT_RXCAD8N
HT_RXCAD7P HT_RXCAD7N HT_RXCAD6P HT_RXCAD6N HT_RXCAD5P HT_RXCAD5N HT_RXCAD4P HT_RXCAD4N HT_RXCAD3P HT_RXCAD3N HT_RXCAD2P HT_RXCAD2N HT_RXCAD1P HT_RXCAD1N HT_RXCAD0P HT_RXCAD0N
HT_RXCLK1P HT_RXCLK1N
HT_RXCLK0P HT_RXCLK0N
HT_RXCTLP HT_RXCTLN
HT_RXCALP HT_RXCALN
RS690T-GP
RS690T-GP
PART 1 OF 6
PART 1 OF 6
HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N
HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N
HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N
HT_TXCLK1P
HYPER TRANSPORT CPU
I/F
HYPER TRANSPORT CPU
I/F
HT_TXCLK1N HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP HT_TXCTLN
HT_TXCALP HT_TXCALN
P21 P22 P18 P19 M22 M21 M18 M19 L18 L19 G22 G21 J20 J21 F21 F22
N24 N25 L25 M24 K25 K24 J23 K23 G25 H24 F25 F24 E23 F23 E24 E25
L21 L22
J24 J25
N23 P23
C25 D24
NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8
NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0
NB0HTTCLKOUT1 NB0HTTCLKOUTJ1
NB0HTTCLKOUT0 NB0HTTCLKOUTJ0
NB0HTTCTLOUT NB0HTTCTLOUTJ
HT_TXCALP HT_TXCALN
NB0HTTCLKOUT1 4 NB0HTTCLKOUTJ1 4
NB0HTTCLKOUT0 4 NB0HTTCLKOUTJ0 4
NB0HTTCTLOUT 4 NB0HTTCTLOUTJ 4
R310
1 2
R310 100R2F-L1-GP-U
100R2F-L1-GP-U
Close to NB ball
NB0CADOUT[15..0] 4 NB0CADOUTJ[15..0] 4
LAYOUT
LAYOUT
A A
5
4
3
2
LAYOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
NB-RS690T_HT
NB-RS690T_HT
NB-RS690T_HT
Ferrari 7
Ferrari 7
Ferrari 7
1
of
of
of
10 47Thursday, August 02, 2007
10 47Thursday, August 02, 2007
10 47Thursday, August 02, 2007
SB
SB
SB
5
D D
4
3
2
1
U52B
U52B
G5
GFX_RX0P
G4
GFX_RX0N
J8
GFX_RX1P
J7
GFX_RX1N
J4
GFX_RX2P
J5
GFX_RX2N
L8
GFX_RX3P
L7
GFX_RX3N
L4
GFX_RX4P
L5
GFX_RX4N
M8
GFX_RX5P
M7
GFX_RX5N
M4
GFX_RX6P
M5
GFX_RX6N
P8
GFX_RX7P
P7
GFX_RX7N
PCIE_RX2P_SB17
C C
PCIE_RXP229 PCIE_RXN229
PCIE_RXP329 PCIE_RXN329
PCIE_RXP028 PCIE_RXN028
PCIE_RXP124 PCIE_RXN124
A-LINK
B B
PCIE_RX2N_SB17 PCIE_RX3P_SB17
PCIE_RX3N_SB17
PCIE_RX0P_SB17 PCIE_RX0N_SB17 PCIE_RX1P_SB17 PCIE_RX1N_SB17
TP19TPAD30 TP19TPAD30 TP60TPAD30 TP60TPAD30
PCE_ISET
1
PCE_TXISET
1
Y4
SB_RX2P
Y5
SB_RX2N
W4
SB_RX3P
W5
SB_RX3N
P4
GPP_RX2P
P5
GPP_RX2N
R4
GPP_RX3P
R5
GPP_RX3N
R7
GPP_RX0P
R8
GPP_RX0N
U4
GPP_RX1P
U5
GPP_RX1N
AB7
SB_RX0P
AB6
SB_RX0N
V9
SB_RX1P
W9
SB_RX1N
AC4
NC#AC4
AD4
NC#AD4
RS690T-GP
RS690T-GP
PART 2 OF 6
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP PCE_CALRN
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
SB_TX2P SB_TX2N
SB_TX3P SB_TX3N
GPP_TX2P GPP_TX2N
GPP_TX3P GPP_TX3N
GPP_TX0P GPP_TX0N
GPP_TX1P GPP_TX1N
SB_TX0P SB_TX0N SB_TX1P SB_TX1N
J1 H2 K2 K1 K3 L3 L1 L2 N2 N1 P2 P1 P3 R3 R1 R2
AA1 AA2
Y2 Y3
U2 U1
V2 V1
V3 W3
W1 W2
AC1 AC2 AB1 AB2
AE4 AE3
GTXN0 GTXP1 GTXN1 GTXP2 GTXN2 GTXP3 GTXN3
SB_TX2P SB_TX2N
SB_TX3P SB_TX3N
GPP_TX2P GPP_TX2N
GPP_TX3P GPP_TX3N
GPP_TX0P GPP_TX0N
GPP_TX1P GPP_TX1N
SB_TX0P SB_TX0N SB_TX1P SB_TX1N
PCE_PCAL PCE_NCAL
GTXP0
C561 SCD1U10V2KX-4GPC561 SCD1U10V2KX-4GP
1 2
C563 SCD1U10V2KX-4GPC563 SCD1U10V2KX-4GP
1 2
C558 SCD1U10V2KX-4GPC558 SCD1U10V2KX-4GP
1 2
C556 SCD1U10V2KX-4GPC556 SCD1U10V2KX-4GP
1 2
C555 SCD1U10V2KX-4GPC555 SCD1U10V2KX-4GP
1 2
C554 SCD1U10V2KX-4GPC554 SCD1U10V2KX-4GP
1 2
C553 SCD1U10V2KX-4GPC553 SCD1U10V2KX-4GP
1 2
C552 SCD1U10V2KX-4GPC552 SCD1U10V2KX-4GP
1 2
C541 SCD1U10V2KX-4GPC541 SCD1U10V2KX-4GP
1 2
C540 SCD1U10V2KX-4GPC540 SCD1U10V2KX-4GP
1 2
C543 SCD1U10V2KX-4GPC543 SCD1U10V2KX-4GP
1 2
C542 SCD1U10V2KX-4GPC542 SCD1U10V2KX-4GP
1 2
C551 SCD1U10V2KX-4GPC551 SCD1U10V2KX-4GP
1 2
C550 SCD1U10V2KX-4GPC550 SCD1U10V2KX-4GP
1 2
C549 SCD1U10V2KX-4GPC549 SCD1U10V2KX-4GP
1 2
C547 SCD1U10V2KX-4GPC547 SCD1U10V2KX-4GP
1 2
C120 SCD1U10V2KX-4GPC120 SCD1U10V2KX-4GP
1 2
C119 SCD1U10V2KX-4GPC119 SCD1U10V2KX-4GP
1 2
C546 SCD1U10V2KX-4GPC546 SCD1U10V2KX-4GP
1 2
C545 SCD1U10V2KX-4GPC545 SCD1U10V2KX-4GP
1 2
C527 SCD1U10V2KX-4GPC527 SCD1U10V2KX-4GP
1 2
C525 SCD1U10V2KX-4GPC525 SCD1U10V2KX-4GP
1 2
C539 SCD1U10V2KX-4GPC539 SCD1U10V2KX-4GP
1 2
C532 SCD1U10V2KX-4GPC532 SCD1U10V2KX-4GP
1 2
R296 562R2F-GPR296 562R2F-GP
1 2
R297 2KR2F-3-GPR297 2KR2F-3-GP
1 2
Close to NB ball
TMDS_A_TX2+ 28 TMDS_A_TX2- 28 TMDS_A_TX1+ 28 TMDS_A_TX1- 28 TMDS_A_TX0+ 28 TMDS_A_TX0- 28 TMDS_A_TXc+ 28 TMDS_A_TXc- 28
PCIE_TX2P_SB 17 PCIE_TX2N_SB 17
PCIE_TX3P_SB 17 PCIE_TX3N_SB 17
PCIE_TXP2 29 PCIE_TXN2 29
PCIE_TXP3 29 PCIE_TXN3 29
PCIE_TXP0 28 PCIE_TXN0 28
PCIE_TXP1 24 PCIE_TXN1 24
PCIE_TX0P_SB 17 PCIE_TX0N_SB 17 PCIE_TX1P_SB 17 PCIE_TX1N_SB 17
VDDA12_PKG2
DVI
NEWCARD MINICARD
LAN
CLOSE TO CAP
R488
R488
100R2J-3-GP
100R2J-3-GP
1 2
R489
R489
100R2J-3-GP
100R2J-3-GP
1 2
R490
R490
100R2J-3-GP
100R2J-3-GP
1 2
R491
R491
100R2J-3-GP
100R2J-3-GP
1 2
TMDS_A_TXc+ TMDS_A_TXc-
TMDS_A_TX0+ TMDS_A_TX0-
TMDS_A_TX1+ TMDS_A_TX1-
TMDS_A_TX2+ TMDS_A_TX2-
LAYOUT
LAYOUT
A A
5
4
3
2
LAYOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
NB-RS690M_MEM/PCIE_LINK I/F
NB-RS690M_MEM/PCIE_LINK I/F
NB-RS690M_MEM/PCIE_LINK I/F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Ferrari 7
Ferrari 7
Ferrari 7
of
of
of
11 47Thursday, August 02, 2007
11 47Thursday, August 02, 2007
11 47Thursday, August 02, 2007
1
SB
SB
SB
5
4
3
2
1
1D8V_S0
R325
R325
1 2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
D D
R198--R200 And R219-R220 Close to NB
TV_DACC28 TV_DACB28 TV_DACA28
GMCH_RED28 GMCH_GREEN28 GMCH_BLUE28
Change 0919
C C
1D2V_S0
L3
L3
1 2
HPB2012ZF-221T30-GP
HPB2012ZF-221T30-GP
B B
LDT_STP#6,17
A A
AVDDQ
12
C582
C582
1D8V_S0
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
10KR2J-3-GP
10KR2J-3-GP
BMREQ#17
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
SC1U10V2ZY
SC1U10V2ZY
12
12
C576
C576
C568
C568
1D8V_S0
R323
R323
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
C585
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
R92
R92
C585
R80
R80
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
C203
C203
VDDPLL
C223
C223
12
C180
C180
SC1U10V3KX-3GP
SC1U10V3KX-3GP
1D8V_S0 3D3V_S0
12
1
3
2
MMBT3904-U1
MMBT3904-U1
Q15
Q15
2ND = 84.03904.T11
2ND = 84.03904.T11
3D3V_S0
12
DY
DY
12
DY
DY
5
12
R69
R69
150R2F-1-GP
150R2F-1-GP
12
SC1U10V2ZY
SC1U10V2ZY
HTPVDD
12
SC1U10V2ZY
SC1U10V2ZY
R87
R87 10KR2F-2-GP
10KR2F-2-GP
C222
C222
12
R72
R72
150R2F-1-GP
150R2F-1-GP
PLVDD
12
12
C202
C202
DY
DY
12
R73
R73
150R2F-1-GP
150R2F-1-GP
12
C578
C578
12
C201
C201 SC1U10V2ZY
SC1U10V2ZY
R84
R84 1KR2J-1-GP
1KR2J-1-GP
NB_LDT_STP#
DY
DY
R83
R83
0R2J-2-GP
0R2J-2-GP
1D8V_S0
12
C571
C571 SC1U10V2ZY
SC1U10V2ZY
1D2V_S0
1 2
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
D4
D4
21
RB751V-40-1-GP
RB751V-40-1-GP
12
12
R76
R76
3D3V_S0
HPB2012ZF-221T30-GP
HPB2012ZF-221T30-GP
R322
R322
0R3-0-U-GP
0R3-0-U-GP
1 2
150R2F-1-GP
150R2F-1-GP
R320
R320
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
12
R75
R75
150R2F-1-GP
150R2F-1-GP
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
12
R74
R74
150R2F-1-GP
150R2F-1-GP
ALLOW_LDTSTOP17
PLLVDD12
C584
C584
690T
BMREQ#_NB
1 2
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
12
C583
C583
GMCH_VSYNC16 GMCH_HSYNC16
Change 0919
HTREF_CLK3
12
R86
R86
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C577
C577
GMCH_DDCCLK16 GMCH_DDCDATA16
NB_PWRGD35
NB_OSC3
TMDS_HPD28
DDC_DAT15
For RS690 designs it is not required to connect BMREQ pin to the BMREQ# pin of SB600. It should be left NC.
4
AVDD
12
C210
C210
SC1U10V2ZY
SC1U10V2ZY
12
C569
C569
AVDDQ
NB_RST#17
PM_SUS_STAT#20,28
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC1U10V2ZY
SC1U10V2ZY
12
12
C199
C199
1D8VAVDDD1_S0
12
C589
C589 SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
R314 715R2F-GPR314 715R2F-GP
1 2
NB_LDT_STP#
NBSRC_CLK3
NBSRC_CLK#3
SBLINK_CLK3
SBLINK_CLK#3
I2C_CLK15
DAT_DDC_EDID15
4K7R2J-2-GP
4K7R2J-2-GP
12
C207
C207
C186
C186
R31210KR2J-3-GP R31210KR2J-3-GP
1 2
R308 0R2J-2-GPR308 0R2J-2-GP
TP58TPAD28 TP58TPAD28 TP59TPAD28 TP59TPAD28 R313
R313
12
0R2J-2-GP
0R2J-2-GP
R307
R307
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
IRSET_NB
HTTST_CLK
12
BMREQ#_NB
THERMAL_P_NB THERMAL_N_NB
TESTMODE_NB
12
R311
R311
12
10KR2J-3-GP
10KR2J-3-GP
B22 C22 G17 H17 A20 B20
A21 A22
C21 C20 D19
E19 F19 G19
C6 A5
B21
B6 A6
A10 B10
B24 B25
E7 F7 F9
G9
C10 C11
C5 B5
C23 B23
C2
B11 A11
F2 E1
G1 G2
B2 A2
B4 AD5 AE5
C14
B3
C3
A3
3D3V_S0
U52C
U52C
RS690T-GP
RS690T-GP
3
AVDD AVDD AVSSN AVSSN AVDDDI AVSSDI
AVDDQ AVSSQ
C Y COMP
RED GREEN BLUE DACVSYNC DACHSYNC
RSET DACSCL
DACSDA PLLVDD18
PLLVSS HTPVDD
HTPVSS
VDD_PLL VDD_PLL VSS_PLL VSS_PLL
SYSRESET# POWERGOOD LDTSTOP# ALLOW_LDTSTOP
HTTSTCLK HTREFCLK
TVCLKIN OSCIN
PLLVDD12 GFX_CLKP
GFX_CLKN SB_CLKP
SB_CLKN BMREQ#
I2C_CLK I2C_DATA THERMALDIODE_P THERMALDIODE_N
TMDS_HPD DDC_DATA TESTMODE STRP_DATA
PART 3 OF 6
PART 3 OF 6
CRT/TVOUT
CRT/TVOUT
PLL PWR
PLL PWR
PM
PM
CLOCKs
CLOCKs
MIS.
MIS.
NB_PWRGD35
TXCLK_LP TXCLK_LN
LPVDD LPVSS
LVDDR33 LVDDR33
LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR
LVSSR LVSSR
B14 B15 B13 A13 H14 G14 D17 E17
A15 B16 C17 C18 B17 A17 A18 B18
E15 D15 H15 G15
D14 E14
A12 B12 C12 C13
A16 A14 D12 C19 C15 C16
F14 F15
E12 G12 F12
D6 D7 C8 C7 B8 A8
TXAOUT3+ TXAOUT3-
Single channel
LVDS_DIGON
LVDS_BLEN_NB
DFT_GPIO0 DFT_GPIO2
DFT_GPIO3 DFT_GPIO4 DFT_GPIO5
TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P
TXOUT_L3N TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_UP TXCLK_UN
LVDDR18D LVDDR18D
LVDS_DIGON
LVDS_BLON LVDS_BLEN
DFT_GPIO0 DFT_GPIO1 DFT_GPIO2 DFT_GPIO3 DFT_GPIO4 DFT_GPIO5
LOAD_ROM#: LOAD ROM STRAP ENABLE
High, LOAD ROM STRAP DISABLE Low, LOAD ROM STRAP ENABLE
2
TP26 TPAD30TP26 TPAD30 TP25 TPAD30TP25 TPAD30
LVDDR33_S0
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
DUMMY?
LOAD_ROM#
DY
DY DY
DY DY
DY DY
DY
3D3V_S5
147
U37A
LVDS_DIGON
GMCH_TXAOUT0+ 15 GMCH_TXAOUT0- 15 GMCH_TXAOUT1+ 15 GMCH_TXAOUT1- 15 GMCH_TXAOUT2+ 15 GMCH_TXAOUT2- 15
GMCH_TXACLK+ 15 GMCH_TXACLK- 15
1D8VLPVDD_S0
LVDDR18D_S0
12
C192
C192
1 2
12
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
12
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
12
C182
C182 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
U37A
3
TSLCX08MTCX-GP
TSLCX08MTCX-GP
C225
C225
C581
C581
C206
C206
GMCH_LCDVDD_ON 15
R90
R90
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
12
C174
C174 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
R321
R321
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
12
C575
C575 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
R85
R85
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
12
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
1D8V_S0 3D3V_S0
Change 0920
TP24 TPAD30TP24 TPAD30
R70 2K7R2J-GP
R70 2K7R2J-GP
1 2
DY
DY
3KR2J-2-GP
3KR2J-2-GPTP29TPAD28 TP29TPAD28
R71
R71
1 2
R78 2K7R2J-GP
R78 2K7R2J-GP
1 2
R317 2K7R2J-GP
R317 2K7R2J-GP
1 2
R315 2K7R2J-GP
R315 2K7R2J-GP
1 2
R316 2K7R2J-GP
R316 2K7R2J-GP
1 2
LAYOUT
LAYOUT
LAYOUT
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
CHECK
DO NOT SUPPORT SIDEPORT MEMORY DO NOT SUPPORT SERIAL STRAP ROM DUMMY IT
NB-RS690M_VIDEO/ CLOCK
NB-RS690M_VIDEO/ CLOCK
NB-RS690M_VIDEO/ CLOCK
A3
A3
A3
Ferrari 7
Ferrari 7
Ferrari 7
GMCH_BL_ON 32
DISABLE DEBUG MODE DUMMY IT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
of
of
of
12 47Thursday, August 02, 2007
12 47Thursday, August 02, 2007
12 47Thursday, August 02, 2007
1
SB
SB
SB
5
D D
4
AD1
AE1
G6
M3
VSSAP9VSSAF3VSSAA1VSSAH1VSSAG3VSSAJ2VSSAH3VSSAJ6VSSAF1VSSAL6VSSAM2VSSAM6VSSAJ3VSSAP6VSSAT1VSSAN3VSSAR6VSSAT2VSSAT3VSSAU3VSSAU6VSSAY1VSSA
VSSA
VSSA
VSSA
VSSA
PAR 5 OF 6
PAR 5 OF 6
VSS
VSS
VSS
VSSE9VSS
VSS
VSS
F11
A25
Y23
P11
D23
R24
G11
VSS
Y7
AA3
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J22
J12
L12
L14
L20
L23
G23
M15
AC18
VSS
M11
VSS
M20
VSS
M23
VSS
M25
VSS
N12
VSS
R9
VSSA
VSS
N14
VSS
VSS
VSS
B7
L24
P13
P20
VSS
3
AE14
A23
F17
M13
VSS
VSS
R23
VSS
VSS
VSSD4VSS
VSSC4VSS
Y12
M17
U52E
U52E
RS690T-GP
RS690T-GP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T23
T25
V11
H23
R17
AE18
AB19
W17
V14
AC10
W6
AA7
AC6
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
P15
Y25
R12
R14
R20
W23
AC12
VSS
GROUND
GROUND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y22
U20
H25
W24
AD25
AC23
D25
VSS
VSS
G24
VSS
VSS
VSS
VSS
VSS
VSS
H12
AA14
AC22
2
1
C C
B B
3D3V_S0
1D2V_S0
L1
L1
1 2
HPB2012ZF-221T30-GP
HPB2012ZF-221T30-GP
A A
VDDA12_PKG1
12
C138
C138
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D2V_S0
1D8V_S0
R324
R324
0R3-0-U-GP
0R3-0-U-GP
1 2
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
1D8V_S0
SC1U10V2ZY
SC1U10V2ZY
12
C530
C530
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
L2
L2
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
12
C574
C574
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
12
C90
C90
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
5
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C91
C91
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
C531
C531
3D3VDDR_S0
12
C587
C587
VDDA_1D2V
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C108
C108
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C94
C94
SC1U10V2ZY
SC1U10V2ZY
12
C533
C533
12
C580
C580
SCD1U16V2ZY-2GP
12
C142
C142
C107
C107
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
12
C99
C99
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC1U10V2ZY
SC1U10V2ZY
12
C87
C87
SC1U10V2ZY
SC1U10V2ZY
12
C205
C205
12
C163
C163
SC1U10V2ZY
SC1U10V2ZY
12
12
C188
C188
SC1U10V2ZY
SC1U10V2ZY
SC1U10V2ZY
SC1U10V2ZY
12
C534
C534
SC1U10V2ZY
SC1U10V2ZY
12
C150
C150
SC1U10V2ZY
SC1U10V2ZY
12
C169
C169
12
C95
C95
TC7
TC7
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC1U10V2ZY
SC1U10V2ZY
12
C88
C88
VDDHT_PKG
SC1U10V2ZY
SC1U10V2ZY
12
C168
C168
ST100U4VBM-10-GP
ST100U4VBM-10-GP
4
12
C92
C92
SC1U10V2ZY
SC1U10V2ZY
12
C110
C110
12
1D8VDD_S0
SC1U10V2ZY
SC1U10V2ZY
12
C101
C101
690T
AE24 AD24 AE25 AE22 AD22 AE23 AD23
D22
E11 D11
AC5
AB3
AB4 AC3 AD2
AE2
AD6 AC7 AC8
AA9 AD7
AB9
AE6
AE8
AE7 AD8
J14 J15
W7
U7
U52D
U52D
RS690T-GP
RS690T-GP
VDD_HT VDD_HT VDD_HT VDD_HT VDD_HT VDD_HT VDD_HT
VDD_HT_PKG
VDD_18 VDD_18
VDDR3 VDDR3
VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12
VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM
PART 4 OF 6
PART 4 OF 6
3
VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12 VDDA_12
VDDA_12 VDDA_12_PKG VDDA_12_PKG
VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE
POWER
POWER
VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE
D1 G7 E2 C1 E3 D2 M9 F4 B1 D3 L9 E6 AD3 M1
L11 L13 L15 M12 R15 M14 N11 N13 N15 J11 H11 P12 P14 R11 R13 A19 B19 U11 U14 P17 L17 J19 D20 G20 A9 B9 C9 D9 A7 A4 U12 U15
12
C158
C158
SC1U10V3KX-3GP
SC1U10V3KX-3GP
VDDA12_PKG2 VDDA12_PKG1
SC1U10V2ZY
SC1U10V2ZY
SC1U10V2ZY
SC1U10V2ZY
12
C135
C135
1D2V_S0
SC1U10V2ZY
SC1U10V2ZY
12
C124
C124
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C140
C140
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C136
C136
SC1U10V2ZY
SC1U10V2ZY
2
SC1U10V2ZY
SC1U10V2ZY
12
C173
C173
SC1U10V2ZY
SC1U10V2ZY
12
12
C123
C123
C198
C198
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C183
C183
C141
C141
VDDA_1D2V
12
C194
C194
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C156
C156
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
???
SC1U10V2ZY
SC1U10V2ZY
SC1U10V2ZY
SC1U10V2ZY
SC1U10V2ZY
SC1U10V2ZY
12
C112
C112
LAYOUT
LAYOUT
LAYOUT
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
SC1U10V2ZY
12
C118
C118
12
C244
C244
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
NB-RS690M_POWER
NB-RS690M_POWER
NB-RS690M_POWER
SC1U10V2ZY
12
C117
C117
12
12
C209
C209
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
Ferrari 7
Ferrari 7
Ferrari 7
12
C131
C131
C151
C151
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
of
of
of
13 47Thursday, August 02, 2007
13 47Thursday, August 02, 2007
13 47Thursday, August 02, 2007
1
SB
SB
SB
5
D D
12
R40
R40 HPB2012ZF-221T30-GP
HPB2012ZF-221T30-GP
C55
C55
1 2
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
MEM_VDDQ
C C
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12
ODT MEM_CLKP MEM_CLKN CKE CS# RAS# CAS# WE#
MEM_DM0 MEM_DM1 MEM_BA0 MEM_BA1
B B
MEM_DQS0P MEM_DQS1P MEM_DQS0N MEM_DQS1N
R8
A0
R3
A1
R7
A2
T2
A3
T8
A4
T3
A5
T7
A6
U2
A7
U8
A8
U3
A9
R2
A10
U7
A11
V2
A12
N9
ODT
M8
CK
N8
CK#
N2
CKE
P8
CS#
N7
RAS#
P7
CAS#
N3
WE#
J3
LDM
E3
UDM
P2
BA0
P3
BA1
2ND = HYNIX 32M*16 72.51216.F0U; 72.18512.M0U Qimonda 32M*16
2ND = HYNIX 32M*16 72.51216.F0U; 72.18512.M0U Qimonda 32M*16
V1
VDDD1VDDH1VDDM9VDDR9VDD
VDDQD9VDDQF1VDDQF3VDDQF7VDDQF9VDDQH9VDDQK1VDDQK3VDDQK7VDDQ
LDQSJ7LDQS#/NUH8UDQS#/NU
VSSDLM7VSSQD7VSSQE2VSSQE8VSSQG2VSSQG8VSSQH7VSSQJ2VSSQJ8VSSQL2VSSQ
UDQS
E7
D8
VSSD3VSSH3VSSM3VSST1VSS
MEM_BA2
MEM_VDDL
K9
V7
M1
VDDL
RFU#P1P1RFU#V3V3RFU#V7
U9
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
MEM_VREF_CHIP
M2
VREF
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
NC#V8 NC#H2 NC#D2
NC#AA9
NC#A1 NC#A2 NC#A8
NC#A9 NC#AA1 NC#AA2 NC#AA8
L8
MT47H64M16BT-37E-GP
MT47H64M16BT-37E-GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
U22
U22
DATA SWAP
K8 K2 L7 L3 L1 L9 J1 J9
MEM_DQ11
F8
MEM_DQ14
F2
MEM_DQ10
G7
MEM_DQ15
G3
MEM_DQ12
G1 G9
MEM_DQ13
E1 E9
V8 H2 D2 AA9 A1 A2 A8 A9 AA1 AA2 AA8
CLOSE TO MEMORY
12
C496
C496
C497
C497
1 2
MEM_DQ1 MEM_DQ3 MEM_DQ2 MEM_DQ0 MEM_DQ6 MEM_DQ4 MEM_DQ7 MEM_DQ5
MEM_DQ9 MEM_DQ8
MEM_A13
4
MEM_CLKP MEM_CLKN
SRN1KJ-7-GP
SRN1KJ-7-GP
4
MEM_A2 MEM_A11 MEM_A6 MEM_A4
MEM_BA1 CKE MEM_A10 CAS#
MEM_A1 MEM_A5 MEM_A7 MEM_A12
MEM_A3 MEM_A8 MEM_A9 MEM_A13
MEM_A0 CS#
ODT
RAS# WE# MEM_BA0 MEM_BA2
MEM_VDDQ
RN40
RN40
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13
MEM_BA0 MEM_BA1 MEM_BA2
RAS# CAS# WE# CS#
CKE ODT
R295 68R2F-GPR295 68R2F-GP
1 2
MEM_DM0 MEM_DM1
MEM_DQS0P MEM_DQS0N MEM_DQS1P MEM_DQS1N
23 1
RN46
RN46
1
8
2
7
3
6
4 5
SRN47J-4-GP
SRN47J-4-GP
RN43
RN43
1
8
2
7
3
6
4 5
SRN47J-4-GP
SRN47J-4-GP
RN41
RN41
1
8
2
7
3
6
4 5
SRN47J-4-GP
SRN47J-4-GP
RN44
RN44
1
8
2
7
3
6
4 5
SRN47J-4-GP
SRN47J-4-GP
RN47
RN47
1
8
2
7
3
6
4 5
SRN47J-4-GP
SRN47J-4-GP
RN42
RN42
1
8
2
7
3
6
4 5
SRN47J-4-GP
SRN47J-4-GP
0D9V_S0
U52F
U52F
PAR 6 OF 6
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13
MEM_BA0 MEM_BA1 MEM_BA2
MEM_RAS# MEM_CAS# MEM_WE# MEM_CS#
MEM_CKE MEM_ODT
MEM_CKP MEM_CKN
MEM_DM0 MEM_DM1
MEM_DQS0P MEM_DQS0N MEM_DQS1P MEM_DQS1N
RS690T-GP
RS690T-GP
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
PAR 6 OF 6
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
MEM_VDDQ
C499
C499 C480
C480
C523
C523 C521
C521
C486
C486 C493
C493
C483
C483 C514
C514
C482
C482 C516
C516
C479
C479 C485
C485
W12
AD10
AB12 AB11
W14 AB15 AB14
AE9 AA12
AC9 AE10
Y14
AD9 AA11
AC11
AE11
AD11
AA15
Y15
AC14
V12
AD12
Y9
W15
V15
AC16 AD19
AE17
AD17 AD21 AC20
3
MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8
MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15
MEM_COMPP MEM_COMPN
MEM_VREF
IOPLLVDD18
IOPLLVSS
IOPLLVDD12
AD13 AE13 AC13 AD14 AC15 AD15 AE15 AE16 AD16 AC17 AD18 AE19 AC19 AE20 AD20 AE21
Y11 W11 AE12 AA17 Y17 AB17
MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8
MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15
MEM_COMPP MEM_COMPN
V_IOPLLVDD_18
V_IOPLLVDD_12
TC4
TC4
TC5
TC5
MEM_VDDQ
R66 40D2R2F-GPR66 40D2R2F-GP
1 2
R67 40D2R2F-GPR67 40D2R2F-GP
1 2
MEM_VREF_NB
R63
R63
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
12
C93
C93
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
12
12
C77
C77
SC10U10V5ZY-1GP
12
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C80
C80
C52
C52
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
ST100U4VBM-10-GP
ST100U4VBM-10-GP
0D9V_S0
ST100U4VBM-10-GP
ST100U4VBM-10-GP
12
C535
C535
SCD1U16V2KX-3GP
4
MEM_VDDQ
12
C103
C103
C511
C511
1 2
1 2
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C481
C481
1 2
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C536
C536 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
R64
R64
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
R42
R42
1 2
HPB2012ZF-221T30-GP
HPB2012ZF-221T30-GP
C517
C517
SRN1KJ-7-GP
SRN1KJ-7-GP
2 3 1
RN49
RN49
68.00082.311 300ohmȍ/100MHz, 0.25ȍ,0.5A
1D2V_S0
12
C68
C68
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C484
C484
1 2
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1D8V_S0
1D8V_S0MEM_VDDQ
2
1
A A
LAYOUT
LAYOUT
LAYOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
NB-RS690T SIDE PORT
NB-RS690T SIDE PORT
NB-RS690T SIDE PORT
Ferrari 7
Ferrari 7
Ferrari 7
1
of
14 47Thursday, August 02, 2007
of
14 47Thursday, August 02, 2007
of
14 47Thursday, August 02, 2007
SB
SB
SB
LCDVDD 3D3V_S0
R195
R195
LCDVDD_ON_1
GMCH_LCDVDD_ON12
FRONT_PWRLED32
E-BUTTON_LED32
1 2
0R2J-2-GP
0R2J-2-GP
Q21
Q21
GND
GND
2
R2
R2
IN
IN
1
CHDTC143ZUPT-GP
CHDTC143ZUPT-GP
2ND = 84.00143.D1K
2ND = 84.00143.D1K
Q22
Q22
GND
GND
2
R2
R2
IN
IN
1
CHDTC143ZUPT-GP
CHDTC143ZUPT-GP
2ND = 84.00143.D1K
2ND = 84.00143.D1K
R1
R1
R1
R1
OUT
OUT
3
84.00143.B1K
84.00143.B1K
OUT
OUT
3
84.00143.B1K
84.00143.B1K
SC1U16V3ZY-GP
SC1U16V3ZY-GP
12
R193
R193
1 2
C419
C419
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
R192
R192
1 2
E-BUTTON_LED_R#
68R2-GP
68R2-GP
12
C420
C420
1 2 3 4
FRONT_PWRLED#_R
68R2-GP
68R2-GP
LED2
LED2
LED1
LED1
U46
U46
IN#1
GND OUT EN GND
G5281RC1U-GP
G5281RC1U-GP
LED-W-23-GP
LED-W-23-GP
AK
LED-W-23-GP
LED-W-23-GP
AK
9 8
IN#8
7
IN#7
6
IN#6
5
IN#5
LED5
LED5
LED6
LED6 LED4
LED4
LED3
LED3
5V_S0
LED-W-23-GP
LED-W-23-GP
AK
LED-W-23-GP
LED-W-23-GP
AK
LED-W-23-GP
LED-W-23-GP
AK
LED-W-23-GP
LED-W-23-GP
AK
SC1U16V3ZY-GP
SC1U16V3ZY-GP
12
C418
C418
3D3V_S0
SRN2K2J-1-GP
SRN2K2J-1-GP
2K2R2J-2-GP
2K2R2J-2-GP
RN3
RN3
R471
R471
3D3V_S0
3D3V_S0
1
23
4
12
SB
TMDS_DDC_DAT 28
TMDS_DDC_CLK 28
5V_S0
12
C7
C7 SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
USB_6­USB_6+
BLON_OUT
DY
DY
SC100P50V2JN-3GP
SC100P50V2JN-3GP
CCD_PWR
12
12
C4
C4 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SRN0J-6-GP
SRN0J-6-GP
2 3 1
RN39
RN39
C421
C421
SC100P50V2JN-3GP
SC100P50V2JN-3GP
F2
F2
1 2
U3
U3
POLYSW-1A6V-3-GP
POLYSW-1A6V-3-GP
1 2
G5240B1T1U-GP
G5240B1T1U-GP
DY
DY
OUT GND NC#33EN
5
IN
4
12
EC126
EC126 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
CCD_ON 32
R1
DDC_CLK
I2C_CLK12
DAT_DDC_EDID12
1 2
0R2J-2-GPR10R2J-2-GP
SC
USBPN6 20
4
USBPP6 20
SB
BRIGHTNESS 32
10KR2J-3-GP
12
C422
C422
DY
DY
10KR2J-3-GP
BLON_OUT 32
12
R194
R194
DDC_DAT12
DDC_CLK
R241
R241
1 2
0R2J-2-GP
0R2J-2-GP
R242
R242
1 2
0R2J-2-GP
0R2J-2-GP
LVDS TMDS
Internal Microphone
DMIC_CLK30 DMIC_1230
SB
3D3V_S0
12
12
DY
DY
DY
DY
MLVG0402220NV09BP-GP
MLVG0402220NV09BP-GP
MLVG0402220NV09BP-GP
MLVG0402220NV09BP-GP
EC38
EC38
EC40
EC40
I2C_CLK
I2C_DATA
DDC_DATA
3D3V_S0
DDC_CLK DAT_DDC_EDID
BRIGHTNESS BL_5SW
SB
LCDVDD
12
C3
C3
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
GMCH_TXAOUT0- 12 GMCH_TXAOUT0+ 12 GMCH_TXAOUT1- 12 GMCH_TXAOUT1+ 12
GMCH_TXAOUT2- 12 GMCH_TXAOUT2+ 12
GMCH_TXACLK- 12 GMCH_TXACLK+ 12
12
12
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
EC127
EC127
C423
C423
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
Single channel
SC
5V_S0
LCD/INVERTER CONN
LCD1
LCD1
41
1
USB_6+ USB_6­CCD_PWR
TP105
TP105
TPAD30
TPAD30
SB
SC1U16V3ZY-GP
SC1U16V3ZY-GP
C462
C462
12
DCBATOUT
SC
BLON_OUT
F1
F1
C2
1 2
12
12
EC1
EC1
FUSE-4A32V-6-GP
FUSE-4A32V-6-GP
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
SB
SB
SC10U25V6KX-1GPC2SC10U25V6KX-1GP
SC
40 39422
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
ACES-CONN40C-GP-U
ACES-CONN40C-GP-U
SB
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
I2C_CLK I2C_CLK
I2C_DATA
DDC_DATA
SB
U64
U64
1
OUT
IN
2
GND NC#33EN
G5240B1T1U-GP
G5240B1T1U-GP
2ND = 74.09711.A7F
2ND = 74.09711.A7F
5
BLON_OUT
4
12
C712
C712 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
LAYOUT
LAYOUT
LAYOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LCD CONN & LED
LCD CONN & LED
LCD CONN & LED
Ferrari 7
Ferrari 7
Ferrari 7
15 47Thursday, August 02, 2007
15 47Thursday, August 02, 2007
15 47Thursday, August 02, 2007
SB
SB
SB
of
of
of
SC
DY
DY
BL_5SW
12
12
C711
C711
EC128
EC128
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C710
C710 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
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