Acer F1725 Schematic

SERVICE MANUAL

SPECTRUM Series

LCD Monitor

F1725

THESE DOCUMENTS ARE FOR REPAIR SERVICE INFORMATION ONLY. EVERY REASONABLE
EFFORT HAS BEEN MADE TO ENSURE THE ACCURACY OF THIS MANUAL; WE CANNOT
GUARANTEE THE ACCURACY OF THIS INFORMATION AFTER THE DATE OF PUBLICATION
AND DISCLAIMS RE LIABILITY FOR CHANGES, ERRORS OR OMISSIONS,

MANUFACTURE DATE : 2004-2-11

TABLE OF CONTENTS

1. SPECIFICATIONS .................................................................................….…...……….. 3

1-1 GENERALSPECIFICATIONS .…................................................………………... 3

1-2 LCD MONITOR DESCRIPTION ....................................................………….…... 4

1-3 INTERFACE CONNECTOR ......................................................…………………. 4

2. PRECAUTION AND NOTICES ................................................................……………..... 5

2-1 ASSEMBLY PRECAUTION ............................................................…………….... 5

2-2 OPERATIONG PRECAUTION .....................................................……………...... 5

2-3 STORAGE PRECAUTION …...................................................……………........... 5

2-4 HIGH VOLTAGE WARNING .......................................................……………....... 5

3. OPERATING INSTRUCTIONS ..................................................................……………... 6

4. ADJUSTMENT .....................................................................................……………......... 7

4-1 ADJUSTMENT CONDITIONS AND PRECAUTIONS ..............………………....... 7

4-2 FRONT PANEL CONTROL KNOBS .........................................………………...... 9

5. CIRCUIT & SOFTWARE DESCRIPTION .............……………………………………..….. 10

5-1 THE DIFFERENT BETWEEN EACH PANEL …………………………………..….. 10

5-2 SIMPLE-INTRODUCTION………………………..…………………………………... 11

5-3 SOFTWARE FLOW-CHART……………………………………………………..….... 13

6. A). INTERFACE-BOARD TROUBLE SHOOTING CHART ..................……………..…... 15

B). INVERTER - MODULE TROUBLE SHOOTING CHART ..................……………...… 22

C). ADAPTER TROUBLE SHOOTING CHART………......………………………………... 34

D). Main-chip GMZAN2 SPECFICATION…………………………………………………….. 35

7. MECHANICAL OF CABINET FRONT DIS-ASSEMBLY....................……………............ 61

8. PARTS LISTING .....................................................................................……………...… 62-76

9. POWER SYSTEM AND CONSUMPTION CURRENT...............................…………….... 76

10. PCB LAYOUT .....................................................................…………………………..….. 77

11. SCHEMATIC ………………………………...…...........................................……………..… 78-82

Page 2 of 82

1. SPECIFICATIONS FOR LCD MONITOR

1-1 General specifications

1. LCD-PANEL :
Active display area 17 inches diagonal

Pixel pitch 0.264 mm x 0.264 mm
Pixel format 1280 x 1024 RGB vertical stripe arrangement

2. Display Color : 8-bit, 16.7 million colors

3. External Controls :Power On/Off, Auto key, Left key, Right key ( for 4-key )
OSD menu Controls: Contrast, Brightness, Focus, Clock, H-position, V-position, Language,
Recall-7800, Recall-6500, Reset,
Exit-OSD, Red, Green, Blue, Selected Dos-resolution

4. Input Video Signal :
Analog-signal 0.7Vpp

Video signal termination impedance 75 OHM

5. Scanning Frequencies :
Horizontal: 29 KHz - 80 KHz
Vertical: 55 Hz – 75 Hz
Pixel clock: 135 MHz

6. Factory Preset Timing : 18
User Timings : 19
Input signal tolerance : H tolerance ±1 K, V tolerance ±1 Hz

7. Power Source :
Switching Mode Power Supply
AC 100 – 240 V, 50/60 Hz Universal Type

8. Operating Temperature : 0℃ - 50℃ Ambient

Non-operating Temperature : -20℃ - 60℃

9. Humidity :

Operating : 20% to 80% RH (non-condensing)
Non Operating : 5% to 95%RH (38.7℃ maximum wet bulb temperature)

10. Weight : 5.5 kg

11. External Connection : 15Pin D-type Connector, AC power-Cord

12. View Angle : x-axis right/left = 60, y-axis up/down = 40 ,60

13. Outside dimension : Width x Height x Thickness = 422x 449 x 215 mm

14. Plug and Play : VESA DDC1/DDC2B

15. Power saving : VESA DPMS

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1-2 LCD MONITOR DESCRIPTION

The LCD MONITOR will contain an main board, an Inverter module, keyboard and External
Adapter which house the flat panel control logic, brightness control logic, DDC and DC-DC
conversion
The Inverter module will drive the backlight of panel .
The Adapter will provides the 12V DC-power 5 Amp to Main-board and Inverter module .

Monitor Block Diagram

CCFL Drive.

Flat Panel and
CCFL backlight

Inverter

Main Board

Adapter

Keyboard

RS232 Connector
For white balance

adjustmen
factory mode

Video signal, DDC

t in

1-3 Interface Connectors

(A) AC-Power Cable
(B) Video Signal Connectors and Cable
(C) External Adapter

AC-IN
100V-240V

HOST Computer

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2. PRECAUTIONS AND NOTICES

2-1 ASSEMBLY PRECAUTION

(1) Please do not press or scratch LCD panel surface with anything hard. And do not soil LCD

panel surface by touching with bare hands (Polarizer film, surface of LCD panel is easy to
be flawed)

In the LCD panel, the gap between two glass plates is kept perfectly even to maintain

display characteristic and reliability. If this panel is subject to hard pressing, the following

occurs :
(a) Uniform color (b) Orientation of liquid crystal becomes disorder
(2) Please wipe out LCD panel surface with absorbent cotton or soft cloth in case of it being

soiled.
(3) Please wipe out drops of adhesive like saliva and water in LCD panel surface immediately.

They might damage to cause panel surface variation and color change.
(4) Do not apply any strong mechanical shock to the LCD panel.

2-2 OPERATING PRECAUTIONS

(1) Please be sure to unplug the power cord before remove the back-cover. (be sure the power

is turn-off)
(2) Please do not change variable resistance settings in MAIN-BOARD, they are adjusted to

the most suitable value. If they are changed, it might happen LUMINANCE does not satisfy

the white balance spec.
(3) Please consider that LCD backlight takes longer time to become stable of radiation

characteristic in low temperature than in room temperature.
(4) Please pay attention to displaying the same pattern for very long-time. Image might stick on

LCD.

2-3 STORAGE PRECAUTIONS

(1) When you store LCD for a long time, it is recommended to keep the temperature between 0

℃-40℃ without the exposure of sunlight and to keep the humidity less than 90% RH.

(2) Please do not leave the LCD in the environment of high humidity and high temperature

such as 60℃ 90%RH.

(3) Please do not leave the LCD in the environment of low temperature; below -15℃.

2-4 HIGH VOLTAGE WARNING

The high voltage was only generated by INVERTER module, if carelessly contacted the
transformer on this module, can cause a serious shock. (the lamp voltage after stable around
600V, with lamp current around 8mA, and the lamp starting voltage was around 1500V, at
Ta=25℃)

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3. OPERATING INSTRUCTIONS

This procedure gives you instructions for installing and using the LM700 LCD monitor display.

1. Position the display on the desired operation and plug–in the power cord into External

Adapter AC outlet. Three-wire power cord must be shielded and is provided as a safety
precaution as it connects the chassis and cabinet to the electrical conduct ground. If the AC
outlet in your location does not have provisions for the grounded type plug, the installer
should attach the proper adapter to ensure a safe ground potential.

2. Connect the 15-pin color display shielded signal cable to your signal system device and

lock both screws on the connector to ensure firm grounding. The connector information is
as follow:

PIN NO.

1. RED 9. 5V power from VGA-card

2. GREEN 10. GND

3. BLUE 11. SYNC. GND

4. GND 12. SDA

5. GND 13. HORIZ. SYNC

6. GND-R 14. VERT. SYNC

7. GND-G 15. SCL

8. GND-B

DESCRIPTION

1

6

11 15

15 - Pin Color Display Signal Cable

5

10

PIN NO.

DESCRIPTION

3. Apply power to the display by turning the power switch to the "ON" position and allow about

thirty seconds for Panel warm-up. The Power-On indicator lights when the display is on.

4. With proper signals feed to the display, a pattern or data should appear on the screen,

adjust the brightness and contrast to the most pleasing display, or press auto-key to get the
best picture-quality.

5. This monitor has power saving function following the VESA DPMS. Be sure to connect the

signal cable to the PC.

6. If your F1725 LCD monitor requires service, it must be returned with the power cord &

Adapter.

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4. ADJUSTMENT

4-1 ADJUSTMENT CONDITIONS AND PRECAUTIONS

Adjustments should be undertaken only on following function : contrast, brightness focus, clock,
h-position, v-position, red, green, blue since 6500 color & 7800 color.

4-2 ADJUSTMENT METHOD

Press MENU button to activate OSD Menu or make a confirmation on desired function, Press
Left/Right button to select the function or done the adjustment.

1. White-Balance, Luminance adjustment

Approximately 30 minutes should be allowed for warm up before proceeding white balance

adjustment.

1.How to do the Chroma-7120 MEM .Channel setting

A、Reference to chroma 7120 user guide

B、Use “ SC” key and “ NEXT” key to modify xyY value and use “ID” key to modify the

TEXT description Following is the procedure to do white-balance adjust

2、Setting the color temp. You want

A、MEM.CHANNEL 3 C2 ( 7800 color):

7800 color temp. parameter is x = 296 ±10, y = 311 ±10, Y = 200 ±10 cd/m

B、MEM.CHANNEL 4 C1 ( 6500 color):

6500 color temp. parameter is x = 313±10, y = 329 ±10, Y =200 ±10 cd/m2)

3、Into factory mode of F1725

A、Press MENU button during 2 seconds along with press Power button will activate the

factory mode, then MCU will do AUTO LEVEL automatically. Meanwhile press MENU
the OSD screen will located at LEFT TOP OF PANEL.

4、Bias adjustment :

2 ,

Set the Contrast

Adjust the Brightness

to 70

to 90.

5、Gain adjustment :

Move cursor to “-F-” and press MENU key
A、Adjust C2(7800) color-temperature

1、Switch the Chroma-7120 to RGB-Mode (with press “MODE” button )

2、Switch the MEM. channel to Channel 3 ( with up or down arrow on chroma 7120 )

3、The LCD-indicator on chroma 7120 will show x = 296 ±10, y = 311 ±10,

Y = 200 ±10 cd/m2

4、Adjust the RED of color1 on factory window until chroma 7120 indicator reached

the value R=100

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5、Adjust the GREEN of color1 on factory window until chroma 7120 indicator reached

the value G=100

6、Adjust the BLUE of color1 on factory window until chroma 7120 indicator reached

the value B=100

7、Repeat above procedure ( item 4,5,6) until chroma 7120 RGB value meet the

tolerance =100±2

B、Adjust C1(6500) color-temperature

1、Switch the chroma-7120 to RGB-Mode (with press “MODE” button )

2、Switch the MEM .channel to Channel 4( with up or down arrow on chroma 7120 )

3、The LCD-indicator on chroma 7120 will show x = 313 ±10, y = 329 ±10,

Y = 200 ±10 cd/m

2

4、Adjust the RED of color3 on factory window until chroma 7120 indicator reached

the value R=100

5、Adjust the GREEN of color3 on factory window until chroma 7120 indicator reached

the value G=100

6、Adjust the BLUE of color3 on factory window until chroma 7120 indicator reached

the value B=100

7、Repeat above procedure ( item 4,5,6) until chroma 7120 RGB value meet the

tolerance =100±2

C、Press reset key and Turn the Power-button “off to on” to quit from factory mode.

2. Clock adjustment

Set the Chroma at pattern 63 (cross-talk pattern) or WIN98/95 shut-down mode (dot-

pattern).

Adjust until the vertical-Stripe-shadow as wide as possible or no visible.

This function is adjust the PLL divider of ADC to generate an accurate pixel clock

Example : Hsyn = 31.5KHz Pixel freq. = 25.175MHz (from VESA spec)

The Divider number is (N) = (Pixel freq. x 1000)/Hsyn

From this formula, we get the Divider number, if we fill this number in ADC register (divider

register), the PLL of ADC will generate a clock which have same period with above Pixel

freq.(25.175MHz) the accuracy of this clock will effect the size of screen.(this clock was

called PIXEL-CLOCK)

3. Focus adjustment

Set the Chroma at pattern 63 (cross talk pattern) or WIN98/95 shut down mode (dot-

pattern).

Adjust the horizontal interference as less as possible

This function is adjust the phase shift of PIXEL-CLOCK to acquire the right pixel data .

If the relationship of pixel data and pixel clock not so match, we will see the horizontal

interference on screen ,we only find this phenomena in crosstalk pattern or dot pattern ,

other pattern the affect is very light

4. H/V-Position adjustment

Set the Chroma to pattern 1 (crosshatch pattern) or WIN98/95 full-white pattern confirm

above item 2 & 3 functions (clock & focus) was done well, if that 2 functions failed, the H/V

position will be failed too. Adjust the four edge until all four-edges are visible at the edge of

screen.

5. MULTI-LANGUAGE function

There have 5 language for selection, press “MENU” to selected and confirm , press “ LEFT”

or “ RIGHT” to change the kind of language ( English , Deutch , Francais, Espanol, Italian)

6. Reset function

Clear each old status of auto-configuration and re-do auto-configuration ( for all mode)

This function also recall 7800 color-temperature , if the monitor status was in “ Factory-

mode” this reset function will clear Power-on counter ( backlight counter) too.

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7. OSD-LOCK function

Press Left & Right key during switching on the monitor, the access to the OSD is locked,

user only has access to “ Contrast, Brightness, Auto-key “.

If the operator pressed the Left & Right during switching on the monitor again , the OSD is

unlocked.

8. View Power-on counter and reset the Power-on counter( if not necessary , no suggest to

entry factory mode)

The Power-on counter was used to record how long the backlight of panel already working,

the backlight life time was guarantee minimal 25000 hours, the maintainer can check the

record only in factory mode.

Press MENU button for 2 seconds along with plug-in DC power cord will be in factory mode,

and the OSD screen will located at left top of panel but take cautions don’t press icon “78”

& “65”, if you press 78/65 , your white-balance data will overlap with the new-one, and you

must perform the white-balance process again.

The result of counter was place at top of OSD, the maximal of record memory was 65000

hours, if exceed 65000 hours the counter will keep in 65000 hours until press “ RESET” at

osd-menu in factory mode.

The “ RESET” function in factory mode will execute following function:

1. clear the Power-on counter to zero hours

2. clear old auto-configuration status for all mode , so the monitor will automatically re-do
auto-config when change to next mode or power on-off

4-2 FRONT PANEL CONTROL KNOBS

Power button : Press to switch on or switch off the monitor.
Auto button : to perform the automatic adjustment from CLOCK, FOCUS, H/V POSITION, but no

affect the color-temperature
Left/Right button : select function or do an adjustment.
MENU button : to activate the OSD window or to confirm the desired function

5.CIRCUIT-DESCRIPTION

5-1 SPECIAL FUNCTION with PRESS-KEY

A). press Menu button during 2 seconds along with plug-in the DC Power cord:

That operation will set the monitor into “Factory- mode”, in Factory mode we can do the
White balance adjustment with RS232 , and view the Backlight counter (this counter is use to
record the panel activate hours ,for convenient the maintainer to check the panel backlight
life time)
In Factory mode, OSD-screen will locate in left top of screen.
Press POWER-button off to on once will quit from factory mode and back to
user-mode.

B). Press both Left & Right button along with Power button off to on once will activate the

OSD-LOCK function, repeat this procedure will disable OSD-LOCK
In OSD-LOCK function, all OSD function will be lock , except Contrast and Brightness

OSD-INDEX EXPLANATION

1. CABLE NOT CONNECTED: Signal-cable not connected.

2. INPUT NOT SUPPORT:
a. INPUT frequency out of range: H > 81kHz, v > 75Hz or H < 28kHz, v < 55Hz
b. INPUT frequency out of VESA-spec. (out of tolerance too far)

3. UNSUPPORT mode, try different Video-card Setting:
Input frequency out of tolerance, but still can catch-up by our system (if this message show,
that means, this is new-user mode, AUTO-CONFIG will disable)

Page 9 of 82

5-2 SIMPLE-INTRODUCTION

1. GMZAN2 ( all-in-one chip solution for ADC, OSD, scalar and interpolation) :
USE for computer graphics images to convert analog RGB data to digital data with
interpolation process, zooming, generated the OSD font , perform overlay function and
generate drive-timing for LCD-PANEL.

2. M6759 (ALI- MCU, type 8052 series with 64k Rom-size and 512 byte ram) :
Use for calculate frequency, pixel-dot , detect change mode, rs232-communication, power­consumption control, OSD-index warning , …etc.

3. 24LC21 (MicroChip IC) :
EEPROM type, 1K ROM-SIZE, for saving DDC-CONTENT.

4. 24C04 (ATMEL IC) :
EEPROM type, 4K ROM-SIZE, for saving AUTO-config data, White-balance data, and
Power-key status and Backlight-counter data.

5. LM2569S( NS brand switching regulator 12V to 5V with 3A load current) .

6. AIC 1084-33CM (AIC brand linear regulator 5V to 3.3V)

7. LVDS ( use NOVATEK NT7181F)

Convert the TTL signal to LVDS signal
The advantage of LVDS signal is : the wire can be lengthen and eliminate wire number , low
EMI .

LVDS signal is high frequency but low voltage, only 0.35 VPP ,the frequency is seven times
higher than TTL

MODULE-TPYE COMPONENT :

1. ADAPTER : CONVERSION-module to convert AC 110V-240V to 12VDC, with 5.0 AMP

2. INVERTER : CONVERSION-module to convert DC 12V to High-Voltage around 1600V, with
frequency 30K-80Khz, 7mA-9Ma

Page 10 of 82

Input analog RGB &
H,V,& ddc signal &
Rs232 communication

DDC-chip

DC 12V 5Amp

EXTERNAL­ADAPTER

GMZAN1 (U200)

Oscillator 50 mhz

MCU ( U302 )

Main-board Block diagram

Communication signal:
Hclk,Hfs,Hdata0

Keyboard module

Data Digital RGB

Panel Control Signal:
Dhs, Dvs, Dclk

Crystal 20 mhz

LVDS chip (U601,
U602)

Panel Power 5V

Panel-Power Control
(U202)

INVERTER module

PANEL

Page 11 of 82

5-3 SOFTWARE FLOW CHART

I. Power-On Subrotine CHART

Page 12 of 82

II. MAIN SUBROTINE LOOP

Main loop start

Process Power-saving status ( according to below flow-chart result)

Check GMZAN IFM status .is change or not.
And check Signal cable status ( cable not connected or not )
** IFM is the register which measured the HSYN & Vsyn status

Yes, IFM have change

Is current system status in Power-saving ?

Check the IFM result is in the standard
Mode table ?

Check the IFM result is in the user mode
table ?

Out of range ( input not support) be
confirm

confirm the frequency ( Hsyn or Vsyn) from IFM already

been changed ? ( check the change mode flag)

Process ( turn off OSD , setting GMZAN1according to
above parameter,set LED status, set backlight status)

Check Auto-config mode flag already been set?

Read Key status and Process on OSD-screen

Check Factory mode flag= 1

Monitoring the time-out of osd status ( if no key input persist for
10 sec , the osd time-out counter will trigger )

)

Wake-up GMZAN1
(because GMZAN1 was in
partial sleeping state)

Set mode index & parameter
Set change mode flag

Do Auto-config
automatically

if the RS232 buffer is full,
process the command( while
adjust white-balance in factory
mode)

Page 13 of 82

6. A). Interface-Board Trouble-Shooting chart

*Use the PC Win 98 white pattern, with some icon on it, and Change the Resolution to 640x480 60 Hz / 31

KHz

**NOTICE : The free-running freq. of our system is 48 KHz / 60 Hz, so we recommend to use another

resolution to do trouble shooting, this trouble shooting is proceed with 640x480 @60Hz 31Khz

I. NO SCREEN APPEAR

DC-Power Part

Page 14 of 82

Page 15 of 82

II (a) THE SCREEN is Abnormal , stuck at white screen, OSD window can’t
appear, but keyboard & LED was normal operation.

At general, this symtom is cause by missing panel data or panel power, so we must
check our wire-harness which connected to panel or the panel power controller
(U202)

Page 16 of 82

II. (b)The screen had the Vertical Straight Line, might be stuck in Red, Green, Blue

That symptom is cause by bad Panel issue ( might be the Source IC from Panel is cold
solder or open loop ) so REPLACE THE PANEL TO NEW ONE.

Page 17 of 82

p

POWER-BLOCK check

**Note : the Waveform of U304 pin 2 can determined the power situation

1. stable rectangle waveform with equal duty, freq around 150K-158KHz
that means all power of this interface board is in normal operation
,and all status of 5V & 3.3V is working well

2. unstable or uneven rectangle waveform without same duty, that means
ABNORMAL operation was happened, check 3.3V or 5V ,if short-circuit or bad
component

3. rectangle waveform with large spike & harmonic pulse on front side , means all

3.3v is no load, U200 GmZAN2 was shut-down, and only U302 MCU still
working , that means the monitor is in power saving status , all power system is
working well .

Measure input power at U304 LM2596 pin 1=
12V ?

NG

Check ADAPTER and connector if loose?

Check U304 pin 2 is a stable rectangle wave?
Around 150k-158kHz stable rectangle wave
with equal duty without any spike or harmonic
pulse?

The interface board power is good

NG

Check U304 pin 2 is a unstable rectangle wave ?

OK, unstable wave

Check all 3.3V & 5V power, there is
short circuit or bad component was
happened

The interface board is in power­saving state, press power key to wake
up & check your signal input

NG, with
harmonic

ulse

Page 18 of 82

pei)

III.ALL SCREEN HAS INTERFERENCES OR NOISE, CAN’T BE FIXED BY AUTO KEY

** NOTE: There is so many kind of interferences, 1). One is cause by some VGA-CARD

that not meet VESA spec or power grounding too bad that influence our circuit

2).other is cause by external interferences, move the monitor far from electronic
equipment.( rarely happened)

Use DOT-pattern, or win98/99 shut-down
mode pattern, press “AUTO” key, was the
interferences disappear ??

Adjust “FOCUS” step by step, until the
horizontal interferences disappear

Does your signal-cable have an additional
cable for extension ??

Does your noise only exist in one mode only?
(ex: only at 1280x1024 @ 75 Hz, other is normal)

That was cause by you VGA-CARD setting, your VGA
card timing backporch/frontporch exceed vesa timing too
far, for some new AGP-VGA-CARD such situation
always happened
So in your control-panel icon ,select monitor ,setting ,

advance ,screen-adjust,at
Size icon, increase step by step slowly, press “”AUTO”

key every step you increase the SIZE . repeat the
procedure( increase/decrease SIZE one-step and press
AUTO) until the interferences disappear, press “APPLY”
to save in your VGA

NO additional extension cable

Yes, only happened on one mode

Yes, has extension

END

END

Put away the additional cable
May be the additional cable grounding is
not quite well

Change the Signal-cable to new-one or
Try other brand VGA-CARD
(make sure just only that brand VGA­CARD has this problem ,contact RD­tai

Page 19 of 82

There is an interferences in DOS MODE
NOTE :the criteria of doing AUTO-CONFIGURATION : must be a full-size screen, if the
screen not full , the auto-configuration will fail. So in dos mode ,just set your “CLOCK” in
OSD-MENU to zero or use some EDITOR software which can full fill the whole screen
(ex: PE2, HE) and then press “AUTO” Or you can use “DOS1.EXE” which attached in
your Driver disk to optimize DOS mode performance

V. THE PANEL LUMINANCE WAS DOWN

Use white pattern and resolution 1280x1024 @ 60Hz , CHROMA 7120 measured the center of panel

Set Contrast, brightness =maximal, RGB= 50
Quit from OSD-screen, measured Y(luminance)
With chroma 7120, check Y= 240±10 CD/M2 ?

If Y can reach ＞190 cd/m2 that means
The lamp still working well, so we just re-do the

white-balance process
As following procedure

Adjust VR201 until maximal, measured Y =
240±10 cd/m2 ?

Use white-pattern, press MENU button along
with AC power-plug in ( you will in factory
mode) The OSD-menu will be at left-top of
screen,

If the Y less than 160 cd/m2 (after the VR201=
MAX, contrast, brightness = max) then change the
LAMP of panel

press AUTO button to automatically adjust
blacklevel value, you will see the sign PASS ,if
FAIL , manual adjust the blacklevel until value 43 !

Set contrast, brightness to max, and turn the VR201
to max , wait for 20 minutes until the luminance Y
stable
The Y should be larger than 200 cd/m2
(for panel which already use for a year, the Y
luminance might be a little down, around 180
cd/m2, there is acceptable too)

Follow this manual page 7 item 4-2 method to
more detail procedure for do a white-balance
adjust

Page 20 of 82

6.B).Inverter –MODULE Spec &Trouble Shooting Chart

MODEL NAME: IN7425A1

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG17” DC TO AC INVERTER

Page 21 of 82

1. TABLE OF CONTENTS

1-1 PART NUNBER

1-2 APPLICATION

1-3 GENERAL CONDITION

1-4 CONNECTOR PIN ASSIGMENT

1-5 ELECTRICAL CHARACTERISTICS

1-6 SCHEMATIC

1-7 FUNCTION TEST CIRCUIT DIAGRAM

1-8 BURN IN CYCLE

1-9 FUNCTION TEST BLOCK DIAGRAM

1-10 FUNCTION TEST LIST

1-11 LABEL

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG 17” DC TO AC INVERTER

Page 22 of 82

2. PART NO.: AOC: IN7425A1

3. APPLICATION: This document defines requirements tested for the
CCFL inverter of the TFT-LCD panel and used HYDIS(HT17E11-300) &
SAMSUNG(P170EUL01) 17” 4 Lamps

4. GENERAL CONDITION:

3-1. Operating ambient temperature ----- 0℃ ~ +40℃

3-2. Operating humidity --------------------- 95% MAX. R.H.
3-3. Storage ambient temperature ------- -40℃ ~ +70℃

3-4. Storage humidity ------------------------ 95% MAX. R.H.

3-5. M.T.B.F. ------------------------------------ 50000 hrs

4.CONNECTOR PIN ASSIGMENT:

4-1. CON1: INPUT

MODEL NO.: 33L3802-5H

PIN SYMBOL DESCRIPTION

1 Vin Input voltage: 12 V

2 Vin Input voltage: 12 V

3 NO/OFF ON: 3V OFF:0V

4 Dimming Dimming range (0V~+5.0V)

5 GND GND

4-2. CON2, CON3, CON4, CON5OUTPUT
MODEL NO.: 33A8021-2-J

PIN SYMBOL DESCRIPTION

1 HV OUTPUT Input H.V to lamps

2 RETURN Return to control

Page 23 of 82

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG 17” DC TO AC INVERTER

5.ELECTRICAL CHARACTERISTICS:

The data test with the set of AOC, and the test circuit is as below.

5-1. MAX BRINGTHNESS (Vadj:5.0v), LOAD=120K

ΩX4

(ROOM TEMPERATURE 25℃ ±4℃)

ITEM

SYMBOL MIN. TYP. MAX. UNIT REMARK

Input voltage Vin 10.8 12 13.2 V

Input current Iin 2250 2530 mA

Output Current Iout 6.0 6.5 7.0 mA

Frequency

H.V open Vopen 1600 1750 1900 Vrms

Start voltage Vst 1750 1850 1950 Vrms

H.V Load Vload 680 780 880 Vrms

F 51.0

56.0 61.0 KHZ

Protect delay time PDT

2.5 3.5 -- Sec

FOR 4 LOAD

FOR 1 LOAD

FOR 1 LOAD

NO LOAD

FOR CCFL

RL=120KΩ

5-2. MIN BRINGTHNESS (Vadj:0.0v), LOAD=120K

ΩX4

(ROOM TEMPERATURE 25℃ ±4℃)

ITEM

SYMBOL MIN. TYP. MAX. UNIT REMARK

input voltage Vin 10.8 12 13.2 V

input current Iin 750 880 mA

Output Current Iout 3.3 3.8 4.3 mA

Frequency

H.V open

Start voltage

H.V Load Vload 350 450 550 Vrms

F 51.0

Vopen

Vst

1600 1750 1900 Vrms

1750 1850 1950 Vrms

56.0 61.0 KHZ

FOR 4 LOAD

FOR 1 LOAD

FOR 1 LOAD

NO LOAD

FOR CCFL

RL=120KΩ

Page 24 of 82

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG 17” DC TO AC INVERTER

6.SCHEMATICS

TP4

1

HVO

TP6

PT1

5 9

1

2K

3,4

2
6

71

80AL17T-3-YS

D7

R38

12K

TP5

PT2

5 9

RLS4148

1

HVO

R40

51K

R30

R31

2K

2K

3,4

2
6

71

80AL17T-3-YS

D8

R41

51K

RLS4148

R39

12K

TP1

TP2

CON1

Vin
Vin

ENB

DIM

GND

33A3802-5H

TP3

C23

C1

+

150U/25V

F1

4A/63V

1

Vin

1

ENA

1
2
3

R1

4

30K

5

1

DIM

+

150U/25V

R2
10K

0.1U/25V

R7
OPEN

C7

4.7U/16V
R5
47K
C5

0.1U/25V

C2

REF

U1

CTRT1IN+

TL1451AC OR BA9741F

C8

1234567

330P/50V

R4
10K

R6
47K

R3

C3

0.1U/25V

10K

C6

0.1U/25V

SCP

R8

2IN-

2IN+

1IN-

R9 4.7K

R11 15K

DTC144WKA

4.7K

C9

1U/25V

2FBK

1FBK

C10

1U/25V

Q1

R10
15K

10111213141516

2OUT

2DTC

1DTC

1OUT

GND Vcc

8 9

AOC (Top Victory) Electronics Co., Ltd.

Title

FOR HYUNDAI 4LAMPS .INVERTER

Size Document Number Rev

A

Date: Sheet

Thursday, April 04, 2002

IN7425A1(715A917-1-5)

22

of

DTA144WKA

C4

0.1U/25V

A

Q3 SI4431ORAO4403

1

Q2

2
3
4

R16

R12

220

3.9K

R14

3.9K

SST3904

R18 470

C11
1U/25V

Q5

SST3906

L1 150UH

8
7
6
5

D3
11B

R20 15K

D1

SR240

Q7

R22 12K

R24
2K

23

Q9

1

2SC5706 OR2SD2098

Q10

1

2SC5706 OR 2SD2098

R252KR262KR27

C13

0.18U/100V

2 3

C21

0.47U/25V

R282KR29

23

Q11

1

2SC5706 OR 2SD2098

Q12

1

2SD2098

2K

C14

0.18U/100V

R13

3.9K

R15

3.9K

Q4 SI4431OR AO4403

1
2
3
4

R17
220

Q6

SST3904

R19

470

C12
1U/25V

SST3906

L2 150UH

8
7
6
5

D4
11B

R21 15K

D2

SR240

Q8

R23 12K

2 3

is power GND

C22

0.47U/25V

is signal GND

HVL

1U/25V

C15

22P/3KV

C16

22P/3KV

R32
1K(1206)

C19

1U/25V

C17

22P/3KV

C18

22P/3KV

R33
1K(1206)

C20

BAV99

R34 510

BAV99

R35 510

R37 510

CON2

1

2

SM02B-BHSS-1-TB

CON3

1

2

SM02B-BHSS-1-TB

D5

1

TP7
HVL

TP8
HVL

R36

1

510

CON4

1

2

SM02B-BHSS-1-TB

CON5

1

2

SM02B-BHSS-1-TB

1

D6

TP9

HVL

Page 25 of 82

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG 17” DC TO AC INVERTER

Page 26 of 82

7.FUNCTION TEST CIRCUIT DIAGRAM

C0N102

5
4
3

12V or 14V

DC POWER SUPPLY

R1

10K

Q1

D1

MMST3904

5.6B

R2

22

NO

SW

OFF

2
1

33L3802-5H

CON201

1

2

SM02(8.0)B-BHS-1-TB

CON202

1

2

SM02(8.0)B-BHS-1-TB

R3
120K

TV

R7
10

R4
120K

R8
10

TV

VR1

0V~5V

10K

CON203

1

2

SM02(8.0)B-BHS-1-TB

CON204

1

2

SM02(8.0)B-BHS-1-TB

R5
120K

TV

R9
10

R6
120K

R10
10

TV

AOC (Top Victory) Electronics Co., Ltd.

Title

CONVERTER&INVERTER FUNCTION CIRCUIT

Size Document Number Rev

A

Date: Sheet of

IN7425A1(715A917-1-5)

Friday, August 30, 2002

22

A

Page 27 of 82

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG 17” DC TO AC INVERTER

8.BURN IN CYCLE

8-1. TEST COINDITION

1. Vin=12.0 ± 0.8V

2. BRIGHTNESS LOAD=CCFL OR 120K

3. BRIGHTNESS LOAD ADJUST=5 VDC

4. BRIGHTNESS LOAD ON=3 VDC

5. AMB TEMPERATURE : 45 ±5℃

8-2. BURN IN CYCLE

1. 第一段於10分鐘內TURN ON & CUT OFF 60次.

2. 第二段連續 TURN ON 30分鐘.

3. 第三段於10分鐘內ON/OFF 20次

4. 第四段CUT OFF10分鐘

5. TESTED ALL OF TWO CYCLE

TURN NO & CUT OFF 60 TIMES

POWER ON

POEWR OFF

10 MINUTE AT
THE ONE STAGES

30 MINUTE AT
THE TWO STAGES

TURN NO & CUT OFF 20 TIMESCONTINUOUS TURN ON

10 MINUTE AT THE
THREE STAGES

CONTINUOUS CUT OFF

10 MINUTE AT THE
FOUR STAGES

Page 28 of 82

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG 17” DC TO AC INVERTER

9.FUNCTION TEST BLOCK DIAGRAM

9-1.OUTPUT OPEN VOLTAGE OF THE TESTED

USED HIGHT VOLTAGE PROBE THEN

TURN ON POWER SUPPLY

AND OPEN ALL OF THE LAMPS TO
SHORT R7. AFTER WANT TO TESTED
TP4, TP5 H.V OUTPUT POINT. THEN
TO CHECK IN DATA ON TEST LIST.

9-2.OUTPUT LOAD VOLTAGE OF THE TESTED

9-2-1 OUTPUT LOAD VOLTAGE( ADJ=5V,MAX) OF THE TESTED

USED HIGHT VOLTAGE PROBE THEN AND

TURN ON POWER SUPPLY

TO TESTED TP6, TP7, TP8, TP9
OUTPUT POINT. AFTER WANT TO ADJUST
DIMMING TO 5V THEN TO CHECK IN
DATA ON TEST LIST.

9-2-2 OUTPUT LOAD VOLTAGE (ADJ=0V,MIN) OF THE TESTED

TURN ON POWER SUPPLY

USED HIGHT VOLTAGE PROBE THAN AND
TO TESTED TP6, TP7, TP8, TP9, AND
OUTPUT POINT. AFTER WANT TO ADJUST
DIMMING TO 0V THEN TO CHECK IN DATA
ON TEST LIST.

Page 29 of 82

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG 17” DC TO AC INVERTER

9-3.INPUT LOAD CURRENT OF THE TESTED

TURN ON POWER SUPPLY

9-4.OUTPUT CURRENT OF THE TESTED

USED DC POWER SUPPLY THAN TO
CHECK IN CURRENT DATA ON TEST
LIST.

9-4-1.OUTPUT CURRENT (ADJ=5V,MAX) OF THE TESTED

TURN ON POWER SUPPLY

USED AC CURRENT METER STRING
TOGETHER WITH CON2 , 3 PIN2 THAN
AND TO TESTED AC CURRENT. AFTER
WANT TO ADJUST DIMMIMG(PT6) TO 5V
THAN TO CHECK IN DATA ON TEST
LIST.

9-4-2.OUTPUT CURRENT (ADJ=0V,MIN) OF THE TESTED

TURN ON LCD MONTION

USED AC CURRENT METER STRING
TOGETHER WITH CON2, 3, 4, 5, PIN2
THAN AND TO TESTED AC CURRENT.
AFTER WANT TO ADJUST DIMMIMG TO
0V THAN TO CHECK IN DATA ON TEST
LIST.

Page 30 of 82

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG 17” DC TO AC INVERTER

9-5.OPERATURE FREQUENCY OF THE TESTED

TURN ON POWER SUPPLY

USED OSCILLOSCOPE PROBE ALONGSID
OF AC CURRENT METER TO TESTED
FREQUENCY CHECK IN DATA ON
TEST LIST.

9-6.OPERATURE TEMPERAYURE OF THE TESTED

TURN ON POWER SUPPLY

USED TEMPERATURT PROBE METER TO
TESTED AROUND TEMPERATURE CHECK
IN DATA ON TEST LIST.

9-7 FUNCTION TEST CYCLE

PASS PASS

FUNCTION TESTED
ALL OF THE ITEM

BURN IN CYCLE

PASS

ELECTRONICS TESTED ALL OF
THE PASS

Page 31 of 82

FUNCTION TEST ALL
OF THE ITEM

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG 17” DC TO AC INVERTER

10.FUNCTION TEST LIST

10-1. TEST LIST

TEST ITEMS SPEC 1 2 3 4 5

Input voltage (V)

Input current (mA) 2530(max)

Output current (max) mA

Output current (min) mA

Output current( max) mA

Output current (min) mA

Frequency (KHZ) A

Frequency (KHZ) B

High voltage (open) A

High voltage (load) A

High voltage (open) B

High voltage (load) B

Protect delay time T >0.4 sec

12 ±1.2

6.5 ± 0.5

3.8 ± 0.5

6.5 ± 0.5

3.8 ± 0.5

56 ± 5

56 ± 5

1750 ± 150

780 ± 100

1750 ± 150

780 ± 100

12.0 12.0 12.0 12.0 12.0

10-2COMPONENT TEMPERATURE REVIEW (Vadj=0.0V)

NO. TEST ITEMS SYMBOL

1. Transformer PT1,PT2 5. Chock L1,L2

2. MOS FET Q3,Q4 6. Transistor Q9, Q10

3. Capacitor C13,14 7. Transistor Q11, Q12

4. Diode D1,D2 8. IC U1

UNIT ℃

NO. TEST ITEMS SYMBOL

10-3. TEST INSTRUMENT:

1. DC POWER SUPPLY GPR-3303D 2. AC VTVM VT:-181E

3. DIGITAL MULTIMERTER MODEL-34401

4. HIGHTVOLT PROB MODEL-P6015A

5. SCOPE MODEL- TDS3052

6. AC mA METER MODEL-2016

UNIT ℃

Page 32 of 82

TOP VICTORY ELECTRONICS (TAIWAN) Co., Ltd.

THE SPECIFICATION OF HYDIS & SAMSUNG 17” DC TO AC INVERTER

11.LABEL

The following item shall be on the label

AOC REV : 0

IN7425A1

╳╳╳╳╳╳╳╳╳╳/╳╳
╳╳

AOC P/N

PRO. ORDER/ LOT NO.

FOR USED PANEL

Page 33 of 82

Page 34 of 82

6 C). ADAPTER-MODULE Trouble shooting chart

The following spec & block-diagram is offer by CHI-SAM –COMPANY, for External
Adapter

Page 35 of 82

6.D). Main-chip GMZAN2 SPECFICATION
GMZAN2

The gmZAN2device utilizes Genesis’ patented third-generation Advanced Image Magnification
technology as well as a proven integrated ADC/PLL to provide excellent image quality within a cost
effective SVGA/XGA LCD monitor solution.
As a pin-compatible replacement for the gmB120, the gmZAN2 incorporates all of the gmB120
features plus many enhanced features; including 10-bit gamma correction, Adaptive Contrast
Enhancement (ACE) filtering, Sync On Green (SOG), and an enhanced OSD.

1.1 Features

z Fully integrated 135MHz 8-bit triple-ADC, PLL, and pre-amplifier
z GmZ2 scaling algorithm featuring new Adaptive Contrast Enhancement (ACE)
z On-chip programmable OSD engine
z Integrated PLLs
z 10-bit programmable gamma correction
z Host interface with 1 or 4 data bits
z Pin-compatible with gmB120

Integrated Analog Front End

z Integrated 8-bit triple ADC
z Up to 135MHz sampling rates
z No additional components needed
z All color depths up to 24-bits/pixel are supported

High-Quality Advanced Scaling

z Fully programmable zoom
z Independent horizontal / vertical zoom
z Enhanced and adaptive scaling algorithm for optimal image quality
z Recovery Mode / Native Mode

Input Format

z Analog RGB up to XGA 85Hz
z Support for Sync On Green (SOG)
z Support for composite sync modes

Output Format

z Support for 8 or 6-bit panels (with high quality dithering)
z One or two pixel output format

Built In High-Speed Clock Generator

z Fully programmable timing parameters
z On-chip PLLs generate clocks for the on-chip ADC and pixel clock from a single reference

oscillator

Auto-Configuration / Auto-Detection

z Phase and image positioning
z Input format detection

Operation Modes

z Bypass mode with no filtering
z Multiple zoom modes:

 With filtering
 With adaptive (ACE) filtering

Integrated On-Screen Display

z On-chip character RAM and ROM for better customization
z External OSD supported for greater flexibility
z Supports both landscape and portrait fonts
z Many other font capabilities including: blinking, overlay and transparency

1.3 Pin Description

Page 36 of 82

Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open.

Table 1 : Analog-to-Digital Converter

PIN # Name I/O Description

77 ADC_VDD2

78 ADC_GND2

79 ADC_VDD1

80 ADC_GND1

81 SUB_GNDA

82 ADC_GNDA

84 ADC_VDDA

83 Reserved

85 ADC_BGNDA

88 ADC_BVDDA

86 BLUE- I

87 BLUE+ I

89 ADC_GGNDA

92 ADC_GVDDA

90 GREEN- I

91 GREEN+ I

93 ADC_RGNDA

96 ADC_RVDDA

94 RED- I

95 RED+ I

Table 2 : Host Interface (HIF) / External On-Screen Display

PIN # Name I/O Description

98 HFS I

103 HCLK I

99 HDATA I/O

100 RESETn I

101 IRQ O

115 OSD-HREF O

116 OSD-VREF O

117 OSD-Clk O

118 OSD-Data0 I

Digital power for ADC encoding logic. Must be bypassed with 0.1uF
capacitor to pin 78 (ADC_GND2)
Digital GND for ADC encoding logic. Must be directly connected to the
digital system ground plane.
Digital power for ADC clocking circuit. Must by passed with 0.1uF
capacitor to pin 80 (ACD_GND1).
Digital GND for ADC clocking circuit. Must be directly connected to the
digital system ground plane.
Dedicated pin for substrate guard ring that protects the ADC reference
system. Must be directly connected to the analog system ground
plane.
Analog ground for ADC analog blocks that are shared by all three
channels. Includes bandgap reference, master biasing and full scale
adjust. Must be directly connected to analog system ground plane.
Analog power for ADC analog blocks that are shared by all three
channels. Includes bandgap reference, master biasing and full scale
adjust. Must be bypassed with 0.1uF capacitor to pin 82
(ADC_GNDA).
For internal testing purpose only. Do not connect.

Analog ground for the blue channel. Must be directly connected to the
analog system ground plane.
Analog power for the blue channel. Must be bypassed with 0.1uF
capacitor to pin 85(BGNDA).
Negative analog input for the Blue channel.

Positive analog input for the Blue channel.

Analog ground for the green channel. Must be directly connected to
the analog system ground plane.
Analog power for the green channel. Must be bypassed with 0.1uF
capacitor to pin 89 (ADC_GGNDA).
Negative analog input for the Green channel.

Positive analog input for the Green channel.

Analog ground for the red channel. Must be directly connected to the
analog system ground plane.
Analog power for the red channel. Must be bypassed with 0.1uF
capacitor to pin 93 (ADC_RGNDA).

Negative analog input for the Red channel.

Positive analog input for the Red channel.

Host Frame Sync. Frames the packet on the serial channel.

Clock signal input for the 3-wire serial communication.

Data signal for the 3-wire serial communication.

Resets the gmZAN2 chip to a known state when low.

Interrupt request output.

HSYNC output for an external OSD controller chip.

VSYNC output for an external OSD controller chip.

Clock output for an external OSD controller chip.

Data input 0 from an external OSD controller chip.

Page 37 of 82

119 OSD-Data1 I

120 OSD-Data2 I

121 OSD-Data3 I

122 OSD-FSW I

123 MFB11 I/O

124 MFB10 I/O

102 MFB9 I/O

104 MFB8 I/O

105 MFB7 I/O

106 MFB6 I/O

107 MFB5 I/O

109 MFB4 I/O

110 MFB3 I/O

111 FMB2 I/O

112 MFB1 I/O

113 MFB0 I/O

Data input 1 from an external OSD controller chip.

Data input 2 from an external OSD controller chip.

Data input 3 from an external OSD controller chip.
External OSD window display enable. Displays data from external

OSD controller when high.
Multi-Function Bus 11. One of twelve multi-function signals MFB[11:0].

Multi-Function Bus 10. One of twelve multi-function signals MFB[11:0].
Multi-Function Bus 9. One of twelve multi-function signals MFB[11:0].

Also used as HDATA3 in a 4-bit host interface configuration.
Multi-Function Bus 8. One of twelve multi-function signals MFB[11:0].
Also used as HDATA2 in a 4-bit host interface configuration.
Multi-Function Bus 7. One of twelve multi-function signals MFB[11:0].
Also used as HDATA1 in a 4-bit host interface configuration.
Multi-Function Bus 6. One of twelve multi-function signals MFB[11:0].
Internally pulled up. When externally pulled down (sampled at reset )
the host interface is configured for 4 bits wide. In this configuration,
MFB9:7 are used as HDATA 3:1.
Multi-Function Bus 5 One of twelve multi-function signals MFB[11:0].
Internally pulled up. When externally pulled down (sampled at reset )
the chip uses an external crystal resonator across pins 141 and 142,
instead of an oscillator.

Multi-Function Bus 4. One of twelve multi-function signals MFB[11:0].

Multi-Function Bus 3. One of twelve multi-function signals MFB[11:0].

Multi-Function Bus 2. One of twelve multi-function signals MFB[11:0].

Multi-Function Bus 1. One of twelve multi-function signals MFB[11:0].

Multi-Function Bus 0. One of twelve multi-function signals MFB[11:0].

Page 38 of 82

Table 3 : Clock Recovery / Time Base Conversion

PIN # Name I/O Description

125 DVDD

127 DAC_DGNDA

128 DAC_DVDDA

129 PLL_DVDDA

130 Reserved

131 PLL_DGNDA

132 SUB_DGNDA

133 SUB_SGNDA

134 PLL_SGNDA

135 Reserved

136 PLL_SVDDA

137 DAC_SVDDA

138 DAC_SGNDA

139 SVDD

141 TCLK I Reference clock(TCLK) input from the 50 MHz crystal oscillator
142 XTAL O If using an external oscillator, leave this pin floating. If using an

143 PLL_RVDDA Analog power for the Reference DDS PLL. Must be bypassed with a

144 PLL_RGNDA Analog ground for the Reference DDS PLL. Must be directly

145 Reserved For testing purposes only. Do not connect.

146 SUB_RGNDA Dedicated pin for the substrate guard ring that protects the Reference

148 VSYNC I CRT Vsync input. TTL Schmitt trigger input.

149 SYN_VDD Digital power for CRT Sync input.

150 HSYNC/CSYN

C

Digital power for Destination DDS (direct digital synthesizer). Must be
bypassed with a 0.1uF capacitor to digital ground plane.
Analog ground for Destination DDS DAC. Must be directly connected
to the analog system ground plane.
Analog power for Destination DDS DAC. Must be bypassed with a

0.1uF capacitor to pin 127 (DAC_DGNDA).
Analog power for the Destination DDS PLL. Must be bypassed with a

0.1uF capacitor to pin 131 (PLL_DGNDA).
For testing purposes only. Do not connect.
Analog ground for the Destination DDS PLL. Must be directly

connected to the analog system ground plane.
Dedicated pin for the substrate guard ring that protects the Destination
DDS. Must be directly connected to the analog system ground plane.
Dedicated pin for the substrate guard ring that protects the Source
DDS. Must be directly connected to the analog system ground plane.
Analog ground for the Source DDS PLL. Must be directly connected to
the analog system ground.

For testing purposes only. Do not connect.
Analog power for the Source DDS DAC. Must be bypassed with a

0.1uF capacitor to pin 134 (PLL_SGNDA)
Analog power for the Source DDS DAC. Must be by passed with a

0.1uF capacitor to pin 138 (DAC_SGNDA)
Analog power for the Source DDS DAC. Must be directly connected to
the analog system ground.
Digital power for the Source DDS. Must be bypassed with a 0.1uF
capacitor to digital ground plane.

external crystal, connect crystal between TCLK(141) and XTAL(142).
See MFB5(pin 107).

0.1uF capacitor to pin 144(PLL_RGNDA)

connected to the analog system ground plane.

DDS. Must be directly connected to the analog system ground plane.

I CRT Hsync or CRT composite sync input. TTL Schmitt trigger input.

Page 39 of 82

Table 4. TFT Panel Interface

PIN # Name I/O

6 PD47 O OB1 - - -

7 PD46 O OB0 - - -

9 PD45 O OG1 - - -

10 PD44 O OG0 - - -

13 PD43 O OR1 - - -

14 PD42 O OR0 - - -

15 PD41 O EB1 - B1 -

16 PD40 O EB0 - B0 -

17 PD39 O EG1 - G1 -

19 PD38 O EG0 - G0 -

20 PD37 O ER1 - R1 -

22 PD36 O ER0 - R0 -

23 PD35 O OB7 OB5 - -

24 PD34 O OB6 OB4 - -

25 PD33 O OB5 OB3 - -

26 PD32 O OB4 OB2 - -

27 PD31 O OB3 OB1 - -

28 PD30 O OB2 OB0 - -

29 PD29 O OG7 OG5 - -

31 PD28 O OG6 OG4 - -

32 PD27 O OG5 OG3 - -

34 PD26 O OG4 OG2 - -

35 PD25 O OG3 OG1 - -

36 PD24 O OG2 OG0 - -

37 PD23 O OR7 OR5 - -

38 PD22 O OR6 OR4 - -

39 PD21 O OR5 OR3 - -

42 PD20 O OR4 OR2 - -

46 PD19 O OR3 OR1 - -

47 PD18 O OR2 OR0 - -

48 PD17 O EB7 EB5 B7 B5

50 PD16 O EB6 EB4 B6 B4

51 PD15 O EB5 EB3 B5 B3

52 PD14 O EB4 EB2 B4 B2

53 PD13 O EB3 EB1 B3 B1

54 PD12 O EB2 EB0 B2 B0

55 PD11 O EG7 EG5 G7 G5

56 PD10 O EG6 EG4 G6 G4

57 PD9 O EG5 EG3 G5 G3

62 PD8 O EG4 EG2 G4 G2

2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk

8bit 6-bit 8-bit 6-bit TFT

Description

Page 40 of 82

PIN # Name I/O

63 PD7 O EG3 EG1 G3 G1

64 PD6 O EG2 EG0 G2 G0

66 PD5 O ER7 EG5 R7 R5

67 PD4 O ER6 ER4 R6 R4

68 PD3 O ER5 ER3 R5 R3

69 PD2 O ER4 ER2 R4 R2

70 PD1 O ER3 ER1 R3 R1

71 PD0 O EG2 ER0 R2 R0

43 PdispE O This output provides a panel display enable signal that is active when

74 PHS O This output provides the panel line clock signal.

73 PVS O This output provides the frame start signal.

44 PCLKA O This output is used to drive the flat panel shift clock.

45 PCLKB O Same as PCLKA above.

75 Pbias O This output is used to turn on/off the panel bias power or controls

76 Ppwr O This output is used to control the power to a flat panel.

PIN # Name I/O Description

3 PSCAN I

155 SCAN_IN1 I

157 SCAN_IN2 I

159 SCAN_OUT1 O

160 SCAN_OUT2 O

153 Reserved

154 Reserved

Table 6. VDD / VSS for Core Circuitry, Host Interface, and Panel/Memory Interface

PIN # Description

65, 40, 33, 12

149, 108, 58, 21, 11

158, 151, 140, 126, 114, 72,

61,

49, 41, 30, 18, 8, 1

2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk

8bit 6-bit 8-bit 6-bit TFT

flat panel data is valid.

The polarity and the phase of this signal are independently

programmable.

backlight.

Table 5. Test Pins

Enable automatic PCB assembly test. When this input is pulled high,
the automatic PCB assembly test mode is entered. An internal pull­down resistor drives this input low for normal operation.

Scan input 1 used for automatic PCB assembly tesing.

Scan input 2 used for automatic PCB assembly tesing.

Scan output 1 used for automatic PCB assembly tesing.

Scan output 2 used for automatic PCB assembly tesing.

PVDD4~PVDD1 for panel / memory interface. Connect to +3.3V.
Must be the same voltage as the CVDD’s
SRVDD2-1, CVDD4, CVDD2-1 for core circuitry. Connect to +3.3V.
Must be the same voltage as the PVDD’s.

Digital grounds for core circuiry and panel / memory interface.

Description

Page 41 of 82

1.4 System-level Block Diagram

ADC_VDD

ADC_GND

Red

Blue

R1RR1RR1

R

Green

R1RR1
R

ADC

ADC

L1

Video Connector

L2

RVDDA

Hsync

Vsync

C1
C

C2
C

To Clock
Generator

On-Screen
Display
Controller

R+,G+,B+

4

OSD-FSW OSD-FSW

OSD-CLK

OSD-HREF

OSD-VREF

MPU with
EPROM

MFBs

RESETn

IRQ

HES

HCLK

HDATA

Host Interface

12

Figure 2. Typical Stand-alone Configuration

CVDD

gmZAN1 Core

CVSS

RVDDA

RGNDA

TCLK

Clock Generator

24

Pbias

Panel Interface

Pbias

SVDDA

SGNDA

DVDDA

DGNDA

Even Data

PCLKA

PHS

PVS

PDISPE

Odd Data

24

Power

Power
Switching

Switching
Module

Module

OSC

+5/3.3V

TFT Panel

+12V

Page 42 of 82

1.5 Operating Modes

The Source Clock (also called SCLK in this document) and the Panel Clock are defined as follows:
z The Source Clock is the sample clock regenerated from the input Hsync timing (called clock

recovery) by SCLK DDS (direct digital synthesis) and the PLL.

z The Panel Clock is the timing clock for panel data at the single pixel per clock rate. The actual

PCLK to the panel may be one-half of this frequency for double-pixel panel data format. When its
frequency is different from that of source clock, the panel clock is generated by Destination Clock
(or DCLK) DDS/PLL.

There are six display modes: Native, Slow DCLK, Zoom, Downscaling, Destination Stand Alone, and
Source Stand Alone.
Each mode is unique in terms of:

z Input video resolution vs. panel resolution
z Source Clock frequency / Panel Clock frequency ratio
z Source Hsync frequency / Panel Hsync frequenc ratio
z Data source (analog RGB, panel background color, on-chip pattern generator

1.5.1 Native

Panel Clock frequency = Source Clock frequency
Panel Hsync frequency = Input Hsync frequency
Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is the same as the panel resolution and the input data
clock frequency is within the panel clock frequency specification of the panel being used.

1.5.2 Slow DCLK

Panel Clock frequency < Source Clock frequency
Panel Hsync frequency = Input Hsync frequency
Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is the same as the panel resolution, but the input data
clock frequency is exceeds the panel clock frequency specification of the panel being used. The panel
clock is scaled to the Source Clock, and the internal data buffers are used to spread out the timing of
the input data by making use of the large CRT blanking time to extends the panel horizontal display
time.

1.5.3 Zoom

Panel Clock frequency > Source Clock frequency
Panel Hsync frequency > Input Hsync frequency
Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is less than the panel resolution. The input data clock is
then locked to the pnael clock, which is at a higher frequency. The input data is zoomed to the panel
resolution.

Page 43 of 82

1.5.4 Downscaling

Panel Clock frequency < Source Clock frequency
Panel Hsync frequency < Input Hsync frequency
Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is greater than the panel resolution, to provide enough of
a display to enable the user to recover to a supported resolution. The input clock is operated at a
frequency less than that of the input pixel rate(under-sampled horizontally) and the scaling filter is
used to drop input lines. In this mode, zoom scaling must be disabled

1.5.5 Destination Stand Alone

Panel Clock = DCLK in open loop (not locked)
Panel Hsync frequency = DCLK frequency / (Destination Htotal register value)
Panel Vsync frequency = DCLK frequency / (Dest. Htotal register value * Dest. Vtotal register
value)

This mode is used when the input is changing or not available. The OSD may still be used as in all
other display modes and stable panel timing signals are produced. This mode may be automatically
set when the gmZAN2 detects input timing changes that could cause out- of-spec operation of the
panel.

1.5.6 Source Stand Alone

Panel Clock = DCLK in open loop (not locked to input Hsync)
Panel Hsync frequency = SCLK frequency / (Source Htotal register value)
Panel Vsync frequency = SCLK frequency / (Source Htotal register value *Source Vtotal
register value)

This mode is used to display the pattern generator data. This mode may be useful for testing an LCD
panel on the manufacturing line (color temperature calibration, etc.).

Page 44 of 82

2. FUNCTIONAL DESCRIPTION

Figure 3 below shows the main functional blocks inside the gmZAN2

2.1 Overall Architecture

Figure 3. Block Diagram for gmZAN2

On-Screen
Display
Control

Analog
RGB

Triple
ADC

Source
Timing
Measurement
/ Generation

Scaling
Engine

Gamma
Control
(CLUT)
+
Dither

Panel
Timing
Control

Panel

MCU

Host
Interface

Clock
Recovery

Pixel
Clock
Generator

Clock
Reference

2.2 Clock Recovery Circuit

The gmZAN2 has a built-in clock recovery circuit. This circuit consists of a digital clock synthesizer
and an analog PLL. The clock recovery circuit generates the clock used to sample analog RGB data
(SCLK or source clock). This circuit is locked to the HSUNC of the incoming video signal. The RCLK
generated from the TCLK input is used as a reference clock.

The clock recovery circuit adjusts the SCLK period so that the feedback pulse generated every SCLK
period multiplied by the Source Horizontal Total value (as programmed into the registers) locks to the
rising edge of the Hsync input. Even though the initial SCLK frequency and the final SCLK frequency
are as far apart as 60MHz , locking can be achieved in less than 1ms across the operation
voltage/temperature range.

Page 45 of 82

The SCLK frequency (1/SCLK period) can be set to the range of 10-to-135 MHz. Using the DDS

p

(direct digital synthesis) technology the clock recovery circuit can generate any SCLK clock frequency
within this range.

The pixel clock (DCLK or destination clock) is used to drive a panel when the panel clock is different
from SCLK (or SCLK/2). It is generated by a circuit virtually identical to the clock recovery circuit. The
difference is that DCLK is locked to SCLK while SCLK is locked to the Hsync input. DCLK frequency
divided by N is locked to SCLK frequency divided by M. The value M and N are calculated and
programmed in the register by firmware. The value M should be close to the Source Htotal value.

Figure 4. Clock Recovery Circuit

Hsync

Sample

Phase

Delay

DDS Digital

Clock

Synthesis

Course

Adjust

DDS Output

Analog

PLL & VCO

VCO

Out

ut

Clock

Divider

÷ n

SCLK

Fine

Adjust

PLL

Divider

÷

Prescaler

÷ 2 (or 1)

Source

Horizontal

Total Divider

TCLK

Analog

PLL & VCO

Post Scale

÷ 2 (or 1)

RCLK

PLL Divider

÷

PLL Divider

÷

Page 46 of 82

The table below summarizes the characteristics of the clock recovery circuit.

Table 7. Clock Recovery Characteristics

Minimum Typical Maximum

SCLK Frequency 10MHz 135 MHz
Sampling Phase

0.5 ns/step, 64 steps

Adjustment

Patented digital clock synthesis technology makes the gmZAN2 clock circuits very
immune to temperature/voltage drift.

2.2.1 Sampling Phase Adjustment

The ADC sampling phase is adjusted by delaying the Hsync input at the programmable
delay cell inside the gmZAN2. The delay value can be adjusted in 64 steps, 0.5 ns/step.
The accuracy of the sampling phase is checked by the gmZAN2 and the “score” can be
read in a register. This feature will enable accurate auto-adjustment of the ADC sampling
phase.

2.2.2 Source Timing Generator

The STG module defines a capture window and sends the input data to the data path
block. The figure below shows how the window is defined.
For the horizontal direction, it is defined in SCLKs (equivalent to a pixel count). For the
vertical direction, it is defined in lines.
All the parameters in the figure that begin with “Source” are programmed into the
gmZAN2 registers.
Note that the vertical total is solely determined by the input.
The reference point is as follows:

z The first pixel of a line: the pixel whose SCLK rising edge sees the transition of the

HSYNC polarity from low to high.

z The first line of a frame: the line whose HSYNC rising edge sees the transition of the

VSYNC polarity from low to high.
The gmZAN2 also supports the use of analog composite sync and digital sync signals as
described in Section 2.3.2

Figure 5. Capture Window

Reference
Point

Source Vertical Total (lines)

Source
Hstart

Source

Vstart

Source Height

Source Horizontal Total (pixels)

Source Width

Capture Window

Page 47 of 82

2.3 Analog-to-Digital Converter

2.3.1 Pin Connection

The RGB signals are to be connected to the gmZAN2 chip as described in Table 8 and Table 9.

Table 8. Pin Connection for RGB Input with Hsync/Vsync

GmZAN2 Pin Name (Pin Number) CRT Signal Name

Red+(#95) Red
Red- (#94) N/A (Tie to Analog GND for Red on the board)
Green+(#91) Green
Green- (#90) N/A (Tie to Analog GND for Green on the board)
Blue+(#87) Blue
Blue- (#86) N/A (Tie to Analog GND for Blue on the board)
HSYNC/CS (#150) Horizontal Sync
VSYNC (#148) Vertical Sync

Table 9. Pin Connection for RGB Input with Composite Sync

GmZAN2 Pin Name (Pin Number) CRT Signal Name

Red+(#95) Red
Red- (#94) N/A (Tie to Analog GND for Red on the board)
Green+(#91) Green

When using Sync-On-Green this signal also carries the sync

pulse.
Green- (#90) N/A (Tie to Analog GND for Green on the board)
Blue+(#87) Blue
Blue- (#86) N/A (Tie to Analog GND for Blue on the board)
HSYNC/CS (#150) Digital composite sync. Not applicable for Sync-On-Green

The gmZAN2 chip has three ADC’s (analog-to-digital converters), one for each color (red, green, and blue).
Table 10 summarizes the characteristics of the ADC.

Table 10. ADC Characteristics

MIN TYP MAX NOTE

RGB Track & Hold Amplifiers

Band Width 160MHz
Settling Time to 1/2% 8.5ns Full Scale Input = 0.75V,

BW=160MHz(*)
Full Scale Adjust Range @ R,G,B
Inputs
Full Scale Adjust Sensitivity +/-1 LSB Measured @ ADC Output (**)
Zero Scale Adjust Range For a larger DC offset from an external

Zero Scale Adjust Sensitivity +/-1 LSB Measured @ ADC Output

ADC+RGB Track & Hold Amplifiers

Sampling Frequency (fs) 20MHz 110MHz
DNL +/-

INL +/-

Channel to Channel Matching +/-

Effective Number of Bits (ENOB) 7 Bits fin = 1MHz, fs=80 MHz Vin= -1db below

Power Dissipation 400mW fs=110 MHz, Vdd=3.3V
Shut Down Current 100uA

(*) Guaranteed by design (**) Independent of full scale R,G,B input
The gmZAN2 ADC has a built-in clamp circuit. By inserting series capacitors (about 10 nF) the DC
offset of an external video source can be removed. The clamp pulse position and width are
programmable.

0.45V 0.95V

video source, the AC coupling feature is

used to remove the offset.

fs = 80 MHz

0.9LSB
fs = 80 MHz

1.5LSB

0.5LSB

full scale=0.75V

Page 48 of 82

2.3.2 Sync. Signal Support

The gmZAN2 chip supports digital separate sync (Hsync/Vsync), digital composite sync, and analog
composite sync (also known as sync-on-green). All sync types are supported without external sync
separation / extraction circuits.

Digital Composite Sync

The types of digital composite sync inputs supported are:

z OR/AND type: No Csync pulses toggling during the vertical sync period
z XOR type: Csync polarity changes during the vertical sync period

The gmZAN2 provides enough sync status information for the firmware to detect the digital composite sync
type.

Sync-On-Green (Analog Composite Sync)

The voltage level of the sync tip during the vertical sync period can be either –0.3V or 0V

2.3.3 Display Mode Support

A mode calculation utility (MODECALC.EXE) provided by Genesis Microchip may be run before
compilation of the firmware to determine which input modes can be supported. Refer to firmware
documents for more details.

2.4 Input Timing Measurement

As described in section 2.2.2 above, input data is sent from the analog-to-digital converter to the source
timing generator (STG) block. The STG block defines a capture window (Figure5).

The input timing measurement block consists of the source timing measurement (STM) block and interrupt
request (IRQ) controller. Input timing parameters are measured by the STM block and stored in registers.
Some input conditions will generate an IRQ to an external micro-controller. The IRQ generating conditions
are programmable.

2.4.1 Source Timing Measurement

When it receives the active CRT signal (R,G,B and Sync signals) the Source Timing Measurement unit
begins measuring the horizontal and vertical timing of the incoming signal using the sync signals and TCLKi
as a reference. Horizontal measurement occurs by measuring a minimum and a maximum value for each
parameter to account for TCLKi sampling granularity. The measured value is updated every line. Vertical
parameters are measured in terms of horizontal lines. The trailing edge of the Hsync input is used to check
the polarity of the Vsync input.
The table below lists all the parameters that may be read in the source timing measurement (STM)
registers of the gmZAN2.

Table 11. Input Timing Parameters Measured by the STM Block

Parameter Unit Updated at:

HSYNC Missing N/A Every 4096 TCLKs and every 80ms (2-bits)
VSYNC Missing N/A Every 80ms
HSYNC/VSYNC Timing Change N/A When the horizontal period delta or the vertical

period delta to the previous line / frame

exceeds the threshold value (programmable).
HSYNC Polarity Positive/Negative After register read
VSYNC Polarity Positive/Negative Every frame
Horizontal Period Min/Max TCLKs and SCLKs After register read
HSYNC High Period Min/Max TCLKs After register read
Vertical Period Lines Every frame
VSYNC High Period Lines Every frame
Horizontal Display Start SCLKs Every frame
Horizontal Display End SCLKs Every frame
Vertical Display Start Lines Every frame
Vertical Display End Lines Every frame
Interlaced Input Detect N/A Every frame
CRC Data/Line Data N/A Every frame
CSYNC Detect N/A Every 80ms

Page 49 of 82

The display start/end registers store the first and the last pixels/lines of the last frame that have RGB data
above a programmed threshold.
The reference point of the STM block is the same as that of the source timing generator (STG) block:
z The first pixel: the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to

high.

z The first line: the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low to

high.

The CRC data and the line data are used to detect a test pattern image sent to the gmZAN2 input port.

2.4.2 IRQ Controller

Some input timing conditions can cause the gmZAN2 chip to generate an IRQ. The IRQ-generating
conditions are programmable, as given in the following table.

Table 12. IRQ-Generation Conditions

IRQ Event Remark

Timing Event One of the three events:

z Leading edge of Vsync input,
z Panel line count (the line count is programmable),
z Every 10ms

Only one event may be selected at a time.

Timing Change Any of the following timing changes:

z Sync loss,
z DDS tracking error beyond threshold,
z Horizontal/vertical timing change beyond threshold

Threshold values are programmable.

Reading the IRQ status flags will not affect the STM registers.
Note that if a new IRQ event occurs while the IRQ status register is being read, the IRQ signal will become
inactive for minimum of one TCLK period and then get re-activated. The polarity of the IRQ signal is
programmable.

2.5 Data Path

The data path block of gmZAN2 is shown in Figure 6.

Figure 6. gmZAN2 Data Path

Sampled Data

(or from

pattern

generator

8 8 10

Scaling

Filter

Gamma

Table

RGB

Offset

Panel

Dither

Background

Color

Internal

OSD

External

OSD

Data

8 or 6

1

0

S

1

0

S

8 or 6

1

0

S

Panel
Data

Page 50 of 82

2.5.1 Scaling Filter

The gmZAN2 scaling filter uses an advanced adaptive scaling technique proprietary to Genesis Microchip
Inc. and provides high quality scaling of real time video and graphics images. This is Genesis’ third
generation scaling technology that benefits from the expertise and feedback gained by supporting a wide
range of solutions and applications.

2.5.2 Gamma Table

The gamma table is used to adjust the RGB data for the individual display characteristics of the TFT panel.
The overall gamma of the display may be set, as well as separate corrections for each of the three display
channels. In addition, the gamma table may be used for contrast, brightness, and white balance
(temperature) adjustments. The lookup table has an 8-bit input (256 different RGB entries) and produces a
10-bit output.

2.5.3 RGB Offset

The RGB offsets provide a simple shift (positive or negative) for each of the three color channels. This may
be used as a simple brightness adjustment within a limited range. The data is clamped to zero for negative
offsets, and clamped to FFh for positive offsets. This adjustment is much faster than recalculating the
gamma table, and could be used with the OSD user controller to provide a quick brightness adjust. An
offset range of plus 127*4 to minus 127*4 is available.

2.5.4 Panel Data Dither

For TFT panels that have fewer than eight bits for each R,G,B input, the gmZAN2 provides ordered and
random dithering patterns to help smoothly shade colors on 6-bit panels.

2.5.5 Panel Background Color

A solid background color may be selected for a border around the active display area. The background
color is most often set to black.

2.6 Panel Interface

The gmZAN2 chip interfaces directly with all of today’s commonly used active matrix flat panels with
640x480, 800x600 and 1024x768 resolutions. The resolution and the aspect ratio are NOT limited to
specific values.

2.6.1 TFT Panel Interface Timing Specification

The TFT panel interface timing parameters are listed in Table 13 below. Refer to three timing diagrams of
Figure 7 and Figure 8 for the timing parameter definition. All aspects of the gmZAN2 interface are
programmable. For horizontal parameters, Horizontal Display Enable Start, Horizontal Display Enable End,
Horizontal Sync Start and Horizontal Sync End are programmable. Vertical Display Enable Start, Vertical
Display Enable End, Vertical Sync Start and Vertical Sync End are also fully programmable.
In order to maximize panel data setup and hold time, the panel clock (PCLKA, PCLKB) output skew is
programmable. In addition, the current drive strength of the panel interface pins is programmable.

Page 51 of 82

Table 13. gmZAN2 TFT Panel Interface Timing

Signal Name Min Typical Max Unit

PVS

PHS

PCLKA,
PCLKB*4

Data

NOTE: Numbers in [ ] are for two pixels/clock mode.
NOTE: The drive current of the panel interface signals is programmable as shown in Table 1. The
drive current is to be programmed through the API upon chip initialization. Output current is
programmable from 2 mA to 20mA in increments of 2 mA. Drive strength should be programmed to
match the load presented by the cable and input of the panel. Values shown are based on a loading of
20pF and a drive strength of 8 mA.
NOTE *1: The PCLK is the panel shift clock.
NOTE *2: The DCLK stands for Destination Clock (DCLK) period. Is equal to:

-PCLK period in one pixel/clock mode,

-twice the PCLK period in two pixels/clock mode.
NOTE *3: The setup/hold time spec. for PCLK also applies to PHS and PdispE. The setup time (t16)

NOTE *4: The polarity of the PCLKA and the PCLKB are independently programmable.

The micro controller must have all the timing parameters of the panel used for the monitor. The
parameters are to be stored in a non-volatile memory. As can be seen from this table, the wide range
of timing programmability of the gmZAN2 panel interface makes it possible to support various kinds of
panels known today:

(a) Vertical size in TFT

PVS

Period t1 0 16.67 2048 - lines

ms
Frequency 60 - Hz
Front porch t2 0 2048 lines
Back porch t3 0 2048 lines
Pulse width t4 0 2048 lines
PdispE t5 0 Panel height 2048 lines
Disp. Start from
VS
PVS set up tp
PHS
PVS hold from
PHS
Period t7 0 2048 [1024 PCLK *1
Front porch t8 0 2048 PCLK *1
Back porch t9 0 2048 PCLK *1
Pulse width t10 0 2048 PCLK *1
PdispE t11 0 Panel width 2048 [1024] PCLK *1
Disp. Start fom
HS
Frequency t13 120 [60] MHz
Clock (H) *2 t14 DCLK/2-3 [DCLK-3] DCLK/2-2 [DCLK-2] ns
Clock (L) *2 t15 DCLK/2-3 [DCLK-3] DCLK/2-2 [DCLK-2] ns
Type - One pxl/clock

Set up *3 t16 DCLK/2-5 [DCLK-5] DCLK/2-2 [DCLK-2] ns
Hold *3 t17 DCLK/2-5 [DCLK-5] DCLK/2-2 [DCLK-2] ns
width 3 bits 18 bits [36

and the hold time (t17) listed in this table are for the case in which no clock-to-data skew is
added. The PVS/PHS/PdispE/Pdata signals are asserted on the rising edge of the PCLK. The
polarity of the PCLK and its skew are programmable. Clock to Data skew can be adjusted in
sixteen 800-ps increments. In combination with the PCLK polarity inversion, the clock-to-data
phase can be adjusted in total of 31 steps.

Figure 7. timing Diagrams of the TFT Panel Interface (One pixel per clock)

t6 0 2048 lines

t18 1 2048 PCLK *1

t19 1 2048 PCLK *1

t12 0 2048 PCLK *1

-

[two pxl/clock]

24 bits [48 bits] bits/pixel

bits]

Page 52 of 82

t1

PHS

(b) Vsync width and display position in TFT

PVS

PHS

RGBs

t18

t4

t19

(c) Horizontal size in TFT

PHS

PCLK

PDE

RGB data from
data paths

t12

Panel Background Color Displayed

(d) Hsync width in TFT

t13

t16

t6

t10

t7

t11

t8

t9

t10

t16

t14

t15

Page 53 of 82

Figure 8. Data latch timing of the TFT Panel Interface

(a) Two pixel per clock mode in TFT

t14

R2,(N:0)

G2,(N:0)

t13

t15

t16

R4,(N:0)

t17

PDE

PCLK

ER

EG

t16

R0,(N:0)

G0,(N:0)

EB

B0,(N:0)

B2,(N:0)

OR

OG

R1,(N:0)

G1,(N:0) G3,(N:0)

R3,(N:0)

OB

B1,(N:0)

B3,(N:0)

(b) One pixel per clock mode in TFT

t15

t16

t17

PDE

PCLK

R(n:0)

t16

R0

t13

t14

R1

G(n:0)

G0

B(n:0)

B0

2.6.2 Power Manager

LCD panels require logic power, panel bias power, and control signals to be sequenced
in a specific order, otherwise severe damage may occur and disable the panel
permanently. The gmZAN2 has a built in power sequencer (Power Manager) that
prevents this kind of damage.
The Power Manager controls the power up/down sequences for LCD panels within the
four states described below. See the timing diagram Figure 9.

Page 54 of 82

2.6.2.1 State 0 (Power Off)

The Pbias signal and Ppower signal are low (inactive). The panel controls and data are forced low. This is
the final state in the power down sequence. PM is kept in state 0 until the panel is enabled.

2.6.2.2 State 1 (Power On)

Intermediate step 1. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is
forced low (inactive).

2.6.2.3 State 2 (Panel Drive Enabled)

Intermediate step 2. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is
active.

2.6.2.4 State 3 (Panel Fully Active)

This is the final step in the power up sequence, with Ppower and Pbias high (active), and the panel
interface active. PM is kept in this state until the internal TFT_Enable signal controlled by Panel Control
register is disabled. The panel can be disabled through either an API call under program control or
automatically by the gmZAN2 to prevent damage to the panel.

Figure 9. Panel Power Sequence

In Figure 9 above, t2=t6 and t3=t5. t1,t2,t3 and t4 are independently programmable from one to eight
steps in length. The length of each step is in the range of 511 * X* (TCLKi cycle) or (TCLKi cycle) *
32193 *X, where X is any positive integer value equal to or less than 256. TCLKi is the reference clock
to the gmZAN2 chip, and ranges from 14.318 MHz to 50 MHz in frequency. This programmability
provides enough flexibility to meet a wide range of power sequencing requirements by various panels.

TFT_EN Bit
(register bit)

PPWR Output

Data/Controls Signals

PBias Output

t1

t4

t6

t2

t5

t3

<State3>

<State2>

<State1><State2><State0>

<State0><State1>

Page 55 of 82

2.6.3 Panel Interface Drive Strength

As mentioned previously, the gmZAN2 has programmable output pads for the TFT panel interface. Three
groups of panel interface pads (panel clock, data, and control) are independently controllable and are
programmed using API calls. See the API reference manual for details.

Table 14. Panel Interface Pad Drive Strength

Value (4 bits) Drive Strength in mA

0 Outputs are in tri-state condition
1 2mA
2 4mA
3 6mA
4 8mA
5 10mA
6 12mA
7 14mA
8 16mA
9 18mA
10,11,12,13,14,15 20mA

2.7 Host Interface

The host microcontroller interface of the gmZAN2 has two modes of operation: gmB120 compatible mode,
and a 4-bit serial interface mode.
z GmB120 compatible mode-Four signals consisting of 1 data bit, a frame synchronization signal, a

clock signal and an Interrupt Request signal (IRQ). This mode is entered when a pull-down resistor is
not connected to MFB6(pin number 106).

z 4-bit serial interface mode-Same as gmB120 compatible mode with the addition of three data bits so

that four data bits are transferred on each clock edge. This mode is entered when a (10K ohm) pull­down resistor is connected to MFB6(pin number 106).

When the chip is configured for 4-bit host interface, MFB9:7 are used as HDATA3:1 and HDATA is used as
HDATA0. For instruction, Read Data, or Write Data, the data order is D3:0, D7:4, D11:8, The burst mode
operation then uses three clocks (instead of twelve) for each 12-bit data (or address) transmission.

In both modes, a reset pin sets the chip to a known state when the pin is pulled low. The RESETn pin must
be low for at least 100ns after the CVDD has become stable (between +3.15V and +3.45V) in order to reset
the chip to a known state.

The gmZAN2 chip has an on-chip pull-down resistor in the HFS input pad. No external pull-up is required.
The signal stays low until driven high by the microcontroller.

Page 56 of 82

2.7.1 Serial Communication Protocol

In the serial communication between the microcontroller and the gmZAN2, the microcontroller always acts
as an initiator while the gmZAN2 is always the target. The following timing diagram describes the protocol
of the serial channel of the gmZAN2 chip.

Figure 10. Timing Diagram of the gmZAN2 Serial Communication

Page 57 of 82

Table 15 summarizes the serial channel specification of the gmZAN2. Refer to Figure 10 for the timing
parameter definition.

Table 15. gmZAN2 Serial Channel Specification

Parameter Min. Typ. Max.

Word Size (Instruction and Data) --- 12 bits --­HCLK low to HFS high (t1) 100 ns
HFS low to HCLK inactive (t2) 100 ns
HDATA Write to Read Turnaround Time
(t3)
HCLK cycle (t4) 100 ns
Data in setup time (t5) 25 ns
Data in hold time (t6) 25 ns
Data out valid (t7) 5 ns 10

In the read operation, the microcontroller (Initiator) issues an instruction lasting 12 HCLKs. After the last bit
of the command is transferred to the gmZAN2 on the 12
before the next rising edge of HCLK at which point the gmZAN2 will start driving data. At the 13
edge of HCLK, the gmZAN2 will begin driving data.

Figure 11. Serial Host Interface Data Transfer Format

2 bits 10 bits 12 bits

1 HCLK cycle 1 HCLK cycle

th

clock, the microcontroller must stop driving data

th

rising

Command Address Data

Command: 01 Write 00 = Read 1x = Reserved

Note that when the chip is configured for a 4-bit host interface, MFB9:7 are used as HDATA 3:1 and
HDATA is used as HDATA0. The command and address information are transferred as Address
1:0+Command1:0, Address5:2 and Address9:6. The data information is transferred as Data3:0,Data 7:4,
Data 11:8. Thus, in this mode the HDATA pin carries Command0, Address2, Address6, Data0, Data4 and
Data8.
On the gmZAN2 reference design board, the microcontroller toggles the HCLK and HDATA lines under
program control. Genesis Microchip provides API calls to facilitate communication between the
microcontroller and the gmZAN2. Refer to the API reference manual for details.

2.7.2 Multi-Function Bus (MFB)

The Multi-Function Bus provides additional 12 pins that are used as general purpose input and output
(GPIO) pins. Each pin can be independently configured as input or output.
MFB pins 9 through 5 have special functions:
z When a 10K ohm pull-down resistor is connected to MFB6 (MFB6 has an internal pull-up resistor)

MFB9:7 are used as host data bits HDATA3:1.

z When a 10K ohm pull-down resistor is connected to MFB5 (MFB5 has an internal pull-up resistor) a

crystal can be placed between XTAL and TCLK instead of using an external oscillator for the TCLK
input.

Note that all pins on the multi-function bus MFB11:0 are internally pulled-up.

2.8 On-Screen Display Control

The gmZAN2 chip has a built-in OSD (On-Screen Display) controller with an integrated font ROM. The chip
also supports an external OSD controller for monitor vendors to maintain a familiar user interface.
The internal and external OSD windows may be displayed anywhere the panel Display Enable is active,
regardless of whether the panel would otherwise display panel background color or active data.

Page 58 of 82

2.8.1 OSD Color Map

Both the internal and external OSD display use a 16 location SRAM block for the color programming. Each
color location is a twelve-bit value that defines the upper four bits of each of the 8 bit Red, Blue and Green
color components as follows:

z D3:0 Blue; D7:4 of blue component of color
z D7:4 Green; D7:4 of green component of color
z D11:8 Red; D7:4 of red component of color

To extend the 4-bit color value programmed to the full 8 bits the following rule is applied: if any of the upper
four color bits are a “1”, then R (G, B) data 3:0=1111b, otherwise R (G, B) data 3:0=0000b

2.8.2 On-Chip OSD Controller

The internal OSD uses a block of SRAM of 1536x12 bits and a ROM of 1024x12 bits. The SRAM is used
for both the font data and the character-codes while the ROM is used to store the bit data for 56 commonly
used characters. The font data is for 12 pixel x 18 line characters, one bit per pixel. The font data starts at
address zero. The character-codes start at any offset (with an address resolution of 16) that is greater than
the last location at which font data has been written . It is the programmer’s responsibility to ensure that
there is no overlap between fonts and character-codes. This implementation results in a trade-off between
the number of unique fonts on-screen at any one time and the total number of characters displayed. For
example, one configuration would be 98 font maps (56 fonts in ROM and 42 fonts in SRAM) and 768
characters (e.g. in a 24x32 array).

The on-chip OSD of the gmZAN2 can support a portrait mode (in which the LCD monitor screen is rotated
90 degrees). In this portrait mode, all the fonts must be loaded in the SRAM, because the ROM stores fonts
for a landscape mode (typical orientation) only. The font size in the portrait mode is 12 pixels by 12 lines.
As is the case in landscape mode, the SRAM is divided into a font storage area and a character code
storage area. For example, 64 fonts can be stored in RAM and an OSD window of 768 characters (such as
24x32) can still be displayed.

The first address of SRAM to be read for the first character displayed (upper left corner of window)is also
programmable, with an address resolution of 16 (8-bits as the top bits of the 12-bit SRAM address). The
character-code is a 12-bit value used as follows:

z D6:0 font-map select, this is the top seven bits of the address for the first line of font bits
z D8:7 Background color, 00=bcolor0, 01=bcolor1, 10=bcolor2, 11=transparent background
z D10:9 Foreground color (0, 1, 2 or 3)
z D11 Blink enable if set to 1, otherwise no blink

Although the OSD color map has room for sixteen colors, only seven are used by the internal OSD: three
background colors and four foreground colors.

The blink rate is based on either a 32 or 64 frame cycle and the duty cycle may be selected as
25/75/50/50% or 75/25%. The 2-bit foreground and background attributes directly select the color (there is
no indirect “look-up”, i.e. there is no TMASK function). The 2560 addresses of the ROM/SRAM are mapped
as 10 segments of 256 contiguous addresses each, to the OSD memory page of 100h-1FFh in the host
interface. A 4-bit register value selects the segment to map to the host R/W page.

The character cell height and width are programmable from 5-66 pixels or 2-65 lines. The X/Y offset of the
font bit-map upper-left pixel relative to the upper-left pixel of the character cell is also programmable from 0­63 (pixels or lines). The OSD window height and width in characters/rows is programmable from 1-64.

The Start X/Y position for the upper left corner of the OSD window is programmable (in panel pixels and
lines) from 0-2047. There is an optional window border (equal width on all four sides of the window) or a
window shadow (the window bottom and right side) the border is a solid color that is selected by an SRAM
location as RGB444. The border width may be set as 1, 2, 4 or 8 pixels/lines. These parameters are
summarized in Figure 12 and Table 16.
The Font Data D11:0 for each line is displayed with bit D11 first (leftmost) and D0 last.
The reference point for the OSD start is always the upper left corner of the Panel display, which is the start
(leading edge) of Panel Display Enable for both Horizontal and Vertical timing.

The OSD Window start position sets the location of the first pixel of the OSD to display, including any
border. That is; if the border is enabled, the start of the character display of the OSD is offset from the OSD
start position by the width/height of the border.

Page 59 of 82

To improve the appearance and make it easy to find the OSD window on the screen, the user may select
optional shadowing (3D effect). The “Shadow” feature operates in the same manner as in the B120; that is,
it produces a region of half intensity (scaler data) pixels of the same width and height as the OSD window,
but offset to the right and down by 8 pixels/lines (the border width setting has no effect). OSD foreground
and background colors always cover the OSD window region of the “shadow”, but transparent background
pixels in the OSD will show the half intensity panel data. Therefore, it is not recommended to use both the
“shadow” feature and transparent background OSD pixels together. The ”shadow” does not
intensity of any panel background color over which it may be located. The border and shadow are mutually
exclusive, only one may be selected at a time.

The OSD window is not affected by the scaling operation. The size will stay the same whether the source
input data is scaled or not.

change the

2.9 TCLK Input

The source timing is measured by using the TCLK input as a reference. Also, the reference clock to the on­chip PLLs are derived from the TCLK. It is therefore crucial to have a jitter-free clock reference.
Table 19 shows the requirements for the TCLK signal.

Table 19. TCLK Specification

Frequency 20 MHz to 50 MHz
Jitter 250 ps maximum
Rise Time (10% to 90%) 5 ns
Duty Cycle 40-60

There is also an option to use a crystal (instead of an oscillator) for the TCLK input. This option is selected
by pulling down MFB5 and connecting the crystal between XTAL and TCLK.

Page 60 of 82

3. ELECTRICAL CHARACTERISTICS

Table 20. Absolute Ratings

Parameter Min. Typ. Max. Note

PVDD 5.6 volts
CVDD 5.6 volts
Vin Vss-0.5 volt Vcc+0.5V
Operating temperature 0 degree C 70 degree C
Storage temperature -65 degree C 150 degree C
Maximum power consumption ~2W

Table 21. DC Electrical Characteristic

Parameter Min. Typ. Max. Note

PVDD 3.15 volts 3.3 volts 3.47 volts
CVDD 3.15 volts 3.3 volts 3.47 volts
Vil (COMS inputs)
Vil (TTL inputs)
Vih (COMS inputs)
Vih (TTL inputs)
Voh 2.4 volts CVDD
Vol 0.2 volts 0.4 volts
Input Current -10 uA 10 uA
PVDD operating supply current 0 mA 20 mA/pad @ 10pF (2)
CVDD operating supply current 0 mA 500 mA (3)
NOTE 1:5V-Tolerent TTL Input pads are as follows:

z CRT Interface: HSYNC (pin #150), VSYNC (#148)
z Host Interface: HFS (#98), HCLK (#103), HDATA (#99), RESETN (#100), MFB[11:0]: MFB11 (#123),

MFB10 (#124), MFB9 (#102), MFB8 (#104), MFB7 (#105), MFB6 (#106), MFB5 (#107), MFB4 (#109),
MFB3 (#110), MFB2 (#111), MFB1 (#112), MFB0 (#113)

z OSD Interface: OSD_DATA3 (#121), OSD_DATA2 (#120), OSD_DATA1 (#119), OSD_DATA0 (#118),

OSD_FSW (#122)
z Non-5V-Tolerant TTL Input Pad is: TCLK(#141)
NOTE 2: When the panel interface is disabled, the supply current is 0 mA. The drive current of each pad
can be programmed in the range of 2 mA to 20 mA (@capacitive loading = 10 pF)
NOTE 3: When all circuits are powered down and TCLK is stopped, the CVDD supply current becomes 0
mA.

7. MECHANICAL OF CABINET FRONT DIS-ASSEMBLY

For temporary, this page still not available.

Wait for mechanical drawing !

0.3*CVDD

0.8 volts

0.7 * CVDD

2.0 volts

1.1*CVDD

5.0+0.5 volts

(1)

Page 61 of 82

8.PARTS LIST OF CABINET

T782KKYMKFMNN

ADPC12416AB LCD ADAPTER ASS'Y M 1 PCS
CBPC782KKYA5 CONVERSION BOARD FOR T M 1 PCS
DCPC780A7 DC POWER BOARD FOR T780 M 1 PCS
IN7425A1 LCD INVERTER BOARD M 1 PCS
KEPC781KA1 KEY BOARD FOR T781K*SNI M 1 PCS
7L 1 20 WOODEN PALLET P 0.025 PCS
15L5689 1 A GND LUG (AL) P 2 PCS
15L5689 2 A GND CLAMP P 1 PCS
15L5695 1 REAR BRACKET P 1 PCS
15L5709 2 MAIN BRACKET P 1 PCS
33L4344 DC 1L HINGE COVER(L) P 1 PCS
33L4344 DC 2L HINGE COVER (R) P 1 PCS
33L4345 DC L CABLE COVER P 1 PCS
33L4362 1 LENS P 1 PCS
33L4401 AX L POWER KEY PAD P 1 PCS
34L 952BDC L FRONT PANEL P 1 PCS
40L 190767 3B ID LABEL P 1 PCS
40L 581 26704
40L 581689 4A SERIAL LABEL FOR MONITO P 1 PCS
40L 581724 1A CARTON LABEL P 2 PCS
41L 68508 A
41L1700767 4A MANUAL P 1 PCS
44L3231 12 EVA WASHER P 1 PCS
44L3265 1 EPSCUSHION(L) P 1 PCS
44L3265 2 EPS CUSHION P 1 PCS
44L3265767 2B CARTON P 1 PCS
44L6000 4 5B
44L9003210
45L 76 28 RN PE BAG for MANUAL/BASE P 1 PCS
45L 77 3
45L 77500 BARCODE RIBBON P 19 CM
45L 77501 BARCODE RIBBON P 0.5 CM
45L 88606 PE BAG FOR BASE P 1 PCS
45L 88607 PE BAG FOR MONITOR P 1 PCS
50L 600 2 HANDLE1 P 1 PCS
50L 600 3 HANDLE2 P 1 PCS
51L 2 14
52L 1185 MIDDLE TAPE FOR CARTON P 120 CM
52L 1186 SMALL TAPE P 8 CM
52L 1208 A ALUMINIUM TAPE P 2 PCS
52L6019 1
52L6020 1 PROTECT FILM P 0 PCS
79L L17 3 S INVERTER SAMPO P 0 PCS

唛头纸　FOR CARTON/PALLET

管制卡

隔板
护角板

打包膜

热熔胶

黄色绝缘胶带

P 0.1 PCS

P 0.1 PCS

P 0.025 PCS

P 0.01 PCS

P 173 CM

P 0.4 G

P 15 CM

Page 62 of 82

85L 594 1 SHIELD MAIN P 1 PCS
89L 174L1710A SIGNAL CABLE P 1 PCS
89L402A18N IS POWER CORD P 0 PCS
89L402A18N YH POWER CORD P 1 PCS
95L8014 5 14 HARNESS P 1 PCS
95L8018 30 5 HARNESS P 1 PCS
B1L1030 5128 SCREW P 5 PCS
M1L 330 6128 SCREW P 10 PCS
M1L1030 10128 SCREW P 4 PCS
M1L1740 12128 SCREW P 4 PCS
Q1L 340 12128 SCREW P 8 PCS
Q1L 340 16128 SCREW P 4 PCS
Q1L1030 10128 SCREW P 2 PCS
750LLK70300 Hydis 17" PANEL(-300) P 1 PCS
705L782KB34035

BD901 93L 50460502 KBP206G P 1 PCS

ADPC12400AAI LCD ADAPTER ASS'Y FOR A M 1 PCS
ADPC12400ASMT LCD ADAPTER ASS'Y FOR S M 1 PCS
ADPC12416AB6 LCD ADAPTER A6 ASS'Y X 1 PCS

GND1 9L6002 1 PIN P 1 PCS

40L 581700 6A LABEL P 1.05 PCS
51L 6 4500
51L 6 4502
51L 6 4503
52L 1213600 COPPER TAPE P 1 PCS

IC903 56L 139 3A PC123Y22 P 1 PCS

IC903 56L 139 3B PC123 Y82 P 0 PCS

C901 63L 107334 5 0.33UF 275VAC P 0 PCS

C901 63L107K334 U MPX 0.33UF,275VAC,+-10% P 1 PCS

C902 65L305M1022E3 1000PF +-20% 400VAC BY P 0 PCS

C903 65L305M1022E3 1000PF +-20% 400VAC BY P 0 PCS

C902 65L305M1022EM 1000PF +-20% 250VAC/400 P 1 PCS

C903 65L305M1022EM 1000PF +-20% 250VAC/400 P 1 PCS

C916 65L306M3322F2 3300PF +-20% 400VAC Y1 P 1 PCS

C900 65L306M4722B2 4700PF +-20% 400VAC Y1 P 1 PCS

C921 67L 215102 3H 1000UF +-20% 16V P 1 PCS

C922 67L 215102 3H 1000UF +-20% 16V P 1 PCS

C921 67L 215102 3K 1000UF +-20% 16V P 0 PCS

C922 67L 215102 3K 1000UF +-20% 16V P 0 PCS

C906 67L305L101 4 100UF +-20% 25V P 1 PCS

C904 67L305S10114H 100UF +-20% 400V P 0 PCS

C904 67L305S10114K

71L 55 2 A FERRITE BEAD 6.5*5*1.7 P 1 PCS
71L 55 30 FERRITE BEAD 4.0*2*3 P 1 PCS

L901 73L 174 26 T1 LINE LILTER 0.45mm P 1 PCS

L902 73L 253 91 H CHOKE COIL P 0 PCS

L902 73L 253 91 L CHOKE BY LI TA P 0 PCS

LCD 后壳 ASS'Y

RTV胶
RTV胶
RTV胶

E.C 105　 CAP

X 1 PCS

P 0 G

P 2 G

P 0 G

P 1 PCS

Page 63 of 82

L902 73L 253 91 S CHOKE COIL P 1 PCS

T901 80L 600 3 L X'FMR BY LI TAI P 0 PCS

T901 80L 600 3 T SRW28EC-T40H017 P 1 PCS

LED1 81L 2 3 2P LED P 1 PCS

F901 84L 53 1 FUSE 2A 250V LF-230002 P 0 PCS

F901 84L 7H200 NL FUSE 2Z 250V HL-50T 2A P 1 PCS

F901 84L 7H200 SL 250V/2A LIHEL FUSE P 0 PCS

CN901 87L 501 10 AC SOCKET P 1 PCS

CN901 87L 501 10 CJ AC SOCKET P 0 PCS
89L 171505 DC POWER CORD P 1 PCS

BD901 93L 50460 8 BRIDGE 2KBP06M2A600V P 0 PCS

D901 93L 6026T52T RECTIFIER DIODE FR107 P 1 PCS

D901 93L 6026W52T FR107 P 0 PCS

D902 93L 6038P52T PS102R P 1 PCS

D902 93L 6038T52T FR103 P 0 PCS

96L 29 8 TUBE P 1 PCS
705L 560 61 04 NR901 ASS'Y X 1 PCS

R911 705LAD17 61 02 R911 ASS'Y X 1 PCS

715L 901 1 4 ADAPTOR P 1 PCS
705L 560 57 03 Q901 ASS'Y X 1 PCS
705L 560 61 03 R930 ASS'Y X 1 PCS
705L 780 93 03 D911 ASS'Y X 1 PCS

L901 6L 31502 1.5MM RIVET P 4 PCS

T901 6L 31502 1.5MM RIVET P 4 PCS
715L 901 3 3 PCB BOARD P 1 PCS

J901 95L 90 23 TIN COATED P 0 PCS

J902 95L 90 23 TIN COATED P 0 PCS

J903 95L 90 23 TIN COATED P 0 PCS

J904 95L 90 23 TIN COATED P 0 PCS

J905 95L 90 23 TIN COATED P 0 PCS

R919 61L 21024352T MFR 24K OHM +- 1% 1/6W P 1 PCS

R925 61L 60220252T CFR 2K OHM+-5% 1/6W P 1 PCS

FB901 71L 55 19 T FERRITE BEAD 9X3.5X0.8 P 1 PCS

IC902 56L 158 2 T 3PIN IC TL431C/T.I. P 0 PCS

IC905 56L 158 2 T 3PIN IC TL431C/T.I. P 0 PCS

IC902 56L 158 4 T A HTL431 P 1 PCS

IC905 56L 158 4 T A HTL431 P 1 PCS

C905 65L 1K152 1T6052 1.5NF/1KV Z5F+-10% P 1 PCS

C905 65L 1K152 1T6285 1.5NF/1KV Z5F+-10% P 0 PCS

C905 65L 1K152 1T6921 1.5NF/1KV Z5F+-10% P 0 PCS

C920 65L517K681 2T6052 680PF 500V +-10% 25P P 0 PCS

C920 65L517K681 2T6213 680PF 500V +-10% 25P P 1 PCS

C920 65L517K681 2T6285 680PF 500V +-10% 25P P 0 PCS

C923 67L 305471 3T 470UF 16V P 1 PCS

IC901 56L 379 25 UC3842ADM P 1 PCS

Q903 57L 417 4 PMBS3904/PHILIPS-SMT(04 P 1 PCS

Q902 57L 417 6 PMBS3906/PHILIPS-SMT(06 P 1 PCS

Page 64 of 82

R928 61L0603102 CHIPR 1K OHM +-5% 1/10W P 1 PCS

R937 61L0603243 1F CHIPR 2.43KOHM+-1% 1/10 P 1 PCS

R936 61L0603931 1F CHIPR 9.31KOHM+-1% 1/10 P 1 PCS

R924 61L0805102 CHIPR 1K OHM +-5% 1/8W P 1 PCS

R929 61L0805102 CHIPR 1K OHM +-5% 1/8W P 1 PCS

R935 61L0805102 CHIPR 1K OHM +-5% 1/8W P 1 PCS

R927 61L0805103 CHIPR 10K OHM +-5% 1/8W P 1 PCS

R922 61L0805104 CHIPR 100K OHM+-5% 1/8W P 1 PCS

R915 61L0805471 CHIPR 470 OHM+-5% 1/8W P 1 PCS

R916 61L0805472 CHIRP 4.7K OHM +-5% 1/8 P 1 PCS

R917 61L0805472 CHIRP 4.7K OHM +-5% 1/8 P 1 PCS

R918 61L0805472 CHIRP 4.7K OHM +-5% 1/8 P 1 PCS

R920 61L0805623 CHIPR 62K OHM +-5% 1/8W P 1 PCS

R921 61L0805683 CHIPR 68K OHM+-5% 1/8W P 1 PCS

R923 61L1206100 CHIPR 10 OHM+-5% 1/4W P 1 PCS

R931 61L1206100 CHIPR 10 OHM+-5% 1/4W P 1 PCS

R932 61L1206100 CHIPR 10 OHM+-5% 1/4W P 1 PCS

R926 61L1206101 CHIP 100 OHM 5% 1/4W P 1 PCS

R912 61L1206129 CHIP 1.2OHM +-5% 1/4W P 1 PCS

R933 61L1206242 CHIPR 2.4K OHM+-5% 1/4W P 1 PCS

R938 61L1206242 CHIPR 2.4K OHM+-5% 1/4W P 1 PCS

R905 61L1206304 CHIP 300K OHM 1/4W P 1 PCS

R906 61L1206304 CHIP 300K OHM 1/4W P 1 PCS

R907 61L1206304 CHIP 300K OHM 1/4W P 1 PCS

R908 61L1206304 CHIP 300K OHM 1/4W P 1 PCS

R909 61L1206304 CHIP 300K OHM 1/4W P 1 PCS

R910 61L1206304 CHIP 300K OHM 1/4W P 1 PCS

R934 61L1206471 CHIPR 470 OHM+-5% 1/4W P 1 PCS

R901 61L1206684 CHIPR 680K OHM+-5% 1/4W P 1 PCS

R902 61L1206684 CHIPR 680K OHM+-5% 1/4W P 1 PCS

R903 61L1206684 CHIPR 680K OHM+-5% 1/4W P 1 PCS

R904 61L1206684 CHIPR 680K OHM+-5% 1/4W P 1 PCS

C913 65L0603101 31 CHIP 100PF 50V NPO P 1 PCS

C914 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C927 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C908 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C909 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C911 65L0603152 32 1500PF +-10% 50V X7R 06 P 1 PCS

C928 65L0805104 22 0.1UF +-10% 25V X7R 080 P 1 PCS

C929 65L0805104 22 0.1UF +-10% 25V X7R 080 P 1 PCS

C924 65L0805104 27 CHIP CAP 0.1uF 25V Y5V P 1 PCS

C912 65L0805105 12 1UF +-10% 16V X7R P 1 PCS

C915 65L0805474 27 CHIP 0.47UF 25V Y5V P 1 PCS

C926 65L0805474 27 CHIP 0.47UF 25V Y5V P 1 PCS

C910 65L1206102 31 1000PF +-5% 50V NPO 120 P 1 PCS

ZD901 93L 39151 MMSZ5248B-SMT P 1 PCS

D904 93L 64 32 LL4148 SMD P 0 PCS

Page 65 of 82

D905 93L 64 32 LL4148 SMD P 0 PCS

D904 93L 6432V LL4148-GS08 P 1 PCS

D905 93L 6432V LL4148-GS08 P 1 PCS

ZD901 93L 39S500 T 19VZENER PIODE P 0 PCS

33L6007 1 LENS P 1.01 PCS
40L 154501 1 HI-POT GND LABEL FOR MO P 1 PCS
40L416B615 1A ADAPTER ID LABEL P 1.02 PCS
45L 88525 E PE BAG P 1 PCS
W33L4477 B T TOP COVER P 1.01 PCS
W33L4478 B T BOTTOM COVER P 1.01 PCS

NR901 61L 58080 WT 8 OHM NCTR P 1 PCS
96L 29 10 SHRINR TUBE UL/CSA P 0.025 M

R911 61L152M10457F MOFR 100KOHM +-5% 2W P 1 PCS

96L 29 6 SHRINK TUBE UL/CSA P 1 PCS
51L 200 1

Q901 57L 724 4 2SK2996 P 1 PCS

Q901 57L 724 4A STP9NK60ZFP P 0 PCS

90L 396502 Q HEAT SINK P 1 PCS
M1L17306.5128 SCREW P 1 PCS

PARENT NO : 705L 560 61 03 R930 ASS'Y

R930 61L 2J47859B WIRE WOUND 0.47 OHM ZW P 1 PCS

96L 29 6 SHRINK TUBE UL/CSA P 1 PCS
51L 200 1
90L 396502 D HEAT SINK P 1 PCS

D911 93L 60226 STPS20H100CT P 1 PCS

D912 93L 60226 STPS20H100CT P 1 PCS

D911 93L 60227 MBR20100CT P 0 PCS

D912 93L 60227 MBR20100CT P 0 PCS

M1L1730 6128 SCREW M3x6 P 2 PCS
AIC782KKYA5 LCD MAIN BOARD FOR T782 M 1 PCS

CN303 33L3802 5H WAFER 5P RIGHT ANELE PI P 1 PCS

CN302 33L3802 9H WAFER 9P RIGHT ANELE PI P 1 PCS

R319 33L8009 2 2 PIN MIN.JUMOER P 1 PCS
33L8010 2 L 2PIN SHUNT MINI JUMPER P 1

CN200 33L8013 14 H PLUG 14P 90 P 1 PCS

CN603 33L801724A H PIN HEADER 24P 2.0mm P 1 PCS

40L 457624 1B CPU LABEL P 1 PCS
40L 45762412A CBPC LABEL P 1 PCS
44L3231 8 A EVA WASHER P 1 PCS
49L 51 1A
51L 6 4500
51L 6 4502
51L 6 4503
51L 500 1
51L6002 2
52L6026 1
52L6026 2

散热油

散热油

去渍油

RTV胶
RTV胶
RTV胶

白胶
促进剂
网版纸
网版纸

P 2 G

P 2 G

P 0.05 ML

P 0 G

P 0 G

P 3 G

P 3 G

P 0 ML

P 20 MM

P 20 MM

Page 66 of 82

55L 100600 A
55L 100600 B
55L 100605

U302 56L1125139K3E CPU P 1 PCS

C307 67L305L331 6 330UF +-20% 35V P 1 PCS

C309 67L305L331 6 330UF +-20% 35V P 1 PCS

C310 67L305L331 6 330UF +-20% 35V P 1 PCS

C312 67L305L331 6 330UF +-20% 35V P 1 PCS

C945 67L309L471 3 470UF+-20% 16V P 1 PCS

FB301 71L 55 28 FERRITE BEAD 7.62*5.08* P 1 PCS

L906 73L 253127 L CC-010730 P 1 PCS

L905 73L 259 4 200UH +/-5% P 1 PCS

VR501 75L 335103 CFVR 10K OHM +-20% P 1 PCS

X300 93L 22 55 H 20MHZ P 1 PCS

U201 93L 22 57 H 50MHZ OSCIL P 1 PCS

J1 95L 900 31 HARNESS P 1 PCS

U601 56L 561 5A M385 P 1 PCS

U602 56L 561 5A M385 P 1 PCS

U305 56L 563 7 AIC1084-33CM P 0 PCS

U905 56L 585 5 RT9164-25CG P 0 PCS

U904 56L 585 4A AP1117E33A P 1 PCS

U300 56L1133 24 AT24C16N-10SC-2.7 P 0 PCS

L200 71L 57G601 N CHIP BEAD P 0 PCS

L201 71L 57G601 N CHIP BEAD P 0 PCS

L202 71L 57G601 N CHIP BEAD P 0 PCS

L203 71L 57G601 N CHIP BEAD P 0 PCS

L300 71L 57G601 N CHIP BEAD P 0 PCS

L900 71L 57G601 N CHIP BEAD P 0 PCS

L601 71L 59B121 TB160808B12 SMD P 0 PCS

L602 71L 59B121 TB160808B12 SMD P 0 PCS

L603 71L 59B121 TB160808B12 SMD P 0 PCS

L604 71L 59B121 TB160808B12 SMD P 0 PCS

R215 71L 59B121 TB160808B12 SMD P 0 PCS

R237 71L 59B121 TB160808B12 SMD P 0 PCS

R238 71L 59B121 TB160808B12 SMD P 0 PCS

D200 93L 39146 LL5232B SMT P 0 PCS

D201 93L 39146 LL5232B SMT P 0 PCS

D208 93L 39146 LL5232B SMT P 0 PCS

D209 93L 39146 LL5232B SMT P 0 PCS

D210 93L 39146 LL5232B SMT P 0 PCS

D200 93L 39149 MLL5232B BY FULL POWER P 0 PCS

D201 93L 39149 MLL5232B BY FULL POWER P 0 PCS

D208 93L 39149 MLL5232B BY FULL POWER P 0 PCS

D209 93L 39149 MLL5232B BY FULL POWER P 0 PCS

D210 93L 39149 MLL5232B BY FULL POWER P 0 PCS

D300 93L 60211 SMB340 BY FULL POWER P 0 PCS

D300 93L 60212 SMB340 SMT P 0 PCS

防溅焊锡
锡丝
锡丝

P 0.3 G

P 0.3 G

P 9.1 G

Page 67 of 82

D303 93L 60219 BAT54C SMT P 0 PCS

D303 93L 60220 BAT54C-GS08 P 0 PCS

D202 93L 64 32 LL4148 SMD P 0 PCS

D203 93L 64 32 LL4148 SMD P 0 PCS

D204 93L 64 32 LL4148 SMD P 0 PCS

D205 93L 64 32 LL4148 SMD P 0 PCS

D206 93L 64 32 LL4148 SMD P 0 PCS

D207 93L 64 32 LL4148 SMD P 0 PCS

D301 93L 64 32 LL4148 SMD P 0 PCS

D302 93L 64 32 LL4148 SMD P 0 PCS

D202 93L 6432U MLL4148 SMD P 0 PCS

D203 93L 6432U MLL4148 SMD P 0 PCS

D204 93L 6432U MLL4148 SMD P 0 PCS

D205 93L 6432U MLL4148 SMD P 0 PCS

D206 93L 6432U MLL4148 SMD P 0 PCS

D207 93L 6432U MLL4148 SMD P 0 PCS

D301 93L 6432U MLL4148 SMD P 0 PCS

D302 93L 6432U MLL4148 SMD P 0 PCS

55L 23520 IPA P 0.06 ML
55L 100600 A
55L 100600 B
55L 100602 6461
55L 100602 6657

U601 56L 561 5 NT7181F P 0 PCS

U602 56L 561 5 NT7181F P 0 PCS

U200 56L 562 12 gmZAN2 P 1 PCS

U304 56L 563 11 SI-8050SD P 1 PCS

U305 56L 563 21 AP1084K33 P 1 PCS

U202 56L 566 6 SI9953DY-T1 P 1 PCS

U904 56L 585 4 AIC1117-33CY P 0 PCS

U905 56L 585 5A AP1117E25A P 1 PCS

U401 56L 74F 14 P N74F14D SMT P 1 PCS

U203 56L1133 16 24LC21A/SN P 1 PCS

U300 56L1133 33 M24C16-MN6T P 1 PCS

Q200 57L 417 4 PMBS3904/PHILIPS-SMT(04 P 1 PCS

Q304 57L 417 4 PMBS3904/PHILIPS-SMT(04 P 1 PCS

RP300 61L 125103 8 CHIP AR 8P4R 10KOHM +-5 P 1 PCS

RP301 61L 125472 8 CHIP AR 8P4R 4.7K OHM+- P 1 PCS

L207 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R203 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R207 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R208 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R221 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R229 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R232 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R233 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R234 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

防溅焊锡
锡丝
锡膏
锡膏

P 0.3 G

P 0.3 G

P 0.85 G

P 0 G

Page 68 of 82

R310 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R317 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R340 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R603 61L0603000 CHIPR 0OHM +-5% 1/10W P 1 PCS

R200 61L0603101 CHIPR 100 OHM +-5% 1/10 P 1 PCS

R201 61L0603101 CHIPR 100 OHM +-5% 1/10 P 1 PCS

R202 61L0603101 CHIPR 100 OHM +-5% 1/10 P 1 PCS

R218 61L0603101 CHIPR 100 OHM +-5% 1/10 P 1 PCS

R219 61L0603101 CHIPR 100 OHM +-5% 1/10 P 1 PCS

R220 61L0603101 CHIPR 100 OHM +-5% 1/10 P 1 PCS

R227 61L0603101 CHIPR 100 OHM +-5% 1/10 P 1 PCS

R216 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R217 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R223 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R224 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R225 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R300 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R301 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R311 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R313 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R315 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R326 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R327 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R328 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R329 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R333 61L0603202 CHIPR 2K OHM+-5% 1/10W P 1 PCS

R213 61L0603222 CHIPR 2.2K OHM+-5% 1/10 P 1 PCS

R214 61L0603222 CHIPR 2.2K OHM+-5% 1/10 P 1 PCS

R303 61L0603472 CHIPR 4.7K OHM +-5% 1/1 P 1 PCS

R204 61L0603750 CHIPR 75 OHM+-5% 1/10W P 1 PCS

R205 61L0603750 CHIPR 75 OHM+-5% 1/10W P 1 PCS

R206 61L0603750 CHIPR 75 OHM+-5% 1/10W P 1 PCS

JP202 61L1206000 CHIPR 0 OHM +-5% 1/4W P 1 PCS

JP303 61L1206000 CHIPR 0 OHM +-5% 1/4W P 1 PCS

L204 61L1206000 CHIPR 0 OHM +-5% 1/4W P 1 PCS

L205 61L1206000 CHIPR 0 OHM +-5% 1/4W P 1 PCS

C948 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C949 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C950 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C951 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C952 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C953 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C954 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C955 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C956 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C957 65L0603102 32 1000PF +-10% 50V X7R P 1 PCS

C229 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

Page 69 of 82

C230 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C231 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C232 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C233 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C234 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C251 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C606 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C608 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C614 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C616 65L0603103 32 0.01UF+-10% 50V X7R P 1 PCS

C201 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C202 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C204 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C205 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C207 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C208 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C209 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C210 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C211 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C212 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C213 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C215 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C217 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C218 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C219 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C220 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C221 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C222 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C223 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C225 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C226 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C227 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C228 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C237 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C244 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C245 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C246 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C300 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C304 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C308 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C311 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C405 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C601 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C602 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C604 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C618 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C619 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

Page 70 of 82

C939 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C940 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C941 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C942 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C944 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C946 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C947 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

JP301 65L0603104 12 0.1UF +-10% 16V X7R P 1 PCS

C303 65L0603220 31 CHIP 22PF 50V NPO P 1 PCS

C306 65L0603220 31 CHIP 22PF 50V NPO P 1 PCS

C250 65L0603330 31 33PF+-5% 50V NPO P 1 PCS

CP301 65L600M102 8T 1000PF+-20% 50V 8P X7R P 1 PCS

CP302 65L600M102 8T 1000PF+-20% 50V 8P X7R P 1 PCS

C605 67L 312100 3 SMD 10uf +-20% 16V P 1 PCS

C607 67L 312100 3 SMD 10uf +-20% 16V P 1 PCS

C613 67L 312100 3 SMD 10uf +-20% 16V P 1 PCS

C615 67L 312100 3 SMD 10uf +-20% 16V P 1 PCS

C620 67L 312100 3 SMD 10uf +-20% 16V P 1 PCS

C200 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C203 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C206 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C214 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C216 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C224 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C305 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C403 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C603 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C927 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C928 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C929 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C930 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C943 67L 312101 3 SMD 100UF +-20% 16V P 1 PCS

C313 67L 312220 3 SMD 22UF +-20% 16V P 1 PCS

C314 67L 312220 3 SMD 22UF +-20% 16V P 1 PCS

L200 71L 57G601 TI3216JIG601-T17A P 1 PCS

L201 71L 57G601 TI3216JIG601-T17A P 1 PCS

L202 71L 57G601 TI3216JIG601-T17A P 1 PCS

L203 71L 57G601 TI3216JIG601-T17A P 1 PCS

L300 71L 57G601 TI3216JIG601-T17A P 1 PCS

L900 71L 57G601 TI3216JIG601-T17A P 1 PCS

L601 71L 59C121 B FCM1608C-121T03 SMD P 1 PCS

L602 71L 59C121 B FCM1608C-121T03 SMD P 1 PCS

L603 71L 59C121 B FCM1608C-121T03 SMD P 1 PCS

L604 71L 59C121 B FCM1608C-121T03 SMD P 1 PCS

R215 71L 59C121 B FCM1608C-121T03 SMD P 1 PCS

R237 71L 59C121 B FCM1608C-121T03 SMD P 1 PCS

R238 71L 59C121 B FCM1608C-121T03 SMD P 1 PCS

Page 71 of 82

MTG U30 87L 202 44 PLCC SMT CONN PD41C-441 P 1 PCS

D200 93L 39147 TZMC5V6-GS08 P 1 PCS

D201 93L 39147 TZMC5V6-GS08 P 1 PCS

D208 93L 39147 TZMC5V6-GS08 P 1 PCS

D209 93L 39147 TZMC5V6-GS08 P 1 PCS

D210 93L 39147 TZMC5V6-GS08 P 1 PCS

D300 93L 60225 SK34B P 1 PCS

D303 93L 60230 BAT54C(L43) P 1 PCS

D202 93L 6432V LL4148-GS08 P 1 PCS

D203 93L 6432V LL4148-GS08 P 1 PCS

D204 93L 6432V LL4148-GS08 P 1 PCS

D205 93L 6432V LL4148-GS08 P 1 PCS

D206 93L 6432V LL4148-GS08 P 1 PCS

D207 93L 6432V LL4148-GS08 P 1 PCS

D301 93L 6432V LL4148-GS08 P 1 PCS

D302 93L 6432V LL4148-GS08 P 1 PCS

715L 820 2 2 TF-1780 LCD MAIN BOARD P 1 PCS
DCPC780A7AI DC POWER BOARD FOR AI M 1 PCS

J7 33L3252 3 H WAFER 3P 3.96MM 90 P 1 PCS

51L 6 4500
51L 6 4502
51L 6 4503

C71 67L305L331 6 330UF +-20% 35V P 1 PCS

JP2 88L 304 1S DC POWER JACK P 0 PCS

JP2 88L 3041CF DC JACK P 1 PCS

F01 95L 90 23 TIN COATED P 1 PCS

JP2 6L 31501

715L 919 2A (DC-IN) BOARD P 1 PCS
44L3521 1EPE EPE P 0 PCS
44L3521624 1A CARTON P 0 PCS
IN7425A1SMT LCD INVERTER BOARD FOR M 1 PCS

CON1 33L3802 5H WAFER 5P RIGHT ANELE PI P 1 PCS

40L 45762412A CBPC LABEL P 1.03 PCS
51L 6 4500
51L 6 4502
51L 6 4503
52L6025 5

C13 64L179J1841AT MKT CAP. 0.18UF+-5% 100 P 1 PCS

C14 64L179J1841AT MKT CAP. 0.18UF+-5% 100 P 1 PCS

C15 65L 3J2206EM 22PF 5% 3KV MURATA P 0 PCS

C16 65L 3J2206EM 22PF 5% 3KV MURATA P 0 PCS

C17 65L 3J2206EM 22PF 5% 3KV MURATA P 0 PCS

C18 65L 3J2206EM 22PF 5% 3KV MURATA P 0 PCS

C15 65L 3J2206ET 22PF 5% 3KV TDK P 1 PCS

C16 65L 3J2206ET 22PF 5% 3KV TDK P 1 PCS

C17 65L 3J2206ET 22PF 5% 3KV TDK P 1 PCS

C18 65L 3J2206ET 22PF 5% 3KV TDK P 1 PCS

RTV胶
RTV胶
RTV胶

铆钉

RTV胶
RTV胶
RTV胶

绝缘片

P 0 G

P 0 G

P 1 G

P 3 PCS

P 0 G

P 0 G

P 1 G

P 2 PCS

Page 72 of 82

C1 67L215C151 4H LOW ESR 150UF 25V 8*7MM P 1 PCS

C23 67L215C151 4H LOW ESR 150UF 25V 8*7MM P 1 PCS

L1 73L 253138 L CHOKE BY LI TAI P 0 PCS

L2 73L 253138 L CHOKE BY LI TAI P 0 PCS

L1 73L 253138 Y CHOKE P 1 PCS

L2 73L 253138 Y CHOKE P 1 PCS

CON2 33L8021 2 E WAFER SMT P 1 PCS

CON3 33L8021 2 E WAFER SMT P 1 PCS

CON4 33L8021 2 E WAFER SMT P 1 PCS

CON5 33L8021 2 E WAFER SMT P 1 PCS

CON2 33L8021 2 J WAFER 2P BHS BY JST-SMT P 0 PCS

CON3 33L8021 2 J WAFER 2P BHS BY JST-SMT P 0 PCS

CON4 33L8021 2 J WAFER 2P BHS BY JST-SMT P 0 PCS

CON5 33L8021 2 J WAFER 2P BHS BY JST-SMT P 0 PCS

Q3 56L 566 10 SI4431DY-T1-SMT P 0 PCS

Q4 56L 566 10 SI4431DY-T1-SMT P 0 PCS

U1 56L 622 1 BA9741F-SMT P 1 PCS

Q5 57L 417 4 PMBS3904/PHILIPS-SMT(04 P 1 PCS

Q6 57L 417 4 PMBS3904/PHILIPS-SMT(04 P 1 PCS

Q7 57L 417 6 PMBS3906/PHILIPS-SMT(06 P 1 PCS

Q8 57L 417 6 PMBS3906/PHILIPS-SMT(06 P 1 PCS

Q2 57L 760 1 FN1L4L P 0 PCS

Q1 57L 760 2 FA1L4L P 0 PCS

Q2 57L 760 4 DTA144WKA BY ROHM SMT(7 P 1 PCS

Q1 57L 760 5 DTC144WKA BY ROHM SMT(8 P 1 PCS

Q10 57L 761 2 2SC5706-TL-SMT P 1 PCS

Q11 57L 761 2 2SC5706-TL-SMT P 1 PCS

Q12 57L 761 2 2SC5706-TL-SMT P 1 PCS

Q9 57L 761 2 2SC5706-TL-SMT P 1 PCS

Q10 57L 761 3 2SC5824R SMT P 0 PCS

Q11 57L 761 3 2SC5824R SMT P 0 PCS

Q12 57L 761 3 2SC5824R SMT P 0 PCS

Q9 57L 761 3 2SC5824R SMT P 0 PCS

Q3 57L 763 3 AO4411 SO-8 BY AOS SMT P 1 PCS

Q4 57L 763 3 AO4411 SO-8 BY AOS SMT P 1 PCS

R2 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R3 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R4 61L0603103 CHIPR 10K OHM +-5% 1/10 P 1 PCS

R22 61L0603123 CHIP 12K OHM 1/10W P 1 PCS

R23 61L0603123 CHIP 12K OHM 1/10W P 1 PCS

R38 61L0603123 CHIP 12K OHM 1/10W P 1 PCS

R39 61L0603123 CHIP 12K OHM 1/10W P 1 PCS

R10 61L0603153 CHIPR 15KOHM+-5% 1/10W P 1 PCS

R11 61L0603153 CHIPR 15KOHM+-5% 1/10W P 1 PCS

R20 61L0603153 CHIPR 15KOHM+-5% 1/10W P 1 PCS

R21 61L0603153 CHIPR 15KOHM+-5% 1/10W P 1 PCS

R16 61L0603221 CHIPR 220 OHM+-5% 1/10W P 1 PCS

Page 73 of 82

R17 61L0603221 CHIPR 220 OHM+-5% 1/10W P 1 PCS

R1 61L0603303 CHIP 30K OHM 5% 1/10W P 1 PCS

R12 61L0603392 CHIP 3.9K OHM 1/10W P 1 PCS

R13 61L0603392 CHIP 3.9K OHM 1/10W P 1 PCS

R14 61L0603392 CHIP 3.9K OHM 1/10W P 1 PCS

R15 61L0603392 CHIP 3.9K OHM 1/10W P 1 PCS

R18 61L0603471 CHIPR 470 OHM+-5% 1/10W P 1 PCS

R19 61L0603471 CHIPR 470 OHM+-5% 1/10W P 1 PCS

R8 61L0603472 CHIPR 4.7K OHM +-5% 1/1 P 1 PCS

R9 61L0603472 CHIPR 4.7K OHM +-5% 1/1 P 1 PCS

R5 61L0603473 CHIP 47K OHM 1/10W P 1 PCS

R6 61L0603473 CHIP 47K OHM 1/10W P 1 PCS

R34 61L0603511 CHIPR 510 OHM+-5% 1/10W P 1 PCS

R35 61L0603511 CHIPR 510 OHM+-5% 1/10W P 1 PCS

R36 61L0603511 CHIPR 510 OHM+-5% 1/10W P 1 PCS

R37 61L0603511 CHIPR 510 OHM+-5% 1/10W P 1 PCS

R40 61L0603513 CHIP 51K OHM 1/10W P 1 PCS

R41 61L0603513 CHIP 51K OHM 1/10W P 1 PCS

F1 61L1206000 4 0 OHM 4A 1/4W P 1 PCS

R32 61L1206102 CHIP 1K OHM 5% 1/4W P 1 PCS

R33 61L1206102 CHIP 1K OHM 5% 1/4W P 1 PCS

R24 61L1206202 CHIP 2K 5% 1/4W P 1 PCS

R25 61L1206202 CHIP 2K 5% 1/4W P 1 PCS

R26 61L1206202 CHIP 2K 5% 1/4W P 1 PCS

R27 61L1206202 CHIP 2K 5% 1/4W P 1 PCS

R28 61L1206202 CHIP 2K 5% 1/4W P 1 PCS

R29 61L1206202 CHIP 2K 5% 1/4W P 1 PCS

R30 61L1206202 CHIP 2K 5% 1/4W P 1 PCS

R31 61L1206202 CHIP 2K 5% 1/4W P 1 PCS

C2 65L0805104 22 0.1UF +-10% 25V X7R 080 P 1 PCS

C3 65L0805104 22 0.1UF +-10% 25V X7R 080 P 1 PCS

C4 65L0805104 22 0.1UF +-10% 25V X7R 080 P 1 PCS

C5 65L0805104 22 0.1UF +-10% 25V X7R 080 P 1 PCS

C6 65L0805104 22 0.1UF +-10% 25V X7R 080 P 1 PCS

C10 65L0805105 27 CHIP 1UF 25V Y5V 0805 P 1 PCS

C11 65L0805105 27 CHIP 1UF 25V Y5V 0805 P 1 PCS

C12 65L0805105 27 CHIP 1UF 25V Y5V 0805 P 1 PCS

C19 65L0805105 27 CHIP 1UF 25V Y5V 0805 P 1 PCS

C20 65L0805105 27 CHIP 1UF 25V Y5V 0805 P 1 PCS

C9 65L0805105 27 CHIP 1UF 25V Y5V 0805 P 1 PCS

C8 65L0805331 32 CHIP 330PF 50V X7R 0805 P 1 PCS

C21 65L0805474 27 CHIP 0.47UF 25V Y5V P 1 PCS

C22 65L0805474 27 CHIP 0.47UF 25V Y5V P 1 PCS

C7 67L 312229 7 SMD 2.2UF +-20% 50V P 1 PCS

PT1 80LL17T 3 YS ADAPTOR BY YAO SHENG SM P 1 PCS

PT2 80LL17T 3 YS ADAPTOR BY YAO SHENG SM P 1 PCS

D7 93L 6432U MLL4148 SMD P 0 PCS

Page 74 of 82

D8 93L 6432U MLL4148 SMD P 0 PCS

D7 93L 6432V LL4148-GS08 P 1 PCS

D8 93L 6432V LL4148-GS08 P 1 PCS

D5 93L 6433G BAV99-SMT P 0 PCS

D6 93L 6433G BAV99-SMT P 0 PCS

D5 93L 6433P BAV99 P 1 PCS

D6 93L 6433P BAV99 P 1 PCS

D3 93L 39S 1 T TZMC11-GS08 P 0 PCS

D4 93L 39S 1 T TZMC11-GS08 P 0 PCS

D3 93L 39S 3 T BZT52-C11 P 1 PCS

D4 93L 39S 3 T BZT52-C11 P 1 PCS

D3 93L 39S 8 T ZD RLZ11B ROHM P 0 PCS

D4 93L 39S 8 T ZD RLZ11B ROHM P 0 PCS

D1 93L2004 1 SMAL240LVXRO-SMT P 0 PCS

D2 93L2004 1 SMAL240LVXRO-SMT P 0 PCS

D1 93L2004 2 SR24/PANJIT-SMT P 1 PCS

D2 93L2004 2 SR24/PANJIT-SMT P 1 PCS

715L 917 1A 5 LCD 17" INVERTER BRD P 1 PCS
AIK780KA5 KEY BOARD FOR T780K* M 1 PCS
AIK780KA5SMT KEY BOARD FOR T780K* SM M 1 PCS

SW101 77L 600 1GCJ TACT SWITCH TSPB-2 P 0 PCS

SW102 77L 600 1GCJ TACT SWITCH TSPB-2 P 0 PCS

SW103 77L 600 1GCJ TACT SWITCH TSPB-2 P 0 PCS

SW104 77L 600 1GCJ TACT SWITCH TSPB-2 P 0 PCS

SW105 77L 600 1GCJ TACT SWITCH TSPB-2 P 0 PCS

SW101 77L 600 1GHJ KEY SWITCH P 1 PCS

SW102 77L 600 1GHJ KEY SWITCH P 1 PCS

SW103 77L 600 1GHJ KEY SWITCH P 1 PCS

SW104 77L 600 1GHJ KEY SWITCH P 1 PCS

SW105 77L 600 1GHJ KEY SWITCH P 1 PCS

LED1 81L 12 1 GP LED P 1 PCS

JP801 95L8014 9 24 HARNESS P 1 PCS
715L 707 1 1 TF-1560 KEY BOARD (SMD) P 1 PCS

J101 95L 90 23 TIN COATED P 0 PCS

J102 95L 90 23 TIN COATED P 0 PCS

R109 61L 60210252T CFR 1K OHM+-5% 1/6W P 1 PCS

R101 61L 60210352T CFR 10K OHM+-5% 1/6W P 1 PCS

R102 61L 60210352T CFR 10K OHM+-5% 1/6W P 1 PCS

R103 61L 60210352T CFR 10K OHM+-5% 1/6W P 1 PCS

R104 61L 60210352T CFR 10K OHM+-5% 1/6W P 1 PCS

R105 61L 60210352T CFR 10K OHM+-5% 1/6W P 1 PCS

R106 61L 60210352T CFR 10K OHM+-5% 1/6W P 1 PCS

R107 61L 60210352T CFR 10K OHM+-5% 1/6W P 1 PCS

R108 61L 60222152T CFR 220 OHM +-5% 1/6W P 1 PCS

Q101 57L 417 4 PMBS3904/PHILIPS-SMT(04 P 1 PCS

Q102 57L 417 4 PMBS3904/PHILIPS-SMT(04 P 1 PCS

C101 65L0805104 32 CHIP 0.1UF 50V X7R P 1 PCS

Page 75 of 82

12L 381 1 RUBBER FOOT P 0 PCS
15L5711 1 BASE PLATE P 1 PCS
34L 916 DC L BACK COVER P 1 PCS
34L 917 DC L SUPPORT FRONT P 1 PCS
34L 918 DC L SUPPORT BACK P 1 PCS
34L 919 DC L BASE P 1 PCS
37L 448 1 LCD HINGE P 1 PCS
Q1L 140 10128 SCREW P 6 PCS
Q1L1030 10128 SCREW P 2 PCS
Q1L1030 12128 SCREW P 4 PCS

9.POWER SYSTEM AND CONSUMPTION CURRENT

Page 76 of 82

10.PCB LAYOUT

Page 77 of 82

11.SCHEMATIC

11.1. Main board SCHEMATIC:

U601
NT7181

TSSOP56

51

TXIN0

52

TXIN1

54

TXIN2

55

TXIN3

56

TXIN4

3

TXIN6

50

TXIN27

2

TXIN5

4

TXIN7

6

TXIN8

7

TXIN9

11

TXIN12

12

TXIN13

14

TXIN14

8

TXIN10

10

TXIN11

15

TXIN15

19

TXIN18

20

TXIN19

22

TXIN20

23

TXIN21

24

TXIN22

16

TXIN16

18

TXIN17

25

TXIN23

27

TXIN24

28

TXIN25

30

TXIN26

31

TXCLKIN

GND

ODD

U602
NT7181

TSSOP56

51

TXIN0

52

TXIN1

54

TXIN2

55

TXIN3

56

TXIN4

3

TXIN6

50

TXIN27

2

TXIN5

4

TXIN7

6

TXIN8

7

TXIN9

11

TXIN12

12

TXIN13

14

TXIN14

8

TXIN10

10

TXIN11

15

TXIN15

19

TXIN18

20

TXIN19

22

TXIN20

23

TXIN21

24

TXIN22

16

TXIN16

18

TXIN17

25

TXIN23

27

TXIN24

28

TXIN25

30

TXIN26

31

TXCLKIN

GND

ADC GNDA

PD[18..23]

PD[24..29]

PD[30..35]

PD[0..5]

PD[6..11]

PD[12..17]

PCLKA

PDISPE

PCLKB

ADC GNDA

PHS

PVS

ADC-AGND

PD36
PD37
PD0
PD1
PD2
PD3
PD4
PD5

PD38
PD39
PD6
PD7
PD8
PD9
PD10
PD11

PD40

PD41
PD12
PD13

PD14
PD15
PD16
PD17

R605

R

GND

PD42
PD43
PD18
PD19
PD20
PD21
PD22
PD23

PD44
PD45
PD24
PD25
PD26
PD27
PD28
PD29

PD46
PD47
PD30
PD31
PD32
PD33
PD34
PD35

PD36
PD37

PD38
PD39

PD40
PD41

PD42
PD43

PD44
PD45

PD46
PD47

U302

R341

TEST(OP)

GND

2

T2/P1.0

3

T2EX/P1.1

4

P1.2

5

P1.3

6

P1.4

7

P1.5

8

P1.6

9

P1.7

10

RST

11

RXD/P3.0

13

TXD/P3.1

14

INT0/P3.2

15

INT1/P3.3

16

TO/P3.4

17

T1/P3.5

18

WR/P3.6

19

RD/P3.7

R340

20

XTAL2

0

21

XTAL1

PS3

JP303

R

JP302

R(OP)

HDATA0

MFB7
MFB8
MFB9
HCLK

HFS

BKLT-PWM
VOL

C316

R302

RST

10 K

22 uF

GND

RXD
TXD
IRQ

MFB2

+5V

C313

D301

22 uF

1N4148

RST

A C

R313

10 K

GND

+A5V

R301

R300

10 K

10 K

SDA

SCL

SDA
SCL

RST1

/VGA_CON

X300

C303

20MHz

33 pF

C306

33 pF

GND

+5V

R333

U300

8

VCC

5

SI

7

WP

1

A0

6

2

A1

SCK

3

A2

4

VSS

24LC04B

2 K

C300

0.1 uF

GND

AVDD_3.3

C602

1

V

1

V

8XC51/PLCC

ALE/PROG

11223

R315

10 K

91726

V

91726

V

P2.0/A8

P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15

P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0

NCNCNC

PSEN

EA/VP

V

V

VCC

NC

34

MMBT3904

0.1uF

C604

0.1uF

1

C601

PWRDWN

TXCLKOUT-

TXCLKOUT+

LVDSVCC

LVDSGND
LVDSGND
LVDSGND

GND

PWRDWN

TXCLKOUT-

TXCLKOUT+

LVDSVCC

LVDSGND
LVDSGND
LVDSGND

24
25
26
27
28
29
30
31

32
33

36
37
38
39
40
41
42
43

44
35

+5V

GND

TXOUT0-

TXOUT0+

TXOUT1-

TXOUT1+

TXOUT2-

TXOUT2+

TXOUT3-

TXOUT3+

PLLVCC

PLLGND
PLLGND

TXOUT0-

TXOUT0+

TXOUT1-

TXOUT1+

TXOUT2-

TXOUT2+

TXOUT3-

TXOUT3+

PLLVCC

PLLGND
PLLGND

R311

10 K

2 3

EDGE

EDGE

GND
GND
GND
GND
GND

GND
GND
GND
GND
GND

Q304

0.1uF

AVDD_3.3

+A5V

C305

100uF

VR501

10 K

EVEN

22

/BKLT-ON

GND

Page 78 of 82

C603

100uF

32

TX0-E

48

TX0+E

47
46

TX1-E
TX1+E

45
42

TX2-E
TX2+E

41
38

TX3-E

37

TX3+E

TXCK-E

40

TXCK+E

39

44

49
43
36

34

35
33

53
29
21
13
5

GND

32

48

TX0-O

TX0+O

47

TX1-O

46

TX1+O

45

TX2-O

42

TX2+O

41

TX3-O

38

TX3+O

37

40

TXCK-O

39

TXO10

44

49
43
36

34

35
33

53
29
21
13
5

GND

+5V

R431

10 K(OP)

/BKLT-ON

KEY1(ORANGE?)
KEY2(GREEN?)

+5V

C304

0.1 uF

C944

0.1 uF

+5V

W

GND

+

GND

C605
10uF

16V

C613
10uF

16V

C615
10uF

16V

PS3

PW5V-ON

BKLT ADJ

C607
10uF

16V

4.7K Ohm

C403

GND

RP301

R303

4.7K

100uF

TXE0
TXE1
TXE2
TXE3
TXE4
TXE5
TXE6
TXE7

TXE8
TXE9

+

C606

0.01UF

+

TXO0
TXO1
TXO2
TXO3
TXO4
TXO5
TXO6
TXO7

TXO8

+

C614

0.01UF

+

C616

0.01UF

(Panel-Select)*

R321

0 (OP)

18
27
36
45

+12V

GND

R401

0(OP)

C608

0.01UF

GND

+5V

AVDD_3.3

AVDD_3.3

1
2

R403

R319

1

8

4.7K(OP)

1
2

BKLT-PWM

EVEN

PANEL_P

LVDS EN

+D5V

R238 0(OP)

KEY

+5V

R329

R328

10 K

10 K

4327

CP302

1000 pF

5

6

GND

VOL

MUTE
STDBY

ACER Electronics Co., Ltd.

Title

Size Document Number Rev

B

星期一, 十月

Date: Sheet of

3

C927

C939

0.1uF

330uF

ACER Electronics Co., Ltd.

Title

Size Document Number Rev
Custom

Date: Sheet of

+5V

R239

4.7K(OP)

R237 0(OP)

1

R236 10 K(OP)

CN302

GND

1
2
3
4
5
6
7
8
9

+5V

HEADER 9

MUTE

C954 1000PF(OP)

STDBY

C955 1000P(OP)

+12V

GND

MICRO CONTROLLER

715L820-2-2

21, 2002

U904
LT1117

IN

星期一, 十月

+5V

Q201

GND

C951

CAP(OP)

CN304

1
2
3
4
5
6

HEADER 6

TXE0
TXE2
TXE4
TXE8
TXE6
TXO0
TXO2
TXO4
TXO8
TXO6

1

GND

21, 2002

R235

4.7K(OP)

2 3

MMBT3904(OP)

GND

CN603

HEADER 12X2

2

OUT

ADJ

715A820-2-2

MUTE

STDBY

+12V

GND

36

1112
1314
1516
1718
1920
2122
2324

C953

CAP(OP)

12
34
56
78
910

LVDS

L900

L

TXE1
TXE3
TXE5
TXE9
TXE7
TXO1
TXO3
TXO5
TXO10
TXO7

GND

A

AVDD_3.3

C928

C940

0.1uF

330uF

66

A

GND

L601
BEAD (120)

L602
BEAD (120)

GND

L603
BEAD (120)

L604
BEAD (120)

K/E Select

R325

R323

0 (OP)

0 (OP)

GND

1

4327

CP301

1000 pF

5

6

8

CN303

1
2
3
4
5

HEADER 5

R402

C401

1K(OP)

100uF(OP)

GND

PW5V-ON

J1

+12V POWER

GND F

L300

(600)

C950

CAP

+5V

C309

330 uF/35V

+3.3V

C312
330 uF/35V

C941

0.1 uF

R307

4.7K

FB301

2 1

4

6 5

INDUCTOR-P

GND

+A5V

+12V

3

1

2

C952

R306

10K

Q202
MMBT3904

CAP

3

+5V

+5V

R305

4.7K

+12V

C307

330 uF/35V

C308

0.1 uF

U304
LM2596S-5.0 / Si8050

TO263

1

VIN

543

/ON

GND

FBK

Vout

D300

B320

2

T300

33 uH(OP)

L906

1 2

CHOKE

GND GND

+A5V

L905

1 2

CHOKE

C945

470uF/16V

GND

U306

1

S1

D1

2

S2

D1

3

S3

D2

4

G

D2

4431

+5V

+D5V

8
7
6
5

R310

+D5V

0

330 uF/35V

GND

C310

JP301

3
2
1

(OP)

C311

0.1 uF

U305 AIC 1084

VoutVin

GND

1

23

GND

+3.3V

1 2

/VGA_CON

ADC GNDA

CN200

1
2
3
4
5
6
7
8

9
10
11
12
13
14

HEADER 14

ADC-AGND

RXD

RXD

TXD

TXD

VGA_5V

A

C618

0.1 uF

GND

C

C943

C619

100uF

0.1 uF

24LC21A

GND

Connect two grounds at single point only.

ADC-AGND

ADC-AGND

BLUE

/VGA_CON1
VGA_HSYNC
VGA_VSYNC
VGA_SCL
VGA_SDA

+5V

2

1
2
3

GND

GND

GND

ACER Electronics Co., Ltd.

Title

Size Document Number Rev

A

Date: Sheet

星期一, 十月

DVDDA

129

C947

0.1uF

21, 2002

RVDDA

SVDDA

143

136

137

PLL_SVDDA

PLL_DVDDA

PLL_RVDDA

DAC_SVDDA

PLL_DGNDA

SUB_DGNDA

SUB_SGNDA

PLL_SGNDA

DAC_DGNDA

DAC_SGNDA

PLL_RGNDA

SUB_RGNDA

131

132

133

134

127

138

144

146

PGND

U905
RT9164

3

2

IN

OUT

ADJ

1

GND

+D5V

123

4

RP300

10 K

876

D204

1N4148

D205

1N4148

R212

100 (op)

MFB7
MFB8
MFB9

HCLK

IRQ

MFB2

C210

0.1 uF

C219

0.1 uF

HFS

GND

R206

75

ADC-AGND

R205

75

ADC-AGND

R204

75

ADC-AGND

U401D

9 8

ADC-AGND

U401B

3 4

74LVT14_ADC

C211

0.1 uF

C220

0.1 uF

C227

0.1 uF

5

R316 NC

R317 0

R200 0

R203 0

R201 0 C230

R207 0

R202 0

R208 0

74LVT14_ADC

ADC-AGND

C212

0.1 uF

C221

0.1 uF

C228

0.1 uF

C229

10 nF
C232

10 nF

10 nF
C233

10 nF

C231

10 nF
C234

10 nF

VSYNC

C236
100 pF(OP)

C235

100 pF(OP)

VDDA

PCLKB

C262

+5V

R327

10 K

R227

100

C251

D210

10nF

5.6 V

A C

ADC-AGND

VGA_5V

ADC-AGND

C948 CAP

C949 CAP

R220

R219
100 R

100 R

+5V

R217

R216

10 K

10 K

DDC_SDA

D209

D303

C244

BAT54

0.1 uF

GND

U203

84

5

NC

SDA

6

NC

SCL

VCCGND

NC

7

VCLK

PLL_GNDA

D208

AC

A C

5.6V

5.6V

GND

R218

100 R

+2.5V

L205

1 2

0

C(OP)

GND

+5V

R210
2 K(OP)

DDC_SCL

+3.3V

R230

0(OP)

+3.3V

+3.3V

+A2.5V

L203

600(1206)

R214

1 K(OP)

+5V

+D5V

C405

R209

0.1UF

2 K(OP)

R213

1 K(OP)

C207

C206

0.1 uF

100uF

C216

C213

22uF

0.1 uF

12

C224

100uF

ADC-AGND

ADC-AGND

ADC-AGND

D203

1N4148

D206

1N4148

D207

1N4148

11 10

D201

5.6 V

A C

ADC-AGND

D200

5.6 V

A C

C208

0.1 uF

C217

0.1 uF

C225

0.1 uF

VDDA

D202

1N4148

A C

A C

VDDA

ADC-AGND

A C

ADC-AGND

A C

U401E

74LVT14_ADC

+D5V

U401A

1 2

74LVT14_ADC

C209

0.1 uF

GND

C218

0.1 uF

ADC GNDA

HDATA0

VDDA

A C

A C

R211 100(op)

GND

C226

0.1 uF

+2.5V

GND

99
105
104
102

103
101

98

107

106

124
123
109
110
111
112
113

95

94

91

90

87

86

148

150

2

3

4

83

97
130
135
142
145
152
153

C956

1000pF

U200

HDATA
MFB7
MFB8
MFB9

HCLK
IRQ
HFS

MFB5

MFB6

MFB10
MFB11
MFB4
MFB3
MFB2
MFB1
MFB0

RED+

RED-

GREEN+

GREEN-

BLUE+

BLUE-

VSYNC

HSYNC/CS

Reserved
PSCAN
Reserved

Reserved
NC
Reserved
Reserved
XTAL(Reserved)
Reserved
Reserved
STI_TM1

ZAN1

L204

1 2

0

+3.3V

R221

R(OP)

33

4058657779

60

RVDD1

RVDD2

RVDD2B

RVDD2A

CVSS1

18183041496172114

5

R232

0(OP)

+3.3V

+A2.5V

+B2.5V

111221

108

RVDD3

RVDD3A

ADC_VDD2

ADC_VDD1

CVSS1A

RVSS1

SRVSS1

RVSS2

CVSS2

RVSS3

RVSS4

CVSS3

GND

R231

0(OP)

+B2.5V

C222

0.1 uF

GND

VDDA

125

139

149

84889296128

SVDD

DVDD

CVDD2

SRVDD1

SRVDD2

SYN_VDD

ADC_VDDA

ADC_BVDDA

ADC_GVDDA

ADC_RVDDA

DAC_DVDDA

ADC_GND2

ADC_GND1

SUB_GNDA

ADC_GNDA

ADC_BGNDA

ADC_GGNDA

ADC_RGNDA

CVSS2A

CVSS5

CVSS4

DVSS

SVSS

SYN_VSS

SRVSS2

126

140

151

158

78

80

8182858993

59

147

R234

0(OP)
R233
0(OP)

ADC-AGND

+D5V

C929

100uF

C223

0.1 uF

OSD_CLK

OSD_VREF

OSD_HREF

OSD_DATA2
OSD_DATA1
OSD_DATA0

OSD_FSW

OSD_DATA3

SCAN_IN1

Reserved

SCAN_IN2
SCAN_OUT1
SCAN_OUT2

+2.5V

C930

100uF

POWER

715L820-2-2

TCLK

141

TCLK

6

PD47

PD47

PD46

7

PD46

PD45

9

PD45

PD44

10

PD44

PD43

13

PD43

PD42

14

PD42

PD41

15

PD41

16

PD40

PD40

PD39

17

PD39

PD38

19

PD38

PD37

20

PD37

PD36

22

PD36

PD35

23

PD35

PD34

24

PD34

PD33

25

PD33

PD32

26

PD32

PD31

27

PD31

PD30

28

PD30

PD29

29

PD29

PD28

31

PD28

PD27

32

PD27

PD26

34

PD26

35

PD25

PD25

36

PD24

PD24

PD23

37

PD23

PD22

38

PD22

PD21

39

PD21

PD20

42

PD20

PD19

46

PD19

PD18

47

PD18

PD17

48

PD17

PD16

50

PD16

PD15

51

PD15

PD14

52

PD14

53

PD13

PD13

54

PD12

PD12

PD11

55

PD11

PD10

56

PD10

57

PD9

PD9

62

PD8

PD8

63

PD7

PD7

PD6

64

PD6

PD5

66

PD5

PD4

67

PD4

PD3

68

PD3

PD2

69

PD2

PD1

70

PD1

PD0

71

PD0

73

PVS

PVS

74

PHS

PHS

LVDS EN

75

PBIAS

PPWR

76

PPWR

43

PDISPE

PDISPE

CLK

44

PCLKA

45

PCLKB

117
116
115

120
119
118

122

121

100

RESETn

154

STI_TM2

155
156
157
159
160

PPWR

C946

0.1uF

GND

GND

LVDS EN

L207

1 2

L

+D5V

R326

10 K

C314

22 uF

C620

10uF

56

+3.3V

L200

600(1206)

L201

600(1206)

L202

600(1206)

0.1 uF

PCLKA

PHS

PD[0..47]

PCLKB

R602

R

PCLKA

R603

R

PCLKB

D302

1N4148

A C

C957

1000PF

GND

C942

0.1 uF

GND

R223

1

10 K

Title

Size Document Number Rev

Date: Sheet

of

12

C200

C201

100uF

0.1 uF

PGND

12

C203

C204

100uF

0.1 uF

PGND

12

U201

1 4

SB VCC

3

Q200
MMBT3904

2

C237

PGND

PCLKB

R229

0

R224

10K

R225
10K

2

GND

PCLKA

PHS

PD[0..47]

GND

3

OUT

GND

50 MHz

PVS

PDISPE

RST1

R229:
Let Zan1 been
reseted twice!

+D5V

4

G2

D2

C245

5

0.1 uF

C246

0.1 uF

ACER Electronics Co., Ltd.

星期一, 十月

21, 2002

ZAN2

715L820-2-2

C

DVDDA

C202

0.1 uF

SVDDA

C205

0.1 uF

GND

JP202

123

S1G1S2

D1D1D2

876

PANEL_P

0

R215

bead 120

C250

33 pF

U202

SI9933ADY

C214

100uF

A

RVDDA

C215

0.1 uF

PGND

TCLK

PVS

PDISPE

+12V

JP203

R (OP)

PANEL_P

of

14

A

Page 79 of 82

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