Acer Extensa 4620, Extensa 4220 Schematics POWER SEQUENCE REV

A

B

C

D

E

Biwa POWER TOPLOGY AND POWER SEQUENCING

CLK GEN

CK_PWRGD/PD#

4 4

CLK_PWRGD

DCBATOUT

5V_AUX_S5

ISL6236 G913

37

-3

5
4 3

SW-TACT-59-GP-U1

SW-TACT-59-GP-U1

RTC

3 3

62.40009.631

62.40009.631

KBC_PWRBTN#_R

PWRSW1

PWRSW1

1

2 4

SW-TACT-103-GP-U

SW-TACT-103-GP-U

SW1

SW1

12

62.40009.631

62.40009.631

RTC_BAT

3
5

PM_SLP_S3#

PM_SLP_S3#

3D3V_AUX_S5

34

12

R7

R7
10KR2J-3-GP

10KR2J-3-GP

R18

R18

1 2

470R2J-2-GP

470R2J-2-GP

1D8V_LDO_1D5V

APL5912

EN

1D8V_LDO_1D25V

APL5915

EN

ECRST#

KBC_PWRBTN#

12

1

C14

C14
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

KA

VOUT

5912_POK

POK

VOUT

5915_POK

POK

1D5V_S0

4b

1D25V_S0

4b

0R2J-2-GP

0R2J-2-GP

R229

R229

WPC8768L

VCC_POR#

GPIO03

PURE_HW_SHUTDOWN#

R328

R328

12

0R2J-2-GP

0R2J-2-GP

12

RTC_AUX_S5

KA

RTC_RST#

PM_PWRBTN#

GPIO23

RSMRST#_KBC

GPIO40

GPIO36

-2

S5_ENABLE

CPUCORE_ON CPUCORE_ON

RTCRST#

PWRBTN# SLP_S4#

2

RSMRST#

-1

10

3

D31

D31

PWROK

9

ICH8M

SLP_S3#

PLTRST#

PCIRST#

CLPWROK

VRMPWRGDPWROK

8

10

1 2

R385 0R2J-2-GPR385 0R2J-2-GP

2

BAS16-1-GP

BAS16-1-GP

1

PWROK

CPUPG

VGATE_PWRGD

3
4

PLT_RST1#
PCIRST1#
H_PWRGD

13

5

PM_SLP_S4#
PM_SLP_M#
PM_SLP_S3#

14

PM_SLP_S4#

PM_SLP_S3#

TP49 TPAD30TP49 TPAD30

3V/5V_EN

1D8V_S3

TPS51100

S5

S3

DCBATOUT

MAX8717

ON1

ON2

DCBATOUT

ISL6236

EN1

EN2

VTTREF

VTT

LX1

PGOOD1

LX2

PGOOD2

PHASE1
POK1

PHASE2
POK2

DDR_VREF_S3

3b

1D8V_S3

3a

5V_S5

DDR_VREF_S0

1D05V_S0

4a

CPUCORE_ON

3D3V_S5

0

3V/5V_POK

PCIRST1#

4b

1 2

0R2J-2-GP

0R2J-2-GP

R372

R372

G28

G28

GAP-OPEN-PWR

GAP-OPEN-PWR

G64

G64

GAP-OPEN-PWR

GAP-OPEN-PWR

1D8V_LDO_1D5V

12

12

DCBATOUT 5V_S0

MAX8770

SHDN# PWRGD

6

1 2

1 2

PM_SLP_S3#

TI 7412

1D8V_LDO_1D25V

3D3V_S0

5V_S0

U46U46

U50U50

PLT_RST1#

VCC_CORE_S0

VGATE_PWRGD

3D3V_S0

M State

M0

M1

M-off

7

8

R252

R252

1 2

0R2J-2-GP

0R2J-2-GP

PWROK

RESET#

G792

Host
System
State

DY

DY

S0

S3-S5

S3-S5

R255

R255
0R2J-2-GP

0R2J-2-GP

10

System
Power
Source

AC or
Battery

AC only

AC or
Battery

12

Power
Wells

All wells
powered

Main well down,
M rails down.

Main well down,
M rails down.

5V_Aux_S5
3D3V_Aux_S5

PWROK_GD

CLPWROK_MCH

1 2

R246 0R2J-2-GPR246 0R2J-2-GP

PLT_RST1#

3D3V_S5

Crestline

12

PWROK

CL_PWROK

11

RSTIN#

14

DRAM

Powered

In self reflash;ME
DRAM controller is
on,using Channel A

Powered off(or
self reflash

PM_SLP_S4#
1D8V_S3
DDR_VREF_S3

15

H_CPURST#

CPU_CPURST#

ME Clocking

Clock chip powered and PLL
/DLL in use.

Clock chip powered with only
the GMCH clock running and
PLL/DLL in use.

None, ME powered off.

PM_SLP_S3#S5_ENABLE
1D05V_S0
3D3V_S05V_S5
5V_S0
DDR_VREF_S0
1D5V_S0
1D25V_S0

CPU

RESET#

PWRGOOD

H_PWRGD

13

HDDDRV#_5

HDDlevel shift

2 2

Sequence of Events:

(-4)VccRTC active to RTCRST# inactive >18ms.

(-3)Insert ADT, ISL6236 output "5V_AUX_S5", G913(LP2951) output "3D3V_AUX_S5" when 5V_AUX_S5 ready.
(-2)WPC8768L asserts "S5_ENABLE", OR gate enables PWM IC for "5V_S5" ad "3D3V_S5".
(-1)WPC8768L drived "RSMRST#_KBC" to ICH8M(rise time 10%-90% <15ns)
(1)User push power botton : "KBC_PWRBTN#" to WPC8768L.
(2)"PM_PWRBTN#" from KBC to ICH8M.
(3)ICH8M asserts "PM_SLP_S4#" to enable PWM IC MAX8717 out "1D8V_S3".
1D8V_S3 regulator comes followed by "DDR_VREF_S3" regulators

(3.1)SLP_S4# inactive to SLP_S3# inactive 1~4 RTCCLK.

(4)ICH8M asserts "PM_SLP_S3#" to enable PWM IC out "1D05V_S0".
After aprox 10ms soft start delay S0 power switches are turned on connecting S0 planes with S5/S3 planes.
5V_S5->"5V_S0",3D3V_S5->"3D3V_S0","1D8V_LDO_1D5V"->"1D5V_S0","1D8V_LDO_1D25V"->"1D25V_S0", "DDR_VREF_S3".

(4.1)V5REF(5V_S0) must be powered up before 3D3V_S0, or after winthin 0.7V. Also V5REF must power down after 3D3V_S0, or before within 0.7V.
(4.2)1D5V_S0 must power up before V_CPU_IO(1D05V_S0) or after winthin 0.7V. Also V_CPU_IO must power down before 1D5V_S0 or after within 0.7V.

(5)PM_SLP_M# : TP.
(6)When 3V, 5V, 1.8V, 1.05V ready, they are asserts "CPUCORE_ON" to PWM IC for CPU power.
(7)5ms after VCC_CORE_S0 regulation, VGATE_PWRGD is driven to ICH8M VRMPWRGD.
(8)"G792_PWROK" Output remains low while VCC is below the reset threshold,

1 1

and for 220ms after VCC rises above the reset threshold.
(9)10ms after "VGATE_PWRGD" plane comes up "CLK_PWRGD" is driven.

(10)Power OK for ICH8M(PWROK assertion indicates that PCICLK has been stable for at least 1ms, Vcc supplies active to PWROK >99ms) .
(10.1)VGATE_PWRGD active to PWROK active >3 ms.

(11)CL_PWROK
(12)POWER OK for GMCH
(13)"H_PWRGD" from ICH8M to CPU
(14)"PLT_RST1#"(PCIRST1#) from ICH8M to GMCH.

(14.1)PWROK active to PLTRST1# active 34~41 RTCCLK

(15)"H_CPURST#" from GMCH to CPU

A

B

C

LPC debug BD

Mini Card

PESET#

P2231

SYSRST#

KBC WPC8768L

LRESET#

LAN BCM5787M

PERST#

D

RESET#

NEW Card

bom1

bom1

bom1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

POWER SEQUENCING

POWER SEQUENCING

POWER SEQUENCING

Taipei Hsien 221, Taiwan, R.O.C.

Biwa

Biwa

Biwa

E

of

11Monday, October 16, 2006

of

11Monday, October 16, 2006

of

11Monday, October 16, 2006

SA

SA

SA