Acer ES1-431 Schematic

5

4

3

2

1

Z8AD UMA(14")

BOM

@ : EMMc

EM

D D

Intel Brasewll Platform Block Diagram

DDR3L SO-DIMM 0 Maximum 8GB

DDR3L

PAGE 11

EMMC 5.0

32GB/64GB

Card Reader

SDMMC1

SDMMC3

Intel Brasewll

Power : 7.5 Watt

Package : FCBG 1170

C C

SATA - HDD Package : 9.5 (mm) Power :

PAGE 16

SATA - ODD Package : 9.5 (mm) Power :

1.8V BIOS+TXE SPI ROM(64Mb)

PAGE 16

PAGE 6

SATA0 3GB/s

SATA1 3GB/s

SPI Interface

Size : 25 x 27 (mm)

Int

PAGE 2~10

Az alia

1

DDI

0

DDI

32.768KHz PAGE 6

19.2 Mhz PAGE 6

B3.0

US

USB 2.0 Interface

Port2

Camera

PAGE 13

B B

3.3V EC code SPI ROM(1Mb)

PAGE 23

Embedded Controller

IT8987

Audio Codec

ALC255

PCIE Gen 2 x 1 LaneLPC Interface

Port3 Port2

LAN

Half Mini Card

Port3

RTL8111H-CG

eDP

HDMI Conn PAGE 13

Port0

USB3.0 Conn PAGE 18

Port1

USB2.0 Port

PAGE 18

PAGE 13

Port0

Port4

NGFF Card

HD@ : HDD GS@ :G-sensor TPM@ : TPM TSI@ :TOUCH SCREEN I2C SP@ :Special

Keyboard

Touch Pad

PAGE 15

PS2

Package : LQPF128

Size : 14 x 14 (mm)

PAGE 23

Package : QFN

Size : 6 x 6 (mm)

PAGE 19

Package : QFN

Size : x (mm)

PAGE 12

WLAN / BT Combo

PAGE 21

WLAN / BT Combo

PAGE 15

I2C

I2C from CPU

A A

5

FAN

Sp

PAGE 16

eaker

PAGE 19

Universal Jack Headphone + MIC

alog MIC

An

4

3

PAGE 19

anta Computer Inc.

Qu

PROJECT :

Si

ze Document Number Rev

We

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

2

dnesday, April 08, 2015

PROJECT :

Intel Block Diagram

Z8AD

1A

of

321

of

321

of

1

321

5

+1

.35VSUS [3,9,11,27]

+3

V_S5 [3,5,9,12,14,15,16,22,26]

D D

PLACE THE RESISTORS AS CLOSE AS POSSIBLE TO SOC(BSW) ROUTE THEM AS SINGLE ENDED LINES

12 *49.9_4

R2

13 *49.9_4

R2

D

GN

ROUTE ALL VREF POWER SIGNALS AS THICK TRACES

+1

.35VSUS

C C

B B

A A

PLACE TWO 4.7K RESISTORS CLOSE TO CPU PINS ON M_VREF ROUTE THE VREF POWER SIGNALS WITH THICK TRACES

28

R2 *4.7K_4

A_VREF_CA

M_

03

A_VREF_DQ

M_

D

GN

D

GN

1333 MHz

1600 MHz

C2

*0.1U/16V_4

02

C2

*0.1U/16V_4

X

20

R2 *4.7K_4

D

GN

+1

.35VSUS

27

R2 *4.7K_4

19

R2 *4.7K_4

D

GN

Channel 0

1333 MHz

1600 MHz

1333 MHz

1600 MHz

Channel 0 need to be populated first for the platform to power on

A_MON1P

M_

08

R2 *100_4

A_MON1N

M_

PLACE 0.1UF CAP CLOSE TO CPU

SoC Supported Memory Operation SpeedChannel 1

1066 MHz

1600 MHz

1066 MHz

1600 MHz

5

M_

A_A[15:0][11]

M_

A_DM0[1 1]

M_

A_DM1[1 1]

M_

A_DM2[1 1]

M_

A_DM3[1 1]

M_

A_DM4[1 1]

M_

A_DM5[1 1]

M_

A_DM6[1 1]

M_

A_DM7[1 1]

M_

A_RAS#[11]

M_

A_CAS#[11]

M_

A_WE#[11]

M_

A_BS#0[11]

M_

A_BS#1[11]

M_

A_BS#2[11]

M_

A_CS#0[11]

M_

A_CS#1[11]

M_

A_CKE0[11]

M_

A_CKE1[11]

M_

A_ODT0[11]

M_

A_ODT1[11]

M_

A_CLK0[11]

M_

A_CLK0#[11]

M_

A_CLK1[11]

M_

A_CLK1#[11]

M_

A_DRAMRST#[11]

79 182_4

R1

GN

D

4

A_A0

M_

A_A1

M_

A_A2

M_

A_A3

M_

A_A4

M_

A_A5

M_

A_A6

M_

A_A7

M_

A_A8

M_

A_A9

M_

A_A10

M_

A_A11

M_

A_A12

M_

A_A13

M_

A_A14

M_

A_A15

M_

A_DM0

M_

A_DM1

M_

A_DM2

M_

A_DM3

M_

A_DM4

M_

A_DM5

M_

A_DM6

M_

A_DM7

M_

A_RAS#

M_

A_CAS#

M_

A_WE#

M_

A_BS#0

M_

A_BS#1

M_

A_BS#2

M_

A_CS#0

M_

A_CS#1

M_

A_CKE0

M_

A_CKE1

M_

A_ODT0

M_

A_ODT1

M_

A_CLK0

M_

A_CLK0#

M_

A_CLK1

M_

A_CLK1#

M_

A_DRAMRST#

M_

A_VREF_CA

M_

A_VREF_DQ

M_

A_MON1P

M_

A_MON1N

M_

C_DRAM_PWROK

SO

M_RCOMP0

DRA

P_S4#[6,14]

SL

4

BB47 BC42 BJ48 BH47 BD42 BH48

BB46 BE46 BD44

BE52

BJ45 BB49 BF48 BF44

BD47

BD49

AP52

AT48

AP44 BA53 BG41 AY36 BD32

BH30

BA40 BG45 BH44

BH46 AY40

BF52

AY38

AU38

BB44

AY42

AV36

BA38

BD40 BF40

BD38 BF38

BA42

AT28 AU28

AT30 AU30

AV28

BA28

SL

P_S4#

U23A

DDR3

_M0_MA_0

DDR3

_M0_MA_1

DDR3

_M0_MA_2

DDR3

_M0_MA_3

DDR3

_M0_MA_4

DDR3

_M0_MA_5

DDR3

_M0_MA_6

DDR3

_M0_MA_7

DDR3

_M0_MA_8

DDR3

_M0_MA_9

DDR3

_M0_MA_10

DDR3

_M0_MA_11

DDR3

_M0_MA_12

DDR3

_M0_MA_13

DDR3

_M0_MA_14

DDR3

_M0_MA_15

DDR3

_M0_DM_0

DDR3

_M0_DM_1

DDR3

_M0_DM_2

DDR3

_M0_DM_3

DDR3

_M0_DM_4

DDR3

_M0_DM_5

DDR3

_M0_DM_6

DDR3

_M0_DM_7

DDR3

_M0_RASB

DDR3

_M0_CASB

DDR3

_M0_WEB

DDR3

_M0_BS_0

DDR3

_M0_BS_1

DDR3

_M0_BS_2

DDR3

_M0_CSB_0

DDR3

_M0_CSB_1

DDR3

_M0_CKE_0

DDR3

_M0_CKE_1

DDR3

_M0_ODT_0

DDR3

_M0_ODT_1

DDR3

_M0_CK_0

DDR3

_M0_CKB_0

DDR3

_M0_CK_1

DDR3

_M0_CKB_1

DDR3

_M0_DRAMRSTB

DRA

M_M0_OCAVREF

DRA

M_M0_ODQVREF

RS

VD_AT30

RS

VD_AU30

DDR3

_DRAM_PWROK

DDR3

_M0_RCOMPPD

VLV_M_D/BGA

RE

V = 1.15

3

AK51

A_DQ0

GN

D

AL51 AT52 AR51 AL53 AK52 AR53 AP51 AP48 AT47 AY48 AV50 AP47 AT50 AY50 AV45 AT40 AP42 AT38 AP40 AT44 AV41 AP41 AV42 BD52 AV52 BC53 AV51 AW51 BC52 AW53 BB51 BG42 BG43 BG37 BJ37 BH42 BJ41 BH36 BH38 BC36 BA36 AU34 AU32 BF36 BD36 AV34 AV32 BF34 BC34 BA32 BD30 BD34 BA34 BF30 BD28 BJ33 BG29 BH34 BG32 BG28 BJ29 BH28 BG33

AM52 AM51 AV47 AV48 AT42 AT41 AY52 BA51 BH40 BG39 AT32 AT34 BC30 BC32 BH32 BG31

PG_1.35V [22,27]

HW

SO

C_DRAM_PWROK

C2

08

*0.1U/16V_4

M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_

M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_

A_DQ1 A_DQ2 A_DQ3 A_DQ4 A_DQ5 A_DQ6 A_DQ7 A_DQ8 A_DQ9 A_DQ10 A_DQ11 A_DQ12 A_DQ13 A_DQ14 A_DQ15 A_DQ16 A_DQ17 A_DQ18 A_DQ19 A_DQ20 A_DQ21 A_DQ22 A_DQ23 A_DQ24 A_DQ25 A_DQ26 A_DQ27 A_DQ28 A_DQ29 A_DQ30 A_DQ31 A_DQ32 A_DQ33 A_DQ34 A_DQ35 A_DQ36 A_DQ37 A_DQ38 A_DQ39 A_DQ40 A_DQ41 A_DQ42 A_DQ43 A_DQ44 A_DQ45 A_DQ46 A_DQ47 A_DQ48 A_DQ49 A_DQ50 A_DQ51 A_DQ52 A_DQ53 A_DQ54 A_DQ55 A_DQ56 A_DQ57 A_DQ58 A_DQ59 A_DQ60 A_DQ61 A_DQ62 A_DQ63

A_DQS0 A_DQS#0 A_DQS1 A_DQS#1 A_DQS2 A_DQS#2 A_DQS3 A_DQS#3 A_DQS4 A_DQS#4 A_DQS5 A_DQS#5 A_DQS6 A_DQS#6 A_DQS7 A_DQS#7

DDR3

_M0_DQ_0

DDR3

_M0_DQ_1

DDR3

_M0_DQ_2

DDR3

_M0_DQ_3

DDR3

_M0_DQ_4

DDR3

_M0_DQ_5

DDR3

_M0_DQ_6

DDR3

_M0_DQ_7

DDR3

_M0_DQ_8

DDR3

_M0_DQ_9

DDR3

_M0_DQ_10

DDR3

_M0_DQ_11

DDR3

_M0_DQ_12

DDR3

_M0_DQ_13

DDR3

_M0_DQ_14

DDR3

_M0_DQ_15

DDR3

_M0_DQ_16

DDR3

_M0_DQ_17

DDR3

_M0_DQ_18

DDR3

_M0_DQ_19

DDR3

_M0_DQ_20

DDR3

_M0_DQ_21

DDR3

_M0_DQ_22

DDR3

_M0_DQ_23

DDR3

_M0_DQ_24

DDR3

_M0_DQ_25

DDR3

_M0_DQ_26

DDR3

_M0_DQ_27

DDR3

_M0_DQ_28

DDR3

_M0_DQ_29

DDR3

_M0_DQ_30

DDR3

_M0_DQ_31

DDR3

_M0_DQ_32

DDR3

_M0_DQ_33

DDR3

_M0_DQ_34

DDR3

_M0_DQ_35

DDR3

_M0_DQ_36

DDR3

_M0_DQ_37

DDR3

_M0_DQ_38

DDR3

_M0_DQ_39

DDR3

_M0_DQ_40

DDR3

_M0_DQ_41

DDR3

_M0_DQ_42

DDR3

_M0_DQ_43

DDR3

_M0_DQ_44

DDR3

_M0_DQ_45

DDR3

_M0_DQ_46

DDR3

_M0_DQ_47

DDR3

_M0_DQ_48

DDR3

_M0_DQ_49

DDR3

_M0_DQ_50

DDR3

_M0_DQ_51

DDR3

_M0_DQ_52

DDR3

_M0_DQ_53

DDR3

_M0_DQ_54

DDR3

_M0_DQ_55

DDR3

_M0_DQ_56

DDR3

_M0_DQ_57

DDR3

_M0_DQ_58

DDR3

_M0_DQ_59

DDR3

_M0_DQ_60

DDR3

_M0_DQ_61

DDR3

_M0_DQ_62

DDR3

_M0_DQ_63

DDR3

_M0_DQSP_0

DDR3

_M0_DQSN_0

DDR3

_M0_DQSP_1

DDR3

_M0_DQSN_1

DDR3

_M0_DQSP_2

DDR3

_M0_DQSN_2

DDR3

_M0_DQSP_3

DDR3

_M0_DQSN_3

DDR3

_M0_DQSP_4

DDR3

_M0_DQSN_4

DDR3

_M0_DQSP_5

DDR3

_M0_DQSN_5

DDR3

_M0_DQSP_6

DDR3

_M0_DQSN_6

DDR3

_M0_DQSP_7

DDR3

_M0_DQSN_7

1 OF 12

+1

_PWOK_C1

R2 10K_4

.35VSUS

31

HW

PG_1.35V

61

2

Q2

7B

PJ4N3KDW

R2

32 *short_4

3

+3

V_S5

R2

40

4.7K_4

DRM

34

5

Q2

7A

PJ4N3KDW

GN

D

2

M_

A_DQ[63:0] [11]

2

A_DQS[7:0]

M_

A_DQS#[7:0]

M_

1

M_

A_DQS[7:0] [11]

M_

A_DQS#[7:0] [11]

anta Computer Inc.

Qu

PROJECT :

Si

ze Document Number Rev

We

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

PROJECT :

Valley 1/9 (DDRA)

Z8AD

1

3A

of

322

of

322

of

322

5

4

3

2

1

U23B

BB7

DDR3

_M1_MA_0

BC12

DDR3

_M1_MA_1

BJ6

DDR3

_M1_MA_2

BH7

DDR3

_M1_MA_3

BD12

DDR3

BD10

BF10

AP10

BG13 AY18 BD22 BH24

BA14

BH10

AY14

AY16

AU16

BB10

AY12

AV18

BA16

BD14 BF14

BD16 BF16

BA12

AT26 AU26

AT24 AU24

AV26

BA26

BH6 BB8 BE8

BE2 BJ9 BB5 BF6

BD7 BD5

AP2 AT6

BA1

BG9

BH8

BF2

_M1_MA_4

DDR3

_M1_MA_5

DDR3

_M1_MA_6

DDR3

_M1_MA_7

DDR3

_M1_MA_8

DDR3

_M1_MA_9

DDR3

_M1_MA_10

DDR3

_M1_MA_11

DDR3

_M1_MA_12

DDR3

_M1_MA_13

DDR3

_M1_MA_14

DDR3

_M1_MA_15

DDR3

_M1_DM_0

DDR3

_M1_DM_1

DDR3

_M1_DM_2

DDR3

_M1_DM_3

DDR3

_M1_DM_4

DDR3

_M1_DM_5

DDR3

_M1_DM_6

DDR3

_M1_DM_7

DDR3

_M1_RASB

DDR3

_M1_CASB

DDR3

_M1_WEB

DDR3

_M1_BS_0

DDR3

_M1_BS_1

DDR3

_M1_BS_2

DDR3

_M1_CSB_0

DDR3

_M1_CSB_1

DDR3

_M1_CKE_0

DDR3

_M1_CKE_1

DDR3

_M1_ODT_0

DDR3

_M1_ODT_1

DDR3

_M1_CK_0

DDR3

_M1_CKB_0

DDR3

_M1_CK_1

DDR3

_M1_CKB_1

DDR3

_M1_DRAMRSTB

DDR3

_M1_OCAVREF

DDR3

_M1_ODQVREF

RS

VD_AT24

RS

VD_AU24

DDR3

_DRAM_PWROK

DDR3

_M1_RCOMPPD

VLV_M_D/BGA

RE

V = 1.15

2 OF 12

3

D D

PLACE THE RESISTORS AS CLOSE AS POSSIBLE TO SOC(BSW) ROUTE THEM AS SINGLE ENDED LINES

14 *49.9_4

R2

15 *49.9_4

R2

D

+1

GN

.35VSUS

GN

.35VSUS

GN

ROUTE ALL VREF POWER SIGNALS AS THICK TRACES

PLACE TWO 4.7K RESISTORS CLOSE TO CPU PINS ON M_VREF ROUTE THE VREF POWER SIGNALS WITH THICK TRACES

30

R2 *4.7K_4

B_VREF_CA

M_

05

B_VREF_DQ

M_

GN

C2

*0.1U/16V_4

D

04

C2

*0.1U/16V_4

D

EC

5

R2 *4.7K_4

D

R2 *4.7K_4

D

22

29

21

C C

B B

A A

B_MON1P

M_

09

R2 *100_4

B_MON1N

M_

PLACE 0.1UF CAP CLOSE TO CPU

EC

_PWROK[14,22]

_PWROK

B_VREF_CA

M_

B_VREF_DQ

M_

B_MON1P

M_

B_MON1N

M_

C_VCCA_PWROK

SO

C_VCCA_PWROK

3B

4

DRA

M_RCOMP1

C2

01

*0.1U/16V_4

GN

D

78 *182_4

R1

GN

D

+1

_PWOK_C2

R2 10K_4

.35VSUS

26

61

2

Q2

PJ4N3KDW

+3

V_S5

R2

36

4.7K_4

DRM

34

5

Q2

3A

PJ4N3KDW

GN

D

DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3

DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3

DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3

_M1_DQSP_0 _M1_DQSN_0 _M1_DQSP_1 _M1_DQSN_1 _M1_DQSP_2 _M1_DQSN_2 _M1_DQSP_3 _M1_DQSN_3 _M1_DQSP_4 _M1_DQSN_4 _M1_DQSP_5 _M1_DQSN_5 _M1_DQSP_6 _M1_DQSN_6 _M1_DQSP_7 _M1_DQSN_7

_M1_DQ_0 _M1_DQ_1 _M1_DQ_2 _M1_DQ_3 _M1_DQ_4 _M1_DQ_5 _M1_DQ_6 _M1_DQ_7 _M1_DQ_8

_M1_DQ_9 _M1_DQ_10 _M1_DQ_11 _M1_DQ_12 _M1_DQ_13 _M1_DQ_14 _M1_DQ_15 _M1_DQ_16 _M1_DQ_17 _M1_DQ_18 _M1_DQ_19 _M1_DQ_20 _M1_DQ_21 _M1_DQ_22 _M1_DQ_23 _M1_DQ_24 _M1_DQ_25 _M1_DQ_26 _M1_DQ_27 _M1_DQ_28 _M1_DQ_29 _M1_DQ_30 _M1_DQ_31 _M1_DQ_32 _M1_DQ_33 _M1_DQ_34 _M1_DQ_35 _M1_DQ_36 _M1_DQ_37 _M1_DQ_38 _M1_DQ_39 _M1_DQ_40 _M1_DQ_41 _M1_DQ_42 _M1_DQ_43 _M1_DQ_44 _M1_DQ_45 _M1_DQ_46 _M1_DQ_47 _M1_DQ_48 _M1_DQ_49 _M1_DQ_50 _M1_DQ_51 _M1_DQ_52 _M1_DQ_53 _M1_DQ_54 _M1_DQ_55 _M1_DQ_56 _M1_DQ_57 _M1_DQ_58 _M1_DQ_59 _M1_DQ_60 _M1_DQ_61 _M1_DQ_62 _M1_DQ_63

AK3 AL3 AT2 AR3 AL1 AK2 AR1 AP3 AP6 AT7 AY6 AV4 AP7 AT4 AY4 AV9 AT14 AP12 AT16 AP14 AT10 AV13 AP13 AV12 BD2 AV2 BC1 AV3 AW3 BC2 AW1 BB3 BG12 BG11 BG17 BJ17 BH12 BJ13 BH18 BH16 BC18 BA18 AU20 AU22 BF18 BD18 AV20 AV22 BF20 BC20 BA22 BD24 BD20 BA20 BF24 BD26 BJ21 BG25 BH20 BG22 BG26 BJ25 BH26 BG21

AM2 AM3 AV7 AV6 AT12 AT13 AY2 BA3 BH14 BG15 AT22 AT20 BC24 BC22 BH22 BG23

anta Computer Inc.

Qu

PROJECT :

Si

Size Document Number Rev

ze Document Number Rev

We

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

2

dnesday, April 08, 2015

PROJECT :

Valley 2/9 (DDRB)

Z8AD

3A

of

323

of

323

of

1

323

5

V[7,9,11,12,13,14,15,16,18,19,21,22,25,27,28,29,30]

+3

U23C

IN

_D2[13] _D2#[13]

IN IN

_D1[13]

IN

_D1#[13] _D0[13]

D D

HDM

IN

I

IN

_D0#[13] _CLK[13]

IN IN_CLK#[13]

I_HPD_CON[13]

HDM

SD

VO_DATA[13] VO_CLK[13]

SD

Internal Pull-High 1.8V

R1

03

402_4

IN

T_EDP_TXP0[13]

T_EDP_TXN0[13]

IN IN

C C

B B

A A

eDP

R102 402_4

T_EDP_TXP1[13]

IN

T_EDP_TXN1[13]

T_eDP_AUXP[13]

IN INT_eDP_AUXN[13] 1_EDP_HPD_R[13]

DDI

5

GN

D

C_DDIO_RCOMP

SO SOC_DDIO_RCOMP_P

H_DISP_ON_C

PC PC

H_EDP_BLON_C H_DPST_PWM_C

PC

SO

C_DDI1_RCOMP C_DDI1_RCOMP_P

SO

80 *0_4

R3

79 *0_4

R3

D50 C51 H49 H50 F53

F52 G53 G52

H47

H46

W51

Y52

Y51

W53

V52

V51

F38 G38

J51

H51

K51

K52

L53

L51

M52 M51

M42

K42

R51

R53

P51

P52

F47

F49

F40 G40

J40

K40

F42 G42

D44

F44

D48

C49

U51

T51

T52

A49

A51

A52

B49

B50

B53

C53

D52

E52

E53 G44

DDI

0_TXP_0

DDI

0_TXN_0 0_TXP_1

DDI DDI

0_TXN_1 0_TXP_2

DDI

0_TXN_2

DDI DDI

0_TXP_3 0_TXN_3

DDI

0_AUXP

DDI

0_AUXN

HV

_DDI0_HPD

_DDI0_DDC_SDA

HV

_DDI0_DDC_SCL

HV

EL0_VDDEN

PAN PAN

EL0_BKLTEN EL0_BKLTCTL

PAN

0_PLLOBS_P

DDI DDI

0_PLLOBS_N

1_TXP_0

DDI DDI

1_TXN_0 1_TXP_1

DDI DDI

1_TXN_1

DDI

1_TXP_2 1_TXN_2

DDI

1_TXP_3

DDI DDI

1_TXN_3

DDI

1_AUXP 1_AUXN

DDI HV

_DDI1_HPD

EL1_VDDEN

PAN PAN

EL1_BKLTEN EL1_BKLTCTL

PAN

1_PLLOBS_P

DDI DDI

1_PLLOBS_N

2_TXP_0

DDI

2_TXN_0

DDI

2_TXP_1

DDI DDI

2_TXN_1 2_TXP_2

DDI DDI

2_TXN_2

DDI

2_TXP_3

DDI

2_TXN_3

DDI

2_AUXP 2_AUXN

DDI

HV_DDI2_HPD

_DDI2_DDC_SCL

HV HV

_DDI2_DDC_SDA

VD_A49

RS

VD_A51

RS RS

VD_A52

RS

VD_B49 VD_B50

RS RS

VD_B53

RS

VD_C53 VD_D52

RS RS

VD_E52 VD_E53

RS

VD_G44

RS

VLV_M_D/BGA

REV = 1.15

4

DDI0

DDI1

DDI2

NC's

3

OF 12

T50

RS

VD_T50

T48

RS

VD_T48

M44

VD_M44

RS

SI_1_CLKP

MC MC

SI_1_CLKN

MC MC

SI_1_DN_0

MC

SI_1_DN_1

MC MC MC

SI_1_DN_2 MC MC

SI_1_DN_3

MC

SI_2_CLKP

SI_2_CLKN

MC

MCSI and Camera interface

SDMMC1

SDMMC2

SDMMC3

MCSI_2_DN_0 MC MC

SI_2_DN_1

MC

GP

_CAMERASB00 _CAMERASB01

GP GP

_CAMERASB02 _CAMERASB03

GP GP

_CAMERASB04 _CAMERASB05

GP GP

_CAMERASB06 _CAMERASB07

GP GP

_CAMERASB08

GP

_CAMERASB09 _CAMERASB10

GP GP

_CAMERASB11

MMC1_CLK

SD

MMC1_CMD

SD

SD SD SD

SD

MMC1_D3_CD_B

1_D4_SD_WE

MMC

SD

MMC1_RCOMP

SDMMC2_CLK

SD

MMC2_CMD

SD SD SD

MMC2_D3_CD_B

SD

MMC3_CLK

SD

MMC3_CMD

SD

MMC3_CD_B

SD SD SD SD

MMC3_1P8_EN

SD

MMC3_PWR_EN_B

SD

MMC3_RCOMP

RS

VD_K48 VD_K47

RS

VD_K44

RS

SI_1_DP_0

SI_1_DP_1

SI_1_DP_2

SI_1_DP_3

SI_2_DP_0

SI_2_DP_1

SI_COMP

MMC1_D0 MMC1_D1 MMC1_D2

MMC

1_D5

MMC

1_D6

MMC

1_D7

1_RCLK

MMC2_D0 MMC2_D1 MMC2_D2

MMC3_D0 MMC3_D1 MMC3_D2 MMC3_D3

K48 K47 K44

T44 T45

Y47 Y48 V45 V47 V50 V48 T41 T42

P50 P48

P47 P45 M48 M47

P44

AB41 AB45 AB44 AC53 AB51 AB52 AA51 AB40 Y44

Y42 Y41 V40

M7

P6

M6 M4 P9 P7 T6 T7 T10 T12 T13 P13

K10 K9

M12 M10 K7 K6

F2 D2 K3

J1 J3 H3 G2

K2 L3 P12

3

MC

_CAMERASB08

GP

_CAMERASB09

GP

_CAMERASB11

EM

MC_CLK_R

EM

MC_RCLK_R

MMC1_COMP

SD

MMC3_COMP

3

SI_COMP

H_EDP_BLON_C

PC

R1

24 150_4

R1

10 0_4

EM

EM EM EM EM EM EM EM EM

R1

46 *0_4

R4

16 80.6_4

2

MC_CMD [21]

MC_DATA_0 [21] MC_DATA_1 [21] MC_DATA_2 [21] MC_DATA_3 [21] MC_DATA_4 [21] MC_DATA_5 [21] MC_DATA_6 [21] MC_DATA_7 [21]

D

GN

R2

10K_4

3

1

GN

D

GN

PC

H_DPST_PWM_C

EM

17

R4 100_4

6

Q1

1

PJA138K

D

MC_CLK [21]

MC_RCLK [21]

D

GN

2

+3

V

7

R2

10K_4

R8

PC

R5

10K_4

6

Q1

3

PJA138K

PC

H_EDP_BLON [21]

H_DISP_ON_C

+3V

7

R3

10K_4

H_DPST_PWM

PC

3

2

Q1

2

PJA138K

1

+1

.8V_S5

Size Document Number Rev

Date: Sheet of

3

0

Q1

2

PJA138K

1

3

2

1

GN

D

2

7

10K_4

3

Q1

7

PJA138K

2

1

GN

D

PC

H_DISP_ON_C H_EDP_BLON_C

PC

H_DPST_PWM_C

PC

Hardware Strap

GP_CAMERASB08

GP_CAMERASB09

GP_CAMERASB11

31 *10K_4

R4

25 *10K_4

R4 R4

20 *10K_4

V

alley 3/9 (Display)

Wednesday, April 08, 2015

alley 3/9 (Display)

2

H_DPST_PWM [13]

follow CRB v1.0

ICLK Xtal OSC Bypass

0 = No Bypass

1 = Bypass CCU SUS RO Bypass

0 = No Bypass

1 = Bypass RTC OSC Bypass

0 = No Bypass

1 = Bypass

_CAMERASB08

GP

_CAMERASB09

GP GP

_CAMERASB11

Qu

PROJECT :

1

+3

V

1

R8

10K_4

PC

32 100K_4

R4

26 100K_4

R4 R4

21 100K_4

Z8AD

H_DISP_ON [13]

+1

.8V_S5

R40 *0_4

3

5

Q1 PJA138K

1

R9

7 *100K_4 9 *100K_4

R3 R7

8 *100K_4

Strap Description

anta Computer Inc.

1

GN

D

3A

324

5

+1

.05V_S5[6,8,26,28,29]

+1

.8V[9,12,13,14,15,16,19,20,21,22,26,30]

SAT

A_TXP0[16]

SAT

+1

OD

.8V_S5

R8

*100K/F_4

A_TXN0[16]

SAT

A_RXP0[16]

SAT

A_RXN0[16]

SAT

A_TXP1[16]

SAT

A_TXN1[16]

SAT

A_RXP1[16]

SAT

A_RXN1[16]

SO

C_KBC_SCI[14]

DE

VSLP0[16]

D_PRSNT#[16]

16

R1

402_4

10

+1

.8V_S5

84 *short_4

R4

00 *short_4

R4

VSLP0

DE

77 *0_4

R4

SATA HDD

D D

TA ODD

SA

SO

C_KCB_SMI[14]

IO_SUS7

01 *0_4

GP

IO_SUS7[6]

C C

High is SSD ,Low is ODD

SSD

_ID[16]

R1

Add SSD ID 1/14

11

R8

10K_4

A_GP3

SAT

C_SPI_CLK

SO

C_SPI_CS#

SO

T_SPI_D0

FS

T_SPI_D1

FS

T_SPI_D2

FS

T_SPI_D3

FS

SAT SAT

A_RCOMP_DP

SAT

A_RCOMP_DN

SAT

BI

4

A_GP0 A_GP1

A_GP3 A_LED#

OS_STRAP

AK10 AK12 AK13

C31 B30

N28 M28

C29 A29

J28

K28

AH2 AG3 AG1 AF3 AH3

N30 M30

W3

V4 V6 V7

V2 V3 U1 U3

B16 C16

AK9

U23D

SAT

A_TXP_0

SAT

A_TXN_0

SAT

A_RXP_0

SAT

A_RXN_0

SAT

A_TXP1

SAT

A_TXN_1

SAT

A_RXP_1

SAT

A_RXN_1

SAT

A_GP0

SAT

A_GP1

SAT

A_GP2

SAT

A_GP3

SAT

A_LED

SAT

A_OBSP

SAT

A_OBSN

FS

T_SPI_CLK

FS

T_SPI_CS0_B

FS

T_SPI_CS1_B

FS

T_SPI_CS2_B

FS

T_SPI_D0

FS

T_SPI_D1

FS

T_SPI_D2

FS

T_SPI_D3

RS

VD_B16

RS

VD_C16

GP

_SSP_2_CLK

GP

_SSP_2_FS

GP

_SSP_2_TXD

GP

_SSP_2_RXD

VLV_M_D/BGA

REV = 1.15

4

OF 12

PC PC

IE_RXN_0

PC PC

IE_TXN_1

PC

IE_RXP_1

PC

IE_RXN_1

PC PC

IE_TXN_2

PC

IE_RXP_2

PC

IE_RXN_2

PC PC

IE_TXN_3

PC

IE_RXP_3

PC

IE_RXN_3

PC

IE_CLKREQ0B

PC

IE_CLKREQ1B

PC

IE_CLKREQ2B

PC

IE_CLKREQ3B

PC PC

M

F_HDA_RSTB

MF

_HDA_SYNC

MF

_HDA_CLK

MF

_HDA_SDO

MF

_HDA_SDI0

MF

_HDA_SDI1

M

F_HDA_DOCKRSTB

M

F_HDA_DOCKENB

PR

IE_TXP_0 IE_TXN_0

IE_RXP_0

IE_TXP_1

IE_TXP_2

IE_TXP_3

IE_OBSP IE_OBSN

SPKR

OCHOT

3

C24 B24

G20 J20

A25 C25

D20 F20

B26 C26

D22 F22

A27 C27

G24 J24

AM10 AM12 AK14 AM14

D26 F26

AF13 AF12 AD9 AF14 AD7 AD6 AB7 AB9

H4

AD50

0.1U/16V_4

IE_TXP1_NGFF_C

PC

IE_TXN1_NGFF_C

PC

IE_TXP2_WLAN_C

PC

IE_TXN2_WLAN_C

PC

IE_TXP3_LAN_C

PC

IE_TXN3_LAN_C

PC

SP7

IE_CLKREQ1_NGFF #

PC

IE_CLKREQ2_W LAN#

PC

IE_CLKREQ3_LAN#

PC

C_PCIE_COMP

SO

C_PCIE_COMN

SO

Z_RST#

AC

Z_SYNC

AC

Z_BCLK

AC

Z_SDOUT

AC

Z_SDIN0

AC

C_PROCHOT#

SO

54

C3

GN

_R

D

C3 C3

33 *short_4

R4

48 20K_4

R4

43 0.1U/16V_4 44 0.1U/16V_4

42 0.1U/16V_4 41 0.1U/16V_4

40 0.1U/16V_4 48 0.1U/16V_4

68 75_4

R2

64 75_4

R2

58 75_4

R2

65 75_4

R2

62 *short_4

R2

CRB is 75 ohm

PC

IE_TXP1_NGFF [19]

PC

IE_TXN1_NGFF [19 ]

PEG

_RXP1_NGFF [19]

PEG

_RXN1_NGFF [19 ]

PC

IE_TXP2_WLAN [20]

PC

IE_TXN2_WLAN [20]

PC

IE_RXP2_WLAN [20]

PC

IE_RXN2_WLAN [20]

PC

IE_TXP3_LAN [12]

PC

IE_TXN3_LAN [ 12]

PC

IE_RXP3_LAN [12]

PC

IE_RXN3_LAN [12 ]

PC

IE_CLKREQ1_NGFF # [19]

PC

IE_CLKREQ2_W LAN# [20]

PC

IE_CLKREQ3_LAN# [12]

PC PC PC PC PC

.8V_S5

+1

2

NGFF X1

WLAN x1

LAN x1

07

R1 402_4

H_AZ_CODEC_RST# [1 8] H_AZ_CODEC_SYNC [18] H_AZ_CODEC_BITCLK [18] H_AZ_CODEC_SDOUT [18] H_AZ_CODEC_SDIN0 [18]

AC

Z_SPKR [18]

H_

PROCHOT# [22,24,28,29]

IE_CLKREQ1_NGFF #

PC

IE_CLKREQ2_W LAN#

PC

IE_CLKREQ3_LAN#

PC

VSLP0

DE

_R

SP7

25 10K_4

R5

23 10K_4

R5

22 10K_4

R5

78 10K_4

R4

21 10K_4

R5

1

.8V_S5

+1

SPI NOR FLASH

B B

T_SPI_D2

FS

T_SPI_D3

FS

A A

5

64

C3

0.1U/16V_4

39 10_4

R4

94 10_4

R4

U2

2

#

_HOLD

5

C_SPI_MOSI_R

SO

SPI

_SI

2

C_SPI_MISO_R

SO

SPI

_SO

1

C_SPI_CS#_R

SO

CS

#

6

C_SPI_CLK_R

_SCK

GN

SO

4

D

GN

SPI

95 10_4

R4

38 10_4

R4

40 33_4

R4

96 10_4

R4

2nd source: AKE5EG-0Q01

SO

C_SPI_CS#

FS

T_SPI_D2_R

FS

T_SPI_D3_R

AC

4

T_SPI_D0

FS

T_SPI_D1

FS

C_SPI_CS#

SO

C_SPI_CLK

SO

BI

OS_STRAP

V_S5

+3

R3

56

10K_4

3

R3

PRESENT[24]

51 *short_4

AC

_PRESENT_NM

2

1

GN

D

3

2

Q4

3

2N7002K

2N7002K Q4

1

AC Present: This input pin indicates when the platform is plugged into AC power.

_PRESENT [6]

AC

2

0 = LPC 1 = SPI

.8V_S5

+1

13

R5 *10K_4

R5

14

*10K_4

GN

D

anta Computer Inc.

Qu

PROJECT :

Si

ze Document Number Rev

Size Document Number Rev

We

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

PROJECT :

Valley 4/9 (SD/PCIE/SATA)

Z8AD

of

325

of

325

of

1

325

3A

8

VC

D

GN

T_SPI_D2_R

FS

T_SPI_D3_R

FS

+1

.8V_S5

C

3

WP

7

SPI

SPI_FLASH

soic8-7_9-1_27

AKE5EZN0N00

IC FLASH (8P) W25Q64FWSSIG (SOIC)

R1

40 3.3K_4

R1

39 3.3K_4

R4

93 3.3K_4

5

0 12P/50V_4

C4

D

GN

D

GN

D D

C C

+1

.8V_S5

B B

C3

2nd source:BG619200014 (TXC)

Hardware Strap

GPIO_SUS[0]

GPIO_SUS[1]

GPIO_SUS[2]

GPIO_SUS[4]

GPIO_SUS[5] Security Flash Descriptors

GPIO_SUS[8]

GPIO_SUS[9]

GPIO_SUS[10] POSM Select

93 4.7K_4

R3

96 4.7K_4

R3

25 10K_4

R1

35 100K_4

R4

29 100K_4

R4

08 *10K_4

R4

13 *1K_4

R4

98 *10K_4

R3

23 4.7K_4

R4 R4

24 *4.7K_4

R4

56 *10K_4

AL25_OUT

XT

1

2

Y7

6

R3

200K_4

2MHZ

19.

4

3

AL25_IN

XT

9 12P/50V_4

NG

FF

AN

WL

LAN

Strap Description

0 = DDI0 not detected

1 = DDI0 detected

0 = DDI1 not detected

1 = DDI1 detected

Top Swap(A16 Override) 0 = Change Boot Loader address

1 = Normal Operation

BIOS Boot Selection 0 = No SPI

1 = SPI

0 = Override

1 = Normal Operation ICLK,USB 2.0,DDI SFR supply select

0 = Supply is 1.25V

1 = Supply is 1.35V ICLK,USB 2.0,DDI SFR Bypass 0 = No bypass

1 = Bypass with 1.05V (internal PU)

0 = Fuse controller

1 = PMC (internal PD)

IO_SUS0

94 *10K_4

GP

R3

IO_SUS1

97 *10K_4

GP

R3

IO_SUS2

48 *10K_4

GP

R1

IO_SUS4

36 *10K_4

GP

R4

IO_SUS5

30 *4.7K_4

GP

R4

IO_SUS8

09 4.7K_4

GP

R4

IO_SUS9

14 *10K_4

GP

R4

IO_SUS10

99 *10K_4

GP

R3

IO_SUS6

GP GP

IO_SUS7

GP

R4

IO_SUS3

63 *10K_4

GN

IO_SUS7 [5]

GP

D

CL

K_PCIE_NGFFN[19]

CL

K_PCIE_NGFFP[19]

CL

K_PCIE_WLANN[20]

CL

K_PCIE_WLANP[20]

CL

K_PCIE_LANN[12]

CL

K_PCIE_LANP[12]

GN

41 2.49K_4

R1

15 49.9_4

R1

D

12/29

R5

R1

D

GN

BO BO BO BO BO BO

81 *100_4

56 100_4

AL25_IN

XT

AL25_OUT

XT

LK_ICOMP

IC

LK_RCOMP

IC

ARD_ID0 ARD_ID1 ARD_ID2 ARD_ID3 ARD_ID4 ARD_ID5

SO

11/28 modify

R5

8 1K_4

3

R8

_Override[22]

EC

A A

5 *short_4

SO

C_Override_NM

2

2N7002K Q1

4

1

GN

D

IO_SUS0

GP

IO_SUS1

GP

IO_SUS2

GP

IO_SUS3

GP

IO_SUS4

GP

IO_SUS5

GP

IO_SUS6

GP

IO_SUS7

GP

IO_SUS8

GP

IO_SUS9

GP

IO_SUS10

GP

C_GPIO_RCOMP

GP

IO_SUS5

4

M22

M26

AH45

AM40 AM41 AM44 AM45 AM47 AK48 AM48 AK41 AK42

AD51 AD52 AH50 AH48 AH51 AH52 AG51 AG53 AF52 AF51 AE51 AC51

AH40

P24

J26 N26 P20 N20 P26 K26

C21 A21

B20 C19

B18 C18

A17 C17

C9

Y13 Y12 V13 V12 V14

IC IC

RS RS IC IC RS RS RS RS

PC PC

A9

MF MF

B8

MF

B7

MF

B5

MF

B4

MF

S S SPI SPI SPI

GP GP GP GP GP GP GP GP GP

GP GP GP GP GP GP GP GP SEC SEC SEC SEC

GP

Y3

GP

U23E

LK_OSCIN LK_OSCOUT

VD_J26

VD_N26 LK_ICOMP LK_RCOMP

VD_P26

VD_K26

VD_M26

VD_AH45

IE_CLK_DIFF_N_ 0

IE_CLK_DIFF_P_0

IE_CLK_DIFF_N_ 1

IE_CLK_DIFF_P_1

IE_CLK_DIFF_N_ 2

IE_CLK_DIFF_P_2

IE_CLK_DIFF_N_ 3

IE_CLK_DIFF_P_3

_PLT_CLK0

_PLT_CLK1

_PLT_CLK2

_PLT_CLK3

_PLT_CLK4

_PLT_CLK5

PI1_CS0_B PI1_CS1_B

1_MISO 1_MOSI 1_CLK

IO_DFX0

IO_DFX1

IO_DFX2

IO_DFX3

IO_DFX4

IO_DFX5

IO_DFX6

IO_DFX7

IO_DFX8

IO_SUS0

IO_SUS1

IO_SUS2

IO_SUS3

IO_SUS4

IO_SUS5

IO_SUS6

IO_SUS7

_GPIO_SUS9 _GPIO_SUS8 _GPIO_SUS10 _GPIO_SUS11

IO0_RCOMP

IO0_ALERT

VLV_M_D/BGA

REV = 1.15

3

+1

.8V_S5[4,5,7,9,13,14,22,24,26,28,29]

+3

VPCU[8,9,12,15,16,18,19,21,22,24,25,26]

+1

.05V_S5[8,26,28,29]

AD12

RT1_RXD

AD10 AD14 AD13

Y7 Y6 V10 V9

AE3 C15 A13 C12 B14

C13 N16 C14 M16 AF2 F14 D14 B12 P18

J16 D18

F18 G16

M18 K18 F16 G18

AD40 AD41 AD42

C11 B10 F12 F10 D12

E8 C7 D6

J12 F7 J14 L13

ARD ID

ARD_ID0 ARD_ID1 ARD_ID2 ARD_ID3 ARD_ID4 ARD_ID5

UA

RT1_TXD

UA

PU_EVENT#_Q

DG

_CLAMP_REQ#_Q

FB

PU_EN

VG

PU_HOLD_RST#_Q

DG

PU_PWR_EN_Q

DG

PU_PWROK_Q

DG

S_PWRDOW NACK

SU

U_WIFI_SUSCL K_R

PM

P_S0IX#

SL

P_S4#

SL

P_S3#

SL

_PRESENT

AC

C_PMC_WAKE

SO

U_BATLOW#

PM

C_PWRBTN#

SO

C_REST_BTN#

SO

C_PLTRST#

SO

H_SUS_STAT#

PC

C_RTEST#

SO

T_CRST#

SR

C_RSMRST#

SO

RE_PWROK

CO

C_X1

RT

C_X2

RT

TC_EXTPAD

BR

D_ALERT#_SOC

SVI

D_DATA_SOC

SVI

D_CLK_SOC

SVI

_INT#

TP

ensor_INT

Gs

_INT_C

TP

_RST#_Q

TP

H_ODD_EN

PC

_INT#

TP

_INT_C

TP

_RST#_Q

TP

ensor_INT

Gs

BO

ARD_ID1

R6

01 NGS@10K_4

R3

86 *10K_4

R3

87 *10K_4

R3

88 NTPM@10K_4

R3

89 10K_4

R3

90 NAC@10K_4

82 *short_4

R4

C7 R1

R4 R4 R4

45

TP

UA

RT1_RXD

UA

RT1_TXD

U

ART1_RTS_B

U

ART1_CTS_B

UA

RT2_RXD

UA

RT2_TXD

U

ART2_RTS_B

U

ART2_CTS_B

SU

SPWRDNACK

PM

U_SUSCLK

P

MU_SLP_S0IX_B P

MU_SLP_S4_B

P

MU_SLP_S3_B

PM

U_AC_PRESENT

PM

U_WAKE_B

P

MU_BATLOW_B

P

MU_PWRBTN_B

P

MU_RESETBUTTON_B

P

MU_PLTRST_B

S

US_STAT_B

P

MU_SLP_LAN_B

P

MU_WAKE_LAN_B

R

TEST_B

S

RTCRST_B

R

SMRST_B

CO

REPWROK

BR

TCX1_PAD

BR

TCX2_PAD

BVC

CRTC_EXTPAD

RS

VD_VSS

S

VID0_ALERT_B

SVI

D0_DATA

SVI

D0_CLK

RS

VD_C11

RS

VD_B10

RS

VD_F12

RS

VD_F10

RS

VD_D12

RS

VD_E8

RS

VD_C7

RS

VD_D6

RS

VD_J12

RS

VD_F7

RS

VD_J14

RS

VD_L13

OF 12

5

R4

IO8[13]

GP

+1

.8V_S5

R6

00 *GS@10K_4

R3

69 10K_4

R3

70 10K_4

R3

71 *TPM@10K_4

R3

72 *10K_4

R3

73 *AC@10K_4

BOARD_ID0 :"H" W/ G-Sensor; "Low " W/O G-Sensor BOARD_ID1 :"H" W/ touch panel; "Low " W/O touch panel BOARD_ID2 :"H" is UMA ; "Low " is DIS BOARD_ID3 :TPM ; HIGH=TPM, LOW=W/O TPM BOARD_ID4 :"L" is for Z8AD,MB ID BOARD_ID5 :IOAC ; High=IOAC ,Low=non-IOAC

4 *short_4

BO

BO BO BO BO BO BO

7 0.1U/16V_4 00 10K_4

52 *short_4 49 *short_4 57 *short_4

46

TP

2/11

32

TP

28

TP

30

TP

31

TP

26

TP

23

TP

27

TP

24

TP

TP PC

+1

.8V_S5

6710K_4

R3

0210K_4

R4

7510K_4

R3

8510K_4

R3

SU

SPWRDANCK [14]

SL

P_S0IX# [14,26]

SL

P_S4# [2,14]

SL

P_S3# [14,26]

AC

_PRESENT [5]

SO

C_PMC_WAKE [14]

SO

C_PWRBTN# [14]

SO

C_PLTRST# [14,21]

PC

H_SUS_STAT# [14]

SO

C_RSMRST# [1 4]

CO

RE_PWROK [14]

GN

D

GN

D

_SVID_ALERT#

VR

_SVID_DATA

VR

_SVID_CLK

VR

TP

_INT# [14]

Gs

ensor_INT [21]

TP

_INT_C [1 4] _RST#_Q [14] H_ODD_EN [16]

+3

2

VR

To

Touch panel

11/26 modify

RT

C Circuitry(RTC)

V_RTC_0

+3

V_RTC_0

12

CN2

1

BAT_CONN

GN

D

VR

_SVID_ALERT# [2 8,29]

VR

_SVID_DATA [28,2 9] _SVID_CLK [28 ,29]

uch pad

20mils

VPCU

+3

R5

59 1K_4

20M

H_SUS_STAT#

PC

U_BATLOW#

PM

S_PWRDOW NACK

SU

C_PMC_WAKE

SO

_PRESENT

AC

P_S4#

SL

P_S3#

SL

P_S0IX#

11/28 modify

*0.1u/16V_4

D3

0

VC

CRTC_1

BAT54C

20MIL

IL 20MIL

SL

C_REST_BTN#

SO

C_PLTRST#

SO

_PRESENT

AC

SPWRDANCK

SU

RE_PWROK

CO

Change from +1.0V to +1.05V

53

C3

D

GN

D_DATA_SOC

SVI

D_ALERT#_SOC

SVI

D_CLK_SOC

SVI

C Clock 32.768KHz

RT

C_X1

RT

C_X2

+3

V_RTC

R3

68 20K_4

30mils

R3

65 20K_4

C4

14

1u/6.3V_4

6/25 Change G9G10 footprint from "SOLDERJUMPER-2" to "RC0603-C" for SMT request

1

47 *10K_4

R3

84 10K_4

R3

81 10K_4

R4

01 10K_4

R4

66 10K_4

R3

3 *10K_4

R2

4 *10K_4

R2

3 *10K_4

R4

79 2.7K_4

R4

5 *1K_4

R6

55 *10K_4

R3

83 *100K_4

R4

8 0.1U/16V_4

C7

+1.05V_S5

53

50

R4

*200_4

3

R3

10M_4

2013/07/25 change package , P/N change from BG332768224 to BG332768453

C3 1u/6.3V_4

*301_4

200_4

12

Y6

768KHZ

32.

12

G6

47

*S

38

+1

58

R4

SO

C_RTEST#

HORT_ PAD1

SR

T_CRST#

.8V_S5

C4

GN

D

GN

D

GN

D

115P/50V_4

215P/50V_4

GN

D

Qu

anta Computer Inc.

PROJECT :

Si

Size Document Number Rev

ze Document Number Rev

We

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

5

4

3

2

dnesday, April 08, 2015

PROJECT :

lley 5/9 (SPI/GPIO/CLK)

Va

Z8AD

3A

of

326

of

326

of

1

326

5

+1

.8V_S5 [4,5,6,9,13,14,22,24,26,28,29]

+3

V [4,9,11,12,13,14,15,16,18,19,21,22,25,27,28,29,30]

US

B30_TX0+[17]

US

B30_TX0-[17]

US

B30_RX0+[17]

US

B30_RX0-[17]

D D

06

R1

402_4

C C

37 22_4

CL

GN

.8V_S5

K_24M_KBC[22]

CL

KRUN#[15,22]

LF

RAME#[15,19,20,22]

SO

C_SERIRQ[14,15]

14 100_4

R1

D

85 1K_4

R1

86 1K_4

R1 R5

08 1K_4

R5

09 *short_4

46 22_4

P_H_TDO

XD

P_H_TMS

XD

P_H_TDI

XD

P_H_PREQ#

XD

P_H_TRST#

XD

P_H_TCK

XD

VD_M13

RS

R4

5

43 TPM@22_4

For TPM

SM

+1

B1ALERT#[16]

CL

K_24M_DEBUG[19,20]

CL

K_TPM[15]

+1

.8V_S5

27 51_4

R1

28 51_4

R1

B B

A A

GN

R4 R1

R4 R1 R4

D

44 51_4 26 51_4

45 51_4 67 51_4 15 *10K_4

R4

42 22_4

R4

RAME#

LF

D0

LA

D0[15,19,20,22]

LA

D1[15,19,20,22]

LA

D2[15,19,20,22]

LA

D3[15,19,20,22]

LA

D1

LA

D2

LA

D3

LA

TP

29

B_SOC_DATA

SM

B_SOC_CLK

SM SM

B_SOC_ALERTB

B3_OBSP

US

B3_OBSN

US

SO SO

SO

LP

P_H_TCK

XD

P_H_TDI

XD

P_H_TDO

XD

P_H_TMS

XD

P_H_TRST#

XD

P_H_PRDY#

XD

P_H_PREQ#

XD

VD_M13

RS

4

C_CLKOUT_0 C_CLKOUT_1

C_CLKRUN#

C_SERIRQ

C_RCOMP

4

GN

B32 C32 F28 D28

A33 C33 F30 D30

C34 B34

G32

J32

C35 A35

G34

J34

D34 F34

C37 A37 F36

D36 M34 M32

C38

B38 G36

J36

N34

P34

P2 R3

T3

P3 M3 M2 N3 N1

T2

T4

AF42 AD47 AF40 AD48 AB48

AD45 AF41

M13

AM7 AM6 AM9

D

U23F

US

B3_TXP0

US

B3_TXN0

US

B3_RXP0

US

B3_RXN0

US

B3_TXP1

US

B3_TXN1

US

B3_RXP1

US

B3_RXN1

US

B3_TXP2

US

B3_TXN2

US

B3_RXP2

US

B3_RXN2

US

B3_TX3

US

B3_TXN3

US

B3_RXP3

US

B3_RXN3

US

B3_OBSP

US

B3_OBSN

RS

VD_C37

RS

VD_A37

RS

VD_F36

RS

VD_D36

RS

VD_M34

RS

VD_M32

RS

VD_C38

RS

VD_B38

RS

VD_G36

RS

VD_J36

RS

VD_N34

RS

VD_P34

MF

_LPC_CLKOUT0

MF

_LPC_CLKOUT1

LP

C_CLKRUNB

LP

C_FRAMEB

MF

_LPC_AD0

MF

_LPC_AD1

MF

_LPC_AD2

MF

_LPC_AD3

IL

B_SERIRQ

LP

C_HVT_RCOMP

TC

K

TD

I

TD

O

TM

S

T

RST_B

C

X_PRDY_B

C

X_PREQ_B

RS

VD_M13

MF

_SMB_DATA _SMB_CLK

MF

F_SMB_ALERTB

M

VLV_M_D/BGA

REV = 1.15

C1

85 0.1U/25V_4

SM

B_SOC_DATA

SM

B_SOC_CLK

+1

.8V_S5

1

2

4

3

1

U1

D

GN

EF1

VR

A1

SD

L1

SC

PCA9306

3

B_OTG_ID

US

B_DP0

US

B_DN0

US

B_DP1

US

B_DN1

US

B_DP2

US

B_DN2

US

B_DP3

US

B_DN3

US

B_DP4

US

B_DN4

US

B_OC_00

US

B_OC_11

RS

VD_B46

B_VBUSSNS

B_RCOMP

RS

VD_H5

RS

VD_H7

RS

VD_P28

RS

VD_P30

RS

VD_AF50

RS

VD_AF48

RS

VD_AF44

RS

VD_AF45

I2

C0_SDA

I2

C0_SCL

I2

C1_SDA

I2

C1_SCL

I2

C2_SDA

I2

C2_SCL

I2

C3_SDA

I2

C3_SCL

I2

C4_SDA

I2

C4_SCL

I2

C5_SDA

I2

C5_SCL

I2

C6_SDA

I2

C6_SCL

VD_Y2

RS

VD_AA3

RS

B48

C42 B42

C43 B44

C41 A41

C45 A45

B40 C40

P14 P16

B46

B47

A48

M36 N36

K38 M38

N38

H5 H7

P28 P30 AF50 AF48 AF44 AF45

AH7 AK6

AH6 AF6

AF7 AF9

AD2 AE4

AD3 AC1

AC3 AB2

AB3 AA1

Y2 AA3

B2_OBSP

US

B_VBUSSNS

US

B_RCOMP

US

B_HSIC_RCOMP

US

C_0_SDA_R

I2

C_0_SCL_R

I2

C_1_SDA

I2

C_1_SCL

I2

C_2_SDA_R

I2

C_2_SCL_R

I2

C_3_SDA

I2

C_3_SCL

I2

C_4_SDA

I2

C_4_SCL

I2

C_5_SDA

I2

C_5_SCL

I2

C_6_SDA

I2

C_6_SCL

I2

C_NFC_SOC_SDA

I2

C_NFC_SOC_SCL

D

GN

1810K_4

R4

1910K_4

R4

1 *49.9_4

R9

10 *short_4

R5

15 *short_4

R5

90 *short_4

R4

01 *short_4

R5

03 *short_4

R5

92 *short_4

R4

R2

16

2.2K_4

R2

2.2K_4

T7 T6

17

US

B_HSIC_0_STROBE US

B_HSIC_0_DATA

US

B_HSIC_1_STROBE US

B_HSIC_1_DATA

US

B_HSIC_RCOMP

6

OF 12

+3

V

R2

18

200K_4

8

C2

EN

EF2

VR

A2

SD

L2

SC

06 0.1U/25V_4

7

5

6

3

US

BP0+ [17]

US

BP0- [17]

US

BP1+ [17]

US

BP1- [17]

US

BP2+ [13]

US

BP2- [13]

US

BP3+ [13]

US

BP3- [13]

US

BP4+ [19,20]

US

BP4- [19,20]

SO

C_USB_OC0 [17]

83 *short_4

R3

82 *0_4

R3

81 113_4

R3

B_RUN_DAT [11,20,21]

SM

B_RUN_CLK [11,20, 21]

SM

2

+1

.8V_S5

R1

I2

C_0_SDA [14]

I2

C_0_SCL [14]

I2

C1_SDA_GPIO6 [13]

I2

C1_SCL_GPIO7 [13]

I2

C_2_SDA [21]

I2

C_2_SCL [21]

2

Port 1 is debug port

USB3. 0

US

B2

uchPanel

To

CAMERA

BT

.8V_S5

+1

GN

D

GN

D

GN

D

GN

1145.3_4

GN

Touch pad

G S

1

61

R3 *20K_4

36

C3

*0.1U/16V_4

D

Touch panel

ensor

C_0_SDA

I2

C_0_SCL

I2

C_1_SDA

I2

C_1_SCL

I2

C_2_SDA_R

I2

C_2_SCL_R

I2

C_3_SDA

I2

C_3_SCL

I2

C_4_SDA

I2

C_4_SCL

I2

C_5_SDA

I2

C_5_SCL

I2

C_6_SDA

I2

C_6_SCL

I2

C_NFC_SOC_SDA

I2

C_NFC_SOC_SCL

Si

Size Document Number Rev

ze Document Number Rev

We

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

11 1K_4

R5

16 1K_4

R5

89 1K_4

R4

00 1K_4

R5

02 1K_4

R5

91 1K_4

R4

64 1K_4

R4

80 1K_4

R4

65 *1K_4

R4

66 *1K_4

R4

67 *1K_4

R4

68 *1K_4

R4

69 *1K_4

R4

70 *1K_4

R4

72 *1K_4

R4

71 *1K_4

change to 1K as CRB

anta Computer Inc.

Qu

PROJECT :

Valley 6/9 (USB/LPC/I2C)

1

+1

.8V_S5

Z8AD

3A

of

327

of

327

of

327

5

+V

CC_CORE [28]

+V

GG [29]

+3

V [4,7,9,11,12,13,14,15,16,18,19,21,22,25,27,28,29,30]

+1

.05V_S5 [6,26,28,29]

+1

.15V [26]

VC

C1_SENSEP[28]

VC

C1_SENSEN[28]

VG

G_SENSEP[29]

VG

69

C1

1U/10V_4

CO

DDI

FU

5

C1 10u/6.3V_6

G_SENSEN[29]

+V

64

C1 22uF/6.3V_6

+V

50

C1 22uF/6.3V_6

+V

GG

57

D

GN

RE_V1P15_PWR

CO

67

C1

1U/10V_4

RE_V1P15_PWR

_1P15_PWR

SE_1P15_PWR

CC_CORE

77

C1 10u/6.3V_6

D D

60

C1 22uF/6.3V_6

D

GN

52

C1 22uF/6.3V_6

D

54

GN

95

C5

22uF/6.3V_6

96

C5 *22uF/6.3V _6

C C

C1

*1U/10V_4

1/7 add

58

97

C1

C5 *10u/6.3V_6

B B

1/13 Add

+1

.15V

A A

D

GN

76 *short_8

R1

83 *short_8

R1

92 *short_8

R1

91 *short_8

R1

66

1U/10V_4

*SHORT_6

3/16 change 0 ohm by acer

C1_SENSEP

VC

C1_SENSEN

VC

T8

Fixed Vnn Sense

C1 10u/6.3V_6

_1P15_PWR

DDI

70 1U/10V_4

56

C1

1U/10V_4

59

C1

4.7uF/6.3V_6

63

C1

4.7uF/6.3V_6

80

C1

C1 10U/6.3V_6

GN

D

61

C1

4.7uF/6.3V_6

62

C1

4.7uF/6.3V_6

72

C1

1U/10V_4

C1

D

GN

R4 R4 R4 R4

79

C1 22uF/6.3V_6

C1

1U/10V_4

83 1U/10V_4

01

872.2_4

982.2_4

862.2_4

972.2_4

68

C0_SENSEP_R

VC

C0_SENSEN_R

VC

C1_SENSEP_R

VC

C1_SENSEN_R

VC

VG VG VN

65

C1

4.7uF/6.3V_6

51

C1

4.7uF/6.3V_6

C1 22uF/6.3V_6

SE_1P15_PWR

FU

84

C1

1U/10V_4

C5

1

10U/6.3V_6

+V

GG

C5

98

*100U/6.3V_ 1206

GN

D

G_SENSEP G_SENSEN N_REFIN_R

78

1/13 Add

4

AG32

AJ32

AD29

AF27 AD24 AD22 AC27

AF36 AG33 AG35 AG36 AG38

AJ33

AJ36

AJ38

AF30 AG27 AG29 AG30

AJ27

AJ29

AJ30

AF29

AD16 AD18 AD19

AF16

AF18

AF19

AF21

AF22

AJ19 AG16 AG18 AG19 AG21 AG22 AG24

AJ21

AJ22

AJ24 AK24

AK30 AK35 AK36 AM29

AK33

AJ35

AM19 AK21

C5

4

10U/6.3V_6

4

U23G

CO

RE_VCC0_SENSE

CO

RE_VSS0_SENSE

CO

RE_VCC1_SENSE

CO

RE_VSS1_SENSE

DDI

_VGG_SENSE

UNCO

RE_VSS_SENSE[2]

UNCO

RE_VSS_SENSE[1]

CO

RE_VCC1_S0IX[3]

CO

RE_VCC1_S0IX[7]

CO

RE_VCC1_S0IX[8]

CO

RE_VCC1_S0IX[9]

CO

RE_VCC1_S0IX[10]

CO

RE_VCC1_S0IX[14]

CO

RE_VCC1_S0IX[15]

CO

RE_VCC1_S0IX[16]

CO

RE_VCC1_S0IX[2]

CO

RE_VCC1_S0IX[4]

CO

RE_VCC1_S0IX[5]

CO

RE_VCC1_S0IX[6]

CO

RE_VCC1_S0IX[11]

CO

RE_VCC1_S0IX[12]

CO

RE_VCC1_S0IX[13]

CO

RE_VCC1_S0IX[1]

DDI

_VGG_S0IX[1]

DDI

_VGG_S0IX[2]

DDI

_VGG_S0IX[3]

DDI

_VGG_S0IX[4]

DDI

_VGG_S0IX[5]

DDI

_VGG_S0IX[6]

DDI

_VGG_S0IX[7]

DDI

_VGG_S0IX[8]

DDI

_VGG_S0IX[15]

DDI

_VGG_S0IX[9]

DDI

_VGG_S0IX[10]

DDI

_VGG_S0IX[11]

DDI

_VGG_S0IX[12]

DDI

_VGG_S0IX[13]

DDI

_VGG_S0IX[14]

DDI

_VGG_S0IX[16]

DDI

_VGG_S0IX[17]

DDI

_VGG_S0IX[18]

DDI

_VGG_S0IX[19]

CO

RE_V1P15_S0IX[1]

CO

RE_V1P15_S0IX[2]

CO

RE_V1P15_S0IX[3]

CO

RE_V1P15_S0IX[4]

FU

SE_V1P15_S0IX[2]

FU

SE_V1P15_S0IX[1]

DDI

_V1P15_S0IX[2]

DDI

_V1P15_S0IX[1]

VLV_M_D/BGA

V = 1.15

RE

C5 10U/6.3V_6

3

RS

VD_AA30

+1

.05V_S5

AA18 AA19 AA21 AA22 AA24 AA25 AC18 AC19 AC21 AC22 AC24 AC25 AD25 AD27

AA30 V33 AA32 AA33 AA35 AA36 AC32 Y30 Y32 Y33 Y35

V19 V18

AM21 AM33 AM22 AN22 AN32 AM32

V22 V24

U24 U22

V27 U27

V29

N18 U19

3

R1

R7

R8

R7

R6

CSRANSOCI_OBS

VC

LK_1P05_PWR

IC

1P05_PWR

DDR_

PD_1P05_PWR

BM

BSSIC_1P05_PWR

US

SE3_1P05_PWR

FU

SE_1P05_PWR

FU

1

C8

1U/10V_4

D

GN

22 *short_8

49 *short_8

50 *short_8

89 *short_8

84 *short_8

5 *SHORT_6

3 *SHORT_6

0 *SHORT_6

9 *SHORT_6

6 *SHORT_6

49

C1

1U/10V_4

R1

C1

6

C6

1U/10V_4

7

C6

1U/10V_4

CO

RE_1P05_PWR

IC

LK_1P05_PWR

DDR_

1P05_PWR

US

BSSIC_1P05_PWR

BM

PD_1P05_PWR

FU

SE3_1P05_PWR

FU

SE_1P05_PWR

FU

SE1_1P05_PWR

53 *0_4

44 1U/10V_4

40 *1U/10V_4

71

C1

1U/10V_4

0

C8

1U/10V_4

GN

45

C1 1U/10V_4

37

C1

1U/10V_4

C1 10U/6.3V_6

6

C7

1U/10V_4

D

GN

D

C1

GN

D

86

GN

1

C6

1U/10V_4

D

GN

SE1_1P05_PWR [9]

FU

29

C1 1U/10V_4

04

1U/10V_4

C1 10U/6.3V_6

D

87

GN

UNCO

RE_VNN_S4[1]

UNCO

RE_VNN_S4[2]

UNCO

RE_VNN_S4[3]

UNCO

RE_VNN_S4[4]

UNCO

RE_VNN_S4[5] UNCO UNCO UNCO UNCO

UNCO UNCO UNCO UNCO UNCO

UNCO

RE_V1P15_S0IX[6]

UNCO

RE_V1P15_S0IX[1]

UNCO

RE_V1P15_S0IX[2]

UNCO

RE_V1P15_S0IX[3]

UNCO

RE_V1P15_S0IX[4]

UNCO

RE_V1P15_S0IX[5]

UNCO

RE_V1P15_S0IX[7]

UNCO

RE_V1P15_S0IX[8]

UNCO

RE_V1P15_S0IX[9]

UNCO

RE_V1P15_S0IX[10]

IC IC

DDR_ DDR_ DDR_ DDR_ DDR_ DDR_

PC

IE_V1P05A_G3[1]

PC

IE_V1P05A_G3[2]

SAT

A_V1P05A_G3[2]

SAT

A_V1P05A_G3[1]

US

B3_V1P05A_G3[2]

US

B3_V1P05A_G3[1]

US

BSSIC_V1P05A_G3

RE_VNN_S4[6]

RE_VNN_S4[7]

RE_VNN_S4[8]

RE_VNN_S4[9]

RE_VNN_S4[10] RE_VNN_S4[11] RE_VNN_S4[12] RE_VNN_S4[13] RE_VNN_S4[14]

LK_GND_OFF[2] LK_GND_OFF[1]

V1P05A_G3[1] V1P05A_G3[4] V1P05A_G3[2] V1P05A_G3[5] V1P05A_G3[6] V1P05A_G3[3]

3.5A

6.4A

1.9A

11A

0.7A

FU

SE3_V1P05A_G5

FU

SE_V1P05A_G3

7 OF 12

+1

.05V_S5

C5

5

0

10U/6.3V_6

C8

D

C1 10U/6.3V_6

CO

36

C1

1U/10V_4

6 1U/10V_4

2

28

RE_1P05_PWR

C1

C7

2

C9 10U/6.3V_6

05

1U/10V_4

2

1U/10V_4

1

.05V_S5

+1

41

C1 *1U/10V_4

18

hrm Protect

+3

VPCU

Si

Size Document Number Rev

ze Document Number Rev

We

Date: Sheet

IO T

03

R4 *10K_4

de

fault 25 degree for detect tempera ture

TH

RM_MOINTO R [22]

04

R4

*0_4

TH

ER_CPU

R3

92

*10K_6_NTC

dnesday, April 08, 2015

49

C3 *0.1U/16V_4

1 2

Qu

anta Computer Inc.

PROJECT :

lley 7/9 (Power 1)

Va

1

Z8AD

of

3A

328

26

C1 *1U/10V_4

30

C1

*1U/10V_4

C1 *1U/10V_4

GN

C1

1U/10V_4

D

GN

48

2

C5 10U/6.3V_6

D

6

+1 +3 +3 +3 +1 +1

D D

+1

.35VSUS

94

C1 22uF/6.3V_6

D

GN

3_3P3_PWR

CF

C C

B B

A A

+1

CF

CO GP

GP

.8V_S5

1_3P3_PWR

RE_1P8_PWR

IOCF2_1P8_PWR

IOCF1_1P8_PWR

+1

.35VSUS

5

.35VSUS [2,3,11,27] V_RTC [6] V_S5 [2,3,5,12,14,15,16,22,26] VPCU [6,8,12,15,16,18,19,21,22,24,25,26] .8V_S5 [4,5,6,7,13,14,22,24,26,28,29] .24VS5 [26]

LLDDR_1P35_PWR

+P

LKDDR_1P35_PWR

+C

82

C1 22uF/6.3V_6

12

R1

17

R1

80

R1

81

R2

10 *short_8

R2

11 *short_8

GN

5

GN

D

*SHORT_6

D

GN

D

GN

D

92

C1 22uF/6.3V_6

C8 C7

C7

C1

C1 C1 C1

C1 C1

SE_1P8_PWR

FU

IOCF2_1P8_PWR

GP

B_1P8_PWR

US

GP

IOCF1_1P8_PWR

+P

LLDDR_1P35_PWR

+C

LKDDR_1P35_PWR

5 1U/10V_4 1 1U/10V_4

9 1U/10V_4

55 1U/10V_4

20 1U/10V_4 27 1U/10V_4 21 1U/10V_4

73 1U/10V_4 74 1U/10V_4

96 1U/10V_4

C1

00 22uF/6.3V_6

C2

C1

99 22uF/6.3V_6

C1

97 1U/10V_4

1.9A

95

C1 22uF/6.3V_6

GN

C1

91

*1U/16V_4

D

GN

0.2A

C1 *1U/16V_4

D

AN27

AM25

BE1

BE53

BJ2 BJ3

BJ49

BJ5

BH50

BH5

BH49

BH4 BE3

BG51

BG3 BJ51 BJ52 AY10 AY44 AV44 AV10 BE51 AV38 AV16 AU36 AU18 AN36 AN35 AN19 AN18

AM36 AM18

E1 E2

G1 AH4 AF4 Y18

AD33 AK18 AF33 AK19

+3

.8V_S5

+1

90

U23H

DDRS

FR_VDDQ_G_S4

DDR_

VDDQ_G_S4[2]

DDR_

VDDQ_G_S4[16]

DDR_

VDDQ_G_S4[19]

DDR_

VDDQ_G_S4[26]

DDR_

VDDQ_G_S4[27]

DDR_

VDDQ_G_S4[28]

DDR_

VDDQ_G_S4[29]

DDR_

VDDQ_G_S4[25]

DDR_

VDDQ_G_S4[24]

DDR_

VDDQ_G_S4[23]

DDR_

VDDQ_G_S4[22]

DDR_

VDDQ_G_S4[17]

DDR_

VDDQ_G_S4[21]

DDR_

VDDQ_G_S4[20]

DDR_

VDDQ_G_S4[30]

DDR_

VDDQ_G_S4[31]

DDR_

VDDQ_G_S4[14]

DDR_

VDDQ_G_S4[15]

DDR_

VDDQ_G_S4[13]

DDR_

VDDQ_G_S4[10]

DDR_

VDDQ_G_S4[18]

DDR_

VDDQ_G_S4[12]

DDR_

VDDQ_G_S4[11]

DDR_

VDDQ_G_S4[9]

DDR_

VDDQ_G_S4[8]

DDR_

VDDQ_G_S4[7]

DDR_

VDDQ_G_S4[6]

DDR_

VDDQ_G_S4[5]

DDR_

VDDQ_G_S4[4]

DDR_

VDDQ_G_S4[3]

DDR_

VDDQ_G_S4[1]

SD

IO_V3P3A_V1P8A_G3 [1]

SD

IO_V3P3A_V1P8A_G3 [2]

SD

IO_V3P3A_V1P8A_G3 [3]

UNCO

RE_V1P8A_G3[2]

UNCO

RE_V1P8A_G3[1]

GP

IO_V1P8A_G3[5]

GP

IO_V1P8A_G3[1]

GP

IO_V1P8A_G3[3]

GP

IO_V1P8A_G3[2]

GP

IO_V1P8A_G3[4]

VLV_M_D/BGA

REV = 1.15

+3

V_S5

+3

V

+1

.8V

V_S5

V

+3

+1

.5V

+1

.8V_S5

4

74

R3

TWO PAD SHARING

R7

0

R7

R8

6

R9

R8

R1

4

1.9A

0.6A

OF 12

8

1 *0_6

4 *0_6

13 *0_6

65

63 *0_6

0.6A

RT RT

*SHORT_6

DDI

_VDDQ_G3[1]

DDI

_VDDQ_G3[2]

MI

PI_V1P2A_G3[2]

MI

PI_V1P2A_G3[1]

IC

LK_VSFR_G3[2]

IC

LK_VSFR_G3[1]

CO

RE_VSFR_G3[5]

CO

RE_VSFR_G3[6]

CO

RE_VSFR_G3[7]

CO

RE_VSFR_G3[4]

CO

RE_VSFR_G3[2]

CO

RE_VSFR_G3[3]

CO

RE_VSFR_G3[1]

US

BHSIC_V1P2A_G3 US

B_VDDQ_G3[2]

US

B_VDDQ_G3[3]

US

B_VDDQ_G3[1]

US

BSSIC_V1P2A_G3

US

B_V1P8A_G3

US

B_V3P3A_G3[2]

US

B_V3P3A_G3[1]

C_V3P3RTC_G5[2] C_V3P3RTC_G5[1]

RT

C_V3P3A_G5[1]

RT

C_V3P3A_G5[2]

FU

SE_V1P8A_G3

FU

SE1_V1P05A_G4

FU

SE0_V1P05A_G3

RS

B_3P3_PWR

US

3_3P3_PWR

CF

SD3 IO SUPPLY

3/2 add

V36 Y36

T40 P40

Y27 Y25

P38 V30 AC30

AF35 AD35 AD38 AC36

M41 U35 V35 H44 P41

AA29

C23 B22

C5 B6 D4 E3

U16 H10 G10 A3

VD_VSS

K20

VD_K20

M20

VD_M20

CF

1_3P3_PWR

LPC IO SUPPLY

CO

RE_1P8_PWR

AUDIO IO SUPPLY

_FUSE_PW R

TP

_FUSE_LDO

TP

C1

C9 C9

C8

C6 C9

C1

BHSIC_1P24_PWR

US

B_1P24_PWR

US

B2_1P24_PWR

US

BSSIC_1P24_PWR

US

C1 C1

C3

C7

C8

SE_1P8_PWR

FU

SE1_1P05_PWR

FU

3

_1P24_PWR

12 1U/10V_4

2 1U/10V_4 3 1U/10V_4

3 1U/10V_4

2 1U/10V_4 1 1U/10V_4

46 1U/10V_4

47 1U/10V_4 81 1U/10V_4

46 1U/10V_4

3 1U/10V_4

4 1U/10V_4

TP

12

TP

13

FU

SE1_1P05_PWR [8]

R3 10K_4

D

GN

DDI

GN

D

Y_1P24_PWR

DP

GN

D

LK_VSFR_1P24_PWR

IC

GN

D

L_1P24_PWR

PL

GN

D

LCPU_1P24_PW R

PL

GN

D

GN

D

GN

D

B_1P8_PWR

US

GN

D

B_3P3_PWR

US

GN

D

RTC_3P3

+V

C_3P3A_PWR

RT

GN

D

SE_1P8_PWR

FU

91

VSDIO VOLTAGE SETTING (CF3_3P3_PWR)

SDMMC3_PWR_EN_N

3

2

PLACE THE CAPS UNDER THE PKG SHADOW

BHSIC_1P24_PWR

US

D

GN

+1

.24VS5

SE1_1P05_PWR

FU

13

C1 1U/10V_4

D

GN

0

C9 1U/10V_4

D

GN

2

4

C9 1U/10V_4

4 *short_8

R6

08

R1

8

R9

3 *short_8

R6

2 *short_8

R6

0 *short_8

R6

13

R1

62 *short_8

R1

3

R9

1 *short_8

R6

B_1P24_PWR

US

2

C8 1U/10V_4

D

GN

IC

US

*SHORT_6

US

*SHORT_6

US

DDI

*SHORT_6

PL

DP

*SHORT_6

PL

󱻎󳠃󴧖

Si

Size Document Number Rev

Date: Sheet

B2_1P24_PWR

US

8

C6 1U/10V_4

LK_VSFR_1P24_PWR

BSSIC_1P24_PWR

BHSIC_1P24_PWR

B_1P24_PWR

B2_1P24_PWR

_1P24_PWR

LCPU_1P24_PW R

Y_1P24_PWR

L_1P24_PWR

+3

V_S5

9

R6

+3

VPCU

+3

ze Document Number Rev

R6

CAPS PLACE NEAR SOC PIN

V_RTC

R6

7

Valley 8/9 (Power 2)

We

dnesday, April 08, 2015

8 *0_6

1

BSSIC_1P24_PWR

US

4

C7 1U/10V_4

D

GN

9

C8

1U/10V_4

D

GN

RT

*SHORT_6

GN

anta Computer Inc.

Qu

PROJECT :

1

GN

C_3P3A_PWR

+V

RTC_3P3

C6

0

0.1U/16V_4

D

GN

53

C1

1U/10V_4

D

GN

Z8AD

D

C6

1U/10V_4

D

C7

0.1U/16V_4

D

C1 1U/10V_4

9

GN

0

06

D

of

3

C6

1U/10V_4

329

3A

5

D D

U23I

AN3

VSS[

98]

AN29

VSS[

97]

AN25

VSS[

96]

AN24

VSS[

95]

AN16

VSS[

94]

AN14

VSS[

93]

AN12

VSS[

92]

AN11

VSS[

91]

AN1

VSS[

90]

AM50

VSS[

89]

AM42

VSS[

88]

AM4

VSS[

87]

AM38

VSS[

86]

AM35

VSS[

85]

AH44

VSS[

60]

AM30

VSS[

84]

AM27

VSS[

83]

U25

VSS[

100]

P10

VSS[

99]

AM16

VSS[

81]

AD4

VSS[

31]

AK7

VSS[

80]

AK50

VSS[

79]

AK47

VSS[

78]

AK45

VSS[

C C

B B

D

GN

AK44 AK40

AK38 AK32 AK27 AK25 AM24 AK16

AJ53 AJ51

AJ25 AJ16

AH47 AH42 AH41 AH14 AH13 AH12 AH10 AG25

AF47

AK4

AJ3

AJ1

AH9

77]

VSS[

76]

VSS[

75]

VSS[

74]

VSS[

73]

VSS[

72]

VSS[

71]

VSS[

70]

VSS[

82]

VSS[

69]

VSS[

68]

VSS[

67]

VSS[

66]

VSS[

65]

VSS[

64]

VSS[

63]

VSS[

62]

VSS[

61]

VSS[

59]

VSS[

58]

VSS[

57]

VSS[

56]

VSS[

55]

VSS[

54]

VSS[

53]

VSS[

52]

VLV_M_D/BGA

V = 1.15

RE

9 OF 12

VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[

VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[

AF38

51]

AF32

50]

AF25

49]

AF10

48]

AE9

47]

AE8

46]

AE6

45]

AE53

44]

AE50

43]

AE48

42]

AE46

41]

AE45

40]

AE43

39]

AE42

38]

AE40

37]

AE14

36]

AE12

35]

AE11

34]

AE1

33]

AD44

32]

AD36

30]

AC29

23]

AD32

29]

AD30

28]

AD21

27]

AC38

26]

AC35

25]

AC33

24]

AC16

22]

AB6

21]

AB50

20]

AB47

19]

AB42

18]

AB4

17]

AB14

16]

AB13

15]

AB12

14]

AB10

13]

AA53

12]

AA38

11]

AA27

10]

AA16

9]

A47

8]

A43

7]

A39

6]

A31

5]

A23

4]

A19

3]

A15

2]

A11

1]

D

GN

4

U23J

AN21

VSS[

5]

BG30

VSS[

101]

BG27

VSS[

100]

BG24

VSS[

99]

BG20

VSS[

98]

BG19

VSS[

97]

BG18

VSS[

96]

BG16

VSS[

95]

BG14

VSS[

94]

BF42

VSS[

93]

BF32

VSS[

92]

BF28

VSS[

91]

BF27

VSS[

90]

BF26

VSS[

89]

BF22

VSS[

88]

BF12

VSS[

87]

BE35

VSS[

86]

BE19

VSS[

85]

C20

VSS[

103]

BD53

VSS[

84]

BG7

VSS[

102]

BD35

VSS[

83]

BD27

VSS[

82]

BD19

VSS[

81]

BD1

VSS[

80]

BC44

VSS[

79]

BC40

VSS[

78]

BC38

VSS[

77]

BC28

VSS[

76]

BC26

VSS[

75]

BC16

VSS[

74]

BC14

VSS[

73]

BC10

VSS[

72]

BB35

VSS[

71]

BB27

VSS[

70]

BB19

VSS[

69]

BA35

VSS[

68]

BA30

VSS[

67]

BA27

VSS[

66]

BA24

VSS[

65]

BA19

VSS[

64]

B36

VSS[

63]

B28

VSS[

62]

AY7

VSS[

60]

AY51

VSS[

59]

AY47

VSS[

58]

AY34

VSS[

56]

AY32

VSS[

55]

AY30

VSS[

54]

AY3

VSS[

53]

AN30

VSS[

6]

AY45

VSS[

57]

10 OF 12

VLV_M_D/BGA

V = 1.15

RE

D

VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[

VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[

VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[

VSS[ VSS[ VSS[

VSS[

VSS[ VSS[ VSS[

AY9

61]

AY28

52]

AY26

51]

AY24

50]

AY22

49]

AY20

48]

AW35

47]

AW27

46]

AW19

45]

AM13

4]

AK29

3]

AK22

2]

AV40

44]

AV35

43]

AV30

42]

AV27

41]

AV24

40]

AV19

39]

AV14

38]

AJ18

1]

AU53

37]

AU51

36]

AU3

35]

AU1

34]

AT9

33]

AT51

32]

AT45

31]

AT36

30]

AT35

29]

AT3

28]

AT27

27]

AT19

26]

AT18

25]

AP9

24]

AP50

23]

AP45

22]

AP4

21]

AN9

20]

AN8

19]

AN6

18]

AN53

17]

AN51

16]

AN5

15]

AN49

14]

AN48

13]

AN46

12]

AN45

11]

AN43

10]

AN42

9]

AN40

8]

AN38

7]

D

GN

3

U23K

AN33

VSS[

2]

P32

VSS[

99]

P27

VSS[

98]

P22

VSS[

97]

P19

VSS[

96]

AF24

VSS[

1]

N53

VSS[

95]

N51

VSS[

94]

N32

VSS[

93]

N24

VSS[

92]

N22

VSS[

91]

M9

VSS[

90]

K45

VSS[

77]

M40

VSS[

87]

M35

VSS[

86]

M27

VSS[

85]

AW13

VSS[

3]

M19

VSS[

84]

M14

VSS[

83]

L35

VSS[

82]

L27

VSS[

81]

L19

VSS[

80]

L1

VSS[

79]

K50

VSS[

78]

T47

VSS[

100]

K4

VSS[

76]

K36

VSS[

75]

K34

VSS[

74]

K32

VSS[

73]

K30

VSS[

72]

K24

VSS[

71]

K22

VSS[

70]

K16

VSS[

69]

K14

VSS[

68]

K12

VSS[

67]

J53

VSS[

66]

M45

VSS[

88]

J38

VSS[

64]

J35

VSS[

63]

J30

VSS[

62]

J27

VSS[

61]

J22

VSS[

60]

J19

VSS[

59]

J18

VSS[

58]

H8

VSS[

57]

E46

VSS[

40]

H35

VSS[

56]

H27

VSS[

55]

H19

VSS[

54]

M50

VSS[

89]

V25

VSS[

101]

OF 12

11

VLV_M_D/BGA

REV = 1.15

D

GN

VSS[

VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[

VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[ VSS[

VSS[

VSS[ VSS[ VSS[ VSS[ VSS[

Y24

102]

G30

53]

G28

52]

G26

51]

G22

50]

G14

49]

G12

48]

F5

47]

F35

46]

F32

45]

F27

44]

F24

43]

F19

42]

E51

41]

E35

39]

E19

38]

D42

37]

D40

36]

D38

35]

D32

34]

D27

33]

D24

32]

D16

31]

D10

30]

J42

65]

C47

29]

C39

28]

C36

27]

C30

26]

C3

25]

C28

24]

C22

23]

AW41

4]

BJ7

22]

BJ47

21]

BJ43

20]

BJ39

19]

BJ35

18]

BJ31

17]

BJ27

16]

BJ23

15]

BJ19

14]

BJ15

13]

BJ11

12]

BG5

11]

BG49

10]

BG40

9]

BG38

8]

BG36

7]

BG35

6]

BG34

5]

D

GN

2

U23L

F1

VSS

C1

VSS

BH

53

VSS

BH

52

VSS

BH

2

VSS

BH

1

VSS

BG

53

VSS

BG

1

VSS

B5

2

VSS

B2

VSS

A6

VSS

A5

VSS

M2

4

VSSA

A7

VSS

BF

50

VSS

BF

4

VSS

BB5

0

VSS

BB4

VSS

BG

47

VSS

Y9

VSS

Y5

0

VSS

Y4

5

VSS

Y4

0

VSS

Y4

VSS

Y3

8

VSS

Y2

9

VSS

Y2

2

VSS

Y2

1

VSS

Y1

9

VSS

Y1

6

VSS

Y1

4

VSS

Y1

0

VSS

P4

VSS

L41

VSS

P3

6

VSS

OF 12

12

VLV_M_D/BGA

REV = 1.15

D

GN

W1

VSS

V4

4

VSS

V4

2

VSS

V4

1

VSS

V3

8

VSS

V3

2

VSS

V2

1

VSS

V1

6

VSS

U9

VSS

U8

VSS

U6

VSS

U5

3

VSS

U5

VSS

U4

9

VSS

U4

8

VSS

U4

6

VSS

U4

5

VSS

U4

3

VSS

U4

2

VSS

U4

0

VSS

U3

8

VSS

U3

3

VSS

U3

2

VSS

U3

0

VSS

U2

9

VSS

U2

1

VSS

U1

8

VSS

U3

6

VSS

U1

4

VSS

U1

2

VSS

U1

1

VSS

T9

VSS

P4

2

VSS

T1

4

VSS

R1

VSS

P3

5

VSS

D

GN

1

A A

anta Computer Inc.

Qu

PROJECT :

Si

Size Document Number Rev

ze Document Number Rev

We

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

5

4

3

2

dnesday, April 08, 2015

PROJECT :

Valley 9/9 (GND)

Z8AD

3A

of

3210

of

3210

of

1

3210

5

M_

A_A[15:0][2]

+1

.35VSUS[2,3,9 ,27] V

+3

DDQ_VTT[27]

+V

D D

M_

A_BS#0[2] M_A_BS#1[2] M_

A_BS#2[2]

A_CS#0[2]

M_

A_CS#1[2]

M_ M_A_CLK0[2]

A_CLK0#[2]

M_ M_

A_CLK1[2]

A_CLK1#[2]

M_

A_CKE0[2]

M_

A_CKE1[2]

M_

A_CAS#[2]

M_ M_

A_RAS#[2]

A_WE#[2]

R5

44 10K_4

R5

45 10K_4

C C

B B

M_

B_RUN_CLK[7,20,21]

SM

B_RUN_DAT[7,20,21]

SM

M_

A_ODT0[2] A_ODT1[2]

M_

A_DM2[2] A_DM0[2]

M_

A_DM3[2]

M_ M_

A_DM1[2]

M_

A_DM4[2]

M_

A_DM5[2] A_DM6[2]

M_

A_DM7[2]

M_

A_DQS[7:0][2]

M_

A_DQS#[7:0][2]

M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_

MM0_SA0

DI

MM0_SA1

DI SM SM

M_

A_DM2

M_

A_DM0

M_

A_DM3 A_DM1

M_

A_DM4

M_ M_

A_DM5

M_

A_DM6

M_

A_DM7

M_ M_A_DQS0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_

A_A0 A_A1 A_A2 A_A3 A_A4 A_A5 A_A6 A_A7 A_A8 A_A9 A_A10 A_A11 A_A12 A_A13 A_A14 A_A15

B_RUN_CLK B_RUN_DAT

A_DQS2

A_DQS3 A_DQS1 A_DQS4 A_DQS5 A_DQS6 A_DQS7 A_DQS#2 A_DQS#0 A_DQS#3 A_DQS#1 A_DQS#4 A_DQS#5 A_DQS#6 A_DQS#7

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78

109 108

79 114 121 101 103 102 104

73

74 115 110 113 197 201 202 200

116 120

11

28

46

63 136 153 170 187

12

29

47

64 137 154 171 188

10

27

45

62 135 152 169 186

4

IM6A

JD

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1

0/AP A11 A1

2/BC# A13 A1

4

5

A1

BA0 BA1 BA2

#

S0

#

S1

0

CK

0#

CK

1

CK CK

1# E0

CK CK

E1 S#

CA RA

S#

WE

# SA0 SA1 SC

L

SD

A

OD

T0 T1

OD

0

DM DM1

2

DM DM3

4

DM

2100 DDR3 SDRAM SO-DIMM

DM5 DM

6 DM7

PC

DQS0 DQ

S1 S2

DQ DQ

S3 S4

DQ DQ

S5 S6

DQ

S7

DQ

S#0

DQ

S#1

DQ

S#2

DQ

S#3

DQ DQ

S#4 S#5

DQ DQ

S#6 S#7

DQ

91-93469-174

DDR-78279-001-RVS-204P-smt

DGMK4000425

IC SOCKET D DR3 STD SO-DIMM (204P,H4.0)

5

0

DQ

7

DQ

1

15

2

DQ

17

DQ

3

4

DQ

6

DQ5

16

6

DQ

18

DQ7

21

8

DQ

23

DQ9

33

DQ

10

35

DQ11

22

DQ

12

24

DQ13

34

DQ

14

36

15

DQ

39

DQ

16

41

17

DQ

51

DQ

18

53

19

DQ

40

20

DQ

42

21

DQ

50

22

DQ

52

23

DQ

57

24

DQ

59

DQ

25

67

26

DQ

69

DQ

27

56

28

DQ

58

DQ

29

68

DQ

30

70

DQ

31

129

DQ

32

131

DQ

33

141

DQ

34

143

35

DQ

130

DQ

36

132

37

DQ

140

DQ

38

142

39

DQ

147

DQ40

149

41

DQ

157

DQ42

159

43

DQ

146

DQ44

148

DQ

45

158

DQ46

160

(204P)

DQ

47

163

DQ48

165

DQ

49

175

50

DQ

177

DQ

51

164

52

DQ

166

DQ

53

174

54

DQ

176

55

DQ

181

56

DQ

183

57

DQ

191

58

DQ

193

59

DQ

180

DQ

60

182

61

DQ

192

DQ

62

194

63

DQ

EZIW

A_DQ17

M_

A_DQ22

M_ M_

A_DQ18

M_

A_DQ20

M_

A_DQ19 A_DQ16

M_

A_DQ21

M_ M_

A_DQ23

M_

A_DQ0 A_DQ5

M_

A_DQ3

M_

A_DQ2

M_ M_

A_DQ4

M_

A_DQ1

M_

A_DQ7 A_DQ6

M_

A_DQ30

M_ M_

A_DQ28 M_A_DQ26 M_

A_DQ31

A_DQ25

M_

A_DQ27

M_ M_A_DQ24

A_DQ29

M_ M_

A_DQ11

A_DQ13

M_

A_DQ9

M_

A_DQ15

M_

A_DQ8

M_ M_

A_DQ12

A_DQ14

M_

A_DQ10

M_

A_DQ36

M_

A_DQ33

M_ M_

A_DQ35

A_DQ38

M_ M_

A_DQ37

A_DQ32

M_

A_DQ34

M_ M_

A_DQ39 M_

A_DQ45 M_

A_DQ44

A_DQ47

M_

A_DQ43

M_ M_

A_DQ40 M_

A_DQ41 M_

A_DQ46

A_DQ42

M_

A_DQ53

M_ M_A_DQ49 M_

A_DQ50 M_

A_DQ55

A_DQ48

M_

A_DQ52

M_

A_DQ51

M_ M_

A_DQ54 M_

A_DQ59

A_DQ56

M_ M_

A_DQ62

A_DQ60

M_ M_

A_DQ63 M_

A_DQ58 M_

A_DQ61

A_DQ57

M_

3

A_DQ[63:0]

M_

M_A_DQ[63:0] [2]

2

0

3

V

A_DRAMRST#[2]

1

M_

MDDR_VREF_DQ

+S

MDDR_VREF_DIMM

+S

+3

74 *short_6

R2

4

5

6

2

2.

48A

+3

V

R2

81 *10K_4

C2

72 *0.1U/16V_4

MDDR_VREF_DQ0

+S

+1

.35VSUS

JD

IM6B

75

VD

D1

76

D2

VD

81

VD

D3

82

D4

VD

87

VDD5

88

D6

VD

93

VDD7

94

D8

VD

99

VDD9

100

VD

D10

105

VDD11

106

VD

D12

111

VDD13

112

VD

D14

117

D15

VD

118

VD

D16

123

D17

VD

124

VD

D18

199

DSPD

VD

77

NC1

122

NC2

125

EST

NCT

198

T#

EVEN

30

RE

SET#

1

VR

EF_DQ

126

VR

EF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

0

VSS1

31

VSS11

32

VSS1

2

37

VSS13

38

VSS1

4

43

VSS15

91-93469-174

DDR-78279-001-RVS-204P-smt

DGMK4000425

IC SOCKET D DR3 STD SO-DIMM (204P,H4.0)

2100 DDR3 SDRAM SO-DIMM PC

VSS1

6 7

VSS1 VSS1

8 9

VSS1 VSS20

1

VSS2 VSS22

3

VSS2 VSS24 VSS2

5 VSS26 VSS2

7 VSS28 VSS2

9

0

VSS3 VSS3

1

2

VSS3 VSS3

3

4

VSS3

5

VSS3

6

VSS3

7

VSS3

8

VSS3

9

VSS3 VSS4

0

1

VSS4 VSS4

2

3

VSS4 VSS4

4 VSS4

5 VSS4

6 VSS4

7 VSS4

8 VSS4

9

0

VSS5 VSS5

1

2

VSS5

(204P)

T1

VT VTT2

GND GN

D

1

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

203 204

205 206

DDQ_VTT

+V

7

+1

0.1uF/10uF 4pcs on each side of connector

Place these Caps near So-Dimm0.

.35VSUS

+1

C2

89

+

*330u/2V_7343

Near SO-DIMM

A A

5

4

.35VSUS

+1

C3

C4

C3

C4

C3

C413 10U/6.3V_6

C4

C411 10U/6.3V_6

C3

C4

C3

86 0.1U/16V_4

07 0.1U/16V_4

06 0.1U/16V_4

83 0.1U/16V_4

87 0.1U/16V_4

85 0.1U/16V_4

05 0.1U/16V_4

84 0.1U/16V_4

08 10U/6.3V_6

79 10U/6.3V_6

12 10U/6.3V_6

81 10U/6.3V_6

80 10U/6.3V_6

82 10U/6.3V_6

3

DDQ_VTT

+V

+S

MDDR_VREF_DIMM

MDDR_VREF_DQ0

+S

+3

V

Follow CHK list

C2

58 1U/6.3V_4

C2

66 1U/6.3V_4

C2

55 1U/6.3V_4

C2

68 1U/6.3V_4

C2

64 10U/6.3V_6

C409 0.1U/16V_4

C410 *2.2U/6.3V_6

54 0.1U/16V_4

C2

59 *2.2U/6.3V_6

C2

C3

88 0.1U/16V_4

C3

78 0.1U/16V_4

+VDDQ[27]

2

R5

R555 *0_6

.35VSUS

VR

EF DQ0 M1 Solution

56

R5

4.7K_4

57 *0_6

+1.35VSUS

R5

54

4.7K_4

MDDR_VREF_DIMM_L

+S

R5

52

4.7K_4

Si

ze Document Number Rev

Si

Date: Sheet

+SMDDR_VREF_DQ

R5

58

4.7K_4

R553 *short_6

dnesday, April 08, 2015

We

+S

Quanta Computer Inc.

PROJECT :

DDR3

DIMM0-STD(4.0H)

1

MDDR_VREF_DIMM

Z8AD

of

1A

3211

5

N/Card reader (LAN)

TP43

C219 *10P/50V_4

D2 LE

RE

ENSWREG

IS

OLATEBPIN PER

CL

KREQBPIN

MS

_BS/SD_WP#

FCLK_N RE

EVDD10

IOAC_LA NPW R#[22]

PCIE_LAN_WAKE#_R

TP40

TP42

36

G_OUT

35

VD

DREG

34 33

D1

VD

32

VD

33

31 30

STBPIN

29 28 27

33_18

DV

26

ON

HS

25

HS

OP

mils (Iout=1A)

40

R241 *short_8

C220

0.1U/16V_4

LAN_XTALI

25MHZ

VDD10

VDD33

SP1[21] SP2[21] SP3[21] SP4[21] SP5[21] SP6[21]

Y8

+3V3_SD_SW

C22510p/50V_4

1

2

4

3

LAN_XTAL2

C22410p/50V_4

R543 2.49K_4

U13

49

E_

PAD

1

MDI_0+ MDI_0-

MDI_1+ MDI_1MDI_2+ MDI_2-

MDI_3+ MDI_3-

For Surge improvement C5117\C5111 close to pin 11,23.

5

C239

*4.7U/6.3V_6

IP0

MD

2

MD

IN0

3

AVDD10

4

IP1

MD

5

MD

IN1

6

MD

IP2

7

IN2

MD

8

AVD

D10

9

MD

IP3

10

IN3

MD

11

_GIGA

HV

12

VD

D3

RSET

10

mils

C226

*4.7U/6.3V_6

C218 *10P/50V_4

SP8 [21]

TP41

TP44

48

47

45

44

43

42

41

40

39

38

46

ET RS

_GIGA HV

_D1

RD_3V3 CA

SD

13

14

15

40

37

D0 LE

_CD#

_CEN

D_CR

XTAL2

XTAL1

D1/GPO

LV

SD

LE

MS

NWAKEB

CK

LE

LA

N48

QF

_D0/MS_D1

_CLK/MS_D0

_CMD/MS_D2

_D3/MS_D3

_D2/MS_CLK

DTX

IP

IN

FCLK_P

SD

VD

HS

RE

16

17

18

19

20

21

22

23

24

Place 0.1uF CAP close to pin-- 24 * Place 1uF CAP close to each VDD10 pin-- 22 (reserve)

*

REGOUT

mils (Iout=1A)

D D

C C

VDD33

B B

VDDREG

40 mils

C227

C228

4.7U/6.3V_6

0.1U/16V_4

ace connect to Pin35

Pl

VDD33

40 mils (Iout=1A)

A A

*

Place 0.1uF CAP close to each

VDD33 pin-- 11, 32

C240

0.1U/16V_4

C229

0.1U/16V_4

(1.5A) 60 mils

REGOUT

ENSWREG

ISOLATEB

PCIE_REQ_LAN#_R

VDD33/18

GPP_TX3N_LAN GPP_TX3P_LAN

4

+3V_S5

+3VPCU

R534

AC@100K_4

R535 AC@20K_4

12/17 modify

R244 *short_4

R245 *SHORT_4

C241 0.1U/16V_4 C242 0.1U/16V_4

CLK_PCIE_LANN [6] CLK_PCIE_LANP [6]

PCIE_TXN3_LAN [5] PCIE_TXP3_LAN [5]

10

mils

VDD33/18

* Place 0.1uF CAP close to each VDD10 pin-- 3, 8, 22, 30

C230

0.1U/16V_4

4

R235 *NAC@0_8

Q22

1

C374

AC@1u/6.3V_4

VDDREG

VDD10 VDD33

SP7 [21]

PCIE_RXN3_LAN [5] PCIE_RXP3_LAN [5]

C237

*4.7u/6.3V_6

Place close to pin 27

C233

0.1U/16V_4

3

2

AC@AO3413

C236

0.1U/16V_4

40 mils (Iout=1A)

R233 *short_8

R234 *short_8

+3V

C231

0.1U/16V_4

50

R248 1K_4

R247 15K_4

R250 *AC@0_4

R249 0_4

VDD10

R255

C223

0.1U/16V_4

40 mils

mils

*SHORT_6

VDD33

VDDREG

IOAC_RS T# [19,20 ,22]

PLTRST# [14,15,19,20,21,22]

EVDD10

30

C243

1U/6.3V_4

ose to Pin20

Cl

VDD10

C235 1U/6.3V_4

3

mils

C232

0.1U/16V_4

3

C244

0.1U/16V_4

ansformer (LAN)

Tr

RJ

45 Connector

WAKE_SRC_1[14,19]

LAN_WAKE#[22]

2

1/12 change footprint

U17

24

C88

0.01U/50V_4X

MDI_0+

MDI_0-

MDI_1+

MDI_1-

MDI_2+

MDI_2-

MDI_3+

MDI_3-

1

2

3

4

5

6

7

8

9

10

11

12

TC

T0

0+

TD

0-

TC

T1

TD

1+

TD

1-

T2

TC

TD

2+

TD

2-

TC

T3

TD

3+

3-

TD

GST5009BLF

LAN_MCT0

T0

MC

23

LAN_MX0+

0+

TX

22

LAN_MX0-

0-

TX

21

LAN_MCT1

T1

MC

20

TX

MCT2

TX

MC

TX

D

GN

25

LGND

LAN_MX1+

1+

19

LAN_MX1-

1-

TX

18

LAN_MCT2

17

LAN_MX2+

2+

16

LAN_MX2-

2-

TX

15

LAN_MCT3

T3

14

LAN_MX3+

3+

13

LAN_MX3-

TX

3-

R52 75_1206

R77 75_1206

R90 75_1206

R104 75_1206

2nd source: DBU83ULAN00

CN12

1

LAN_MX0+

2

LAN_MX0-

3

LAN_MX1+

4

LAN_MX2+

5

LAN_MX2-

6

LAN_MX1-

7

LAN_MX3+

8

LAN_MX3-

PCIE_CLKREQ3_LAN#[5]

R537 0_4

R538 *0_4

1

Q28 PJA138K

VDD33

R542 0_4

2

C100JH-10805-L

+1.8V

2

R540 1K_4

2

Q50

13

*DTC144EUA

9 10

LGND LGND

+3V

R254 10K_4

3

PCIE_REQ_LAN#_R

PCIE_LAN_WAKE#_R

C125 *0.01U/5 0V_4

C124 *0.1U/16 V_4

R147 *short_8

EM

Size Document Number Rev

Date: Sheet of

1

Layout:All termination signal should have 30 mil trace

LANCT3

R434 1M_8

I

MDI_0+

MDI_0-

MDI_1+

MDI_2+

MDI_2-

MDI_1-

MDI_3+

MDI_3-

Qu

PROJECT :

LA

N (RTL8111GS)

Wednesday, April 08, 2015

1

+3V_S5[2,3,5,9,14,15,16,22,26] +3V[4,7,9,11,13,14,15,16,18,19,21,22,25,27,28,29,30]

C352 1000P/3KV_1808

LGND

C44 *6.8P/50V_4

C46 *6.8P/50V_4

C56 *6.8P/50V_4

C64 *6.8P/50V_4

C75 *6.8P/50V_4

C58 *6.8P/50V_4

C95 *6.8P/50V_4

C100 *6.8P/50V_4

anta Computer Inc.

Z8AD

3212

1A

5

D POWER SWITCH

LC

1U

/6.3V_4C198

+3

V

PCH_DISP_ON[4]

D D

Touc

h screen level shift I2C(reserve)

R3

C C

I2

C1_SDA_GPIO6[7]

I2

C1_SCL_GPIO7[7]

42 *TSI@0_4

*PJ4N3KDW

1

4 3

Q3

9

R3

6

4

3

R8

00K_4

*1

6

2

5

44 *TSI@0_4

U6

IN

/OFF

ON

243AT11U

G5

I2

C1_SDA_GPIO6_CONN

+1.8V

I2

C1_SCL_GPIO7_CONN

R3

31

*TSI@10K_4

OU

GN

T

D

+3

V

R3 *TSI@10K_4

1

2

5

V

30

4

80 mile trace

ME2N7002DS-G_300MA

2

C3

0.1U/16V_4

R3

37*TPS@10K_4

Q8

+LCDVCC_R

TP_RST#

+1.8V_S5

R2

10K_4

3

1

D

GN

5

2

3

C3

0.01U/25V_4

GN

DDI

1_EDP_HPD_R [4]

ULT_EDP_HPD

0

R1

100K/F_4

D

R1

5 *short_8

5

C3

22U/6.3V_8

C6 180P/50V_4

D

GN

+L

CDVCC

R2

R21 *100K_4

V

+3

Refer to intel CRB

3/2 add

98

3

0 *100K_4

IN

T_eDP_AUXP[4]

IN

T_eDP_AUXN[4]

IN

T_eDP_TXP1[4]

INT_eDP_TXN1[4]

T_eDP_TXP0[4]

IN IN

T_eDP_TXN0[4]

P_AUXP

ED

EDP_AUXN

3/2 add

GN

D

GND

PWR

CCD_

INT_eDP_AUXN

T_eDP_TXP1

IN IN

T_eDP_TXN1

IN

T_eDP_TXP0

CAMERA

uchPanel

To

C6

99 *10p/50V_4

00 180P/50V_4

C7

C3

14

*10p/50V_4

C3

23

1000P/50V_4

CDVCC

+L

+5 +3

C3

17 0.1U/16V_4

C318 0.1U/16V_4

19 0.1U/16V_4

C3

20 0.1U/16V_4

C3

21 0.1U/16V_4

C3

22 0.1U/16V_4

US

BP3+[7]

USBP3-[7]

BP2+[7]

US

BP2-[7]

US

TS_EN[22]

TP_INT[14]

_RST#[14]

TP

GP

IO8[6]

Touch screen SEL.

TS_EN

GP

IO8

2

V_

BLIGHT

+V

IN

+3V

V V

eDP_AUXPINT_eDP_AUXP eDP_AUXN

eD eD

eD eDP_TXN0INT_eDP_TXN0

US US

C3

26 *4.7U/25V_8

C325 0.1U/50V_6

16 0.01U/25V_4

C3

36 *short_8

R3

25 *short_8

R3

35

R3

PC

H_DPST_PWM[4]

BLON_CON[21]

P_TXP1 P_TXN1

P_TXP0

BP3+

US US

BP3-

BP2+ BP2-

Touch screen (I2C)

19 *33_4

R8

R818 33_4

*SHORT_6

R9

0_6

R6

*0_4

UL

T_EDP_HPD

R326 *short_4

27 *short_4

R3

28 *short_4

R3

29 *short_4

GPIO8_R

+1.8V_S5

MA

X 1.5A

CCD_

TP

_PWR

H_DPST_PWM

PC BL

ON_CON

R8

20 33_4

BP3+_R

US US

BP3-_R

US

BP2+_R

US

BP2-_R

C1_SCL_GPIO7_CONN

I2

C1_SDA_GPIO6_CONN

I2 TS

_EN_R

TP

_INT

TP

_RST#

32 *10K_4

R3

V_

PWR

BLIGHT

1

CN8

5 G_

40 39 38 37 36 35 34 33 32

G_

31

4 30 29 28 27

ED

P_HPD

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

1

G_

0 G_

7300L40-100000-G4

HDMI Conn.

HDMI SMBus Isolation

R5

12/29 add

B B

SD

VO_CLK[4]

SDVO_DATA[4]

12/29 add

I-detect (HDM)

HDM

A A

HDM

I_HPD_CON[4]

+1

.8V_S5

+1

.8V

76 2.2K_4

R455 *2.2K_4

4 3

VO_CLK

SD

1

SD

VO_DATA

54 *2.2K_4

R4 R577 2.2K_4

HDMI_HPD_CON

8

Q1

ME2N7002DS-G_300MA

5

Q4

PJ4N3KDW

7

+1

.8V_S5

3

1

R164 10K_4

+1.8V

5

I_SCLK

HDM

2

6

HDM

I_SDATA

2

HDMI_HPD

R168 100K_4

4

EMI (EMC)

TX0_HDMI+

C_

85 *100_4

R4

C_TX1_HDMI+

17 *100_4

R5

C_TX2_HDMI+

R5

29 *100_4

C_TXC_HDMI+

R505 *100_4

V

+3

87 *100K_4

R1

C36 0.1U/16V_4

2

C_

TX0_HDMI-

TX1_HDMI-

C_

TX2_HDMI-

C_

TXC_HDMI-

3

1

DG

PU_CL_HDMIP

Q21

ME2N7002DS-G_300MA

R2

04 470_4

1 2 1 2

R1

90 470_4

1 2

88 470_4

R1

1 2

82 470_4

R1

1 2

R1

72 470_4

R1

70 470_4

1 2

R1

77 470_4

1 2

75 470_4

R1

3

IN_D2[4]

_D2#[4]

IN

_D1[4]

IN

_D1#[4]

IN

_D0[4]

IN

_D0#[4]

IN

_CLK[4]

IN

_CLK#[4]

C_ C_

C_ C_TX1_HDMI-

C_ C_

C_ C_TXC_HDMI-

IN IN IN_D1 IN_D1# IN IN

IN_CLK C_TXC_HDMI+ IN_CLK#

+5

V

+5V

TX2_HDMI+ TX2_HDMI-

TX1_HDMI+

TX0_HDMI+ TX0_HDMI-

TXC_HDMI+

_D2 _D2#

_D0 _D0#

C3

72 0.1U/16V_4

C3

70 0.1U/16V_4

C3

69 0.1U/16V_4 C368 0.1U/16V_4 C362 0.1U/16V_4

61 0.1U/16V_4

C3

66 0.1U/16V_4 C365 0.1U/16V_4

2 1

D2

6 RB500V-40

2 1

7 RB500V-40

D2

Q4

8

3

OU

IN

GN

AP2331SA-7

C_

TX2_HDMI+

C_

TX2_HDMIC_TX1_HDMI+ C_TX1_HDMI-

TX0_HDMI+

C_

TX0_HDMI-

C_

C_TXC_HDMI-

R4

60 2.2K_4

_HSMBCK

5V

_HSMBDT

60

C3 *220p/50V_4

74 2.2K_4

R4

59 *10P/50V_4

C3 C355 *10P/50V_4

12

D2

8

*5V/30V/0.23 p_4

12

VC

6

*5V/30V/0.23 p_4

Si

Size Document Nu mber Rev

ze Document Nu mber Rev

Date: Sheet

5V

1

T

2

D

2

I_SCLK

HDM

I_SDATA

HDM

I_5V

HDMI_HPD

C1

66

220P/50V_4

D/HDMI/Camera

LC

Wednesday, April 08, 2015

CN14

1

D2

+

3

D2

-

4

+

D1

6

D1-

7

+

D0

9

-

D0

10

CK

+

12

CK

-

15

CLK

DDC

16

DATA

DDC

18

V

+5

19

HP

DET

C128B7-K1907-L

Qu

anta Computer Inc.

PROJECT :

1

D2 D1 D0 CK

CE

Z8AD

SH

ELL1

SH

ELL2

SH

ELL3 ELL4

SH

Shield Shield Shield Shield

GN

Remote

20 21 22 23

2 5 8 11 17

D

13 14

NC

1A

of

3213

of

3213

of

3213

5

+1

.8V_S5

27

C_PWRBTN#[6]

.8V_S5

PC

C_KCB_SMI[5]

C_KBC_SCI[5]

SPWRDANCK[6]

+3

3

1

GN

H_SUS_S TAT#

R4

V

To

45

R3 *TPS@10K_4

D

5 10K_4

R4

*10K_4

.8V_S5

+1

2

1

1 *PJA138K

Q4

R3

1 *0_4

R7

4 *10K_4

7 10K_4

R5

uch Pa nel inter rupt

3

2

*TPS@PJA138K

1

Q54

GN

D

3

+3

V_S5

1

VC

CA

3

A

2

D

GN

*G2129TL1U

R3

54 *10K_4

H_SLP_S0 _N

PC

6 5 4

74LV

6 5 4

74LV

+1.8V_S5

1

0 *PJA138K

Q2

74 0_4

R1

_INT_C [6]

TP

Y1 VC

C2G07GW

Y1 VC

C2G07GW

D D

C_SERIRQ

SO

C_SERIRQ[7,15]

PC

H_SUS_S TAT#[6]

8 *0_4

R3

+1

.8V_S5

R3

5 0_4

V_S5

+3

C C

B B

_INT[13]

TP

SO

.8V_S5

+1

SO

+1

2

Q3

7

*TPS@PJA138K

C_PMC_WAKE[6]

SO

.8V_S5

SU

toTouch screen INT

4

.8V_S5[4,5,6,7,9,13,22,24,26,28,29]

+1

V_S5[2,3,5,9,12,15,16,22,26]

+3

.8V[9,12,13,15,16,19,20,21,22,26,30]

+1

V[4,7,9,11,12,13,15,16,18,19,21,22,25,27,28,29,30]

+3

R4

060_4

+3V_S5+1.8V_S5

U1

8

6

VC

CB

4

B

5

OE

V_S5

+3

PC

R4

07

*10K_4

H_SLP_S0 _N [2 2]

SER

+1

IRQ [ 22]

.8V_S5

Reserve for +1.8V new EC

U7

1

A1

2

GN

D

C

A23Y2

U9

1

A1

2

GN

D

C

A23Y2

2

3

GN

D

R4

1 *10K_4

D

GN

TP_RST#_Q[6]

DN

BSWON# [22]

KE_SRC_1 [12,19]

WA

V_S5

+3

O_EXT_SMI# [22]

SI

O_EXT_SCI# [22]

PC

H_SUSPW RDAN CK [2 2,26]

2

*PJA138K

Q4

5

+3

R3

60

*10K_4

2

3

*PJA138K

4

Q4

1

GND

3

EC

_PWROK[3,22]

WROK_EC[22]

DP

RS

MRST#[22]

U_RSMR ST#[26]

PM

SL

P_S3#[6,26]

SLP_S4#[2,6]

SL

P_S0IX#[6,26]

C_PLTRST#[6,21]

SO

V

R362 *10K_4

TP

3

1

_RST# [13]

D

GN

76 0.1U/25V_4

C2

C_0_SDA[7]

I2

C_0_SCL[7]

_INT#[6]

TP

+1

.8V_S5

2

57 0_4

R3

64 *0_4

63

R3

100K_4

GN

D

78 *0_4

R3

77 0_4

R3

R1

4 0_4

5

2

9 0_4

R1

R2

9 *0_4

Q7

1

.8V_S5

+1

1

+1

.8V

5

U1

1

GN

D

2

VR

EF1

4

A1

SD

3

SCL1

PCA9306

For Touch pad : POWER-A

TP

_INT#

3

ME2N7002DS-G_300MA

1

GN

34

Q6

A

*PJ4N3KDW

61

Q6

B

*PJ4N3KDW

2

A138K

PJ

VR

EF2

SD

SCL2

2

Q3

D

*PJA138K

Q9

EN

A2

1

3

8

7

5

6

R3

76

*100K_4

GN

D

R7

R1

8 *10K_4

1 *10K_4

R1

2 *10K_4

R1

R2

+T

PVDD_1

84

R2

200K_4

C2

3

2

Q3

2

ME2N7002DS-G_300MA

1

D

GN

*10K_4

SU

SUSC# [22]

R1

6 *10K_4

7 *0_4

2 10K_4

73 0.1U/25V_4

83 10K_4

R2

80 10K_4

_SENSOR_INT_R

TP

RE_PWROK [6]

CO

SO

C_RSMRST# [6]

10/30 add

D

GN

Reserve For EC GPIO input.

SB# [22,28,29]

V_S5

+3

10/30 add

GN

D

Reserve For EC GPIO input.

V_S5

+3

SL

P_SUS#_EC [ 22]

SL

P_SUS#_PW [ 27]

TRST# [ 12,15 ,19,2 0,21, 22]

PL

+3

V

D

GN

_SENSOR_INT_R [15]

TP

+T

R2

2.2K_4

PVDD_1

1

88

86

R2

2.2K_4

I2

C_6_SDA_R [15]

C_6_SCL_R [15]

I2

A A

anta Computer Inc.

Qu

Level Shfiter

dnesday, April 08, 2015

Qu

PROJECT :

1

Z8AD

1A

of

3214

of

3214

of

3214

3/2 Del

Size Document Number Rev

ze Document Number Rev

Si

We

Date: Sheet

5

4

3

2

Date: Sheet

5

YBOARD (KBC) TOUCH PAD (TPD)

KE

0

1 *100p/50V_4

MX

C3

1

0 *100p/50V_4

MX

C3

MX

2

9 *100p/50V_4

CN9

1

MY0

MY

2

MY

3

MY

4

MY

5

MY

6

MY

7

D D

27 28

50503-

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

0260N-001

MY MY MY8 MY MY MY MY MY MY MY MY MY MX MX MX MX MX MX MX MX

0 [22]

1

MY

1 [22]

2

MY

2 [22]

3

3 [22]

MY

4

4 [22]

MY

5

MY

5 [22]

6

MY

6 [22]

7

7 [22]

MY

8 [22]

MY

9

9 [22]

MY

10

10 [22]

MY

11

11 [22]

MY

12

12 [22]

MY

13

13 [22]

MY

14

14 [22]

MY

15

15 [22]

MY

16

16 [22]

MY

17

17 [22]

MY

7

7 [22]

MX

6

6 [22]

MX

5

5 [22]

MX

4

4 [22]

MX

3

3 [22]

MX

2

2 [22]

MX

1

1 [22]

MX

0

0 [22]

MX

MX3

4

MX

5

MX MX

6

MX

7

MY

0 MY1 MY

2 MY

3

MY

4 MY

5 MY

6 MY

7

MY

8 MY

9

MY

10

MY

11

MY

12

MY

13

14

MY MY

15

MY

16

MY

17

C2 C28 *100p/50V_4

7 *100p/50V_4

C2

6 *100p/50V_4

C2

5 *100p/50V_4

C2 C2

4 *100p/50V_4

C6

*100p/50V_4

C7 *100p/50V_4

*100p/50V_4

C8 C9

*100p/50V_4

C1

0 *100p/50V_4

C1

1 *100p/50V_4

C1

2 *100p/50V_4

C1

3 *100p/50V_4

C1

4 *100p/50V_4

C1

5 *100p/50V_4

C1

6 *100p/50V_4

C1

7 *100p/50V_4

C1

8 *100p/50V_4

C1

9 *100p/50V_4

C2

0 *100p/50V_4

C2

1 *100p/50V_4

C2

2 *100p/50V_4

C2

3 *100p/50V_4

4

IN

TERNAL KEYBOARD

STRIP SET (KBC)

VPCU

+3

RP

6

10

1 9 8 7 4

10KX8

R1

3 *10K_4

2

3

56

MX

4

MX

5

MX

6

MX

7

MY

0

3

2

1

POWER-A

51 0_6

C404

*0

.1u/16V_4

48 *short_4

R5

1

R5 *10K_4

R5

86

3

+TPVDD_1+3VPCU

R5

50 *0_4

*AO3413

Q5

2

03 *1000p/50V_4

C4

2

3

2

1

Q5

0.22u/25V_6

12N7002K

02

C4

TP

_SENSOR_INT_R

+

C398

0.

1U/16V_4

CLK[22]

TP

DATA[22]

TP

TP TP

R5

47

10K_4

C4

01

*10p/50V_4

I2 I2

_SENSOR_INT_R[14] _EN_EC[22]

C_6_SDA_R[14] C_6_SCL_R[14]

Touch pad I2C

L19 *SHORT_6

+3

V_S5

MX3 MX

2

MX

1

MX

0

+3

VPCU

_POWER_ON[22]

TP

_INT_EC#[22]

+T

PVDD_1

R5

10K_4

C4

*10p/50V_4

46

00

40mi

l

C397

0.

1U/16V_4

R5

88 33_4

99

C3 180P/50V_4

TP

_SENSOR_INT_C

R5

87 33_4

94

C5 180P/50V_4

TP

_EN_EC_C

+T

PVDD_1

CN2

1 2 3 4 5 6 789

50503-0080N-001

PVDD_1 [14]

0

10

Touch pad INT

C C

TP

M (TPM)

B B

+3

VPCU[6,8,9,12,16,18,19,21,22,24,25,26]

+5

V[13,16,18,25,30]

+3

V[4,7,9,11,12,13,14,16,18,19,21,22,25,27,28,29,30]

6

R4

*TPM_I@0_4

5

24

10

19

0

R1

44

TPM_N@10K_4

D3[7,19,20,22]

LA

D2[7,19,20,22]

LA

D1[7,19,20,22]

LA

D0[7,19,20,22]

LA

RAME#[7,19,20,22]

LF

CL

PL

TP

R1

M_SERIRQ

45 *short_4

R1

K_TPM[7]

KRUN#[7,22]

PLTRST#

TRST#[12,14,19,20,21,22]

42 *short_4

C9

8 *TPM@10p/50V_4

R1

43 *short_4

R405 *short_4

SER

PL

IRQ_R

TRST#_R

TP14

U1

17

D3

LA

20

D2/SPI_IRQ

LA

23

D1/MOSI

LA

26

D0/MISO

LA

22

LF

RAME/SCS

27

SER

21

LCLK/SCLK

15

KRUN/GPIO04

CL

16

LRESET/SPI_RST

28

CPD

LP

D3

D1

D2

VSB

VD

GP

IO0/XOR_OUT

IRQ

GP

IO3/BADD

D2

D1

D3

D4

GN

TPM_S@NPCT620/650_TSSOP28

4

11

18

25

AL000650K00 : NPCT650AA0WX AL009655K01 : SNI SLB9655TT1.2

X/GPIO2

GP

TEST

TP

M_VDD

7

C9

[email protected]/10V_4

R4

7

PP

IO1

NC1 NC2 NC3 NC4

R5

6

R5

2

TP

1

TP

9

R3

8

R4

3 12 13 14

9

C4

[email protected]/10V_4

9 *[email protected]_4 0 *[email protected]_4 1 *TPM_I@20K_4

11

pin9 : 9655󴣊󲋮 reset , 9660 and Nuvoton NC pin

10 95 *TPM_I@0_4 8 *TPM_N@10K_4

PL

TRST#

9

C9

[email protected]/10V_4

M_VSB

TP

M_VDD

TP

C4

[email protected]/10V_4

51

C3

[email protected]/10V_4

8

R4

50

C3

TPM@10U/6.3V_6

7 *short_4

R4

C4

7

TPM_N@10U/6.3V_6

22 [email protected]_6

+3

V

+3

V_S5

+1

C_SERIRQ

SO

C_SERIRQ[7,14]

SO

Touch pad ON/OFF

.8V

R4

28

*TPM_I@10K_4

GN

R4

41 *TPM_I@0_4

+1

.8V

VCCA1VCCB

3

A

2

GN

D

*TPM_I@G2129TL1U

20140303:NPCT650 TPM doesn't need SERIRQ.

+3

V

U1

9

6

4

B

5

OE

M_SERIRQ

TP

R447 *TP M_I@10K_4

+1

.8V

D3

LA

LAD2

A A

D1

LA

D0

LA

CL

K_TPM

14 *10p/50V_4

C1

C115 *10p/50V_4

16 *10p/50V_4

C1

17 *10p/50V_4

C1

23 *10p/50V_4

5

TPM_N for TPM_I for

󲓹󲓹󲓹󲓹 󱑙󱑙󱑙󱑙 󴈺󴈺󴈺󴈺󵠤󵠤󵠤󵠤󱄕󱄕󱄕󱄕

---- default

4

Qu

anta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet

3

2

Date: Sheet

KB/

BT/TP

PROJECT :

Z8AD

15

1

15

1A

of

32Wednesday, April 08, 2015

5

5" SATA HDD (HDD)

2.

CN

17

23

GN

D23

1

GN

D1

2

A_TXP0_R

RX

P

RX

N

D2

GN

D D

C C

N

TX

P

TX

D3

GN

3.

3V

3.

3V

3.

3V

D

GN

D

GN

D

GN

5V 5V 5V

GN

D

RS

VD

GN

D 12V 12V 12V

D24

GN

HD@C166FQ- 12208-L

CPU FA

V

+5

R3

EC

PWM SIGNAL

B B

CPU Thermal sensor(THS) / MB Local TEMP

A A

SAT

3

A_TXN0_R

SAT

4 5

A_RXN0_R

SAT

6

SAT

A_RXP0_R

7

8 9 10

VSLP0_R

DE

11 12 13 14 15 16 17 18 19 20 21

*HD@100u/6.3V_3528

22

24

N CTRL(THM)

50 *short_8

B1ALERT#[7]

SM

CP

UFAN#[22]

MB

CLK2[22]

DATA2[22]

MB

TP

39

30 *10K_4

R5

V

+3

+

C3

MB

AL

CLK2

DATA2

ERT#

75

HD

1 2

C3

2.2U/6.3V_6

46 *HD@0_4

R2

11

C2

HD@10U/6.3V_6

D_INTA_R

33

+5

V_HDD

C221

[email protected]/16V_4

*H

78 *short_4

R5

6

U1

2

N

VI

GN

1

ON

/F

GN GN

4

ET

VS

GN

G991P11U

FA

NPWR = 1.6 *VSET

5

U2

8

LK

VC

SC

7

A

DX

SD

6

DX

AL

ERT#

4

ERT#

GN

OV

*EMC1412-1-ACZL-TR

VO

D D D D

C

P

N

D

DE

120m

C222

[email protected]/16V_4

*H

3 5 6 7 8

1

2

3

5

96 [email protected]/25V_4

C3

94 [email protected]/25V_4

C3

92 [email protected]/25V_4

C3 C3

90 [email protected]/25V_4

VSLP0 [5]

il

C212

@0.01U/25V_4

HD

D_INTA [21]

FA

NSIG[22]

_FAN_POWE R

TH

C3

30

1 2

2.2U/6.3V_6

73 *0.01U/16V_4

C3

TH

ERMDA

TH

ERMDC

R5

36 *short_8

V

+3

DE

C3

32

0.01U/25V_4

VSLP0_R

30mils

TP

SAT SAT

C3

*0.01U_4

+3

A_TXP0 A_TXN0

A_RXN0 A_RXP0

37

38

24

V

+5

R5

49*HD@10K_4

*HD@PJA138K

+3

EMC1412-1-ACZL-TR(98h)Main:AL001412003

TMP431ADGKR(98h)2nd:AL000431014

V

3

V

R3

10K_4

SAT SAT

.8V

+1

2

Q5

24

10

CN

1 2 3

50273-0030L-001

4

A_TXP0 [5] A_TXN0 [5]

A_RXN0 [5] A_RXP0 [5]

1

DE

3

VSLP0

SATA ODD Connector

11

CN

14

GN

D14

1

D1

GN

2

P

RX

3

N

RX

4

D2

GN

5

TX

N

6

TX

P

7

SSD

D3

8

DP

9

V

+5

10

V

+5

11

VD

12

GN

D

13

GN

D

15

D15

FANSIGCPUFAN#

13

C3

*220P/50V_6

For

EMI

GN

RS

GN

C185Q2-11309-L

15

C3

*220P/50V_6

SAT

A_TXP1_C

SAT

A_TXN1_C

SAT

A_RXN1_C

SATA_RXP1_C

_ID

A_DP

SAT

C312

0.

EC

_ODD_EJ

R3

SSD

_ID [5]

R3

52 *1K_4

C329

01U/25V_4

0.

R8

15 33_4

49 10K_4

D Power (SATA)

OD

D_POWER[22]

OD

H_ODD_ EN[6]

PC

12 *33_4

R8

C328

*0

+3

V

3

.1u/16V_4

C6

C311

.1u/16V_4

*0

_ODD_EJ# [22]

EC

EC_ODD_EJ#

D_PRSNT#

OD

R3

58 *0_4

59 *0_4

R3

C3

45 0.01U/25V_4

C3

39 0.01U/25V_4

C3

37 0.01U/25V_4 35 0.01U/25V_4

C3

93 *33P/50V_4

+5

10

C3

10U/6.3V_6

OD

D_EN

12

V_ODD

+

31

C3

*100u/6.3V_3528

96 180P/50V_4

C6

97 *10p/50V_4

C6

R3

53

*100K

R3 *100K

SAT SAT

VPCU

+3

34

A_TXP1 [5] A_TXN1 [5]

A_RXN1 [5] A_RXP1 [5]

D_PRSNT# [5]

OD

3/2 add

12

D_EN_Q

OD

2

+1

6

154 3

*2N7002DW

VPCU

+3

V_S5

2

LED/SW

Battery

LE

Blue

2

1

19-123-S2BHC-A30-2T

Amber

R indicator

PW

(UIF)

indicator

3 *5.5V/25V/410P_4

D2

D7

3

4

2 *5.5V/25V/410P_4

D2

Blue

LE

2

1

19-123-S2BHC-A30-2T

1 2

D6

R3

3

4

15 680_4

14 909_4

1 2

D2

1 *5.5V/25V/410P_4

13 680_4

R3

12 909_4

R3

1 2

D2

0 *5.5V/25V/410P_4

BAT

LED0# [22]

LED1# [22]

PW

RLED# [22]

SU

S_LED# [22]

1

Amber

R button DB CON

PW

D#

LI

SWON#

NB

Q3

5V

6

V

*AO6402A

+5

6 524

1

R3

48

MO

3

12

*100K

Q4

D_EN_5V

12

27

C3 *0.1u/25V_6

0

OD

D_EN_Q

+5

2

4

Q3

*DMN601K-7

V_ODD

3

1

R3 *22_8

R3

43 0_8

22

V

+5

SWON#[22]

CN

12

*SATA_CONN

01 180P/50V_4

C7

02 180P/50V_4

+3

VPCU

09

C3

*0.1u/16V_4

CN

7

1

LID

16 33_4

R8

LI

D#[21,22]

18

1 2 3 4 5 6 7 8 91011

17 33_4

R8

A_TXP0_CN

SAT

A_TXN0_CN

SAT

A_RXN0_CN

SAT

A_RXP0_CN

DE

VSLP0_R

+5V_HDD

C3 C3

SWON

NB

50503-0040N-V01

95 *0.01u/16V_4 93 *0.01u/16V_4

91 *0.01u/16V_4 89 *0.01u/16V_4

2 3

5

4 6

A_TXP0

SAT

A_TXN0

SAT

A_RXN0

SAT

A_RXP0

anta Computer Inc.

Qu

PROJECT :

ze Document Number Rev

Si

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

Hall/eMMC/LED

HDD/

1

Z8AD

16

1A

32Wednesday, April 08, 2015

5

4

3

2

1

USB 3.0 Connector

D D

BP0-[7]

US

From APU

C C

USB 2.0 Connector

B B

BP0+[7]

US

B30_TX0-[7] B30_TX0+[7]

US

B30_RX0-[7]

US

B30_RX0+[7]

US

34

C2

*1.6P/50V_4

+5

V_S5

BON#[22]

US

SO

C_USB_OC0[7]

US US

77 0.1U/16V_4

C3 C3

76 0.1U/16V_4

US US

38

C2

*1.6P/50V_4

USBON#

B30_RX0B30_RX0+

C2

09

4.7U/10V_6

B30_TX0-_C

US US

B30_TX0+_C

5V

USB_0

C2

15

470P/50V_4

42 *short_4

R2 R243 *short_4

53 *short_4

R2 R2

51 *short_4

41 *short_4

R5 R5

39 *short_4

4/7 Del

47E2P81U: Enable: Low Active /2.5A

G5

U1

2

5

IN

4

EN

AP22802BW5-7

OU

T

GN

D

/O

C

2A

1

2

3

From HUB

77 *short_4

R2

BP1-_CN

BP1-[7]

US US

A A

BP1+[7]

5

78 *short_4

R2

US

BP1+_CN

US

4/7 Del

4

US USBP0+_R

US US

5V

USB_0

ose USB3.0

Cl

C2

16

0.1U/16V_4

BP0-_R

B30_RX0-_R B30_RX0+_R

B30_TX0-_R B30_TX0+_R

3

VC

C2

17

100U/6.3V_1206

7

*TVM0G5R5M261R_4

8

VC

*TVM0G5R5M261R_4

USB2.0 connector P/N: DFHS04FR487

CN16

1

S

VBU

1

2

D-

2

3

D+

3

4

GND

5

SSRX-

5

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

9

111110

131312

10

12

C19083-90905-L

49

C2

100U/6.3V_1206

BP1-_CN

US

BP1+_CN

US

12

D16 5V/30V/0.23p_4

2

2/25 add

5V

USB_0

U2

8

1

B30_TX0-_R

US

99

C5 *0.1u/16V_4

US

BP0-_R

US

B30_RX0-_R

53

C2

0.1U/16V_4

12

D15 5V/30V/0.23p_4

ze Document Num ber Rev

Si

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

We

I/O

1

I/O

2

3

4

5

USB30_ESD_AZ1065-06F.R7 G

EP1 EP2

US

B / eMMC CONN

6

D

VD

GN

D_2

1

NC_

2

NC_

2

I/O

5

3

I/O

D_1

I/O

4

GN

11

9

CN1

1

VD

D

2

D-

3

D+

4

D4

GN

C14783-10409-L

anta Computer Inc.

Qu

PROJECT :

10

US

9

8

7

US

6

US

GN GN GN GN

1

B30_TX0+_R

BP0+_R

B30_RX0+_R

EP3 EP4

5

D5

6

D6

7

D7

8

D8

Z8AD

of

1A

3217

5

Co

dec(ADO)

+5

V[13,16,25,30]

D D

placed close to codec

C2

81

1U/10V_4

Place close to codec

+1

.5VA

C2

75

C2

74

+5

VAA

C2

63

10u/6.3V_4

0.1U/16V_4

C2

62

0.1U/16V_4

near Codec

70

C2

10u/6.3V_4

near Codec

Low is power down amplifier output

R2

61 *SHORT_6

V

+3

AD

C2

0.1U/16V_4

OGND

C2

84 10U/6.3V_4

69

PK+

L_S

PK-

R_

SPK-

SPK+

R_

PD

#

57

C2

0.1U/16V_4

10U/6.3V_4

AD

OGND

Place next to pin 40

Analog

Digital

C C

+5

VAA

V

+3

37

38

39

40

41

42

43

44

45

46

47

48

49

+A

ZA_VDD

51

C2

10U/6.3V_6

CB

AVSS2

LD

AVD

PVD

SPK-

PVDD2

PD

SPD

DG

P

O2-CAP

D2

D1

L+

L-

R-

R+

B

IFO/GPIO2

ND

8210U/6.3V_4 C2

36

VDD CP

DD DV

1

Place next to pin 1

R302 *SHORT_4 R2

70 *SHORT_4

R2

76 *SHORT_4 87 *SHORT_4

R2

ADOGND

R269 *SHORT_4 R3

01 *SHORT_4 85 *SHORT_4

R2 R2

79 *SHORT_4

79 *1000p/50V_4

C2

03 *1000p/50V_4

C3

+5

V

1U/6.3V_4

C2

61

L10

B1608KF-60 1T20(600,2A)

HC

C2

60

10U/6.3V_4

+5

B B

4

HP

R

L

HP

NE1-VREFO-L

LI

NE1-VREFO-R

LI

C2-VREFO

MI

CO

DEC_VREF

C2

R2

C2

89

86 2.2U/6.3V_4

85 10U/6.3V_4

100K_4

INT_AMIC-VREFO

801U/ 10V_4 C2

Place next to pin 26

NE1-VREFO-L LI

T-CLK BI

30

NE1-VREFO-R LI

O3-CAP LD

7

C2

10U/6.3V_4

27

28

29

EF VR

O1-CAP LD

C2-VREFO MI

C

ATA-IN

DD-IO

SD

DV

SYN

8

9

10

47

Z_SDIN

AC

56 *22P/50V_4

C2

25

26

D1

AVSS1

AVD

MI

C2-R/SLEEVE

MI

C2-L/RING2

MO

BEEP

SETB RE

PC

11

12

AC

Z_RST#_AUDIO

R2

71 33_4

NE2-L

LI

NE2-R

NE1-L

LI

NE1-R

C1-CAP

NO-OUT

JDREF

nse B

Se

nse A

PC

BEEP

4

U1

NC

24

C1_INT_L

MI

23

C1_INT_R

MI

22

LI

NE1-L

21

LI

NE1-R

20

82 *SHORT_6

R2

19

18

SL

EEVE

17

RI

NG2

16

15

14

13

Placement near Audio Codec

6Vrms

1.

C2

48 0.1U/16V_4

C2

100P/50V_4

35

31

32

33

34

N

VEE

CB

-OUT-L

CP

-OUT-R HP

HP

C255

AL

IO0/DMIC-DATA

IO1/DMIC-CLK

ATA-OUT

SS

GP

DV

SD

2

3

5

6

4

R2

66 *0_4

VAA

AD

83

C2

0.1U/16V_4

AD

71 1U/10V_6

C2

67 1U/10V_6

C2

+3

VPCU

65 10U/6.3V_4

C2

75 200K_4

R2

73 100K_4

R2

BEEP

_1

R2

59 10K_4

56

50

R2

4.7K_4

H_AZ_C ODEC_ RST# [5 ]

PC

H_AZ_C ODEC_ SYNC [5]

PC

H_AZ_C ODEC_ SDIN0 [5]

PCH_AZ_ CODEC _BITC LK [5]

PC

H_AZ_C ODEC_ SDOUT [ 5]

3

OGND

VA

+5

OGND

AD

88

C2

10U/6.3V_4

cap place close to MIC-connector

C1_INT_L_C

MI

C1_INT_R_C

AD

OGND

HP_JD#SENSEA

91 1K_4

R2

90 1K_4

R2

+3

D1

2 RB500V-40

1 RB500V-40

D1

C2

45

0.1U/16V_4

V

Place next to pin 9

C2

87 0.1U/16V_4

MI

C1_INT_R_C

C1_INT_L_C

MI

C2

*1000p/50V_4

Analog

Digital

+1

.5V

C2

46

10U/6.3V_4

78

AD

OGND

MI

C1_INTL1

C2

*1000p/50V_4

Z_SPKR [5]

AC

PC

BEEP_EC [ 22]

Gr

77

OGND

AD

INT MIC array

DN001542000 mic-a-m-qt zea01hf-2p-top

INT_AMIC_SMD

HEADPHONE/MIC/LINE combo

2

ounding circuit(ADO)

PIN1, PIN4, PIN3, PIN6 are ANALOG

AD

6

U2

1

2

AD

OGND

MI

3

Q3

1

4 3

*ME2N7002DKW-G_115MA

C1_INTL1

C4

15

*22p/50V_4

40mils

NG2

RI

EEVE

SL

40mils

R

HP

HPL

R3

*1K_4

6

2

5

R5

63 10K_4

L17 80ohm

L14 80ohm

L15

L16

R3

05

*1K_4

EEVE

SL

RI

NG2

*SHORT_6

06

MI

_100MHz

IN

C2-VREFO

R-1

HP

HPL-1

+3

VPCU

R2

57

*100K_4

T_AMIC-VREFO

00

R3

2.2K_4

04 62_4

R3

07 62_4

R3

1

+1

.5V

67

R2

3

1

10

R3

2.2K_4

RI

SL

C3

*2200P/50V_4

AD

*100K_4

2

0

Q3 *PJA138K

C2

52

*1u/10V_4

21 *0_4

R3 R3

20 *0_4

R3

09 *0_4

R5

60 *0_4

R5

62 *0_4 61 *0_4

R5

AD

OGND

FB

1/FB2(SLEEVE/RING2) should choose DC resistance (Rdc) < 30m-ohm to get the best audio performance for HP crosstalk

NG2_R

EEVE_R

C3

00

*2200P/50V_4

01

OGND

C2

*100P/50V_4

AD

63 *10K_4

R2

SL

94

OGND

EEVE_R

R_SYS

HP

RI

NG2_R

C3

04

*100P/50V_4

AC

HP

_JD#

HPL_SYS

Z_RST#_AUDIO

AD

OGND

4 2 6 5 7 1 3

22

CN

313301-1

V

Mute(ADO)Codec PWR 5V(ADO)

AVDD1

DIGITAL

+5V

A A

Co

dec PWR 1.5V(ADO)

+1

.5V

L13

L12

ANALOG

BLM15PX181SN1D_1.5A

ANALOG DIGITAL

*SHORT_6

5

+5VA

R_ R_

+1

.5VA

L_S L_S

SPK+ SPK-

+3V

AM

P_MUTE# [22]

1

R2

72

1K_4

#

PD

3 RB500V-40

D1

4 RB500V-40

D1

In

ternal Speaker

AC

Z_RST#_AUDIO

Z_RST#_AUDIO_R

AC

40mil for each signal

16 *SHORT_6

R3

PKPK+

17 *SHORT_6 18 *SHORT_6

R3

19 *SHORT_6

R3

06

05

C3

*68p/50V_4

4

+3

+1.5V

2

9

Q2 PJA138K

R2

60

*10K_4

3

footprint 88266-040xx-xxx-4p-l

SPK+_1

R_

SPK-_1

R_

PK-_1

L_S L_S

PK+_1

08

07

C3

*68p/50V_4

3

CN

23

1 2 3 4

50224-00401-001

NE1-L

LI

NE1-VREFO-L

NE1-VREFO-R

LI

NE1-R

Close to Audio Jack

AD

R3

11 *SHORT_6

OGND

C3

02 4.7U/6.3V_6

08 4.7K_4

R3

03 4.7K_4

C299 4.7U/6.3V_6

2

L-1

HP

R-1

HP

R_SYS

HP

D1

21

8 *VPORT 0402 151 MV05

HP

L_SYS

9 *VPORT 0402 151 MV05

D1

21

OGND

Z8AD

AD

of

3218

of

3218

of

3218

7

D1

SL

EEVE_R

RING2_R

Size Document Number Rev

ze Document Number Rev

Si

ALC283/HP/SPK

We

Date: Sheet

1 2

5V/30V/0.23p_4

D2

4

1 2

change from AGND to GND for ESD issue.

dnesday, April 08, 2015

5V/30V/0.23p_4

anta Computer Inc.

Qu

PROJECT :

1

1A

5

FF WiFi & BT (NGF)

NG

D D

USBP4

+[7,20]

USBP4

-[7,20]

C C

B B

PCI

E_TXP1_NGFF[5]

PCI

E_TXN1_NGFF[5]

_RXP1_NGFF[5]

PEG

_RXN1_NGFF[5]

PEG

K_PCIE_NGFFP[6]

CL CLK_PCIE_NGFFN[6]

K_24M_DEBUG[7,20]

CL

AME#[7,15,20,22]

LFR

WL

AN_CLKREQ#

PCIE_WAKE#_R[20]

R518 *NGFF@0_4 R1

71 *NGFF@0_4

CLK_24M_DEBUG_C LFR

AN_WAKE_R#

WL

AME#_C

4

CN1

3

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75

NGFF

GN

D

USB_

D+

USB_

D-

GN

D O CLK(O)

SDI

O CMDIO)

SDI

O DAT0(IO)

SDI

O DAT1(IO)

SDI

O DAT2(IO)

SDI SDI

O DAT3(IO)

SDI

O Wake(I)

SDI

O Reset

KEY

1

KEY

2 3

KEY

4

KEY

D

GN

p0

PET PET

n0

GN

D

PERp

0

PERn

0

GN

D

REF

CLKP0 CLKN0

REF

D

GN

KREQ0#

CL

ake0#

PEW GN

D

PET

p1

PET

n1

GN

D

PERp

1

PERn1

D

GN

served1

Re

served2

Re

D

GN

NGFF@WLAN_NGFF CONN(Type 2230)

PCM_

UART

UART UART

Cl

ink RESET

CL

K(32KHz)

SUSCL

PERST

DISABLE#2

W_

DISABLE#1

W_

NF

C I2C SM DATA

NF

C I2C SM CLK

NF

C I2C IRQ

NF RESERVED3 RESERVED4 RESERVED5

PCM_

UART

ink DATA

C Reset#

3.

3Vaux

3.

3Vaux

LE

D#1 CLK

SYNC

OUT

D#2

LE

GN

Wake

Ke Ke Ke Ke

CTS RTS

ink CLK

CO

EX3

CO

EX2

CO

EX1

3Vaux

3. 3Vaux

3.

ini1_VDD

+3V_M

2 4 6 8 10 12

IN

14 16 18

D

20 22

Rx

24

y 5

26

y 6

28

y 7

30

y 8

32

Tx

34 36 38 40 42 44 46 48 50 52

WL

0#

54

BT

56

RF

58 60 62 64

LA

66

LA

68

LA

70

LA

72

+3V_M

74

AN_RST# _EN_R _EN_R

D0_C D1_C D2_C D3_C

ini1_VDD

3

+3VPCU

AC_WLAN PWR#[22]

IO

TP R9 R1

R1 R1 R159 *NGFF@0_4 R1

47 2 *NGFFAC@0_4 51 NGFF@0_4

R8

21 33_4 22 33_4

R8

57 *NGFF@0_4 58 *NGFF@0_4

60 *NGFF@0_4

PL

TRST#

R2

39

*100K_4

LA LA LA LA

+3V

D0 [7,15,20,22] D1 [7,15,20,22] D2 [7,15,20,22] D3 [7,15,20,22]

6

Q2

1

C214

*AC@1u/6.3V_4

2

*AC@AO3413

+3V_M

12/29 add

AC_RST# [1 2,20,22]

IO

PLTRST# [12,14,15,20,21,22] BT_POWERON [20,22] RF

_EN [20,22]

R2

ini1_VDD

2

07NAC@0_8

3

C1

93

10U/6.3V_6

NG

FF@10u/6.3V_6C132

NG

[email protected]/10V_4C135

NG

[email protected]/10V_4C134 [email protected]/10V_4C138

NG

[email protected]/10V_4C139

NG

_POWERON

BT

_EN

RF

ini1_VDD

+3V_M

C2

07

0.1U/16V_4

94 180P/ 50V_4

C6 C695 180P/ 50V_4

C1

89

*0.1u/16V_4

+3V_M

ini1_VDD

C1

88

*0.1u/16V_4

1

ini1_VDD

+3V_M

1

5

Q2 *AC@PJA138K

ini1_VDD

+3V_Mini1_VDD

R2

38

*[email protected]_4

PCI

E_WAKE#_R

Qu

anta Computer Inc.

PROJECT :

Si

ze Document Number Rev

Si

We

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

2

dnesday, April 08, 2015

PROJECT :

US

B HUB -1

Z8AD

1A

of

3219

of

3219

of

1

3219

73

R1 [email protected]_4

E_CLKREQ1_NGFF#[5]

PCI

A A

5

1

+1.

8V

Q1 NGFF@PJA138K

2

3

9

4

WL

AN_CLKREQ#

23 *AC@0_4

WA

KE_SRC_1[12,14]

WL

AN_WAKE#[22]

R2

24 *0_4

R2

3

2

+3V_M

5

AN

WL

D D

BT

_POWERON[19,22]

K_24M_DEBUG[7,19]

CL

PC

IE_TXP2_WLAN[5]

PC

IE_TXN2_WLAN[5]

PC

IE_RXP2_WLAN[5] IE_RXN2_WLAN[5]

PC

C C

K_PCIE_WLANP[6]

CL

K_PCIE_WLANN[6]

CL

IE_WAKE#_R[19]

PC

TRST#

PL

+3

V_Mini1_VDD

PC

IE_CLKREQ2_WLAN #

PC

IE_WAKE#_R

R2 R5

4

25 *Mini@0_4 19 *Mini@0_4

3

+3

V_Mini1_VDD

5

CN1

51

served

Re

49

served

Re

47

Re

served

45

Re

served

43

D

GN

41

.3Vaux

+3

39

.3Vaux

+3

37

GN

D

35

GN

D

33

p0

PET

31

n0

PET

29

D

GN

27

GN

D

25

PER

p0

23

n0

PER

21

D

GN

19

M_C4

UI

17

UI

M_C8

15

D

GN

13

FCLK+

RE

11

FCLK-

RE

9

GN

D

7

CL

KREQ#

5

served

Re

3

served

Re

1

KE#

WA

LE LE

D_WWAN#

LE

SM

W_

UI

D

GN

*Mini@AAA-PCI-092-P05

54

53

+3

GN

+1 D_WPAN# D_WLAN#

GN

US

B_D+

US

B_DGN

B_DATA

B_CLK

SM

+1

GN

.3Vaux

+3

ST#

PER

DISABLE#

GN

M_VPP

UI

M_RESET

M_CLK

UI

M_DATA

UI

M_PWR

+1

GN

+3

52

.3V

50

D

48

.5V

46 44 42 40

D

38 36 34

D

32 30 28

.5V

26

D

24 22 20 18

D

16 14 12 10 8 6

.5V

4

D

2

.3V

US US

SM

B_RUN_DAT_ R B_RUN_CLK_R

SM

PL

TRST#_2

RF

_EN_C

RAME#_R

LF LA

D3_R

LA

D2_R

LA

D1_R

LA

D0_R

B_BT+ B_BT-

AN_LED#

WP

AN_LED1#

WL

MAX_LED#

WI

R2

02 *Mini@0_4

R2

03 *Mini@0_4

R1 R2

05 *Mini@0_4

R2

06 *Mini@0_4

R2

R5

06 *Mini@0_4

R5

07 *Mini@0_4

99 *MiniAC@0_4 01 *Mini@0_4

23 *33_4

R8

R1

94 *Mini@0_4

R1

95 *Mini@0_4 96 *Mini@0_4

R1

97 *Mini@0_4

R1

98 *Mini@0_4

R1

V_Mini1_VDD

R1

*[email protected]_4

PL

LF

2

93

US

BP4+ [7,19]

US

BP4- [7,19]

SM

B_RUN_DAT [7,11,21]

SM

B_RUN_CLK [7,11,21]

TRST#

RAME# [7,15,19,22] D3 [7,15,19,22]

LA

D2 [7,15,19,22]

LA

D1 [7,15,19,22]

LA

D0 [7,15,19,22]

LA

IO

AC_R ST# [1 2,19,2 2]

TRST# [12,14 ,15,19,21,22]

PL

_EN [19,22]

RF

1

_EN_C

RF

V_Mini1_VDD

B B

Q2 *Mini@PJA138K

2

3

4

IE_CLKREQ2_WLAN #[5]

PC

A A

5

1

.8V

+1

+3

R2

37

*[email protected]_4

PC

IE_CLKREQ2_WLAN #

.8V[9,12,13,14,15 ,16,19,21,22,26,30]

+1

V[4,7,9,11,12,13 ,14,15,16,18,19,21,22,25,2 7,28,29,30]

+3

3

2

Si

Size Docum ent Number Rev

ze Doc ument Num ber Rev

Date: Sheet

C7

03 *10p/50V_4

Wi

We

dnesday, April 08, 2015

anta Computer Inc.

Qu

PROJECT :

Fi & BT

Z8AD

1

1A

of

3220

of

3220

of

3220

5

eMMC

+1

.8V

Ve

ndor P/N

EM EM EM EM

SOC_PLTRST#[6,14]

EM

MC_CMD[4]

EM

MC_CLK[4]

MC_DATA_0[4] MC_DATA_1[4] MC_DATA_2[4] MC_DATA_3[4]

MC_DATA_4[4] MC_DATA_5[4] MC_DATA_6[4] MC_DATA_7[4]

PL

TRST#[12,14,15,19,20,22]

MC_RCLK[4]

AKE3TZ-0500

AKE3SZ-T500

AKE3TG-TW00

AKE3SZ-TW00

R1 R1

19 *EM@0_4 18 EM@0_4

EM

SAMSUNG 64G

D D

Samsung 32G

HYNIX 64G

HYNIX 32G

C C

R1 R1

R5

D

GN

MC_GPO_RST0_R

33

TP TP

34

21 *EM@10K_4 20 *EM@10K_4

97 *EM@10K_4

1

U2

W5

D

CM

W6

K

CL

H3

T0

DA

H4

DA

T1

H5

DA

T2

J2

DA

T3

J3

T4

DA

J4

T5

DA

J5

DA

T6

J6

DA

T7

U5

RS

T

R5

RCL

K

M9

VSF

_M9

M10

VSF_M10

EM@H26M52103FMR

fbga169-samsung-kmhog0000m-0_5s

EM

MC_GPO_RST0_R

EM

MC_CMD

MC_RCLK

VC

CQ CQ

VC

CQ

VC VC

CQ

VC

CQ

VC VC VC VC

DI

VD

VSS VSS VSS VSS VSS

VSS VSSQ VSSQ VSSQ VSSQ VSSQ

C C C C

4

K6 AA5 W4 Y4 AA3

T10 U9 M6 N5

K2

0

R1 U8 M7 P5 H6 T5 AA6 Y5 Y2 AA4 K4

[email protected]/6.3V_4

GN

D

+3

C1

[email protected]/6.3V_4

GN

D

DI

VD

89 *EM@0_4

R5

90 *EM@0_4

R5

.8V_EMMC

+1

42

C1

V_EMMC

76

GN

D

C1

[email protected]/6.3V_4

GN

D

75

C1 [email protected]/6.3V_4

GN

D

31

C1

[email protected]/10V_4

GN

D

33

C1

[email protected]/6.3V_4

GN

D

22

C1

[email protected]/6.3V_4

GN

D

02

GN

03

C1 [email protected]/10V_4

GN

D

R1

52 *SHORT_4

19

C1

[email protected]/6.3V_4

D

69 *SHORT_4

R1

43

C1 [email protected]/6.3V_4

D

3

G-sensor(ACS)

AC

CEL_INTA

.8V

+1

+3

V

C_2_SDA[7]

I2

C_2_SCL[7]

C3

57

GS@22P/50V_4

SM

B_RUN_DAT[7,11,20] B_RUN_CLK[7,11,20]

SM

2

+3

V

HDD_

+G

31 *GS@0_4

R5

*GS@PJ4N3KDW

1

4 3

Q4

9

R5

32 *GS@0_4

73 *SHORT_6

R4

INTA[16]

I2

C_2_SDA_C C_2_SCL_C

I2

+G

_SEN_PW

24 GS@0_4

R5 R5

20 GS@0_4

6

I2

C_2_SDA_C

2

+1.8V

C_2_SCL_C

I2

5

_SEN_PW

G_

R5

27 *[email protected]_4 04 *[email protected]_4

R5

Gs

ensor_INT[6]

63

C3 [email protected]/10V_4

+G

MBDATA_R

MBCLK_R

G_MBDATA_R

MBCLK_R

G_

_SEN_PW

+G

R526 *SHORT_4

28 *GS@0_4

R5

12 *GS@0_4

R5

_SEN_PW

C3

C367 GS@33P/50V_4

58

C3

GS@10u/6.3V_6

AC

CEL_INTA

G_

MBDATA_R MBCLK_R

G_

71 GS@33P/50V_4

G_

MBDATA_R

G_

MBCLK_R

R5

95 *SHORT_4

GS@2N7002K

Q5

5

1

U2

4

1

Vd

14

VD

11

IN

T1

9

IN

T2

7

SA0

6

SD

4

SC

8

CS

GS@LIS3DHTR

3

2

1

GS@2N7002K

d_IO

Q4

+1

.8V[9,12,13,14,15,16,19,20,22,26,30]

+3VPCU[6,8,9,12,15,16,18,19,22,24,25,26]

V[4,7,9,11,12,13,14,15,16,18,19,22,25,27,28,29 ,30]

+3

2

NC

RE RE

SERVED SERVED

V

+3

3

1

NC

GN

D D

GN

D

GN GN

D

R4

59

GS@10K_4

2

3

10 15

5 12 13 16

CEL_INTA

AC

D

A L

6

G Sensor INT

SD

LL IC (HSR)

HA

2nd

source󶁪AL008251000 -- YBT

3rd source 󶁪AL009132001

B B

4th source 󶁪AL009249000

+3VPCU

23

R3

BL

ON_CON

Q3 DTC144EUA

*100K_4

2

5

+3

V

R338

10K_4

PCH_EDP_BLON[4]

H_BLON_EC[22]

PC

A A

R339 *SHORT_4

40 *SHORT_4

R3

5

PCH_BLON_R BL#

41

R3

100K_4

Q3

8

PJ4N3KDW

5

R333

10K_4

6

2

1 3

1

4 3

LID591#,EC intrnal PU

LID#

D2

5

1N4148WS

BL

4

LID# [16,22]

ON_CON [13]

EC

_FPBACK# [ 22]

/MMC CARD READER (DRD)

95 *SHORT_4

3

R2

96 *SHORT_4

R2 R2

97 *SHORT_4

R292 *SHORT_4

93 *SHORT_4

R2 R2

94 *SHORT_4

98 *SHORT_4

R2

99 *SHORT_4

SD_D1 SD_D0 SD_CLK SD_CMD SD_D3 SD_D2 SD_WP SD_CD#

MS_D1 MS_D0 MS_D2 MS_D3 MS_CLK MS_BS

MS_INS#

C2

96 *10p/50V_4

C2

97 *10p/50V_4

C291 *10p/50V_4

C2

92 *10p/50V_4

C2

93 *10P/50V_4

SP1[1

2] 2]

SP2[1 SP3[1

2]

SP4[1

2]

SP5[1 SP6[1

2]

SP7[1

SP8[1

2]

Sh

are Pin

SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9

SP1

=SD_D1

SP2

=SD_D0=MS_D1

SP4

=SD_CMD=MS_D2

SP5

=SD_D3=MS_D3

SP6

=SD_D2=MS_CLK

SP1

=SD_D1

SP2

=SD_D0=MS_D1

SP3

=SD_CLK=MS_D0

SP4

=SD_CMD=MS_D2

=SD_D3=MS_D3

SP5

=SD_D2=MS_CLK

SP6

=SD_WP=MS_BS

SP7

SP8

=SD_CD#

CN6

11

WP

10

CD

9

DA

TA2

8

DA

TA1

7

DA

TA0

6

VSS2

5

K

CL

4

VD

D

3

VSS1

2

D

CM

1

CD/

DATA3

12

I

EM

SP3

=SD_CLK=MS_D0

C2

98

10P/50V_4

D

GN

13

D

GN

14

15

16

NC

17

NC

D

GN

5-

251301001000-6

V3_SD_SW

+3

SP7

=SD_WP=MS_BS

SP8

=SD_CD#

SP6

=SD_D2=MS_CLK

SP1

=SD_D1

SP2

=SD_D0=MS_D1

=SD_CLK=MS_D0

SP3

+3

V3_SD_SW

=SD_CMD=MS_D2

SP4

SP5

=SD_D3=MS_D3

10

mils

V3_SD_SW

+3

C290

4.7U/6.3V_6

C2

95

0.1U/16V_4

Place close to connector

Qu

anta Computer Inc.

PROJECT :

Size Document Number Rev

ze Document Number Rev

Si

Date: Sheet

2

Date: Sheet

PROJECT :

MC/G-sensor/HALL/CR

eM

Z8AD

1A

21

1

1A

of

32Wednesday, April 08, 2015

5

(KBC)

EC

R1

23 2.2_6

1 2

VPCU

+3

+3VPCU_EC and +3V_RTC minimum trace width 12mils.

D D

3/2 add

+3

VPCU

D10

SDMK0340L-7-F

PCH_SUSPWRDANCK[14,26]

US

_POWER_ON[1 5]

PC

_Protect[24]

AC

SU

SPWRDANCK_EC[26]

BON#[17]

R72 100K_4

2 1

1 2

3

C5 1u/6.3V_4

K_24M_KBC

C C

B B

CL

2

R8

*22_4

C5

7

*10p/50V_4

TP

L6

M15AG121SN1D(120,500MA)_4

BL

12

mils

C108

C334

0.

1U/16V_4

+3

V_S5

PL

CL

H_SLP_S0_N[14]

SER

SIO_EXT_SMI#[14]

SIO_EXT_SCI#[14 ]

WL

AN_WAKE#[19]

DNBSWON#[14]

EC_PWROK[3,14]

H_BLON_EC[21 ]

PC

LA

EC_Override[6]

AMP_MU TE#[18]

OD

TEMP_MBAT[24]

IOAC_ WLAN PWR #[19]

PC

PG_1.05V_EC#[26]

HW

TP

17

US

BON#

TP22

0.

1U/16V_4

+3V

D0[7,15,19,20]

LA LA

D1[7,15,19,20] LAD2[7,15,19,20] LAD3[7,15,19,20]

TRST#[12,14,15,19,20 ,21]

K_24M_KBC[7]

LF

RAME#[7,15,19,20]

R138 *0_4

IRQ[14]

R95 *SHORT_4

TP

15

R83 *SHORT_4

SUSB#[14,2 8,29]

_EN[13 ]

TS

N_WAKE#[12]

D_POWER[16]

AC

IN[24]

BEEP_EC[18]

MY MY

MY MY1[15] MY2[15] MY MY MY5[15] MY6[15] MY7[15] MY8[15]

MY9[15] MY10[15] MY11[15] MY12[15] MY13[15] MY14[15] MY15[15]

C111

0.

R8

R814 2.2_6

1 2

AC

_Protect _R

16[15] 17[15]

R28 *SHORT_4

_POWER_ON

TP

0[15]

3[15] 4[15]

1U/16V_4

8 *2.2_6

1 2

LA LA LA LAD3 PL CL LF

PROCHOT_EC

SL SER SI SIO_EXT_SCI# WR

WL

KB_ DNB

EC SU EC_PWROK PC TS LA ME AMP_MU TE#

OD AC TE IOAC_ WLAN PWR # PC HW

PC

H_SUSPWRDANCK

SO SO SO SO

MY MY

MY MY MY2 MY MY MY MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15

For test only

A A

SW6

3 1 4

*Power Switch

2

5 6

5

NBSWON#

+A

C45

0.1U/16V_4

EC

VPCU_EC

+3

C87

C43

0.

1U/16V_4

+3V_EC

C65

1U/16V_4

0.

D0 D1 D2

TRST#

K_24M_KBC

RAME#

P_A#

O_EXT_SMI#

N_WAKE#

126

IRQ

ST#

KBR

AN_WAKE#

113

BL_LED

123

SWON#

_APWROK

119

SB#

H_BLON_EC _EN

109

_WR#

108

D_POWER IN MP_MBAT

BEEP_EC

122

PG_1.05V_EC#

105

C_SPI_CLK_R1

101

C_SPI_CS#_R1

102

C_SPI_MOSI_R1

103

C_SPI_MISO_R1

16 17

FA

N1_PWM

100

S5_ON_R

125

0 1

3 4 5

MX0[15] MX1[15] MX2[15] MX3[15] MX4[15] MX5[15] MX6[15] MX7[15]

set SW (FSW)

Re

3VPCU

.8V_S5

+1

AGND

U8

10

LA

9

LA

8

LA

7

LAD3/GPM3(3)

22

LP

13

LP

6

LF

17

LPCPD#/GPE6

GA

5

SER

15

EC

23

ECSCI#/GPD3

14

WR

4

KBR

16

PW

CRX CT

80

DA DS

33

GINT/CTS0#/GPD5

88

PS2

81

DA

87

PS2 TX RXD/SIN0/GPB0

71

AD

72

AD

73

AD

35

RTS1#/GPE5

34

PW DT

95

CT

94

CRX

FS FS FM FM

56

KSO

57

KSO

32

PW

SSCE0#/GPG2 SSC

36

KSO

37

KSO

38

KSO2/PD2

39

KSO

40

KSO

41

KSO5/PD5

42

KSO6/PD6

43

KSO7/PD7

44

KSO8/ACK#

45

KSO9/BUSY

46

KSO10/PE

51

KSO11/ERR#

52

KSO12/SLCT

53

KSO13

54

KSO14

55

KSO15

4

12 mils

R154 *SHORT_6

+3V_RTC_R

55 *0_6

R1

C109

0.

D0/GPM0(3) D1/GPM1(3) D2/GPM2(3)

CRST#/GPD2 CCLK/GPM4(3) RAME#/GPM5(3)

20/GPB5(3)

IRQ/GPM6(3)

SMI#/GPD4(3)

ST# ST#/GPB6(3)

UREQ#/BBO/SMCLK2ALT/GPC7(3)

0/GPC0

X0/TMA0/GPB2(3)

C4/DCD0#/GPJ4(3) R0#/GPG6

DAT1/RTS0#/GPF3

C5/RIG0#/GPJ5(3)

CLK1/DTR0#/GPF2

D/SOUT0/GPB1

C5/DC D1#/GPI5( 3) C6/DS R1#/GPI6( 3) C7/CT S1#/GPI7( 3)

M7/RIG1#/GPA7 R1#/SBUSY/GPG1/ID7 X1/SOUT1/GPH2/SMDAT3/ID2

1/SIN1/SMCLK3/GPH1/ID1

CK/GPG7 CE#/GPG3

OSI/GPG4 ISO/GPG5

16/SMOSI/GPC3(3) 17/SMISO/GPC5(3)

M6/SSCK/GPA6

E1#/GPG0

0/PD0 1/PD1

3/PD3 4/PD4

C107

0.

1U/16V_4

11

26

50

92

C

BY

VC

VST

EXTERNAL SERIAL FLASH

KBMX

0/STB#

1/AFD#

2/INIT#

3/SLIN#

4

KSI

58

59

60

61

62

MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7

4

1U/16V_4

114

121

BY

VST

LPC

CIR

SPI ENABLE

5

6

KSI

63

64

+3VPCU_ECPLL

C110

0.

106

127

74

83

84

C

AVC

BY(PLL)

BY_FSPI

CS#/GPE2

CLK/GPE3

VST

EG

IT8987 LQFP

UART port

7

KSI

VSS

VSS27VSS

1

49

65

L7 BLM15AG121SN1D(120,500MA)_4

L8 BL

M15AG121SN1D(120,500MA)_4

1U/16V_4

82

20

19

T/GPE7

AD/GPE1 EG

L80LLA

LAT/BAO/GPE0

L80H

GPIO

VSS

AVSS

VSS

75

91

104

AGND EC

+3VPCU_EC

or PLL Power)

(F

H_ACPRESENT

PC

DP

3

98

99

H7 GP

5/GPH5

6/GPH6

ID

WROKEC

BT

_POWERON

SLP_SUS#_EC

_CLAMP_REQ#

FB

US

BON_#

GP

5

USB_CLT1

B_BC_ON

US

96

97

93

3/GPH3

4/GPH4

ID

KRUN#/ID0/GPH0 CL

R8

9 *SHORT_4

R84 *SHORT_4

SM BUS

PEC

DAT2/PECIRQT#/GPF7(3)

SM

PS/2

PS2

CLK0/CEC/TMB0/GPF0

PS2

I/SMCLK2/GPF6(3)

DAT0/TMB1/GPF1

PWM

TA

TACH1A/TMA1/GPD7(3)

WAKE UP

NG#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7

RI

A/D D/A

DA

C2/TACH0B/GPJ2(3)

DAC3/TACH1B/GPJ3(3)

CLOCK

ORE VC

12

C59

0.1U/16V_4

SPI_PWR

R412 3.3K_4

R461 3.3K_4

BT

_POWERON [19,20]

SLP_SUS#_EC [14]

9

TP

C#

D/

KRUN#R

CL

CLK0/GPB3

SM SM

DAT0/GPB4

SM

CLK1/GPC1

SMDAT1/GPC2

PS2CLK2/GPF4

DAT2/GPF5

PS2

PWM0/GPA0

M1/GPA1

PW

M2/GPA2

PW PW

M3/GPA3

PW

M4/GPA4

PWM5/GPA5

CH0A/GPD6(3)

RI0/GPC4(3)

TM TM

RI1/GPC6(3)

RSW/GPE4

PW

RI

1#/GPD0(3)

RI

2#/GPD1

AD

C0/GPI0 (3)

ADC1/GP I1(3)

C2/GPI2 (3)

AD

C3/GPI3 (3)

AD AD

C4/GPI4 (3)

CH2/GPJ0(3)

TA

GP

J1(3)

GPJ7 GPJ6

IT

C356

0.1U/16V_4

3

R105 0_4

110 111 115 116 117 118

85 86 89 90

24 25 28 29 30 31

47 48

120 124

107 18 21

112

66 67 68 69 70

76 77 78 79

2 128

898 7

SPI_PWR

GND

3

C# [24]

D/

TP

19 TP21 TP18

20

TP

CL

CLK

MB MB

DATA

MB

CLK2

MBDATA2

PECI

H_

D#

LI

IO

AC_R ST#

EC

_FPBACK#

TPCLK

DATA

TP

PWRLED#

TLED1#

BA

SLED#

SU BA

TLED0#

MA

INON

FAN2_PWM

FA

NSIG

FAN2_RPM

SON

SU dG

PU_OTP#

SWON#

NB dG

PU_OPP#

HW

PG

MRST#

RS

_EN

RF IC

MNT

7 10u/6.3V_6

C3

SC_#

SU

ON

VR IO

AC_L ANPW R#

KRUN_#

CL EC

_FB_CLAMP

PC

H_PWROK

FAN2_DAC

IOAC_ WIGIG_ RST# TP_INT_EC#

SPI NOR FLASH

SPI_WP#

SPI_Hold#

ACDC [24]

SB_

WROK_EC [14]

DP

KRUN#

CLK [24]

MB MB

DATA [24]

MB

CLK2 [16]

R1

36 *43_4

0 *SHORT_4

R3

R54 *SHORT_4

R42 *0_4

TP

IO

AC_R ST# [ 12,19 ,20]

EC_FPBACK# [21]

TPCLK [15]

DATA [15]

TP

PWRLED# [16]

TLED1# [16]

BA

S_LED# [16]

SU BA

TLED0# [16]

MAINON [26,27,28,29,30]

FANSIG [16]

TP6

SON [25,27]

SU

TP

SWON# [16]

NB

RS

_EN [19,20]

RF

IC

MNT [2 4]

ECAGND

TP TP

IO

AC_L ANPW R# [1 2]

R53 *SHORT_4

9 *SHORT_4

R5

6 *SHORT_4

R7

R99 *SHORT_4

TP_INT_EC# [15]

MBDATA2 [16]

25

LI

16

MRST# [14]

7 8

SM BUS ARRANGEMENT TABLE

SM

Bus 1

SM Bus 2

SM Bus 3

Bus 4

SM

U20

8

VCC

3

WP#

SPI_HOLD7GND

SPI_FLASH

soic8-7_9-1_27

AKE5GZP 0N00

IC FL ASH (8 P) W 25Q8 0BW SSIG ( SOIC)

SPI_SI

SPI_SO

SPI_SCK

5 2 1

CS#

6

4

D# [16,21]

RM_MOINTOR [8]

TH

SU

SC#

EC_ODD_EJ# [16]

Battery

PCH/VGA

SOC_SPI_MOSI_R1 SOC_SPI_MISO_R1 SOC_SPI_CS#_R1 SOC_SPI_CLK_R1

GND

2nd source: AKE5GFN0Q00

SU

SC# [14]

KRUN# [7,15]

CL

S5

_ON [25,26,30]

TP_EN_EC [15]

CPUFAN# [16]

2

SPI_PWR

2

R410 3.3K_4

SOC_SPI_MOSI_R1

SOC_SPI_MISO_R1

PC

SM BUS PU(KBC)

PROCHOT_EC

HW

PG(KBC)

VGG_PW RGD[28,29]

VCORE_ PWRGD[28]

SYS_HWPG[25]

HWPG_1.35V[2,2 7]

SOC_SPI_CS#_R1

R462 *10K_4

R411 *10K_4

Size D ocument Number Rev

Size Document Number Rev

Date: Sheet of

_ON_R

S5

EC

_FB_CLAMP

NB

SWON#

H_SUSPWRDANCK

BEEP_EC

MA

INON

SON

SU

VR

ON

MB

CLK

MB

DATA

MB

CLK2

MB

DATA2

CLK2

MB

DATA2

MB

R96

100K_4

SPI_PWR

R5

64 10K_4

R130 10K_4

31 10K_4

R1

29 *10K_4

R602 *10K_4

2 100K_4

R3

R1

37 100K_4

R34 100K_4

R132 4.7K_4

33 4.7K_4

R1

R134 4.7K_4

35 4.7K_4

R1

R6

04 *4.7K_4

R603 *4.7K_4

3

Q16

2

2N7002K

1

D7 *RB500V-40

D8 RB500V-40

D9 RB500V-40

D6 *RB500V-40

R475 *SHORT_4 R476 *0_4

Qu

PROJECT :

KBC IT8987

1

+3VPCU

+1.8V_S5

+1

.8V

2/11

+3

VPCU

+3

V_S5

2/11

+3V

H_PROCHOT# [5,24,28,29]

+3V

R55 10K_4

HWPG

+1.8V_S5 +3VPCU

anta Computer Inc.

Z8AD

22 32Wednesday, April 08, 2015

1

22 32Wednesday, April 08, 2015

3A

5

4

3

2

1

LE6

HO *H-C315D118P2

D D

1

LE10

HO *h-o138x91d138x91n

1

C C

LE12

HO *h-c91d91n

1

B B

LE14

HO *h-o138x91d138x91n

1

HO

LE18

*H-E315X276D118P2

HO *H-C315D118P2

1

LE8

1

LE19

HO MBZRT001010

1

HO

LE16

*H-C315D118P2

1

R593 *0_6

LE9

HO *H-C315D118P2

1

LE21

HO *H-TC197BC65D65P2

1

*H-C276D118P2

LE7

HO

1

LE17

HO *H-C315D118P2

1

HO MBZ8A001010

*0_6 R5

96

LE22

1

LE11

HO *H-C315D118P2

1

LE20

HO MBZ8A001010

1

+V

IN

C3

4

*0.1U/25V_4

A A

5

+V

IN

C3

*0.1U/25V_4

+V

IN

C2

8

10

*0.1U/25V_4

+V

IN

C2

*0.1U/25V_4

13

uanta Computer Inc.

Q

PROJECT :

Si

ze Document Number Rev

The

rmal / Hole

We

Date: Sheet

4

3

Date: Sheet

We

dnesday, April 08, 2015

2

Z8AD

1A

of

3223

of

3223

of

1

3223

5

4

3

2

1

2DC2003-002111F

dcjk-2dc2 003-00011 1-3p-v

7

PJ

1 2

ACDC[22]

6

1 2 3 4 5 6 7 8

7

IN[2 2]

AC

PC60

*47p/50V_4

3

456

PR

8

*Short_4

PC10

0.1u/50V_6

8

PC

*100p/50V_4

70

PC

0.1u/50V_6

PR *0_4

6

69

PC

2200p/50V_6

PR

7

*10K_4

+3

VPCU

6

154 3

BAT

PR 100K_4

2

-V

PR

12

147

100K_4

6

PQ 2N7002DW

Delete Bat_EN

T_EN#

BAT

2 1

PD

PDZ5.6B

5

10

PR 100_4

129

133 *Short_4

PR

132 100_4

PR

PR 100_4

2 1

11

PD

PDZ5.6B

130

*47p/50V_4

TE

MP_MBAT

PR131 1M_4

MB

DATA [22]

MB

PC61

CLK [22]

VPCU

+3

TE

MP_MBAT [22]

D D

C C

AC

PRESENT[5]

SB_

B B

PJ

LHY-08D1-B-040/013-H-R

A A

PC

6

0.1u/25V_4

VA1

PC

62

0.1u/50V_6

PD

6

1N4148WS

recommend 200mA at least.

PR

24

*Short_6

+3VPCU

136

PR 10K_4

PR

149

10K_4

14

PR

316K_4

3

2

M#

24737_B

25

PQ *2N7002K

1

A-45W

UM

4

PR 20_1206

MB

DATA

CLK

MB

PR

138

*100K_4

PR 100K_4

PR

146

10K/F_4

19

PR *Short_4

16

0.01u/25V_4

12

PD P4SMAFJ20A

2 1

PR

18

63.4K_4

24737_A

CDET

24737_V

CC

PC

74

0.47u/25V_6

143

140

24737_BM#

MPOUT

24737_C

LIM

24737_I

24737_CMPIN

PR

148

100K_4

R2

63

PC

R1

IC

MNT[22]

R21 R148

100K51K

PC

0.1u/50V_6

PC

0.1u/50V_6

6

20

5

8

9

11

3

10

4

PR 51K_4

PQ AOL1413

1

3

PR

9

11

220K_4

1 6

2

PR

10

220K_4

3

80

AC

VC

AC

SD

SC

BM

CM

IL

IM

CM

21

DET

C

OK#

A

L

#

POUT

0.1u/50V_6

2

P AC

BQ24737RGRR

T

IOU

7

PC

72

100p/50V_4

3

75

PC

1

ACN

PU

8

D

GN

GND22GND24GN

21

23

25

24737_C

AC

_Protect[22]

PQ

IMD2AT108

24737_A

PC

0.1u/50V_6

HI

PH

LC

D

GN

PR

*0_4

MPOUT

5

4

7

CP

CN

81

16

GN

RE

17

BT

ST

18

DRV

19

ASE

15

DRV

14

PG

ND

13

P

SR

12

SR

N

17

22

PR *Short_4

VA2

27

52

4

24737_R

EGN

PR *Short_6

24737_B

ST

H

24737_D

24707_LX

24737_D

L

137 10_6

PR

135 7.5_6

PR

Ch

eck with HW side

.8V_S5

+1

PR

25

*100K_4

3

2

1

For BATT Only

SV1040

13

PR *Short_4

15

24737_S

24737_SRN

PQ 2N7002K

PD

9

1

2

PC 1u/16V_6

RP

9

3

57

8

PD RB500V-40

71

PC 47n/50V_6

AON7410

PC

0.1u/25V_4

56

PC

0.1u/25V_4

PC

0.1u/25V_4

H_

PROCHOT# [5,22,28,29]

PR

144

0.02/F_0612

1 2

D/

C# [22]

PQ

26

54

55

2

PQ

+V

IN

145

PR *Short_4

142

PR *Short_4

52

4

PQ28

AON7410

3

1

52

3

1

24737_A

59

PC

2200p/50V_6

6.8uH_7X7X3

9

PR *4.7_6

PC

7

*680p/50V_6

CN

PC

79

0.1u/50V_6

CP

+V

IN

PL

6

PR *Short_4

24737_S

58

PC

10u/25V_8

1 2

127

RP

RN

PC 2200p/50V_6

134

PR

0.01/F_0612

78

PR *Short_4

128

1

3

PR

141

33K/F_4

PQ

29

2N7002K

PC64

2200p/50V_6

8

AOL1413

2

4

PR 10K_4

3

1

PC53

10U/25V_8

52

139

BAT

-V

PC65

10U/25V_8

SRP󶁟󶁟󶁟󶁟SRN

4-Cells Others

bq24707A

bq24737

0󶁟󶁟󶁟󶁟010󶁟󶁟󶁟󶁟7.5

10󶁟󶁟󶁟󶁟7.5 10󶁟󶁟󶁟󶁟7.5

REGN MAX voltage 6.5V V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr =0.793V for 3.965A current limit

Pin10 ILIM=0.793V Rsr = 0.01ohm

anta Computer Inc.

Qu

PROJECT :

ze Document Number Rev

Si

arger(BQ24737RGRR)

Ch

Date: Sheet of

PROJECT :

Z8AD

24

1

24

2A

32Wednesday, April 08, 2015

33

5

4

3

2

1

IN

+3

VPCU

+

PC

120

220u/6.3V_6X4.2

VPCU

+3

3

2

1

C : 0.038A

TD PEAK : 0.05A Width : 20mil

34

PQ13 *AO3404

VSUS

+3

of

1A

110

PR *4.7_6

PC151

0.1u/50V_6

124

PR 22_8

PQ 2N7002K

PR 22_8

24

SY

PC

138

2200p/50V_6

235

2

S_SHDN#

+1

5V_ALWP

5V

+1

3

2N7002K

1

4

PR 1M_6

S_SHDN# [30]

SY

PR

215

*Short_6

+3

VPCU

S_HWPG[22]

SY

S_SHDN#

SY

227

PQ

V_S5

209

PR

*Short_4

*100K_4

N1

51225_E

H1

51225_D

51225_V

BST1

51225_S

W1

L1

51225_D

51225_F

B1

PR *Short_6

141

PC

0.1u/50V_6

4

MA

IND

42

228

PR

*Short_4

52

PQ

40

AON7410

4

3

1

PR

PC

136

1/F_6

2

1

2

1

PR *1M_6

S5D

4

PQ

AON7752

150

118

51

0.1u/50V_6

39

3

4

142

PC

0.1u/50V_6

VPCU

+5

52

3

1

MDV1528Q

+5

C : 3.38A

TD PEAK : 4.5A Width : 140mil

52

3

1

PD14 1PS302

13

PD 1PS302

PC

0.1u/50V_6

IN

+V

119

20

PQ

PC *2.2n/50V_4

VL 3V

210

PC129 10u/6.3V_6

7

PG

OOD

20

1

EN

16

H1

DRV

17

1

VBST

18

1

SW

15

L1

DRV

2

VF

B1

14

VO

1

19

CLK

51225_V

229

+5

VPCU

52

PQ

3

1

MDV1528Q

TDC : 3.6A PEAK : 4.8A Width : 160mil

3

13

VREG5

TPS51225RUKR

CS11CS2

VCLK

51225_CS151225_C

219 110K/F_4 PR

41

+5V

_LDO

PR

216

10K/F_4

PC

125

IN

PC126 0.1u/25V_4

51225_V

12

VIN

11

PU

5

26

S2

PR214 90.9K/F_4

MA

IND

PC128 4.7u/6.3V_6

3

EN

VREG3

DRV

VBST

SW

DRV

VF

GN

GND23GND24GND25GND

PR

108

*Short_6

+3

VPCU

52

4

3

TDC : 1.88A PEAK : 2.5A Width : 80mil

H2

L2

B2

2

D

1

6

S_SHDN#

SY

10

H2

51225_D

9

51225_V

8

51225_S

11

51225_D

4

51225_F

21

22

SU

PQ

12

MDV1528Q

PR

211

BST2

W2

1/F_6

L2

B2

1/13 Adding +3VSUS power for touch pad (By acer request)

SON[22,27]

+3V

2

*DTC144EU

PQ

PC

0.1u/50V_6

15

AON7410

124

AON7752

1 3

35

PQ

52

4

3

1

52

4

36

3

1

IN

+V

PR

113

*1M_6

PR114 *1M_6

2

2200p/50V_6

PL11

2.2uH_7X7X3

107

PR *4.7_6

PC

45

*680p/50V_6

+3

VSUS

PR

106

*22_8

3

2

PQ14 *2N7002K

1

Size Document Number Rev

Date: Sheet

PC

127

10u/25V_8

+3VPCU

3.3 Volt +/- 5% TDC : 5.5A PEAK : 7.2A OCP : 9A Width : 240mil

PR

212

6.81K/F_4

213

PR 10K/F_4

OC

P:9A

L(ripple current) =(9-3.3)*3.3/(2.2u*0.355M*9) ~2.676A Io

cp=9-(2.676/2)=7.662A Vth=4.108A*14.5mOhm+1mV=112.098mV R(Ilim)=(112.098mV*8)/10uA ~89.67K

5V

+1

PR

111

*1M_6

3

2

PQ16

*2N7002K

1

Qu

PROJECT :

EM 5V/3V (TPS51225)

SYST

We

dnesday, April 08, 2015 3225

+V

PC

121

0.1u/50V_6

IN

+V

PR

112

*1M_6

SU

SD

PC50 *2.2n/50V_4

anta Computer Inc.

1

MA

IND

D D

IN

+V

+5VPCU

VPCU

+5

C C

B B

A A

5 Volt +/- 5% TDC : 7A PEAK : 9.3A OCP : 11A Width : 280mil

PC

152

220u/6.3V_6X4.2

P:11A

OC

L(

ripple current) =(9-5)*5/(2.2u*0.3M*9) =3.367A

cp=11-(3.367/2)=9.316A

Io Vth=9.316A*14.5mOhm+1mV=136.082mV R(Ilim)=(136.082mV*8)/10uA =108.86K

S5

_ON[22 ,26,30]

5

+

2

PQ

DTC144EU

+

23

12

PC

0.1u/50V_6

PC

118

33U/25V_6X4.5

153

1 3

MA

PR

217

15.4K/F_4

218

PR 10K/F_4

IN

+V

PR 1M_6

IND [26,30]

121

PR 1M_6

123

PC

134

10u/25V_8

2.2uH_7X7X3

5V

+1

2

PL13

49

PC *680p/50V_6

V_S5

+5

3

1

5

4

3

2

1

+1.8V_S5

35

put Range: 1.8V~2V

In

Input Range : 2.7V~5.5V

77

D D

PC

ting 0.9A

Ra TDC : 0.413A

Rating 1A TDC : 0.525A

Rating 0.1A TDC : 0.45A

C C

Rating 900mA

Rating 0.4A TDC : 0.15A

B B

PC73

10u/6.3V_6

+1.24VS5

+1.15V

+1.5V_P

+1.8V_S5

+3VPCU

+3V_S5

PC76

10u/6.3V_6

+1.5V_P

1

11 PC

2

22u/6.3V_6

1

12 PC

2

22u/6.3V_6

1

82 PC

2

4.7u/10V_6

1

87 PC

2

2.2u/6.3V_6

1

90 PC

2

2.2u/6.3V_6

1

15 PC

2

2.2u/6.3V_6

1

16 PC

2

2.2u/6.3V_6

PU9 RT5041AGQW

7

IN

_1P2 4A

8

_1P1 5A

IN

9

_1P5 S

IN

5

1P24A

O_

6

1P15A

O_

Bu

ck 1

LDO

10

1P5S

O_

LX LX

14

IN_1P8A

SW

16

O_1P8A

SW

Switch

17

IN

_3P3 A

18

O_

3P3A

Buck 2

EN

SL

SU

SPWRDNACK

SL

D

ND

GN

12

ND

PG

15

29

_1P8

IN IN

_1P8

LX

_1P8 _1P8

LX

O_

1P8

IN

_1P0 5A _1P0 5A

IN

_1P05A _1P05A

1P05A

O_

VC

_1P05A

P_S0iX_B

P_S3_B

RSMRST

1 2

27 28

3

Input Range : 2.7V~5.5V

20 21

22 23

19

11

5041_VCC

C

26

25

24

4

13

66 PC

10u/10V_8

LX_1P8

PL7

1uH_7X7X3

93 PC

10u/10V_8

PL8

0.47uH_7X7x3

Input Range : 4.5V~5.5V

PR152 *short_4

1

PC83 1u/10V_4

2

PR151 *short_4

PR236 *short_4 PR150 *0_4

PR155 *0_4 PR154 *0_4

PR238 *short_4 PR20 *0_4 PR237 *0_4

PR156 *short_4

PR153 10K/F_4

68

67

PC

10u/10V_8

92

94

PC

10u/10V_8

+5VPCU

S5_ON

SLP_S0IX#

SUSPWRDANCK_EC

R580 100K_4

HWPG_1.05V_EC#

PMU_RSMRST#

10u/10V_8

MAINON

1

84 PC

2

1

89 PC

2

+3VPCU

1

13 PC

88 PC

22u/6.3V_6

+3VPCU

22u/6.3V_6

PC86

2

22u/6.3V_6

1

PC97

2

22u/6.3V_6

2

22u/6.3V_6

1

2

22u/6.3V_6

S5_ON [22,25,30]

MAINON [22,27,28,29, 30]

SLP_S0IX# [6,14]

PCH_SUSPWRDANCK [14,22] SUSPWRDANCK_EC [22]

HWPG_1.05V_EC# [22]

SLP_S3# [6,14]

PMU_RSMRST# [14]

1

2

1

2

12/29

ting 4.1A

Ra

Peak : 1.97A TDC : 1.48A

+1.8V_S5

1

PC14

PC85

2

22u/6.3V_6

Ra

ting 4.4A

ak : 5.4A

Pe TDC : 4.05A

+1.05V_S5

1

PC96

PC95

2

22u/6.3V_6

+1.8V_S5

+

PC91

330u/2.5V_6X4.2

+1.5V

PR23 *short_8

+3VPCU

MAIND[25,30]

MAIND+1.5V_P+1.5V

2

3

PQ11 AO3404

1

TD

C : 0.015A

+1.8V

PEAK : 0.02A Width : 20mil

A A

a Computer Inc.

Quant

PROJECT :

Size Document Number Rev

Custom

Date: Sheet of

5

4

3

Date: Sheet of

2

PROJECT :

PM

IC (RT5041AGQW)

a Computer Inc.

26 32Wednesday, April 08, 2015

1

A

1

2

3

4

5

36

+1.35VSUS[2,3,9,11] +V

DDQ_VTT[11] V_S5[17,25,28,29]

PC137 10U/6.3V_6

146

PC

0.22U/10V_4

51216S

51216P

51216T

51216M

+5

21

17

3

16

5

20

G

18

RIP

19

ODE

12

PC145

1U/6.3V_4

PU

12

3

T

VT

1

VT

TSNS

4

TGND

VT

7

GN

D

GN

5

VT

TREF

S3

S5

OOD

PG

TR

IP

DE

MO

V5

IN

APW8819AQAI

VDDQ

VL

DOIN

DRVH

VBST

DRVL

PG

SNS

VREF

REF

SW

ND

IN

+1.35VSUS

2

14

51216DRVH

15

51216V

13

51216S

11

51216D

10

9

51216V

6

+1

8

51216REFIN

PC

140

*10U/6.3V_6

BST

W

RVL

DDQSNS

.8VREF

PC

149

0.1U/16V_4

PC

148

0.01U/25V_4

PR

2.2_6

.35VSUS

PC144

0.1U/16V_4

+1

1.35 Volt +/- 5% TDC : 8.9A PEAK : 11.8A OCP : 14A Width : 360mil

+1

.35VSUS

+V

IN

PQ

AON7410

139

51216V

PR

234

10K/F_4

PR233

30.1K/F_4

BST_S

PC

0.1U/25V_4

PQ

AON7752

Rds(on)=14.5mohm

230

52

37

4

3

52

4

38

3

PC46

0.1U/25V_4

1

109

PR *2.2_6

48

PC

1

*2200P/50V_4

PC47

PC135

10u/25V_8

PC133

2200P/50V_4

12

PL

1uH_7X7X3

PR

*short_4

PC130

0.1U/25V_4

231

+

PC143

330u/2.5V_6X4.2

A A

VTT / 0.75A )

(

DDQ_VTT

+V

3

PR

SL

P_SUS#_PW[14]

221 *0_4

51216S

( VDDQ / 0.375A )

+V

B B

PC

220 *short_4

PR

*100K_4

PG_1.35V

PR

226 *short_4

PR

225

MA

INON[22,26,28,29,30]

SUSON[22,25]

C C

HW

*0.1u/16V_4

PC

*0.1u/16V_4

V

+3

DDQ[11]

132

131

PG_1.35V[2,22]

HW

PR232 100/J_4

147

PC

0.1U/16V_4

PR

224 *short_4

PR

222 147K/F_4

PR

223 200K/F_4

+5V_S5

Fsw = 400KHz

OCP=14A L ripple current =(19-1.35)*1.35/(1u*400k*19) =3.135A Vtrip=14-(3.135/2)*14.5mohm =180.269mV Rlimit=180.269mV/10uA*8=144.21Kohm

D D

1

DDR=1.35V PR104=10K/F_4 PR106=30.1K/F_4

2

Mode

Frequency Discharge mode

200K 400K Tracking Discharge

100K 300K Tracking Discharge

S3 S5

S0

S3 (mainon off)

S4/S5

1

0

1

ON

ON ON

OFF

3

ON

OFF OFF00

VTTREF+1.35VSUS

ON

OFF

Qu

anta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Wednesday, April 08, 2015 3227

Date: Sheet of

Wednesday, April 08, 2015 3227

Date: Sheet of

4

Wednesday, April 08, 2015 3227

PROJECT :

L (APW8819)

DDR3

1A

5

+1

D D

VC

ORE_PWRGD[22]

11/20 modify

G_PWRGD[22,29]

VG

SU

VR

H_

_SVID_CLK[6,29]

_SVID_ALERT#[6,29]

VR

_SVID_DATA[6,29]

MA

PROCHOT#[5,22,24,29]

168 *short_4

PR

164 *0_4

C C

+5

V_S5

+V

REF_VCORE

B B

A A

.05V_S5

52

54

PR

301_4

*200_4

187

PR

+3

V

10K_4

PR

182 *short_4

PR

5

100 *0_4

PR50 *0_4

PR

64.9K/F_4

PR

22.6K/F_4

PR

39.2K/F_4

PC

103

0.1U/16V_4

SB#[14,22,29]

INON[22,26,27,29,30]

Cl

53

PR 200_4

VR

_SVID_DATA ERT#_VCORE

AL

_SVID_CLK

VR

+1

.8V_S5

PR

163

13K/F_4

167

PR

300/F_4

PR

171

432/F_4

ace NTC close to

Pl Vcore Hot-Spot

55 PR

100K/F_4

V_S5

+5

ose to VR

19

PC

0.1U/16V_4

185 *short_4

PR

51

*75_4

PR

180 200_4

178 *short_4

PR

176 16.9/F_4

PR

172 *0_4

162

PR

22.1K_4

166

1.1K_4

170

13.7K_4

177

PR

6.49K/F_4

194 PR

100K/F_4_4250NTC

SET

38

PR

41

46

PR

49 PR

GND_VCORE

6.98K_4

_READY_VCORE

VR

20

PC

*0.1U/16V_4

VRON_VCORE

VR

VC

ERT#_VCORE

AL

VD

SET

39

PR

1K_4

SET2_VCORE

PR

42

20/F_4

SET

47

PR

221_4

TS

EN_VCORE

105 PC

HOT#_VCORE

LK_VCORE

IO_VCORE

GND_VCORE

1_VCORE

SET

GND_VCORE

SET

3_VCORE

SET

GND_VCORE

0.1U/16V_4

V_S5

+5

98 PC

2.2U/6.3V_6

17

VR_READY

26

EN

12

VR

15

VC

14

ALERT#

13

VD

30

SET

7

SET

8

SET2

9

SET

11

TSEN

18

DRV

181 PR

*short_4

PR

44 10K_4

SET

4

+5

V_S5

33

PR 22_6

HOT#

LK

IO

GND

1

3

_EN

DRV

24

GND_VCORE

4

C_VCORE VC

6

C VC

29

+5

PU

10

RT8171BGQW

OTSEL

VBO

PR

48

10K_4

V_S5

3

56

PR

2.2_6

21

C_VCORE

PVC

21

19

PC

2.2U/6.3V_6

186

PR

2.2_4

183

PR

C

16

NSET

TO

PVC

25

UG

ATE

22

BO

OT

23

PH

ASE

20

ATE

LG

32

NC

28

EN1P

IS

27

ISEN1N

31

IMON

1

VR

EF

4

VSEN

2

CO

MP

3

FB

5

RG

ND

D

ND

IAS IB

GN

PG

33

10

PR

173

100K/F_4

TO

N_VCORE

UG

ATE_VCORE

BO

OT_VCORE

PR

184 2.2/F_6

PH

ASE_CORE

LG

ATE_VCORE

IS

EN1P_VCORE

ISEN1N_VCORE

102

PC

*0.1U/16V_4

43

PR

5.11K_4

99 0.47u/6.3V_4

PC

MP_VCORE

CO

_VCORE

FB

D_VCORE

GN

866K/F_4

PC

0.1U/25V_4

175

PR

680/F_4

100

PC 100p/50V_4

36

PR 68K/F_4

108

PR

20/F_4

34

PR

158

*short_4

PC107

0.1U/25V_4

PC

106

*0.1U/16V_4

159

PR *short_4

29

PR *short_4

150_4

PR32

PQ

AON6978

3.57K_4

2

D1

G1

1

S1/D2

8

G2

S2

567

33

PR27

*short_4

30

PR

160

PR *short_4

3

9

PR *2.2_6

PC25 *2200P/50V_4

198

PR

10K/F_4_3435NTC

35

PR

*short_4

101

PC 390p/50V_4

161

PR 10K_4

23 PC

PH

ASE_CORE

72

110 PC

0.1U/25V_4

2200P/50V_4

PR *short_4

PR169

180/F_4

ose with

Cl VCORE Inductor

B=

3435

+V

REF_VCORE

PC

116

*0.1U/25V_4

165

109 PC

10u/25V_8

PL

9

0.33uH_7X7X3

1 2

3

4

PC104

0.47u/25V_6

174

PR

*160_4

+V

CC_CORE

22 PC

10u/25V_8

DCR=

PR *short_4

201

PR 100/F_4

PR

202 *short_4

PR

205 *short_4

PR

204

100/F_4

179

0.1U/16V_4

3.9mOhm

119

PC

2

IN

+V

12

+

115

PC

22u/6.3V_8

VC VC

Parallel

2

PC111

33U/25V_6x4.5

117

PC

22u/6.3V_8

C1_SENSEP [8] C1_SENSEN [8]

+V

CC_CORE

PC

330u/2V_7343

1

37

12.1

VR

+

112

swell - VCC0+1 (1 Phase)

Bra

Icc TDC PL2󶁪TBD

c Max󶁪7A

Ic

OCP󶁪12.4A

w󶁪800KHz

Fs

Vboot󶁪1V

address󶁪0

VR

VCC0+1 L/L󶁪󶁪󶁪󶁪

R_DC_LL󶁪0 mV/A

R_AC_LL󶁪0 mV/A

Qu

anta Computer Inc.

PROJECT :

Si

ze Document Number Rev

Size Document Number Rev

We

Date: Sheet

dnesday, April 08, 2015 28 32

Date: Sheet

dnesday, April 08, 2015 28 32

Date: Sheet

dnesday, April 08, 2015 28 32

PROJECT :

V

CC0+1 (RT8171BGQW)

1

of

2A

5

4

3

2

1

V_S5

+1

.05V_S5

D D

V

+3

VGG_PWRGD[22,28]

11/19 modify

SU

SB#[14,22,2 8]

MA

INON[22,26,27,28,30]

C C

+VREF_VGG

B B

A A

H_

PROCHOT#[5,22,24,28]

VR

_SVID_CLK[6,28]

VR_SVID_ALERT#[6,28]

_SVID_DATA[6,28]

VR

PR

V_S5

+5

73 *short_4

66 *0_4

PR

84

PR 301/F_4

5

87

PR *200_4

98

PR

10K/F_4

PR

96 *0_4

99 *short_4

PR

64.9K/F_4

13.7K/F_4

976/F_4

29

PC

0.1U/16V_4

91

PR 200/F_4

VR_SVID_DATA

ERT#_VGG

AL

_SVID_CLK

VR

+1.8V_S5

67

PR

18.2K/F_4

PR

74

274/F_4

76

PR

1/F_4

Place NTC close to Vcore Hot-Spot

206 PR

100K/F_4

V_S5

+5

Close to VR

33

PC

0.1U/16V_4

95 *short_4

PR

79

*75_4

PR92 200/F _4

88 *short_4

PR

85 16.9/F _4

PR196

*0_4

68

22.1K/F_4

75

1.1K/F_4

77

402/F_4

PR

199

6.49K/F_4

208 PR

100K/F_4_4250NTC

SETGND_VGG

PR

PR191

PR

189

193

197 PR

*0.1U/16V_4

6.98K/F_4

VR

PC

34

VR

VC

AL

VD

SET

PR

2.43K/F_4

SET

PR190

64.9/F_4

SET3_VGG

PR

16/F_4

TS

_READY_VGG

ON_VGG

HOT#_VGG

LK_VGG

ERT#_VGG

IO_VGG

GND_VGG

1_VGG

188

SET

2_VGG

SET

192

SET

EN_VGG

113 PC

0.1U/16V_4

+5V_S5

GND_VGG

+5

PR

59

22_6

27 PC

1U/6.3V_4

17

_READY

VR

26

EN

12

HOT#

VR

15

VC

LK

14

AL

ERT#

13

VD

IO

30

GND

SET

7

1

SET

8

SET

2

9

3

SET

11

EN

TS

18

_EN

DRV

_EN

DRV

200 PR

24

*short_4

PR

81

10K/F_4

GND_VGG

SET

4

CC_VGG +V

6

C VC

29

+5

PU7

RT8171BGQW

OTSEL

VBO

PR195 10K/F_4

V_S5

PR

203

2.2_6

IN

+V

39 PC

VCC_VGG +P

21

19

C

PVC

ND

PG

TONSET

UG

ATE

BO

ASE

PH

ATE

LG

IS

EN1P

EN1N

IS

IM

VR

VSEN

CO

RG

D

GN

33

OT

NC

ON

EF

MP

FB

ND

IAS IB

10

100K/F_4

2.2U/6.3V_6

PR

16

25

22

23

20

32

28

27

31

1

4

2

3

5

PR

80

887K/F_4

TO

N_VGG

UG

ATE_VGG

BOOT_VGG

PR102 2.2 /F_6

PH

ASE_VGG

LGATE_VGG

ISEN1P_VGG

IS

EN1N_VGG

PC

30

*0.1U/16V_4

PR

78

2.26K/F_4

PC28 0.47u/6.3 V_4

CO

PC

MP_VGG

68p/50V_4

FB

_VGG

GND_VGG

103

0.1U/25V_4

PR

93

680/F_4

26

PR61 68K/F_4

40

PC

PR

70

200/F_4

PR *short_4

105

PR

2.2_4

PC42

1U/25V_4

0.

PC32

*0.1U/16V_4

64

PR *short_4

PR60 *short_4

69

PQ

AON6978

63

PR

649/F_4

3

1

8

34

PR62

2.1K/F_4

G1

S1/D2

G2

2

D1

S2

71

PR

301/F_4

PR

58

*short_4

D1

9

S2

567

10K/F_4_3435NTC

PR65

619/F_4

PC 390p/50V_4

PR57 10K/F_4

PR *2.2_6

PC *2200P/50V_ 4

PR

24

207

122 PC

ASE_VGG

PH

104

41

2200P/50V_4

43 PC

PC44

0.1U/25V_4

0.33uH_7X7X3

1 2

PR

83

*short_4

82

PR

180/F_4

ose with

Cl VCORE Inductor

B=3435

+V

REF_VGG

PC

35

*0.1U/25V_4

10u/25V_8

3

PL

10

+VGG

4

0.47u/25V_6

123 PC

10u/25V_8

DCR=

31

PC

89

PR

*160_4

PR

101

100/F_4

PR

97 *short_4

PR

94 *short_4

PR

90

100/F_4

3.9mOhm

PR

86

*short_4

38

PC

0.1U/16V_4

2

36

PC

22u/6.3V_8

VGG_SENSEP [8]

G_SENSEN [8]

VG

Parallel

37

PC

22u/6.3V_8

+V

GG

+

114

PC

330u/2V_7343

12.1

VR

swell - VGG (1 Phase)

Bra

Icc TDC PL2󶁪TBD

c Max󶁪15A

Ic

OCP󶁪20.7A

Fsw󶁪800KHz

Address󶁪5

VR

VCORE L/L󶁪󶁪󶁪󶁪

R_DC_LL󶁪0 mV/A

R_AC_LL󶁪0 mV/A

Qu

anta Computer Inc.

PROJECT :

ze Document Nu mber Rev

Size Document Nu mber Rev

Si

Date: Sheet

Wednesday, April 08, 2015 29 32

Date: Sheet

Wednesday, April 08, 2015 29 32

Date: Sheet

Wednesday, April 08, 2015 29 32

PROJECT :

GG (RT8171BGQW)

+V

1

38

of

2A

5

4

3

2

1

39

IN

+V

D D

7

PD DA2J10100L

PR

26

1M_6

2

1

31

PQ AO3409

2

_ON

S5

_ON[22,25,26]

C C

Thermal Protection

(1

) Need fine tune

for thermal protect point

S5

30

PQ

DTC144EUA

VLVL

1 3

3

28

PR *0/short_6

S_SHDN# [25]

SY

(2) Note placement position

+V

IN

MA

B B

MA

INON[22,2 6,27,28,29]

2

PR *100K_6

19

PQ DTC144EU

1 3

122

117

PR 1M_4

INON_ON_G

120

PR 1M_4

+3

V

PR 22_8

3

2

1

115

PQ

17

2N7002K

+5

2

+1

V

3

1

125

PR 220_8

PQ

22

2N7002K

.8V

116

PR 22_8

3

2

PQ

18

2N7002K

1

+1

5V

126

PR 1M_4

MA

IND

3

2

PQ

21

2N7002K

1

52

PC *2200p/50V_4

MA

IND [25,26]

2

S5

_ON

10K/F_4_3435NTC

3

PQ

10

2N7002K

1

PR

157

1.5K_4

2.

469V

PR 200K_4

45

84

3

+

2

-

5

+

6

-

40

PR

PR37

200K_4

PC

0.1U/50V_6

1

PU

6A

AS393MTR-E1

7

PU6B AS393MTR-E1

17

31

PR 200K_6

PC

0.1U/50V_6

3

2

18

32

PQ 2N7002K

1

For EC control thermal protection (output 3.3V)

A A

Qu

anta Computer Inc.

PROJECT :

Size Document Number Rev

We

Date: Sheet

dnesday, April 08, 2015 3230

Date: Sheet

dnesday, April 08, 2015 3230

Date: Sheet

5

4

3

2

dnesday, April 08, 2015 3230

PROJECT :

mal / Discharge

Ther

1A

of

1

of

5

4

3

2

1

Bay Trail-M S4/S5 to S0 (Power Up) Sequence

24

D D

C C

B B

A A

anta Computer Inc.

Qu

PROJECT :

Si

ze Document Number Rev

We

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

5

4

3

2

dnesday, April 08, 2015

PROJECT :

Power sequence

Z8AD

1A

of

3231

of

3231

of

1

3231

5

Ve

rsion

Mo

del

Z8AD

BBBB

12/25

page 6: change GPIO_SUS7 net connect to SOC_KCB_SMI net & add R429

page 6: change GPIO_SUS7 net connect to SOC_KCB_SMI net & add R429 12/25

12/25

page 6: change GPIO_SUS7 net connect to SOC_KCB_SMI net & add R429 page 6: change GPIO_SUS7 net connect to SOC_KCB_SMI net & add R429

12/25

page 12: change U13 pin34 connect to GND & Del PCIERST# net

page 12: change U13 pin34 connect to GND & Del PCIERST# netpage 12: change U13 pin34 connect to GND & Del PCIERST# net

page 14: add Q54 & R22

page 14: add Q54 & R22page 14: add Q54 & R22

page 19: Del PCIERST# net & change C214 connect +3VPCU & IOAC_WLANPWR# & Q25 pin2 connect +3V_Mini1_VDD

page 19: Del PCIERST# net & change C214 connect +3VPCU & IOAC_WLANPWR# & Q25 pin2 connect +3V_Mini1_VDD page 19: Del PCIERST# net & change C214 connect +3VPCU & IOAC_WLANPWR# & Q25 pin2 connect +3V_Mini1_VDD

page 20: Del PCIERST# net

page 20: Del PCIERST# netpage 20: Del PCIERST# net

page 31: add MAINON net & PR236

page 31: add MAINON net & PR236page 31: add MAINON net & PR236

12/29

12/29 page 6: add R581 connect to GND & R585, PMU_WIFI_SUSCLK_R net

page 6: add R581 connect to GND & R585, PMU_WIFI_SUSCLK_R net

12/2912/29

page 6: add R581 connect to GND & R585, PMU_WIFI_SUSCLK_R netpage 6: add R581 connect to GND & R585, PMU_WIFI_SUSCLK_R net

page 14: add Q54 for Touch screen & U13 circuit for Intel WIFI card

page 14: add Q54 for Touch screen & U13 circuit for Intel WIFI cardpage 14: add Q54 for Touch screen & U13 circuit for Intel WIFI card

page 19: add WIFI_SUSCLK net & R584

page 19: add WIFI_SUSCLK net & R584page 19: add WIFI_SUSCLK net & R584

page 26: add SLP_S3# net & PR237 & PR238 &MAINON net

page 26: add SLP_S3# net & PR237 & PR238 &MAINON net page 26: add SLP_S3# net & PR237 & PR238 &MAINON net

page 6: Move SOC_KCB_SMI to SATA_GP1(pin AG3)

1/06

page 6: Move SOC_KCB_SMI to SATA_GP1(pin AG3) page 6: Move SOC_KCB_SMI to SATA_GP1(pin AG3)

1/06 1/06

page 14: add R591

D D

C C

page 14: add R591page 14: add R591

page 15:add R588,R587,C594,RR586

page 15:add R588,R587,C594,RR586page 15:add R588,R587,C594,RR586

page 16: Del Q55,R579

page 16: Del Q55,R579page 16: Del Q55,R579

page 21: DelD29 & add Q55,R592,R589,R590

page 21: DelD29 & add Q55,R592,R589,R590page 21: DelD29 & add Q55,R592,R589,R590

1/06

1/06 page 3: Del R533

page 3: Del R533

1/06 1/06

page 3: Del R533page 3: Del R533

page 14: Del R591

page 14: Del R591page 14: Del R591

page 8: Del R499,R488 & addC595,C596

page 8: Del R499,R488 & addC595,C596page 8: Del R499,R488 & addC595,C596

page 21: Del R592

page 21: Del R592page 21: Del R592

CCCC

page 6: add board ID 0 & R600,R601

page 6: add board ID 0 & R600,R601page 6: add board ID 0 & R600,R601

12/25

page 22: add R602 ,R598 & R599 &Del R109

page 22: add R602 ,R598 & R599 &Del R109page 22: add R602 ,R598 & R599 &Del R109

3/2

3/2 page 5: add ODD circuit ODD_PRSNT# connect to SATA_LED# (U34D AH3) & Add SSD ID at pin AF3 (SATA_GP3) ,Add R810,R811

page 5: add ODD circuit ODD_PRSNT# connect to SATA_LED# (U34D AH3) & Add SSD ID at pin AF3 (SATA_GP3) ,Add R810,R811

3/23/2

page 5: add ODD circuit ODD_PRSNT# connect to SATA_LED# (U34D AH3) & Add SSD ID at pin AF3 (SATA_GP3) ,Add R810,R811page 5: add ODD circuit ODD_PRSNT# connect to SATA_LED# (U34D AH3) & Add SSD ID at pin AF3 (SATA_GP3) ,Add R810,R811

page 22: add R813

page 22: add R813page 22: add R813

page 16: add R812,C693 &ODD_PRSNT# net ,SSD ID net

page 16: add R812,C693 &ODD_PRSNT# net ,SSD ID netpage 16: add R812,C693 &ODD_PRSNT# net ,SSD ID net

page 22: add R814

page 22: add R814page 22: add R814

page 6: Del R585 & Add TP 24

page 6: Del R585 & Add TP 24page 6: Del R585 & Add TP 24

page 14: Del U27,R583,R582,C593

page 14: Del U27,R583,R582,C593page 14: Del U27,R583,R582,C593

page 19: Del R584 & Add TP 47

page 19: Del R584 & Add TP 47page 19: Del R584 & Add TP 47

page 13: Add R818,R819,R820,C698,C699,C700

page 13: Add R818,R819,R820,C698,C699,C700page 13: Add R818,R819,R820,C698,C699,C700

page 16: Add R815,R816,R817,C696,C697,C701,C702

page 16: Add R815,R816,R817,C696,C697,C701,C702page 16: Add R815,R816,R817,C696,C697,C701,C702

page 19: Add R821,R822,,C694,C695

page 19: Add R821,R822,,C694,C695page 19: Add R821,R822,,C694,C695

4

CHANGE LIST

3

2

1

B B

A A

PROJECT MODEL

DO

C NO.

:

PART NUMBER: DRAWING BY: REVISON:

5

APPROVED BY:

4

TE:

DA

3

2

Quanta Computer Inc.

PROJECT :

Z8AD

PROJECT :

Z8AD

PROJECT :

Size Document Number Rev

ange list

Ch

We

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Date: Sheet

dnesday, April 08, 2015

Z8AD

of

32

1

32

3A