Acer E5-574 Schematics
5
4
3
2
1
D D
C C
Cardre ader
CONN. 2 in 1
P28
I/O boa rd
B B
Zoro_SL (ZRW) SKL ULT SYSTEM BLOCK DIAGRAM
DDR3L-SO DIMM CHA
P12
DDR3L-SO DIMM CHB
P13
SATA - H DD
SATA OD D
RTS51 70
(cardre ader)
CCD(Cam era)
Touch Screen
Blue To oth
I/O Boa rd Con n.USB2 IO* 1
P25
P25
P28
P21
P21
P26
P28
Dual C hann el DD R III
1066/1333 /1600 MHZ
SATA0
SATA1
USB2-8
USB2-7
USB2-6
USB2-5
USB2-4
P6
BATTER Y
Azalia
SKY LAKE ULT 15W
MCP 1356pins
IMC
DC+GT3e
42 mm X 24 mm
SATA
Integrated PCH
USB2.0
DMIC_CL K0
DMIC_DA TA0
RTC
IHDA
P2~P10
LPC
PCI-E x4
TX/RX
CLK
eDP
USB3.0/2 .0
CLK
PCI-E x1
CLK
I2C_0
SPI
DP
PCIE1-4
EDP
DDI2
DDI1
USB3-1 & USB3-2
USB2-1 & USB2-2
X'TAL
32.768KHz
X'TAL 24MHz
SPI ROM
8M+4M
GPU
N16S-GT
N16V-GM
P7
P14~P1 9
ITE6516
PS8201
X'TAL 27MHz
P20
P22
PCIE-6
PCIE-5
VRAM
DDR3
P18~P1 9
eDP Conn.
VGA C onn.
HDM I Conn.
P21
P21
P22
USB3 Port MB s ide
CN13 -> USB3 port 2 ( up )
CN16 -> USB3 port 1 ( down )
MINI CAR D
WLAN+BT
RTL81 11H
10/100/ 1G
P26
P23
X'TAL 25MHz
IV@ : iGPU
EV@ : Optimus
GT@ : N16S-GT / GC6
GM@ : N16V-GM / W O GC6
DR@ : For Dual Rank ( VRAM 8 pcs)
KBL@ : Keyboard backlight
TPM@ : TPM
TPM_N@: For TPM 2.0
TPM_l@ : For TPM 1.2
8M@ : 8M FLASH ROM
4M@ : 4M FLASH ROM
GS@ :G-SENSOR
TDI@ : TOUCH PAD I2C
TSU@ : TOUCH SCREEN USB
TSI@ : TOUCH SCREEN I2C
GT3@ : GT3 CPU
NAC@ : Non IOAC
IOAC@ : For IOAC
P28
RJ45
P23
BOM
K/B
BL
Con.
EC
IT8987
P27
Touch PAD
P27
HALL
SENSOR
3
P17
P29
Fan Driv er
(Fan sig nal)
TPM(option)
P27
P25
2
BQ24780RUY R
Batery Charge r
TPS51 225
+3V/+5V
RT823 7CZQW
+1V_S5
NB681 GD-Z
+VCCOPC/+VC CEOPIO
G5316R Z1D
+1.35VSUS
P30
MDV1 528Q
+5V_S5/+3V_S5/+3 V/+5V
P31
ISL9585 9HRT Z-T
+VCORE/VCC SA/VCCGT
P32
P33
Therm al Prote ction
P35
Discharger
UP165 8RQKF
+VGPU_CORE
P31
RT806 8AZQW
P38
+1.05V_GFX/+3V _GFX
+1.5V_GFX
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJEC T :
PROJEC T :
PROJEC T :
P7
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Block Dia gram
Block Dia gram
Block Dia gram
1
P40
ZRW
ZRW
ZRW
P41
P42
1 48Monday, July 20, 2015
1 48Monday, July 20, 2015
1 48Monday, July 20, 2015
3A
3A
3A
D-MIC
Int. D-MIC
P24
Universal HP
A A
5
ALC255
AUDIO CODEC
P24 P24
P24
Speaker*2
LED
4
P27
K/B Con .
P27
5
4
3
2
1
Skylake ULT (DISPLAY,eDP)
AT16
AU16
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
H66
H65
SKL_ULT
DDI
DISPLAY SIDEBANDS
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
U35D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
CPU MISC
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
SKL_ULT/BG A
REV = 1
1 OF 20
SKL_ULT
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
EDP
4 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
C47
EDP_TXN0
C46
EDP_TXP0
D46
EDP_TXN1
C45
EDP_TXP1
A45
B45
A47
B47
E45
EDP_AUXN
F45
EDP_AUXP
B52
G50
F50
E48
CRT_AUX#_C
F48
CRT_AUX_C
G46
F46
L9
INT_HDMI_HPD
L7
CRT_HPD
L6
R567 *short_4
N9
R571 *short_4
L10
EDP_HPD
R12
PCH_BLON
R11
PCH_BRIGHT
U13
PCH_VDDEN
?
B61
XDP_TCK0
D60
XDP_TDI_CPU
A61
XDP_TDO_CP U
C60
XDP_TMS _CPU
B59
XDP_TRST#
B56
XDP_TCK1
D59
XDP_TDI
A56
PCH _JTAG_ TDO
C59
XDP_TMS
C61
A59
PCH_TRST#
PCH_JTAGX
EDP_TXN0 (21)
EDP_TXP0 (21)
EDP_TXN1 (21)
EDP_TXP1 (21)
EDP_AUXN (21)
EDP_AUXP (21)
R546 *0_4
R553 *0_4
C671 *short_4
C670 *short_4
Rev:D change to sho rtpad
R539 *short_4
R549 *short_4
R517 *short_4
Rev:D change to sho rtpad
?
XDP_TDO
R795 0_4
XDP_TDI
R796 0_4
If use In tel DCI USB 3.0 f ixture need to s hort
1. XDP_TDO <--> XDP_TDO_CPU
2. XDP_TDI <--> XDP_TDI_CP U
3. XDP_TM S <--> XDP_TM S_CPU
R797 0_4
PCH_BRIGHTDP_UTIL
CRT_AUXN (20)
CRT_AUXP (20)
INT_HDMI_HPD (22)
CRT_HPD (20)
KBSMI# (29)
EC_SCI# (29)
EDP_HPD (21)
PCH_BLON (21)
PCH_BRIGHT (21)
EDP_VDD_E N ( 21)
XDP_TDO
XDP_TRST#
XDP_TCK0
XDP_TDO_CP U
XDP_TDI_CPU
XDP_TMS _CPUXDP_TMS
Rev:F add
eDP Panel
PCH JTAG
TCK,TMS
Trace Leng th < 9000mils
H_PWRGOO D (50ohm)
Trace Leng th: 1~11.25 inche s
CRT_AUXN
CRT_AUXP
CRT_CLK
CRT_DATA
KBSMI#
EC_SCI#
CRT_HPD
EDP_HPD
100k pull- down on PC H si de
JTAG_TC K,JTAG_TMS
Trace L ength < 9000mils
R533 *100K_4
R532 *100K_4
R577 2.2K_4
R152 2.2K_4
R780 20K/F_4
R781 20K/F_4
Rev:D add
R564 100K_4
R563 100K_4
Change to +1V_VCCST 11/6
XDP_TDO_CP U
XDP_TMS
XDP_TDI
PCH _JTAG_ TDO
PCH_JTAGX
XDP_TRST#
XDP_TCK0
XDP_TCK1
PCH_TRST#
2/16
,XDP_TC K1,XDP_TMS
don't nee d pull up or pul l down
5/29 XDP_ TCK0 R558 Stuf f
R559 51_4
R514 51_4
R515 51_4
R538 51_4
R513 *1K_4
R535 *51_4
R558 51_4
R537 *51_4
R534 51_4
D D
HDMICRT
+VCCIO
C C
+1V_VCCST
CPU_THRMTR IP#
R5291K_4
CATERR#
Rev:E St uff only f or C2 build Debug
Ramp will r emove
+VCCIO
R465 1K_4
B B
R78849.9/F_4
H_PROCHOT#
H_PROCHOT#(29,30,36)
Avoid 125M hz
BPM#[0: 7]
Trace Leng th 1~6 inches
Length m atch < 300 mi ls
H_PECI (50 ohm)
Route on m icrostrip onl y
Spacing >1 8 mils
Trace Leng th: 0.4~6.125 ich es
SM_RCO MP[0:2]
Trace leng th < 500 mils
Trace widt h = 12~15 mils
Trace spac ing = 20 mils
INT_HDMITX2N(22)
INT_HDMITX2P(22)
INT_HDMITX1N(22)
INT_HDMITX1P(22)
INT_HDMITX0N(22)
INT_HDMITX0P(22)
INT_HDMICLK-(22)
INT_HDMICLK+(22)
CRT_TXN0(20)
CRT_TXP0(20)
CRT_TXN1(20)
ITE FAE sugge st CAP
should be at PCH si de.
HDMI_DDCCLK_ SW(22)
HDMI_DDCDAT A_SW(22)
CRT_TXP1(20)
PCH_ODD_EN( 25)
eDP_RC OMP
Trace le ngth < 100 mils
Trace w idth = 20 mils
Trace s pacing = 25 mils
H_PECI(29)
THRMTRIP#
DGPU_PW_C TRL#(4)
HDMI_DDCCLK_ SW
HDMI_DDCDAT A_SW
CRT_CLK
CRT_DATA
EDP_RCOM P
R15424.9/F_4
TP65
R531 499/F_4
R530 100/F_4
TP89
TP90
TP64
TP62
U35A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKL_ULT/BG A
REV = 1
CATERR#
H_PECI
H_PROCHOT#_ RH_PROCHOT#
CPU_THRMTR IP#
XDP_BPM #0
XDP_BPM #1
XDP_BPM #2
XDP_BPM #3
DGPU_PW_C TRL#
R635 49.9/F_4
R646 49.9/F_4
R158 49.9/F_4
R162 49.9/F_4
+3V
+3V
MP remo ve(Intel)
+1V_VCCST
+1V_VCCST
+1V_VCCST
2
R488
*1K_4
1 3
Q5 MMB T3904-7-F
3
Q31
FDV301N
1
R74
1K_4
2
SYS_SHDN # (31, 40)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, July 2 0, 2015
Date: Sheet of
Monday, July 2 0, 2015
Date: Sheet of
3
2
Monday, July 2 0, 2015
PROJECT :
Skylake 1/4 (D DI/eDP)
Skylake 1/4 (D DI/eDP)
Skylake 1/4 (D DI/eDP)
ZRW
ZRW
ZRW
3A
3A
2 48
2 48
2 48
1
3A
CPU thermal trip
+1V_VCCST
U33
NC1VCC
A A
IMVP_PW RGD( 36)
2
A
GND3Y
74AUP1G07GW
5
R478 *0_4
5
C628
0.1u/16V_4
4
+3V
12
R485
10K_4
IMVP_PW RGD_3V (8)
IMVP_PW RGD_3V
THRMTRIP#
4
5
4
3
2
1
Change Data an d DQS to inte rleave.
?
D D
C C
B B
M_A_DQ 0(12)
M_A_DQ 1(12)
M_A_DQ 2(12)
M_A_DQ 3(12)
M_A_DQ 4(12)
M_A_DQ 5(12)
M_A_DQ 6(12)
M_A_DQ 7(12)
M_A_DQ 8(12)
M_A_DQ 9(12)
M_A_DQ 10(12)
M_A_DQ 11(12)
M_A_DQ 12(12)
M_A_DQ 13(12)
M_A_DQ 14(12)
M_A_DQ 15(12)
M_A_DQ 16(12)
M_A_DQ 17(12)
M_A_DQ 18(12)
M_A_DQ 19(12)
M_A_DQ 20(12)
M_A_DQ 21(12)
M_A_DQ 22(12)
M_A_DQ 23(12)
M_A_DQ 24(12)
M_A_DQ 25(12)
M_A_DQ 26(12)
M_A_DQ 27(12)
M_A_DQ 28(12)
M_A_DQ 29(12)
M_A_DQ 30(12)
M_A_DQ 31(12)
M_A_DQ 32(12)
M_A_DQ 33(12)
M_A_DQ 34(12)
M_A_DQ 35(12)
M_A_DQ 36(12)
M_A_DQ 37(12)
M_A_DQ 38(12)
M_A_DQ 39(12)
M_A_DQ 40(12)
M_A_DQ 41(12)
M_A_DQ 42(12)
M_A_DQ 43(12)
M_A_DQ 44(12)
M_A_DQ 45(12)
M_A_DQ 46(12)
M_A_DQ 47(12)
M_A_DQ 48(12)
M_A_DQ 49(12)
M_A_DQ 50(12)
M_A_DQ 51(12)
M_A_DQ 52(12)
M_A_DQ 53(12)
M_A_DQ 54(12)
M_A_DQ 55(12)
M_A_DQ 56(12)
M_A_DQ 57(12)
M_A_DQ 58(12)
M_A_DQ 59(12)
M_A_DQ 60(12)
M_A_DQ 61(12)
M_A_DQ 62(12)
M_A_DQ 63(12)
M_A_DQ 0
M_A_DQ 1
M_A_DQ 2
M_A_DQ 3
M_A_DQ 4
M_A_DQ 5
M_A_DQ 6
M_A_DQ 7
M_A_DQ 8
M_A_DQ 9
M_A_DQ 10
M_A_DQ 11
M_A_DQ 12
M_A_DQ 13
M_A_DQ 14
M_A_DQ 15
M_A_DQ 16
M_A_DQ 17
M_A_DQ 18
M_A_DQ 19
M_A_DQ 20
M_A_DQ 21
M_A_DQ 22
M_A_DQ 23
M_A_DQ 24
M_A_DQ 25
M_A_DQ 26
M_A_DQ 27
M_A_DQ 28
M_A_DQ 29
M_A_DQ 30
M_A_DQ 31
M_A_DQ 32
M_A_DQ 33
M_A_DQ 34
M_A_DQ 35
M_A_DQ 36
M_A_DQ 37
M_A_DQ 38
M_A_DQ 39
M_A_DQ 40
M_A_DQ 41
M_A_DQ 42
M_A_DQ 43
M_A_DQ 44
M_A_DQ 45
M_A_DQ 46
M_A_DQ 47
M_A_DQ 48
M_A_DQ 49
M_A_DQ 50
M_A_DQ 51
M_A_DQ 52
M_A_DQ 53
M_A_DQ 54
M_A_DQ 55
M_A_DQ 56
M_A_DQ 57
M_A_DQ 58
M_A_DQ 59
M_A_DQ 60
M_A_DQ 61
M_A_DQ 62
M_A_DQ 63
U35B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
SKL_ULT/B GA
REV = 1
SKL_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR CH - A
2 OF 20
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26
AW50
AT52
AY67
AY68
BA67
AW67
?
M_A_OD T0
M_A_OD T1
M_A_A5
M_A_A9
M_A_A6
M_A_A8
M_A_A7
M_A_A12
M_A_A11
M_A_A15
M_A_A14
M_A_A13
M_A_A2
M_A_A10
M_A_A1
M_A_A0
M_A_A3
M_A_A4
M_A_DQ S#0
M_A_DQ S0
M_A_DQ S#1
M_A_DQ S1
M_A_DQ S#2
M_A_DQ S2
M_A_DQ S#3
M_A_DQ S3
M_A_DQ S#4
M_A_DQ S4
M_A_DQ S#5
M_A_DQ S5
M_A_DQ S#6
M_A_DQ S6
M_A_DQ S#7
M_A_DQ S7
DDR0_AL ERT#
TP_DDR0_ PARITY#
+VREF_C A_CPU
+VREFDQ _SA_M3
+VREFDQ _SB_M3
DDR_VTT_C TRL
R621 *10K_4
M_A_CL K0# (12)
M_A_CL K0 (12)
M_A_CL K1# (12)
M_A_CL K1 (12)
M_A_CKE 0 (12)
M_A_CKE 1 (12)
M_A_CS# 0 (12)
M_A_CS# 1 (12)
M_A_OD T0_DIMM (12)
M_A_OD T1_DIMM (12)
M_A_BS# 2 (12)
M_A_CAS # (12)
M_A_W E# (12)
M_A_RAS # (12)
M_A_BS# 0 (12)
M_A_BS# 1 (12)
M_A_DQ S#0 (12)
M_A_DQ S0 (12)
M_A_DQ S#1 (12)
M_A_DQ S1 (12)
M_A_DQ S#2 (12)
M_A_DQ S2 (12)
M_A_DQ S#3 (12)
M_A_DQ S3 (12)
M_A_DQ S#4 (12)
M_A_DQ S4 (12)
M_A_DQ S#5 (12)
M_A_DQ S5 (12)
M_A_DQ S#6 (12)
M_A_DQ S6 (12)
M_A_DQ S#7 (12)
M_A_DQ S7 (12)
TP21
+1.35VSU S
2
1 3
Q35
*DTC144EU
+3V_S5
R682
*100K_4
M_B_DQ 0(13)
M_B_DQ 1(13)
M_B_DQ 2(13)
M_B_DQ 3(13)
M_B_DQ 4(13)
M_B_DQ 5(13)
M_B_DQ 6(13)
M_B_DQ 7(13)
M_B_DQ 8(13)
M_B_DQ 9(13)
M_B_DQ 10(13)
M_B_DQ 11(13)
M_B_DQ 12(13)
M_B_DQ 13(13)
M_B_DQ 14(13)
M_B_DQ 15(13)
M_B_DQ 16(13)
M_B_DQ 17(13)
M_B_DQ 18(13)
M_B_DQ 19(13)
M_B_DQ 20(13)
M_B_DQ 21(13)
M_B_DQ 22(13)
M_B_DQ 23(13)
M_B_DQ 24(13)
M_B_DQ 25(13)
M_B_DQ 26(13)
M_B_DQ 27(13)
M_B_DQ 28(13)
M_B_DQ 29(13)
M_B_DQ 30(13)
M_B_DQ 31(13)
M_B_DQ 32(13)
M_B_DQ 33(13)
M_B_DQ 34(13)
M_B_DQ 35(13)
M_B_DQ 36(13)
M_B_DQ 37(13)
M_B_DQ 38(13)
M_B_DQ 39(13)
M_B_DQ 40(13)
M_B_DQ 41(13)
M_B_DQ 42(13)
M_B_DQ 43(13)
M_B_DQ 44(13)
M_B_DQ 45(13)
M_B_DQ 46(13)
M_B_DQ 47(13)
M_B_DQ 48(13)
M_B_DQ 49(13)
M_B_DQ 50(13)
M_B_DQ 51(13)
M_B_DQ 52(13)
M_B_DQ 53(13)
M_B_DQ 54(13)
M_B_DQ 55(13)
M_B_DQ 56(13)
M_B_DQ 57(13)
M_B_DQ 58(13)
M_B_DQ 59(13)
M_B_DQ 60(13)
M_B_DQ 61(13)
M_B_DQ 62(13)
M_B_DQ 63(13)
DDR_VTTT_ PG_CTRL (35 )
M_B_DQ 0
M_B_DQ 1
M_B_DQ 2
M_B_DQ 3
M_B_DQ 4
M_B_DQ 5
M_B_DQ 6
M_B_DQ 7
M_B_DQ 8
M_B_DQ 9
M_B_DQ 10
M_B_DQ 11
M_B_DQ 12
M_B_DQ 13
M_B_DQ 14
M_B_DQ 15
M_B_DQ 16
M_B_DQ 17
M_B_DQ 18
M_B_DQ 19
M_B_DQ 20
M_B_DQ 21
M_B_DQ 22
M_B_DQ 23
M_B_DQ 24
M_B_DQ 25
M_B_DQ 26
M_B_DQ 27
M_B_DQ 28
M_B_DQ 29
M_B_DQ 30
M_B_DQ 31
M_B_DQ 32
M_B_DQ 33
M_B_DQ 34
M_B_DQ 35
M_B_DQ 36
M_B_DQ 37
M_B_DQ 38
M_B_DQ 39
M_B_DQ 40
M_B_DQ 41
M_B_DQ 42
M_B_DQ 43
M_B_DQ 44
M_B_DQ 45
M_B_DQ 46
M_B_DQ 47
M_B_DQ 48
M_B_DQ 49
M_B_DQ 50
M_B_DQ 51
M_B_DQ 52
M_B_DQ 53
M_B_DQ 54
M_B_DQ 55
M_B_DQ 56
M_B_DQ 57
M_B_DQ 58
M_B_DQ 59
M_B_DQ 60
M_B_DQ 61
M_B_DQ 62
M_B_DQ 63
AF65
AF64
AK65
AK64
AF66
AF67
AK67
AK66
AF70
AF68
AH71
AH68
AF71
AF69
AH70
AH69
AT66
AU66
AP65
AN65
AN66
AP66
AT65
AU65
AT61
AU61
AP60
AN60
AN61
AP61
AT60
AU60
AU40
AT40
AT37
AU37
AR40
AP40
AP37
AR37
AT33
AU33
AU30
AT30
AR33
AP33
AR30
AP30
AU27
AT27
AT25
AU25
AP27
AN27
AN25
AP25
AT22
AU22
AU21
AT21
AN22
AP22
AP21
AN21
Stuff Q54 for both UMA and GPU in DDR_VTT_CNTL
SKL ULT (DDR3L)SKL ULT (DDR3L)
U35C
DDR1_DQ[0]/DDR0_DQ[16]
DDR1_DQ[1]/DDR0_DQ[17]
DDR1_DQ[2]/DDR0_DQ[18]
DDR1_DQ[3]/DDR0_DQ[19]
DDR1_DQ[4]/DDR0_DQ[20]
DDR1_DQ[5]/DDR0_DQ[21]
DDR1_DQ[6]/DDR0_DQ[22]
DDR1_DQ[7]/DDR0_DQ[23]
DDR1_DQ[8]/DDR0_DQ[24]
DDR1_DQ[9]/DDR0_DQ[25]
DDR1_DQ[10]/DDR0_DQ[26]
DDR1_DQ[11]/DDR0_DQ[27]
DDR1_DQ[12]/DDR0_DQ[28]
DDR1_DQ[13]/DDR0_DQ[29]
DDR1_DQ[14]/DDR0_DQ[30]
DDR1_DQ[15]/DDR0_DQ[31]
DDR1_DQ[16]/DDR0_DQ[48]
DDR1_DQ[17]/DDR0_DQ[49]
DDR1_DQ[18]/DDR0_DQ[50]
DDR1_DQ[19]/DDR0_DQ[51]
DDR1_DQ[20]/DDR0_DQ[52]
DDR1_DQ[21]/DDR0_DQ[53]
DDR1_DQ[22]/DDR0_DQ[54]
DDR1_DQ[23]/DDR0_DQ[55]
DDR1_DQ[24]/DDR0_DQ[56]
DDR1_DQ[25]/DDR0_DQ[57]
DDR1_DQ[26]/DDR0_DQ[58]
DDR1_DQ[27]/DDR0_DQ[59]
DDR1_DQ[28]/DDR0_DQ[60]
DDR1_DQ[29]/DDR0_DQ[61]
DDR1_DQ[30]/DDR0_DQ[62]
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_DQ[32]/DDR1_DQ[16]
DDR1_DQ[33]/DDR1_DQ[17]
DDR1_DQ[34]/DDR1_DQ[18]
DDR1_DQ[35]/DDR1_DQ[19]
DDR1_DQ[36]/DDR1_DQ[20]
DDR1_DQ[37]/DDR1_DQ[21]
DDR1_DQ[38]/DDR1_DQ[22]
DDR1_DQ[39]/DDR1_DQ[23]
DDR1_DQ[40]/DDR1_DQ[24]
DDR1_DQ[41]/DDR1_DQ[25]
DDR1_DQ[42]/DDR1_DQ[26]
DDR1_DQ[43]/DDR1_DQ[27]
DDR1_DQ[44]/DDR1_DQ[28]
DDR1_DQ[45]/DDR1_DQ[29]
DDR1_DQ[46]/DDR1_DQ[30]
DDR1_DQ[47]/DDR1_DQ[31]
DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]
DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]
DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]
DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]
SKL_ULT/B GA
REV = 1
M_A_A[1 5:0]
DDR0_AL ERT#
DDR1_AL ERT#
?
SKL_ULT
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR CH - B
3 OF 20
M_A_A[1 5:0] (12 )
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
DDR1_PAR
?
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
M_B_OD T0
M_B_OD T1
M_B_A5
M_B_A9
M_B_A6
M_B_A8
M_B_A7
M_B_A12
M_B_A11
M_B_A15
M_B_A14
M_B_A13
M_B_A2
M_B_A10
M_B_A1
M_B_A0
M_B_A3
M_B_A4
M_B_DQ S#0
M_B_DQ S0
M_B_DQ S#1
M_B_DQ S1
M_B_DQ S#2
M_B_DQ S2
M_B_DQ S#3
M_B_DQ S3
M_B_DQ S#4
M_B_DQ S4
M_B_DQ S#5
M_B_DQ S5
M_B_DQ S#6
M_B_DQ S6
M_B_DQ S#7
M_B_DQ S7
DDR1_AL ERT#
TP_DDR1_ PARITY#
CPU_DRAM RST#
SM_RCO MP_0
SM_RCO MP_1
SM_RCO MP_2
M_B_A[1 5:0]
M_B_CL K0# (13)
M_B_CL K1# (13)
M_B_CL K0 (13)
M_B_CL K1 (13)
M_B_CKE 0 (13)
M_B_CKE 1 (13)
M_B_CS# 0 (13)
M_B_CS# 1 (13)
M_B_OD T0_DIMM (13)
M_B_OD T1_DIMM (13)
M_B_BS# 2 (13)
M_B_CAS # (13)
M_B_W E# (13)
M_B_RAS # (13)
M_B_BS# 0 (13)
M_B_BS# 1 (13)
M_B_DQ S#0 (13)
M_B_DQ S0 (13)
M_B_DQ S#1 (13)
M_B_DQ S1 (13)
M_B_DQ S#2 (13)
M_B_DQ S2 (13)
M_B_DQ S#3 (13)
M_B_DQ S3 (13)
M_B_DQ S#4 (13)
M_B_DQ S4 (13)
M_B_DQ S#5 (13)
M_B_DQ S5 (13)
M_B_DQ S#6 (13)
M_B_DQ S6 (13)
M_B_DQ S#7 (13)
M_B_DQ S7 (13)
TP18
M_B_A[1 5:0] (1 3)
DRAMRST
+1.35VSU S
A A
CPU DRAM
CPU_DRAM RST#
5
4
3
12
R679
470_4
R670 *short_4
12
C750
*0.1u/16 V_4
2
DDR3_DR AMRST# ( 12,13)
SM_RCO MP_0
SM_RCO MP_1
SM_RCO MP_2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet of
Monday, July 2 0, 2015
Date: Sheet of
Monday, July 2 0, 2015
Date: Sheet of
Monday, July 2 0, 2015
PROJECT :
Skylake 2/3 (DDR3 I/F)
Skylake 2/3 (DDR3 I/F)
Skylake 2/3 (DDR3 I/F)
R685120/ F_4
R67880.6 /F_4
R681100/ F_4
ZRW
ZRW
ZRW
3A
3A
3 48
3 48
1
3 48
3A
5
4
3
2
1
SKL ULT (SIDEBAND ) GPIO
H_PECI (50ohm)
Route on microstrip only
Spacing >18 mils
Trace Length: 0.4~6.125 iches
H_PWRGOOD (50ohm)
Touch PAD
Touch Screen
R196* IV@10K_4
R256*100K_4
R199*10K_4
UMA boot
GPU boot
+3V
Trace Length: 1~11.25 inches
UART2 fo r RMT
HDA
PCH_AZ_C ODEC_SYNC(24)
PCH_AZ_C ODEC_BITCLK(24)
PCH_AZ_C ODEC_SDOUT(24)
PCH_AZ_C ODEC_SDIN0(24)
PCH_AZ_C ODEC_RST#(24)
Reserve con nect to DMIC (acer request 1 /14)
SPKR
R624 *20K_4
D D
+3V_S5
I2C0_SDA
R1672.2K_4
I2C0_SCL
R1662.2K_4
I2C1_SDA
R165*2.2K_4
I2C1_SCL
R169*2.2K_4
PU 2.2K for t ouch p ad I2C bus(4 00 KHz )
+3V
+3V
DGPU_PW_CTRL#
C C
high
low
DGPU_PW_ CTRL#(2)
R127 EV@100K_4
GPU Con trol PU/PD
R220*EV@ 10K_4
R257*10K_4
R204*10K_ 4
20131015 For GC6 N V DG GC6 _FB_EN PD .1A-1
R208 10K_4
UMA Only
GPU power i s control by PCH
GPIO (Discr ete, SG or Optimize)
DGPU_PW_ CTRL#
VGPU_EN
DGPU_PWR _EN
GC6_FB_EN
DGPU_HOL D_RST#
DGPU_PWR OK
R115 IV@ 1K_4
DGPU_PWROK PD on GPU side
Setup
DGPU_PW_CTRL#
UMA Only
SG/Optimise
VGA H/W
Menu
Signal
UMA
1
0
Hidden
Hidden
GPU
545659- 103
Add GPU P ower Control Sigan ls
Touch PAD
Touch Screen
DMIC_CL K0_L(24)
DMIC_DA TA0_L(24)
DGPU_HOL D_RST#(14)
DGPU_PWR _EN(42)
DGPU_PWR OK(16)
GC6_FB_EN(15,17 )
DGPU_EVEN T#(17)
ODD_PRSN T#(25)
C742 *10p/ 50V_4
R667 33_4
R644 33_4
R645 33_4
R660 33_4R110 *10K_4
C739
*10p/50V_4
R769 *33_4
R770 *33_4
VGPU_EN(41)
ACCEL_IN TA(27)
TP_INT_PC H(21)
I2C0_SDA(27)
I2C0_SCL(27)
I2C1_SDA(21)
I2C1_SCL(21)
Strappin g
SPKR(24)
TPD_INT #_D
UART2_RX D
UART2_TX D
UART2_RT S#
UART2_CT S#
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
HDA_SYNC _R
HDA_BCLK_ R
HDA_SDO_R
HDA_RST# _R
DMIC_CL K0_R
DMIC_DA TA0_R
SPKR
GSPI0_MOSI
GSPI1_MOSI
Skylake-U Strapping Table
Pin Nam e Strap de scription
GPP_B14 (SPKR)
B B
GPP_B18
(GSPI0_M OSI)
GPP_C2
(SMBALERT #)
GPP_B22
(GSPI1_M OSI)
GPP_C5
(SML0ALE RT#)
SPI0_MO SI
SPI0_MIS O
GPP_B23
(SML1ALE RT#
/PCHHOT #)
SPI0_IO2
A A
SPI0_IO3
HDA_SDO /
I2S_TXD 0
GPP_E19
(DDPB_CT RLDATA)
GPP_E21
(DDPC_CT RLDATA)
Top-Block Swap ov erride PCH_PWROK
No reboot PCH_PW ROK
TLS Conf identiality
Boot BIO S Strap B it (BBS)
eSPI or LP C
Reserved
Reserved
Reserved
Reserved
Reserved
Flash Descriptor Security
Override / Intel ME Debug Mode
Display Po rt B Detec ted
Display Po rt C Detec ted
5
Sampled
RSMRST#
PCH_PW ROK
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
PCH_PW ROK
PCH_PW ROK
PCH_PW ROK
Configura tion note
0 = *Disab le Top Swap (iPD 20K)
1 = Enabl e Top Swap Mode
0 = *Disab le No Reboot (i PD 20K)
1 = Enabl e No Reboot Mode
0 = *Disab le Intel ME Cryp to TL S(iPD 20K)
1 = Enabl e Intel M E Cryp to TLS
0 = *SPI (iPD 20K)
1 = LPC
0 = *LPC is selecte d for EC (iPD 20K)
1 = eSPI selected f or EC
+3V
+3V
+3V_S5
+3V
+3V_S5
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
(iPD 20K)
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
0 = *Ena ble securi ty in the Flash
Descriptio n (iPD 20K)
1 = Disabl e Flash Descriptor Sec urity (Overrid e)
0 = *Port B is no t detected (iPD 20 K)
1 =Port B is detected
0 = *Port C is no t detected (iPD 20 K)
1 =Port C is detected
4
R625 *1K_4
R619 *1K_4
R160 *10K_4
R207 *1K_4
change loca tion to near CPU t o prevent impact HDA_SDO signa l
HDA_SDO_R
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
W4
AB3
AD1
AD2
AD3
AD4
U7
U6
U8
U9
AH9
AH10
AH11
AH12
AF11
AF12
BA22
AY22
BB22
BA21
AY21
AW22
J5
AY20
AW20
AK7
AK6
AK9
AK10
H5
D7
D8
C8
AW5
R586 *1K_4
R737 1K_4
U35F
LPSS ISH
GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C9/UART0_T XD
GPP_C10/UART0_RT S#
GPP_C11/UART0_CT S#
GPP_C20/UART2_RXD
GPP_C21/UART2_T XD
GPP_C22/UART2_RT S#
GPP_C23/UART2_CT S#
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
SKL_ULT/BG A
REV = 1
U35G
AUDIO
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1
+3V_S5
GPP_B14/SPKR
SKL_ULT/BG A
REV = 1
SPKR
GSPI0_MOSI
GSPI1_MOSI
3
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+3V_S5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
ME_WR# (29)
SKL_ULT
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
SKL_ULT
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
7 OF 20
SMBALERT# (7)
SML0ALERT # (7)
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+1.8V_S 5
+1.8V_S 5
GPP_D13/ISH_UART0_RXD/SML0BDAT A/I2C4B_SDA
GPP_D14/ISH_UART0_T XD/SML0BCLK/I2C4B_SCL
GPP_D16/ISH_UART0_CT S#/SML0BALERT#
GPP_C14/UART1_RT S#/ISH_UART1_RTS#
GPP_C15/UART1_CT S#/ISH_UART1_CTS#
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
6 OF 20
SDIO/SDXC
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
GPP_A17/SD_PWR_EN #/ISH_GP7
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D15/ISH_UART0_RT S#
GPP_C12/UART1_RXD/ISH_UAR T1_RXD
GPP_C13/UART1_T XD/ISH_UART1_TXD
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
GPP_A12/BM_BUSY#/ISH_GP6
SD_RCOMP
GPP_F23
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_W P
GPP_A16/SD_1P8_SEL
+1.8V_S 5
?
GPP_D9
GPP_D10
GPP_D11
GPP_D12
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
?
R174200/F_4
Touch pad INT
2
Reserve UART FFC connector for Win 7 debu g
UART2_RX D
R275 *49.9K/F_4
UART2_TX D
R280 *49.9K/F_4
UART2_RT S#
R283 *49.9K/F_4
UART2_CT S#
R290 *49.9K/F_4
+5V
CN3
UART2_RX D
UART2_TX D
UART2_RT S#
UART2_CT S#
TPD_INT #_D
S5 S5
TPD_INT #(27,29)
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Monday, J uly 20, 2015
Date: Sheet of
Monday, J uly 20, 2015
Date: Sheet of
Monday, J uly 20, 2015
1
2
3
7
4 8
5
6
*UART F unction
+3V_S5
R177TDI@10 0K_4
+3V
2
1
Skyla ke 6/7 (PEG /DMI/FDI)
Skyla ke 6/7 (PEG /DMI/FDI)
Skyla ke 6/7 (PEG /DMI/FDI)
3
Q20
TDI@2N 7002K
R164 *0_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJEC T :
PROJEC T :
PROJEC T :
1
+3V_S5
TPD_INT #_D
ZRW
ZRW
ZRW
4 48
4 48
4 48
3A
3A
3A
5
Backside cap
C184
1U/6.3V_2
C243
22u/6.3V_6
C233
22u/6.3V_6
C226
22u/6.3V_6
C203
22u/6.3V_6
C219
22u/6.3V_6
C224
22u/6.3V_6
C236
22u/6.3V_6
Backside cap
C214
C245
C676
1U/6.3V_2
1U/6.3V_2
D D
C282
C272
C273
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
10u/6.3V_4
C289
22u/6.3V_6
10u/6.3V_4
Backside cap
C259
10u/6.3V_4
C189
1U/6.3V_2
C647
10u/6.3V_4
C252
1U/6.3V_2
C651
10u/6.3V_4
Backside cap
C212
C196
1U/6.3V_2
1U/6.3V_2
C181
C228
1U/6.3V_2
1U/6.3V_2
+VCCEOPIO
C708
GT3@10u/6.3V_4
+1.8V_PRIM
GT3@10u/6.3V_4
C C
B B
A A
C687
R565
C709
GT3@10u/6.3V_4
Backside cap
C686
GT3@10u/6.3V_4
GT3@0_6
5
Backside cap
+1.8V_PRIM+1.8V_S5
C201
1U/6.3V_2
Backside cap
C269
1U/6.3V_2
For 2+3e C PU
For 2+3e C PU
C186
10u/6.3V_4
C197
1U/6.3V_2
C262
1U/6.3V_2
C237
1U/6.3V_2
C185
10u/6.3V_4
C194
1U/6.3V_2
C215
1U/6.3V_2
C209
1U/6.3V_2
C682
GT3@10u/6.3V_4
C155
10u/6.3V_4
C193
1U/6.3V_2
+1.35VSUS
Backside cap
+1V_SUS
C227
C246
1U/6.3V_2
1U/6.3V_2
C285
1U/6.3V_2
Backside cap
C688
GT3@1U/6.3V_2
Backside cap
C158
C232
10u/6.3V_4
10u/6.3V_4
Backside cap
C241
C188
1U/6.3V_2
1U/6.3V_2
C318
10u/6.3V_4
C326
10u/6.3V_4
R194 *short_4
1 2
Rev:F chang e to Shortpad
+VCCIO
Rev:F chang e to Shortpad
+1V_SUS
Rev:F chang e to Shortpad
4
C255
C251
22u/6.3V_6
22u/6.3V_6
C657
C257
10u/6.3V_4
10u/6.3V_4
C235
C222
1U/6.3V_2
1U/6.3V_2
C200
1U/6.3V_2
100 ohm near CPU
1.0V_CPU 3A
C681
C684
GT3@1U/6.3V_2
GT3@1U/6.3V_2
For 2+3e C PU
C218
10u/6.3V_4
C240
1U/6.3V_2
Backside cap
C313
C328
1U/6.3V_2
10u/6.3V_4
Primary side cap
C323
10u/6.3V_4
+VDDQC
C299
1U/6.3V_2
R550 *short_6
Primary side cap
R135 *short_6
R112 *short_6
4
+VCCCORE
+1.8V_PRIM
+VCCOPC
+VCCOPC_SRC(33)
681_AGND(33)
For 2+3e C PU
+VCCOPC_SRC
681_AGND
+VCCOPC
C685
C683
GT3@1U/6.3V_2
GT3@1U/6.3V_2
C161
C151
10u/6.3V_4
10u/6.3V_4
C198
C239
1U/6.3V_2
1U/6.3V_2
100 ohm N ear CPU
VCCGT_SENSE(36)
VSSGT_SENSE(36)
C311
C308
1U/6.3V_2
1U/6.3V_2
C325
C327
10u/6.3V_4
10u/6.3V_4
+1V_VCCST
C286
10u/6.3V_4
C677
1U/6.3V_4
Backside cap
Primary side cap
+VCCOPC
For 2+3e C PU
+1.8V_PRIM
R172 GT3@100/F_4
R176 GT3@100/F_4
C689
GT3@1U/6.3V_2
+VCCGT
C223
10u/6.3V_4
C204
1U/6.3V_2
C205
1U/6.3V_2
R155
100/F_4
R161
100/F_4
C312
1U/6.3V_2
+VCCSTG
C176
1U/6.3V_4
TP12
TP20
R634 GT3@0_4
R636 GT3@0_4
+VCCEOPIO
R633 GT3@0_4
R632 GT3@0_4
C148
10u/6.3V_4
C206
1U/6.3V_2
C195
1U/6.3V_2
+VCCGT
+1.35VSUS
+VCCPLL
C172
1U/6.3V_4
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
AK32
AB62
AC63
AE63
AE62
AG62
AL63
AJ62
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
AL23
A30
A34
A39
A44
G30
K32
P62
V62
H63
G61
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
REV = 1
A18
A22
K20
K21
U35L
VCC_A30
S0
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD_K32
RSVD_AK3 2
VCCOPC_AB 62
VCCOPC_P6 2
VCCOPC_V6 2
VCC_OPC_1 P8_H63
VCC_OPC_1 P8_G61
VCCOPC_SE NSE
VSSOPC_S ENSE
VCCEOPIO
S0
VCCEOPIO
VCCEOPIO_SE NSE
VSSEOPIO_S ENSE
SKL_ULT/BGA
REV = 1
SKL_ULT
U35M
CPU POWER 2 OF 4
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
S0
VCCGT
0.55~1.5V
VCCGT
VCCGT
VCCGT
VCCGT
2+3e peak 6A
VCCGT
2+3e TPY 4A
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENS E
SKL_ULT/BGA
U35N
SKL_ULT
CPU POWER 3 OF 4
S3
DDR3L
VDDQ_AU23
VDDQ_AU28
1.35V
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51
VDDQC
VCCST
S3
1.0V
VCCSTG_A22
S0
VCCPLL_OC
S0
1.0V
VCCPLL_K 20
VCCPLL_K 21
S3
120mA
1.0V
SKL_ULT/BGA
3
?
SKL_ULT
CPU POWER 1 OF 4
VCC
0.55V~1.5V
2+2 peak 24A
2+2 TPY 17A
2+3e peak 24A
2+3e TPY 17A
1.0V
S0
Sx
1.8V
GT3 CPU
1.0V
?
VCCGT
S0
0.55~1.5V
2+2 peak 31A
2+2 TPY 15A
2+3e peak 56A
2+3e TPY 17A
VCCGTX
2+2 X
13 OF 20
?
S0
0.85V/0.95V
2A
S0
1.15V
2+2 peak 5A
2+2 TPY 4A
2+3e peak 5.1A
2+3e TPY 5A
120mA
40mA
1.0V
260mA
14 OF 20
3
3A
50mA
3A
12 OF 20
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENS E
VSSGTX_SEN SE
VCCIO
3.0A
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENS E
VSSSA_S ENSE
VCCSA_SE NSE
REV = 1
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENS E
VSS_SEN SE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
?
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
?
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
?
+VCCGT
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
R109 100/F_4
R122 100/F_4
100 ohm near CPU
+VCCCORE
R98 100/F_4
C174
1U/6.3V_4
C199
47u/6.3V_8
C693
22u/6.3V_6
C692
22u/6.3V_6
+VCCGT
C303
GT3@22u/6.3V_6
C291
GT3@10u/6.3V_4
TP86
TP87
TP17
TP14
VSASS_SENSE (36)
VSA_SENSE (36)
+VCCSA
C666
47u/6.3V_8
C679
10u/6.3V_4C258
+VCCCORE
R96 100/F_4
+VCCSTG
C190
47u/6.3V_8
C705
22u/6.3V_6
C704
22u/6.3V_6
E3A C202 c hange to 47u/6.3v_ 6
C310
GT3@22u/6.3V_6
For 2+3e C PU
C279
GT3@10u/6.3V_4
+VCCIO
C284
10u/6.3V_4
C701
1U/6.3V_4
+VCCSA
C254
10u/6.3V_4
C207
1U/6.3V_2
C114
10u/6.3V_4
2
Primary side cap
C144
47u/6.3V_8
C650
47u/6.3V_8
C645
47u/6.3V_8
Primary side cap
C674
10u/6.3V_4
VCORE_SENSE (36)
VCORESS_SENSE (36)
H_CPU_SVIDART#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
C664
10u/6.3V_4
C667
10u/6.3V_4
100 ohm Ne ar CPU
Primary side cap
C702
47u/6.3V_8
Primary side cap
C706
22u/6.3V_6
C171
22u/6.3V_6
C178
22u/6.3V_6
Primary side cap
C202
47u/6.3V_6
C694
22u/6.3V_6
C691
22u/6.3V_6
Primary side cap
C302
GT3@22u/6.3V_6
C307
GT3@22u/6.3V_6
C277
22u/6.3V_6
REV:F Stuff C 277,C274,C27 5
Backside cap
C324
C281
GT3@10u/6.3V_4
GT3@10u/6.3V_4
C316
GT3@10u/6.3V_4
Backside cap
C266
C283
10u/6.3V_4
1U/6.3V_2
Primary side cap
C700
C710
1U/6.3V_4
1U/6.3V_4
Backside cap
C247
C238
10u/6.3V_4
10u/6.3V_4
Backside cap
C216
C278
1U/6.3V_2
1U/6.3V_2
Primary side cap
C641
C643
10u/6.3V_4
10u/6.3V_4
2
C690
47u/6.3V_8
C659
47u/6.3V_8
C673
10u/6.3V_4
C707
22u/6.3V_6
C703
22u/6.3V_6
C274
22u/6.3V_6
C280
GT3@10u/6.3V_4
Imax 3(A)
C297
1U/6.3V_2
C711
1U/6.3V_4
C229
10u/6.3V_4
C242
1U/6.3V_2
C165
10u/6.3V_4
C150
47u/6.3V_8
C663
C675
10u/6.3V_4
10u/6.3V_4
+1V_VCCST
SVID
R138
100/F_4
H_CPU_SVIDDAT
Place PU re sistor
close to CPU
Place PU re sistor
close to CPU
H_CPU_SVIDART#
R552 220_4
H_CPU_SVIDCLK
C697
C248
47u/6.3V_8
47u/6.3V_8
C210
47u/6.3V_6
E3A C210 c hange to 47u/6.3v_ 6
C275
C276
22u/6.3V_6
GT3@22u/6.3V_6
C317
C290
GT3@10u/6.3V_4
GT3@10u/6.3V_4
C264
C298
1U/6.3V_2
1U/6.3V_2
C263
C221
10u/6.3V_4
10u/6.3V_4
C267
C260
1U/6.3V_2
1U/6.3V_2
C642
C157
10u/6.3V_4
10u/6.3V_4
1
C678
10u/6.3V_4
Layout note: need routing to gether
and ALERT need betw een CLK and DATA.
C814
1000P/50V_4
+1V_VCCST
C696
47u/6.3V_8
C288
10u/6.3V_4
C249
1U/6.3V_2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
C816
C815
*1000P/50V_4
*1000P/50V_4
REV:F add 1000p
R134
54.9/F_4
Skylake 12 /13/14 (POW ER)
Skylake 12 /13/14 (POW ER)
Skylake 12 /13/14 (POW ER)
Monday, July 20, 2015
Monday, July 20, 2015
Monday, July 20, 2015
C818
C817
*1000P/50V_4
*1000P/50V_4
H_CPU_SVIDDAT (36)
VR_SVID_ALERT#_VCORE (36)
H_CPU_SVIDCLK (36)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
ZRW
ZRW
ZRW
C819
*1000P/50V_4
5 48
5 48
5 48
3A
3A
3A
5
4
3
2
1
Skylake ULT (GPU, SATA , ODD, CLK ,USB2&3)
?
U35H
PCIE/USB3/SATA
PEG_RX#0(14 )
PEG_RX0(14)
D D
dGPU P EG*4
LAN
WIFI
C C
B B
PEG_TX#0(14)
PEG_TX0(14)
PEG_RX#1(14 )
PEG_RX1(14)
PEG_TX#1(14)
PEG_TX1(14)
PEG_RX#2(14 )
PEG_RX2(14)
PEG_TX#2(14)
PEG_TX2(14)
PEG_RX#3(14 )
PEG_RX3(14)
PEG_TX#3(14)
PEG_TX3(14)
PCIE_RX5-_ LAN(23)
PCIE_RX5+ _LAN(23)
PCIE_TX5-_ LAN(23 )
PCIE_TX5+ _LAN(23)
PCIE_RX6-_ WLAN(26)
PCIE_RX6+ _WLAN(26)
PCIE_TX6-_ WLAN(26)
PCIE_TX6+ _WLAN(26)
CLK_PCIE_V GA#(14)
CLK_PCIE_V GA(1 4)
CLK_PEGA_R EQ#(14)
N16S VGALANWLA N
CLK_PCIE_L ANN(23)
CLK_PCIE_L ANP(23)
CLK_PCIE_L AN_REQ#(23)
CLK_PCIE_W LANN(26)
CLK_PCIE_W LANP(26)
PCIE_CLKR EQ_WLAN#(26)
HDD
ODD
C653 EV@0.22u/1 0V_4
C652 EV@0.22u/1 0V_4
C656 EV@0.22u/1 0V_4
C655 EV@0.22u/1 0V_4
C661 EV@0.22u/1 0V_4
C662 EV@0.22u/1 0V_4
C654 EV@0.22u/1 0V_4
C660 EV@0.22u/1 0V_4
C668 0.1u/16V_4
C669 0.1u/16V_4
C648 0.1u/16V_4
C649 0.1u/16V_4
SATA_RXN0(25)
SATA_RXP0(25)
SATA_TXN0(25)
SATA_TXP0(25)
SATA_RXN1(25)
SATA_RXP1(25)
SATA_TXN1(25)
SATA_TXP1(25)
R562 100/F_4
R235
R229
R224
TP22
TP25
TP73
*short_4
*short_4
*short_4
XDP_PRDY#
XDP_PREQ#
PIRQA#
TP91
TP92
CLK_PCIE_R EQ0#
CLK_PCIE_R EQ1#
CLK_PCIE_R EQ2#
CLK_PCIE_R EQ3#
CLK_PCIE_R EQ4#
CLK_PCIE_R EQ5#
Rev:D change to shortpad
A A
CLK_PCIE_R EQ0#
CLK_PCIE_R EQ1#
CLK_PCIE_R EQ2#
CLK_PCIE_R EQ3#
CLK_PCIE_R EQ4#
CLK_PCIE_R EQ5#
5
R234 10K_4
R215 10K_4
R227 10K_4
R618 10K_4
R228 10K_4
R223 10K_4
+3V
C_PEG_TX#0
C_PEG_TX0
C_PEG_TX#1
C_PEG_TX1
C_PEG_TX#2
C_PEG_TX2
C_PEG_TX#3
C_PEG_TX3
PCIE_TX5PCIE_TX5+
PCIE_TX6PCIE_TX6+
PCIE_RCO MPN
PCIE_RCO MPP
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKL_ULT/BG A
REV = 1
U35J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKL_ULT/BG A
REV = 1
+3V_S5
4
SKL_ULT
SSIC / USB3
USB2
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
+3V_S5
GPP_E2/SATAXPCIE2/SATAGP2
+3V_S5
+3V_S5
8 OF 20
?
SKL_ULT
CLOCK SIGNALS
+3V_S5
CLKOUT_ITPXDP_N
+3V_S5
+3V_S5
+3V_S5
+3V_S5
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_OUT
XCLK_BIASREF
+3V_S5
+3V_S5
10 OF 20
Rev:D add for EC res et RTC
EC_RTCR ST(29)
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E8/SATALED#
?
F43
E43
BA17
E37
XTAL24_IN
SRTCRST#
RTCRST#
XTAL24_IN
E35
XTAL24_OUT
E42
XCLK_BIASR EF
AM18
RTC_X1
RTCX1
AM20
RTC_X2
RTCX2
AN18
SRTC_RST #
AM16
RTC_RST #
?
3
2
R786
1
100K_4
Rev:E Reser ve only Rev:E Reser ve only
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
CLK_PCIE_X DPN
CLK_PCIE_X DPP
SUSCLK
SRTC_RST #
PQ6059
*2N7002K
USB3_RXN0 (28)
USB3_RXP0 (28)
USB3_TXN0 (28)
USB3_TXP0 (28)
USB3_RXN1 (28)
USB3_RXP1 (28)
USB3_TXN1 (28)
USB3_TXP1 (28)
USBP0- (2 8)
USBP0+ ( 28)
USBP1- (2 8)
USBP1+ ( 28)
USBP3- (2 8)
USBP3+ ( 28)
USBP4- (2 6)
USBP4+ ( 26)
USBP5- (2 1)
USBP5+ ( 21)
USBP6- (2 1)
USBP6+ ( 21)
USBP7- (2 8)
USBP7+ ( 28)
USBCOMP
R178 113/F_4
USB2_ID
R587 1K_4
R778 1K_4
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
SATA_DEVSL P0
SATA_DEVSL P1
SATA_DEVSL P2
SATAGP0
SATAGP1
SATAGP2
TP93
TP94
SUSCLK (26)
R512 2.7K/F_4
R768 *60.4/F_4
RTC_RST # (11)
1V pow er plane
0.71 checklist p14
3
1A-1
USB_OC0# (28)
USB_OC1# (28)
USB_OC2# (28)
DEVSLP0 (25)
EC_RTCR ST
MB USB3. 0 CN16 ( Charger IC ) Do wn
MB USB3. 0 CN13 - > Up
MB USB3. 0 CN16 ( Charger IC ) Do wn
MB USB3. 0 CN13 - > Up
DB USB2.0
BT
Touch Screen
CCD
Card reader
USBCOMP
Impedan ce = 50 ohm
Trace leng th < 500 mils
Trace spac ing = 15 mils
MB U3
MB U3
DB U2
+1V_S5
Reserve PD 60 o hm in E42
ball for Cannonlake U
RTC_RST #
3
2
PQ6060
*2N7002K
1
Add SSD ID 1/14
Hight is SSD , Low is ODD
SSD_ID(25)
Skylake-U userd 24 MHz (50 Ohm ES R) XTAL
XTAL24_IN
XTAL24_OUT
Note: Change Y4 to 38.4 MHz(ESR 30 o hm) for C annonlake U
RTC Clock 32.768KHz (R TC)
Trace length < 1 000 m ils
RTC Circuitry (RTC)
+3VPCU
On SKL voltage at VCCRTC does not excee d 3.2V
R304
1.5K/F_4
VCCRTC _2
R301
45.3K/F_4
2013/10/16 Chage +3V_RTC_0 to VCCTC_2.
1A-2
1. AHL0300 3057 DBV CR2032
2. AHL0300 3003 VDE CR2032
2
PCH PU /PD
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
SATA_DEVSL P0
SATA_DEVSL P1
SATA_DEVSL P2
PIRQA#
SATAGP1
SATAGP2
R568 10K_4
C351 6.8p/ 50V_4
C362 6.8p/ 50V_4
1B-1
R308 1K_4
12
BT1
BAT_CONN
SATAGP0
C665 10P/50 V_4
4
3
Y4
R536
24MHz
1M_4
1
2
C658 10P/50 V_4
12
Y2
32.768KHZ
D7
+3V_RTC_2
+3V_RTC_1
+3V_RTC_[0: 2]
Trace widt h = 20 mils
BAT54C
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Monday, J uly 20, 2015
Date: Sheet of
Monday, J uly 20, 2015
Date: Sheet of
Monday, J uly 20, 2015
+3V_S5
R541 10K_4
R540 10K_4
R543 10K_4
R542 10K_4
R573 *10K_4
R574 *10K_4
R575 *10K_4
R631 *10K_4
R569 *10K_4
R566 *10K_4
+3V_S5
R570 100K_4
CH01006JB08 -> 10p
CH01506JB06 -> 15p
CH-6806TB01 -> 6.8p
RTC_X1
R255
10M_4
RTC_X2
+3V_RTC
+3V_RTC
Trace widt h = 30 mils
R299
20K/F_4
R300
20K/F_4
C381
1u/6.3V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJEC T :
PROJEC T :
PROJEC T :
Skyla ke 9/10 (PE G/USB /CLK)
Skyla ke 9/10 (PE G/USB /CLK)
Skyla ke 9/10 (PE G/USB /CLK)
+3V
24MHz: BG 624000078
38.4MHz : ?
BG3327684 53 -> SEG
BG3327681 04 -> TXC
12
C380
1u/6.3V_4
C382
1u/6.3V_4
ZRW
ZRW
ZRW
6 48
6 48
1
6 48
RTC_RST #
J1
*JUMP
SRTC_RST #
3A
3A
3A
5
4
3
2
1
?
U35E
SPI - FLASH
EC_RC IN#
PCH_S PI_CS0#
PCH_S PI_CS1#
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
SPI - TOUCH
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
C LINK
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
AW13
GPP_A0/RCIN#
AY11
GPP_A6/SERIRQ
SKL_U LT/BGA
REV = 1
PCH_S PI_SO
PCH_S PI_SO_EC
PCH_S PI_CLK_R
PCH_S PI_SI_R
PCH_S PI_SO_R
only 0ohm opti on
1A-13
+3V_S 5
+3V_S 5
+3V_PC H_ME
PCH_S PI_CLK
PCH_S PI_SO
PCH_S PI_SI
PCH_S PI_IO2
D D
For M.2 wifi m odule must
Rev:D change to shortpad
C C
SPI ROM
Skylake
3.3V
B B
Vender Size Quan ta P/N Vende r P/N
IRQ_SER IRQ(25,2 9)
8M
8M
PCH_S PI_CLK_EC(29)
PCH_S PI_SI_EC(29)
PCH_S PI_SO_EC(29)
SPI_CS0 #_UR_ME(29)
SIO_RCIN#(29)
AKE3EFP0 N07
AKE2EZN 0Q00
+3V_PC H_ME
PCH_S PI_IO3
PCH_S PI_CS0#
PCH_S PI_CS1# SML0AL ERT#
CL_CL K
TP68
CL_DAT
TP66
CL_RS T#
TP67
R652 *short_4
IRQ_SER IRQ
W25Q64F VSSIQWND
GD25B64C SIGRGGD
R689 *4M@33_ 4
R641 *4M@33_ 4
R594 *4M@33_ 4
R602 8M@0_4
R603 *4M@0_ 4
R591 10K_4
SPI_CS0 #_UR_ME
SKL_ULT
+3V_S 5
LPC
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
5 OF 20
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
PCH SPI ROM(8M+4M )
15ohm CS01 502JB12
33ohm CS03 302JB29
PCH_S PI_CS0#
R588 8M@15_ 4
3.3K is orig inal and for no
support f ast read function
PCH_S PI_CS1#
PCH_S PI_CLK
PCH_S PI_SI
PCH_S PI_SO
C745 *22p /50V_4
SPI_SO_8 M
R649 1K_4
R669 *4M@33_ 4
R658 *4M@33_ 4
R604 *4M@33_ 4
PCH_S PI_CLK_R
PCH_S PI_SI_R
PCH_S PI_SO_R
+3V_PC H_ME
SMBUS, SMLINK
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
+3V_S 5
GPP_A14/SUS_STAT#/ES PI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
Rev:D change to shortpad
R700 *short_6
+3V_S5
U41
1
2
3
4
W25Q 64FV -- 8MB
SPI_WP _IO2_ME
PCH_S PI_IO2
PCH_S PI_IO3
R597 *1K_4
CS#
IO1/DO
IO2/WP#
GND
VCC
IO3/HOLD#
IO0/DI
PCH_S PI_CLK_EC
PCH_S PI_SI_EC
R596 *4M@3 3_4
R589 8M4M@ 15_4
R238 *4M@33 _4
R239 8M4M@1 5_4
U39
1
CE#
6
SCK
5
SI
2
SO
3
WP#
*4M@R OM-4M_EC
SPI_WP _IO2_EC
R7
PCH_M BCLK0_R
R8
PCH_M BDAT0_R
R10
SMBALER T#
R9
VGA_MBC LK
W2
VGA_MBD ATA
W1
W3
SMB_M E1_CLK
V3
SMB_M E1_DAT
AM7
SML1AL ERT#
eSPI chang e to 15 oh m
AY13
R659 *short_4
BA13
R640 *short_4
BB13
R653 *short_4
AY12
R668 *short_4
BA12
BA11
R748 *0_4
C806 0.1u/1 6V_4
eSPI chang e to 15 oh m
AW9
R623 22/J_4
AY9
AW11
R626 22/J_4
R627 22/J_4
CLKRU N#
2/10 add C 806 for EMI request ,
?
R748 no stuiff from EC site
move at C PU site
+3V_PC H_ME
8
7
SPI_HOL D_IO3_ME
6
SPI_CLK _8M
CLK
5
SPI_SI_8M
R687 8M@15 _4
R654 8M@15 _4
SPI_HOL D_IO3_EC
SPI_HOL D_IO3_ME
8
VDD
7
SPI_HOL D_IO3_EC
HOLD#
4
VSS
Rev:D change to shortpad
LPC_L AD0 (25,26 ,29)
LPC_L AD1 (25,26 ,29)
LPC_L AD2 (25,26 ,29)
LPC_L AD3 (25,26 ,29)
LPC_L FRAME# ( 25,26,29)
ESPI_RS T# (29)
CLK_P CI_EC (29)
PCLK_ TPM ( 25)
CLK_P CI_LPC (26)
C754 0.1u /16V_4
R698 1K_4R650 8M4M@1 5_4
R684 8M4M @15_4
R691 8M4M @15_4
SPI_WP _IO2_EC
SPI_WP _IO2_ME
reserve for SPI fast r ead
+3V_PC H_ME
R232 *1K_4
C741
*4M@0 .1u/16V_4
Strapping
SMBALER T# (4)
SML0AL ERT# (4)
SMB1AL ERT# (27)
ckl v 0.71 p.24
CLKRU N# (25 ,29)
+3V_PC H_ME
PCH_S PI_CLK
PCH_S PI_SI
C747
*22p/5 0V_4
CLKRU N#
IRQ_SER IRQ
EC_RC IN#
R630 8.2K/F_4
R629 10K_4
R639 10K_4
SMBus
PCH_M BCLK0_R
PCH_M BDAT0_R
VGA_MBD ATA
VGA_MBC LK
SML1AL ERT#
Term ination Resistor Requirement f or PCH PC HHOT# Pin
Reserve PU 150K resister
+3V
S5 S0
SMBus(PCH)
PCH_M BDAT0_R
PCH_M BCLK0_R
PCH_XDP_WLAN/S5 DDR_TP/S0
R5782.2K _4
R5802.2K _4
R5852.2K _4
R5822.2K _4
R205*15 0K_4
D2B change to 2.2k
R576
2.2K_4
Q32
5
2
6
2N700 2DW
SMBus(EC)
2ND_M BCLK(17,2 9)
2ND_M BDATA(17,29 )
EC/S5
2ND_M BCLK
2ND_M BDATA
R171 *short_4
R175 *short_4
Rev:D change to shortpad
43
1
+3V
+3V_S5
+3V_S5
R572
2.2K_4
CLK_S DATA (12,13,2 7)
CLK_S CLK (12,13 ,27)
SMB_M E1_CLK
SMB_M E1_DAT
1A-3 2013/10/16 A dd U34 flas h 4M ROM res erve for ZQ 0D.
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJEC T :
PROJEC T :
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Shee t of
Date: Shee t of
Date: Shee t of
Monday, J uly 20, 201 5
Monday, J uly 20, 201 5
5
4
3
2
Monday, J uly 20, 201 5
PROJEC T :
Skylake 5 (SATA/HDA/SPI)
Skylake 5 (SATA/HDA/SPI)
Skylake 5 (SATA/HDA/SPI)
ZRW
ZRW
ZRW
7 4 8
7 4 8
1
7 4 8
3A
3A
3A
5
4
3
2
1
PCI_PLTR ST#
SYS_RESET#(11)
SYS_PWROK
PCH_SUSPW RACK_R(29)
PCH_SUSAC K#(29)
PCIE_LAN_W AKE#(23,26)
R611 *10K_4
R613 *10K_4
R615 *10K_4
R600 *10K_4
R599 *10K_4
R608 *10K_4
R590 *10K_4
R593 10K_4
R607 *10K_4
R765 *10K_4
R767 *10K_4
4
R214
100K_4
RSMRST#(29)
R556 *short_4
R643 *0_4
+1.8V_S5
PLTRST# (14 ,23,25,26,29)
Realtek
Audio codec
(Default)
Reserved
(Default)
+VCCIO
11/12 R eserve PU 10 K
R544 *10K_4
D D
Rev:D change to shortpad
PROC_PWR GD
Rev:D change to shortpad
Board ID
2
1
RAM_ID1
RAM_ID2
RAM_ID3
Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
5
IOACNon IOAC
G-sensor No G-sensor
TPM
touch panel
+3V
C332 0.1u/16 V_4
U14
3 5
TC7SH08F U
R610 10K_4
R612 10K_4
R614 10K_4
R595 10K_4
R598 10K_4
R605 10K_4
R592 10K_4
R606 10K_4
R764 10K_4
R766 10K_4
VRAM 2GB VRAM 4GB
C C
B B
No TPM
No touch panel
PLTRST# Buffer
A A
PCI_PLTR ST#
SYS_RESET#
R655 *short_4
R554 10K_4
VCCST_PW RGD
R622 *0_4
R617 *0_4
PCH_RSM RST#
PROC_PWR GD
SYS_PWROK _R
EC_PWROK _R
DPWROK_R PCH_ACPR ESENT
PCH_SUSPW RACK
PCIE_LAN_W AKE#
SUSACK#_R
TP84
CPU DSP
ReserveReserved
Reserve
For platforms not supporting Deep
Sx, connect directly to RSMRST#
U35K
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRG D
B65
VCCST_PWR GD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PW ROK
AR13
GPP_A13/SUSWARN# /SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
SKL_ULT/BG A
REV = 1
U35I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
SKL_ULT/BG A
Power Sequence
PCH_PWR OK(29)
SYSPWOK
4
SYSTEM POWER M ANAGEMENT
I
I
REV = 1
SYS_PWROK
?
SKL_ULT
GPP_B12/SLP_S0#
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
SKL_ULT
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
+1.8V_S 5
Rev:D change to shortpad
DPWROK_R PCH_RSM RST#
DPWROK_R
U8
*TC7SH08 FU
+3V_S5
+3V_S5
+3V_S5
+3V_S5
GPD9/SLP_WLAN#
+3V_S5
+3V_S5
GPD1/ACPRESENT
+3V_S5
+3V_S5
+3V_S5
+3V_S5
GPP_B11/EXT_PW R_GATE#
+3V_S5
+3V_S5
11 OF 20
?
+3V_S5
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
9 OF 20
EMMC
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC_RCOMP
?
GPP_B2/VRALERT#
Non Deep S x
R647 *short_4
EC_PWROK SYS_PWROK _R
R131 *0_4
No Deep Sx
+3V_S5
4
3 5
R113 *0_4
R560 *short_4
Rev:D change to shortpad
R661 *short_4
R674 *0_4
C168 *0.1u/16V_4
2
EC_PWROK
1
GPD10/SLP_S5#
GPD3/PWRBT N#
GPD0/BATLOW #
Rev:D change to shortpad
GPD4/SLP_S3#
GPD5/SLP_S4#
SLP_SUS#
SLP_LAN#
GPD6/SLP_A#
GPP_A11/PME#
INTRUDER#
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
INTRUD ER#
AM10
MPHY_EXT_ PWR
AM11
PCH_VRALE RT#
?
R145 100/F_4
RAM_ID1
RAM_ID2
RAM_ID3
Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
R616200/F_4
EC_PWROK _R
DPWROK_C (29)
EC_PWROK (29)
IMVP_PWR GD_3V (2)
R130
*10K_4
3
SUSB#
SUSC#
PCH_SLP_S5 #
PCH_SLP_SU S#
PCH_SLP_LA N#
PCH_SLP_W LAN#
PCH_SLP_A#
PCH_PWR BTN#
PCH_BATLO W#
TP63
TP29
R249 1M_4
TP19
Board_ID4 (21)
REV:E tPLT17(max
200us) ->S LP_S3#
assertion to IMVP
VR_ON(VRO N) deassertion
VRON(33,36)
REV:F Stuf f R792
SUS0# (29 )
SUSB# (11 ,29,31)
SUSC# (11,29)
PCH_SLP_S5 # (11)
PCH_SLP_SU S# (29)
TP30
Rev:D change to shortpad
TP23
R677*sho rt_4
R676*sho rt_4
U50
*TC7SH08 FU
VCCST_PW RGD
TP74
+3V_RTC
4
R792 0_4
C136
*0.1u/16V_4
PCH_SLP_A# (11)
DNBSWON # (29)
ACPRESENT ( 29)
+3V_S5
C813 *0.1u/16V_4
2
1
3 5
+1V_VCCST
R89 60.4 /F_4
Shortpad change
to 60.4 ohm. 11/6
VCCST_PW RGD_EN
2013/10/2 1 Del APW ORK.1A-6
REV:E t PLT15(max 200us)
->SLP_S4# a ssertion to
VDDQ(+1.3 5VSUS) ramp
down start (SUSON)
REV:F Stuf f R790
SUSB#
VRON_EC
CRB is via +1.05V PGVCCST PWRGD
+3V_S5
C164
R85
0.1u/16V_4
1K_4
VCCST_PW RGD_R
R103 *0_4
R102 0_4
2
SUSON
SUSON(32,35)
VRON_EC (29)
U6
5
NC
VCC
A
4
GND
Y
74AUP1G07GW
PCH_PWR OK
HWPG
Rev:D change netmane for HW PG
PCH_VRALE RT#
SYS_RESET#
PCH_ACPR ESENT
PCH_BATLO W#
PCIE_LAN_W AKE#
MPHY_EXT_ PWR
PCH_RSM RST#
PCH_PWR OK
SYS_PWROK _R
DPWROK_C
+3V_S5
C811 *0.1u/16V_4
4
U48
3 5
*TC7SH08 FU
R790 0_4
REV:E t PLT18(max 200 us )
->SLP_S3# a ssertion to
VCCIO VR( MAIND for +1V_S 5
to +VCCIO ) disabled
MAINON(35,40)
REV:F Stuf f R791
B2A
S0->S5 & S 0->S3
Power of s equence 1us
SUSB# -> VC CST_PWRGD
1
2
VCCST_PW RGD_EN_L
3
HWPG (29)
+3V
R211 10K_4
R561 10K_4
R651 8.2K/F_4
R628 8.2K/F_4
R250 10K_4
R195 *1K_4
R642 10K_4
R648 10K_4
R555 10K_4
R675 100K_4
2
SUSC#
1
SUSON_EC
4
U47
TC7SH08F U
R777 *0_4
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Monday, J uly 20, 2015
Date: Sheet of
Monday, J uly 20, 2015
Date: Sheet of
Monday, J uly 20, 2015
+3V_S5
Rev:F add
SUSON_EC ( 29)
+3V_S5
C812 *0.1u/16V_4
2
4
U49
*TC7SH08 FU
R791 0_4
+3V_S5
C808 0.1u/16V_4
2
1
VCCST_PW RGD_EN
3 5
Skyla ke 9/11 (PW ROK/Bo ard_ID )
Skyla ke 9/11 (PW ROK/Bo ard_ID )
Skyla ke 9/11 (PW ROK/Bo ard_ID )
SUSB#
1
MAINON_E C
3 5
SUSB#
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJEC T :
PROJEC T :
PROJEC T :
1
ZRW
ZRW
ZRW
MAINON_E C (29)
8 48
8 48
8 48
3A
3A
3A
5
4
3
2
1
U35S
E68
D D
CFG4
R156 49.9/F_4
+1V_S5
C C
B B
CFG_RC OMP
R153 1.5K/F_4
B67
D65
D67
E70
C68
D68
C67
G69
G68
H70
G71
H69
G70
E63
E66
E60
AY2
AY1
K46
K45
AL25
AL27
C71
B70
A52
BA70
BA68
G65
E61
F71
F70
F63
F66
E8
D1
D3
F60
J71
J68
F65
F61
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10 ]
CFG[11 ]
CFG[12 ]
CFG[13 ]
CFG[14 ]
CFG[15 ]
CFG[16 ]
CFG[17 ]
CFG[18 ]
CFG[19 ]
CFG_R COMP
ITP_PMO DE
RSVD_A Y2
RSVD_A Y1
RSVD_D 1
RSVD_D 3
RSVD_K 46
RSVD_K 45
RSVD_A L25
RSVD_A L27
RSVD_C 71
RSVD_B 70
RSVD_F 60
RSVD_A 52
RSVD_T P_BA70
RSVD_T P_BA68
RSVD_J 71
RSVD_J 68
VSS_F6 5
VSS_G6 5
RSVD_F 61
RSVD_E 61
REV = 1
RESERVED SIGNALS-1
SKL_ULT /BGA
SKL_ULT
?
19 OF 20
RSVD_T P_BB68
RSVD_T P_BB69
RSVD_T P_AK13
RSVD_T P_AK12
RSVD_B B2
RSVD_B A3
RSVD_D 5
RSVD_D 4
RSVD_B 2
RSVD_C 2
RSVD_B 3
RSVD_A 3
RSVD_A W1
RSVD_E 1
RSVD_E 2
RSVD_B A4
RSVD_B B4
RSVD_A 4
RSVD_C 4
RSVD_A 69
RSVD_B 69
RSVD_A Y3
RSVD_D 71
RSVD_C 70
RSVD_C 54
RSVD_D 54
VSS_AY 71
ZVM#
RSVD_T P_AW71
RSVD_T P_AW70
MSM#
PROC_ SELECT#
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW 1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
AR56
AW 71
AW 70
AP56
C64
?
Rev:D c hange to shortp ad
Rev:F R emove S hort Jum per for all +1V_ S5
+1V_S5
TP95
Rev:F r eserve T P
+1V_S5
Rev:F S tuff C69 9
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+3VPCU
+3V_S5
+3V
+1.5V
+3V_S5
R759 *short_4
Rev:D cha nge t o
short pad
R760 *short_4
R762 *GT3@ 0_4
R761 100K_ 4
+1V_S5
+3V_S5
+1V_S5
+1V_S5
+1V_VC CST
VCCPRIM_1P0 & VCCPRIM_CORE Short
AB19
AB20
P18
AF18
C698 1U/6.3V_ 4
C699 47u/6.3V _8
C7121U/6.3V_4
C695 1U /6.3V_4
R210 *0_6
R212 *short_6
R789 0_ 6
R683 *0_6
R193 *short_6
R186 *short_6
LPM_ZV M_N (33)
C793 1U/6 .3V_4
C191 1U/6.3V_ 4
C182 47u/6.3V _8
C179 1U/6.3V_ 4
C225 *1U/6.3V_ 4
+VCCPD SW_3P3
C748 1U/6.3V_ 4
C192 1U/6.3V_ 4
+VCCPR IM_3P3
C261 1U/6.3V_ 4
C173 1U/6.3V_ 4
For 2+3 e CPU N o Stuff
TP88
+VCCD SW_1P0
C314*0.1U/16V_ 4
+VCCH DA
+VCCPS PI
AF19
AB17
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
AJ21
AK20
V20
V21
AL1
K17
L1
N15
N16
N17
P15
P16
K15
L15
V15
Y18
T19
T20
N18
SKL_ULT
U35O
CPU POWER 4 OF 4
VCCPR IM_1P0
VCCPR IM_1P0
VCCPR IM_1P0
VCCPR IM_CORE
VCCPR IM_CORE
VCCPR IM_CORE
VCCPR IM_CORE
DCPDS W_1P0
VCCMP HYAON_1P0
VCCMP HYAON_1P0
VCCMP HYGT_1P0_N 15
VCCMP HYGT_1P0_N 16
VCCMP HYGT_1P0_N 17
VCCMP HYGT_1P0_P 15
VCCMP HYGT_1P0_P 16
VCCAM PHYPLL_1P0
VCCAM PHYPLL_1P0
VCCAP LL_1P0
VCCPR IM_1P0_AB17
VCCPR IM_1P0_Y18
VCCDS W_3P3_A D17
VCCDS W_3P3_A D18
VCCDS W_3P3_A J17
1.5V
VCCHD A
3.3V
VCCSP I
VCCSR AM_1P0
VCCSR AM_1P0
VCCSR AM_1P0
VCCSR AM_1P0
VCCPR IM_3P3_AJ21
VCCPR IM_1P0_AK20
VCCAP LLEBB
1.0V
SKL_ULT /BGA
REV = 1
1.0V
S5
1.0V
1.0V
30mA
11mA
1.0V
642mA
1.0V
S5
1.0V
22mA
S5
1.0V
1.258A
1.0V
S5
1.0V
S5
3.3V
118mA
3.3V
1.0V
33mA
?
696mA
2.574A
75mA with AJ21 pin
6mA
26mA
696mA
S5
S5
+3V
75mA
696mA
15 OF 20
44mA
S5
33mA
41mA
VCCPR IM_3P3_V19
1.0V
VCCPR IM_1P0_T1
1.8V
<1mA
VCCRT CPRIM_3P3
3.0V+
RTC
1.0V
135mA
S5
GPP_B0 /CORE_VID0
GPP_B1 /CORE_VID1
S5
S5
VCCPG PPG
VCCAT S_1P8
VCCRT C_AK19
VCCRT C_BB14
GPIO Group Power Plane
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
?
+VCCPG PPA
+VCCPG PPB
+VCCPG PPC
+VCCPG PPD
+VCCPG PPE
+VCCPG PPF
+VCCPG PPG
+VCCPR IM_3P3
+VCCPR IM_1P0
+VCCAT S_1P8
+VCCPR TCPRIM_3P 3
V0P85A_ VID0
V0P85A_ VID1
VCCPG PPA
VCCPG PPB
VCCPG PPC
VCCPG PPD
VCCPG PPE
VCCPG PPF
DCPRT C
VCCCL K1
VCCCL K2
VCCCL K3
VCCCL K4
VCCCL K5
VCCCL K6
C250 1U/6.3V_ 4
C349 1U/6.3V_ 4
+VCCPR TC
C322 1U/6.3V_ 4
DCPRT C
C680 *1U/6.3V_ 4
C672 1U/6.3V_ 4
C292 *1U/6.3V_ 4
C268 1U/6.3V_ 4
C230 1U/6.3V_ 4
C265 *1U/6.3V_ 4
R198*short_6
R185*short_6C217 1U/6.3V_ 4
R182*short_6
R187*short_6
R179*short_6
R192*short_6
R188*short_6
C256 1U/6.3V_ 4
C270 *1U/6.3V_ 4
R180*short_6
R240*short_6
C348 0.1U/16 V_4
R252*short_6
C352 0.1U/16 V_4
C732 0.1U/16 V_4
TP31
TP16
Rev:D cha nge t o sh ortpa d
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+1.8V_S5
+3V_S5
+1V_S5
+1.8V_S5
+3V_S5
+3V_RTC
+1V_S5
Pin Name Strap description Configuration
CFG[0] Stall reset sequenc e after PCU PLL lock un til de-asserted
CFG[1]
CFG[2]
Reserved Configurat ion lane
PCI Exp ress* S tatic x16 Lane Nu mbering Rev ersal
1 = *Normal Operation; No stall (iPU 3K)
0 = Stall
1 = *Normal Operation(i PU 3K)
0 = Lan number rev ersed
Note
H & S p rocessor used only
CFG[3] Reserved Configurat ion lane
CFG[4]
CFG[6:5] PCI Expres s* Bifun ction
A A
eDP enab le
CFG[7] PEG Training
CFG[19:8 ]
Reserved Configurat ion lane
5
1 = Disabled (iPU 3K )
0 = *En abled
00 = 1x8, 2x4 PC I Expres s*
01 = res erved
10 = 2x8 PCI E xpress*
11 = 1x16 PCI E xpress*
1 = *PE G Trai n immed iatedly follow
RESET# de-asse rtion (iPU 3K)
0 = PE G wait for BIOS for training
4
CFG4
R548 1K _4
H & S p rocessor used only
H & S p rocessor used only
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Docu ment Number Rev
Size Docu ment Number Rev
Size Docu ment Number Rev
Date: Sheet of
Monday, July 20, 20 15
Date: Sheet of
Monday, July 20, 20 15
Date: Sheet of
2
Monday, July 20, 20 15
PROJECT :
Skylake PCH-LP 15/19 (POWER)
Skylake PCH-LP 15/19 (POWER)
Skylake PCH-LP 15/19 (POWER)
ZRW
ZRW
ZRW
3A
3A
9 48
9 48
1
9 48
3A
5
4
3
2
1
Skylake ULT (GND)
GND 3 OF 3
?
18 OF 20
U35R
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
?
SKL_ULT
U35T
SPARE
L18
L2
+1.8V_S5
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
?
R775 *0_4
*1U/6.3V _4
Reserve 1uF no stuff in CPU U11,U12 ball
support Cannonlake-U PCH
2
AW69
RSVD_A W69
AW68
RSVD_A W68
AU56
RSVD_A U56
AW48
RSVD_A W48
C7
RSVD_C 7
U12
RSVD_U 12
U11
RSVD_U 11
H11
C794
Size Docu ment Num ber Rev
Size Docu ment Num ber Rev
Size Docu ment Num ber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
RSVD_H 11
SKL_UL T/BGA
REV = 1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Skylake 10/17/18 (GND)
Skylake 10/17/18 (GND)
Skylake 10/17/18 (GND)
Monday, Ju ly 20, 2015
Monday, Ju ly 20, 2015
Monday, Ju ly 20, 2015
20 OF 20
RSVD_F 6
RSVD_E 3
RSVD_C 11
RSVD_B 11
RSVD_A 11
RSVD_D 12
RSVD_C 12
RSVD_F 52
ZRW
ZRW
ZRW
1
G10
G22
G43
G45
G48
G52
G55
G58
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
F8
G5
G6
J8
SKL_ULT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_UL T/BGA
REV = 1
?
A67
A70
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL2
AL28
AL32
AL35
AL38
AL4
AL45
AL48
AL52
AL55
AL58
AL64
A5
REV = 1
SKL_ULT
GND 1 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_UL T/BGA
D D
C C
B B
A A
5
16 OF 20
U35P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
?
4
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
REV = 1
SKL_ULT
GND 2 OF 3
SKL_UL T/BGA
?
17 OF 20
U35Q
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
?
3
F6
E3
C11
B11
A11
D12
C12
F52
?
10 48
10 48
10 48
3A
3A
3A
5
4
3
2
1
D D
C C
B B
R289 *0_6
Intel APS Fixture use
CN2
A A
*ACES _88511 -180N
1
APS1
1
2
2
3
APS3
3
4
4
5
5
6
6
7
APS7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
5
R291 *0_6
R282 *0_4
R278 *0_6
R279 *0_4
R274 *0_4
R273 *0_4
R271 *0_6
R268 *0_4
R265 *0_4
R267 *0_4
APS3
+3V_S 5
SYS_RE SET#
R272 *0_6
SUSB # (8,29,31)
PCH_ SLP_S 5# (8)
SUSC # (8,29)
PCH_ SLP_A # (8)
RTC_R ST# (6)
NBSW ON# ( 27,29)
SYS_RE SET# (8)
4
APS7APS1
+3VPC U
+3VPC U
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Docume nt Num ber Rev
Size Docume nt Num ber Rev
Size Docume nt Num ber Rev
Date: Sheet of
Monda y, July 20 , 2015
Date: Sheet of
Monda y, July 20 , 2015
Date: Sheet of
3
2
Monda y, July 20 , 2015
PROJECT :
CPU/PCH XDP
CPU/PCH XDP
CPU/PCH XDP
ZRW
ZRW
ZRW
11 48
11 48
11 48
1
3A
3A
3A
5
M_A_A[15:0](3)
D D
M_A_BS#0(3)
M_A_BS#1(3)
M_A_BS#2(3)
M_A_CS#0(3 )
M_A_CS#1(3 )
M_A_CLK0(3 )
M_A_CLK0#(3)
M_A_CLK1(3 )
M_A_CLK1#(3)
M_A_CKE0(3)
M_A_CKE1(3)
M_A_CAS#(3)
M_A_RAS#(3)
CLK_SCLK(7,13,27)
CLK_SDATA(7,13,27)
M_A_ODT0_DIMM(3)
M_A_ODT1_DIMM(3)
M_A_DQS[7:0](3)
M_A_DQS#[7:0](3)
C430
10u/6.3V_6
M_A_WE#(3)
C445
10u/6.3V_6
+VDDQ_VTT
5
C444
0.1u/16V_4
C468
1u/6.3V_4
R332 10K_4
R335 10K_4
1A-8
2013/10 /23 Ch ange D IMM1_S A0/SA1
C C
to DIMM 0_SA0/ SA1.
1A-2
2013/10 /16 Ch age ne t name M_B_D QS#[7: 0] to
B B
+1.35VSUS
C470
10u/6.3V_6
+3V
C439
2.2u/6.3V_6
A A
M_A_DQS #[7:0] .
Place these Caps near SO-DIM M
C472
10u/6.3V_6
C448
0.1u/16V_4
C432
10u/6.3V_6
C471
10u/6.3V_6
C446
0.1u/16V_4
C466
0.1u/16V_4
C434
1u/6.3V_4
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
DIMM0_SA0
DIMM0_SA1
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
C447
0.1u/16V_4
107
119
109
108
114
121
101
103
102
104
115
110
113
197
201
202
200
116
120
136
153
170
187
137
154
171
188
135
152
169
186
C464
0.1u/16V_4
C467
1u/6.3V_4
98
97
96
95
92
91
90
86
89
85
84
83
80
78
79
73
74
11
28
46
63
12
29
47
64
10
27
45
62
+
JDIM2A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DDR3-DIMM1_H=4.0_STD
C486
330u/2V_7343
C442
1u/6.3V_4
4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
(204P)
PC2100 DDR3 SDRAM SO-DIMM
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
+SMDDR_VREF_DIMM
C480
0.1u/16V_4
C449
4.7U/10V_6
4
C473
2.2u/6.3V_6
4.7U/10V_6
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
+SMDDR_VREF_DQ0
C441
0.1u/16V_4
C463
C455
4.7U/10V_6
C443
2.2u/6.3V_6
M_A_DQ0 (3)
M_A_DQ4 (3)
M_A_DQ6 (3)
M_A_DQ7 (3)
M_A_DQ1 (3)
M_A_DQ5 (3)
M_A_DQ3 (3)
M_A_DQ2 (3)
M_A_DQ12 (3)
M_A_DQ8 (3)
M_A_DQ10 (3)
M_A_DQ14 (3)
M_A_DQ9 (3)
M_A_DQ13 (3)
M_A_DQ15 (3)
M_A_DQ11 (3)
M_A_DQ17 (3)
M_A_DQ21 (3)
M_A_DQ22 (3)
M_A_DQ18 (3)
M_A_DQ20 (3)
M_A_DQ16 (3)
M_A_DQ23 (3)
M_A_DQ19 (3)
M_A_DQ28 (3)
M_A_DQ24 (3)
M_A_DQ30 (3)
M_A_DQ31 (3)
M_A_DQ25 (3)
M_A_DQ29 (3)
M_A_DQ27 (3)
M_A_DQ26 (3)
M_A_DQ36 (3)
M_A_DQ33 (3)
M_A_DQ38 (3)
M_A_DQ39 (3)
M_A_DQ32 (3)
M_A_DQ37 (3)
M_A_DQ34 (3)
M_A_DQ35 (3)
M_A_DQ44 (3)
M_A_DQ45 (3)
M_A_DQ46 (3)
M_A_DQ47 (3)
M_A_DQ40 (3)
M_A_DQ41 (3)
M_A_DQ42 (3)
M_A_DQ43 (3)
M_A_DQ48 (3)
M_A_DQ52 (3)
M_A_DQ55 (3)
M_A_DQ54 (3)
M_A_DQ53 (3)
M_A_DQ49 (3)
M_A_DQ51 (3)
M_A_DQ50 (3)
M_A_DQ59 (3)
M_A_DQ58 (3)
M_A_DQ56 (3)
M_A_DQ57 (3)
M_A_DQ62 (3)
M_A_DQ63 (3)
M_A_DQ60 (3)
M_A_DQ61 (3)
CHA
CHB
3
+VREF_CA_CPU
M3 solution
+VREFDQ_SA_M3
M3 solution
SA0SA1
0 0
01
3
DDR3_DRAMRST#(3,13)
R362 *Short_6
R327 *Short_6
R347 *10K_4
+3V
+SMDDR_VREF_DQ0
+SMDDR_VREF_DIMM
R363 2/F_6
C478
0.022u/16V_4
1 2
R357
24.9/F_4
R328 2/ F_6
C427
0.022u/16V_4
1 2
R325
24.9/F_4
2
+1.35VSUS
2.48A
+3V
PM_EXTTS#0
C465 * 0.1u/16V_4
+SMDDR_VREF_DQ0
M1 solution
+1.35VSUS
R358
1.8K/F_4
R346
1.8K/F_4
M1 solution
+1.35VSUS
R330
1.8K/F_4
R331
1.8K/F_4
2
1
JDIM2B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDR3-DIMM1_H=4.0_STD
PC2100 DDR3 SDRAM SO-DIMM
(204P)
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VTT1
VTT2
GND
GND
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
203
204
205
206
+VDDQ_VTT
Vref_CA
+SMDDR_VREF_DIMM
C479
470p/50V_4
Vref_DQ
+SMDDR_VREF_DQ0
C440
470p/50V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Monday, July 20 , 2015
Date: Sheet of
Monday, July 20 , 2015
Date: Sheet of
Monday, July 20 , 2015
PROJECT :
DDR3 MEMORY SO-DIMM A
DDR3 MEMORY SO-DIMM A
DDR3 MEMORY SO-DIMM A
1
ZRW
ZRW
ZRW
12 48
12 48
12 48
3A
3A
3A
5
4
3
2
1
M_B_A[15:0](3)
D D
M_B_BS#0(3)
M_B_BS#1(3)
M_B_BS#2(3)
M_B_CS#0(3)
M_B_CS#1(3)
M_B_CLK0(3)
M_B_CLK0#(3)
M_B_CLK1(3)
M_B_CLK1#(3)
M_B_CKE0(3)
M_B_CKE1(3)
M_B_CAS#(3)
M_B_RAS#(3)
CLK_SCLK(7,12,27)
CLK_SDATA(7,12,27)
M_B_ODT0_DIMM(3)
M_B_ODT1_DIMM(3)
M_B_DQS[7:0](3)
M_B_DQS#[7:0](3)
C402
10u/6.3V_6
C404
10u/6.3V_6
+VDDQ_VTT
M_B_WE#(3)
C421
0.1u/16V_4
R323 10K_4
R305 10K_4
+3V
C C
B B
1A-2
2013/10/ 16 Swap M_B_DQS 2/M_B_D QS3 and swap
M_B_DQS #2/M_B_ DQS#3.
+1.35VSUS
C419
10u/6.3V_6
+3V
Place these Caps near SO-DIMM
C418
10u/6.3V_6
C401
10u/6.3V_6
C420
10u/6.3V_6
C400
0.1u/16V_4
C403
0.1u/16V_4
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
DIMM1_SA0
DIMM1_SA1
M_B_DQS1
M_B_DQS0
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#1
M_B_DQS#0
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
C416
0.1u/16V_4
C399
0.1u/16V_4
JDIM1A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDR3-DIMM1_H=4.0_RVS
+SMDDR_VREF_DIMM
+
C433
330u/2V_7343
0.1u/16V_4
C422
PC2100 DDR3 SDRAM SO-DIMM
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
(204P)
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2.2u/6.3V_6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
+SMDDR_VREF_DQ1
C423
0.1u/16V_4
C393
C392
2.2u/6.3V_6
M_B_DQ12 (3)
M_B_DQ8 (3)
M_B_DQ11 (3)
M_B_DQ10 (3)
M_B_DQ9 (3)
M_B_DQ13 (3)
M_B_DQ15 (3)
M_B_DQ14 (3)
M_B_DQ4 (3)
M_B_DQ0 (3)
M_B_DQ3 (3)
M_B_DQ6 (3)
M_B_DQ5 (3)
M_B_DQ1 (3)
M_B_DQ2 (3)
M_B_DQ7 (3)
M_B_DQ17 (3)
M_B_DQ16 (3)
M_B_DQ18 (3)
M_B_DQ19 (3)
M_B_DQ21 (3)
M_B_DQ20 (3)
M_B_DQ22 (3)
M_B_DQ23 (3)
M_B_DQ24 (3)
M_B_DQ25 (3)
M_B_DQ30 (3)
M_B_DQ31 (3)
M_B_DQ28 (3)
M_B_DQ29 (3)
M_B_DQ26 (3)
M_B_DQ27 (3)
M_B_DQ36 (3)
M_B_DQ37 (3)
M_B_DQ39 (3)
M_B_DQ35 (3)
M_B_DQ32 (3)
M_B_DQ33 (3)
M_B_DQ34 (3)
M_B_DQ38 (3)
M_B_DQ44 (3)
M_B_DQ45 (3)
M_B_DQ42 (3)
M_B_DQ43 (3)
M_B_DQ41 (3)
M_B_DQ40 (3)
M_B_DQ46 (3)
M_B_DQ47 (3)
M_B_DQ48 (3)
M_B_DQ52 (3)
M_B_DQ55 (3)
M_B_DQ54 (3)
M_B_DQ49 (3)
M_B_DQ53 (3)
M_B_DQ50 (3)
M_B_DQ51 (3)
M_B_DQ57 (3)
M_B_DQ56 (3)
M_B_DQ58 (3)
M_B_DQ62 (3)
M_B_DQ61 (3)
M_B_DQ60 (3)
M_B_DQ63 (3)
M_B_DQ59 (3)
DDR3_DRAMRST#(3,12)
+VREFDQ_SB_M3
M3 solution
R324 *10K_4
+3V
+SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM
R302 *Short_6
R307 2/F_6
1 2
+1.35VSUS
2.48A
+3V
PM_EXTTS#1
C415 *0.1u/16V_4
+SMDDR_VREF_DQ1
C397
0.022u/16V_4
R313
24.9/F_4
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199
77
122
125
198
30
1
126
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
DDR3-DIMM1_H=4.0_RVS
M1 solution
+1.35VSUS
R309
1.8K/F_4
R310
1.8K/F_4
JDIM1B
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
NC1
NC2
NCTE ST
EVENT#
RESET#
VREF_D Q
VREF_C A
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
Vref_DQ
+SMDDR_VREF_DQ1
PC2100 DDR3 SDRAM SO-DIMM
CHA
CHB
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
(204P)
VTT1
VTT2
GND
GND
C391
470p/50V_4
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
203
204
205
206
0 0
+VDDQ_VTT
SA0SA1
01
A A
C388
2.2u/6.3V_6
C390
0.1u/16V_4
5
C429
1u/6.3V_4
C396
1u/6.3V_4
C426
1u/6.3V_4
C395
1u/6.3V_4
C394
4.7U/10V_6
4
C417
4.7U/10V_6
C414
4.7U/10V_6
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
DDRIII Memory SO-DIMM B
DDRIII Memory SO-DIMM B
DDRIII Memory SO-DIMM B
PROJECT :
ZRW
ZRW
ZRW
3A
3A
3A
13 48Monday, July 20, 2015
13 48Monday, July 20, 2015
13 48Monday, July 20, 2015
1
1
2
3
4
5
6
7
8
+1.05V_GF X
A A
Near GPU
C605 EV@2 2U/6.3VS_6
C72 EV@22U/6.3VS _6
C78 EV@4.7U/10V_ 6
C111 EV@4 .7U/10V_6
C63 EV@4.7U/10V_ 6
C97 EV@1U/6.3V_4
C91 EV@1U/6.3V_4
Under GP U
PEX_IOVDD + PEX_IOVDDQ = 1.042A
+1.05V_GF X
PEX_PLL_HVDD +
PEX_SVDD_3V3 = 143mA
B B
100 ohm near GP U
C C
R72 EV @0_6
+1.05V_GF X
D D
Near GPU
Under GP U
1
C64 EV@22U/6.3VS _6
C87 *22U/6.3VS_6
C65 *10U/10V_6
C90 EV@4.7U/10V_ 6
C602 EV@4 .7U/10V_6
Near GPU
Under GP U
C119 EV@1 U/6.3V_4
C121 EV@1 U/6.3V_4
+3V_GFX
C131 EV @0.1U/16V_4
C135 EV@ 4.7U/10V_6
C132 E V@4.7U/10V_6
Near GPU
+VGPU_C ORE
VGA_VCC SENSE(41)
VGA_VSS SENSE(41)
R481 *200/F_ 4
PEX_TS TCLK
PEX_TS TCLK#
CX300T300 01 Change to 0ohm
PEX_PL LVDD
C80EV @4.7U/10V_6
C96EV@ 1U/6.3V_4
C92EV@ 0.1U/16V_4
PEX_PLLVDD = 130mA
EV@10K /F_4
R79
R473EV@ 2.49K/F_4
TESTMO DE
PEX_TE RMP
R123
EV@100 _4
R124
EV@100 _4
AA22
AB23
AC24
AD25
AE26
AE27
AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27
AA8
AA9
AB8
AF22
AE22
AA14
AA15
AD9
AF25
F2
F1
2
U34A
PEX_IOVD D
PEX_IOVD D
PEX_IOVD D
PEX_IOVD D
PEX_IOVD D
PEX_IOVD D
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_IOVD DQ
PEX_PLL _HVDD
PEX_PLL _HVDD
PEX_SVD D_3V3
VDD_SE NSE
GND_SEN SE
PEX_TST CLK_OUT
PEX_TST CLK_OUT
PEX_PLL VDD
PEX_PLL VDD
TESTMODE
PEX_TER MP
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1/14 PCI_EXPR ESS
PEX_WAK E
PEX_RST
PEX_CLK REQ
PEX_REF CLK
PEX_REF CLK
PEX_TX0
PEX_TX0
PEX_RX0
PEX_RX0
PEX_TX1
PEX_TX1
PEX_RX1
PEX_RX1
PEX_TX2
PEX_TX2
PEX_RX2
PEX_RX2
PEX_TX3
PEX_TX3
PEX_RX3
PEX_RX3
PEX_TX4
PEX_TX4
PEX_RX4
PEX_RX4
PEX_TX5
PEX_TX5
PEX_RX5
PEX_RX5
PEX_TX6
PEX_TX6
PEX_RX6
PEX_RX6
PEX_TX7
PEX_TX7
PEX_RX7
PEX_RX7
PEX_TX8
PEX_TX8
PEX_RX8
PEX_RX8
PEX_TX9
PEX_TX9
PEX_RX9
PEX_RX9
PEX_TX1 0
PEX_TX1 0
PEX_RX1 0
PEX_RX1 0
PEX_TX1 1
PEX_TX1 1
PEX_RX1 1
PEX_RX1 1
PEX_TX1 2
PEX_TX1 2
PEX_RX1 2
PEX_RX1 2
PEX_TX1 3
PEX_TX1 3
PEX_RX1 3
PEX_RX1 3
PEX_TX1 4
PEX_TX1 4
PEX_RX1 4
PEX_RX1 4
PEX_TX1 5
PEX_TX1 5
PEX_RX1 5
PEX_RX1 5
GF119GF1 17
COMMONbga595-nvidia -n13p-gv2-s-a2
3
AB6
AC7
AC6
AE8
AD8
AC9
AB9
AG6
AG7
AB10
AC10
AF7
AE7
AD11
AC11
AE9
AF9
AC12
AB12
AG9
AG10
AB13
AC13
AF10
AE10
AD14
AC14
AE12
AF12
AC15
AB15
AG12
AG13
AB16
AC16
AF13
AE13
AD17
AC17
AE15
AF15
AC18
AB18
AG15
AG16
AB19
AC19
AF16
AE16
AD20
AC20
AE18
AF18
AC21
AB21
AG18
AG19
AD23
AE23
AF19
AE19
AF24
AE24
AE21
AF21
AG24
AG25
AG21
AG22
C134 *0.1U/16V_ 4
VGA_RST #
PEX_CL KREQ#
PEG_RXP 0_C
PEG_RXN 0_C
PEG_RXP 1_C
PEG_RXN 1_C
PEG_RXP 2_C
PEG_RXN 2_C
PEG_RXP 3_C
PEG_RXN 3_C
R86 EV@0_4
R91 EV @10K/F_4
C632 EV@0 .22U/10V_4
C638 EV@0 .22U/10V_4
C627 EV@0 .22U/10V_4
C629 EV@0 .22U/10V_4
C626 EV@0 .22U/10V_4
C610 EV@0 .22U/10V_4
C609 EV@0 .22U/10V_4
C607 EV@0 .22U/10V_4
PLTRST #(8,23,25,2 6,29)
DGPU_H OLD_RST#(4)
N16V stuff it, not support GC6 2.0
GPU_PEX _RST_HOLD#(17)
PEX_CL KREQ#
4
PEGX_RS T# (17)
+3V_GFX
CLK_PC IE_VGA (6)
CLK_PC IE_VGA# (6)
PEG_RX0 (6)
PEG_RX# 0 ( 6)
PEG_TX0 (6)
PEG_TX# 0 (6)
PEG_RX1 (6)
PEG_RX# 1 ( 6)
PEG_TX1 (6)
PEG_TX# 1 (6)
PEG_RX2 (6)
PEG_RX# 2 ( 6)
PEG_TX2 (6)
PEG_TX# 2 (6)
PEG_RX3 (6)
PEG_RX# 3 ( 6)
PEG_TX3 (6)
PEG_TX# 3 (6)
+3V
EV@MC 74VHC1G08D FT2G
U10
2
1
SYS_PEX_ RST_MON#
SYS_PEX_ RST
R132 GM @0_4
GPU_PEX _RST_HOLD#
1
Q10
EV@2N 7002K
R92 *0_4
NVDD = 3 2.22 ~ 26. 66 A
C180
EV@0.1U /16V_4
4
SYS_PEX_ RST
3 5
SYS_PEX_ RST_MON# (17)
+3V
U7
GT@MC 74VHC1G08DF T2G
2
1
3 5
+3V_GFX
Follow Z09 to isolat e CLK_REQ #
2
3
5
Under GP U
C88 EV@1U/6.3V_4
C128 EV@1U /6.3V_4
C125 EV@1U /6.3V_4
C130 EV@1U /6.3V_4
C113 EV@4.7U /10V_6
C86 EV@4.7U/10V_6
C118 EV@4.7U /10V_6
C112 EV@4.7U /10V_6
C120 EV@4.7U /10V_6
C93 EV@4.7U/10V_6
C109 EV@4.7U /10V_6
C116 EV@4.7U /10V_6
C126 EV@4.7U /10V_6
C123 EV@4.7U /10V_6
12
+
C85
EV@330 u_2.5V_3528
C159 EV@22U /6.3V_8
C153 EV@47u /6.3V_8
C160 EV@4.7U /6.3VS_6
C140 EV@4.7U /6.3VS_6
C146 EV@4.7U /6.3VS_6
C149 EV@4.7U /6.3VS_6
C163 EV@4.7U /6.3VS_6
Near GPU
R143 EV @0_4
C175
GT@0.1U/1 6V_4
4
PEGX_RS T#
CLK_PE GA_REQ# (6)
PU at page 9
+VGPU_C ORE
K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
P14
P16
P18
R11
R13
R15
R17
T10
T12
T14
T16
T18
U11
U13
U15
U17
V10
V12
V14
V16
V18
SYS_PEX_ RST_MON#
R142
GT@100K /F_4
R114
EV@100 K/F_4
U34E
11/14 NVVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
bga595-nvidia -n13p-gv2-s-a2
COMMON
6
AD10
AD7
B19
F11
TP5
V5
V6
G1
G2
G3
G4
G5
G6
G7
V1
V2
W1
W2
W3
W4
ALL 3.3V
+3VGFX & +3V3_AON
+VGACORE
PEX_VDD
+1.05V_GFX
FBVDDQ
+1.5V_GFX
U34C
14/14 XVDD/VDD 33
NC
NC
NC
3V3AUX_ NC
FERMI_RS VD1_NC
FERMI_RS VD2_NC
CONFIGURABLE
POWER CHAN NELS
* nc on substrate
XPWR_G1
XPWR_G2
XPWR_G3
XPWR_G4
XPWR_G5
XPWR_G6
XPWR_G7
XPWR_V1
XPWR_V2
XPWR_W1
XPWR_W2
XPWR_W3
XPWR_W4
bga595-nvidia -n13p-gv2-s-a2 COMMON
t>0NVVDD
Size Docu ment Number Rev
Size Docu ment Number Rev
Size Docu ment Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
7
N16S-GT (PCIE I/F) /NVDD
N16S-GT (PCIE I/F) /NVDD
N16S-GT (PCIE I/F) /NVDD
Monday, July 20, 20 15
Monday, July 20, 20 15
Monday, July 20, 20 15
VDD33 = 56mA
G10
VDD33
VDD33
VDD33
VDD33
G12
G8
G9
+3V_GFX
C117 EV@0.1U /16V_4
C145 EV@ 4.7U/10V_6
1 2
C138 EV@ 1U/10V_6
C143 EV@ 4.7U/10V_6
1 2
C137 EV@ 1U/10V_6
C124 EV@0 .1U/16V_4
C127 EV@0 .1U/16V_4
Under GP U
+3V_MA IN
Under GP U
Power up
sequence
t>=0
Power down
sequence
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZRW
ZRW
ZRW
14 48
14 48
14 48
8
Near GPU
3A
3A
3A
1
R525 EV@ 10K/F_4
FBA_CM D0
A A
FBA_ODT _L
FBA_CKE _L
FBA_ODT _H
FBA_CKE _H
FBA_RST #
B B
C C
FB_PLLAVDD = 55mA
+1.05V_GF X
D D
+1.5V_GFX
EV@BLM 15PX330SN 1DEV_4
L1
C79 EV@22U/6.3VS _6
C76 EV@0.1U/16V_ 4
C89 EV@0.1U/16V_ 4
C77 EV@0.1U/16V_ 4
FBA_CM D3
FBA_CM D16
FBA_CM D19
FBA_CM D20
VMA_C LK0(18,19)
VMA_C LK0#(18,19)
VMA_C LK1(18,19)
VMA_C LK1#(18,19)
R60 EV @10K/F_4
R59 EV @10K/F_4
R47 EV @10K/F_4
R43 EV @10K/F_4
R453 EV@ 10K/F_4
FBA_CM D0(18,1 9)
FBA_CM D1(19)
FBA_CM D2(18)
FBA_CM D3(18,1 9)
FBA_CM D4(18,1 9)
FBA_CM D5(18,1 9)
FBA_CM D6(18,1 9)
FBA_CM D7(18,1 9)
FBA_CM D8(18,1 9)
FBA_CM D9(18,1 9)
FBA_CM D10(18,19)
FBA_CM D11(18,19)
FBA_CM D12(18,19)
FBA_CM D13(18,19)
FBA_CM D14(18,19)
FBA_CM D15(18,19)
FBA_CM D16(18,19)
FBA_CM D17(19)
FBA_CM D18(18)
FBA_CM D19(18,19)
FBA_CM D20(18,19)
FBA_CM D21(18,19)
FBA_CM D22(18,19)
FBA_CM D23(18,19)
FBA_CM D24(18,19)
FBA_CM D25(18,19)
FBA_CM D26(18,19)
FBA_CM D27(18)
FBA_CM D28(18,19)
FBA_CM D29(18,19)
FBA_CM D30(19)
R80 *60.4 _4
R87 *60.4 _4
+FB_PLL AVDD
FB_DLLAVDD = 15mA
1
PS_FB_C LAMP
2
F3
C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26
F22
J22
D24
D25
N22
M22
D18
C18
D17
D16
T24
U24
V24
V25
F16
P22
H22
2
U34B
FB_CLAMP
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_DEBUG0
FBA_DEBUG1
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBA_WCK0 1
FBA_WCK0 1
FBA_WCK2 3
FBA_WCK2 3
FBA_WCK4 5
FBA_WCK4 5
FBA_WCK6 7
FBA_WCK6 7
FB_PLLAVDD
FB_PLLAVDD
FB_DLLAVDD
INT
bga595-nvidia -n13p-gv2-s-a2
GF119NC
GF117
GF119
GF117FB_PLL AVDD
3
3
2/14 FBA
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_W P0
FBA_DQS_W P1
FBA_DQS_W P2
FBA_DQS_W P3
FBA_DQS_W P4
FBA_DQS_W P5
FBA_DQS_W P6
FBA_DQS_W P7
FBA_DQS_RN 0
FBA_DQS_RN 1
FBA_DQS_RN 2
FBA_DQS_RN 3
FBA_DQS_RN 4
FBA_DQS_RN 5
FBA_DQS_RN 6
FBA_DQS_RN 7
FB_VREF_PR OBE
COMMON
E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W2 6
Y25
R26
T25
N27
R27
V26
V27
W2 7
W2 5
D19
D14
C17
C22
P24
W2 4
AA25
U25
E19
C15
B16
B22
R25
W2 3
AB26
T26
F19
C14
A16
A22
P25
W2 2
AB27
T27
D23
VMA_D Q0
VMA_D Q1
VMA_D Q2
VMA_D Q3
VMA_D Q4
VMA_D Q5
VMA_D Q6
VMA_D Q7
VMA_D Q8
VMA_D Q9
VMA_D Q10
VMA_D Q11
VMA_D Q12
VMA_D Q13
VMA_D Q14
VMA_D Q15
VMA_D Q16
VMA_D Q17
VMA_D Q18
VMA_D Q19
VMA_D Q20
VMA_D Q21
VMA_D Q22
VMA_D Q23
VMA_D Q24
VMA_D Q25
VMA_D Q26
VMA_D Q27
VMA_D Q28
VMA_D Q29
VMA_D Q30
VMA_D Q31
VMA_D Q32
VMA_D Q33
VMA_D Q34
VMA_D Q35
VMA_D Q36
VMA_D Q37
VMA_D Q38
VMA_D Q39
VMA_D Q40
VMA_D Q41
VMA_D Q42
VMA_D Q43
VMA_D Q44
VMA_D Q45
VMA_D Q46
VMA_D Q47
VMA_D Q48
VMA_D Q49
VMA_D Q50
VMA_D Q51
VMA_D Q52
VMA_D Q53
VMA_D Q54
VMA_D Q55
VMA_D Q56
VMA_D Q57
VMA_D Q58
VMA_D Q59
VMA_D Q60
VMA_D Q61
VMA_D Q62
VMA_D Q63
VMA_D M0
VMA_D M1
VMA_D M2
VMA_D M3
VMA_D M4
VMA_D M5
VMA_D M6
VMA_D M7
VMA_W DQS0
VMA_W DQS1
VMA_W DQS2
VMA_W DQS3
VMA_W DQS4
VMA_W DQS5
VMA_W DQS6
VMA_W DQS7
VMA_R DQS0
VMA_R DQS1
VMA_R DQS2
VMA_R DQS3
VMA_R DQS4
VMA_R DQS5
VMA_R DQS6
VMA_R DQS7
TP2
4
VMA_D Q[63:0]
FBVDDQ + FBVDD = 3.116A
C71 EV@0.1U/16V_4
C82 EV@0.1U/16V_4
1 2
C95 EV@ 1U/10V_6
1 2
C74 EV@ 1U/10V_6
C73 EV@4.7U/10V_6
C69 EV@4.7U/10V_6
C84 EV@10U/6.3V_6
C83 EV@22U/6.3V_8
VMA_D M[7:0] (18,19 )
VMA_W DQS[7:0] (18,19)
VMA_R DQS[7:0] (18,19)
4
5
VMA_D Q[63:0] (18,19)
+1.5V_GFX
FBA_CM D4
R458EV@100/F _4
FBA_CM D5
R461EV@100/F _4
FBA_CM D6
FBA_CM D7
R50EV@100/F_ 4
FBA_CM D8
R445EV@100/F _4
FBA_CM D9
R41EV@100/F_ 4
FBA_CM D10
R22EV@100/F_ 4
FBA_CM D11
R62EV@100/F_ 4
FBA_CM D12
R455EV@100/F _4
FBA_CM D13
R24EV@100/F_ 4
FBA_CM D14
R451EV@100/F _4
FBA_CM D15
R64EV@100/F_ 4
FBA_CM D21
R21EV@100/F_ 4
FBA_CM D22
R30EV@100/F_ 4
FBA_CM D23
R18EV@100/F_ 4
FBA_CM D24
R40EV@100/F_ 4
FBA_CM D25
R55EV@100/F_ 4
FBA_CM D26
R27EV@100/F_ 4
FBA_CM D27
R31EV@100/F_ 4
FBA_CM D28
R54EV@100/F_ 4
FBA_CM D29
R49EV@100/F_ 4
FBA_CM D30
R35EV@100/F_ 4
5
U34D
12/14 FBVDDQ
B26
FBVDDQ
C25
FBVDDQ
E23
FBVDDQ
E26
FBVDDQ
F14
FBVDDQ
F21
FBVDDQ
G13
FBVDDQ
G14
FBVDDQ
G15
FBVDDQ
G16
FBVDDQ
G18
FBVDDQ
G19
FBVDDQ
G20
FBVDDQ
G21
FBVDDQ
H24
FBVDDQ
H26
FBVDDQ
J21
FBVDDQ
K21
FBVDDQ
L22
FBVDDQ
L24
FBVDDQ
L26
FBVDDQ
M21
FBVDDQ
N21
FBVDDQ
R21
FBVDDQ
T21
FBVDDQ
V21
FBVDDQ
W2 1
FBVDDQ
bga595-nvidia -n13p-gv2-s-a2
COMMON
FB_CAL_PD _VDDQ
FB_CAL_PU _GND
FB_CALTER M_GND
R459EV@100/F_ 4
R462EV@100/F_ 4
R46EV@100/F_4R45EV@100/F_ 4
R51EV@100/F_4
R446EV@100/F_ 4
R42EV@100/F_4
R23EV@100/F_4
R61EV@100/F_4
R456EV@100/F_ 4
R25EV@100/F_4
R452EV@100/F_ 4
R63EV@100/F_4
R20EV@100/F_4
R29EV@100/F_4
R17EV@100/F_4
R39EV@100/F_4
R56EV@100/F_4
R26EV@100/F_4
R32EV@100/F_4
R57EV@100/F_4
R48EV@100/F_4
R36EV@100/F_4
D22
C24
B25
+1.5V_GFX
6
FB_CAL _PD_VDDQ
FB_CAL _PU_GND
FB_CAL _TERM_GND
R84 EV @40.2/F_4
R73 EV @42.2/F_4
R71 EV @51.1/F_4
For supp ort GC6 1.0
For supp ort GC6 2.0
EC_FB_ CLAMP(17,29)
GC6_FB_ EN(4,17)
GPU_PW R_GD(4 1)
6
7
U34F
13/14 GND
A2
GND
AB17
GND
AB20
GND
AB24
GND
AC2
GND
AC22
GND
AC26
GND
AC5
GND
AC8
GND
AD12
GND
AD13
GND
A26
GND
AD15
GND
AD16
GND
AD18
GND
AD19
GND
AD21
GND
AD22
GND
AE11
GND
AE14
GND
AE17
GND
AE20
GND
AB11
GND
AF1
GND
AF11
GND
AF14
GND
AF17
GND
AF20
GND
AF23
GND
AF5
GND
AF8
GND
AG2
GND
AG26
GND
AB14
GND
B1
GND
B11
GND
B14
GND
B17
GND
B20
GND
B23
GND
B27
GND
B5
GND
B8
GND
E11
GND
E14
GND
E17
GND
E2
GND
E20
GND
E22
GND
E25
GND
E5
GND
E8
GND
H2
GND
H23
GND
H25
GND
H5
+1.5V_GFX
GND
K11
GND
K13
GND
K15
GND
K17
GND
L10
GND
L12
GND
L14
GND
L16
GND
L18
GND
L2
GND
L23
GND
L25
GND
L5
GND
M11
GND
bga595-nvidia -n13p-gv2-s-a2 COMMON
+3V
C177
R140 *0_4
R139 GT@0 _4
2
1
GT@NL1 7SZ32DFT2G
U9
3 5
GT@0.1U/1 6V_4
4
R137 GM@ 0_4
N16V stuff it, not sup port GC6 2. 0
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Docu ment Number Rev
Size Docu ment Number Rev
Size Docu ment Number Rev
Date: Sheet of
Monday, July 20, 20 15
Date: Sheet of
Monday, July 20, 20 15
Date: Sheet of
Monday, July 20, 20 15
7
PROJECT :
N16S-GT (MEMORY/GND)
N16S-GT (MEMORY/GND)
N16S-GT (MEMORY/GND)
R126
EV@100 K/F_4
ZRW
ZRW
ZRW
8
M13
GND
M15
GND
M17
GND
N10
GND
N12
GND
N14
GND
N16
GND
N18
GND
P11
GND
P13
GND
P15
GND
P17
GND
P2
GND
P23
GND
P26
GND
P5
GND
R10
GND
R12
GND
R14
GND
R16
GND
R18
GND
T11
GND
T13
GND
T15
GND
T17
GND
U10
GND
U12
GND
U14
GND
U16
GND
U18
GND
U2
GND
U23
GND
U26
GND
U5
GND
V11
GND
V13
GND
V15
GND
V17
GND
Y2
GND
Y23
GND
Y26
GND
Y5
GND
AA7
GND
AB7
GND
FBVDDQ _EN (42)
15 48
15 48
15 48
8
3A
3A
3A
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