Acer Aspire ES1-521, Aspire ES1-522 Schematics

A

B C D

E

Com

1 1

2 2

pal Confidential

Mod

el Name : Bellemere_BE

Com

pal Project Name : B5W1E

File Name : LA-D121P

Comp

al Confidential

B5W1E Schematics Document

AM

D "Beema" Platform

D 15W APU With Puma+ Core

3 3

LA-D121P REV: 1.0

2015-04-16

4 4

Sec

urity Classification

ued Date

Iss

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

2014/03/27 2016/03/27

Com

pal Secret Data

Deciphered Date

Co

mpal Electronics, Inc.

le

Tit

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

mpal Electronics, Inc.

CO

B5W

uesday, April 21, 2015

B5W

ER PAGE

V

1E_LA-D121P

133T

E

1.0

A

B

C

D

E

Com

1 1

pal Confidential

Mod

el Name : B5W1E

5W1K

B B

5W1R

Display Port

Port 0Port 1

AMD Beema/ Kabini/

Memory BUS(DDR3) Single Channel

1.5V

DDRIII 1600MHz

USB2.0

or

t 8

P

204pin

DDR3-SO-DIMM X2

Page 10,11

or

t 2

P

or

t 3Port 0

P

or

t 5

P

Carrizo-L

Sub B

HDMI

Conn.

Page 13

2 2

MIN

I Card

(WLAN/BT)

Page 17

Fan

Control

3 3

DC/

DC Interface CKT.

r Circuit DC/DC

Powe

Sub B

B471P

LS-

Page

oard

Page 22

Page

24

24~33

eDP Conn.

LAN

(GbE)

RTL

Tra RJ45

Pag

e 12

GPP

8111GUS

Page 15

nsformer

Page 15

AMD

FT3b APU

USB3.0

Por

MB 2.0 Conn.

t 0

BT M

Pag

e 19 Page 17 Page 12 Page 12

ini Card

USB

Camera

Touch Screen

Puma+ Core

PCIE

1GPP2

BGA 769-balls

SPI L

PC

Page

5~9

HD Audio(AZ)

SATA III

BIOS (8M)

8

Page

HDD Conn.

ENE

U3.

0 Conn.

Page 19

Por

t 0 Port 1

Pag

e 18

ODD C

onn.

Pag

e 18

Audio ALC233-VB2

Page

USB

16

KBC9022

Page 14

Un

versal Jack

i

Touch PadInt.KBD

Page 20Page 20

Page 16

Int

. Speaker

Conn.

Page 16

Ana

log MIC

Page

16

oard

Port 1

2.0 Conn.

LS-B471P

Card Reader RTS5170 SD only

Pag

Port 4

e 19

s

crete TPM

Card Reader

RTS5170

4 4

2 in 1 (

SD)

2.0

USB conn x1

USB

port 2

P.21

A

B

Di

Page 20

Sec

urity Classification

ued Date

Iss

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2014/03/27 2016/03/27

Com

pal Secret Data

Deciphered Date

D

Co

mpal Electronics, Inc.

le

Tit

Size Document Number Rev

Cus

tom

Date: Sheet of

mpal Electronics, Inc.

BL

CK DIAGRAMS

O

1E_LA-D121P

B5W

233Thursday, April 16, 2015

E

233Thursday, April 16, 2015

1.0

5

D D

AC ADAPTOR 19V 65W

VIN

PU301 CHARGER BQ24725ARGRR

BAT

T+

BAT

TERY

HDMI

+5V

C C

B B

S_DISP

1

HDD x ODD x1

S_HDD @ 1.1A

+5V +5VS_ODD @ 2A

io

Aud ALC233-VB2-CG

+AVDD1_HDA +PVDD_HDA +3VS_DVDD +1.5VS_VDDA +1.5VS_DVDDIO

FAN

+VCC_FAN1

USB2.0 x1 USB3.0 x1

+USB3_VCCA

+5VS

+5VS +3VS +1.5VS

+5VS

+5VALW

EC

+EC_VCC

panel

LCD 14"

+INVPWR_B+ +LCDVDD @ 1.4A

+3VLP

+19VB +3VS

4

VB

+19

PU1000

8880CGQW

RT

PU501

8207PGQW

RT

PU601 SY8288RAC

PU401 SY8286BRAC

3

+1.5V

+0.75VS

+0.95VALW

PU602 SY8003DFC

+3VALW

+5VALW

DDRIII SODIMMX2

RAM

5V

+1.

+0.75VS

+APU_CORE

+APU_CORE_NB

+1.8VALW

U2 EM5209VF

VDD_MEM 8A

VTT_MEM 2A

U4

304L

AO4

U3 EM5209VF

+3VS

+5VS

2

+1.8VS

+1.5VS

+0.95VS

AMD

APU FT3b Beema (15W )

+0

5~+1.4V

.

+0.

7~1.325V

+1.5V

VDDCR_CPU @ 21A(EDC)

VDDCR_NB @ 17A(EDC)

VDDIO_MEM_S @ 3A

VDDIO_AZ_ALW @ 0.1A+1.5VS

+0.95VALW

+0.95VS

+1.8VS

+1.8VALW

+3VALW

VDD_095_USB3_Dual @ 1A

VDD_095_ALW @ 0.5A

VDD

_095 @ 5A

VDD_095_GFX @ 0.6A

VDD_18 @ 1.5A

VDD_18_ALW @ 0.5A

VDD_33_ALW @ 0.2A

+3VS VDD_33 @ 0.2A

1

+1.5V_RTC VDDBT_RTC_G @ 4.5uA

PU402 SY8286CRAC

+RTC_APU

PU101 AP

2138N-1.5TRG1

+RTCCONN

RTC Bettary

/CR Combo

LAN RTL8411B-CG

+3V

A A

_LAN @ 1A

Card(WLAN)

M.2

S_WLAN @ 2A

+3V

+3VALW

5

HD Camera

+3V

S_CMOS

ch Screen

Tou

S_TS

+5V

+3VS

+5VS

Security Classificati on

Issued Date

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2014/03/27 2016/03/27

3

Com

pal Secret Data

Deciphered Date

Co

pal Electronics, Inc.

m

le

Tit

Size Documen t Number Rev

B

Date: Sheet of

2

Date: Sheet of

m

POW

B5W

ursday, April 16, 2015

ER MAP

1E_LA-D121P

1

1.0

333Th

A

tage Rails

Vol

VIN

B+

+AP

U_CORE OFFON

1 1

+0.95VALW

+0.95VS

+1.8VALW

+1.8VS

+1.5V

+1.5VS

+3VALW

+3V

S

+5VALW ON

+5VS

+RTC_APU

2 2

us List

SMB

EC

SMBus Port1 (+3VALW)

rt Battery

Sma

3 3

4 4

SMBus Port0 (+3VS)

APU

DDR DI

MM1

DDR DI

MM2

ZZZ

PC

B

t Number = DAZ1GS00100

Par PCB B5W1E LA-D121P LS-D121P

ZZZ

HDMI_ROYALTY

ROY

ALTY HDMI W/LOGO+HDCP

RO0

000003HM

45@

DescriptionPower Plane

Adapte r power supply (19V)

AC or batter y power rail fo r power circuit .

Core voltage f or APU

Vol

tage for On-die VGA of APU OFFOFFON+APU_CORE_NB

0.95V always on power rail

0.95V switched power rail

1.8V always on power rail

1.8V switched power rail

1.5V power rail for APU and DDR

1.5V switched power rail

0.75V switched power rail for DDR terminator

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

EC

SMBus Port2 (+3VS)

ice HEXAddres s

Dev

HEXAddres sDevice

b

0001 011X

Add

ressDevice

1010 000X

1010 001X

U44

EC

t Number = SA000075S30

Par S IC KB9022QD LQFP 128P EC CONTROLLER

A

16H

HEX

b

A0

b

A2H

9022@

SI (APU)

SB-T

SMBus Port1(+3VALW)

APU

Dev

ice Address

H

1001 100X

B C D

Boa

rd ID / SKU ID Table for AD channel

S5S3S0

ONONON

ON ON

ON

ON+0.75VS

ON OFFOFF

OFF

ONON

ON

OFFON

OFF

ON ON

OFFOFFON

ON OFFON

OFFON OFF

OFF OFF

ON

ONON

OFFOFFON

ONON

ONONON

Structure Table

BOM

BTO ItemBOM Structure

@ CONN@

b

98H

KBN@ BMA@ CZL@ 233@ 255@ 283@ EMC@ @EMC@ SP@

HEX

HDT@ RS@ 45@ 9012@ 9022@ BL@ TPM@ ECI2C@ TPUSB@ BYOC@ NBYOC@

JP@ TP@

Unpop

Connector part control by ME

Stuff when use Kabini APU

Stuff when use Beema APU

Stuff when use CZ-L APU

Use for Audio Codec ALC233-VB2

Use for Audio Codec ALC255

Use for Audio Codec ALC283

EMI pop component

EMI unpop component

Short pad for clear CMOS

HDT+ for test phase, MP remove

R-short

HDMI royalty

Use KBC9012

Use KBC9022

Keyboard backlight

Use discrete TPM module

Use EC I2C T/P

Use USB to I2C IC for T/P

Stuff when support BYOC

Stuff when non-support BYOC

Jump

Test point

Sec

urity Classification

ued Date

Iss

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

2014/03/27 2016/03/27

Com

pal Secret Data

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

APU POWER SEQUENCE

G-A

G-B

G-C

G-D

G-E

Deciphered Date

+RTC

EC_ON

+3VALW/+5VALW

+1.8VALW

+0.95VALW

SYSON

+1.5V

SUSP#

+3VS

+1.8VS

+1.5VS

+0.95VS

VR_ON

+APU_CORE

+APU_CORE_NB

D

E

BOARD

Board ID

ID Table

12 13 14* 15

PCB Revision EVT DVT PVT

Pre-MP

16 17 18 19

SLP_S3#

HIGH HIGH

LOW

LOWS5 (Soft OFF)

re check

Tit

Size Document Number Rev

B

Date: Sheet of

+VALWSLP_S5# +VS+V Clock

ON

HIGHHIGH

HIGH

le

ON

OFF

ONLOW

OFF

Co

mpal Electronics, Inc.

NO

B5W

uesday, April 21, 2015

B5W

ON

OFF

ES LIST

T

1E_LA-D121P

E

ONON

LOW

OFF

1.0

433T

1.0

5

@

U1A

_SMA[15..0]<10,11>

DDRAB

D D

_SBS0#<10,11>

DDRAB

_SBS1#<10,11>

DDRAB DDRAB

_SBS2#<10,11>

DDRAB

_SDM[7..0]<10,11>

C C

B B

A A

MEM_

DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRA DDRAB DDRAB DDRAB_SDQS6<10,11> DDRAB DDRAB DDRAB

DDRA_ DDRA_ DDRA_CLK1<10> DDRA_ DDRB_ DDRB DDRB_ DDRB_

MAB_RST #<10,11>

MAB_EVEN T#<10,11>

DDRA_ DDRA_ DDRB DDRB_

DDRA_ DDRA_ DDRB_ DDRB_

DDRAB DDRAB DDRAB

+ME

_SDQS0<10,11> _SDQS0#<10,11> _SDQS1<10,11> _SDQS1#<10,11> _SDQS2<10,11> _SDQS2#<10,11> _SDQS3<10,11> _SDQS3#<10,11> _SDQS4<10,11>

B

_SDQS4#<10,11> _SDQS5<10,11> _SDQS5#<10,11>

_SDQS6#<10,11> _SDQS7<10,11> _SDQS7#<10,11>

CLK0<10> CLK0#<10>

CLK1#<10> CLK0<11>

_

CLK0#<11> CLK1<11> CLK1#<11>

CKE0<10> CKE1<10>

_

CKE0<11> CKE1<11>

ODT0<10> ODT1<10> ODT0<11> ODT1<11>

SCS0#<10> SCS1#<10> SCS0#<11> SCS1#<11>

_SRAS#<10,11> _SCAS#<10,11> _SWE#<10,11>

M_VREF

T33

5

DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB

DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB DDRAB

APU_

_SMA0 _SMA1 _SMA2 _SMA3 _SMA4 _SMA5 _SMA6 _SMA7 _SMA8 _SMA9 _SMA10 _SMA11 _SMA12 _SMA13 _SMA14 _SMA15

_SDM0 _SDM1 _SDM2 _SDM3 _SDM4 _SDM5 _SDM6 _SDM7

VREFDQ

UAP

AG3

8 W35 W38 W34 U38 U37 U34 R35 R38 N38

AG3

4 R34 N37

AN34

L38 L35

8

AJ3

AG3

5 N34

B32

B38 G40 N41

AG4

0 1

AN4

0

AY4 AY3

4

Y40

B33

A33

B40

A40 H41 H40

P41

P40

AH4

1

AH4

0 AP41 AP40 BA40 AY4

1 AY3

3 BA34 AA40

Y41

AC3

5

4

AC3 AA34 AA32 AE38 AE37 AA37 AA38

G38

AE34

L34 J38 J37 J34

8

AN3 AU3

8 AN3

7 AR3

7

4

AJ3

AR3

8

AL3

8 AN3

5

7

AJ3 AL3

4

AL3

5

0

AD4

8

AC3

FT3_BGA_769P-T

Part Number =

M_ADD0

ADD1

M_

ADD2

M_ M_

ADD3

M_

ADD4

M_

ADD5 ADD6

M_

ADD7

M_ M_

ADD8

M_

ADD9

M_ADD1 0

ADD11

M_

ADD12

M_ M_ADD1 3 M_A

DD14

M_A

DD15

M_BANK0 M_BANK1 M_

BANK2

DM0

M_

DM1

M_ M_

DM2

M_

DM3 M_DM4 M_DM5 M_DM6 M_DM7 M_

DM8

DQS_H 0

M_

DQS_L 0

M_ M_

DQS_H 1 M_

DQS_L 1 M_

DQS_H 2

DQS_L 2

M_

DQS_H 3

M_ M_

DQS_L 3 M_DQS_ H4 M_DQS_ L4

DQS_H 5

M_

DQS_L 5

M_ M_

DQS_H 6 M_DQS_ L6 M_DQS_ H7

DQS_L 7

M_

DQS_H 8

M_ M_

DQS_L 8

M_CLK_ H0 M_CLK_ L0

CLK_H 1

M_ M_

CLK_L 1 M_

CLK_H 2 M_

CLK_L 2

CLK_H 3

M_

CLK_L 3

M_

RESET _L M_

EVENT _L

CKE0

M0_ M0

_CKE1 M1

_CKE0 M1

_CKE1

M0_ODT 0 M0_ODT 1 M1_ODT 0 M1_ODT 1

M0_CS_ L0 M0_CS_ L1 M1_CS_ L0 M1_CS_ L1

M_RAS_ L M_CAS_ L M_WE_ L

M_VREF M_VREFD Q

MEMO

RY

M_ZVDD IO_MEM_S

4

M_

DATA0 DATA1

M_

DATA2

M_ M_

DATA3

M_

DATA4

M_

DATA5 DATA6

M_

DATA7

M_

DATA8

M_

DATA9

DATA1 0

M_

DATA1 1

M_ M_DAT A12 M_

DATA1 3

M_

DATA1 4

M_

DATA1 5

M_

DATA1 6

M_

DATA1 7

M_

DATA1 8 DATA1 9

M_

DATA2 0

M_ M_

DATA2 1

M_

DATA2 2

M_

DATA2 3

DATA2 4

M_ M_

DATA2 5

M_

DATA2 6

M_

DATA2 7

M_

ATA28

D DATA2 9

M_ M_

DATA3 0

M_

DATA3 1

M_DAT A32 M_DAT A33 M_

DATA3 4

M_

DATA3 5

M_

DATA3 6 DATA3 7

M_ M_DAT A38 M_DAT A39

M_DAT A40 M_DAT A41 M_DAT A42 M_DAT A43 M_DAT A44 M_DAT A45 M_DAT A46 M_DAT A47

M_

DATA4 8

M_DAT A49

DATA5 0

M_ M_DAT A51 M_DAT A52 M_

DATA5 3 M_DAT A54 M_DAT A55

M_

DATA5 6 M_DAT A57 M_

DATA5 8 M_DAT A59

DATA6 0

M_ M_DAT A61 M_

DATA6 2 M_DAT A63

CHECK 0

M_ M_

CHECK 1

M_

CHECK 2

M_CHEC K3

CHECK 4

M_

CHECK 5

M_ M_

CHECK 6

M_

CHECK 7

4

B30 A32 B35 A36 B29 A30 A34 B34

B37 A38 D40 D41 B36 A37 B41 C4

F40 F41 K40 K41 E40 E41 J40 J41

M41 N40 T41 U40 L40 M40 R40 T40

AF4 AF4 AK40 AK41 AE40 AE41 AJ4 AJ4

AM4 AN4 AT4 AU4 AL4 AM4 AR4 AT4

AV41 AW4 BA38 AY3 AU4 AV40 AY3 AY3

BA36 AY3 BA32 AY3 BA37 AY3 BA33 AY3

V41 W40 AB40 AC4 U41 V40 AA41 AB41

AD4

3

_SDQ[63..0] <10,11>

1 2

R74

39.

2_0402_1%

DDRAB

Beema

E_ARX_DTX_P1<15>

PCI

E_ARX_DTX_N1<15>

PCI

E_ARX_DTX_P2<17>

I

E_ARX_DTX_N2<17>

PC

95VS

+0.

1 2

R40

1.69K_0402_1%

+1.

UAP

U1

CZ-L

AM7210ITJ44JB 1.8G BG A 769P

A4_7210@

SA00008R420

UAP

U1

EM6010IUJ23JB 1.35G BG A 769P

E1_6010@

SA00007RC20

@

UAP

U1B

R10

P_

GPP_RXP0

R8

P_G

PP_RXN0

R5

P_

PP_RXP1

G

R4

PP_RXN1

P_G

N5

P_G

PP_RXP2

N4

P_G

PP_RXN2

N10

GPP_RXP3

P_

N8

P_G

PP_RXN3

X_ZVDD_095

P_T

4

5V

2014/03/27 2016/03/27

W8

P_T

X_ZVDD_095

L5

P_G

FX_RXP0

L4

G

FX_RXN0

P_

J5

FX_RXP1

P_G

J4

P_G

FX_RXN1

G5

G

FX_RXP2

P_

G4

FX_RXN2

P_G

D7

P_G

FX_RXP3

E7

P_G

FX_RXN3

FT3_BGA_769P-T

Part Number =

Com

pal Secret Data

Deciphered Date

3

UAP

U1

EM6110ITJ44JB 1.5G BG A 769P

E2_6110@

SA00007RB20

E

PCI

P_G P_G

P_

LAN

WLAN

P_G

P_G P_

P_G P_G

R

X_ZVDD_095

P_

P_G P_

P_G P_G

P_ P_G

P_G P_G

G

PP_TXP0 PP_TXN0

PP_TXP1 PP_TXN1

PP_TXP2 PP_TXN2

PP_TXP3 PP_TXN3

FX_TXP0

G

FX_TXN0

FX_TXP1 FX_TXN1

G

FX_TXP2 FX_TXN2

FX_TXP3 FX_TXN3

L2 L1

K2 K1

J2 J1

H2 H1

W7

G2 G1

F2 F1

E2 E1

D2 D1

_SDQ0

DDRAB DDRAB

_SDQ1

DDRAB

_SDQ2 _SDQ3

DDRAB

_SDQ4

DDRAB

_SDQ5

DDRAB DDRAB

_SDQ6

DDRAB

_SDQ7

_SDQ8

DDRAB

_SDQ9

DDRAB DDRAB

_SDQ10

DDRAB

_SDQ11 _SDQ12

DDRAB

_SDQ13

DDRAB

_SDQ14

DDRAB

0

DDRAB

_SDQ15

_SDQ16

DDRAB

_SDQ17

DDRAB

_SDQ18

DDRAB DDRAB

_SDQ19

DDRAB

_SDQ20 _SDQ21

DDRAB

_SDQ22

DDRAB

_SDQ23

DDRAB

_SDQ24 _SDQ25

DDRAB

_SDQ26

DDRAB

_SDQ27

DDRAB DDRAB

_SDQ28

DDRAB

_SDQ29 _SDQ30

DDRAB

_SDQ31

DDRAB

0

DDRAB

_SDQ32

1

DDRAB

_SDQ33 _SDQ34

DDRAB

_SDQ35

DDRAB

_SDQ36

DDRAB DDRAB

_SDQ37

0

DDRAB

_SDQ38

1

_SDQ39

DDRAB

1

_SDQ40

DDRAB

0

DDRAB

_SDQ41

1

DDRAB

_SDQ42

0

_SDQ43

DDRAB

0

_SDQ44

DDRAB

0

_SDQ45

DDRAB

0

DDRAB

_SDQ46

0

DDRAB

_SDQ47

_SDQ48

DDRAB

0

_SDQ49

DDRAB DDRAB

_SDQ50

7

DDRAB

_SDQ51

1

_SDQ52

DDRAB

_SDQ53

DDRAB

9

_SDQ54

DDRAB

8

DDRAB

_SDQ55

_SDQ56

DDRAB

5

_SDQ57

DDRAB

_SDQ58

DDRAB

1

DDRAB

_SDQ59

DDRAB

_SDQ60

6

_SDQ61

DDRAB

_SDQ62

DDRAB

2

_SDQ63

DDRAB

0

VDDIO

M_Z

Security Classificati on

1

Issued Date

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

KABINI

UAP

U1

AM7310ITJ44JB 2G FC BGA 769P

A6_7310@

SA00008K930

UAP

U1

AM6210ITJ44JB 1.8G BG A 769P

A4_6210@

SA00007RA20

PCI

E_ATX_DRX_P1

PCI

E_ATX_DRX_N1

E_ATX_DRX_P2

PCI

E_ATX_DRX_N2

PCI

X_ZVDD_095

P_R

+1.5V

2

12

1 2

9 .

C1

1 2

C20 .

1 2

C17 .

1 2

C18 .

R73 1K

_0402_1%

R75 1K

_0402_1%

R76

_0402_1%

1K

le

Tit

Size Documen t Number Rev

B

Date: Sheet of

1

UAP

U1

EM2100CJ23HM 1G BGA7 69

E1_2100@

SA00

006QX70

UAP

U1

AM7410ITJ44JB 2.2G F CBGA 769P

A8_7410@

SA00008K660

UAP

U1

AM6310ITJ44JB 1.8G BG A 769P

A6_6310@

SA00007R920

1U_0402_16V7K 1U_0402_16V7K

95VS

+0.

12

UAP

EM2500BJ23HM 1.4G BGA

E1_2500@

SA00

UAP

U1

EM7110ITJ44JB 1.8G F CBGA 769P

E2_7110@

SA00008MA20

UAP

U1

AM6410ITJ44JB 2G BGA 7 69P

A8_6410@

SA00007TQ80

E_ATX_C_DRX_ P1 <15>

PCI

E_ATX_C_DRX_ N1 <15>

PCI

E_ATX_C_DRX_ P2 <17>

I

E_ATX_C_DRX_ N2 <17>

PC

MEMORY VREF

+1.

5V

+ME

M_VREF

7

R7 1K

1

C33

7

1U_0402_6.3V6K

2

P05

B5W

ursday, April 16, 2015

2

C16

3

.1U_0402_1 6V7K

1

Co

pal Electronics, Inc.

m

-FT3 MEMORY INTERFACE/PCIE

1E_LA-D121P

_0402_1%

1

U1

006R670

12

MEM_

533Th

MAB_EVEN T#

1.0

A

APU_

DP1_P0<13>

APU_

DP1_N0<13>

DP1_P1<13>

APU_

DP1_N1<13>

HDMI

1 1

eD

P

SVT<30>

APU_

SVC<30>

APU_ APU_

APU_ EC_ APU_ EC_

SVD<30>

APU_

PR

ALERT#

SMB_DA2

PROCHOT#

SMB_CK2

A4W1E D VT

PWRGD<30>

O

CHOT#<7,14,30>

2 2

3 3

PU +1.8VS

4 4

SVT_R

APU_

SVC_R

APU_ APU_

SVD_R

APU_RST# APU_

PWRGD

R80 3 R82 3

A

APU_

DP1_P2<13> DP1_N2<13>

APU_

DP1_P3<13>

APU_ APU_

DP1_N3<13>

TXP0<12>

EDP_

TXN0<12>

EDP_

TXP1<12>

EDP_

TXN1<12>

1 2

4 33_0402_5%

R67

1 2

9 33_0402_5%

R66

1 2

R67

0 33_0402_5%

SMB_CK2<14>

EC_

SMB_DA2<14>

EC_

1 2

R11

7 0_0402_5%KBN@

1 2

8 0_0402_5%KBN@

R11

1 2

R12

0 0_0402_5%RS@

VDDNB_SEN<30>

APU_

APU_VDD_SEN<30>

VDD_RUN_FB_ L<30>

APU_

RP4

1 8 2 7 3 6 4 5

_0804_8P4R_5%

1K

@

RP5

1 8 2 7 3 6 4 5

1K

_0804_8P4R_5%

1 2 1 2

00_0402_5% 00_0402_5%

APU_ APU_ APU_

APU_ LDT

APU_ APU_

T15

APU_ APU_ APU_ APU_

T18

APU_

+3V

S

8VS

+1.

SVT_R SVC_R SVD_R

RST#

_RST#

PWRGD

_PWRGD

PROCHOT# ALERT#

TDI TDO TCK TMS TRST# DBRDY DBREQ#

B

@

U1C

UAP

A9

TDP

1_TXP0

B9

TDP

1_TXN0

A10

P1_TXP1

TD

B10

TD

P1_TXN1

A11

TD

P1_TXP2

B11

P1_TXN2

TD

A12

TD

P1_TXP3

B12

TD

P1_TXN3

A4

LT

P0_TXP0

D

B4

P0_TXN0

LTD

A5

LTD

P0_TXP1

B5

LTD

P0_TXN1

A6

P0_TXP2

LTD

B6

LTD

P0_TXN2

A7

LTD

P0_TXP3

B7

LT

P0_TXN3

D

K15

DI

SP_CLKIN_H

H15

DI

SP_CLKIN_L

G31

SVT

D27

SVC

E29

SVD

B22

C

SI

B21

D

SI

B20

APU

_RST_L

A20

LD

T_RST_L

B19

_PWROK

APU

A19

LD

T_PWROK

A22

PR

OCHOT_L

B18

ERT_L

AL

D29

TD

I

D31

TD

O

D35

TC

K

D33

S

TM

G27

ST_L

TR

B25

DB

RDY

A25

DB

REQ_L

D23

DCR_NB_SENSE

VD

G23

DCR_CPU_SEN SE

VD

E25

VD

DIO_MEM_S_SENSE

E23

VSS_

SENSE

AV33

D_095_FB_H

VD

3

AU3

VDD_095_FB_L

FT3_BGA_769P-T

Part Number =

Close To PU1000

Close To APU's Pin

B

C

DISP

LAY/SVI2/JTAG/TEST

HDM

Security Classificati on

Issued Date

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DP

_150_ZVSS

DP

_2K_ZVSS DP DP

DP

_VARY_BL

P1_AUXP

TD

P1_AUXN

TD

DP0_AUXP

LT

DP0_AUXN

LT

DP0_HPD

DA

C_GREEN

DA

C_HSYNC

DA

C_VSYNC

DA DA

DA

TH TH

DI

ECRACKMON

PL PL

BY

PASSCLK_H PASSCLK_L

BY

LCHRZ_H

PL PLLCHRZ_L

O_TSTDTM0_SERIALCLK

GI

O_TSTDTM0_CLKINIT

USB_ATEST0

B_ATEST1

US

ANALO GIN

M_

ANALO GOUT

TM

I_EN/DP_STEREOSYNC

APU_

PWRGD

APU_

RST#

PROCHOT#

APU_

APU_ALERT#

B16

150_ZVSS

DP_

A21

2K_ZVSS

DP_

B17

_BLON

A17

_DIGON

A18

D17 E17

H19

P1_HPD

D15 E15

H17

4

B1

DAC_

C_RED

C_BLUE

C_SCL C_SDA

C_ZVSS

ERMDA ERMDC

BP0 BP1 BP2

BP3 LTEST1 LTEST0

M_

TEST

EE_2

FR

ON_CAL

C12

72 33P_0402_50V8J

70 33P_0402_50V8J

C12

73 33P_0402_50V8J

76 100P_0402_50V8J

C12

77 100P_0402_50V8J

C12

RED

A14

GRN

DAC_

B15

BLU

DAC_

G19

HSYNC

DAC_

E19

VSYNC

DAC_

D19

DAC_

DDC_CLK

D21

DAC_

DDC_DATA

A16

ZVSS

DAC_

H27

APU_

TEST4

H29

APU_

TEST5

D25 A27

TEST14

APU_

B27

TEST15

APU_

A26

APU_

TEST16

B26

APU_

TEST17

B28

TEST18

APU_

A28

TEST19

APU_

B24

TEST25_H

APU_

A24

APU_

TEST25_L

AV35

APU_

TEST28_H

AU3

5

TEST28_L

APU_

E33

TEST31

APU_

A29

APU_

TEST34_L

H21

APU_

TEST36

H25

TEST37

APU_

AJ1

0

TEST42

APU_

AJ8

APU_

TEST43

R32

APU_

TEST39

N32

TEST40

APU_

AP29

TEST41

APU_

E21

APU_

TEST35

1 2

EMC@

1 2

EMC@

1 2

EMC@

1 2

@EMC@

1 2

@EMC@

2014/03/27 2016/03/27

C

1 2

R40

1 150_0402_1%

1 2

R40

0 2K_0402_1%

ENBKL

<14>

D <12>

ENVD

TPW M < 12>

INV

_CLK <13>

HDMI

_DATA <13>

HDMI

_HPD <13>

EDP_

AUXP <12>

EDP_

AUXN <12>

EDP_

HPD <12>

CRT

A4W1E

03

T25

04

T25

01 02

T25

1 2

R41

6 499_0402_1%

T13 T14

1 2

R19 5

1 2

R18 5

T4 T5 T6

T7

0

T1 T8 T9 T11 T12

Com

pal Secret Data

Deciphered Date

11_0402_1% 11_0402_1%

+1

D

.

8VS

D

E

A4W1E

RED

DAC_

GRN

DAC_

BLU

DAC_

R11

HSYNC

DAC_

NOTE: DAC_HSYNC PU FOR HDMI ENABLE PD FOR CUSTOMER (DNI)

APU_ APU_ APU_ APU_

APU_

APU_ APU_ APU_ APU_

APU_ APU_ APU_

le

Tit

Size Documen t Number Rev

B

Date: Sheet of

R11

TEST16 TEST17 TEST14 TEST15

TEST37 TEST36 TEST37 TEST36

TEST35

R11

RP6

1 8

TDI

2 7

TMS

3 6

TCK

4 5

DBREQ#

1K_0804_8P4R_5%

RP8

1 8 2 7

TRST#

3 6

TEST19

4 5

TEST18

1K

Co

FT3

ursday, April 16, 2015

3

RP2

1 8 2 7 3 6 4 5

75_0804_8P4R_1%

1 2

5 1K_0402_5%

1 2

3 1K_0402_5%

@

RP7

1 8 2 7 3 6 4 5

_0804_8P4R_5%

1K

@

RP3

1 8 2 7 3 6 4 5

_0804_8P4R_5%

1K

1 2

4 1K_0402_5%@

+1.

8VS

+1.

8VS

_0804_8P4R_5%

pal Electronics, Inc.

m

DISP/MISC/HDT

1E_LA-D121P

B5W

E

+3V

S

8VS

+1.

633Th

1.0

A

1 2

5 150P_0402_50V8J

C61

1 2

2 33_0402_5%

_RST#<14,20>

LPC

E_RST#<15,17>

APU_PCI

1 1

2 2

1 2

@

1 2

R3

@

39 10K_0402_5%

9

1 2

R39

@

38 10K_0402_5%

R39

37 10K_0402_5%

Che

cklist suggestion

#_AUDIO<16>

HDA_RST

SY

NC_AUDIO<16>

HDA_ HDA_SDO

UT_AUDIO<16>

HDA_BI

TCLK_AUDIO<16>

+3VALW

3 3

+3VS

1 2

1 100K_0402_5%@

R90

1 2

5 100K_0402_5%

R90

1 2

6 100K_0402_5%@

R90

1 2

R6

5 1K_0402_5%@

7

1 2

6 2.2K_0402_5%

R67

1 2

7 2.2K_0402_5%

R67

1 2

R68

4 10K_0402_5%@

1 2

R68

8 10K_0402_5%@

R60

1 2

R90

7 33_0402_5%

1 2

C912 150P_0402_50V8J

PBTN_

OUT#<14>

SYS_

PWRGD_EC<14>

E_WAKE#<15>

APU_PCI

S3#<14>

SLP_

S5#<14>

SLP_

1 2

R40 1

1 2

R41 1

1 2

R42 1

#<14>

KBRST GAT

EA20<14>

EC_SCI

#<14>

EC_SMI

#<14>

_CLKREQ#<15>

LAN

N_CLKREQ#<17>

WLA

USB_O

C0#<19>

HDA_SDI

N0<16>

EMC@

RP13

1 8 2 7 3 6 4 5

33_0804_8P

APU_PCI USB_O USB_O EC_

APU_SCL APU_SDAT

HDA_BI HDA_SDI

HDA_RST HDA_SY HDA_SDO HDA_BI

4R_5%

C0# C1#

ID_OUT#

L

TCLK

T16

#

NC

UT

TCLK

E_WAKE#

K0

A0

N0

LPC APU_PCI

EC_RSMRST

APU_PCI

5K_0402_5% 5K_0402_5% 5K_0402_5%

LAN WLA

USB_O USB_

HDA_BITCLK HDA_SDO HDA_SDI HDA_SDI HDA_ HDA_SDI HDA_SY HDA_RST

32K_X

_RST_A#

E_RST#_R

E_WAKE#

APU_T APU_T APU_T

_CLKREQ#

N_CLKREQ#

T21

C0# C1#

O

T19 T20

UT N0 N1 N2

SDI

N3

NC

#

1

2

EC_RSMRST

#_R

EST0 EST1 EST2

#<14>

32.768KMHz CRYSTAL

1

32K_X

12

1

2

C68 18P_0402_50V8J

2

A

Y3

32K_X

2

4 4

32.768K

R91 20M_0402_5%

1

6

C68 18P_0402_50V8J

2

SJ100001K00

HZ_12.5PF_CM31532768DZFT

12

4

B

@

UAPU1D

AY4

LPC

_RST_L

AY9

RST_L

PCIE_

AM1

AW1

AW2

AY5

BA8

AY7

AY3 BA5

AU1 AY10

AY6

AR2 AR

AN5

AL7

AP15 AV13

BA9 BA10 AV15

AU2

AR2 AV27 AY29

AY8 AW1

AV1

AY1

AN2 AN

AK2

AK1

AM1

AL2

AM2

AL1

AJ2

AJ1

_L

RSMRST

PWR_

BTN_L

9

PWR_

GOOD

SYS_

RESET_L/GEVENT19_L

1

WAKE_L/GEVENT8_L

S3_L

SLP_

S5_L

SLP_

3

TES

T0

TES

T1/TMS T2

TES

3

L

KBRST_

3

1

2

0IN/GEVENT0_L

GA LPC

_PME_L/GEVENT3_L

LPC

_SMI_L/GEVENT23_L

IR_RX0/GEVENT16_L

AC_PRES/

TX0 /GEVEN T21_ L

IR_

TX1 /GEVEN T6_L

IR_ IR_

RX1 /GEVEN T20_ L

IR_

LED _L/LLB _L/GP IO184

9

CLK_

REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60

9

REQ1_L/GPIO61

CLK_

7

REQ2_L/GPIO62

CLK_

REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63

CLK_ CL

REQG_L/GPIO65/OSCIN

K_

USB_O

C0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L

USB_O

C1_L/TDI/GEVENT13_L C2_L/TCK/GEVENT14_L

USB_O

C3_L/TDO/GEVENT15_L

USB_O

AZ

BITCLK

_

1

AZ_

SDOUT

AZ_

SDIN0/GPIO167

AZ_

SDIN1/GPIO168

AZ_SDIN2/GPIO169

SDIN3/GPIO170

AZ_

SYNC

AZ_

RST_L

AZ_

X32

K_X1

K_X2

X32

GA_769P-T

FT3_B

Part Number =

A4W1 E

1 2

R39

45 0_0402_5%@

1 2

D3

1V-40 SOD-323

RB75

RB751 Max Vf=0.37V

B

ACPI

/SD/AZ/GPIO/RTC/MISC

C

SD_PW

R_CTRL

K/GPIO73

SD_CL

GPIO74

SD_CMD/

SD_

GPIO75

CD/

SD_W

P/GPIO76

SD_DAT

A0/GPIO77

SD_DATA1/GPIO78

A2/GPIO79

SD_DAT

A3/GPIO80

SD_DAT

SD_L

ED/GPIO45

SCL0

/GPIO43

GPIO47

SDA0/

/GPIO227

SCL1

/

GPIO228

SDA1

GPI GPI GPI GPI GPI GPI GPI GPI

SPKR/G

PIO66 GPI GPI GPI GPI

O174

GPI

GEV

ENT2_L

GEV

ENT4_L ENT7_L

GEV

ENT10_L

GEV

ENT11_L

GEV GE

ENT17_L

V

BLI

NK/GEVENT18_L

GEV

ENT22_L

GENINT1_L/GPIO32

INT2_L/GPIO33

GEN

OUT0/GPIO52

FAN

FA

IN0/GPIO56

N

RTCCL

O49 O50 O51 O55 O57 O58 O59 O64

O68 O69 O70 O71

BA23 AY22

AY23 AY20 BA20

BA2

2 AY21 AY24 BA24

AY25

5

AU2 AV25

AY11 BA1

AP27 AY28 BA2 AV23 AP21 BA26 AV19 AY27 BA27 AU2 AY26 AV21 AM2 BA3

AV17 BA4 AR AP17 AP11 AN8 AU BA6

BA29 AP23

AV31 AU3

AV11

K

APU_SCL APU_SDAT

APU_SCL

1

APU_SDAT

APU_G

8

APU_G

1

APU_G APU_G

GEV GE

1

5

7

1

GE GEN

1

V

N

RTC_

PIO49

PIO51

PIO71 PIO174

ENT2# ENT4#

INT1_L INT2_L

K0

A0

K1

A1

1 2

R66

1 0_0402_5%@

1 2

6 10K_0402_5%

R68

1 2

R68

9 10K_0402_5%

EC_L

ID_OUT# <14>

CLK

APU_SCL APU_SDAT

DEVSLP0

APU_SPKR

T17

K0 <10,11,17>

A0 <10,11,17>

<18>

D

<16>

PROCHO

STRAPS OF APU

LPC_FRAME# LPC_CLK0_EC

SPI ROM

_FRAME#<8,14>

LPC

_CLK0_EC<8,14>

LPC

_CLK1<8,20>

LPC

iphered Date

(DEFAULT)

LPC ROM

A4W1 E DV T

H

+1.8VALW

L

5

9

1 2

1

2

R68

5

10K_0402_5%

1 2

1

2

C21 1U_0402_6.3V6K

2

2014/03/

+3VS

1 2

46 10K_0402_5%

R39

1 2

9

47 10K_0402_5%@

R3

1 2

R39

48 10K_0402_5%

2

8

C94 .1U_040 2_16V7K

1

@EMC@

pal Secret Data

Com

27 2016/03/27

C

Dec

R34

47K_0402_5%

#_R

EC_RSMRST

SYS_

PWRGD_EC

C20

1U_0402_6.3V6K

urity Classification

Sec

Issued Date

THI

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BOOT FAIL TIMER ENABLED

BOOT FAIL TIMER DISABLED (DEFAULT)

ENT2#

GEV

CLK

RTC_

D

12

@

0

2

R9 10K_0402_5%

12

@

R90

3

2K_0402_5%

E

APU_SCL

K1

APU_SDATA1

A4W1 E

APU_G APU_G

PIO51 PIO49

1K_0402_5%

1 2

12

10K_0402_5%

12 12

CZL@

R69

4

2

R39 R39444.7K_0402_5%

+3VALW

434.7K_0402_5%

+3VS

KBN@

5

R69

1K_0402_5%

1 2

12

1

R69

10K_0402_5%

GPIO51 GPIO49Platform identify

Be

ma

e Kabini Carrizo_L (Reserve)

T# <6,14,30>

NA (Reserve)

ENT4#

GEV

1 2

oject identify

GEV

1 2

GEN

INT1_L

INT2_L

@

200_0402_5%

R39

1 2

RS@

R39

230_0402_5%

LPC_CLK1 GEVENT2_L

CLKGEN ENABLE (DEFAULT)

CLKGEN DISABLED

12

@

0

4

R9 10K_0402_5%

12

R92

6

2K_0402_5%

Tit

le

Tit

Size Document Number Rev

tom

Cus

Date: Sheet

Date: Sheet of

1.8V SPI ROM

3.3V SPI ROM (DEFAULT)

12

@

2

5

R9

10K_0402_5%

12

@

R92

7

2K_0402_5%

pal Electronics, Inc.

Com

GPIO/AZ/MISC/STRAPS

FT3

1E_LA-D121P

B5W

0 0 1 11

7 10K_0402_5%@

R68

R6

8 10K_0402_5%

6

14" 15"Pr

ENT4# 0 1

TP_I

NORMAL POWR UP/RESET TIMING (DEFAULT)

FAST POWER UP/RESET TIMING FOR SIMULATION

+3VALW

12

@

R9 10K_0402_5%

12

R92 2K_0402_5%

12

2

8

12

9

E

0 1 0

+3VALW

2C_INT#_APU <20>

RTC_CLK

4

R9 10K_0402_5%

@

R95

2.2K_0402_5%

733Thursday, April 16, 2015

(DEFAULT)

9

0

of

1.0

A

SATA_

FTX_DRX_P0<18>

SATA_

HDD

1 1

ODD

95VS

+0.

2 2

LAN

WLAN

C

_CLK0_EC<7,14>

LP LPC

_CLK1<7,20>

3 3

LPC

1 2

R93

8

1M_0402_5%

2

4 4

3

12

C79

4

6.8P_0402_50V8C

FTX_DRX_N0<18>

FRX_DTX_N0<18>

SATA_

FRX_DTX_P0<18>

SATA_

FTX_DRX_P1<18> FTX_DRX_N1<18>

SATA_

FRX_DTX_N1<18>

SATA_ SATA_

FRX_DTX_P1<18>

R90 1 R96 1

+3V

S

R63 10K_0402_5%

CLK

_PCIE_LAN<15> _PCIE_LAN#<15>

CLK

_PCIE_WLAN<17>

CLK CLK

_PCIE_WLAN#<17>

LPC_AD0<14>

LPC

_AD1<14>

_AD2<14>

LPC

C

_AD3<14>

LP

_FRAME#<7,14>

SERI

RQ<14>

CLK

RUN#<20> PD#<20>

LPC

48M_X

1

Y1

48MH

Z_8PF_X3S048000D81H-W

Part Number = SJ10000AF00

4

12

C79

5

5.6P_0402_50V8D

SE07156AD80

A

12

K_0402_1%

12

K_0402_1%

12

@

3

R10

3 0_0402_5%RS@ 4 0_0402_5%RS@

R10

2

1

48M_X

1 2 1 2

SATA_ SATA_

SATA_

BA14 AY1

4

BA16 AY1

6

AY1

9

BA19

AY1

7

BA17

9

AR1

ZVSS

AP19

ZVDD

BA30

ACT#

2

AY1

BA12

U4 U5

AC8

AC1

0

AE4 AE5

AC4 AC5

AA5 AA4

AP13

AY2

AW2

AT2 AT1 AR2 AR1 AP2

AP1 AV29 AP25

AV2

N2

N1

1

2

B

@

U1E

UAP

SAT

A_TX0P

SATA_TX0N

A_RX0N

SAT SATA_RX0P

SATA_TX1P

A_TX1N

SAT

SATA_RX1N SAT

A_RX1P

SATA_ZVSS

A_ZVDD_095

SAT

A_ACT_L/GPIO67

SATA_X1

A_X2

SAT

GFX

_CLKP

GFX

_CLKN

P_CLK0P

GP GPP_CLK0N

GPP

_CLK1P

GP

_CLK1N

P

GP

P_CLK2P

GP

P_CLK2N

GP

_CLK3P

P

_CLK3N

GPP

X1

4M_25M_48M_OSC

M_X1

X48

M_X2

LP

CCLK0

LP

CCLK1

D0

LA LA

D1

LA

D2

LA

D3

AME_L

LFR

Q0_L

LDR SER

IRQ/GPIO48

LP

C_CLKRUN_L

LPC

_PD_L/GEVENT5_L/SPI_TPM_CS_L

FT3_BGA_769P-T

Part Number =

B

/SATA/USB/SPI/LPC

CLK

USB

CLK/14M_25M_48M_OSC

US US

US USB_HSD3N

US US

USB USB

US US

USB USB

USB US

USB

_SS_ZVDD_095_USB3_DUAL

US

US USB

USB USB

SPI

_CLK/GPIO162

_CS1_L/GPIO165

SPI

_CS2_L/GPIO166

SPI

SPI_DO/GPIO163

SPI

SPI_HOLD_L/GEVENT9 _L

_DI/GPIO164

_WP_L/GPIO161

SPI

B_ZVSS

US

B_HSD0P B_HSD0N

B_HSD1P B_HSD1N

B_HSD2P B_HSD2N

B_HSD3P

B_HSD4P B_HSD4N

_HSD5P _HSD5N

B_HSD6P B_HSD6N

B_HSD7P B_HSD7N

_HSD8P _HSD8N

_HSD9P _HSD9N

B

B_SS_ZVSS

_SS_0TXP

B

_SS_0TXN

_SS_0RXP _SS_0RXN

_SS_1TXP _SS_1TXN

_SS_1RXP _SS_1RXN

W4

AG4

AL4 AL5

AJ4 AJ5

AG7 AG8

AG1 AG2

AF1 AF

AE1 AE2

AD1 AD2

AC1 AC2

AB1 AB2

AA1 AA2

AE10 AE8

T2 T1

V2 V1

R1 R2

W1 W2

AU7 AW9 AR4 AR1 AR7 AU1 AU9

C

USB

_ZVSS

2

SS_ZVSS

USB

SS_ZVDD

USB

APU_ APU_

1

APU_ APU_

1

APU_ APU_

1 2

R64

1 11.8K_0402_1%

1 2

4 1K_0402_1%

R64

1 2

R64

5 1K_0402_1%

SPI_CLK_R SPI_CS1#

SPI_MOSI SPI_MISO SPI_HOLD# SPI_WP#

R10

5 0_0402_5%RS@

T37

1 2

20_P0 <19>

USB USB

20_N0 <19>

20_P1 <19>

USB

20_N1 <19>

USB

20_P2 <17>

USB

20_N2 <17>

20_P3 <12>

USB

20_N3 <12>

USB

20_P4 <19> 20_N4 <19>

USB

20_P5 <12>

USB USB

20_N5 <12>

20_P6 <21>

USB

20_N6 <21>

USB

20_P8 <19>

USB

20_N8 <19>

USB

3_FTX_DRX_P0 <19>

USB

3_FTX_DRX_N0 <19>

USB

3_FRX_DTX_P0 <19>

B

3_FRX_DTX_N0 <19>

US

APU_

95VALW

+0.

SPI_CLK

D

USB/

B port 0

SUB/B USB2

WLAN/BT combo

CAMERA

SUB/B CR

Touch Screen

USB 2 I2C Bridge

MB USB3.0 port0 (2.0)

1 2

76 0_0402_5%RS@

R16

1 2

6

77 0_0402_5%RS@

R1

1 2

R16

78 0_0402_5%RS@

1 2

R1

79 0_0402_5%RS@

6

8MB SPI ROM48MHz CRYSTAL

+3V

ALW

RP1

2

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

Security Classificati on

2014/03/27 2016/03/27

Issued Date

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI

THI AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/03/27 2016/03/27

C

Com

pal Secret Data

Deciphered Date

APU_ APU_ APU_

SPI_CS1# SPI_WP# SPI_HOLD#

SPI_CS1#

APU_

SPI_MISO

APU_ APU_

SPI_WP#

D

E

Port 0-3 USB OHCI1 ( Dev 12 Func 0 )

Port 4-7 USB OHCI2 ( Dev 13 Func 0 )

USB2.0 Only Port 8-9 USB OHCI2 ( Dev 16 Func 0 )

USB3.0 Port 0-1 USB XHCI ( Dev 10 Func 0 )

U56

1

CS#

2

DO(

HOL

IO1)

3

WP#

4

GN

W2

SA000039A30

A4W1E

le

Tit

Size Documen t Number Rev

B

Date: Sheet of

D#(IO3)

(IO2)

D

5Q64FVSSIQ_SO8

ursday, April 16, 2015

EHCI1 ( Dev 12 Func 2 )

EHCI2 ( Dev 13 Func 2 )

EHCI2 ( Dev 16 Func 2 )

EC_

SPI_CLK <14> SPI_CS1# <14>

EC_

SPI_MOSI <14> SPI_MISO <14>

EC_

C63 .1U_0402_1 6V7K

8

VCC

DI

CLK

(

IO0)

Co

FT3

B5W

m

7 6 5

SPI_HOLD#

APU_ APU_

SPI_CLK

APU

SPI_MOSI

_

APU_

SPI_CLK

R61 10_0402_5%

pal Electronics, Inc.

SATA/CLK/USB/SPI

1E_LA-D121P

12

5

@

1 2

7

@EMC@

E

+3V

ALW

1 2

C63

6

10P_0402_50V8J

833Th

@EMC@

1.0

CORE POWER OF APU

+AP

U_CORE

VDDCR_CPU

C17

9 1U_0402_6.3V6K

C18

0 1U_0402_6.3V6K

1

2

A

C18

C182 1U_0402_6.3V6K

1 1U_0402_6.3V6K

3 1U_0402_6.3V6K

1

2

C18

C1

C18

6 1U_0402_6.3V6K

4 1U_0402_6.3V6K

1

2

C19

C18

8

8 1U_0402_6.3V6K

7 1U_0402_6.3V6K

0 180P_0402_50V8J

9 1U_0402_6.3V6K

1

2

B

C

D

E

1 1

INTEGRATED GPU POWER OF APU

U_CORE_NB

+AP

+1.5V/+1.5VS OF APU

5V

+1.

2 2

VDDIO_MEM_S

C94

C92

9 10U_0603_6.3V6M

5 10U_0603_6.3V6M

4 10U_0603_6.3V6M

1

2

@

+0.95VALW/+0.95VS OF APU

VDD_095

+0.

95VS

C19

C93

5 10U_0603_6.3V6M

1

2

3 3

VDD_095_USB3_DUAL

C20

C93

C19

9 1U_0402_6.3V6K

5 1U_0402_6.3V6K

4 10U_0603_6.3V6M

8 1U_0402_6.3V6K

1

2

@

95VALW

+0.

C93

7 10U_0603_6.3V6M

8 10U_0603_6.3V6M

1

2

VDDCR_NB

C92

3 1U_0402_6.3V6K

6 .1U_0402_16V7K

1

2

C2

C20

C26

0 4 1U_0402_6.3V6K

6 1U_0402_6.3V6K

0 1U_0402_6.3V6K

1

2

C21

6 1U_0402_6.3V6K

4 1U_0402_6.3V6K

1

2

@

+3VALW/+3VS OF APU

C25

5 1U_0402_6.3V6K

4 1U_0402_6.3V6K

1

2

1

C24

5 180P_0402_50V8J

1

2

+3V

C25

6 180P_0402_50V8J

1

2

C94

6

.1U_0402_16V7K

@EMC@

ALW

C25

2 1U_0402_6.3V6K

C25

3 1U_0402_6.3V6K

1

2

1

+RT

C94

7 .1U_0402_16V7K

@EMC@

C_APU_R

+1.

8VALW

ALW

+3V

+0.95VALW

95VALW

+0.

+RT

5VS

C_APU_R

+1.

5V

3A

AG32 AG3

AM1

AA31 AA35 AC3 AC3 AE31 AE35

AJ3 AL3 AL3 AR3

AL1 AL11

AL1

AW5

AE11 AE13 AJ11 AJ1

J35 L32

L37 N35 R31 R37 U32 U35

W3

1 W32 W37

2

7

5

2

7

5

0

B1 B2

3

AR5 AU4 AV7

3

AN4

@

UAP

U1F

IO_MEM_S_1

VDD

IO_MEM_S_2

VDD VDD

IO_MEM_S_3 IO_MEM_S_4

VDD VDDIO_MEM_S_5

IO_MEM_S_6

VDD

IO_MEM_S_7

VDD VDD

IO_MEM_S_8 IO_MEM_S_9

VDD

IO_MEM_S_10

VDD VDD

IO_MEM_S_11

VDD

IO_MEM_S_12 IO_MEM_S_13

VDD

D

IO_MEM_S_14

VD

IO_MEM_S_15

VDD VDD

IO_MEM_S_16

VDD

IO_MEM_S_17 IO_MEM_S_18

VDD VDD

IO_MEM_S_19

VDD

IO_MEM_S_20 IO_MEM_S_21

VDD VDDIO_MEM_S_22

IO_MEM_S_23

VDD

IO_AZ_ALW_1

VDD

IO_AZ_ALW_2

VDD

_18_ALW_1 _18_ALW_2

VDD

_33_ALW_1

VDD VDD

_33_ALW_2

VDD_095_USB3_DUAL_1 VDD

_095_USB3_DUAL_2 _095_USB3_DUAL_3

VDD VDD_095_USB3_DUAL_4

_095_ALW_1

VDD VDD

_095_ALW_2

VDD

_095_ALW_3 _095_ALW_4

VDD

BT_RTC_G

FT3_BGA_769P-T

Part Number =

POW

ER

VDD VDD VDD VDD VD VDD VDD VDD VDD VDD VDD VDD VDDCR_CPU_22 VDD VDD VDD VDD

VDD VDD VDD

CR_CPU_1

VDD

CR_CPU_2

VDD VDD

CR_CPU_3 CR_CPU_4

VDD VDDCR_CPU_5

CR_CPU_6

VDD

CR_CPU_7

VDD VDD

CR_CPU_8 CR_CPU_9

VDD

CR_CPU_10 CR_CPU_11 CR_CPU_12 CR_CPU_13

D

CR_CPU_14 CR_CPU_15 CR_CPU_16 CR_CPU_17 CR_CPU_18 CR_CPU_19 CR_CPU_20 CR_CPU_21

CR_CPU_23 CR_CPU_24 CR_CPU_25 CR_CPU_26

CR_NB_1

VDD VDD

CR_NB_2

VDD

CR_NB_3 CR_NB_4

VDD

D

CR_NB_5

VD

CR_NB_6

VDD VDD

CR_NB_7

VDD

CR_NB_8 CR_NB_9

VDD

CR_NB_10 CR_NB_11

VDD VD

CR_NB_12

D

CR_NB_13

VDD VDD

CR_NB_14

VDD

CR_NB_15 CR_NB_16

VDD VDD

CR_NB_17

VDD

CR_NB_18

VDD

CR_NB_19 CR_NB_20

VDD VDD

CR_NB_21

VDD VDD VDD VDD

VDD VDD

VDD_095_1 VDD

_095_2 _095_3

VDD VDD_095_4 VDD

_095_5 _095_6

VDD VDD

_095_7

VDD

_095_8 _095_9

VDD

_095_GFX_1 _095_GFX_2 _095_GFX_3

_18_1 _18_2 _18_3 _18_4

_33_1 _33_2

L21 L23 L25 L27 L29 N21 N23 N27 R2 R23 R27 U21 U23 U27 W21 W23 W27 AA21 AA23 AA27 AC2 AC2 AC2 AE21 AE23 AE2

L13 L17 N11 N13 N17 R11 R1 R17 U13 U17 W13 W17 AA13 AA17 AC1 AC1 AE15 AE17 AE19 AG1 AG2

A2 A3 B3 C3

AM1 AM1

AG2 AG2 AJ2 AJ2 AL2 AL2 AL2 AM23 AM2

U10 W10 AA10

AA1 AA15 AA19 AA25 AA29 AA39

AC1 AC15 AC1 AC2 AC2 AC3 AC3 AC4

AE25 AE29 AE32 AE39

AG1 AG AG13 AG1 AG1 AG2 AG2 AG3 AG3 AG4

W29 W39 W41

Y1

Y2 AA3 AA7 AA8

1

AC3 AC7

1

9 5 9 1 9

1 AE3 AE7

AG3 AG5

0

1

5

9

5

9

1

9

1

AH1 AH2 AJ3 AJ7

AJ1

5

7

AJ1 AJ19 AJ2

3

5

AJ2 AJ29 AJ3

1

2

AJ3 AJ39

AL3

AL8 AL15 AL1

7 9

AL1 AL2

5 9

AL2

@

UAP

U1H

25

VSS_1

26

VSS_1 VSS_1

27 28

VSS_1 VSS_129

30

VSS_1

31

VSS_1 VSS_1

32 33

VSS_1

34

VSS_1 VSS_1

35

VSS_1

36 37

VSS_1

1

38

VSS_

39

VSS_1 VSS_1

40

VSS_1

41 42

VSS_1 VSS_1

43

VSS_1

44 45

VSS_1 VSS_146

47

VSS_1 VSS_1

48

VSS_1

49 50

VSS_1

51

VSS_1 VSS_1

52 53

VSS_1

54

VSS_1

1

55

VSS_

56

VSS_1 VSS_1

57 58

VSS_1

59

VSS_1 VSS_1

60

VSS_1

61 62

VSS_1 VSS_

63

1

64

VSS_1 VSS_1

65

VSS_1

66 67

VSS_1 VSS_1

68

VSS_1

69

VSS_1

70 71

VSS_1 VSS_1

72

VSS_1

73 74

VSS_1 VSS_1

75 76

VSS_1

77

VSS_1 VSS_1

78 79

VSS_1

80

VSS_1 VSS_1

81 82

VSS_1 VSS_183 VSS_1

84 85

VSS_1 VSS_186

FT3_BGA_769P-T

Part Number =

GND

VSSBG_

VSS_1 VSS_1 VSS_1 VSS_1 VSS_191 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_ VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_208 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_ VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_ VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2 VSS_2

VBURN

PSEN

AL3

9

87

AL4

1

88

1

AM1

89

7

AM2

90

AM3

1

AN3

92

AN7

93

AN3

9

94

AP3

1

95

AR3

96

AR1

3

97

7

AR1

98

AR2

1

99

AR2

5

2

00

9

AR2

01

9

AR3

02

AR4

1

03

AU1

04

AU2

05

AU3

06

5

AU1

07

AU1

9 3

AU2

09

7

AU2

10

AU3

9

11

AV9

12

AW3

13

AW7

14

3

AW1

15

AW1

5

16

AW1

7

2

17

9

AW1

18

AW2

1

19

AW

3

2

20

AW25

21

AW2

7

22

1

AW3

23

AW3

3

24

AW3

5

25

2

7

AW3

26

9

AW3

27

AW4

1

28

AY13

29

AY15

30

AY18

31

AY30

32

BA2

33

BA7

34

BA13

35

BA15

36

BA18

37

BA21

38

BA25

39

BA31

40

BA35

41

BA39

42

A15

DAC

AL31 AM2

9

@

UAP

U1G

GND

+AP

9

R11

0_0402_5%

RS@

1

1 3 7

7

+AP

U_CORE_NB

3

3 7

7 1

+1.

8VS

5

S

+3V

7

3

+0.95VS

7 1 7 1 3 7

5

VSS_1

A13

VSS_2

A23

VSS_3

A31

VSS_4

A35

VSS_5

A39

VSS_6

B8

VSS_7

B13

VSS_8

B2

3

1 2

VSS_9

B31

0

VSS_1

B39

VSS_1

1

C1

VSS_1

2

C2

3

VSS_1

C5

1

4

VSS_

C7

5

VSS_1

C9

VSS_1

6

C11

VSS_1

7

C13

8

VSS_1

C15

VSS_1

9

C17

VSS_2

0

C19

1

VSS_2

C21

VSS_22

C23

3

VSS_2

C25

VSS_2

4

C27

VSS_2

5

C2

9

6

VSS_2

C31

7

VSS_2

C33

VSS_2

8

C35

9

VSS_2

C37

0

VSS_3

C39

3

1

VSS_

C41

2

VSS_3

D9

VSS_3

3

D1

1

4

VSS_3

D13

5

VSS_3

E3

VSS_3

6

E4

VSS_3

7

E9

8

VSS_3

E11

VSS_

9

3

E13

0

VSS_4

E27

VSS_4

1

E31

VSS_4

2

E35

3

VSS_4

E38

VSS_4

4

E39

VSS_4

5

G3

VSS_4

6

G7

7

VSS_4

G11

VSS_4

8

G13

VSS_4

9

G15

0

VSS_5

G17

VSS_5

1

G21

2

VSS_5

G25

3

VSS_5

G29

VSS_5

4

G35

5

VSS_5

G37

6

VSS_5

G39

VSS_5

7

G41

8

VSS_5

H11

VSS_59

H13

VSS_6

0

H23

1

VSS_6

H31

VSS_62

FT3_BGA_769P-T

Part Number =

A8

U_CORE

VSS_6 VSS_6 VSS_6 VSS_6 VSS_67 VSS_6 VSS_6 VSS_7 VSS_7 VSS_7 VSS_7 VSS_7 VSS_7 VSS_ VSS_7 VSS_7 VSS_7 VSS_8 VSS_8 VSS_8 VSS_8 VSS_84 VSS_8 VSS_8 VSS_8 VSS_8 VSS_8 VSS_9 VSS_9 VSS_9 VSS_ VSS_9 VSS_9 VSS_9 VSS_9 VSS_9

VSS_9 VSS_1 VSS_ VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_1 VSS_121 VSS_1 VSS_1 VSS_124

J3

3

J7

4

J8

5

J39

6

K11 K13

8

K17

9

K19

0

K2

1

K23

2

K25

3

K27

4

K29

5

K31

7

6

L3

7

L7

8

L8

9

L10

0

L11

1

L15

2

L19

3

L31 L39

5

L41

6

M1

7

M2

8

N3

9

N7

0

N15

1

N19

2

N25

9

3

N29

4

N31

5

N3

9

6

P1

7

P2

8

R3

9

R7

00

R15

01

1

R19

02

R25

03

R29

04

R39

05

R41

06

U1

07

U2

08

U3

09

U7

10

U8

11

U11

12

U15

13

U19

14

U25

15

U29

16

U31

17

U39

18

W3

19

W5

20

W11 W15

22

W19

23

W25

S

+3V

C20

C19

C20

1 1U_0402_6.3V6K

0 1U_0402_6.3V6K

1

2

C19

2 1U_0402_6.3V6K

3 1U_0402_6.3V6K

1 1U_0402_6.3V6K

1

2

C19

5 1U_0402_6.3V6K

4 1U_0402_6.3V6K

7 180P_0402_50V8J

1

2

C24

C25

9 1U_0402_6.3V6K

7 180P_0402_50V8J

1

2

VDD_33_ALWVDD_33

VDDIO_AZ_ALW

PLANE SPLIT

C20

C92

7 1U_0402_6.3V6K

C93

C92

1 1U_0402_6.3V6K

8 .1U_0402_16V7K

9 .1U_0402_16V7K

1

2

@

C21

C2 1

0 .1U_0402_16V7K

2 1U_0402_6.3V6K

0 180P_0402_50V8J

1 180P_0402_50V8J

1

2

C23

C20

C23

8 180P_0402_50V8J

1 180P_0402_50V8J

7 180P_0402_50V8J

0 180P_0402_50V8J

1

2

@

(Could be S0 or S5 power rail)

+1.

C25

9 180P_0402_50V8J

8 180P_0402_50V8J

1

2

5VS

C23

C16

2 1U_0402_6.3V6K

1 4.7U_0603_6.3V6K

1

2

@

+1.8VALW/+1.8VS OF APU

+1.8VALW

C16

0 4.7U_0603_6.3V6K

1

2

VDD_18_ALW

VDD_18

C23

7 1U_0402_6.3V6K

6 1U_0402_6.3V6K

1

2

C23

C24

C23

3 180P_0402_50V8J

0 1U_0402_6.3V6K

9 1U_0402_6.3V6K

8 1U_0402_6.3V6K

1

2

C24

4 1U_0402_6.3V6K

1

2

C25

C24

0 1U_0402_6.3V6K

8 1U_0402_6.3V6K

6 1U_0402_6.3V6K

1

2

+1.

8VS

C21

3 180P_0402_50V8J

1

2

95VALW

+0.

C22

C21

1 1U_0402_6.3V6K

8 180P_0402_50V8J

1

2

@

C22

C21

0 1U_0402_6.3V6K

9 1U_0402_6.3V6K

1

2

@

C93

3 10U_0603_6.3V6M

1

2

C22

C21

2 1U_0402_6.3V6K

7 1U_0402_6.3V6K

1

2

VDD_095_ALW

VDDBT_RTC_G

12

SP@

CLRP

2

SHORT PADS

A4W1E

1 2

R93 1

12

1

SP@

CLRP SHORT PADS

C_APU_R

4 4

A

RTC OF APU

B

+RT

C16

0.22U_0402_10V6K

W=20mils

6

1

2

C_APU

+RT

0K_0402_5%

Need OPEN

for Clear CMOS

C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USEDBY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELEC TRONICS, INC.

MAY BE USEDBY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELEC TRONICS, INC.

2014/03/27 2016/03/27

pal Secret Data

Com

Deciphered Date

D

le

Com

FT3

B5W

ursday, April 16, 2015

PWR/GND

1E_LA-D121P

E

933Th

of

Title

Tit

Size Document N umber Rev

C

Date: Sheet

pal Electronics, Inc.

Com

1.0

A

_SDQ0 _SDQ1

_SDM0

_SDQ2

_SDQ8 _SDQ9

_SDQS1# _SDQS1

_SDQ10 _SDQ11

_SDQ16 _SDQ17

_SDQS2# _SDQS2

_SDQ18 _SDQ19

_SDQ25

_SDM3

_SDQ26 _SDQ27

CKE0

_SBS2#

_SMA12

_SMA8

_SMA5

_SMA3 _SMA1

CLK0

_

CLK0#

_SMA10 _SBS0#

_SWE# _SCAS#

_

SCS1#

_SDQ32 _SDQ33

_SDQS4#

B

_SDQS4

_SDQ34 _SDQ35

_SDQ40 _SDQ41

_SDM5

B

_SDQ42

_SDQ48

_SDQS6# _SDQS6

_SDQ50 _SDQ51

_SDQ56 _SDQ57

_SDM7

_SDQ58

dress: 00>

5

@EMC@

+1.

5V

15mi

JDI

MM1

l

1

VREF

3

VSS2

5

DQ0

7

DQ1 VSS49DQS

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ VSS925VSS10

27

DQS

29

DQS VSS1131VSS12

33

DQ1

35

DQ1 VSS1337VSS14

39

DQ1

41

DQ1 VSS1543VSS16

45

DQS#2

47

DQS VSS1849DQ2

51

DQ1

53

DQ1 VSS2055DQ2

57

DQ2

59

DQ2 VSS2261DQS

63

DM3 VSS2365VSS24

67

DQ2

69

DQ2 VSS2571VSS26

73

CK

75

VD

77

NC1

79

BA2

81

VDD

83

A12

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0

105

VDD

107

A1

109

BA0

111

VDD

113

WE#

115

CAS

117

VDD

119

A13

121

S1#

123

VD

125

NCT

127

VSS27

129

DQ3

131

DQ3

133

VSS29

135

DQS

137

DQS

139

VSS32

141

DQ

143

DQ3

145

VSS34

147

DQ4

149

DQ4

151

VSS36

153

DM5

155

VSS37

157

DQ4

159

DQ4

161

VSS39

163

DQ4

165

DQ4

167

VSS41

169

DQS

171

DQS

173

VSS44

175

DQ5

177

DQ5

179

VSS46

181

DQ56

183

DQ5

185

VSS48

187

DM7

189

VSS49

191

DQ5

193

DQ59

195

VSS51

197

SA0

199

VDD

201

SA1

203

VTT

205

G1

LCN_DAN06-K4406-0101

CONN@

SP07

_DQ

9

#1 1

0 1

6 7

2

8 9

4 5

6 7

0

E D

1

3

/BC#

5

7

9

# 11

/AP

0

13

# 15

17

D

E

ST

2 3

#4 4

4

3

5

0 1

2 3

8 9

#6 6

0 1

7

8

SPD

1

000PT00

VR

RES

VSS17

VSS19

VSS21

VDD

VD EF VSS28

VSS30

VSS31

VSS33

VSS35 DQS

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47 DQS

VSS50

VSS52

EVENT

VSS1

VSS3

DQS

VSS6

VSS8 DQ1 DQ

DQ1 DQ1

DQ2 DQ2

DQ2

DQS

DQ3 DQ3

CK VD

VDD

CK1

RA

ODT

DQ3 DQ3

DQ3 DQ

DQ4 DQ4

DQS

DQ4 DQ4

DQ5 DQ5

DQ6 DQ61

DQS7

DQ6 DQ63

VTT

2 4

DQ4

6

DQ5

8 10

#0

12

0

14 16

DQ6

18

DQ7

20 22

2

24

1

3

26 28

DM1

30

ET#

32 34

4

36

5

38 40

0

42

1

44 46

DM2

48 50

2

52

3

54 56

8

58

9

60 62

#3

64

3

66 68

0

70

1

72

74

1

E

76

D

2

78

A15

80

A14

82

4

84

A11

86

A7

88

6

90

A6

92

A4

94

8

96

A2

98

A0

100

10

102

CK1

104

#

106

12

108

BA1

110

S

#

112

14

114

S0#

116

0

118

16

120

1

122

NC2

124

18

D

126

_CA

128 130

6

132

7

134 136

DM4

138 140

8

142

9

3

144 146

4

148

5

150 152

#5

154

5

156 158

6

160

7

162 164

2

166

3

168 170

DM6

172 174

4

176

5

178 180

0

182 184 186

#7

188 190 192

2

194 196 198

#

200

SDA

202

SCL

204

2

206

G2

EF_DQ

+VR

DDRAB

1

2

6

C17

1

.1U_0402_16V7K

1000P_0402_50V7K

1 1

2 2

3 3

S

+3V

1

C13 .1U_0402_16V7K

2

_SDQS1#<5,11>

DDRAB DDRAB

_SDQS1<5,11>

_SDQS2#<5,11>

DDRAB DDRAB_SDQS2<5,11>

CKE0<5>

DDRA_

DDRAB

_SBS2#<5,11>

DDRA_

CLK0<5> CLK0#<5>

DDRA_

DDRA

_SBS0#<5,11>

B

_SWE#<5,11>

DDRAB

_SCAS#<5,11>

SCS1#<5>

DDRA_

_SDQS4#<5,11>

DDRAB DDRAB

_SDQS4<5,11>

DDRAB

_SDQS6#<5,11> _SDQS6<5,11>

DDRAB

2

6

C94 .1U_0402_16V7K

1

2

4

4 C1

@EMC@

DDRAB

DDRAB DDRAB_SDQ3

DDRAB DDRAB

DDRAB_SDQ24 DDRAB

DDRAB

DDRAB DDRAB

DDRA_

DDRAB

DDRAB DDRAB_SMA9

DDRAB DDRAB

DDRA_ DDRA

DDRAB DDRAB

DDRAB_SMA13 DDRA

DDRAB DDRAB

DDRAB DDRA

DDRAB DDRAB

DDRA

DDRAB DDRAB_SDQ43

DDRAB DDRAB_SDQ49

DDRAB DDRAB

DDRAB

DDRAB DDRAB_SDQ59

<Ad

2

C94 .1U_0402_16V7K

1

5V

+1.

B

_SDQ4

DDRAB

_SDQ5

DDRAB

_SDQS0#

DDRAB

_SDQS0

DDRAB

_SDQ6

DDRAB_SDQ7

_SDQ12

DDRAB DDRAB

_SDQ13

_SDM1

DDRAB MEM_

MAB_RST#

_SDQ14

DDRAB DDRAB

_SDQ15

_SDQ20

DDRAB DDRAB

_SDQ21

_SDM2

DDRAB

_SDQ22

DDRAB

_SDQ23

DDRAB

_SDQ28

DDRAB_SDQ29

_SDQS3#

DDRAB DDRAB

_SDQS3

_SDQ30

DDRAB DDRAB

_SDQ31

DDRA_

CKE1

_SMA15

DDRAB

_SMA14

DDRAB

_SMA11

DDRAB DDRAB_SMA7

_SMA6

DDRAB DDRAB

_SMA4

_SMA2

DDRAB DDRAB

_SMA0

CLK1

DDRA_

_

CLK1#

DDRA

DDRAB

_SBS1#

DDRAB

_SRAS#

DDRA_

SCS0#

DDRA_

ODT0

DDRA_ODT1

15mil

_SDQ36

DDRAB DDRAB

_SDQ37

_SDM4

DDRAB

_SDQ38

DDRAB DDRAB

_SDQ39

_SDQ44

DDRAB DDRAB

_SDQ45

_SDQS5#

DDRAB DDRA

_SDQS5

B

DDRAB

_SDQ46

DDRAB_SDQ47

_SDQ52

DDRAB DDRAB_SDQ53

_SDM6

DDRAB

_SDQ54 _SDQ55

DDRAB

_SDQ60

DDRAB

_SDQ61

DDRAB

_SDQS7#

DDRAB

_SDQS7

DDRAB

_SDQ62

DDRAB DDRAB_SDQ63

MAB_EVENT#

MEM_

DDRAB

_SDQS0# <5,11> _SDQS0 <5,11>

DDRAB

_SDQ[0..63]

_SDM[0..7]

_SMA[0..15]

C

DDRAB

_SDQ[0..63] <5,11>

_SDM[0..7] <5,11>

_SMA[0..15] <5,11>

D

E

+1.5V/+0.75VS OF DIMM1

MEM_

DDRAB

_SDQS3# <5,11> _SDQS3 <5,11>

DDRAB

CKE1 <5>

DDRA_

MAB_RST# <5,11>

+1.

5V

C11

C116 .1U_0402_16V7K

C11

7 .1U_0402_16V7K

5 .1U_0402_16V7K

4 .1U_0402_16V7K

1

2

@

C12

C119 .1U_0402_16V7K

C12

8 .1U_0402_16V7K

1

2

@

C12

1 .1U_0402_16V7K

2 .1U_0402_16V7K

0 .1U_0402_16V7K

3 .1U_0402_16V7K

1

2

@

+0.

75VS

C12

C126 .1U_0402_16V7K

C12

@EMC@

9 .1U_0402_16V7K

1

2

C127 4.7U_0603_6.3V6K

@EMC@

8 .1U_0402_16V7K

1

2

VREF for DIMM1,2

CLK1 <5>

DDRA_ DDRA_

CLK1# <5>

_SBS1# <5,11>

DDRAB DDRA

_SRAS# <5,11>

B

DDRA_

SCS0# <5>

DDRA_

ODT0 <5>

DDRA_

ODT1 <5>

EF_CA

+VR

2

1

7

4

C16

C13

1

2

.1U_0402_16V7K

1000P_0402_50V7K

_SDQS5# <5,11>

DDRAB DDRAB

_SDQS5 <5,11>

DDRAB

_SDQS7# <5,11> _SDQS7 <5,11>

DDRAB

MEM_

MAB_EVENT# <5,11>

SDATA0 <7,11,17>

APU_ APU_

+0.

75VS

SCLK0 <7,11, 17>

+VR

EF_DQ

+VR

EF_CA

1K

1 2

MAB_RST#

MEM_

C12

74

100P_0402_50V8J

RP9

1 8 2 7 3 6 4 5

_0804_8P4R_1%

@EMC@

+1.

5V

DIM

M_A H:4mm RVS

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USEDBY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELEC TRONICS, INC.

MAY BE USEDBY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELEC TRONICS, INC.

A

B

MAY BE USEDBY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELEC TRONICS, INC.

C

2014/03/27 2016/03/27

pal Secret Data

Com

Deciphered Date

D

Tit

Size Document N umber Rev

C

Date: Sheet

DDR3

B5W

ursday, April 16, 2015

SODIMM-I Socket

1E_LA-D121P

E

10 33Th

of

pal Electronics, Inc.

Com

le

Tit

1.0

Acer Aspire ES1-521, Aspire ES1-522 Schematics

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