Acer ASPIRE ES1-520ES1 Schematic

A

Co

mpal Confidential

Mo

del Name : Bellemere_BE

Co

mpal Project Name : B5W1E

File Name : LA-D121P

1 1

B

C

D

E

Co

2 2

mpal Confidential

B5W1E Schematics Document

A

MD "Beema" Platform

MD 15W APU With Puma+ Core

A

3 3

LA-D121P REV: 1.0

2015-04-16

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2014/03/27 2016/03/27

Co

mpal Secret Data

Deciphered Date

C

ompal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

CO

VER PAGE

W1E_LA-D121P

B5

133Tuesday, April 21, 2015

E

1.0

of

A

Co

mpal Confidential

Mo

del Name : B5W1E

B

C

D

E

B5W1K B5W1R

1 1

Display Port

Port 0Port 1

AMD Beema/ Kabini/

Memory BUS(DDR3) Single Channel

1.

5V DDRIII 1600MHz

USB2.0

ort 8

P

204pin DDR3-SO-DIMM X2

Page 10,11

P

ort 2

ort 3Port 0

P

ort 5

Carrizo-L

Sub

US

B2.0 Conn.

Board

Port 1

LS-B471P

Card Reader RTS5170 SD only

ge 19

Pa

Port 4

HDM

I Conn.

Page 13

2 2

MINI Card (WLAN/BT)

Page 17

Fa

n Control

3 3

DC

/DC Interface CKT.

wer Circuit DC/DC

Po

Sub

-B471P

LS

P

Board

Page 22

P

age 24

age 24~33

eDP Conn.

LA

N(GbE)

RT

L8111GUS

Transformer RJ45

Pa

ge 12

GP

Page 15

D FT3b APU

AM

USB3.0

P

ort 0

MB 2.0 Conn.

Pa

ge 19 Page 17 Page 12 Page 12

BT

Mini Card

US

B Camera

Touch Screen

Puma+ Core

PCIE

P1GPP2

BGA 769-balls

SP

I LPC

age 5~9

P

HD Audio(AZ)

SATA III

BIOS (8M)

age 8

P

HDD Conn.

ENE

U3

.0 Conn.

Page 19

P

ort 0 Port 1

ODD Conn.

Pa

ge 18

Audio ALC233-VB2

P

age 16

Pa

ge 18

KBC9022

Page 14

Un

iversal Jack

Touch PadInt.KBD

Page 20Page 20

Page 16

In

t. Speaker

Conn.

Page 16

alog MIC

An

P

age 16

screte TPM

Card Reader

RTS5170

4 4

2 i

n 1 (SD)

B 2.0

US conn x1

US

B port 2

P.21

A

B

Di

Page 20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2014/03/27 2016/03/27

www.schematic-x.blogspot.com

Co

mpal Secret Data

Deciphered Date

D

C

ompal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

ompal Electronics, Inc.

BL

OCK DIAGRAMS

W1E_LA-D121P

B5

of

233Thursday, April 16, 2015

of

233Thursday, April 16, 2015

of

E

233Thursday, April 16, 2015

1.0

1

+RTCCONN

RTC Bettary

4304L

2

+1.8VS

+1.5VS

+0.95VS

+RTC_APU

AM

D APU FT3b Beema (15W)

+0

.5~+1.4V

+0

.7~1.325V

+1.5V

VDDCR_CPU @ 21A(EDC)

VDDCR_NB @ 17A(EDC)

VDDIO_MEM_S @ 3A

VDDIO_AZ_ALW @ 0.1A+1.5VS

+0.95VALW

+0.95VS

+1.8VS

+1.8VALW

+3VALW

VDD_095_USB3_Dual @ 1A

VDD_095_ALW @ 0.5A

VD

D_095 @ 5A

VDD_095_GFX @ 0.6A

VDD_18 @ 1.5A

VDD_18_ALW @ 0.5A

VDD_33_ALW @ 0.2A

+3VS VDD_33 @ 0.2A

+1.5V_RTC VDDBT_RTC_G @ 4.5uA

PU

101

AP2138N-1.5TRG 1

5

D D

AC ADAPTOR 19V 65W

VIN

PU301 CHARGER BQ24725ARGRR

BA

TT+

4

9VB

+1

1000

PU RT8880CGQW

3

M DDRIII SODIMMX2

RA

.5V

+1

+0.75VS

VDD_MEM 8A

VTT_MEM 2A

+APU_CORE

+APU_CORE_NB

+1.5V

TTERY

BA

HDM

I

+5

VS_DISP

C C

x1

HDD ODD x1

VS_HDD @ 1.1A

+5 +5VS_ODD @ 2A

dio

Au ALC233-VB2-CG

+AVDD1_HDA +PVDD_HDA +3VS_DVDD +1.5VS_VDDA +1.5VS_DVDDIO

B B

FA

N

+VCC_FAN1

USB2.0 x1 USB3.0 x1

+USB3_VCCA

+5VS

+5VS +3VS +1.5VS

+5VS

+5VALW

EC

+EC_VCC

D panel

LC 14"

+INVPWR_B+ +LCDVDD @ 1.4A

+3VLP

+19VB +3VS

501

PU RT8207PGQW

PU601 SY8288RAC

PU401 SY8286BRAC

PU402 SY8286CRAC

+0.75VS

+0.95VALW

PU602 SY8003DFC

+3VALW

+5VALW

+1.8VALW

U2 EM

5209VF

U4 AO

U3 EM5209VF

+3VS

+5VS

N/CR Combo

LA RTL8411B-CG

+3

V_LAN @ 1A

A A

2 Card(WLAN)

M.

VS_WLAN @ 2A

+3

+3VALW

5

HD Camera

+3

VS_CMOS

uch Screen

To

VS_TS

+5

+3VS

+5VS

Security Classificati on

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2014/03/27 2016/03/27

3

Co

mpal Secret Data

Deciphered Date

Co

mpal Electronics, Inc.

Title

Size Documen t Number Rev

B

Date: Sheet

2

Date: Sheet

mpal Electronics, Inc.

PO

WER MAP

B5W1E_LA-D121P

1

1.0

of

333Thursday, April 16, 2015

of

333Thursday, April 16, 2015

of

333Thursday, April 16, 2015

A

B

Bo

ard ID / SKU ID Table for AD channel

C

Voltage Rails

VIN

B+

+A

PU_CORE OFFON

1 1

+0.95VALW

+0.95VS

+1.8VALW

+1.8VS

+1.5V

+1.5VS

+3VALW

+3

VS

+5VALW ON

+5VS

+RTC_APU

2 2

Bus List

SM

EC

SMBus Port1 (+3VALW)

art Battery

Sm

3 3

4 4

U SMBus Port0 (+3VS)

AP

DDR

DIMM1

DDR

DIMM2

ZZZ

PC

B

Part Number = DAZ1GS00100 PCB B5W1E LA-D121P LS-D121P

ZZZ

HDMI_ROYALTY

ROYALTY HDMI W/LOGO+HDCP

RO0000003HM

45@

DescriptionPower Plane

Adapte r power supply (19V)

AC or batter y power rail fo r power circuit .

Core voltage f or APU

Vo

ltage for On-die VGA of APU OFFOFFON+APU_CORE_NB

0.95V always on power rail

0.95V switched power rail

1.8V always on power rail

1.8V switched power rail

1.5V power rail for APU and DDR

1.5V switched power rail

0.75V switched power rail for DDR terminator

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

EC

SMBus Port2 (+3VS)

vice HEXAddres s

De

HEXAddres sDevice

011X b

0001

Ad

dres sDevice

000Xb

1010

001Xb

1010

U44

EC

Part Number = SA000075S30 S IC KB9022QD LQFP 128P EC CONTROLLER

A

16H

HEX

A0H

A2

9022@

TSI (APU)

SB-

U SMBus Port1(+3VALW)

AP

De

vice Address

H

ON

ON+0.75VS

ON OFFOFF

100X b

1001

S5S3S0

ONONON

ON ON

OFF

ONON

ON

OFFON

OFF

ON ON

OFFOFFON

ON OFFON

OFFON OFF

OFF OFF

ON

ONON

OFFOFFON

ONON

ONONON

98H

HEX

B

M Structure Table

BO

@ CONN@ KBN@ BMA@ CZL@ 233@ 255@ 283@ EMC@ @EMC@ SP@ HDT@ RS@ 45@ 9012@ 9022@ BL@ TPM@ ECI2C@ TPUSB@ BYOC@ NBYOC@

JP@ TP@

BTO ItemBOM Structure

Unpop

Connector part control by ME

Stuff when use Kabini APU

Stuff when use Beema APU

Stuff when use CZ-L APU

Use for Audio Codec ALC233-VB2

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

Use for Audio Codec ALC255

Use for Audio Codec ALC283

EMI pop component

EMI unpop component

APU POWER SEQUENCE

Short pad for clear CMOS

HDT+ for test phase, MP remove

R-short

HDMI royalty

Use KBC9012

G-A

G-B

Use KBC9022

Keyboard backlight

Use discrete TPM module

Use EC I2C T/P

Use USB to I2C IC for T/P

Stuff when support BYOC

Stuff when non-support BYOC

Jump

G-C

G-D

G-E

Test point

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2014/03/27 2016/03/27

Co

mpal Secret Data

Deciphered Date

D

SIGNAL

+RTC

EC_ON

+3VALW/+5VALW

+1.8VALW

+0.95VALW

SYSON

+1.5V

SUSP#

+3VS

+1.8VS

+1.5VS

+0.95VS

VR_ON

+APU_CORE

+APU_CORE_NB

D

BO

ARD ID Table

Board ID

12 13 14* 15 16 17 18 19

SLP_S3#

HIGH HIGH

LOW

LOWS5 (Soft OFF)

re check

Title

Size Document Number Rev

B

Date: Sheet

HIGHHIGH

HIGH

+VALWSLP_S5#

ON

ONLOW

C

ompal Electronics, Inc.

E

PCB Revision EVT DVT PVT Pre-MP

+VS+V Clock

ON

OFF

NO

TES LIST

W1E_LA-D121P

B5

E

ONON

LOW

OFF

1.0

of

433Tuesday, April 21, 2015

of

433Tuesday, April 21, 2015

of

433Tuesday, April 21, 2015

5

@

PU1A

B_SMA[15..0]<10,11>

DDRA

D D

B_SBS0#<10,11>

DDRA

B_SBS1#<10,11>

DDRA

B_SBS2#<10,11>

DDRA

B_SDM[7..0]<10,11>

C C

B B

A A

B_SDQS0<10,11>

DDRA

B_SDQS0#<10,11>

DDRA DDRAB_SDQS1<10,11>

DDRA

B_SDQS1#<10,11>

DDRA

B_SDQS2<10,11>

B_SDQS2#<10,11>

DDRA

B_SDQS3<10,11>

DDRA

DDRAB_SDQS3#<10,11> DDRA

B_SDQS4<10,11>

B_SDQS4#<10,11>

DDRA

B_SDQS5<10,11>

DDRA

B_SDQS5#<10,11>

DDRA DDRAB_SDQS6<10,11>

DDRA

B_SDQS6#<10,11> B_SDQS7<10,11>

DDRA

B_SDQS7#<10,11>

DDRA

_CLK0<10> _CLK0#<10>

DDRA

DDRA_CLK1<10> DDRA_CLK1#<10>

_CLK0<11>

DDRB

_CLK0#<11>

DDRB

DDRB_CLK1<11>

DDRB_CLK1#<11>

ME

M_MAB_R ST#<10,11>

M_MAB_EV ENT#<10,11>

ME

DDRA_CKE0<10> DDRA

_CKE1<10>

_CKE0<11>

DDRB

_CKE1<11>

DDRB

DDRA

_ODT0<10>

DDRA

_ODT1<10>

_ODT0<11>

DDRB

_ODT1<11>

DDRB

DDRA

_SCS0#<10>

DDRA

_SCS1#<10>

_SCS0#<11>

DDRB

_SCS1#<11>

DDRB

DDRA

B_SRAS#<10,11>

DDRA

B_SCAS#<10,11>

B_SWE#<10,11>

DDRA

+M

EM_VREF

T3

3

5

DDRA

DDRA DDRA

DDRA

DDRA DDRA

DDRA

DDRA DDRA

DDRA

DDRA DDRA

DDRA

DDRA DDRA

DDRA

APU

B_SMA0

B_SMA1

B_SMA2

B_SMA3

B_SMA4 B_SMA5

B_SMA6

B_SMA7

B_SMA8

B_SMA9

B_SMA10 B_SMA11

B_SMA12

B_SMA13 B_SMA14

B_SMA15

B_SDM0

B_SDM1 B_SDM2

B_SDM3

B_SDM4 B_SDM5

B_SDM6

B_SDM7

_VREFDQ

UA

AG

38

5

W3

8

W3 W3

4

U3

8

U3

7

4

U3

5

R3

8

N3

8

AG

34

4

R3

7

N3

AN34

L38 L35

38

AJ

AG35

N3

4

2

B3

8

B3

G4

0

N4

1

AG

40

41

AN

40

AY

34

Y4

0

3

B3

3

A3

B4

0

A4

0

H4

1 0

H4

1

P4 P4

0

AH

41

AH

40

1

AP4

0

AP4

BA4

0

AY

41

AY

33

4

BA3

0

AA4

Y4

1

AC

35 34

AC

4

AA3 AA3

2

AE3

8

AE3

7

AA3

8

AA3

G3

8

AE3

4

L34 J3

8

J3

7

J3

4

38

AN AU

38

AN

37

AR

37

34

AJ

AR

38

AL

38

AN

35

37

AJ AL

34

AL

35

40

AD

38

AC

FT3_BGA_769P-T

Part Number =

M_ADD0 M_ADD1

M_ADD2 M_ADD3

M_ADD4 M_ADD5

M_ADD6 M_ADD7

M_ADD8 M_ADD9

M_ADD1 0 M_ADD1 1

M_ADD1 2 M_ADD1 3

M_ADD1 4 M_

ADD15

M_BANK0 M_BANK1

M_BANK2

M_DM0

M_DM1 M_DM2

M_DM3 M_DM4

M_DM5 M_DM6

M_DM7 M_DM8

M_DQS_ H0 M_DQS_ L0

M_DQS_ H1 M_DQS_ L1

M_DQS_ H2 M_DQS_ L2

M_DQS_ H3 M_DQS_ L3

M_DQS_ H4 M_DQS_ L4

M_DQS_ H5 M_DQS_ L5

M_DQS_ H6 M_DQS_ L6

M_DQS_ H7 M_DQS_ L7

M_DQS_ H8 M_DQS_ L8

M_CLK_ H0 M_CLK_ L0

M_CLK_ H1 M_CLK_ L1

M_CLK_ H2 M_CLK_ L2

M_CLK_ H3 M_CLK_ L3

M_RESET _L M_EVENT _L

_CKE0

M0 M0_CKE 1

M1_CKE 0 M1_CKE 1

M0_ODT 0 M0_ODT 1

M1_ODT 0 M1_ODT 1

M0_CS_ L0 M0_CS_ L1

M1_CS_ L0 M1_CS_ L1

M_RAS_ L M_CAS_ L

M_WE_ L

M_VREF

M_VREFD Q

MEMORY

M_ZVDD IO_MEM_S

4

M_DAT A0

M_DAT A1 M_DAT A2

M_DAT A3 M_DAT A4

M_DAT A5 M_DAT A6

M_DAT A7

M_DAT A8

M_DAT A9

M_DAT A10

M_DAT A11 M_DAT A12

M_DAT A13 M_DAT A14

M_DAT A15

M_DAT A16

M_DAT A17 M_DAT A18

M_DAT A19 M_DAT A20

M_DAT A21 M_DAT A22

M_DAT A23

M_DAT A24

M_DAT A25 M_DAT A26

M_DAT A27 M_

DATA2 8

M_DAT A29 M_DAT A30

M_DAT A31

M_DAT A32

M_DAT A33 M_DAT A34

M_DAT A35 M_DAT A36

M_DAT A37 M_DAT A38

M_DAT A39

M_DAT A40

M_DAT A41 M_DAT A42

M_DAT A43 M_DAT A44

M_DAT A45 M_DAT A46

M_DAT A47

M_DAT A48

M_DAT A49 M_DAT A50

M_DAT A51 M_DAT A52

M_DAT A53 M_DAT A54

M_DAT A55

M_DAT A56

M_DAT A57 M_DAT A58

M_DAT A59 M_DAT A60

M_DAT A61 M_DAT A62

M_DAT A63

M_CHEC K0

M_CHEC K1 M_CHEC K2

M_CHEC K3 M_CHEC K4

M_CHEC K5 M_CHEC K6

M_CHEC K7

4

B3

0

DDRA

2

A3

DDRA

5

B3

DDRA

A3

6

DDRA

B2

9

DDRA

A3

0

DDRA

4

A3

DDRA

4

B3

DDRA

B3

7

DDRA

A3

8

DDRA

0

D4

DDRA

1

D4

DDRA

B36

DDRA

A37

DDRA

B4

1

DDRA

0

C4

DDRA

F40

DDRA

F4

1

DDRA

K4

0

DDRA

1

K4

DDRA

0

E4

DDRA

E4

1

DDRA

J4

0

DDRA

J4

1

DDRA

1

M4

DDRA

N4

0

DDRA

T4

1

DDRA

U4

0

DDRA

L40

DDRA

0

M4

DDRA

R4

0

DDRA

T4

0

DDRA

40

AF

DDRA

41

AF

DDRA

AK4

0

DDRA

AK4

1

DDRA

AE4

0

DDRA

1

AE4

DDRA

40

AJ

DDRA

AJ

41

DDRA

AM

41

DDRA

40

AN

DDRA

41

AT

DDRA

AU

40

DDRA

AL

40

DDRA

AM

40

DDRA

40

AR

DDRA

40

AT

DDRA

AV4

1

DDRA

AW

40

DDRA

8

BA3

DDRA

37

AY

DDRA

AU

41

DDRA

AV4

0

DDRA

AY

39

DDRA

38

AY

DDRA

BA3

6

DDRA

AY

35

DDRA

BA3

2

DDRA

31

AY

DDRA

7

BA3

DDRA

AY

36

DDRA

BA3

3

DDRA

AY

32

DDRAB_SDQ63

1

V4

W4

0

AB4

0

AC

40

1

U4

0

V4 AA4

1

AB4

1

41

AD

B_SDQ[63..0] <10,11>

1

R7

4

39.2_0402_1%

DDRA

Beema

IE_ARX_DTX_P1<15>

PC

IE_ARX_DTX_N1<15>

PC

IE_ARX_DTX_P2<17> IE_ARX_DTX_N2<17>

PC

.95VS

+0

1

R4

1.69K_0402_1%

2

+1

04

.5V

B_SDQ0

B_SDQ1

B_SDQ2

B_SDQ3

B_SDQ4

B_SDQ5 B_SDQ6

B_SDQ7

B_SDQ8

B_SDQ9

B_SDQ10

B_SDQ11

B_SDQ12

B_SDQ13

B_SDQ14

B_SDQ15

B_SDQ16 B_SDQ17

B_SDQ18

B_SDQ19

B_SDQ20

B_SDQ21

B_SDQ22

B_SDQ23

B_SDQ24

B_SDQ25

B_SDQ26

B_SDQ27

B_SDQ28 B_SDQ29

B_SDQ30

B_SDQ31

B_SDQ32

B_SDQ33

B_SDQ34

B_SDQ35

B_SDQ36

B_SDQ37

B_SDQ38

B_SDQ39

B_SDQ40

B_SDQ41

B_SDQ42

B_SDQ43

B_SDQ44

B_SDQ45

B_SDQ46

B_SDQ47

B_SDQ48

B_SDQ49

B_SDQ50

B_SDQ51

B_SDQ52

B_SDQ53

B_SDQ54

B_SDQ55

B_SDQ56

B_SDQ57

B_SDQ58

B_SDQ59

B_SDQ60

B_SDQ61

B_SDQ62

ZVDDIO

M_

Security Classificati on

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

UA

PU1

CZ-L

AM7210ITJ44JB 1.8G BG A 769P

A4_7210@

SA00008R420

UA

PU1

EM6010IUJ23JB 1.35G BG A 769P

E1_6010@

SA00007RC20

@

UA

PU1B

R1

0

P_GPP_RXP0

R8

P_

GPP_RXN0

R5

P_

GPP_RXP1

R4

GPP_RXN1

P_

N5

P_

GPP_RXP2

N4

P_

GPP_RXN2

0

N1

P_GPP_RXP3

N8

P_

GPP_RXN3

2

TX_ZVDD_095

P_

2014/03/27 2016/03/27

W8

P_

TX_ZVDD_095

L5

P_

GFX_RXP0

L4

GFX_RXN0

P_

J5

GFX_RXP1

P_

J4

P_

GFX_RXN1

G5

GFX_RXP2

P_

G4

GFX_RXN2

P_

D7

P_

GFX_RXP3

E7

P_

GFX_RXN3

FT3_BGA_769P-T

Part Number =

Co

mpal Secret Data

Deciphered Date

3

UA

PU1

EM6110ITJ44JB 1.5G BG A 769P

E2_6110@

SA00007RB20

IE

PC

P_

GPP_TXP0

P_

GPP_TXN0

P_

LAN

WLAN

GPP_TXP1

GPP_TXN1

P_

GPP_TXP2

GPP_TXN2

P_

GPP_TXP3

P_

GPP_TXN3

RX_ZVDD_095

P_

GFX_TXP0 GFX_TXN0

P_

GFX_TXP1

P_ P_

GFX_TXN1

GFX_TXP2

P_

GFX_TXN2

P_

GFX_TXP3

P_

GFX_TXN3

2

KABINI

UA

PU1

AM7310ITJ44JB 2G FC BGA 769P

A6_7310@

SA00008K930

UA

PU1

AM6210ITJ44JB 1.8G BG A 769P

A4_6210@

SA00007RA20

L2

L1

K2

PC

IE_ATX_DRX_P1

K1

PC

IE_ATX_DRX_N1

J2

IE_ATX_DRX_P2

PC

J1

IE_ATX_DRX_N2

PC

H2

H1

W7

RX_ZVDD_095

P_

G2 G1

F2 F1

E2 E1

D2 D1

+1.5V

1

R7

5

1K_0402_1%

2

1

6

R7 1K_0402_1%

2

UA

PU1

EM2100CJ23HM 1G BGA7 69

E1_2100@

SA0

0006QX70

UA

PU1

AM7410ITJ44JB 2.2G F CBGA 769P

A8_7410@

SA00008K660

UA

PU1

AM6310ITJ44JB 1.8G BG A 769P

A6_6310@

SA00007R920

1

2

9 .1U_0402_16V7K

C1

1

2

0 .1U_0402_16V7K

C2

1

2

C1

7 .1U_0402_16V7K

1

2

C1

8 .1U_0402_16V7K

.95VS

+0

1

2

R7

3

1K_0402_1%

MEMORY VREF

+M

EM_VREF

1

C3

37

1U_0402_6.3V6K

2

Title

P0

Size Documen t Number Rev

Date: Sheet

P0

B

B5W1E_LA-D121P

2

C1 .1U_0402_1 6V7K

1

Co

mpal Electronics, Inc.

5-FT3 MEMORY INTERFACE/PCIE

1

UA

PU1

EM2500BJ23HM 1.4G BGA

E1_2500@

SA0

UA

PU1

EM7110ITJ44JB 1.8G F CBGA 769P

E2_7110@

SA00008MA20

UA

PU1

AM6410ITJ44JB 2G BGA 7 69P

A8_6410@

SA00007TQ80

IE_ATX_C_DRX_P1 <15>

PC

IE_ATX_C_DRX_N1 <15>

PC

IE_ATX_C_DRX_P2 <17>

IE_ATX_C_DRX_N2 <17>

PC

+1.5V

2

7

R7 1K_0402_1%

63

1

0006R670

1

M_MAB_EV ENT#

ME

of

533Thursday, April 16, 2015

of

533Thursday, April 16, 2015

of

533Thursday, April 16, 2015

1.0

2

+1.8VS

+1

.8VS

E

8

7

6

5

+3

VS

8

7

6

5

+1.8VS

8

7

6

5

1.0

of

633Thursday, April 16, 2015

of

633Thursday, April 16, 2015

of

633Thursday, April 16, 2015

E

.8VS

D

A4W1E

C_RED

DA

C_GRN

DA

C_BLU

DA

R1

C_HSYNC

DA

NOTE: DAC_HSYNC PU FOR HDMI ENABLE PD FOR CUSTOMER (DNI)

APU APU

APU

APU APU

APU

APU APU_TEST18

Title

Size Documen t Number Rev

B

Date: Sheet

D

Date: Sheet

_TEST16 _TEST17

_TEST14

_TEST15

_TEST37

_TEST36

_TEST37 _TEST36

_TEST35

_TDI

_TMS

_TCK

_DBREQ#

_TRST#

_TEST19

R1

RP6

1

2

3

4

1K_0804_8P4R_5%

RP

1

2

3

4

1K_0804_8P4R_5%

Co

FT3

23

RP

1

2

3

4

75_0804_8P4R_1%

1

15 1K_0402_5%

1

13 1K_0402_5%

@

7

RP

1

2

3

4

1K_0804_8P4R_5%

@

3

RP

1

2

3

4

1K_0804_8P4R_5%

1

14 1K_0402_5%@

8

7

6

5

8

7

6

5

mpal Electronics, Inc.

DISP/MISC/HDT

B5W1E_LA-D121P

C

B1

6

_150_ZVSS

DP

A2

1

_2K_ZVSS

DP

7

B1

7

A1 A1

8

7

D1

7

E1

H1

9

5

D1

5

E1

H17

4

B1

DA

C_RED

A14

C_GRN

DA

B1

5

C_BLU

DA

G1

9

C_HSYNC

DA

E1

9

C_VSYNC

DA

9

D1

DA

C_DDC_CLK

1

D2

DA

C_DDC_DATA

A1

6

C_ZVSS

DA

7

H2

APU

_TEST4

9

H2

APU

_TEST5

D2

5

A2

7

_TEST14

APU

B2

7

_TEST15

APU

6

A2

APU

_TEST16

6

B2

APU

_TEST17

B2

8

_TEST18

APU

A2

8

_TEST19

APU

B2

4

_TEST25_H

APU

4

A2

APU

_TEST25_L

5

AV3

APU

_TEST28_H

AU

35

_TEST28_L

APU

E3

3

_TEST31

APU

9

A2

APU

_TEST34_L

1

H2

APU

_TEST36

H2

5

_TEST37

APU

AJ

10

_TEST42

APU

8

AJ

APU

_TEST43

2

R3

APU

_TEST39

N3

2

_TEST40

APU

AP2

9

_TEST41

APU

1

E2

APU

_TEST35

1

2

EMC@

1

2

EMC@

1

2

EMC@

1

2

@EMC@

1

2

@EMC@

2014/03/27 2016/03/27

C

1 2

R4

01 150_0402_1%

1 2

R4

00 2K_0402_1%

EN

BKL <14>

VDD <12>

EN

VTPW M <12>

IN

I_CLK <13>

HDM

I_DATA <13>

HDM

I_HPD <13>

ED

P_AUXP <12>

ED

P_AUXN <12>

ED

P_HPD <12>

CRT

A4W1E

503

T2

504

T2

501

502

T2

1

R4

16 499_0402_1%

Co

mpal Secret Data

2

T1

3

4

T1

1

R1

9 511_0402_1%

8 511_0402_1%

R1

T4

T5

T6

T7

T1

T8

T9

T11

T12

Deciphered Date

2

1

2

0

+1

_SVT_R _SVC_R

_SVD_R

_RST#

T_RST#

_PWRGD

T_PWRGD

_PROCHOT#

_ALERT#

_TDI

_TDO

_TCK

_TMS

_TRST#

_DBRDY _DBREQ#

B

@

PU1C

UA

A9

TD

P1_TXP0

B9

TD

P1_TXN0

0

A1

TDP1_TXP1

B1

0

TDP1_TXN1

A1

1

TDP1_TXP2

1

B1

TDP1_TXN2

A1

2

TDP1_TXP3

B1

2

TDP1_TXN3

A4

LT

DP0_TXP0

B4

DP0_TXN0

LT

A5

LTDP0_TXP1

B5

LT

DP0_TXN1

A6

DP0_TXP2

LT

B6

LTDP0_TXN2

A7

LT

DP0_TXP3

B7

LT

DP0_TXN3

K1

5

DISP_CLKIN_H

H1

5

DISP_CLKIN_L

1

G3

SVT

D2

7

SVC

E2

9

SVD

2

B2

SIC

1

B2

SID

B2

0

APU_RST_L

A2

0

LDT_RST_L

9

B1

APU_PWROK

A1

9

LDT_PWROK

A2

2

PROCHOT_L

8

B1

ALERT_L

D2

9

TDI

D3

1

TDO

D3

5

TCK

3

D3

TMS

7

G2

TRST_L

B2

5

DBRDY

A2

5

DBREQ_L

3

D2

VDDCR_NB_SEN SE

3

G2

VDDCR_CPU_ SENSE

E2

5

VDDIO_MEM_S_SENSE

E2

3

VSS_SENSE

3

AV3

VDD_095_FB_H

33

AU

VDD_095_FB_L

FT3_BGA_769P-T

Part Number =

Close To PU1000

Close To APU's Pin

B

DIS

PLAY/SVI2/JTAG/TEST

HDMI_EN/DP_STEREOSYNC

Security Classificati on

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DP_150_ZVSS

DP_2K_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP TDP1_AUXN

TDP1_HPD

LTDP0_AUXP

LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_GREEN

DAC_BLUE

DAC_HSYNC

DAC_VSYNC

DAC_SCL

DAC_SDA

DAC_ZVSS

THERMDA THERMDC

DIECRACKMON

BP0

BP1 BP2

BP3

PLLTEST1

PLLTEST0

BYPASSCLK_H

BYPASSCLK_L

PLLCHRZ_H

PLLCHRZ_L

M_TEST

GIO_TSTDTM0_SERIALCLK

GIO_TSTDTM0_CLKINIT

FREE_2

USB_ATEST0

USB_ATEST1 M_ANAL OGIN

M_ANAL OGOUT

TMON_CAL

APU

_PWRGD

APU

_RST#

_PROCHOT#

APU

APU_ALERT#

C1272 33P_0402_50V8J

C1

270 33P_0402_50V8J

273 33P_0402_50V8J

276 100P_0402_50V8J

277 100P_0402_50V8J

A

APU

_DP1_P0<13>

APU

_DP1_N0<13>

_DP1_P1<13>

APU

_DP1_N1<13>

HDM

I

1 1

APU

APU APU

ED

_DP1_P2<13> _DP1_N2<13>

_DP1_P3<13> _DP1_N3<13>

P_TXP0<12>

P_TXN0<12>

P_TXP1<12>

P_TXN1<12>

eDP

1

_SMB_CK2<14>

EC

_SMB_DA2<14>

EC

1

R1

17 0_0402_5%KBN@

1

R118 0_0402_5%KBN @

1

R1

20 0_0402_5%RS@

_VDDNB_SEN<30>

APU_VDD_SEN<30>

_VDD_RUN_F B_L<30>

8

7

6

5

8

7

6

5

2

+3VS

.8VS

+1

74 33_0402_5%

_SVT<30>

APU

_SVC<30>

APU

_ALERT#

EC

_SMB_DA2

_PROCHOT#

APU

_SMB_CK2

EC

_SVD<30>

PR

APU

_PWRGD<30>

OCHOT#<7,14,30>

A4W1E D VT

2 2

3 3

PU +1.8VS

4 4

_SVT_R

APU

APU_SVC_R

APU_SVD_R

APU_RST# APU_PWRGD

R6

69 33_0402_5%

R6

70 33_0402_5%

APU

4

RP

1

2

3

4

1K_0804_8P4R_5%

@

RP

5

1

2

3

4

1K_0804_8P4R_5%

1

R80 300_0402_5%

1

R82 300_0402_5%

A

T15

T18

APU APU

APU

LD

APU

LD

APU

APU APU

A

1 2

15 150P_0402_50V8J

C6

1 2

02 33_0402_5%

LPC_RST#<14,20>

PCIE_RST#<15,17>

APU_

1 1

2 2

1

2

@

1

R3

939 10K_0402_5%

R3

938 10K_0402_5%

R3

937 10K_0402_5%

RST#_AUDIO<16>

HDA_

HDA_ HDA_

+3VALW

3 3

+3VS

2

@

1

2

@

Ch

ecklist suggestion

SYNC_AUDIO<16>

SDOUT_AUDIO<16> BITCLK_AUDIO<16>

1

01 100K_0402_5%@

R9

1

05 100K_0402_5%

R9

1

06 100K_0402_5%@

R9

1

R6

75 1K_0402_5%@

1

76 2.2K_0402_5%

R6

1

77 2.2K_0402_5%

R6

1

R684 10K_0402_5%@

1

R688 10K_0402_5%@

R6

1 2

R9

07 33_0402_5%

1 2

C912 150P_0402_50V8J

PBT

N_OUT#<14>

SY

S_PWRGD_EC<14>

PCIE_WAKE#<15>

APU_

P_S3#<14>

SL

P_S5#<14>

SL

0 15K_0402_5%

R4

1 15K_0402_5%

R4

2 15K_0402_5%

#<14>

KBRST GA

TEA20<14>

EC_

SCI#<14>

EC_

SMI#<14>

N_CLKREQ#<15>

LA

AN_CLKREQ#<17>

WL

USB_

OC0#<19>

HDA_

SDIN0<16>

EMC@

RP1

3

1

2

3

4

33_0804_8P4R_5%

2

1

8

HDA_

7

HDA_SYNC

6

HDA_

5

HDA_

PCIE_WAKE#

APU_

OC0#

USB_

OC1#

USB_

EC_

LID_OUT#

SCLK0

APU_

SDATA0

APU_

HDA_BITCLK HDA_SDIN0

T16

2

RST#

SDOUT BITCLK

C_RST_A#

LP

APU_

PCIE_RST#_R

EC_

RSMRST#_R

APU_

PCIE_WAKE#

APU_

LA

N_CLKREQ#

WL

AN_CLKREQ#

T21

OC0#

USB_

OC1#

T19

T20

HDA_BITCLK

SDOUT

HDA_

SDIN0

HDA_

SDIN1

HDA_ HDA_

SDIN2

HDA_

SDIN3

HDA_

SYNC

HDA_

RST#

_X1

32K

_X2

EC_

RSMRST#<14>

TEST0

TEST1

TEST2

32.768KMHz CRYSTAL

32K_X1

1

C682 18P_0402_50V8J

2

A

Y3

2

32K_X2

4 4

32.768KHZ_12.5PF_CM31532768DZFT

2

R914 20M_0402_5%

1

C686 18P_0402_50V8J

2

SJ100001K00

1

B

@

D

UAPU1

AY4

LP

C_RST_L

AY9

E_RST_L

PCI

AY5

RST_L

RSM

BA8

PW

R_BTN_L

19

AM

PW

R_GOOD

AY7

SY

S_RESET_L/GEVENT19_L

AW

11

WAKE_L/GEVENT8_L

AY3

P_S3_L

SL

BA5

P_S5_L

SL

AU13

TE

ST0

0

AY1

TE

ST1/TMS

AY6

ST2

TE

23

AR AR

AP1 AV1

BA1

AV1

AU

AW

AR

AV2 AY2

_L

KBRST

31

20IN/GEVENT0_L

GA

AN

5

LP

C_PME_L/GEVENT3_L

AL7

LP

C_SMI_L/GEVENT23_L

5

PRES/IR_RX0/GEVENT16_L

AC_

3

_TX 0/GEVE NT21 _L

IR

BA9

_TX 1/GEVE NT6_ L

IR

0

IR

_RX 1/GEVE NT20 _L

5

IR

_LE D_L/LL B_L/G PIO18 4

29

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60

29

K_REQ1_L/GPIO61

CL

27

K_REQ2_L/GPIO62

CL

7

K_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63

CL

9

CL

K_REQG_L/GPIO65/OSCIN

AY8

USB_

OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L

1

AW

USB_

OC1_L/TDI/GEVENT13_L

AV1

OC2_L/TCK/GEVENT14_L

USB_

AY1

OC3_L/TDO/GEVENT15_L

USB_

2

AN

AZ

_BITCLK

AN

1

AZ

_SDOUT

AK2

AZ

_SDIN0/GPIO167

AK1

AZ

_SDIN1/GPIO168

1

AM

AZ_SDIN2/GPIO169

AL

2

_SDIN3/GPIO170

AZ

AM

2

_SYNC

AZ

1

AL

_RST_L

AZ

AJ

2

X3

2K_X1

AJ

1

2K_X2

X3

FT3_BGA_769P-T

Part Number =

A4W1 E

1

D3

51V-40 SOD-323

RB7

2

R3

945 0_0402_5%@

RB751 Max Vf=0.37V

B

AC

PI/SD/AZ/GPIO/RTC/MISC

C

SD_

PWR_CTRL

CLK/GPIO73

SD_

CMD/GPIO74

SD_

CD/GPIO75

SD_

WP/GPIO76

SD_

DATA0/GPIO77

SD_DATA1/GPIO78

DATA2/GPIO79

SD_

DATA3/GPIO80

SD_

LED/GPIO45

SCL

0/GPIO43

/GPIO47

SDA0

1/GPIO227

SCL

/GPIO228

SDA1

GP

IO49

GP

IO50

GPIO51

IO55

GP

IO57

GP

IO58

GP

IO59

GP

IO64

SPKR/

GPIO66

GPIO68

IO69

GP

IO70

GP

IO71

GP

IO174

GP

GE

VENT2_L

GE

VENT4_L

VENT7_L

GE

VENT10_L

GE

VENT11_L

GE GE

VENT17_L

BL

INK/GEVENT18_L

GE

VENT22_L

GENINT1_L/GPIO32

NINT2_L/GPIO33

GE

NOUT0/GPIO52

FA

NIN0/GPIO56

CCLK

RT

BA2

AY2

AY2 BA2

BA2 AY2

AY24 BA2

AY2

AU

AV2

AY1

BA1

AP27

AY2 BA2

AV2 AP2

BA2 AV1

AY2 BA2

AU AY2

AV2 AM

BA3

AV1

BA4 AR

AP1 AP11

AN AU

BA6

BA2

AP2

AV3

AU

AV1

3

2

3

0 0

2 1

4

5

25

5

1

8 8

3 1

6 9

7 7

21

6

1

21

7

15

7

8 17

9

3

1

31

1

SCLK0

APU_ APU_

SDATA0

APU_

SCLK1

APU_SDATA1

GPIO49

APU_

GPIO51

APU_

GPIO71

GPIO174

APU_

VENT2#

GE

VENT4#

GE

NINT1_L

GE

NINT2_L

RT

C_CLK

SCLK0 <10,11,17>

APU_

SDATA0 <10,11,17>

APU_

P0 <18>

DEVSL

APU_

SPKR <16>

1

R6

61 0_0402_5%@

86 10K_0402_5%

R6

89 10K_0402_5%

EC_

LID_OUT# <14>

2

1

2

1

2

T17

D

PRO

CHOT# <6,14,30>

STRAPS OF APU

LPC_FRAME#

SPI ROM

2

LPC_FRAME#<8,14> LPC_CLK0_EC<8,14>

LPC_CLK1<8,20>

(DEFAULT)

LPC ROM

A4W1 E DV T

H

+1.

8VALW

L

2

R3

47K_0402_5%

RSMRST#_R

EC_

SYS_PWRGD_EC

C209

1U_0402_6.3V6K

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R6

1

2

85

10K_0402_5%

1

C212 1U_0402_6.3V6K

2

2014/03/27 2016/03/27

C

+3VS

1

946 10K_0402_5%

R3

1

947 10K_0402_5%@

R3

1

R3948 10K_0402_5%

2

C948 .1U_040 2_16V7K

1

@EMC@

mpal Secret Data

Co

Deciphered Date

45

LPC_CLK0_EC LPC_CLK1 GEVENT2_L

BOOT FAIL TIMER ENABLED

BOOT FAIL TIMER DISABLED (DEFAULT)

1

@

02

R9 10K_0402_5%

2

GEVENT2#

RTC_CLK

1

@

R903 2K_0402_5%

2

D

E

APU_

SCLK1

APU_SDATA1

A4W1 E

APU_

GPIO51

GPIO49

2

1K_0402_5%

1

10K_0402_5%

2

12

CZL@

R6

+3VALW

R3

9434.7K_0402_5%

R39444.7K_0402_5%

+3VS

2

KBN@

94

92

95

R6

1K_0402_5%

1

91

R6

10K_0402_5%

2

GPIO51 GPIO49Platform identify

Be

GE

NINT1_L

NINT2_L

ema Kabini Carrizo_L (Reserve) NA (Reserve)

1

VENT4#

GE

1

@

9200_0402_5%

R3

1

RS@

R3

9230_0402_5%

GE

2

0 0 1 11

2

87 10K_0402_5%@

R6

2

R6

68 10K_0402_5%

14"

VENT4# 0 1

TP

_I2C_INT#_APU <20>

0 1 0

+3VALW

15"Project identify

(DEFAULT)

RTC_CLK

CLKGEN ENABLE (DEFAULT)

CLKGEN DISABLED

1

@

04

R9 10K_0402_5%

2

1

R926 2K_0402_5%

2

Ti

tle

Title

Size Document Number Rev

Custom

Date: Sheet

1.8V SPI ROM

3.3V SPI ROM (DEFAULT)

1

@

R9

10K_0402_5%

2

1

@

R927

2K_0402_5%

2

Co

1

25

FT3

B5W1E_LA-D121P

@

28

R9 10K_0402_5%

2

1

R929 2K_0402_5%

2

mpal Electronics, Inc.

GPIO/AZ/MISC/STRAPS

E

NORMAL POWR UP/RESET TIMING (DEFAULT)

FAST POWER UP/RESET TIMING FOR SIMULATION

+3VALW

1

49

R9 10K_0402_5%

2

1

@

R950

2.2K_0402_5%

2

of

733Thursday, April 16, 2015

of

733Thursday, April 16, 2015

1.0

1

2

C635

@

.1U_0402_1 6V7K

_SPI_CLK _SPI_MOSI

1

_SPI_CLK

R6

17

10_0402_5%

E

+3VALW

@EMC@

E

2

1

2

C6

36

@EMC@

10P_0402_50V8J

of

833Thursday, April 16, 2015

of

833Thursday, April 16, 2015

of

833Thursday, April 16, 2015

1.0

A

BA1

SAT

A_FTX_DRX_P0<18>

SAT

HDD

1 1

ODD

.95VS

+0

2 2

LAN

WLAN

C_CLK0_EC<7,14>

LP LP

C_CLK1<7 ,20>

3 3

1

2

R938

1M_0402_5%

2

4 4

3

12

C794

6.8P_0402_50V8C

A_FTX_DRX_N0<18>

A_FRX_DTX_N0<18>

SAT

A_FRX_DTX_P0<18 >

SAT

A_FTX_DRX_P1<18> A_FTX_DRX_N1<18>

SAT

A_FRX_DTX_N1<18>

SAT SAT

A_FRX_DTX_P1<18 >

2

R9

0 1K_0402_1%

2

6 1K_0402_1%

R9

2

+3

VS

LPC_AD0<14>

LPC_AD1<14>

LP

LPC_FRAME#<7,14>

SER

CL

LP

1

4

@

R6

33

10K_0402_5%

CL

K_PCIE_LAN<15>

K_PCIE_LAN#<15>

CL

CLK_PCIE_WLAN<17>

CL

K_PCIE_WLAN#<17>

C_AD2<14>

C_AD3<14>

IRQ<14>

KRUN#<20>

CPD#<20>

48M

1

Y1

48M

HZ_8PF_X3S048000D81H-W

Part Number = SJ10000AF00

4

1

C795

5.6P_0402_50V8D

2

SE07156AD80

A

_X2

_X1

1

R1

03 0_0402_5%RS@

04 0_0402_5%RS@

R1

SAT

A_ZVSS

SAT

A_ZVDD

A_ACT#

SAT

48M

_X1

_X2

48M

1

2

1

2

AY

BA1 AY

AY BA1

AR AP1

BA3

AY

BA1

AC

AP1

AW

AV2 AP2

AC

AE4

AE5

AC

AA5

AA4

AY

AT AT

AR AR

AP2 AP1

AV2

4

14

6

16

19

9

17

7

19

9

0

12

2

U4

U5

8

10

4

5

3

N2

N1

2 2

2 1

9 5

B

@

PU1E

UA

SATA_TX0P SATA_TX0N

SATA_RX0N SATA_RX0P

SATA_TX1P SATA_TX1N

SATA_RX1N SATA_RX1P

SATA_ZVSS SATA_ZVDD_095

SATA_ACT_L/GPIO67

SATA_X1

SATA_X2

GF

X_CLKP

GF

X_CLKN

GPP_CLK0P

GPP_CLK0N

GP

P_CLK1P

GP

P_CLK1N

GPP_CLK2P

GPP_CLK2N

GP

P_CLK3P

P_CLK3N

GP

X14M_25M_48M_OSC

8M_X1

X4

8M_X2

LPCCLK0 LPCCLK1

LAD0 LAD1

LAD2 LAD3

RAME_L

LF

RQ0_L

LD

SERIRQ/GPIO48 LPC_CLKRUN_L

LP

C_PD_L/GEVENT5_L/SPI_TPM_CS_L

FT3_BGA_769P-T

Part Number =

B

K/SATA/USB/SPI/LPC

CL

B_HSD5N

B_HSD8P

B_HSD8N

B_HSD9P

B_HSD9N

W4

AG

AL

AJ

AG

AG AG2

AF

AE1 AE2

AD

AC AC

AB1

AB2

AA1

AA2

AE1

AE8

T2

T1

V2

V1

R1

R2

W1

W2

AU

AW AR

AR AR

AU AU

US

BCLK/14M_25M_48M_OSC

USB_ZVSS

USB_HSD0P

USB_HSD0N

USB_HSD1P

USB_HSD1N

USB_HSD2P

USB_HSD2N

USB_HSD3P USB_HSD3N

USB_HSD4P

USB_HSD4N

USB_HSD5P US

USB_HSD6P

USB_HSD6N

USB_HSD7P USB_HSD7N

US

B_SS_ZVDD_095_USB3_DUAL

Security Classificati on

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB_SS_ZVSS

US

B_SS_0TXP

B_SS_0TXN

US

B_SS_0RXP

US

B_SS_0RXN

B_SS_1TXP

US

B_SS_1TXN

US

B_SS_1RXP

B_SS_1RXN

US

SPI_CLK/GPIO162

SPI_CS1_L/GPIO165 SPI_CS2_L/GPIO166

SPI_DO/GPIO163

SPI_DI/GPIO164

SPI_HOLD_L/GEVENT9 _L

SPI_WP_L/GPIO161

Issued Date

C

4

US

B_ZVSS

4

5

4

5

7

8

1

2

1

2

1 2

0

BSS_ZVSS

US

BSS_ZVDD

US

7

_SPI_CLK_R

APU

9

APU

_SPI_CS1#

4

11

_SPI_MOSI

APU

7

_SPI_MISO

APU

11

_SPI_HOLD#

APU

9

APU

_SPI_WP#

1 2

R6

41 11.8K_0402_1%

B20_P0 <19>

US US

B20_N0 <19>

B20_P1 <19>

US

B20_N1 <19>

US

B20_P2 <17>

US

B20_N2 <17>

B20_P3 <12>

US

B20_N3 <12>

US

B20_P4 <19>

B20_N4 <19>

US

B20_P5 <12>

US US

B20_N5 <12>

B20_P6 <21>

US

B20_N6 <21>

US

B20_P8 <19>

US

B20_N8 <19>

US

1

05 0_0402_5%RS@

T37

2

B3_FTX_DRX_P0 <19>

US

B3_FTX_DRX_N0 <19>

US

B3_FRX_DTX_P0 <19> B3_FRX_DTX_N0 <19>

US

2

44 1K_0402_1%

R6

45 1K_0402_1%

R1

APU

+0.95VALW

_SPI_CLK

8MB SPI ROM48MHz CRYSTAL

+3

VALW

RP12

1

8

_SPI_CS1#

2

3

4

Co

mpal Secret Data

2014/03/27 2016/03/27

C

mpal Secret Data

Deciphered Date

APU

7

_SPI_WP#

APU

6

APU_SPI_HOLD#

5

10K_0804_8P4R_5%

D

US

B/B port 0

SUB/B USB2

WLAN/BT combo

CAMERA

SUB/B CR

Touch Screen

USB 2 I2C Bridge

MB USB3.0 port0 (2.0)

1

_SPI_CS1#

APU APU_SPI_MISO APU

_SPI_WP#

D

2

676 0_0402_5%RS@

R1

677 0_0402_5%RS@

R1

R1678 0_0402_5%RS@

R1

679 0_0402_5%RS@

Port 0-3 USB OHCI1 ( Dev 12 Func 0 ) EHCI1 ( Dev 12 Func 2 )

Port 4-7 USB OHCI2 ( Dev 13 Func 0 ) EHCI2 ( Dev 13 Func 2 )

USB2.0 Only Port 8-9 USB OHCI2 ( Dev 16 Func 0 ) EHCI2 ( Dev 16 Func 2 )

USB3.0 Port 0-1 USB XHCI ( Dev 10 Func 0 )

EC

_SPI_CLK <14 > _SPI_CS1# <1 4>

EC

EC_SPI_MOSI <14>

_SPI_MISO <14>

EC

U5

6

1

CS#

2

DO(IO1)

3 4

HOLD#(IO3)

#(IO2)

WP

D

GN

W25Q64FVSSIQ_SO8

SA000039A30

A4W1E

Title

Size Documen t Number Rev

B

Date: Sheet

8

VCC

7

APU_SPI_HOLD#

6

APU

K

CL

5

(IO0)

DI

Co

FT3

B5W1E_LA-D121P

APU

mpal Electronics, Inc.

SATA/CLK/USB/SPI

CORE POWER OF APU

+A

PU_CORE

VDDCR_CPU

C1 79 1U_0402_6.3V6K

C1 80 1U_0402_6.3V6K

1

2

A

C1

C182 1U_0402_6.3V6K

C1 81 1U_0402_6.3V6K

1

2

C1

84 1U_0402_6.3V6K

86 1U_0402_6.3V6K

83 1U_0402_6.3V6K

1

2

1

2

C1

89 1U_0402_6.3V6K

90 180P_0402_50V8J

87 1U_0402_6.3V6K

88 1U_0402_6.3V6K

1

2

B

C

D

E

1 1

INTEGRATED GPU POWER OF APU

PU_CORE_NB

+A

+1.5V/+1.5VS OF APU

.5V

+1

2 2

VDDIO_MEM_S

C9

49 10U_0603_6.3V6M

25 10U_0603_6.3V6M

24 10U_0603_6.3V6M

1

2

@

+0.95VALW/+0.95VS OF APU

VDD_095

+0

.95VS

C1

C9 35 10U_0603_6.3V6M

1

2

3 3

VDD_095_USB3_DUAL

C2

C934 10U_0603_6.3V6M

C1

99 1U_0402_6.3V6K

05 1U_0402_6.3V6K

98 1U_0402_6.3V6K

1

2

@

+0.95VALW

C9

C938 10U_0603_6.3V6M

37 10U_0603_6.3V6M

1

2

VDDCR_NB

C2 00 1U_0402_6.3V6K

C9

23 1U_0402_6.3V6K

26 .1U_0402_16V7K

1

2

C2

04 1U_0402_6.3V6K

06 1U_0402_6.3V6K

60 1U_0402_6.3V6K

1

2

C2

16 1U_0402_6.3V6K

14 1U_0402_6.3V6K

1

2

@

+3VALW/+3VS OF APU

VDD_33_ALWVDD_33

C2 54 1U_0402_6.3V6K

1

2

1

2

C2 45 180P_0402_50V8J

C2

56 180P_0402_50V8J

55 1U_0402_6.3V6K

1

2

C946 .1U_0402_16V7K

1

@EMC@

1

2

VALW

+3

C2

53 1U_0402_6.3V6K

52 1U_0402_6.3V6K

1

2

1

2

C947 .1U_0402_16V7K

1

@EMC@

+RTC_APU_R

+1.5VS

+1.8VALW

+3VALW

+0.95VALW

+RTC_APU_R

+1

.5V

3A

AA3

AA3 AC AC

AE3 AE3 AG32

AG AJ AL

AL AR

AL10

AL11

AL13 AM13

AE11 AE13 AJ11

AJ13

J3

5 L32 L37

5

N3 R3

1

R3

7

2

U3 U3

5

W3

1

W32 W3

7

1

5

32 37

1

5

37 35 32

37 35

B1 B2

AR5

AU4

AV7

AW5

AN4

@

UA

PU1F

DIO_MEM_S_1

VD

DIO_MEM_S_2

VD VD

DIO_MEM_S_3

DIO_MEM_S_4

VD VDDIO_MEM_S_5

DIO_MEM_S_6

VD

DIO_MEM_S_7

VD VD

DIO_MEM_S_8 DIO_MEM_S_9

VD

DIO_MEM_S_10

VD VD

DIO_MEM_S_11

VD

DIO_MEM_S_12

VDDIO_MEM_S_13

DIO_MEM_S_14

VD

DIO_MEM_S_15

VD

DIO_MEM_S_16

VD

DIO_MEM_S_17 DIO_MEM_S_18

VD

DIO_MEM_S_19

VD

DIO_MEM_S_20 DIO_MEM_S_21

VD

VDDIO_MEM_S_22

DIO_MEM_S_23

VD

VDDIO_AZ_ALW_1

VDDIO_AZ_ALW_2

VDD_18_ALW_1 VDD_18_ALW_2

VDD_33_ALW_1 VDD_33_ALW_2

VDD_095_USB3_DUAL_1

VDD_095_USB3_DUAL_2 VDD_095_USB3_DUAL_3 VDD_095_USB3_DUAL_4

VDD_095_ALW_1 VDD_095_ALW_2 VDD_095_ALW_3

VDD_095_ALW_4

VDDBT_RTC_G

FT3_BGA_769P-T

Part Number =

WER

PO

DCR_CPU_1

VD

DCR_CPU_2

VD

DCR_CPU_3 DCR_CPU_4

VD VDDCR_CPU_5

DCR_CPU_6

VD

DCR_CPU_7

VD VD

DCR_CPU_8

DCR_CPU_9

VD

DCR_CPU_10

VD VD

DCR_CPU_11

VD

DCR_CPU_12

VDDCR_CPU_13

DCR_CPU_14

VD

DCR_CPU_15

VD VD

DCR_CPU_16

VD

DCR_CPU_17

DCR_CPU_18

VD VD

DCR_CPU_19

VD

DCR_CPU_20

DCR_CPU_21

VD VDDCR_CPU_22

DCR_CPU_23

VD

DCR_CPU_24

VD

DCR_CPU_25 DCR_CPU_26

VD

DCR_NB_1

VD VD

DCR_NB_2

VD

DCR_NB_3

VDDCR_NB_4

DCR_NB_5

VD

DCR_NB_6

VD

DCR_NB_7

VD

DCR_NB_8 DCR_NB_9

VD

DCR_NB_10 DCR_NB_11

VD VD

DCR_NB_12

DCR_NB_13

VD VD

DCR_NB_14

VD

DCR_NB_15

DCR_NB_16

VD VD

DCR_NB_17

VD

DCR_NB_18

VDDCR_NB_19 VDDCR_NB_20 VDDCR_NB_21

VDD_18_1 VDD_18_2 VDD_18_3

VDD_18_4

VDD_33_1 VDD_33_2

VDD_095_1 VDD_095_2 VDD_095_3

VDD_095_4 VDD_095_5 VDD_095_6

VDD_095_7 VDD_095_8 VDD_095_9

VDD_095_GFX_1 VDD_095_GFX_2 VDD_095_GFX_3

L21 L23

L25 L27 L29

N2 N2 N2

R2 R23 R2

U2 U2 U2

W2 W2 W2

AA21 AA2 AA2

AC AC AC

AE2 AE2 AE2

L13 L17 N1

N1 N1 R1

R1 R17 U1

U1 W1 W1

AA1 AA1 AC

AC17 AE15 AE1

AE19 AG17 AG21

A2 A3 B3

C3

AM15 AM17

AG23 AG27 AJ21

AJ27 AL21 AL23

AL27 AM23 AM25

U10 W10 AA10

AA1

AA15 AA1 AA2

AA2 AA3

AC AC15

AC AC AC

AE25

AE2 AE3 AE3

AG

AG AG13 AG

AG AG AG

AJ15 AJ17

AJ19 AJ23 AJ25

AJ29 AJ31 AJ32

AJ39

AL15 AL17 AL19

AL25 AL29

W2

9

W3

9 1

W4

Y1 Y2

AA3

AA7 AA8

1

9 5

9 9 3

AC

7

AC

11

19 25 29

31 39 41

AE3 AE7

9 2 9

AG

3 5

AG

10

11

15

19 25 29

31 39 41

AH1 AH2

3

AJ

AJ7

AL3 AL8

@

UA

PU1H

125

VSS_

126

VSS_ VSS_

127

128

VSS_ VSS_129

130

VSS_

131

VSS_ VSS_

132 133

VSS_

134

VSS_ VSS_

135

VSS_

136

VSS_137

138

VSS_

139

VSS_

140

VSS_

141 142

VSS_

143

VSS_

144 145

VSS_

VSS_146

147

VSS_ VSS_

148

VSS_

149 150

VSS_

151

VSS_

152 153

VSS_ VSS_154

155

VSS_

156

VSS_ VSS_

157

158

VSS_

159

VSS_ VSS_

160

VSS_

161 162

VSS_ VSS_

163

164

VSS_ VSS_

165

VSS_

166

167

VSS_ VSS_

168

VSS_

169

VSS_170 VSS_171 VSS_172

VSS_173 VSS_174 VSS_175

VSS_176 VSS_177 VSS_178

VSS_179 VSS_180 VSS_181

VSS_182 VSS_183 VSS_184

VSS_185 VSS_186

FT3_BGA_769P-T

Part Number =

D

GN

VSSBG_DAC

VSS_ VSS_

VSS_ VSS_ VSS_191

VSS_ VSS_ VSS_

VSS_ VSS_199 VSS_

VSS_ VSS_ VSS_

VSS_ VSS_208 VSS_

VSS_ VSS_ VSS_

VSS_216 VSS_ VSS_

VSS_ VSS_ VSS_

VSS_ VSS_232 VSS_233

VSS_234 VSS_235 VSS_236

VSS_237 VSS_238 VSS_239

VSS_240 VSS_241 VSS_242

VBURN

PSEN

AL

39

187

AL

41

188

11

AM

189

27

AM

190

AM

31

AN

3

192

7

AN

193

AN

39

194

AP3

1

195

AR3

196

AR

13

197

17

AR

198

AR

21

AR

25

200

29

AR

201

39

AR

202

AR

41

203

AU1

204

AU

2

205

3

AU

206

15

AU

207

AU

19 23

AU

209

27

AU

210

AU

39

211

AV9

212

AW3

213

7

AW

214

13

AW

215

AW

15

AW

17

217

19

AW

218

AW

21

219

AW

23

220

AW25

221

AW

27

222

31

AW

223

AW

33

224

AW

35

225

37

AW

226

39

AW

227

AW

41

228

AY13

229

AY15

230

8

AY1

231

AY30 BA2

BA7 BA13 BA15

BA18 BA21 BA25

BA31 BA35 BA39

A15 AL31 AM29

@

UA

PU1G

D

GN

R1

RS@

A8

1

VSS_

A1

3

2

VSS_

3

A2

VSS_

3

1

A3

4

VSS_

2

A3

5

VSS_5

A3

9

19

1

B8

B1

3

B2

3

B31 B3

9

C1

C2 C5 C7

C9

C1

1

C13

C1

5 7

C1

9

C1

C2

1 3

C2

5

C2

7

C2

9

C31

3

C3

5

C3 C3

7

C3

9 1

C4

D9

D1

1

D13

E3

E4 E9

E1

1

3

E1

7

E2 E3

1

E35 E38

9

E3

G3 G7

G11

G13 G15 G17

G21 G25 G29

G35 G37 G39

G41 H11 H13

H23 H31

6

VSS_

7

VSS_ VSS_

8 9

VSS_

10

VSS_ VSS_

11

VSS_

12

VSS_13

14

VSS_

15

VSS_

16

VSS_

17 18

VSS_

19

VSS_

20 21

VSS_

VSS_22

23

VSS_ VSS_

24

VSS_

25 26

VSS_

27

VSS_

28 29

VSS_ VSS_30

31

VSS_

32

VSS_ VSS_

33

34

VSS_

35

VSS_ VSS_

36

VSS_

37 38

VSS_ VSS_

39

40

VSS_ VSS_

41

VSS_

42

43

VSS_ VSS_

44

VSS_

45

VSS_46 VSS_47 VSS_48

VSS_49 VSS_50 VSS_51

VSS_52 VSS_53 VSS_54

VSS_55 VSS_56 VSS_57

VSS_58 VSS_59 VSS_60

VSS_61 VSS_62

FT3_BGA_769P-T

Part Number =

PU_CORE

+A

1 3

0_0402_5%

7

1

7

1 3 7

3 7

21 23 27

1 3 7

+A

PU_CORE_NB

1

3 7 1

3

7

3 7

13

7

+1.8VS

+3VS

+0.95VS

VSS_ VSS_

VSS_ VSS_ VSS_67

VSS_ VSS_ VSS_

VSS_ VSS_75 VSS_

VSS_ VSS_ VSS_

VSS_ VSS_84 VSS_

VSS_ VSS_ VSS_

VSS_92 VSS_ VSS_

VSS_ VSS_ VSS_

VSS_ VSS_

VSS_

VSS_ VSS_ VSS_

VSS_ VSS_108 VSS_109

VSS_110 VSS_111 VSS_112

VSS_113 VSS_114 VSS_115

VSS_116 VSS_117 VSS_118

VSS_119 VSS_120 VSS_121

VSS_122 VSS_123 VSS_124

J3

63

J7

64

J8

65

9

J3

66

K1

1

K1

3

68

7

K1

69

K1

9

70

K2

1

71

K23

72

K2

5

73

7

K2

74

K2

9

K3

1

76

L3

77

L7

78

L8

79

L10

80

L11

81

L15

82

L19

83

L31 L39

85

L41

86

M1

87

M2

88

N3

89

N7

90

5

N1

91

N1

9

N2

5

93

9

N2

94

N3

1

95

N3

9

96

P1

97

P2

98

R3

99

R7

100

R1

5

101

9

R1

102

5

R2

103

R2

9

104

R39

105

R41

106

U1

107

U2 U3

U7 U8 U11

U15 U19 U25

U29 U31 U39

W3 W5 W11

W15 W19 W25

VS

+3

C2

C201 1U_0402_6.3V6K

C1

02 1U_0402_6.3V6K

92 1U_0402_6.3V6K

93 1U_0402_6.3V6K

91 1U_0402_6.3V6K

1

2

1

2

C1

95 1U_0402_6.3V6K

94 1U_0402_6.3V6K

97 180P_0402_50V8J

1

2

PLANE SPLIT

C2

C9 27 1U_0402_6.3V6K

C9

C928 .1U_0402_16V7K

C9

31 1U_0402_6.3V6K

29 .1U_0402_16V7K

1

2

@

C2

30 .1U_0402_16V7K

32 1U_0402_6.3V6K

10 180P_0402_50V8J

11 180P_0402_50V8J

1

2

C2

08 180P_0402_50V8J

07 180P_0402_50V8J

1

2

@

C2

C230 180P_0402_50V8J

31 180P_0402_50V8J

59 180P_0402_50V8J

58 180P_0402_50V8J

1

2

C2

49 1U_0402_6.3V6K

57 180P_0402_50V8J

1

2

VDDIO_AZ_ALW (Could be S0 or S5 power rail)

.5VS

+1

C2

C161 4.7U_0603_6.3V6K

32 1U_0402_6.3V6K

1

2

@

+1.8VALW/+1.8VS OF APU

+1.8VALW

C1 60 4.7U_0603_6.3V6K

1

2

VDD_18_ALW

VDD_18

C2

37 1U_0402_6.3V6K

36 1U_0402_6.3V6K

1

2

C2

33 180P_0402_50V8J

40 1U_0402_6.3V6K

39 1U_0402_6.3V6K

38 1U_0402_6.3V6K

1

2

C2

50 1U_0402_6.3V6K

48 1U_0402_6.3V6K

44 1U_0402_6.3V6K

46 1U_0402_6.3V6K

1

2

+1

.8VS

C213 180P_0402_50V8J

1

2

+0.95VALW

C2

21 1U_0402_6.3V6K

18 180P_0402_50V8J

1

2

@

C2

20 1U_0402_6.3V6K

19 1U_0402_6.3V6K

1

2

@

C9 33 10U_0603_6.3V6M

1

2

C2

22 1U_0402_6.3V6K

17 1U_0402_6.3V6K

1

2

VDD_095_ALW

VDDBT_RTC_G

4 4

A

RTC OF APU

B

+RTC_APU_R

C166

0.22U_0402_10V6K

W=20mils

1

2

1

R93 10K_0402_5%

1

CLRP1 SHORT PADS

2

SP@

CLRP2 SHORT PADS

A4W1E

2

SP@

Need OPEN

for Clear CMOS

+RTC_APU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONI CS, INC.

C

2014/03/27 2016/03/27

Compal Secr et Data

Deciphered Date

D

mpal Electronics, Inc.

Co

Title

Size Document N umber Rev

C

Date: Sheet

Co

FT3

B5

PWR/GND

W1E_LA-D121P

E

of

933Thursday, April 16, 2015

of

933Thursday, April 16, 2015

of

933Thursday, April 16, 2015

1.0

C

DDRA

B_SDQ[0..63] <5,11>

DDRA

B_SDM[0..7] <5,11>

B_SMA[0..15] <5,11>

DDRA

C117 .1U_0402_16V7K

C118 .1U_0402_16V7K

C116 .1U_0402_16V7K

1

2

@

C121 .1U_0402_16V7K

C119 .1U_0402_16V7K

C122 .1U_0402_16V7K

C120 .1U_0402_16V7K

1

2

@

VREF for DIMM1,2

+V

REF_DQ

+V

REF_CA

MEM_MAB_RST#

C123 .1U_0402_16V7K

1

2

@

1K_0804_8P4R_1%

1

C1274 100P_0402_50V8J

1

2 3

4

RP

2

@EMC@

+0

.75VS

C128 .1U_0402_16V7K

C126 .1U_0402_16V7K

C129 .1U_0402_16V7K

@EMC@

1

2

+1

.5V

9

8

7

6 5

C127 4.7U_0603_6.3V6K

@EMC@

1

2

.5V

+1

DDRA

DDRAB_SDQ7

DDRA

ME

DDRA

DDRAB_SDQ15

DDRAB_SDQ20

DDRAB_SDQ21

DDRA

DDRAB_SDQ29

DDRA

15mi

B

B_SDQ4

B_SDQ5

B_SDQS0#

B_SDQS0

B_SDQ6

B_SDQ12

B_SDQ13

B_SDM1

M_MAB_RST#

B_SDQ14

B_SDM2

B_SDQ22

B_SDQ23

B_SDQ28

B_SDQS3#

B_SDQS3

B_SDQ30

B_SDQ31

DDRA

_CKE1

B_SMA15

DDRA

B_SMA14

DDRA

B_SMA11

DDRA

DDRAB_SMA7

B_SMA6

DDRA

B_SMA4

B_SMA2

DDRA

B_SMA0

DDRA_CLK1

_CLK1#

DDRA

B_SBS1#

DDRA

B_SRAS#

DDRA

_SCS0#

DDRA

_ODT0

DDRA_ODT1

l

B_SDQ36

DDRA

B_SDQ37

DDRAB_SDM4

B_SDQ38

DDRA

B_SDQ39

B_SDQ44

DDRA

B_SDQ45

B_SDQS5#

DDRA

B_SDQS5

DDRA

B_SDQ46

DDRAB_SDQ47

DDRAB_SDQ52

DDRAB_SDQ53

DDRAB_SDM6

DDRAB_SDQ54

DDRAB_SDQ55

DDRAB_SDQ60

DDRAB_SDQ61

DDRAB_SDQS7#

DDRAB_SDQS7

DDRAB_SDQ62

DDRAB_SDQ63

MEM_MAB_EVENT#

+0.75VS

DDRA

B_SDQS0# <5,11> B_SDQS0 <5,11>

DDRA

ME

M_MAB_RST# <5,11>

DDRA

B_SDQS3# <5,11>

DDRAB_SDQS3 <5,11>

_CKE1 <5>

DDRA

_CLK1 <5>

DDRA

_CLK1# <5>

B_SBS1# <5,11>

DDRA

B_SRAS# <5,11>

DDRA

_SCS0# <5>

DDRA

_ODT0 <5>

DDRA

_ODT1 <5>

1

34 C1

2

.1U_0402_16V7K

1000P_0402_50V7K

B_SDQS5# <5,11>

DDRA DDRA

B_SDQS5 <5,11>

DDRAB_SDQS7# <5,11>

DDRAB_SDQS7 <5,11>

MEM_MAB_EVENT# <5,11>

APU_SDATA0 <7,11,17> APU_SCLK0 <7,11,17>

B_SDQ[0..63]

DDRA

B_SDM[0..7]

DDRA

B_SMA[0..15]

+1.5V/+0.75VS OF DIMM1

+1

.5V

C115 .1U_0402_16V7K

C114 .1U_0402_16V7K

1

2

@

REF_CA

+V

2

C167

1

A

B_SDQ0

B_SDQ1

B_SDM0

B_SDQ2

B_SDQ8

B_SDQ9

B_SDQS1#

B_SDQS1

B_SDQ10

B_SDQS2#

B_SDQS2

B_SDQ18

B_SDQ19

B_SDQ25

B_SDM3

B_SDQ26

B_SDQ27

_CKE0

B_SBS2#

B_SMA12

B_SMA8

B_SMA5

B_SMA3

B_SMA1

_CLK0#

B_SMA10

B_SBS0#

B_SWE#

B_SCAS#

_SCS1#

B_SDQ32

B_SDQ33

B_SDQS4

B_SDQ34

B_SDQ35

B_SDQ40

B_SDQ41

B_SDM5

B_SDQ42

@EMC@

+1

.5V

15mil

JD

IMM1

1

VR

EF_DQ

3

VSS2

5

DQ0

7

DQ

1

9

VSS4

11

DM

0

13

VSS5

15

2

DQ

17

DQ

3

19

VSS7

21

8

DQ

23

9

DQ

25

VSS9

27

DQ

S#1

29

S1

DQ

31

1

VSS1

33

DQ

10

35

DQ

11

37

3

VSS1

39

DQ

16

41

DQ

17

43

5

VSS1

45

DQS#2

47

S2

DQ

49

VSS1

8

51

DQ

18

53

19

DQ

55

0

VSS2

57

DQ

24

59

25

DQ

61

VSS22

63

DM

3

65

3

VSS2

67

DQ

26

69

27

DQ

71

5

VSS2

73

CK

E0

75

D1

VD

77

NC1

79

BA2

81

D3

VD

83

A1

2/BC#

85

A9

87

D5

VD

89

A8

91

A5

93

VD

D7

95

A3

97

A1

99

D9

VD

101

CK

0

103

0#

CK

105

D11

VD

107

A1

0/AP

109

BA0

111

VD

D13

113

#

WE

115

S#

CA

117

VD

D15

119

A1

3

121

#

S1

123

VD

D17

125

EST

NCT

127

VSS2

7

129

DQ

32

131

33

DQ

133

VSS2

9

135

DQ

S#4

137

S4

DQ

139

2

VSS3

141

DQ

34

143

DQ35

145

VSS3

4

147

40

DQ

149

41

DQ

151

VSS3

6

153

5

DM

155

7

VSS3

157

DQ

42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0101

CONN@

SP07000PT00

RE

VR

EVENT#

VSS1

VSS3

DQ

VSS6

VSS8

DQ

VSS1

SET#

VSS1

DQ

VSS1

DQ

VSS1

DQ

VSS1

DQ

VSS2

DQS#3

DQ

VSS2

DQ

VSS2

CK

VD

CK

VD

RA

VD

OD

VD

OD

VD

EF_CA

VSS2

DQ

VSS3

DQ

VSS33

DQ

VSS3

DQ

VSS3

DQ

DQ47

VSS40

DQ52

DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

VTT2

2

4

DQ

6

DQ5

8

10

S#0

12

S0

14

16

6

DQ

18

DQ

7

20

22

12

24

13

26

0

28

DM

1

30 32

2

34

14

36

15

38

4

40

20

42

21

44

6

46

DM2

48

7

50

22

52

23

54

9

56

28

58

29

60

1

62

64

S3

66

4

68

30

70

31

72

6

74

E1

76

D2

78

A1

5

80

A1

4

82

D4

84

A1

1

86

A7

88

D6

90

A6

92

A4

94

D8

96

A2

98

A0

100

D10

102

CK

1

104

1#

106

D12

108

BA1

110

S#

112

D14

114

#

S0

116

T0

118

D16

120

T1

122

NC2

124

D18

126 128

8

130

36

132

37

134

0

136

DM

4

138

1

140

38

142

39

144 146

44

148

45

150

5

152

S#5

154

S5

156

8

158

46

160

162 164

166

168 170

DM6

172

174 176

178

180 182

184

186 188 190

192 194

196

198 200

SDA

202

SCL

204

206

G2

REF_DQ

+V

1

2

@EMC@

42 C1

DDRA

DDRAB_SDQ3

DDRA

DDRAB_SDQ11

DDRAB_SDQ16

DDRAB_SDQ17

DDRA

DDRAB_SDQ24

DDRA

DDRAB_SMA9

DDRA

DDRA_CLK0 DDRA

DDRA

DDRAB_SMA13

DDRA

DDRAB_SDQS4#

DDRA

DDRAB_SDQ43

DDRAB_SDQ48

DDRAB_SDQ49

DDRAB_SDQS6#

DDRAB_SDQS6

DDRAB_SDQ50

DDRAB_SDQ51

DDRAB_SDQ56

DDRAB_SDQ57

DDRAB_SDM7

DDRAB_SDQ58

DDRAB_SDQ59

<Address: 00>

2

C945 .1U_0402_16V7K

1

2

76 C1

1

.1U_0402_16V7K

1000P_0402_50V7K

1 1

2 2

3 3

+3VS

1

C136 .1U_0402_16V7K

2

DDRA DDRA

DDRA DDRAB_SDQS2<5,11>

DDRA

DDRAB_SDQS6#<5,11> DDRAB_SDQS6<5,11>

DDRA

DDRA DDRA

DDRA

B_SDQS1#<5,11> B_SDQS1<5,11>

B_SDQS2#<5,11>

_CKE0<5>

B_SBS2#<5,11>

_CLK0<5> _CLK0#<5>

B_SBS0#<5,11>

B_SWE#<5,11>

B_SCAS#<5,11>

DDRA

B_SDQS4#<5,11>

B_SDQS4<5,11>

2

C944 .1U_0402_16V7K

1

_SCS1#<5>

D

E

DI

MM_A H:4mm RVS

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONI CS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONI CS, INC.

C

2014/03/27 2016/03/27

Compal Secr et Data

Deciphered Date

D

mpal Electronics, Inc.

Co

Title

Size Document N umber Rev

C

Date: Sheet

Co

DDR3

W1E_LA-D121P

B5

SODIMM-I Socket

10 33Thursday, April 16, 2015

E

10 33Thursday, April 16, 2015

of

1.0

Acer ASPIRE ES1-520ES1 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual