Acer Aspire_E5_575 Schematic

Dr-Bios.com

ZAA Serials SKL ULT SYSTEM BLOCK DIAGRAM

IV@ : iGPU EV@ : Optimus KBL15@ :For Key/B 15" KBL17@ : For Key/B 17" KBL@ : Key/B backlight TPM@ : TPM GS@ :G-SENSOR TDI@ : Touch PAD I2C TSU@ : Toutch Screen (USB) TSI@ : Toutch Screen (I2C) GT3@ : GT3 CPU NAC@ : Non IOAC IOAC@ : For IOAC

P23

SP@ : Special part GC6@ : for GC6 FPD@ : for 8 Pin Finger/P. GKA@ : For kill GPU A-chanle. GKB@ : For kill GPU B-chanle. ROM@ : For SKL or KBL TYC@ : For Type-C

P21

X'TAL 27MHz

TPS25810

PTN36242

PCIE-6

PCIE-5

VRAM

GDDR5/ 1.35V

eDP Conn.

RTD2166

P22

P21

HDMI Conn.

USB3 Port MB side USB3 port 2 USB3 port 1

LAN_CRD_COMBO RTL8411

P19~20

P23

P24

MINI CARD WLAN+BT

10/100/1G

VGA Conn.

Type-C connector

P30

P28

P25

X'TAL 25MHz

D D

SKY LAKE ULT 15W

MCP 1356pins

DDR4-SODIMM CHA

DDR4-SODIMM CHB

SATA - HDD Mai n & 2'nd

SATA ODD

C C

POA Finger/ print

CCD(Camera)

Touch Screen

Blue Tooth

I/O board

I/O Board Conn.USB2 IO*2

B B

Small/B Audio jack

P27

P23

P30

P28

D-MIC

P26

P12

P13

P27

Dual Channel DDR4

SATA0

SATA1

USB2-9

USB2-7

USB2-6

USB2-5

USB2-4

USB2-3

BATTERY

Azalia

IMC

DC+GT3e

42 mm X 24 mm

SATA

Integrated PCH

USB2.0

DMIC_CLK0 DMIC_DATA0

RTC

IHDA

LPC

P2~P10

PCI-E x4 TX/RX

USB3.0/2.0

PCI-E x1

PCI-E x2

CLK

eDP

DP-2

DP-1

CLK

I2C_0

SPI

PCIE1-4

EDP

DDI2

DDI1

USB3-1 & USB3-2

USB2-1 & USB2-2

X'TAL

32.768KHz

X'TAL 24MHz

SPI ROM 8M+4M

GPU

N16S-GTR

N16S-GT1

P14~P18

+5V_S5

PTN3366BS

M.2 SSD

P24

P28

BOM

Cardreader CONN. 2in 1

P25

RJ45

P25

K/B BL Con.

IT8987

P29

HALL SENSOR

P23

Touch PAD

P29

remove TPM from SKL , KBL keeps it.---- for B2 add POA FUNCTION, , add 0hm*4 between EC to POA conn & server VST * 7 pcs POA ( change FP power from 3v to 5v )

P31

Fan Driver

(Fan signal)

TPM(option)

P29

P27

BQ24780S

Batery C harger

TPS51225R

+3V/+5V

RT8237CZQW

+1V_S5

NB681GD-Z

+VCCOPC/+VCCEOPIO

G5316RZ1D

+1.2VSUS

P33

ISL95859HRT Z-T

+VCORE/VCCSA/VCCGT

P34

P35

ISL95808

VCCSA

P36

Thermal Protection

P37

Discharger

UP1658RQKF

+VGPU_CORE

P38-39

RT8068AZQW

+1.05V_GFX/+3V_GFX +1.5V_GFX

P39

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Block Diagram

P41

P42

P43

ZAA

148Friday, February 05, 2016

Int. D -MIC

A A

CH6221M9A00 CAP CHIP 22U 6.3V(+-20%,X5R,0805)H1.25 CH6221M9A01 CAP CHIP 22U 6.3V(+-20%,X5R,0805)H1.25 CH6221M9A02 CAP CHIP 22U 6.3V(+-20%,X5R,0805)H1.25

ALC25 5

AUDIO CODEC

Speaker*2

P26

LED

P29

K/B Con.

P29

Dr-Bios.com

AJ0QKKQVT00 -->CPU(1356P)KBL 1.7G QKKQ(FCBGA) -----no use AJ0QKKSUT00 -->CPU(1356P)KBL 2.4G QKKS(FCBGA) AJ0QKJWQT02 -->CPU(1356P)KBL-U 2.6G QKJW(BGA) QCI PN ---- C-test

i3-6100U AJSR2EUUT07 i5-6200U AJSR2EYUT07 i7-6500U AJSR2EZRT07 i5-6267U AJSR2JK8T02--no use

D D

HDMI

To RTS2166 iC

+VCCIO

C C

+1V_VCCST

CPU_THRMTRIP#

R5291K_4

CATERR#

R78849.9/F_4

+VCCIO

R465 1K_4

B B

H_PROCHOT#

H_PROCHOT#<31,32,37>

Avoid 125Mhz

BPM#[0:7] Trace Length 1~6 inches Length match < 300 mils

H_PECI (50ohm) Route on microstrip only Spacing >18 mils Trace Length: 0.4~6.125 iches

INT_ HDMIT X2N<24> INT_ HDMIT X2P<24> INT_ HDMIT X1N<24> INT_ HDMIT X1P<24> INT_ HDMIT X0N<24> INT_ HDMIT X0P<24>

INT_ HDMIC LK-<24> INT_ HDMIC LK+<24>

DDI2_TXN0<22> DDI2_TXP0<22> DDI2_TXN1<22> DDI2_TXP1<22>

HDMI_DDCCLK_SW<24>

HDMI_DDCDATA_SW<24>

PCH_ODD_EN<27>

eDP_RCOMP Trace length < 100 mils Trace width = 20 mils Trace spacing = 25 mils

H_PECI<31>

SM_RCOMP[0:2] Trace length < 500 mils Trace width = 12~15 mils Trace spacing = 20 mils

H_PECI

THRMTRIP#

DGPU_PW_CTRL#<4>

TP4395 TP4394 TP4392 TP4393

CRT_CLK CRT_DATA

TP4390

EDP_RCOMP

R15424.9/F_4

R531 499/F_4 R530 100/F_4

Skylake ULT (DISPLAY,eDP)

AT16 AU16

D63 A54 C65 C63 A65

C55 D55 B54 C56

A7 BA5 AY5

H66 H65

SKL_ULT

DDI

DISPLAY SIDEBANDS

+3V_S5 +3V_S5

U35D

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

CPU MISC

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

SP@SKL_ULT/BGA

<PART_SYM_NUM>

SKL_ULT

+3V_S5 +3V_S5 +3V_S5 +3V_S5

TP65

TP89 TP90 TP64 TP62

R635 49.9/F_4 R646 49.9/F_4 R158 49.9/F_4 R162 49.9/F_4

U35A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SP@SKL_ULT/BGA

CATERR#

H_PROCHOT#_RH_PROCHOT# CPU_THRMTRIP#

XDP_BP M#0 XDP_BP M#1 XDP_BP M#2 XDP_BP M#3

EDP

+3V_S5

GPP_E13/DDPB_HPD0

+3V_S5

GPP_E14/DDPC_HPD1

+3V_S5

GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

+3V_S5 +3V_S5

<PART_SYM_NUM>

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48

DDI2_AUXN

F48

DDI2_AUXP

G46 F46

L9 L7

PCH_DP_HPD

L6 N9

R571 *short_4

L10

EDP_HPD

R12 R11

PCH_BRIGHT

U13

B61

XDP_TC K0

D60

XDP_TD I_CPU

A61

XDP_TD O_CPU

C60

XDP_TM S_CPU

B59

PCH_TRST#

B56

XDP_TC K1

D59

XDP_TD I

A56

XDP_TD O

C59

XDP_TM S

C61

PCH_TRST#

A59

XDP_TC K0

R546 *0_4 R553 *0_4

PCH_TypeC_UPFb#

EDP_TXN0 <23> EDP_TXP0 <23> EDP_TXN1 <23> EDP_TXP1 <23> EDP_TXN2 <23> EDP_TXP2 <23> EDP_TXN3 <23> EDP_TXP3 <23>

EDP_AUXN <23> EDP_AUXP <23>

PCH_BRIGHTDP_UTIL

DDI2_AUXN <22> DDI2_AUXP <22>

SIO_EXT_SCI#

PCH_BLON < 23> PCH_BRIGHT <23>

EDP_VDD_EN <23>

R796 *short_4 R795 *short_4 R797 *short_4

If use Intel D CI USB 3.0 fix ture ne ed to short

1. XDP_TDO <--> XDP_TDO_CPU

2. XDP_TDI <--> XDP_TDI_CPU

3. XDP_TMS <--> XDP_TMS_CPU

eDP Panel

For 4K

INT_ HDMI_ HPD <24 > PCH_DP_HPD <22> PCH_TypeC_UPFb# <21> SIO_EXT_SCI# <31> EDP_HPD <23>

PCH JTAG

JTAG_TCK,JTAG_TMS Trace Length < 9000mils

XDP_TD I_CPU

XDP_TD O_CPU

XDP_TM S_CPU

DDI2_AUXN

DDI2_AUXP

R533 *100K_4

R532 *100K_4

Change for leakage

CRT_CLK CRT_DATA

SIO_EXT_SCI#

PCH_TypeC_UPFb#

PCH_DP_HPD EDP_HPD

R577 *2.2K_4 R152 2.2K_4

R781 20K/F_4

R11251 20K/F_4

For Type-C change

R564 100K_4 R563 100K_4

100k pull-down on PCH side

Change to +1V_VCCST 11/6

XDP_TD O

XDP_TM S XDP_TD I

XDP_TC K0

XDP_TC K0 XDP_TC K1

PCH_TRST#

2/16 ,XDP_TCK1,XDP_ TMS don't need pull up or pull down

R559 51_4 R514 51_4 R515 51_4

R513 *1K_4

R558 51_4 R537 *51_4 R534 51_4

+3V

+3V_S5

+3V

+3V_S5

MP remove(Intel)

+1V_VCCST

5/29 XDP_TCK0 R558 Stuff

+1V_VCCST

R488

*1K_4

1 3

Q5 MMBT3904-7-F

Q31

FDV301N

R74 1K_4

SYS_SHDN# <31,33,40>

+VCCIO <5,8,32,34,37,40> +1V_VCCST <5,8,9,37>

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

PROJECT :

Skylake 1/4 (DDI/eDP)

ZAA

248

CPU thermal trip

+1V_VCCST

U33

A A

IMVP_ PWRG D<37>

*74AUP1G07GW

NC1VCC

GND3Y

R478 *0_4

C628

*0.1u/16V_4

+3V

R485 10K_4

IMVP_ PWRG D_3V

IMVP_ PWRG D_3V <8>

IMVP_ PWRG D_3V

THRMTRIP#

Dr-Bios.com

Change Data and DQS to interleave.

SKL ULT (DDR3L)SKL ULT (DDR3L)

U35C

DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

SP@SKL_ULT/BGA

*0.1u/16V_4

M_B_A[13:0]

C750

SKL_ULT

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

<PART_SYM_NUM>

DDR3_DRAMRST# <12,1 3>

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

M_B_A[13:0] <13>

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7

M_B_A12 M_B_A11

M_B_A13

M_B_A2

M_B_A10 M_B_A1 M_B_A0 M_B_A3 M_B_A4

M_B_ALERT#

CPU_DRAMRST#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

M_B_CLK0# <13> M_B_CLK1# <13>

M_B_CLK0 <13> M_B_CLK1 <13>

M_B_CKE0 <13> M_B_CKE1 <13>

M_B_CS#0 <13> M_B_CS#1 <13> M_B_ODT0_DIMM <13> M_B_ODT1_DIMM <13>

M_B_BG#0 <13>

M_B_ACT# <13> M_B_BG#1 <13>

M_B_CAS# <13> M_B_WE# <13> M_B_RAS# <13> M_B_BA#0 <13>

M_B_BA#1 <13>

M_B_DQS#0 <13> M_B_DQS0 <13> M_B_DQS#1 <13> M_B_DQS1 <13> M_B_DQS#2 <13> M_B_DQS2 <13> M_B_DQS#3 <13> M_B_DQS3 <13> M_B_DQS#4 <13> M_B_DQS4 <13> M_B_DQS#5 <13> M_B_DQS5 <13> M_B_DQS#6 <13> M_B_DQS6 <13> M_B_DQS#7 <13> M_B_DQS7 <13>

M_B_ALERT# <13> M_B_PARITY <13>

!"#$%&'$(

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

PROJECT :

Skylake 2/3 (DDR3 I/F)

R685120/F_4

R67880.6/F_4

R681100/F_4

ZAA

348

M_A_A[13:0]

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

<PART_SYM_NUM>

M_A_A[13:0] <12>

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51

M_A_A5

BB54

M_A_A9

BA52

M_A_A6

AY52

M_A_A8

AW52

M_A_A7

AY55 AW54

M_A_A12

BA54

M_A_A11

BA55 AY54

AU46

M_A_A13

AU48 AT46 AU50 AU52 AY51

M_A_A2

AT48 AT50

M_A_A10

BB50

M_A_A1

AY50

M_A_A0

BA50

M_A_A3

BB52

M_A_A4

AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50

M_A_ALERT#

AT52

AY67 AY68 BA67

AW67

DDR_VTT_CTRL

R621 *10K_4

+VREF_CA_CPU

+VREFDQ_SB_M3

M_A_CLK0# <12>

M_A_CLK0 <12>

M_A_CLK1# <12>

M_A_CLK1 <12>

M_A_CKE0 <12> M_A_CKE1 <12>

M_A_CS#0 <12> M_A_CS#1 <12> M_A_ODT0_DIMM <12> M_A_ODT1_DIMM <12>

M_A_BG#0 <12>

M_A_ACT# <12> M_A_BG#1 <12>

M_A_CAS# <12> M_A_WE# <12> M_A_RAS# <12> M_A_BA#0 <12>

M_A_BA#1 <12>

M_A_DQS#0 <12> M_A_DQS0 <12> M_A_DQS#1 <12> M_A_DQS1 <12> M_A_DQS#2 <12> M_A_DQS2 <12> M_A_DQS#3 <12> M_A_DQS3 <12> M_A_DQS#4 <12> M_A_DQS4 <12> M_A_DQS#5 <12> M_A_DQS5 <12> M_A_DQS#6 <12> M_A_DQS6 <12> M_A_DQS#7 <12> M_A_DQS7 <12>

M_A_ALERT# <12> M_A_PARITY <12>

+VREFDQ_SA_M3

+1.2VSUS

1 3

Q35 *DTC144EU

TP4344

+3V_S5

M_B_DQ[63:0]<13>

For GDDR5 remove

R682 *100K_4

DDR_VTTT_PG_CTRL <36>

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8

M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

M_A_DQ[63:0]<12>

D D

C C

B B

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8

M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

U35B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SP@SKL_ULT/BGA

For Sx ,stuff Q? in DDR_VTT_CNTL

+3V_S5 <2,4,6,7,8,9,11,21,25,27,28,29,31,33,35,36,41> +1.2VSUS <5,12,13,36>

DRAMRST

+1.2VSUS

A A

CPU DRAM

CPU_DRAMRST#

R679 470_4

R670 *short_4

Dr-Bios.com

SKL ULT (SIDEBAND ) GPIO

H_PECI (50ohm) Route on microstrip only Spacing >18 mils Trace Length: 0.4~6.125 iches

H_PWRGOOD (50ohm)

D D

+3V_S5

PU 2.2K for touch pad I2C bus(400 KHz)

I2C0_SDA

R1672.2K_4

I2C0_SCL

R1662.2K_4

I2C1_SDA

R165*2.2K_4

I2C1_SCL

R169*2.2K_4

Trace Length: 1~11.25 inches

Touch PAD

Touch Screen

UART2 for RMT

+3V

C C

DGPU_PW_CTRL#

DGPU_PW_CTRL#<2>

R127 EV@100K_4

UMA Only

SG/Optimise

GPU Control PU/PD

VGPU_EN

R220*10K_4

DGPU_PWR_EN

R257*10K_4

GC6_FB_EN

R204*GC6@10K_4

20131015 For GC6 NV DG GC6_FB_EN PD.1A-1

R208 10K_4

DGPU_HOLD_RST#

high UMA Only

GPU power is control by PCH GPIO (Discrete, SG or Optimize)

low

DGPU_PW_CTRL#

DGPU_PWROK

DGPU_PWROK PD on GPU side

DGPU_PW_CTRL#

VGA H/W Signal

UMA

GPU

R115 *IV@1K_4

R110 *10K_4

Setup Menu

Hidden

UMA boot

Hidden

GPU boot

R196*10K_4

R256*100K_4

R199*GC6@10K_4

HDA

+3V

SPKR

PCH_AZ_CODEC_SYNC<26>

PCH_AZ_CODEC_BITCLK<26>

PCH_AZ_CODEC_SDOUT<26>

PCH_AZ_CODEC_SDIN0<26>

PCH_AZ_CODEC_RST#<26>

R624 *20K/F_4

545659-103

Add GPU Power Con trol Siganls

Touch PAD

Touch Screen

ESD request 2015/12/21

DGPU_HOLD_RST#<14>

DGPU_PWR_EN<42>

DGPU_PWROK<16> GC6_FB_EN<14,17>

DGPU_EVENT#<17>

ODD_PRSNT#<27>

C739 22P/50V_4

VGPU_EN<41>

ACCEL_INTA<29>

TP_INT_PCH<23>

I2C0_SDA<29>

I2C0_SCL<29>

I2C1_SDA<23>

I2C1_SCL<23>

C742 *10p/50V_4

R667 33_4 R644 33_4 R645 33_4

R660 33_4

TP4372 TP4373

Strapping

SPKR<26>

VGPU_EN DGPU_HOLD_RST# DGPU_PWR_EN GSPI0_MOSI

GC6_FB_EN

GSPI1_MOSI

TPD_INT#_D

UART2_RXD UART2_TXD UART2_RTS# UART2_CTS#

I2C0_SDA I2C0_SCL

I2C1_SDA I2C1_SCL

HDA_SYNC_R HDA_BCLK_R HDA_SDO_R

HDA_RST#_R

DMIC_CLK0_R DMIC_DATA0_R

SPKR

Skylake-U Strapping Table

Pin Name Strap description

GPP_B14 (SPKR)

B B

GPP_B18 (GSPI0_MOSI)

GPP_C2 (SMBALERT#)

GPP_B22 (GSPI1_MOSI)

GPP_C5 (SML0ALERT#)

SPI0_MOSI

SPI0_MISO

GPP_B23 (SML1ALERT# /PCHHOT#)

SPI0_IO2

A A

SPI0_IO3

HDA_SDO / I2S_TXD0

GPP_E19 (DDPB_CTRLDATA)

GPP_E21 (DDPC_CTRLDATA)

Top-Block Swap override PCH_PWROK

No reboot PCH_PWROK

TLS Confidentiality

Boot BIOS Strap Bit (BBS)

eSPI or LPC

Reserved

Flash Descriptor Security Override / Intel ME Debug Mode

Display Port B Det ected

Display Port C Detec ted

Sampled

RSMRST#

PCH_PWROK

RSMRST#

PCH_PWROK

Configuration note

0 = *Disable T op Swap (iPD 20K)

1 = Enable Top Swap Mode

0 = *Disable No Reboot (iPD 20K)

1 = Enable No Reboot Mode

0 = *Disable I ntel ME Cryp to TLS(iPD 20K)

1 = Enable Int el ME Cryp to TLS

0 = *SPI (iP D 20K)

1 = LPC

0 = *LPC is sel ected for EC (iPD 20K)

1 = eSPI select ed for EC

+3V

+3V_S5

+3V

+3V_S5

(iPU 15 ~ 40K)

(iPD 20K)

(iPU 15 ~ 40K)

0 = *Enable secu rity in the Flash Description (iPD 20K)

1 = Disable Fl ash Descriptor Securi ty (Override)

0 = *Port B i s not detected (iPD 20K)

1 =Port B i s detected

0 = *Port C i s not detected (iPD 20K)

1 =Port C is det ected

R625 *1K_4

R619 *1K_4

R160 *10K_4

R207 *1K_4

change location to near CPU to prevent impact HDA_SDO signal

HDA_SDO_R

AN8 AP7 AP8 AR7

AM5

AN7 AP5 AN5

AB1 AB2

AB3

AD1 AD2 AD3 AD4

U7 U6

U8 U9

AH9

AH10

AH11 AH12

AF11 AF12

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK7 AK6 AK9

AK10

H5 D7

D8 C8

AW5

R586 *1K_4

R737 1K_4

U35F

LPSS ISH

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

SP@SKL_ULT/BGA

U35G

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFR M I2S1_TX D

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

+3V_S5

GPP_B14/SPKR

SP@SKL_ULT/BGA

SPKR

GSPI0_MOSI

GSPI1_MOSI

+3V_S5 +3V_S5 +3V_S5 +3V_S5

+3V_S5 +3V_S5

+1.8V_S5 +1.8V_S5

+3V_S5

+1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5

+3V_S5 +3V_S5

ME_WR# <31>

SKL_ULT

+3V_S5 +3V_S5 +3V_S5 +3V_S5

SKL_ULT

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5

+3V_S5 +3V_S5

<PART_SYM_NUM>

SMBALERT# <7>

SML0ALERT# <7>

+3V_S5 +3V_S5 +3V_S5 +3V_S5

+3V_S5 +3V_S5

+1.8V_S5 +1.8V_S5

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5

<PART_SYM_NUM>

SDIO/SDXC

SD GPI SD GPI SD GPI SD GPI SD GPI SD GPI SD GPI SD GPI

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

+1.8V_S5

GPP_D9 GPP_D10 GPP_D11 GPP_D12

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

R174200/F_4

Touchpad INT

TPD_INT#<29,31>

Reserve UART FFC conn ector for Win 7 debug

UART2_RXD

R275 *49.9K/F_4

UART2_TXD

R280 *49.9K/F_4

UART2_RTS#

R283 *49.9K/F_4

UART2_CTS#

R290 *49.9K/F_4

UART2_RXD UART2_TXD UART2_RTS# UART2_CTS#

TPD_INT#_D

TP4354 TP4355 TP4356 TP4357

S5 S5

*TDI@2N7002K

R164 *short_4

+3V_S5 <2,3,6,7,8,9,11,21,25,27,28,29,31,33,35,36,41> +3V <2,6,7,8,9,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>

Size Document Nu mber Rev

Date: Sheet of

+3V_S5

R177TDI@10K_4

+3V

TPD_INT#_D

Q20

Quanta Computer Inc.

PROJECT :

Skylake 6/7 (PEG/DMI/FDI)

Friday, February 05, 2016

ZAA

448

Dr-Bios.com

Backside cap

C184

1U/6.3V_2

C243 22u/6.3V_6

C233 22u/6.3V_6

C226 22u/6.3V_6

C203 22u/6.3V_6

C219 22u/6.3V_6

C224 22u/6.3V_6

Backside cap

C214

C245

1U/6.3V_2

D D

C273

C272 22u/6.3V_6

C282 22u/6.3V_6

22u/6.3V_6

C676 10u/6.3V_4

C289 22u/6.3V_6

C258

C259

10u/6.3V_4

Backside cap

C189

1U/6.3V_2

C647 10u/6.3V_4

C252 1U/6.3V_4

Backside cap

C262

C212

1U/6.3V_2

C196

1U/6.3V_2

C201

1U/6.3V_2

C215

1U/6.3V_2

C227 1U/6.3V_4

Backside cap

C237

C228

1U/6.3V_2

Backside cap

For 2+3e CPU

Backside cap

C686

For 2+3e CPU

*GT3@10u/6.3V_4

+1.8V_PRIM+1.8V_S5

C269

1U/6.3V_2

C186 10u/6.3V_4

C197

1U/6.3V_2

+VCCCORE <37,38> +VCCOPC <35>

+VCCEOPIO <35>

+1.8V_S5 <8,9,10,40> +VCCGT <37,38>

+1V_VCCST <2,8,9,37>

+VCCIO <2,8,32,34,37,40> +VCCSA <37,39> +1.2VSUS <3, 12,13,36> +1V_SUS <34>

C181

1U/6.3V_2

+VCCEOPIO

C708

*GT3@10u/6.3V_4

+1.8V_PRIM

*GT3@10u/6.3V_4

C C

B B

A A

C709 *GT3@10u/6.3V_4

C687

R565

*GT3@0_6

C185 10u/6.3V_4

C194 1U/6.3V_4

C209

1U/6.3V_2

Backside cap

C682 *GT3@10u/6.3V_4

Backside cap

C158

C155

10u/6.3V_4

Backside cap

C188

C193

1U/6.3V_2

+1.2VSUS

Backside cap

+1V_SUS

+VCCIO

+1V_SUS

C318 10u/6.3V_4

C236 22u/6.3V_6

C651 10u/6.3V_4

C222

1U/6.3V_2

C246

1U/6.3V_2

C285

1U/6.3V_2

C684

C688

*GT3@1U/6.3V_2

*GT3@1U/6.3V_4

For 2+3e CPU

C232 10u/6.3V_4

C241 1U/6.3V_4

C328 10u/6.3V_4

C326 10u/6.3V_4

R194 *short_4

R550 *short_6

R135 *short_6

R112 *short_6

+VCCCORE

C255

C251

22u/6.3V_6

C657

C257

10u/6.3V_4

C235

1U/6.3V_2

C200

1U/6.3V_2

100 ohm near CPU

C681

*GT3@1U/6.3V_2

C151 10u/6.3V_4

C239

1U/6.3V_2

+VCCOPC

C685

*GT3@1U/6.3V_2

1.0V_CPU 3A

C218 10u/6.3V_4

C240

1U/6.3V_2

100 ohm Near CPU

Backside cap

C313

C308

1U/6.3V_2

Primary side cap

C323

C325

10u/6.3V_4

+VDDQC

C299

C286 10u/6.3V_4

1U/6.3V_2

Primary side cap

Backside cap

Primary side cap

For 2+3e CPU

+1.8V_PRIM

+VCCOPC

+VCCOPC_SRC<35>

681_AGND<35>

For 2+3e CPU

+VCCOPC_SRC 681_AGND

+VCCOPC

C683

*GT3@1U/6.3V_4

C223

C161

10u/6.3V_4

C204

C198

1U/6.3V_2

VCCGT_SEN SE<37> VSSGT_SE NSE<37>

C311

1U/6.3V_2

C327 10u/6.3V_4

+1V_VCCST

C677

1U/6.3V_4

+VCCOPC

+1.8V_PRIM

R172 *GT3@100/F_4

R634 *GT3@0_4 R636 *GT3@0_4

R176 *GT3@100/F_4

+VCCEOPIO

R633 *GT3@0_4 R632 *GT3@0_4

C689

*GT3@1U/6.3V_4

+VCCGT

C148 10u/6.3V_4

C206

1U/6.3V_2

C195

C205

1U/6.3V_2

1U/6.3V_4

+VCCGT

R155 100/F_4

R161 100/F_4

C312

1U/6.3V_2

+VCCSTG

C176

1U/6.3V_4

+VCCPLL

TP12

TP20

+1.2VSUS

C172

1U/6.3V_4

A30 A34 A39

A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40 AM32 AM33 AM35 AM37 AM38

G30

K32

AK32

AB62

P62

V62

H63

G61

AC63 AE63

AE62 AG62

AL63 AJ62

A48

A53

A58

A62

A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

J43

J45

J46

J48

J50

J52

J53

J55

J56

J58

J60

K48

K50

K52

K53

K55

K56

K58

K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71

M62

N63

N64

N66

N67

N69

J70

J69

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

A18

A22

AL23

K20

K21

SKL_ULT

U35L

VCC_A30

VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

SP@SKL_ULT/BGA

SKL_ULT

U35M

CPU POWER 2 OF 4

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT

0.55~1.5V

VCCGT VCCGT VCCGT VCCGT

2+3e peak 6A

VCCGT

2+3e TPY 4A

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

SP@SKL_ULT/BGA

U35N

SKL_ULT

CPU POWER 3 OF 4

DDR3L

VDDQ_AU23 VDDQ_AU28

1.35V

VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC

VCCST

1.0V

VCCSTG_A22

VCCPLL_OC

1.0V

VCCPLL_K20 VCCPLL_K21

120mA

1.0V

SP@SKL_ULT/BGA

CPU POWER 1 OF 4

VCC

0.55V~1.5V

2+2 peak 24A 2+2 TPY 17A

2+3e peak 24A 2+3e TPY 17A

1.0V

1.8V

GT3 CPU

1.0V

<PART_SYM_NUM>

VCCGT

0.55~1.5V

2+2 peak 31A 2+2 TPY 15A

2+3e peak 56A 2+3e TPY 17A

VCCGTX

2+2 X

VCCGTX_SENSE

VSSGTX_SENSE

<PART_SYM_NUM>

0.85V/0.95V

3.0A

1.15V

2+2 peak 5A 2+2 TPY 4A 2+3e peak 5.1A 2+3e TPY 5A

120mA

40mA

1.0V

260mA

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

<PART_SYM_NUM>

50mA

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70

VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42 VCC_J30 VCC_J33 VCC_J37 VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

+VCCCORE

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

+VCCGT

TP17 TP14

R109 100/F_4

VSASS_SEN SE <37> VSA_SENSE <37>

R122 100/F_4

100 ohm near CPU

C174

1U/6.3V_4

+VCCGT

+VCCSA

R96 100/F_4

R98 100/ F_4

C199 47u/6.3V_8

C693 22u/6.3V_6

C692 22u/6.3V_6

C303 *GT3@22u/6.3V_6

C291 *GT3@10u/6.3V_4

+VCCIO

+VCCSA

C645

C666

47u/6.3V_8

C679

C667

10u/6.3V_4

+VCCCORE

+VCCSTG

Primary side cap

C190

C702

47u/6.3V_8

Primary side cap

C705

C178

22u/6.3V_6

Primary side cap

C202

C704

22u/6.3V_6

Primary side cap

C277

C310

22u/6.3V_6

*GT3@22u/6.3V_6

C281

C279

*GT3@10u/6.3V_4

C284 10u/6.3V_4

C701

1U/6.3V_4

C254 10u/6.3V_4

C207

1U/6.3V_2

C114 10u/6.3V_4

Primary side cap

C144

C650

47u/6.3V_8

Primary side cap

C674

C664

10u/6.3V_4

100 ohm Near CPU

VCORE_SE NSE <37> VCORESS_ SENSE <37>

H_CPU_SVIDART# H_CPU_SVIDCLK H_CPU_SVIDDAT

C690 47u/6.3V_8

C706

C171

22u/6.3V_6

C4816

C694

22u/6.3V_6

C307

C302 *GT3@22u/6.3V_6

*GT3@22u/6.3V_6

Backside cap

C324

C316 *GT3@10u/6.3V_4

*GT3@10u/6.3V_4

For 2+3e CPU

Backside cap

C266

C283

1U/6.3V_2

10u/6.3V_4

Primary side cap

C700

C710

1U/6.3V_4

Backside cap

C247

C238

10u/6.3V_4

Backside cap

C278

C216

1U/6.3V_2

1U/6.3V_4

Primary side cap

C643

C641

10u/6.3V_4

C659 47u/6.3V_8

C673 10u/6.3V_4

SVID

C248 47u/6.3V_8

C707 22u/6.3V_6

C691 22u/6.3V_6

C274 22u/6.3V_6

C280

*GT3@10u/6.3V_4

Imax 3(A)

C297

1U/6.3V_2

C711

1U/6.3V_4

C229 10u/6.3V_4

C242 1U/6.3V_4

C165 10u/6.3V_4

C675 10u/6.3V_4

H_CPU_SVIDDAT

Place PU resistor close to CPU

H_CPU_SVIDART#

H_CPU_SVIDCLK

C703 22u/6.3V_6

C275 22u/6.3V_6

C290 *GT3@10u/6.3V_4

C264

1U/6.3V_2

C221 10u/6.3V_4

C260

1U/6.3V_2

C642 10u/6.3V_4

C150 47u/6.3V_8

C697 47u/6.3V_8

C4732 47u/6.3V_8

C678

C663

10u/6.3V_4

+1V_VCCST

Layout note: need routing together and ALERT need between CLK and DATA.

C814

R138 100/F_4

R552 220/F_4

C298

1U/6.3V_2

C263 10u/6.3V_4

C267

1U/6.3V_2

C157 10u/6.3V_4

1000P/50V_4

+1V_VCCST

C696 47u/6.3V_8

C276 *GT3@22u/6.3V_6

C317

*GT3@10u/6.3V_4

C288 10u/6.3V_4

C249

1U/6.3V_2

C815 *1000P/50V_4

DATA & CLK must be equal (± 0.1 inch).

R134

54.9/F_4

C816

C817

*1000P/50V_4

Size Document Number Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

C819

C818

*1000P/50V_4

H_CPU_SVIDDAT < 37>

VR_SVID_ALE RT#_VCOR E <37>

H_CPU_SVIDCLK <37>

Quanta Computer Inc.

PROJECT :

Skylake 12/13/1 4 (POWER)

ZAA

548

Dr-Bios.com

+3V <2,4,7,8,9,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42> +3V_S5 <2,3,4,7,8,9,11,21,25,27,28,29,31,33,35,36,41> +3VPCU <9,11,23,25,26,27,28,29,31,32,33,40,41,42> +3V_RTC <8,9,31> +1V_S5 <9,34>

PEG_RX#0<14>

PEG_RX0<14>

D D

dGPU PEG*4

PEG_TX#0<14>

PEG_TX0<14>

PEG_RX#1<14>

PEG_RX1<14>

PEG_TX#1<14>

PEG_TX1<14>

PEG_RX#2<14>

PEG_RX2<14>

PEG_TX#2<14>

PEG_TX2<14>

PEG_RX#3<14>

PEG_RX3<14>

PEG_TX#3<14>

PEG_TX3<14>

C653 EV@0.22u/10V_4 C652 EV@0.22u/10V_4

C656 EV@0.22u/10V_4 C655 EV@0.22u/10V_4

C661 EV@0.22u/10V_4 C662 EV@0.22u/10V_4

C654 EV@0.22u/10V_4 C660 EV@0.22u/10V_4

For Thunderbolt

SATA_RXN0<27>

HDD

ODD

C C

LAN

WIFI

For M.2 SSD -NA

For M.2 SSD -1

B B

N16S VGA

M.2 SSD

For Thunderbolt

LANWLAN

A A

PCIE_RX5-_LAN<25> PCIE_RX5+_LAN<25>

PCIE_TX5-_LAN<25> PCIE_TX5+_LAN<25>

PCIE_RX6-_WLAN<28> PCIE_RX6+_WLAN<28>

PCIE_TX6-_WLAN<28> PCIE_TX6+_WLAN<28>

SATA_RXN3/PEG_RXN9_L0<28> SATA_RXP3/PEG_RXP9_L0<28>

SATA_TXN3/PEG_TXN9_L0<28>

SATA_TXP3/PEG_TXP9_L0<28> SATA_RXN3/PEG_RXN10_L1<28> SATA_RXP3/PEG_RXP10_L1<28>

SATA_TXN3/PEG_TXN10_L1<28>

SATA_TXP3/PEG_TXP10_L1<28>

CLK_PCIE_VGA#<14>

CLK_PCIE_VGA<14>

CLK_PEGA_REQ#<14>

NGFF_SSD_CLK#<28> NGFF_SSD_CLK<28>

PCIE_CLKREQ_NGFF_SSD#<28>

CLK_PCIE_LANN<25>

CLK_PCIE_LANP<25>

CLK_PCIE_LAN_REQ#<25>

CLK_PCIE_WLANN<28> CLK_PCIE_WLANP<28>

PCIE_CLKREQ_WLAN#<28>

CLK_PCIE_REQ0# CLK_PCIE_REQ1#

CLK_PCIE_REQ2#

CLK_PCIE_REQ3# CLK_PCIE_REQ4# CLK_PCIE_REQ5#

TP4389

TP4387

SATA_RXP0<27> SATA_TXN0<27> SATA_TXP0<27>

SATA_RXN1<27> SATA_RXP1<27> SATA_TXN1<27> SATA_TXP1<27>

C668 0.1u/16V_4 C669 0.1u/16V_4

C648 0.1u/16V_4 C649 0.1u/16V_4

R562 100/F_4

TP91 TP92

R235 *short_4

R11112 *short_4 R11113 *short_4 R11111 *short_4

TP22

R229 *short_4

R224 *short_4 J1

R234 10K_4 R215 10K_4

R227 *10K_4

R618 *10K_4 R228 10K_4 R223 10K_4

TP4380 TP4379 TP4382 TP4381

TP4385 TP4383 TP4386 TP4384

XDP_PRDY# XDP_PREQ# PIRQA#

+3V

C_PEG_TX#0 C_PEG_TX0

C_PEG_TX#1 C_PEG_TX1

C_PEG_TX#2 C_PEG_TX2

C_PEG_TX#3 C_PEG_TX3

PCIE_TX5PCIE_TX5+

PCIE_TX6PCIE_TX6+

PCIE_RCOMPN PCIE_RCOMPP

CLK_PCIE_REQ0#

NGFF_SSD_CLK#_C NGFF_SSD_CLK_C CLK_PCIE_REQ1#

CLK_PCIE_REQ2#

CLK_PCIE_REQ3#

CLK_PCIE_REQ4#

CLK_PCIE_REQ5#

Skylake ULT (GPU, SATA , ODD, CLK ,USB2&3)

H13 G13 B17 A17

G11 F11 D16 C16

H16 G16 D17 C17

G15 F15 B19 A19

F16 E16 C19 D19

G18 F18 D20 C20

F20 E20 B21 A21

G21 F21 D21 C21

E22 E23 B23 A23

F25 E25 D23 C23

F5 E5

D56 D61

BB11

E28 E27 D24 C24 E30 F30 A25 B25

D42 C42

AR10

B42 A42 AT7

D41 C41 AT8

D40 C40

AT10

B40 A40 AU8

E40 E38 AU7

U35H

PCIE/USB3/SATA

PCIE1_RXN/USB3_5_RXN PCIE1_RXP/USB3_5_RXP PCIE1_TXN/USB3_5_TXN PCIE1_TXP/USB3_5_TXP

PCIE2_RXN/USB3_6_RXN PCIE2_RXP/USB3_6_RXP PCIE2_TXN/USB3_6_TXN PCIE2_TXP/USB3_6_TXP

PCIE3_RXN PCIE3_RXP PCIE3_TXN PCIE3_TXP

PCIE4_RXN PCIE4_RXP PCIE4_TXN PCIE4_TXP

PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP

PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP

PCIE7_RXN/SATA0_RXN PCIE7_RXP/SATA0_RXP PCIE7_TXN/SATA0_T XN PCIE7_TXP/SATA0_T XP

PCIE8_RXN/SATA1A_RXN PCIE8_RXP/SATA1A_RXP PCIE8_TXN/SATA1A_T XN PCIE8_TXP/SATA1A_T XP

PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP

PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP

PCIE_RCOMPN PCIE_RCOMPP

PROC_PRDY# PROC_PREQ#

+3V_S5

GPP_A7/PIRQA#

PCIE11_RXN/SATA1B_RXN PCIE11_RXP/SATA1B_RXP PCIE11_TXN/SATA1B_T XN PCIE11_TXP/SATA1B_T XP PCIE12_RXN/SATA2_RXN PCIE12_RXP/SATA2_RXP PCIE12_TXN/SATA2_T XN PCIE12_TXP/SATA2_T XP

SP@SKL_ULT/BGA

U35J

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#

SP@SKL_ULT/BGA

Rev:D add for EC reset RTC

SKL_ULT

CLOCK SIGNALS

+3V_S5

CLR_CMOS<31>

SKL_ULT

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

+3V_S5 +3V_S5 +3V_S5 +3V_S5

+3V_S5

+3V_S5 +3V_S5

+3V_S5 +3V_S5 +3V_S5

<PART_SYM_NUM>

+3V_S5

<PART_SYM_NUM>

CLR_CMOS CLR_CMOS

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

+3V_S5

GPP_E8/SATALED#

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

R786 100K_4

USB3_1_RXN USB3_1_RXP USB3_1_TXN

USB3_1_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN

USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

F43 E43

BA17

E37

XTAL24_IN

E35

XTAL24_OUT

E42

XCLK_BIASREF

AM18

RTC_X1

AM20

RTC_X2

AN18

SRTC_RST#

AM16

RTC_RST#

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

CLK_PCIE_XDPN CLK_PCIE_XDPP

SUSCLK

SRTC_RST#

Q6059 *2N7002K

TP4377 TP4378

USBCOMP

R178 113/F_4

USB2_ID

R587 1K_4 R778 1K_4

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

DEVSLP0 SATA_DEVSLP1 SATA_DEVSLP2

SATAGP0 SATAGP1

R512 2.7K/F_4

USB3_RXN0 <30> USB3_RXP0 <30> USB3_TXN0 <30> USB3_TXP0 <30>

USB3_RXN1 <30> USB3_RXP1 <30> USB3_TXN1 <30> USB3_TXP1 <30>

USB3_RXN2 <21> USB3_RXP2 <21> USB3_TXN2 <21> USB3_TXP2 <21>

USB3_RXN3 <21> USB3_RXP3 <21> USB3_TXN3 <21> USB3_TXP3 <21>

USBP0- <30> USBP0+ <30>

USBP1- <30> USBP1+ <30>

USBP2- <30> USBP2+ <30>

USBP3- <30> USBP3+ <30>

USBP4- <28> USBP4+ <28>

USBP5- <23> USBP5+ <23>

USBP6- <23> USBP6+ <23>

USBP7- <21> USBP7+ <21>

USBP8- <27> USBP8+ <27>

USB_OC0# <30> USB_OC1# <30> USB_OC2# <30> USB_OC3# <21>

TP93 TP94

SUSCLK <28>

RTC_RST# <11>

1V power plane

0.71 checklist p14

MB USB3.0 ( Charger IC )

MB USB3.0

For TYPE-C

MB USB3.0 Charger IC )

MB USB3.0

DB USB2.0

For 17" DB use

Touch Screen

CCD

For TYPE-C

POA

USBCOMP Impedance = 50 ohm Trace length < 500 m ils Trace spacing = 15 m ils

MB U3

DB U2

DEVSLP0 <27>

SATA_DEVSLP2 <28>

NGFF_SATA_DET <28>

+1V_S5

MB U3

For Type-C

RTC_RST#

Q6060 2N7002K

Add SSD ID 1/1 4

Hight is SSD , Low is ODD

SSD_ID<27>

Skylake-U userd 24 MHz (50 Ohm ESR) XTAL

XTAL24_IN XTAL24_OUT

Note: Change Y4 to 38.4 MHz(ESR 30 ohm) for Cannonlake U

RTC Clock 32.768KHz (RTC)

Trace length < 1000 mils

RTC Circuitry (RTC)

+3VPCU

On SKL voltage at VCCRTC does not exceed 3.2V

R304

1.5K/F_4

VCCRTC_2

R301

45.3K/F_4

2013/10/16 Chage +3V_RTC_0 to VCCTC_2.

1A-2

1. AHL03003057 DBV CR2032

2. AHL03003003 VDE CR2032

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

R568 10K_4

R536 1M_4

C351 8.2p/50V_4

C362 8.2p/50V_4

1B-1

R308 1K_4

+3V_RTC_[0:2] Trace width = 20 m ils

BT1

BAT_CONN

PCH PU/PD

DEVSLP0 SATA_DEVSLP1 SATA_DEVSLP2 PIRQA#

SATAGP1

SATAGP0

C665 10P/50V_4

Y4 24MHz

C658 10P/50V_4

32.768KHZ

+3V_RTC_2

+3V_RTC_1

BAT54C

Size Document Nu mber Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

+3V_S5

R541 10K_4 R540 10K_4 R543 10K_4 R542 10K_4

+3V

R573 *10K_4 R574 *10K_4 R575 *10K_4 R631 *10K_4

R569 *10K_4

+3V_S5

R570 100K_4

24MHz: BG624000078

38.4MHz : ?

CH01006JB08 -> 10p CH01506JB06 -> 15p CH-6806TB01 -> 6.8p

RTC_X1

R255 10M_4

RTC_X2

+3V_RTC

Trace width = 30 m ils

R299

20K/F_4

R300

20K/F_4

C381 1u/6.3V_4

Quanta Computer Inc.

PROJECT :

Skylake 9/10 (PEG/USB/CLK)

C380 1u/6.3V_4

C382 1u/6.3V_4

BG332768453 - > SEG

BG332768104 - > TXC

ZAA

RTC_RST#

*JUMP

SRTC_RST#

648

Dr-Bios.com

U35E

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO

GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SP@SKL_ULT/BGA

SPI - FLASH

SPI - TOUCH

C LINK

+3V_S5

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5

+3V_S5

PCH_SPI_CLK PCH_SPI_SO

D D

PCH_SPI_SI PCH_SPI_IO2 PCH_SPI_IO3 PCH_SPI_CS0#

For M.2 wifi module must

SIO_RCIN#<31>

IRQ_SERIRQ<27,31>

C C

R652 *short_4

IRQ_SERIRQ

EC_RCIN#

AW3

AW2

AW13

AY11

AV2

AV3

AU4 AU3 AU2 AU1

M2 M3

V1 V2 M1

G3 G2 G1

SP@ socket P/N: DFHS08FS023 only for A-TEST

SPI ROM

Skylake

3.3V

B B

A A

Vender Size Quanta P/N Vender P/N

W25Q64FVSSIQWND

GD25B64CSIGRGGD

PCH_SPI_CLK_EC PCH_SPI_SI_EC PCH_SPI_SO_EC

R602 *short_4

SPI_CS0#_UR_ME

PCH_SPI_CLK_EC<31>

SPI_CS0#_UR_ME<31>

PCH_SPI_SI_EC<31>

PCH_SPI_SO_EC<31>

8M 8M

+3V_PCH_ME

AKE3EFP0N07

AKE2EZN0Q00

R591 10K_4

PCH_SPI_CS0#

Platform

SKL KBL

PCH_SPI_SO PCH_SPI_SO_EC

1A-13

+3V_PCH_ME

SKL_ULT

LPC

+3V_S5

<PART_SYM_NUM>

Winbound for SKL / Giga for KBL

PCH_SPI_CS0#

R650 15_4 R588 15_4

R649 1K_4

3.3K is original and for no support fast read func tion

SMBUS, SMLINK

+3V_S5 +3V_S5 +3V_S5

+3V_S5 +3V_S5

GPP_B23/SML1ALERT#/PCHHOT#

+3V_S5

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5

+3V_S5 +3V_S5

+3V_S5

SPI_SO_8M

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

U41

ROM@W25Q64FV -- 8MB

SPI_WP_IO2_ME

PCH_SPI_IO2

PCH_SPI_IO3

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

PCH_MBCLK0_R

PCH_MBDAT0_R

R10

VGA_MBCLK

VGA_MBDATA

SMB_ME1_CLK

SMB_ME1_DAT

AM7

SML1ALERT#

SMBALERT#

SML0ALERT#

SMB1ALERT# <29>

eSPI change to 15 ohm

AY13

R659 *short_4

BA13

R640 *short_4

BB13

R653 *short_4

AY12

R668 *short_4

BA12 BA11

eSPI change to 15 ohm

AW9

R623 22_4

AY9 AW11

CLK

R626 22_4 R627 22_4

CLKRUN#

R11127 0_6

R11126 *0_6

SPI_HOLD_IO3_ME

SPI_CLK_8M

SPI_SI_8M

R687 15_4 R654 15_4

SPI_WP_IO2_ME

SPI_HOLD_IO3_ME

GPP_A8/CLKRUN#

+3V_S5

+3V_LDO_EC

CS#

IO1/DO

IO2/W P#

GND

VCC

IO3/HOLD #

IO0/DI

PCH_SPI_CLK_EC PCH_SPI_SI_EC

R589 15_4

R239 15_4

+3V <2,4,6,8,9,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42> +3V_S5 <2,3,4,6,8,9,11,21,25,27,28,29,31,33,35,36,41>

LPC_LAD0 <27,28,31> LPC_LAD1 <27,28,31> LPC_LAD2 <27,28,31> LPC_LAD3 <27,28,31> LPC_LFRAME# <27,28,31>

CLK_PCI_EC <31>

PCLK_TPM <27>

CLKRUN# <27,31>

+3V_PCH_ME

C754 0.1u/16V_4

R698 1K_4

R684 15_4

R691 15_4

reserve for SPI fast read

Strapping

SMBALERT# <4>

SML0ALERT# <4>

ckl v0.71 p.24

C806 0.1u/16V_4

+3V_PCH_ME

PCH_SPI_CLK

PCH_SPI_SI

C747 *22p/50V_4

2/10 add C806 for EMI request , R748 no stuif f from E C site move at CPU site

C4723 *22p/50V_4

CLK_PCI_LPC <28>

EMI

SMBus(PCH)

PCH_XDP_WLAN/S5 DDR_TP/S0

SMBus(EC)

CLKRUN# IRQ_SERIRQ EC_RCIN#

R630 8.2K/F_4 R629 10K_4 R639 10K_4

SMBus

PCH_MBCLK0_R PCH_MBDAT0_R VGA_MBDATA VGA_MBCLK

SML1ALERT#

Termination Resistor Requ irement for PCH PCHHOT# Pin Reserve PU 150 K resister

+3V

D2B change to 2.2k

Q32

PCH_MBDAT0_R

PCH_MBCLK0_R

2ND_MBCLK<17,31> 2ND_MBDATA<17,31>

2N7002DW

2ND_MBCLK 2ND_MBDATA

R5782.2K_4 R5802.2K_4 R5852.2K_4 R5822.2K_4

R205*15 0K_4

R576

2.2K_4

R171 *short_4 R175 *short_4

R572

2.2K_4

EC/S5

+3V

+3V_S5

CLK_SDATA <12,13,22,29>

CLK_SCLK <12,13,22,29>

SMB_ME1_CLK SMB_ME1_DAT

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

PROJECT :

Skylake 5 (SATA/HDA/SPI)

ZAA

748

Dr-Bios.com

U35K

+VCCIO

11/12 Reserve PU 10K

R544 *10K_4

D D

PROC_PWRGD

EC only PD, so PD 10K

PCH_SUSPWRACK

R11114

10K_4

Board ID

C C

R610 SP@10K_4 R612 10K_4 R614 10K_4 R595 *10K_4 R598 SP@10K_4 R605 SP@10K_4 R592 SP@10K_4

R606 *10K_4 R764 10K_4 R766 SP@10K_4

)'#"!*+!,

)'#"!*+!5

)'#"!*+!6

)'#"!*+!7

)'#"!*+!1

B B

No TPM

No touch panel

PLTRST# Buffer

A A

PCI_PLTRST#

RAM_ID1 RAM_ID2 RAM_ID3 Board_ID0 Board_ID1 Board_ID2 Board_ID3 Board_ID4

Board_ID5 Board_ID6 Board_ID7

234

-./0

VRAM X32 VRAM X16

IOACNon IOAC

G-sensor No G-sensor

TPM

touch panel

+VCCIO <2,5, 32,34,37,40> +3V_RTC <6,9,31> +3V <2,4,6,7,9,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42> +3V_S5 <2,3,4,6,7,9,11,21,25,27,28,29,31,33,35,36,41>

+1.8V_S5 <5,9,10,40> +1V_VCCST <2,5,9,37>

+3V

C332 0.1u/16V_4

U14

3 5

TC7SH08FU

SYS_RESET#<11>

RSMRST#<31>

SYS_PWROK

PCH_SUSPWRACK<31>

PCIE_LAN_WAKE#<25,28>

R611 *SP@10K_4 R613 *10K_4 R615 *10K_4 R600 10K_4 R599 SP@10K_4 R608 SP@10K_4 R590 SP@10K_4 R593 10K_4

R607 10K_4 R765 *10K_4 R767 SP@10K_4

)'#"!*+!9

)'#"!*+!:

R214 100K_4

R655 *short_4

R554 10K_4

R556 *short_4 R643 *0_4

PCH_SUSPWRACK

TP4368

+1.8V_S5

14" 15/17")'#"!*+!8

Reserved (Default)

GPU--> KA (Kill A-chanel)

(Default)

PLTRST# <14,25,27,28,31 >

PCI_PLTRST# SYS_RESET# PCH_RSMRST#

PROC_PWRGD VCCST_PWRGD

SYS_PWROK_R EC_PWROK_R DPWROK_R PCH_ACPRESENT

R11140 *short_4

SUSACK#_R

PCIE_LAN_WAKE#

TP84

-./0234

Reserve

GPU--> KB (Kill B-chanel)

AN10

GPP_B13/PLTRST#

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRG D

B65

VCCST_PW RGD

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SP@SKL_ULT/BGA

U35I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SP@SKL_ULT/BGA

Power Sequence

PCH_PWROK<31>

For platforms not supporting Deep Sx, connect directly to RSMRST#

SYSPWOK

SYS_PWROK

SKL_ULT

SYSTEM POWER MANAGEMENT

+3V_S5

I I

+3V_S5

+3V_S5 +3V_S5 +3V_S5

SKL_ULT

+1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5

+1.8V_S5 +1.8V_S5 +1.8V_S5

+3V_S5

+3V_S5 +3V_S5

<PART_SYM_NUM>

GPP_D4/FLASHTRIG

+3V_S5

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

<PART_SYM_NUM>

+3V_S5 +3V_S5 +3V_S5 +3V_S5

+3V_S5 +3V_S5

+3V_S5 +3V_S5 +3V_S5

+3V_S5

GPP_B11/EXT_PWR_GATE#

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

EMMC_RCOMP

Rev:D change to shortpad

EC_PWROK SYS_PWROK_R

No Deep Sx

DPWROK_R PCH_RSMRST#

R661 *short_4

+3V_S5

C168 *0.1u/16V_4

U8 *TC7SH08FU

R113 *0_4

R560 *short_4

EC_PWROK

3 5

GPD4/SLP_S3# GPD5/SLP_S4#

SLP_SUS# SLP_LAN#

GPD6/SLP_A#

GPP_A11/PME#

INTRU DER#

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

INTRUDER#

AM10

MPHY_EXT_PWR

AM11

PCH_VRALERT#

R145 100/F_4

RAM_ID1 RAM_ID2 RAM_ID3 Board_ID0 Board_ID1 Board_ID2 Board_ID3 Board_ID4

Board_ID5 Board_ID6 Board_ID7

R616200/F_4

SUSB# SUSC# PCH_SLP_S5#

PCH_SLP_SUS# PCH_SLP_LAN# PCH_SLP_WLAN# PCH_SLP_A#

PCH_PWRBTN#

PCH_BATLOW#

GPP_B12/SLP_S0#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_B2/VRALERT#

Non Deep Sx

R647 *short_4

R131 *0_4

EC_PWROK_R

Rev:D change to shortpad

EC_PWROK < 31>

IMVP_PWRGD_3V <2>

R130 *10K_4

TP29

R249

1M_4

TP19

TP63

Board_ID4 <23>

REV:E tPLT17(max

200us) ->SLP_S3# assertion to IMVP VR_ON(VRON) deassert ion

VRON_R<35,37>

Stuff 1000P/50V

TP30 TP23

R677*short_4

R676*short_4

TP74

+3V_RTC

U50 *TC7SH08FU

R792 *short_4

VCCST_PWRGD

C136 1000P/50V_4

TP4367

SUSB# <11,31,33> SUSC# <11, 31> PCH_SLP_S5# <11>

TP4369

PCH_SLP_A# <11> DNBSWON# <31>

SB_ACDC <31>

+3V_S5

C813 *0.1u/16V_4

3 5

+1V_VCCST

R89 60.4/F_4

Shortpad change to 60.4 ohm. 11/6

REV:E tPLT15 (max 200us)

->SLP_S4# assertion to VDDQ(+1.35VSUS) ram p down start(SUSON)

SUSON_R<34,36>

SUSB#

VRON

VRON <31>

CRB is via +1.05V PGVCCST PWRGD

+3V_S5

VCC

C164

R85

0.1u/16V_4

1K_4

VCCST_PWRGD_R

74AUP1G07GW

PCH_VRALERT# SYS_RESET#

PCH_ACPRESENT PCH_BATLOW#

PCIE_LAN_WAKE#

MPHY_EXT_PWR

PCH_RSMRST# PCH_PWROK SYS_PWROK_R

+3V_S5

SUSON_R

U48 *TC7SH08FU

R790 *short_4

REV:E tPLT18 (max 200 us)

->SLP_S3# assertion to VCCIO VR(MAIND for +1V_S5 to +VCCIO) disabled

MAINON_R<33,36,40>

VCCST_PWRGD_EN_L

GND

PCH_PWROK

HWPG<31>

Rev:D change netmane for HWPG

Change for leakage

R211 10K_4 R561 10K_4

R651 8.2K/F_4 R628 8.2K/F_4

R250 10K_4

R195 *1K_4

R642 10K_4 R648 10K_4 R555 10K_4

C811 *0.1u/16V_4

3 5

C823 *1000P/50V_4

HWPG

SUSC#

SUSON

U49 *TC7SH08FU

R791 *short_4

B2A S0->S5 & S0->S3 Power of sequence 1 us SUSB# -> VCCST_PWRGD

U47 TC7SH08FU

C824 *1000P/50V_4

R777 *0_4

Reserve 1000P/50 V

R103*0_4

R102*short_4

Size Document Nu mber Rev

Date: Sheet of

+3V_S5

Rev:F add

SUSON <31>

+3V_S5

C812 *0.1u/16V_4

3 5

+3V_S5

C808 0.1u/16V_4

3 5

Friday, February 05, 2016

+3V

SUSB#

MAINON

VCCST_PWRGD_EN

MAINON <27,31>

SUSB#

Quanta Computer Inc.

PROJECT :

Skylake 9/11 (PWROK/Board_ID)

ZAA

848

<2,4,6,7,8,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>

Dr-Bios.com

U35S

E68

D D

CFG4

R156 49.9/F_4

+1V_S5

C C

B B

CFG_RCOMP

R153 1.5K/F_4

B67 D65 D67 E70 C68 D68 C67

G69

G68 H70 G71 H69 G70

E63

E66

E60

AY2 AY1

K46 K45

AL25 AL27

C71 B70

A52

BA70 BA68

G65

E61

F71

F70

F63

F66

D1 D3

F60

J71 J68

F65

F61

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMOD E

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SP@SKL_ULT/BGA

SKL_ULT

RESERVED SIGNALS -1

<PART_SYM_NUM>

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

TP4

A69 B69

AY3

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71 AR56

AW71 AW70

AP56 C64

Rev:D change to shortpa d

Rev:F Remove Short Jumper for all +1V_S5

+1V_S5

TP95

Rev:F reserve TP

+1V_S5

Rev:F Stuff C699

+1V_S5

+3VPCU

+3V_S5

+3V

+1.5V

+3V_S5

R759 *short_4

Rev:D change to shortpad

R760 *short_4 R762 **GT3@0_4

R761 100K_4

+1V_S5

+3V_S5

+1V_S5

+1V_VCCST

VCCPRIM_1P0 & VCCPRIM_CORE Short

AB19 AB20

C217 1U/6.3V_4

C698 1U/6.3V_4

C699 47u/6.3V_8

C695 1U/6.3V_4

R210 *0_6

R212 0_6

R789 0_6

R683 *0_6

R193

R186 *short_6

LPM_ZVM_N <35>

C793 1U/6.3V_4

C191 1U/6.3V_4

C182 47u/6.3V_8

C179 1U/6.3V_4

C225 *1U/6.3V_4

C748 1U/6.3V_4

*short_6

C192 1U/6.3V_4

C261 1U/6.3V_4

C173 1U/6.3V_4

For 2+3e CPU No Stuff

TP88

+VCCDSW_1P0

C7121U /6.3V_4

+VCCPDSW_3P3

C314*0.1U/16V_4

+VCCHDA

+VCCPSPI

+VCCPRIM_3P3

AF18 AF19

AB17

AD17 AD18

AJ17

AJ19

AJ16

AF20 AF21

AJ21

AK20

P18

V20 V21

AL1

K17

N15 N16 N17 P15 P16

K15

L15

V15

Y18

T19 T20

N18

SKL_ULT

U35O

CPU POWER 4 OF 4

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0 VCCMPHYAON_1P0

VCCMPHYGT_1P0_N15 VCCMPHYGT_1P0_N16 VCCMPHYGT_1P0_N17 VCCMPHYGT_1P0_P15 VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0_AB17 VCCPRIM_1P0_Y18

VCCDSW_3P3_AD17 VCCDSW_3P3_AD18 VCCDSW_3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0

VCCPRIM_3P3_AJ21

VCCPRIM_1P0_AK20

VCCAPLLEBB

SP@SKL_ULT/BGA

1.5V

3.3V

1.0V

30mA

11mA

1.0V

642mA

1.0V

22mA

1.0V

3.3V

118mA

3.3V

1.0V

696mA

1.0V

1.258A

26mA

33mA

2.574A

696mA

44mA

33mA 41mA

75mA with AJ21 pin

VCCPRIM_3P3_V19

1.0V

6mA

1.8V

<1mA

VCCRTCPRIM_3P3

3.0V+

RTC

1.0V

135mA

GPP_B0/CORE_VID0

+3V

GPP_B1/CORE_VID1

75mA

696mA

<PART_SYM_NUM>

VCCPGPPG

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTC_AK19 VCCRTC_BB14

GPIO Group Power Plane

AK15

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

+VCCPGPPA

AG15

+VCCPGPPB

Y16

+VCCPGPPC

Y15

+VCCPGPPD

T16

+VCCPGPPE

AF16

+VCCPGPPF

AD15

+VCCPGPPG

V19

+VCCPRIM_3P3

+VCCPRIM_1P0

AA1

+VCCATS_1P8

AK17

+VCCPRTCPRIM_3P3

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11

V0P85A_VID0

AN13

C250 1U/6.3V_4

C349 1U/6.3V_4

+VCCPRTC

C322 1U/6.3V_4

DCPRTC

C680 *1U/6.3V_4

C672 1U/6.3V_4

C292 *1U/6.3V_4 C268 1U/6.3V_4 C230 1U/6.3V_4

C265 *1U/6.3V_4 R198 *short_6 R185 *short_6 R182 *short_6 R187 *short_6 R179 *short_6 R192 *short_6 R188 *short_6

C256 1U/6.3V_4

C270 *1U/6.3V_4

R180 *short_6 R240 *short_6

C348 0.1U/16V_4

R252 *short_6

C352 0.1U/16V_4 C732 0.1U/16V_4

TP31

+3V_S5 +3V_S5

+3V_S5

+1.8V_S5

+3V_S5

R11131 *short_6

+1.8V_S5 +3V_S5

+3V_RTC

+1V_S5

Pin Name Strap description Configuration

CFG[0] Stall reset sequence after PCU PLL lock until de-asserted

CFG[1]

CFG[2]

Reserved Configuration lane

PCI Express* Static x16 Lane Numbering Reversal

1 = *Normal Operation; No stall (iPU 3K)

0 = Stall

1 = *Normal Operation(iPU 3K)

0 = Lan number reversed

Note

H & S processor used only

+1V_S5 <6,34> +3VPCU <6,11,23,25,26,27,28,29,31,32,33,40,41,42> +3V_S5 <2,3,4,6,7,8,11,21,25,27,28,29,31,33,35,36,41> +3V

+1V_VCCST <2,5,8,37> +1.8V_S5 <5,8,10,40> +3V_RTC <6,8,31>

CFG[3] Reserved Configuration lane

CFG[4]

CFG[6:5] PCI Express* Bifunction

A A

eDP enable

CFG[7] PEG Training

CFG[19:8]

Reserved Configuration lane

1 = Disabled (iPU 3K)

0 = *Enabled

00 = 1x8, 2x4 PCI Expres s* 01 = reserved 10 = 2x8 PCI Express* 11 = 1x16 PCI Express*

1 = *PEG Train immediatedly follow RESET# de-asserti on (iPU 3K)

0 = PEG wait for B IOS for training

CFG4

R548 1K_4

H & S processor used only

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

PROJECT :

Skylake PCH-LP 15/19 (POWER)

ZAA

948

Dr-Bios.com

Skylake ULT (GND)

A67

A70 AA2 AA4

AA65 AA68 AB15 AB16 AB18 AB21

AB8

AD13 AD16 AD19 AD20 AD21 AD62

AD8 AE64 AE65 AE66 AE67 AE68 AE69

AF1 AF10 AF15 AF17

AF2

AF4 AF63

AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH6 AH63 AH64 AH67

AJ15 AJ18 AJ20

AJ4 AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8

AL2 AL28 AL32 AL35 AL38

AL4 AL45 AL48 AL52 AL55 AL58 AL64

SKL_ULT

GND 1 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SP@SKL_ULT/BGA

D D

C C

B B

A A

U35P

<PART_SYM_NUM>

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

AT63 AT68

AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71

AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

F68

BA45

SKL_ULT

GND 2 OF 3

<PART_SYM_NUM>

SP@SKL_ULT/BGA

U35Q

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

G10 G22 G43 G45 G48

G52 G55 G58

G60 G63 G66 H15 H18 H71

J11 J13 J25 J28 J32 J35 J38 J42

K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71

L11 L16 L17

VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL_ULT

GND 3 OF 3

<PART_SYM_NUM>

SP@SKL_ULT/BGA

U35R

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

AW69

RSVD_AW69

AW68

+1.8V_S5

R775 *0_4

C794

*1U/6.3V_4

Reserve 1uF no stuff in CPU U11,U12 ball support Cannonlake-U PCH

Size Document Numb er Rev

Date: Sheet of

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

Skylake 10/17/18 (GND)

Friday, February 05, 2016

SKL_ULT

U35T

SPARE

RSVD_F6 RSVD_E3

RSVD_C11

RSVD_B11

RSVD_A11 RSVD_D12 RSVD_C12

RSVD_F52

<PART_SYM_NUM>

SP@SKL_ULT/BGA

+1.8V_S5 <5,8,9,40>

Quanta Computer Inc.

PROJECT :

ZAA

F6 E3 C11 B11 A11 D12 C12 F52

10 48

Dr-Bios.com

D D

C C

B B

R289 *0_6

Intel APS Fixture use

CN2

A A

*ACES_88511-180N

APS1

APS3

APS7

R291 *0_6

R282 *0_4

R278 *0_6 R279 *0_4 R274 *0_4 R273 *0_4

R271 *0_6

R268 *0_4

R265 *0_4

R267 *0_4

APS3

+3V_S5

SYS_RESET#

R272 *0_6

SUSB# <8,31,33>

PCH_SLP_S5# <8> SUSC# < 8,31> PCH_SLP_A# <8>

RTC_RST# <6>

NBSWON# <29,31>

SYS_RESET# <8>

APS7APS1

+3VPCU

+3V_S5 <2,3,4,6,7,8,9,21,25,27,28,29,31,33,35,36,41> +3VPCU <6,9,23,25,26,27,28,29,31,32,33,40,41,42>

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

PROJECT :

CPU/PCH XDP

ZAA

11 48

Dr-Bios.com

M_A_A[13:0]<3>

D D

M_A_WE#<3> M_A_CAS#<3> M_A_RAS#<3>

M_A_ACT#<3> M_A_PARITY<3>

R10890 *1K_4

M_A_ODT0_DIMM<3> M_A_ODT1_DIMM<3>

CLK_SCLK<7,13,22,29> CLK_SDATA<7,13,22,29>

+1.2VSUS

M_A_ALERT#<3>

C1258 *0.1U/10V_4

Close to PCH

M_A_BA#0<3> M_A_BA#1<3> M_A_BG#0<3> M_A_BG#1<3>

M_A_CS#0<3> M_A_CS#1<3> M_A_CKE0<3> M_A_CKE1<3>

M_A_CLK0<3> M_A_CLK0#<3> M_A_CLK1<3> M_A_CLK1#<3>

R10880 *10K_4

R10886 10K_4

R10885 240/F_4

M_A_EVENT#

PM_THRM TRIP#<13>

R10889 *10K_4

CHA_SA2CHA_SA1CHA_SA0

R10877 10K_4

DDR3_DRAMRST#<3,13>

+1.2VSUS

C C

B B

R10872 *10K_4

R10882 10K_4

+3V

TP154 TP153

M_A_EVENT#

CHA_SA0 CHA_SA1 CHA_SA2

R10896 240/F_4 R10871 240/F_4 R10875 240/F_4 R10881 240/F_4 R10879 240/F_4 R10884 240/F_4 R10888 240/F_4 R10892 240/F_4

+1.2VSUS

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_CB0 M_A_CB1 M_A_CB2 M_A_CB3 M_A_CB4 M_A_CB5 M_A_CB6 M_A_CB7

P/N and F/P

JDIM1A

144

133

132

131

128

126

127

122

125

121

146

A10/AP

120

A11

119

A12

158

A13

151

A14/WE#

156

A15/CAS#

152

A16/RAS#

162

S2#/C0

165

S3#/C1

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

150

BA0

145

BA1

115

BG0

113

BG1

149

S0#

157

S1#

109

CKE0

110

CKE1

137

CK0

139

CK0#

138

CK1

140

CK1#

155

ODT0

161

ODT1

253

SCL

254

SDA

256

SA0

260

SA1

166

SA2

CB0

CB1

101

CB2

105

CB3

CB4

CB5

100

CB6

104

CB7

DM0

DM1

DM2

DM3

178

DM4

199

DM5

220

DM6

241

DM7

DM8

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48

(260P)

DDR4 SODIMM 260 PIN

DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8

DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 DQS#8

M_A_DQ0

M_A_DQ4

M_A_DQ2

M_A_DQ6

M_A_DQ5

M_A_DQ1

M_A_DQ7

M_A_DQ3

M_A_DQ13

M_A_DQ8

M_A_DQ15

M_A_DQ10

M_A_DQ9

M_A_DQ12

M_A_DQ11

M_A_DQ14

M_A_DQ21

M_A_DQ16

M_A_DQ23

M_A_DQ22

M_A_DQ17

M_A_DQ20

M_A_DQ18

M_A_DQ19

M_A_DQ28

M_A_DQ29

M_A_DQ30

M_A_DQ26

M_A_DQ25

M_A_DQ24

M_A_DQ31

M_A_DQ27

174

M_A_DQ37

173

M_A_DQ33

187

M_A_DQ35

186

M_A_DQ39

170

M_A_DQ32

169

M_A_DQ36

183

M_A_DQ34

182

M_A_DQ38

195

M_A_DQ41

194

M_A_DQ40

207

M_A_DQ42

208

M_A_DQ45

191

M_A_DQ47

190

M_A_DQ44

203

M_A_DQ43

204

M_A_DQ46

216

M_A_DQ53

215

M_A_DQ49

228

M_A_DQ51

229

M_A_DQ55

211

M_A_DQ48

212

M_A_DQ52

224

M_A_DQ54

225

M_A_DQ50

237

M_A_DQ62

236

M_A_DQ59

249

M_A_DQ60

250

M_A_DQ61

232

M_A_DQ58

233

M_A_DQ63

245

M_A_DQ56

246

M_A_DQ57

M_A_DQS0

M_A_DQS1

M_A_DQS2

M_A_DQS3

179

M_A_DQS4

200

M_A_DQS5

221

M_A_DQS6

242

M_A_DQS7

M_A_DQS8

M_A_DQS#0

M_A_DQS#1

M_A_DQS#2

M_A_DQS#3

177

M_A_DQS#4

198

M_A_DQS#5

219

M_A_DQS#6

240

M_A_DQS#7

M_A_DQS#8

M_A_DQ[63:0] <3>

0-7

8-15

16-23

24-31

33-39

40-47

48-55

56-63

M_A_DQS[7:0] <3>

M_A_DQS#[7:0] <3>

M_A_DQS8

M_A_DQS#8

R10891

240/F_4

R10894

240/F_4

+1.2VSUS

2250mA

255

257 259

258

164

VREF_C A_DIM M0

2 6 10 14 18 22 26 30 36 40 44 48 52 56 60 64 68 72 78 82 86 90 94 98 102 106 168 172 176 180 184 188 192 196 202 206 210 214 218 222 226 230 234 238 244 248 252

261 262

R11170 *0_4

C1265 10U/6.3V_6

C1267 0.1U/10V_4

0.5A

600mA

JDIM1B

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

141

VDD11

142

VDD12

147

VDD13

148

VDD14

153

VDD15

154

VDD16

159

VDD17

160

VDD18

163

VDD19

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

103

VSS25

107

VSS26

167

VSS27

171

VSS28

175

VSS29

181

VSS30

185

VSS31

189

VSS32

193

VSS33

197

VSS34

201

VSS35

205

VSS36

209

VSS37

213

VSS38

217

VSS39

223

VSS40

227

VSS41

231

VSS42

235

VSS43

239

VSS44

243

VSS45

247

VSS46

251

VSS47

VDDSPD

VPP1 VPP2

VTT

VREF_C A

VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68

(260P)

DDR4 SODIMM 260 PIN

VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94

GND GND

R11133 *short_4

+2.5V_SUS

DDR_VTTREF

+2.5V

+3V

Place these Caps near So-Dimm1.

1uF/10uF 4pcs on each side of connector

+1.2VSUS

C1244 1U/6.3V_4

+1.2VSUS <3,5,13,36> +3V <2,4,6,7,8,9,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42> +2.5V_SUS <13,36> DDR_VTTREF <13,36>

+VDDQ <13,36>

A A

+VREF_CA_CPU <3>

C1271 1U/6.3V_4

C1260 1U/6.3V_4

C1273 1U/6.3V_4

C1253 1U/6.3V_4

C1256 1U/6.3V_4

C1254 1U/6.3V_4

C1261 1U/6.3V_4

C1263 10U/6.3V_6 C1247 10U/6.3V_6

C1272 10U/6.3V_6 C1248 10U/6.3V_6

C1262 10U/6.3V_6 C1246 10U/6.3V_6

C1250 10U/6.3V_6 C1264 10U/6.3V_6

DDR_VTTREF

+3V

C1251 1U/6.3V_4

C1275 1U/6.3V_4

C1249 1U/6.3V_4

C1245 1U/6.3V_4

C1270 10U/6.3V_6

C1276 0.1U/16V_4

C1268 10U/6.3V_6

VREF_C A_DIM M0

+2.5V_SUS

C1259 0.1U/16V_4

C1255 10U/6.3V_6

C1266 0.1U/16V_4

C1257 10U/6.3V_6

VREF DQ0 M1 Solution

+VREF_CA_CPU

1023 Change R10410 from 2ohm to 24.9ohn

C1252

0.022U/25V_4

2 1

R10878 2/F_6

R10873 24.9/F_4

+1.2VSUS

R10883 1K/F_4

VREF_C A_DIM M0

R10895 1K/F_4

R10887*0_4

+VDDQ

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

PROJECT :

DDR4 DIMM-STD(5.2H) CHA

ZAA

12 48

Dr-Bios.com

M_B_A[13:0]<3>

D D

M_B_WE#<3> M_B_CAS#<3> M_B_RAS#<3>

M_B_ACT#<3> M_B_PARITY<3>

+1.2VSUS

R10928 240/F_4

M_B_EVENT#

PM_THRM TRIP#<12>

C C

B B

+3V

R10940

R10924 *10K_4

CHB_SA0 CHB_SA1 CHB_SA2

R10943 10K_4

10K_4

R10937 *10K_4

R10923 *10K_4

R10927 10K_4

M_B_ALERT#<3>

DDR3_DRAMRST#<3,12>

R10921 *1K_4

Close to PCH

M_B_BA#0<3> M_B_BA#1<3> M_B_BG#0<3> M_B_BG#1<3>

M_B_CS#0<3> M_B_CS#1<3> M_B_CKE0<3> M_B_CKE1<3>

M_B_CLK0<3> M_B_CLK0#<3> M_B_CLK1<3> M_B_CLK1#<3>

M_B_ODT0_DIMM<3> M_B_ODT1_DIMM<3>

CLK_SCLK<7,12,22,29> CLK_SDATA<7,12,22,29>

+1.2VSUS

For EMI RESERVE

+1.2VSUS

EC39 *120P/50V_4

EC48 *120P/50V_4

EC42 *120P/50V_4

EC49 120P/50V_4

EC46 *120P/50V_4

EC45 *120P/50V_4 EC 50 *0.1U/16V_4

A A

DDR_VTTREF

EC35 *120P/50V_4

EC40 *120P/50V_4

+1.2VSUS

EC47 *120P/50V_4

EC43 *120P/50V_4

EC38 *0.1U/16V_4

EC41 *0.1U/16V_4

EC37 *0.1U/16V_4EC44 *120P/50V_4

M_B_EVENT#

C1317 *0.1U/10V_4

M_B_EVENT#

CHB_SA0 CHB_SA1 CHB_SA2

R10931 240/F_4 R10936 240/F_4 R10933 240/F_4 R10939 240/F_4 R10941 240/F_4 R10922 240/F_4 R10942 240/F_4 R10925 240/F_4

+1.2VSUS

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

TP158 TP157

M_B_CB0

M_B_CB1 M_B_CB2 M_B_CB3

M_B_CB4

M_B_CB5 M_B_CB6 M_B_CB7

1uF/10uF 4pcs on each side of connector

+1.2VSUS DDR_VTTREF

P/N and F/P

JDIM2A

144

133

132

131

128

126

127

122

125

121

146

A10/AP

120

A11

119

A12

158

A13

151

A14/WE#

156

A15/CAS#

152

A16/RAS#

162

S2#/C0

165

S3#/C1

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

150

BA0

145

BA1

115

BG0

113

BG1

149

S0#

157

S1#

109

CKE0

110

CKE1

137

CK0

139

CK0#

138

CK1

140

CK1#

155

ODT0

161

ODT1

253

SCL

254

SDA

256

SA0

260

SA1

166

SA2

CB0

CB1

101

CB2

105

CB3

CB4

CB5

100

CB6

104

CB7

DM0

DM1

DM2

DM3

178

DM4

199

DM5

220

DM6

241

DM7

DM8

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

174

DQ32

173

DQ33

187

DQ34

186

DQ35

170

DQ36

169

DQ37

183

DQ38

182

DQ39

195

DQ40

194

DQ41

207

DQ42

208

DQ43

191

DQ44

190

DQ45

203

DQ46

204

DQ47

216

DQ48

(260P)

215

DDR4 SODIMM 260 PIN

DQ49

228

DQ50

229

DQ51

211

DQ52

212

DQ53

224

DQ54

225

DQ55

237

DQ56

236

DQ57

249

DQ58

250

DQ59

232

DQ60

233

DQ61

245

DQ62

246

DQ63

DQS0

DQS1

DQS2

DQS3

179

DQS4

200

DQS5

221

DQS6

242

DQS7

DQS8

DQS#0

DQS#1

DQS#2

DQS#3

177

DQS#4

198

DQS#5

219

DQS#6

240

DQS#7

DQS#8

Place these Caps near So-Dimm0.

C1332 1U/6.3V_4

C1325 1U/6.3V_4

C1309 1U/6.3V_4

C1318 1U/6.3V_4

C1314 1U/6.3V_4

C1336 1U/6.3V_4

C1335 1U/6.3V_4

C1330 10U/6.3V_6

C1312 10U/6.3V_6

C1321 10U/6.3V_6

C1331 10U/6.3V_6

C1328 10U/6.3V_6

C1334 10U/6.3V_6

C1313 10U/6.3V_6

C1308 10U/6.3V_6

VREF_C A_DIM M1

+2.5V_SUS

+3V

M_B_DQ1 M_B_DQ4 M_B_DQ7 M_B_DQ3 M_B_DQ0 M_B_DQ5 M_B_DQ2 M_B_DQ6 M_B_DQ13 M_B_DQ9 M_B_DQ14 M_B_DQ15 M_B_DQ12 M_B_DQ8 M_B_DQ11 M_B_DQ10 M_B_DQ21 M_B_DQ17 M_B_DQ19 M_B_DQ22 M_B_DQ20 M_B_DQ16 M_B_DQ18 M_B_DQ23 M_B_DQ28 M_B_DQ25 M_B_DQ26 M_B_DQ31 M_B_DQ29 M_B_DQ24 M_B_DQ30 M_B_DQ27 M_B_DQ32 M_B_DQ36 M_B_DQ39 M_B_DQ35 M_B_DQ33 M_B_DQ37 M_B_DQ38 M_B_DQ34 M_B_DQ45 M_B_DQ40 M_B_DQ42 M_B_DQ47 M_B_DQ44 M_B_DQ41 M_B_DQ43 M_B_DQ46 M_B_DQ53 M_B_DQ49 M_B_DQ54 M_B_DQ55 M_B_DQ48 M_B_DQ52 M_B_DQ51 M_B_DQ50 M_B_DQ61 M_B_DQ60 M_B_DQ59 M_B_DQ62 M_B_DQ57 M_B_DQ56 M_B_DQ58 M_B_DQ63

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS8

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS#8

C1315 1U/6.3V_4

C1311 1U/6.3V_4EC36 *120P/50V_4

C1310 1U/6.3V_4

C1319 1U/6.3V_4

C1333 1U/6.3V_4C1337 1U/6.3V_4

C1323 0.1U/16V_4

C1327 10U/6.3V_6

C1320 0.1U/16V_4

C1324 10U/6.3V_6

C1326 0.1U/16V_4

C1316 10U/6.3V_6

M_B_DQ[63:0] <3>

0-7

8-15

16-23

24-31

32-39

40-47

48-55

56-63

M_B_DQS[7:0] <3>

M_B_DQS#[7:0] <3>

+VREFDQ_SB_M3

+1.2VSUS

R10926

240/F_4

M_B_DQS8

+1.2VSUS

R10929

240/F_4

M_B_DQS#8

VREF DQ1 M1 Solution

+VREFDQ_SB_M3 VREF _CA_D IMM1

R10932 2/F_6

C1329

0.022U/25V_4

2 1

R10930

24.9/F_4

2250mA

+1.2VSUS

R10934 1K/F_4

R10938 1K/F_4

JDIM2B

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

141

VDD11

142

VDD12

147

VDD13

148

VDD14

153

VDD15

154

VDD16

159

VDD17

160

VDD18

163

VDD19

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

103

VSS25

107

VSS26

167

VSS27

171

VSS28

175

VSS29

181

VSS30

185

VSS31

189

VSS32

193

VSS33

197

VSS34

201

VSS35

205

VSS36

209

VSS37

213

VSS38

217

VSS39

223

VSS40

227

VSS41

231

VSS42

235

VSS43

239

VSS44

243

VSS45

247

VSS46

251

VSS47

VDDSPD

VPP1 VPP2

VTT

VREF_C A

VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68

(260P)

DDR4 SODIMM 260 PIN

VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94

GND GND

+1.2VSUS <3,5,12,36> +3V <2,4,6,7,8,9,12,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42> +2.5V_SUS <12,36> DDR_VTTREF <12,36>

+VDDQ <12,36> +VREFDQ_SB_M3 <3>

R10935*0_4

+VDDQ

255

257 259

258

164

VREF_C A_DIM M1

2 6 10 14 18 22 26 30 36 40 44 48 52 56 60 64 68 72 78 82 86 90 94 98 102 106 168 172 176 180 184 188 192 196 202 206 210 214 218 222 226 230 234 238 244 248 252

261 262

R11174 *0_4

C1322 10U/6.3V_6

C1338 0.1U/10V_4

0.5A

600mA

R11134 *short_4

+2.5V_SUS

DDR_VTTREF

+2.5V

+3V

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

PROJECT :

DDR4 DIMM-RVS(5.2H) CHB

ZAA

13 48

Dr-Bios.com

N16S-GT1-KA-A2 GM107-710-KA-A2 AJ0N16S0T22 B/S PN

U3002A

(;<*+'>!!BC%?%77,,@#

+1.05V_GFX

To be placed no fur ther from the GPU than bewteen the PS and GPU

C4000 EV@22U/6.3V_6 C4001 EV@22U/6.3V_6 C4002 EV@22U/6.3V_6

A A

B B

C C

D D

C4003 EV@22U/6.3V_6 C4004 EV@10U/6.3V_6 C4005 EV@10U/6.3V_6 C4006 EV@10U/6.3V_6 C4007 EV@10U/6.3V_6

PLACE NEAR BALLS

C4008 EV@1U/6.3V_4 C4009 EV@1U/6.3V_4 C4010 EV@1U/6.3V_4 C4011 EV@1U/6.3V_4

PLACE UNDER BGA

C4012 EV@4.7U/6.3V_4 C4014 EV@4.7U/6.3V_4

PLACE CLOSE TO BGA

C4026 EV@4.7U/6.3V_4 C4027 EV@1U/6.3V_4

C4028 EV@0.1u/16V_4 C4029 *EV@0.1U/16V_4 C4031 *EV@0.1U/16V_4

PLACE CLOSE TO GPU BALL S

+3V_GFX +3V_MAIN

>!!77%?%A8@#

PLACE CLOSE TO BGA

C4032 EV@4.7U/6.3V_4 C4033 EV@1U/6.3V_4

PLACE CLOSE TO GPU BALL S

C4034 EV@0.1u/16V_4

C4035 EV@0.1u/16V_4

AG19 AG21 AG22 AG24 AH21 AH25

AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27

AJ27 AK27 AL27 AM28 AN28

AC6

AJ28

AL11

AJ4 AJ5

C15 D19 D20 D23 D26 H31

V32

Y1 Y2

Y3 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8

SP@N16P-GT

PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24

3V3_AON_1 3V3_AON_2 3V3_MAIN_1 3V3_MAIN_2

[PEG Interface]

PEX_RX0

PEX_RX0_N

PEX_RX1

PEX_RX1_N

PEX_RX2

PEX_RX2_N

PEX_RX3

PEX_RX3_N

PEX_RX4

PEX_RX4_N

PEX_RX5

PEX_RX5_N

PEX_RX6

PEX_RX6_N

PEX_RX7

PEX_RX7_N

PEX_RX8

PEX_RX8_N

PEX_RX9

PEX_RX9_N

PEX_RX10

PEX_RX10_N

PEX_RX11

PEX_RX11_N

PEX_RX12

PEX_RX12_N

PEX_RX13

PEX_RX13_N

PEX_RX14

PEX_RX14_N

PEX_RX15

PEX_RX15_N

PEX_TX0

PEX_TX0_N

PEX_TX1

PEX_TX1_N

PEX_TX2

PEX_TX2_N

PEX_TX3

PEX_TX3_N

PEX_TX4

PEX_TX4_N

PEX_TX5

PEX_TX5_N

PEX_TX6

PEX_TX6_N

PEX_TX7

PEX_TX7_N

PEX_TX8

PEX_TX8_N

PEX_TX9

PEX_TX9_N

PEX_TX10

PEX_TX10_N

PEX_TX11

PEX_TX11_N

PEX_TX12

PEX_TX12_N

PEX_TX13

PEX_TX13_N

PEX_TX14

PEX_TX14_N

PEX_TX15

PEX_TX15_N

PEX_REFCLK

PEX_REFCLK_N

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT_N

PEX_RST_N

PEX_CLKREQ_N

PEX_TERMP

TESTMODE

PEX_PLLVDD

PEX_PLL_HVDD PEX_SVDD_3V3

3.3V_AUX_NC

VDD_SENSE

GND_SENSE

AN12 AM12 AN14 AM14 AP14 AP15 AN15 AM15 AN17 AM17 AP17 AP18 AN18 AM18 AN20 AM20 AP20 AP21 AN21 AM21 AN23 AM23 AP23 AP24 AN24 AM24 AN26 AM26 AP26 AP27 AN27 AM27

AK14

PEG_RXP0_C

AJ14

PEG_RXN0_C

AH14

PEG_RXP1_C

AG14

PEG_RXN1_C

AK15

PEG_RXP2_C

AJ15

PEG_RXN2_C

AL16

PEG_RXP3_C

AK16

PEG_RXN3_C

AK17 AJ17 AH17 AG17 AK18 AJ18 AL19 AK19 AK20 AJ20 AH20 AG20 AK21 AJ21 AL22 AK22 AK23 AJ23 AH23 AG23 AK24 AJ24 AL25 AK25

AL13 AK13

AJ26

PEX_TSTCLK

AK26

PEX_TSTCLK#

AJ11

AJ12

PEGX_RST#

AK12

PEX_CLKREQ#

AP29

PEX_TERMP

AK11

TESTMODE

AG26

PEX_PLLVDD

AH12 AG12

(;<*=>!!*7>7%?%65,@#

3.3V_AUX

PEG_TX0 <6> PEG_TX#0 <6> PEG_TX1 <6> PEG_TX#1 <6> PEG_TX2 <6> PEG_TX#2 <6> PEG_TX3 <6> PEG_TX#3 <6>

C4015 EV@0.22U/10V_4 C4016 EV@0.22U/10V_4 C4017 EV@0.22U/10V_4 C4018 EV@0.22U/10V_4 C4020 EV@0.22U/10V_4 C4021 EV@0.22U/10V_4 C4022 EV@0.22U/10V_4 C4023 EV@0.22U/10V_4

CLK_PCIE_VGA <6> CLK_PCIE_VGA# <6>

R4006 *EV@200/F_4

R4008 EV@10K_4

R4009 EV@2.49K/F _4

R4011 EV@10K_4

(;<*(22>!!%?%58,@#

C4038EV@0.1u/16V_4 C4039EV@4.7U/6.3V_4

PLACE NEAR BGA

C4041EV@4.7U/6.3V_4

TP4000

VGA_VCCSENSE <41>

VGA_VSSSENSE <41>

PEGX_RST# <17>

+3V_GFX

N16S-GT1-KB-A2 GM107-710-KB-A2 AJSR2JK8T02 N16S-GTR-B-A2 GM108-770-A2 AJ0N16S0T24

3V MAIN POWER

3/11 GC6 timing issue from 200K change to 100K

R4000 EV@10K_4

R4002 EV@100K_4

Q4001 EV@2N7002K

+3V

SYS_PEX_RST_MON#<17>

C4030

U4001

3 5

GC6@74AHC1G09GW

GC6 FBVDDQ_EN

GC6_FB_EN<4,17>

GPU_PWR_GD<41>

PEG_RX0 <6> PEG_RX#0 <6> PEG_RX1 <6> PEG_RX#1 <6> PEG_RX2 <6> PEG_RX#2 <6> PEG_RX3 <6> PEG_RX#3 <6>

+3V_GFX

PEX_CLKREQ#

R4010 *short_6

C4036 EV@4.7U/6.3V_4

C4037 EV@1U/6.3V_4

C4040 EV@0.1u/16V_4

+3V_MAIN

Q4002

EV@2N7002KW_1 15MA

GC6:+3V_MAIN

GC6 Power control

+3V_MAIN_EN<17>

GC6 PEGX_RST#

DGPU_HOLD_RST#<4>

+1.05V_GFX

B2A

PLACE NEAR GPU

PLACE UNDER GPU BALLS

CLK_PEGA_REQ# <6>

+3V_GFX

R4001 EV@10K_4

PLTRST#<8,25,27,28,31>

EV@1000p/50V_4

+1.05V_GFX <15,16,42> +3V_GFX <16,17,31,42> +3V_MAIN <15,16,17> +3V <2,4,6,7,8,9,12,13,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>

+3V_GFX+3V_GFX

C4013

EV@0.022U/25V_4

C4019

EV@0.022U/25V_4

C4024 GC6@0.1U/16V_4

GPU_PEX_RST_HOLD#<17>

R11108 *short_4

RST_MON#

R4007

RST_MON# PEGX_RST#

GC6_FB_EN

GC6@BAT54CW_200MA

60mil

Q4000 EV@AO3413

60mil

R4003

*0_8

+3V_MAIN

N16V stuff not support GC6 2.0.

+3V

C4025 GC6@0.1U/16V_4

*NGC6@0_4

D4000

R4012 GC6@1M_4

Size Document Number Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

3 5

U4002 GC6@TC7SH08FU(F)

FBVDDQ_EN <42>

C3A

Quanta Computer Inc.

PROJECT :

N16 - 1/5 (PCIE)

+3V_GFX

ZAA

R4004 *GC6@10K_4

PEGX_RST#

R4005 GC6@100K_4

14 48

Dr-Bios.com

FBA_CMD0<19> FBA_CMD1<19> FBA_CMD2<19> FBA_CMD3<19> FBA_CMD4<19>

FBA_CMD5<19>

FBA_CMD6<19> FBA_CMD7<19>

A A

B B

FBA_CMD8<19> FBA_CMD9<19> FBA_CMD10<19> FBA_CMD11<19> FBA_CMD12<19> FBA_CMD13<19> FBA_CMD14<19> FBA_CMD15<19> FBA_CMD16<19> FBA_CMD17<19>

FBA_CMD18<19>

FBA_CMD19<19> FBA_CMD20<19> FBA_CMD21<19> FBA_CMD22<19> FBA_CMD23<19> FBA_CMD24<19> FBA_CMD25<19> FBA_CMD26<19> FBA_CMD27<19> FBA_CMD28<19> FBA_CMD29<19> FBA_CMD30<19> FBA_CMD31<19>

FBA_DBI[7:0]<19>

FBA_EDC[7:0]<19>

FBA_CMD0 FBA_CMD1

FBA_CMD2 FBA_CMD3

FBA_CMD4

FBA_CMD5

FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17

FBA_CMD18 FBA_CMD19

FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_DBI0 FBA_DBI1 FBA_DBI2 FBA_DBI3 FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

GDDR5 NO USE

+1.35V_GFX

PLACE CLOSE TO GPU BALLS

C C

D D

C4100 EV@1U/6.3V_4 C4101 EV@1U/6.3V_4 C4102 EV@1U/6.3V_4 C4103 EV@1U/6.3V_4

C4104 EV@0.1U/16V_4 C4105 EV@0.1U/16V_4 C4106 EV@0.1U/16V_4 C4107 EV@0.1U/16V_4

PLACE CLOSE TO BGA

C4108 EV@4.7U/6.3V_4 C4109 EV@4.7U/6.3V_4 C4110 EV@4.7U/6.3V_4 C4113 EV@4.7U/6.3V_4 C4111 EV@10U/6.3V_6 C4115 EV@10U/6.3V_4

C4117 *EV@10U/6.3V_4 C4815 *EV@10U/6.3V_4

C4119 EV@22U/6.3V_6

B2A

U30

U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33

Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33

Y28

Y29

W31

Y30 AA34

Y31

Y34

Y33

V31

P30

M32 AD31

AL29

AM32

AF34

M31

G31

E33

M33 AE31 AK30 AN33

AF33

M30

H30

E34

M34

AF30 AK31 AM34

AF32

AA27 AA30 AB27 AB33 AC27 AD27 AE27

AF27 AG27

B13 B19 E13 E19 H10 H11 H12 H13 H14 H18 H19 H20 H21 H22 H23 H24

M27 N27 P27 R27

Y27

B16 E16 H15 H16

V27 W27 W30 W33

T31

F31 F34

L27

T27 T30 T33

U3002B SP@N16P-GT

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_12 FBVDDQ_13 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29

FBVDDQ_30

FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_44

FBVDDQ_AON_1 FBVDDQ_AON_2 FBVDDQ_AON_3 FBVDDQ_AON_4 FBVDDQ_AON_5 FBVDDQ_AON_6 FBVDDQ_AON_7 FBVDDQ_AON_8

[MEMORY I/F A]

FBA_CLK0_N

FBA_CLK1_N

FBA_WCK01_N

FBA_WCK23_N

FBA_WCK45_N

FBA_WCK67_N

FB_DLL_AVDD

FBA_PLL_AVDD

FB_VDDQ_SENSE

FB_GND_SENSE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CALTERM_GND

FBA_D00 FBA_D01 FBA_D02 FBA_D03 FBA_D04 FBA_D05 FBA_D06 FBA_D07 FBA_D08 FBA_D09 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_CLK0

FBA_CLK1

FBA_CMD32 FBA_CMD33 FBA_CMD34 FBA_CMD35

FB_VREF

FBA_WCK01

FBA_WCK23

FBA_WCK45

FBA_WCK67

FB_CLAMP

NC NC NC NC NC NC NC NC

L28

VMA_DQ0

M29

VMA_DQ1

L29

VMA_DQ2

M28

VMA_DQ3

N31

VMA_DQ4

P29

VMA_DQ5

R29

VMA_DQ6

P28

VMA_DQ7

J28

VMA_DQ8

H29

VMA_DQ9

J29

VMA_DQ10

H28

VMA_DQ11

G29

VMA_DQ12

E31

VMA_DQ13

E32

VMA_DQ14

F30

VMA_DQ15

C34

VMA_DQ16

D32

VMA_DQ17

B33

VMA_DQ18

C33

VMA_DQ19

F33

VMA_DQ20

F32

VMA_DQ21

H33

VMA_DQ22

H32

VMA_DQ23

P34

VMA_DQ24

P32

VMA_DQ25

P31

VMA_DQ26

P33

VMA_DQ27

L31

VMA_DQ28

L34

VMA_DQ29

L32

VMA_DQ30

L33

VMA_DQ31

AG28

VMA_DQ32

AF29

VMA_DQ33

AG29

VMA_DQ34

AF28

VMA_DQ35

AD30

VMA_DQ36

AD29

VMA_DQ37

AC29

VMA_DQ38

AD28

VMA_DQ39

AJ29

VMA_DQ40

AK29

VMA_DQ41

AJ30

VMA_DQ42

AK28

VMA_DQ43

AM29

VMA_DQ44

AM31

VMA_DQ45

AN29

VMA_DQ46

AM30

VMA_DQ47

AN31

VMA_DQ48

AN32

VMA_DQ49

AP30

VMA_DQ50

AP32

VMA_DQ51

AM33

VMA_DQ52

AL31

VMA_DQ53

AK33

VMA_DQ54

AK32

VMA_DQ55

AD34

VMA_DQ56

AD32

VMA_DQ57

AC30

VMA_DQ58

AD33

VMA_DQ59

AF31

VMA_DQ60

AG34

VMA_DQ61

AG32

VMA_DQ62

AG33

VMA_DQ63

R30 R31 AB31 AC31

R28

FBA_DEBUG0_K

AC28

FBA_DEBUG1_K

R32

FBA_DEBUG0

AC32

FBA_DEBUG1

H26

K31 L30 H34 J34 AG30 AG31 AJ34 AK34

J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33

PS_FB_CLAMP

K27

FB_DLLAVDD

U27

FB_PLLAVDD

FBVDDQ_SENSE

FB_GND_SENSE

J27

FB_CAL_PD_VDDQ

H27

FB_CAL_PU_GND

H25

FB_CAL_TERM_GND

VMA_DQ0 <19> VMA_DQ1 <19> VMA_DQ2 <19> VMA_DQ3 <19> VMA_DQ4 <19> VMA_DQ5 <19> VMA_DQ6 <19> VMA_DQ7 <19> VMA_DQ8 <19> VMA_DQ9 <19> VMA_DQ10 <19> VMA_DQ11 <19> VMA_DQ12 <19> VMA_DQ13 <19> VMA_DQ14 <19> VMA_DQ15 <19> VMA_DQ16 <19> VMA_DQ17 <19> VMA_DQ18 <19> VMA_DQ19 <19> VMA_DQ20 <19> VMA_DQ21 <19> VMA_DQ22 <19> VMA_DQ23 <19>

VMA_DQ24 <19>

VMA_DQ25 <19>

VMA_DQ26 <19>

VMA_DQ27 <19> VMA_DQ28 <19> VMA_DQ29 <19> VMA_DQ30 <19> VMA_DQ31 <19> VMA_DQ32 <19> VMA_DQ33 <19> VMA_DQ34 <19> VMA_DQ35 <19> VMA_DQ36 <19> VMA_DQ37 <19> VMA_DQ38 <19> VMA_DQ39 <19> VMA_DQ40 <19> VMA_DQ41 <19> VMA_DQ42 <19> VMA_DQ43 <19> VMA_DQ44 <19> VMA_DQ45 <19> VMA_DQ46 <19> VMA_DQ47 <19> VMA_DQ48 <19> VMA_DQ49 <19> VMA_DQ50 <19>

VMA_DQ51 <19>

VMA_DQ52 <19> VMA_DQ53 <19> VMA_DQ54 <19> VMA_DQ55 <19> VMA_DQ56 <19> VMA_DQ57 <19> VMA_DQ58 <19> VMA_DQ59 <19> VMA_DQ60 <19> VMA_DQ61 <19> VMA_DQ62 <19> VMA_DQ63 <19>

VMA_CLK0 <19> VMA_CLK0# <19> VMA_CLK1 <19> VMA_CLK1# <19>

R4103*EV@60.4/F_4 R4105*EV@60.4/F_4

VMA_WCK01 <19> VMA_WCK01# <19> VMA_WCK23 <19> VMA_WCK23# <19> VMA_WCK45 <19> VMA_WCK45# <19> VMA_WCK67 <19> VMA_WCK67# <19>

R4114 EV@10K_4

DE)*(22#>!!%?%96@#

+1.35V_GFX

R4115 *EV@0_4

R4116 *EV@0_4

R4117 EV@40.2/F_4

R4118 EV@42.2/F_4

R4119 EV@60.4/F_4

PLACE CLOSE TO GPU BALLS

TP4106 TP4107

+1.35V_GFX

C4114 EV@0.1U/16V_4

C4116 EV@0.1U/16V_4

C4118 EV@10U/6.3V_4 C4812 EV@10U/6.3V_4

+1.35V_GFX

FBB_CMD0<20> FBB_CMD1<20> FBB_CMD2<20> FBB_CMD3<20> FBB_CMD4<20>

FBB_CMD5<20>

FBB_CMD6<20> FBB_CMD7<20> FBB_CMD8<20> FBB_CMD9<20> FBB_CMD10<20> FBB_CMD11<20> FBB_CMD12<20> FBB_CMD13<20> FBB_CMD14<20> FBB_CMD15<20> FBB_CMD16<20> FBB_CMD17<20>

FBB_CMD18<20>

FBB_CMD19<20> FBB_CMD20<20> FBB_CMD21<20> FBB_CMD22<20> FBB_CMD23<20> FBB_CMD24<20> FBB_CMD25<20> FBB_CMD26<20> FBB_CMD27<20> FBB_CMD28<20> FBB_CMD29<20> FBB_CMD30<20> FBB_CMD31<20>

FBB_DBI[7:0]<20>

FBB_EDC[7:0]<20>

GDDR5 NO USE

C4719 EV@0.1U/16V_4

C4721 EV@22U/6.3V_6

L4206*SP@HCB1005K F-330T30

L4100SP@HCB1005KF-330T30

B2A

U3002C SP@N16P-GT

D13 E14

F14 A12 B12 C14 B14 G15

F15 E15 D15 A14 D14 A15 B15 C17 D18 E18

F18 A20 B20 C18 B18 G18 G17

F17 D16 A18 D17 A17 B17 E17

E11

E3 A3

C9 F23 F27

C30 A24

D10

E23 E28 B30 A23

D22 D28 A30 B23

FBB_CMD0 FBB_CMD1 FBC_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBC_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBC_CMD30 FBC_CMD31

FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7

FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7

FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7

L4207EV@HCB1005KF-330T30

+3V_MAIN

+1.05V_GFX

FBB_CMD0 FBB_CMD1

FBB_CMD2 FBB_CMD3

FBB_CMD4

FBB_CMD5

FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17

FBB_CMD18 FBB_CMD19

FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

FBB_DBI0 FBB_DBI1 FBB_DBI2 FBB_DBI3 FBB_DBI4 FBB_DBI5 FBB_DBI6 FBB_DBI7

FBB_EDC0 FBB_EDC1 FBB_EDC2 FBB_EDC3 FBB_EDC4 FBB_EDC5 FBB_EDC6 FBB_EDC7

+1.05V_GFX

E3F%59;

E3F%59(

C574 close to K27 (under GPU)

C575 close to U27 (under GPU) C576 near to GPU

+1.35V_GFX <19,20,42> +1.05V_GFX <14,16,42>

MEMORY I/F C

FBC_D00 FBC_D01 FBC_D02 FBC_D03 FBC_D04 FBC_D05 FBC_D06 FBC_D07 FBC_D08 FBC_D09 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

FBB_CMD32 FBB_CMD33 FBB_CMD34 FBB_CMD35

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_PLL_AVDD

VMB_DQ0

VMB_DQ1

VMB_DQ2

VMB_DQ3

F11

VMB_DQ4

G11

VMB_DQ5

F12

VMB_DQ6

G12

VMB_DQ7

VMB_DQ8

VMB_DQ9

VMB_DQ10

VMB_DQ11

VMB_DQ12

VMB_DQ13

VMB_DQ14

VMB_DQ15

VMB_DQ16

VMB_DQ17

VMB_DQ18

VMB_DQ19

VMB_DQ20

VMB_DQ21

VMB_DQ22

VMB_DQ23

A11

VMB_DQ24

C11

VMB_DQ25

D11

VMB_DQ26

B11

VMB_DQ27

VMB_DQ28

VMB_DQ29

VMB_DQ30

VMB_DQ31

F24

VMB_DQ32

G23

VMB_DQ33

E24

VMB_DQ34

G24

VMB_DQ35

D21

VMB_DQ36

E21

VMB_DQ37

G21

VMB_DQ38

F21

VMB_DQ39

G27

VMB_DQ40

D27

VMB_DQ41

G26

VMB_DQ42

E27

VMB_DQ43

E29

VMB_DQ44

F29

VMB_DQ45

E30

VMB_DQ46

D30

VMB_DQ47

A32

VMB_DQ48

C31

VMB_DQ49

C32

VMB_DQ50

B32

VMB_DQ51

D29

VMB_DQ52

A29

VMB_DQ53

C29

VMB_DQ54

B29

VMB_DQ55

B21

VMB_DQ56

C23

VMB_DQ57

A21

VMB_DQ58

C21

VMB_DQ59

B24

VMB_DQ60

C24

VMB_DQ61

B26

VMB_DQ62

C26

VMB_DQ63

D12 E12 E20 F20

G14

FBB_DEBUG0_K

G20

FBB_DEBUG1_K

C12

FBB_DEBUG0

C20

FBB_DEBUG1

F8 E8 A5 A6 D24 D25 B27 C27

F26

E26

A26

A27

H17

FB_PLLAVDD

Size Document Number Rev

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

Date: Sheet of

Friday, February 05, 2016

VMB_DQ0 <20> VMB_DQ1 <20> VMB_DQ2 <20> VMB_DQ3 <20> VMB_DQ4 <20> VMB_DQ5 <20> VMB_DQ6 <20> VMB_DQ7 <20> VMB_DQ8 <20> VMB_DQ9 <20> VMB_DQ10 <20> VMB_DQ11 <20> VMB_DQ12 <20> VMB_DQ13 <20> VMB_DQ14 <20> VMB_DQ15 <20> VMB_DQ16 <20> VMB_DQ17 <20> VMB_DQ18 <20> VMB_DQ19 <20> VMB_DQ20 <20> VMB_DQ21 <20> VMB_DQ22 <20> VMB_DQ23 <20>

VMB_DQ24 <20>

VMB_DQ25 <20>

VMB_DQ26 <20>

VMB_DQ27 <20> VMB_DQ28 <20> VMB_DQ29 <20> VMB_DQ30 <20> VMB_DQ31 <20> VMB_DQ32 <20> VMB_DQ33 <20> VMB_DQ34 <20> VMB_DQ35 <20> VMB_DQ36 <20> VMB_DQ37 <20> VMB_DQ38 <20> VMB_DQ39 <20> VMB_DQ40 <20> VMB_DQ41 <20> VMB_DQ42 <20> VMB_DQ43 <20> VMB_DQ44 <20> VMB_DQ45 <20> VMB_DQ46 <20> VMB_DQ47 <20> VMB_DQ48 <20> VMB_DQ49 <20> VMB_DQ50 <20>

VMB_DQ51 <20>

VMB_DQ52 <20> VMB_DQ53 <20> VMB_DQ54 <20> VMB_DQ55 <20> VMB_DQ56 <20> VMB_DQ57 <20> VMB_DQ58 <20> VMB_DQ59 <20> VMB_DQ60 <20> VMB_DQ61 <20> VMB_DQ62 <20> VMB_DQ63 <20>

VMB_CLK0 <20> VMB_CLK0# <20> VMB_CLK1 <20> VMB_CLK1# <20>

R4100 *EV@60.4/F_4 R4102 *EV@60.4/F_4

VMB_WCK01 <20> VMB_WCK01# <20> VMB_WCK23 <20> VMB_WCK23# <20> VMB_WCK45 <20> VMB_WCK45# <20> VMB_WCK67 <20> VMB_WCK67# <20>

C262 close to H27 (under GPU)

B2A

C4112 EV@0.1U/16V_4

Quanta Computer Inc.

PROJECT :

N16 - 2/5 (Memory)

ZAA

15 48

TP4104 TP4105

+1.35V_GFX

+ 33 hidden pages

Acer Aspire_E5_575 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual