Acer Aspire E5-573G Schematic
5
ZRT/ZRTA_GDDR3 BWD ULT SYSTEM BLOCK DIAGRAM
DDR3L-SODIMM CHA
D D
DDR3L-SODIMM CHB
SATA - HDD
SA
Cardreader
CONN. 2in 1
RTS5170
(cardreader)
P27
CCD(Camera)
C C
Touch Screen
Bl
ue Toot h
I/O board
I/O Board Conn.USB2 IO*1
TA ODD
P14
P27
P27
P27
P22
P22
P2
4
P27
4
Du
al Channel DDR III
1066/1333/1600 MHZ
SATA0
SAT
USB2-7
USB2-6
USB2-5
USB2-4
USB2-2
P8 RTC
BA
TTERY
Azalia
A1
DWELL ULT 15W
BRO
MCP 1 168pins
IMC
D
40 mm X 24 mm
SATA
In
tegrate d PCH
USB2.0
IHDA
C+GT3
3
2
1
BOM
15@ : For 15W CPU
28@ : For 28W CPU
6515@ : For 6515 stuff
AC@ : For IOAC
DM@ : Dual MIC
DR@ : For Dual Ran k
EV@ : Optimus
GM@ :N16V-GM /WO GC6
GS@ : G sensor
GT@ :N16S-GT /GC6
IV@ : iG PU
KBL@ : Keyboard backlight
NAC@ : Non IOAC
NGS@ : Non G se nsor
NTPM@ : Non TPM
S28@ : 28W Change BOM
SM@ : Single MIC
SP@ : Special
SR@ : Single Rank
TPM@ : TPM
TPN_N@ : For TPM 2.0
TPN_S@ : For TPM 1.2
RJ45
P25
TAL 27MHz
X'
PCIE-4
PCIE-3
VRAM
DDR3
eD
P Conn.
VG
A Conn.
HDMI Conn.
P20,P21
P2
P2
P24
USB3 Port*2
MB side
NG
FF CARD
WLAN+BT
RTL8111H
10/100/1G
3
3
P3
0
P28
P25
X'TAL 25MHz
U
GP
TAL
SPI ROM
8M
N16S-GT
N16V-GM
P8
P16~P19
IT
E6515
P22
PCIE-5
PC
I-E x4
TX/RX
CLKP15
EDP
eDP
DDI2
DP
DDI1
USB3-1,-2
USB3.0/2.0
P2~P13
LPC
CLK
PCI-E x1
CL
SPI
B2-0,-1
US
X'
32.768KHz
X'TAL 24MHz
K
ALC2 55
AUDIO COD EC
Universal HP
P28 P28
Speaker*2
P2
8
BACKLIGHT
(OPTION)
K/B Con.
P29
9
P2
B B
D-MIC
D-MIC
A A
P2
P2
Int. D- MIC
8
8
EC
IT8987
Touch PAD
TP
M(option)
7
P3
1
Fan Driver
an signal)
(F
P29
P29
P2
BQ
24737RG RR
tery Charger
Ba
TPS51225RUKR
+3V/+5V
TPS51624RSM
VCCIN
+
TPS51211DSCR
1.05V_S5/+1.05V
+
TP
1.35V_SUS
+
P31
TPS54318RTER
+1.5V
P32
UP1658RQKF
VGPU_CORE
+
3
P3
PS51211DSCR
1.5V_GFX/1.05V_GFX/3V_GFX
+
P34
S51216RUKR
Thermal Protection
5
P3
Di
P36
7
P3
P38
scharger
6
P3
https://t.me/schematicslaptop
https://t.me/biosarchive
ze Document Number Rev
ze Document Number Rev
ze Document Number Rev
Si
Si
Si
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Qu
Qu
Qu
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Bl
Bl
Bl
ock Diagram
ock Diagram
ock Diagram
1
T/ZRTA
T/ZRTA
T/ZRTA
ZR
ZR
ZR
14
14
14
of
of
of
4Wednesday, February 11, 2015
4Wednesday, February 11, 2015
4Wednesday, February 11, 2015
3A
3A
3A
5
4
3
2
1
Haswell ULT (DISPLAY,eDP)
U37A
HSW_ULT_DDR3L
D D
HDMI
CRT
ITE FAE suggest CAP
should be at PCH side.
C C
B B
INT_HDMITX0N[24]
INT_HDMITX0P[24]
INT_HDMITX1N[24]
INT_HDMITX1P[24]
INT_HDMITX2N[24]
INT_HDMITX2P[24]
INT_HDMICLK -[24]
INT_HDMICLK +[24]
CRT_TXN0[22]
CRT_TXP0[22]
CRT_TXN1[22]
CRT_TXP1[22]
PCH_BRIGHT[23]
PCH_BLON[23]
EDP_VDD_EN[23]
TP87
BOARD_ID4[10]
BOARD_ID1[10]
BOARD_ID2[10]
PCH_BRIGHT
PCH_BLON
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PME#
TPD_INT#_ D
DGPU_SELECT#
BOARD_ID4
BOARD_ID1
BOARD_ID2
C54
C55
B58
C58
B55
A55
A57
B57
C51
C50
C53
B54
C49
B50
A53
B53
AD4
B8
A9
C6
U6
P4
N4
N2
U7
L1
L3
R5
L4
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
U37I
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
+3V
GPIO55
+3V
GPIO52
+3V
GPIO54
+3V
GPIO51
+3V
GPIO53
eDP SIDEBAND
+3V
+3V
+3V
+3V
+3V_S5
PCIE
HSW_ULT_DDR3L
1 OF 19
9 OF 19
EDPDDI
DISPLAY
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
C45
B46
A47
B47
C47
C46
A49
B49
A45
B45
D20
A43
B9
C9
D9
D11
C5
B6
B5
A6
C8
A8
D6
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
CRT_CLK
CRT_DATA
CRT_AUXN
CRT_AUXP
R360
100K_4
EDP_TXN0 [23]
EDP_TXP0 [23]
EDP_TXN1 [23]
EDP_TXP1 [23]
EDP_TXN2 [23]
EDP_TXP2 [23]
EDP_TXN3 [23]
EDP_TXP3 [23]
EDP_AUXN [23]
EDP_AUXP [23]
R353 24.9/F_4
R705 *0_4
R706 *0_4
HDMI_DDCCLK_SW [24]
HDMI_DDCDATA_SW [24]
CRT_AUXN [22]
CRT_AUXP [22]
INT_HDMI_HP D [24]
CRT_HPD [22]
EDP_HPD [23]
R686
4.7K_4
PCH_BRIGHTDP_UTIL
eDP Panel
+VCCIOA_OUT
eDP_RCOMP
Trace length < 100 mils
Trace width = 20 mils
Trace spacing = 25 mils
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
DGPU_SELECT#
CRT_CLK
CRT_DATA
TPD_INT#_ D
CRT_AUXN
CRT_AUXP
R316 10K_4
R635 10K_4
R328 10K_4
R640 10K_4
R653 10K_4
R365 2.2K_4
R363 2.2K_4
R327 100K_4
+3V
+3V
R691 *100K_4
R692 *100K_4
+3V
2
TPD_INT#[29,31]
A A
5
3
Q23
2N7002K
1
4
TPD_INT#_ D
https://t.me/schematicslaptop
https://t.me/biosarchive
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Date: Sheet of
Date: Sheet of
2
PROJECT :
Haswell 3/5 (DDI/eDP)
Haswell 3/5 (DDI/eDP)
Haswell 3/5 (DDI/eDP)
ZRT/ZRTA
ZRT/ZRTA
ZRT/ZRTA
of
244
244
244
1
3A
3A
3A
5
4
3
2
1
Change Data and DQS to interleave.
Haswell ULT (DDR3L) Haswell Processor (DDR3)
U37C
AH63
M_A_DQ0[14]
M_A_DQ1[14]
M_A_DQ2[14]
M_A_DQ3[14]
M_A_DQ4[14]
D D
C C
B B
M_A_DQ5[14]
M_A_DQ6[14]
M_A_DQ7[14]
M_A_DQ8[14]
M_A_DQ9[14]
M_A_DQ10[14]
M_A_DQ11[14]
M_A_DQ12[14]
M_A_DQ13[14]
M_A_DQ14[14]
M_A_DQ15[14]
M_B_DQ0[15]
M_B_DQ1[15]
M_B_DQ2[15]
M_B_DQ3[15]
M_B_DQ4[15]
M_B_DQ5[15]
M_B_DQ6[15]
M_B_DQ7[15]
M_B_DQ8[15]
M_B_DQ9[15]
M_B_DQ10[15]
M_B_DQ11[15]
M_B_DQ12[15]
M_B_DQ13[15]
M_B_DQ14[15]
M_B_DQ15[15]
M_A_DQ16[14]
M_A_DQ17[14]
M_A_DQ18[14]
M_A_DQ19[14]
M_A_DQ20[14]
M_A_DQ21[14]
M_A_DQ22[14]
M_A_DQ23[14]
M_A_DQ24[14]
M_A_DQ25[14]
M_A_DQ26[14]
M_A_DQ27[14]
M_A_DQ28[14]
M_A_DQ29[14]
M_A_DQ30[14]
M_A_DQ31[14]
M_B_DQ16[15]
M_B_DQ17[15]
M_B_DQ18[15]
M_B_DQ19[15]
M_B_DQ20[15]
M_B_DQ21[15]
M_B_DQ22[15]
M_B_DQ23[15]
M_B_DQ24[15]
M_B_DQ25[15]
M_B_DQ26[15]
M_B_DQ27[15]
M_B_DQ28[15]
M_B_DQ29[15]
M_B_DQ30[15]
M_B_DQ31[15]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
SA_DQ0
AH62
SA_DQ1
AK63
SA_DQ2
AK62
SA_DQ3
AH61
SA_DQ4
AH60
SA_DQ5
AK61
SA_DQ6
AK60
SA_DQ7
AM63
SA_DQ8
AM62
SA_DQ9
AP63
SA_DQ10
AP62
SA_DQ11
AM61
SA_DQ12
AM60
SA_DQ13
AP61
SA_DQ14
AP60
SA_DQ15
AP58
SA_DQ16
AR58
SA_DQ17
AM57
SA_DQ18
AK57
SA_DQ19
AL58
SA_DQ20
AK58
SA_DQ21
AR57
SA_DQ22
AN57
SA_DQ23
AP55
SA_DQ24
AR55
SA_DQ25
AM54
SA_DQ26
AK54
SA_DQ27
AL55
SA_DQ28
AK55
SA_DQ29
AR54
SA_DQ30
AN54
SA_DQ31
AY58
SA_DQ32
AW58
SA_DQ33
AY56
SA_DQ34
AW56
SA_DQ35
AV58
SA_DQ36
AU58
SA_DQ37
AV56
SA_DQ38
AU56
SA_DQ39
AY54
SA_DQ40
AW54
SA_DQ41
AY52
SA_DQ42
AW52
SA_DQ43
AV54
SA_DQ44
AU54
SA_DQ45
AV52
SA_DQ46
AU52
SA_DQ47
AK40
SA_DQ48
AK42
SA_DQ49
AM43
SA_DQ50
AM45
SA_DQ51
AK45
SA_DQ52
AK43
SA_DQ53
AM40
SA_DQ54
AM42
SA_DQ55
AM46
SA_DQ56
AK46
SA_DQ57
AM49
SA_DQ58
AK49
SA_DQ59
AM48
SA_DQ60
AK48
SA_DQ61
AM51
SA_DQ62
AK51
SA_DQ63
HSW_ULT_ DDR3 L
DDR CHANNEL A
3 OF 19
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
AU43
AW43
AY42
AY43
AP33
AR32
AP32
AY34
AW34
AU34
AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
AP49
AR51
AP51
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DQS#0
M_A_DQS#1
M_B_DQS#0
M_B_DQS#1
M_A_DQS#2
M_A_DQS#3
M_B_DQS#2
M_B_DQS#3
M_A_DQS0
M_A_DQS1
M_B_DQS0
M_B_DQS1
M_A_DQS2
M_A_DQS3
M_B_DQS2
M_B_DQS3
+VREF_CA_CPU
+VREFDQ_SA_M3
+VREFDQ_SB_M3
M_A_CLK0# [14]
M_A_CLK0 [14]
M_A_CLK1# [14]
M_A_CLK1 [14]
M_A_CKE0 [14]
M_A_CKE1 [14]
M_A_CS#0 [14]
M_A_CS#1 [14]
TP26
M_A_RAS# [14]
M_A_WE# [14]
M_A_CAS# [14]
M_A_BS#0 [14]
M_A_BS#1 [14]
M_A_BS#2 [14]
M_A_A[15:0] [14]
M_A_DQS#0 [14]
M_A_DQS#1 [14]
M_B_DQS#0 [15]
M_B_DQS#1 [15]
M_A_DQS#2 [14]
M_A_DQS#3 [14]
M_B_DQS#2 [15]
M_B_DQS#3 [15]
M_A_DQS0 [14]
M_A_DQS1 [14]
M_B_DQS0 [15]
M_B_DQS1 [15]
M_A_DQS2 [14]
M_A_DQS3 [14]
M_B_DQS2 [15]
M_B_DQS3 [15]
U37D
AY31
M_A_DQ32[14]
M_A_DQ33[14]
M_A_DQ34[14]
M_A_DQ35[14]
M_A_DQ36[14]
M_A_DQ37[14]
M_A_DQ38[14]
M_A_DQ39[14]
M_A_DQ40[14]
M_A_DQ41[14]
M_A_DQ42[14]
M_A_DQ43[14]
M_A_DQ44[14]
M_A_DQ45[14]
M_A_DQ46[14]
M_A_DQ47[14]
M_B_DQ32[15]
M_B_DQ33[15]
M_B_DQ34[15]
M_B_DQ35[15]
M_B_DQ36[15]
M_B_DQ37[15]
M_B_DQ38[15]
M_B_DQ39[15]
M_B_DQ40[15]
M_B_DQ41[15]
M_B_DQ42[15]
M_B_DQ43[15]
M_B_DQ44[15]
M_B_DQ45[15]
M_B_DQ46[15]
M_B_DQ47[15]
M_A_DQ48[14]
M_A_DQ49[14]
M_A_DQ50[14]
M_A_DQ51[14]
M_A_DQ52[14]
M_A_DQ53[14]
M_A_DQ54[14]
M_A_DQ55[14]
M_A_DQ56[14]
M_A_DQ57[14]
M_A_DQ58[14]
M_A_DQ59[14]
M_A_DQ60[14]
M_A_DQ61[14]
M_A_DQ62[14]
M_A_DQ63[14]
M_B_DQ48[15]
M_B_DQ49[15]
M_B_DQ50[15]
M_B_DQ51[15]
M_B_DQ52[15]
M_B_DQ53[15]
M_B_DQ54[15]
M_B_DQ55[15]
M_B_DQ56[15]
M_B_DQ57[15]
M_B_DQ58[15]
M_B_DQ59[15]
M_B_DQ60[15]
M_B_DQ61[15]
M_B_DQ62[15]
M_B_DQ63[15]
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
SB_DQ0
AW31
SB_DQ1
AY29
SB_DQ2
AW29
SB_DQ3
AV31
SB_DQ4
AU31
SB_DQ5
AV29
SB_DQ6
AU29
SB_DQ7
AY27
SB_DQ8
AW27
SB_DQ9
AY25
SB_DQ10
AW25
SB_DQ11
AV27
SB_DQ12
AU27
SB_DQ13
AV25
SB_DQ14
AU25
SB_DQ15
AM29
SB_DQ16
AK29
SB_DQ17
AL28
SB_DQ18
AK28
SB_DQ19
AR29
SB_DQ20
AN29
SB_DQ21
AR28
SB_DQ22
AP28
SB_DQ23
AN26
SB_DQ24
AR26
SB_DQ25
AR25
SB_DQ26
AP25
SB_DQ27
AK26
SB_DQ28
AM26
SB_DQ29
AK25
SB_DQ30
AL25
SB_DQ31
AY23
SB_DQ32
AW23
SB_DQ33
AY21
SB_DQ34
AW21
SB_DQ35
AV23
SB_DQ36
AU23
SB_DQ37
AV21
SB_DQ38
AU21
SB_DQ39
AY19
SB_DQ40
AW19
SB_DQ41
AY17
SB_DQ42
AW17
SB_DQ43
AV19
SB_DQ44
AU19
SB_DQ45
AV17
SB_DQ46
AU17
SB_DQ47
AR21
SB_DQ48
AR22
SB_DQ49
AL21
SB_DQ50
AM22
SB_DQ51
AN22
SB_DQ52
AP21
SB_DQ53
AK21
SB_DQ54
AK22
SB_DQ55
AN20
SB_DQ56
AR20
SB_DQ57
AK18
SB_DQ58
AL18
SB_DQ59
AK20
SB_DQ60
AM20
SB_DQ61
AR18
SB_DQ62
AP18
SB_DQ63
HSW_ULT_ DDR3 L
DDR CHANNEL B
4 OF 19
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
M_B_ODT0
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_A_DQS#4
M_A_DQS#5
M_B_DQS#4
M_B_DQS#5
M_A_DQS#6
M_A_DQS#7
M_B_DQS#6
M_B_DQS#7
M_A_DQS4
M_A_DQS5
M_B_DQS4
M_B_DQS5
M_A_DQS6
M_A_DQS7
M_B_DQS6
M_B_DQS7
M_B_CLK0# [15]
M_B_CLK0 [15]
M_B_CLK1# [15]
M_B_CLK1 [15]
M_B_CKE0 [15]
M_B_CKE1 [15]
M_B_CS#0 [15]
M_B_CS#1 [15]
TP25
M_B_RAS# [15]
M_B_WE# [15]
M_B_CAS# [15]
M_B_BS#0 [15]
M_B_BS#1 [15]
M_B_BS#2 [15]
M_B_A[15:0] [15]
M_A_DQS#4 [14]
M_A_DQS#5 [14]
M_B_DQS#4 [15]
M_B_DQS#5 [15]
M_A_DQS#6 [14]
M_A_DQS#7 [14]
M_B_DQS#6 [15]
M_B_DQS#7 [15]
M_A_DQS4 [14]
M_A_DQS5 [14]
M_B_DQS4 [15]
M_B_DQS5 [15]
M_A_DQS6 [14]
M_A_DQS7 [14]
M_B_DQS6 [15]
M_B_DQS7 [15]
https://t.me/schematicslaptop
https://t.me/biosarchive
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
ZRT/ZRTA
PROJECT :
ZRT/ZRTA
PROJECT :
1
ZRT/ZRTA
of
344
344
344
3A
3A
3A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Haswell 2/5 (DDR3 I/F)
Haswell 2/5 (DDR3 I/F)
Haswell 2/5 (DDR3 I/F)
Date: Sheet of
Date: Sheet of
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Wednesday, February 11, 2015
5
4
3
2
Date: Sheet
5
4
3
2
1
H_PECI (50ohm)
Route on microstrip only
D D
C C
B B
Spacing >18 mils
Trace Length: 0.4~6.125 iches
H_PWRGOOD (50ohm)
Trace Length: 1~11.25 inches
CPU_PLTRST# (50ohm)
Trace Length: 10~17 inches
H_PECI[31] XDP_PRDY# [13]
H_PROCHOT#[31,32,36]
SM_RCOMP[0:2]
Trace length < 500 mils
Trace width = 12~15 mils
Trace spacing = 20 mils
R662 56_4
TP106
TP99
DRAM COMP
R663 *62_4
R664 62_4
R682 10K_4
5
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
+VCCIO_OUT
+1.05V_VCCST
DRAMRST
+1.35V_SUS
CPU DRAM
CPU_DRAMRST#
R254 200/F_4
R250 120/F_4
R260 100/F_4
PU/PD of CPU
H_PROCHOT#
A A
H_PWRGOOD_R
Haswell ULT (SIDEBAND)
U37B
PROC_DETECT
CATERR#
H_PECI
H_PROCHOT#_RH_PROCHOT#
H_PWRGOOD_R
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
DDR_PG_CTRL
12
4
R551
470_4
AU60
AV60
AU61
AV15
AV61
XDP_TDO_CPU
XDP_TCK0
XDP_TRST#
D61
PROC_DETECT
K61
CATERR
N62
PECI
K63
PROCHOT
C61
PROCPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
R659 51_4
R340 51_4
R578 *51_4
R552 *short_4
DSW
+1.05V_VCCST
12
C488
*0.1u/10V_4
MISC
THERMAL
PWR
DDR3L
HSW_ULT_DDR3L
DDR3_DRAMRST# [14,15]
3
JTAG
2 OF 19
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
DDR3L ODT GENERATIONXDP PU/PD
J62
XDP_PRDY#
K62
XDP_PREQ#
E60
XDP_TCK0
E61
XDP_TMS_CPU
XDP_TRST#
E59
F63
XDP_TDI_CPU
F62
XDP_TDO_CPU
J60
XDP_BPM#0
H60
XDP_BPM#1
H61
XDP_BPM#2
H62
XDP_BPM#3
K59
XDP_BPM#4
H63
XDP_BPM#5
K60
XDP_BPM#6
J61
XDP_BPM#7CPU_DRAMRST#
DDR_VTTT_PG_CTRL[35]
R164
220K/F_4
XDP_PREQ# [13]
XDP_TCK0 [8, 13]
XDP_TMS_CPU [13]
XDP_TRST# [8,13]
XDP_TDI_CPU [13]
XDP_TDO_CPU [13]
XDP_BPM#0 [13]
XDP_BPM#1 [13]
TP103
TP102
TP46
TP104
TP100
TP47
+5V_S5
12
R162
*220K/F_4
2
+3VSUS
12
0.1u/10V_4
+1.35V_SUS
2
TCK,TMS
Trace Length < 9000mils
BPM#[0: 7]
Trace Length 1~6 inches
Length match < 300 mils
+1.35V_SUS
U7
5
12
C152
4
3
1
74AUP1G07GW
R87 66.5/F_4
Q8
R86 66.5/F_4
2N7002K
R84 66.5/F_4
R85 66.5/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Date: Sheet
Date: Sheet of
Date: Sheet of
1
NC
VCC
2
A
3
GND
Y
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Haswell 1/5 (PEG/DMI/FDI)
Haswell 1/5 (PEG/DMI/FDI)
Haswell 1/5 (PEG/DMI/FDI)
R167 *short_4
M_A_ODT0_DIMM [14]
M_A_ODT1_DIMM [14]
M_B_ODT0_DIMM [15]
M_B_ODT1_DIMM [15]
1
ZRT/ZRTA
ZRT/ZRTA
ZRT/ZRTA
DDR_PG_CTRL
3A
3A
3A
of
444
444
444
https://t.me/schematicslaptop
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VDDQ Output Deco upling Recommenda tions
330uFx2 7343
22uFx11
10uFx10
D D
+1.35V_SUS
R208 *short_1206
R209 *short_1206
+
C C
+1.05V_VCCST
VRON_CPU IMVP_PWRGD
B B
5
BOT socket s ide
5 onTOP, 6 on BOT insi de socket cavity
0805
5 onTOP, 5 on BOT insi de socket cavity
0805
C187
C190
10u/6.3V_6
10u/6.3V_6
C217
C489
2.2u/6.3V_6
*470u/2V_7343
+VCCIN
VCC_SENSE[36]
R332 *10K_4
R333 10K_4
PWR_DEBUG[13]
+1.05V_VCCST
+1.35V_CPU 1.4A
C226
10u/6.3V_6
C227
2.2u/6.3V_6
300mA
300mA
+1.35V_CPU
+1.35V_CPU
C220
10u/6.3V_6
C181
2.2u/6.3V_6
R666 100/F_4
R676 *short_4
VCCST_PWRGD[13]
VRON_CPU[36]
IMVP_PWRGD[10,36]
R319 *short_4 C253
R323 150_6
C188
10u/6.3V_6
+VCCIO_OUT
+VCCIOA_OUT
1006 add
C219
2.2u/6.3V_6
+VCCIN
TP43
TP44
TP49
TP97
C191
10u/6.3V_6
VCC_SENSE_R
H_CPU_SVIDART#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
VCCST_PWRGD
VRON_CPU
IMVP_PWRGD
PWR_DEBUG_ R
ULT_RVSD_69
ULT_RVSD_70
ULT_RVSD_71
ULT_RVSD_72
1006 Del
R345 *short_8
+1.05V_VCCST+1.05V
C235
*4.7u/10V_6
+1.05V_VCCST
+VCCIN
HWPG_1.05V for DDR=1.5V
Q9
*MMBT3904-7-F
+3V
R94
*4.7K_4
C73
*1000p/50V_4
2
A A
+1.05V
R99 *4.7K_4
C72
*1000p/50V_4
5
2
1 3
4
Haswell ULT (POWER)
U37L
L59
RSVD
J58
RSVD
AH26
VDDQ
AJ31
VDDQ
AJ33
VDDQ
AJ37
VDDQ
AN33
VDDQ
AP43
VDDQ
AR48
VDDQ
AY35
VDDQ
AY40
VDDQ
AY44
VDDQ
AY50
VDDQ
F59
VCC
N58
RSVD
AC58
RSVD
E63
VCC_SENSE
AB23
RSVD
A59
VCCIO_OU T
E20
VCCIOA_OU T
AD23
RSVD
AA23
RSVD
AE59
RSVD
L62
VIDALERT
N63
VIDSCLK
L63
VIDSOUT
B59
VCCST_PWR GD
F60
VR_EN
C59
VR_READY
D63
VSS
H59
PWR_DEBUG
P62
VSS
P60
RSVD_TP
P61
RSVD_TP
N59
RSVD_TP
N61
RSVD_TP
T59
RSVD
AD60
RSVD
AD59
RSVD
AA59
RSVD
AE60
RSVD
AC59
RSVD
AG58
RSVD
U59
RSVD
V59
RSVD
AC22
VCCST
AE22
VCCST
AE23
VCCST
AB57
VCC
AD57
VCC
AG57
VCC
C24
VCC
C28
VCC
C32
VCC
+3V
R78
1 3
*4.7K_4
Q7
*DTC144EU
R77
*100K/F_4
10/30 reserve
DDR=1.5V ,This block POP
4
HWPG_1.05V [31]
HSW_ULT_DDR3L
HSW ULT POWER
12 OF 19
3
+
C556
*470u/2V_7343
C36
VCC
C40
VCC
C44
VCC
C48
C256
VCC
C52
VCC
C56
VCC
E23
VCC
E25
VCC
E27
VCC
E29
VCC
E31
VCC
E33
VCC
E35
VCC
E37
VCC
E39
VCC
E41
VCC
E43
VCC
E45
VCC
E47
VCC
E49
VCC
E51
VCC
E53
VCC
E55
VCC
E57
VCC
F24
VCC
F28
VCC
F32
VCC
F36
VCC
F40
VCC
F44
VCC
F48
VCC
F52
VCC
F56
VCC
G23
VCC
G25
VCC
G27
VCC
G29
VCC
G31
VCC
G33
VCC
G35
VCC
G37
VCC
G39
VCC
G41
VCC
G43
VCC
G45
VCC
G47
VCC
G49
VCC
G51
VCC
G53
VCC
G55
VCC
G57
VCC
H23
VCC
J23
VCC
K23
VCC
K57
VCC
L22
VCC
M23
VCC
M57
VCC
P57
VCC
U57
VCC
W57
VCC
3
C329
22u/6.3V_8
22u/6.3V_8
C245
C270
22u/6.3V_8
22u/6.3V_8
C548
C252
22u/6.3V_8
22u/6.3V_8
C246
C283
22u/6.3V_8
22u/6.3V_8
C549
*22u/6.3V_8
*22u/6.3V_8
VCC Output Deco upling Recommend ations
470uFx4 7343
22uFx8
0805
22uFx11
0805
10uFx11
0805
C289
C312
22u/6.3V_8
22u/6.3V_8
C552
C275
22u/6.3V_8
22u/6.3V_8
C260
C339
22u/6.3V_8
22u/6.3V_8
C251
C250
22u/6.3V_8
22u/6.3V_8
C236
C334
*22u/6.3V_8
*22u/6.3V_8
TOP socket side
4 on TOP, 4 on BOT near soc ket edge
TOP, inside socket cavity
BOT, insi de socket cavity
C279
22u/6.3V_8
C240
22u/6.3V_8
C550
22u/6.3V_8
C337
22u/6.3V_8
C545
*22u/6.3V_8
2
+VCCIN 32A
C335
22u/6.3V_8
C259
22u/6.3V_8
C261
22u/6.3V_8
C554
22u/6.3V_8
C234
*22u/6.3V_8
2
VCCST PWRGD
VCCST_PWRGD
+VCCIN
SVID
H_CPU_SVIDDAT
H_CPU_SVIDART#
H_CPU_SVIDCLK
CRB is via +1.05V PG
+1.05V_VCCST
C465
*0.1u/10V_4
VCCST_PWRGD _EN
1A-6 2013/10/21 Del APWORK.
+VCCIO_OUT
Place PU resistor
close to CPU
Place PU resistor
close to CPU
+3V_S5
5
C466
R681
10K_4
R503 *short_4
R489 *0_4
0.1u/10V_4
VCCST_PWRGD _R
Layout note: need routing together
and ALERT need between CLK and DATA.
+1.05V_VCCST
R651
*130/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Date: Sheet
4
HWPG_1.05V_EC
Q43
*2N7002K
R107 *short_4
R108 *0_4
+VCCIO_OUT+1.05V
R351 *0_8
R652
130/F_4
R650 *short_4
+1.05V_VCCST
R631 43_4
R628 *short_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Haswell 4/5 (POWER)
Haswell 4/5 (POWER)
Haswell 4/5 (POWER)
1
U28
NC1VCC
A
GND3Y
74AUP1G07GW
3
Reserve from EC
2
1
PCH_PWROK [7,31]
EC_PWROK [7,31]
C263
*4.7u/10V_6
+VCCIO_OUT
R637
75_4
1
2
VCCST_PWRGD _EN
HWPG_1.05V_EC# [31]
VR_SVID_DATA [36]
R636
*75_4
VR_SVID_ALERT# [36 ]
VR_SVID_CLK [36]
ZRT/ZRTA
ZRT/ZRTA
ZRT/ZRTA
of
544
544
544
3A
3A
3A
https://t.me/schematicslaptop
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5
4
3
2
1
Haswell ULT (CFG,RSVD)
U37S
HSW_ULT_DDR3L
D D
C C
1A-10 20131025 reserve A5 ball to 100k PU 3VPCU.
1A-12 20131028 reserve A5 ball toTP.
NOA_STBN_0[13]
NOA_STBN_1[13]
NOA_STBP_0[13]
NOA_STBP_1[13]
R618 49.9/F_4
TP109
CFG0[13]
CFG1[13]
CFG2[13]
CFG3[13]
CFG4[8,13]
CFG5[13]
CFG6[13]
CFG7[13]
CFG8[13]
CFG9[13]
CFG10[13]
CFG11[13]
CFG12[13]
CFG13[13]
CFG14[13]
CFG15[13]
R689 8.2K_4
NOA_STBN_0
NOA_STBN_1
NOA_STBP_0
NOA_STBP_1
CFG_RCOMP
REFPKG_OCC
TD_IREF
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
AC60
AC62
AC63
AA63
AA60
AA62
AA61
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
U63
U62
V63
A5
E1
D1
J20
H18
B12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
RESERVED
PROC_OPI_RCOMP
19 OF 19
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AV63
AU63
C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15
OPI_COMP1
AV62
D58
P22
VSS
N21
VSS
P20
R20
R555 49.9/F_4
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Processor Strapping
CFG0
EAR-STALL/NOT STALL RESET SEQUENCE
AFTER PCU PLL IS LOCKED
CFG1
PCH/ PCH LESS MODE SELECTION
B B
CFG3
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
CFG 8
ALLOW THE USE OF NOA O N LOCKED UNITS
CFG9
NO SVID PRO TOCOL CAPABLE VR
CONNECTED
A A
CFG10
SAFE MODE BOOT
5
(DEFAULT) NORMAL OPERATION; NO STALL
(DEFAULT) NORMAL OPERATION
DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED
TO
EMBEDDED DISPLAY PORT
DISABLED(DEFAULT); IN THIS CASE, NOA
WILL BE DISABLED IN LOCKED UNITS AND
ENABLED IN UN-LOCKED UNITS
VRS SUPPORTING SVID PROTOCOL ARE
PRESENT
POWER FEATURES ACTIVATED
DURING RESET
1 0
STALL
PCH-LESS MODE
ENABLED
AN EXTERNAL DISPLAY PORT DEVICE IS
CONNECTED
TO THE EMBEDDED DISPLAY PORT
ENABLED; NOA WILL BE AVAILABLE
REGARDLESS OF THE LOCKING OF THE UNIT
NO VR SUPPORT ING SVID IS PRESENT. THE
CHIP WI LL NOT GENERATE (OR RE SPOND TO)
SVID ACTIVITY
POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED
4
CFG0
R289 *1K_4
CFG1
R606 *1K_4
CFG3
R610 *1K_4
CFG8
R614 *1K_4
CFG9
R619 *1K_4
CFG10
R295 *1K_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Wednesday, February 11, 2015
Wednesday, February 11, 2015
3
2
Wednesday, February 11, 2015
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Haswell 5/5 (CFG/GND)
Haswell 5/5 (CFG/GND)
Haswell 5/5 (CFG/GND)
ZRT/ZRTA
ZRT/ZRTA
ZRT/ZRTA
1
3A
3A
3A
of
644
644
644
5
PCH_SUSACK#[31]
PCH_SUSPWRACK
SYS_RESET#[1 3]
DNBSWON#[31]
ACPRESENT[32]
RSMRST#[31]
R276 *short_4
R279 *0_4
R282 *0_4
D D
1C1-1 2014/02/19 add R692 for SUSPWRACK# to EC.
SYS_PWROK
EC_PWROK
PCH_SUSPWRACK_R[31]
R597 *0_4
R596 *0_4
C237 *1u/6.3V_4
R546 *0_4
R283 *0_4
R548 *short_4
R583 *0_4
R265 *short_4
R294 *short_4
TP77
TP28
SUSACK#_R
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
EC_PWROK_R
APWROK_R
PCI_PLTRST#
PCH_RSMRST#
PCH_SUSPWRACK
PCH_PWRBTN#
PCH_ACPRESENT
PCH_BATLOW#
PCH_SLP_S0#_R
PCH_SLP_WLAN#
4
Haswell ULT PCH (PM)
U37H
AK2
SUSACK
AC3
SYS_RESET
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST
AW6
RSMRST
AV4
SUSWARN/SUSPW RDNACK/GPIO30
AL7
PWRBTN
AJ8
ACPRESENT/GPIO31
AN4
BATLOW/GPIO72
AF3
SLP_S0
AM5
SLP_WLAN/GPIO29
+3V_S5
HSW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
+3V_S5
DSW
DSW
DSW
+3V_S5
DSW
8 OF 19
3
+3V
+3V_S5
+3V_S5
DSW
DSWVRMEN
DPWROK
DSW
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
DSW
SLP_S4
DSW
SLP_S3
DSW
SLP_A
DSW
SLP_SUS
DSW
SLP_LAN
AW7
DSWVREN
DPWROK_R
AV5
AJ5
PCIE_LAN_WAKE#
V5
CLKRUN#
GPIO61
AG4
AE6
PCH_SUSCLK
AP5
PCH_SLP_S5#
AJ6
SUSC#
SUSB#
AT4
AL5
PCH_SLP_A#
AP4
PCH_SLP_SUS#
PCH_SLP_LAN#
AJ7
2
Deep Sx
R543 *0_4
TP74
TP32
DSWVREN [8]
DPWROK [31 ]
PCIE_LAN_WAKE# [25,28]
CLKRUN# [27,31]
PCH_SUSCLK [ 28]
PCH_SLP_S5# [13]
SUSC# [13,3 1]
SUSB# [13,31]
PCH_SLP_A# [13]
PCH_SLP_SUS# [ 31]
1
C C
https://t.me/schematicslaptop
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PCH PM PU/PD
+3V
CLKRUN#
SYS_RESET#
B B
PCH_RSMRST#
SYS_PWROK
DPWROK_R
PCH_SUSCLK
PCH_SUSPWRACK
GPIO61
1C-5 2014/01/16 Change R264 from 10k to 1k
for wake on lan issue.
PCH_ACPRESENT
PCH_BATLOW#
PCIE_LAN_WAKE#
PCH_PWRBTN#
A A
R638 8.2K_4
R612 10K_4
R554 10K_4
R277 *10K_4
R553 100K/F_4
R306 *10K_4
R590 *10K_4
R603 *10K_4
R287 10K_4
R255 8.2K_4
R298 1K_4
R267 *10K_4
R293 *10K_4
R256 *8.2K_4
R296 *1K_4
R264 *10K_4
5
+3V_S5
+3V_S5
+3VPCU
DSW PU
Power Sequence
PCH_PWROK[5,31]
R106
100K_4
EC_PWROK SYS_PWROK_R
R559 *short_4
R284 *0_4
R549 *short_4
Non Deep Sx
EC_PWROK_R
DPWROK_RRSMRST#
PLTRST# Buffer Deep Sx Circuit
+3V
PCI_PLTRST#
2
1
C202 0.1u/10V_4
4
U15
3 5
TC7SH08FU
R227
100K_4
PLTRST# [13,16,25,27,2 8,31]
+3V_S5 +3VCC_S5
SYSPWOK
+3V_S5
C249 *0.1u/10V_4
2
4
SYS_PWROK[13]
4
SYS_PWROK
U17
TC7SH08FU
R305 *0_4
EC_PWROK
1
3 5
3
R297
10K_4
EC_PWROK [5,31]
IMVP_PWRGD_3V [10]
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet
2
APWORK[31]
Speed up 250ms to boot up
for EC power on 250 ms
R285 *short_4
Non Deep Sx
R220 *Short_6
1
R212
C178
*0.33u/10V_ 6
*100K_4
PCH_SLP_SUS#
LPT 1/6 (DMI/FDI/VGA)
LPT 1/6 (DMI/FDI/VGA)
LPT 1/6 (DMI/FDI/VGA)
2
3
2
Q16
*2N7002K
1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
APWROK_R
R280
10K_4
3
Q14
*AO3413
R211
*0_6
ZRT/ZRTA
ZRT/ZRTA
ZRT/ZRTA
of
744
744
744
1
3A
3A
3A
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RTC Cl ock 32 .768KHz (RTC)
C506 15p/50V_4
C498 15p/50V_4
RTC Ci rcuit ry (RTC )
D D
R528 *Short_6
+3VPCU
R525 1K_4
VCCRTC _2
+3V_RTC_[0:2]
Trace width = 20 mils
12
BT1
BAT_CONN
1A-2
2013/10/16 Chage +3V_RTC_0 to VCCTC_2.
HDA
PCH_AZ_CODEC_RST#[26]
PCH_AZ_CODEC_SDOUT[26]
PCH_AZ_CODEC_BITCLK[26]
C C
PCH_AZ_CODEC_SYNC[26]
PCH JTA G
JTAG_TCK,JTAG_TM S
Trace Length < 9000mils
B B
ULT Strapping Table
Pin Name Strap description
GPIO81(SPKR)
HDA_SDO
INTVRMEN
GPIO66
GPIO86
GPIO15
A A
CFG4
DSWVREN
5
RTC_X1
12
R577
Y2
10M_4
32.768KHZ
RTC_X2
1B-1
+3V_RTC
D25
+3V_RTC_2
+3V_RTC_1
BAT54C
C185
1u/6.3V_4
R236 33_4
R572 33_4
R570 33_4
C490
*10p/50V_4
R237 33_4
C221 *10p/50V_4
MP remove(Intel)
XDP_TM S
R585 51_4
XDP_TD I
R586 51_4
PCH_JTAG_TDO
R591 51_4
PCH_JTAGX
R587 *1K_4
XDP_TC K1
R580 *51_4
No reboot on TCO Timer
expiration
Flash Descriptor Sec urity
Override / Intel ME Debug Mode
Integr ated 1 .05V VR M enab le ALWAYS
Top-Block Swap override
Boot BIOS Strap Bit
TLS(Transport layer security)
DP presence strap
Deep Sx well on die VR enable
5
+3V_RTC
Trace width = 30 mils
R219
20K/F_4
C182
2.2u/6.3V_4
R214
20K/F_4
C186
2.2u/6.3V_4
+1.05V_S5
12
SRTC_RST#
HDA_RST#_R
HDA_SDO_R
HDA_BCLK_R
HDA_SYNC_R
RTC_RST#
J1
*JUMP
Sampled
PWROK
PWROK
+3V_RTC
PCH_AZ_CODEC_SDIN0[26]
XDP_TR ST#[4,13]
XDP_TC K1[13]
XDP_TD I[13]
XDP_TD O[13]
XDP_TM S[13]
XDP_TC K0[4,13]
1A-10
1A-12
0 = Default en able (iPD 20K )
1 =Disable No- Reboot mode
0 = Default can program ME ( iPD 20K)
1 =can't progr am ME
1=Should be al ways pull- up
0 = Default d isable (iPD 20K)
1 = Enable TBS function
0 = Default SP I (iPD 20K )
1 =LPC
0 = Default en able w/o
confidenti ality(i PD 20K)
1 =Default enable wi th
confidentiality
0 = Enable an extern al display
port is connected to the eDP
1 =disable
1=Should be al ways pull- up
4
Haswell ULT PCH (RTC/HDA/SATA/SPI)
U37E
AW5
RTC_X1
RTCX1
AY5
RTC_X2
RTCX2
AU6
SM_INTRUDER#
R562 1M_4
RTC_RST#[13]
R592 *short _4
R581 *short _4
TP70
2013/10/25 reserve AV2 ball to GND.
2013/10/28 reserve AV2 ball to TP.
Configuration note
PCH_INTVRMEN
RTC_RST#
HDA_BCLK_R
HDA_SYNC_R
HDA_RST#_R
HDA_SDO_R
XDP_TC K1
XDP_TD I
PCH_JTAG_TDO
PCH_JTAGX
PCH_EDM
4
INTRUD ER
AV7
INTVRME N
AV6
SRTCRST
AU7
RTCRST
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST/I2S_MCLK
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN/I2S1_TXD
AV10
HDA_DOCK_RST/I2S1_SFRM
AY8
I2S1_SC LK
AU62
PCH_TRST
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
+3V
+3V_RTC
+3V
+3V
+3V_S5
+3V_RTC
HDA_SDO_R
GPIO86[10]
GPIO15[10]
DSWVREN[7]
JTAG
R304 *1K_4
R545 330K_4
R356 *1K_4
R343 *1K_4
R317 8.2K_4
CFG4[6,13]
R557 330K_4
HSW_ULT_DDR3L
RTC
AUDIO SATA
5 OF 19
SPKR
PCH_INTVRMEN
GPIO66
GPIO86
GPIO15
CFG4
DSWVREN
SPKR [10,26]
ME_WR# [31]
R558 *330K_4
R361 *1K_4
R346 *1K_4
R307 *1K_4
R611 1K_4
R567 *330K_4
R573 *short_4
+3V
+3V
+3V
+3V
3
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_IREF
SATA_RCOMP
SATALED
3
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
VGPU_EN
V1
U1
ODD_PRSNT#
V6
DEVSLP_ODD
GPIO37
AC1
A12
SATA_IREF
L11
RSVD
K10
RSVD
C12
SATA_RCOMP
U3
SATA_LED#
SATA_RCOMP
Impedance = 50 ohm
Trace length < 500 mils
Trace spacing = 15 mils
PCH SPI ROM(8M +4M)
15ohm CS01502JB12
R690 *short_4
R688 3.01K/F_4
R626 10K_4
PCH_SPI_CLK_EC[31]
PCH_SPI_SI_EC[31]GPIO66[10]
+3V_PCH_ME
SATA_RXN0 [27]
SATA_RXP0 [27]
HDD
SATA_TXN0 [27]
SATA_TXP0 [27]
SATA_RXN1 [27]
SATA_RXP1 [27]
ODD
SATA_TXN1 [27]
SATA_TXP1 [27]
VGPU_EN [ 38]
ODD_PRSNT# [27]
DEVSLP_ODD [27]
TP91
+V1.05S_ASATA3PLL
+V1.05S_ASATA3PLL
+3V
U38
1
PCH_SPI_CS0#
CS#
SPI_SO_8M
2
IO1/DO
3
SPI_WP_IO2_ME
IO2/WP#
4
GND
W25Q64FW -- 8MB
PCH_SPI_CLK_EC
PCH_SPI_CLK
PCH_SPI_SI_EC
PCH_SPI_SI
+3V_PCH_ME
PCH_SPI_SO_EC[31]
+3V_PCH_ME
SPI_CS0#_UR_ME[31]
R600 15_4
R648 *1K_4
PCH_SPI_IO2 SPI_WP_IO2_ME
R657 15_4
PCH_SPI_SO_EC
PCH_SPI_SO
R313 10K_4
2
Haswell ULT PCH(LPC,SPI,SMBUS,C-LINK,THERMAL)
HSW_ULT_DDR3L
U37G
LPC_LFRAME#[27,28,31]
R308 *Short_6
VCC
IO3/HOL D#
CLK
IO0/DI
R593 15_4
R602 15_4
R598 15_4
R604 15_4
R605 *1K_4
R649 15_4
R658 15_4
LPC_LAD0[27,28,31]
LPC_LAD1[27,28,31]
LPC_LAD2[27,28,31]
LPC_LAD3[27,28,31]
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_IO3
GPIO37
DEVSLP_ODD
R622*10K_4
1A-14
2013/12/02 change GPIO36 to PD.
2013/12/04 change GPIO36/GPI037 to PU.
1B-2
+3V_PCH_ME+3V_S5
8
SPI_HOLD_IO3_ME
7
6
SPI_CLK_8M
5
SPI_CLK_8M
C522 *22p/50V_4
SPI_SI_8M
SPI_HOLD_IO3_MEPCH_SPI_IO3
R639 *short_4
2
VGPU_EN
SPI_SI_8M
SPI_SO_8M
PCH_SPI_CS0#
AU14
LAD0
AW12
LAD1
AY12
LAD2
AW11
LAD3
AV12
LFRAME
AA3
SPI_CLK
Y7
SPI_CS0
Y4
SPI_CS1
AC2
SPI_CS2
AA2
SPI_MOSI
AA4
SPI_MISO
Y6
SPI_IO2
AF1
SPI_IO3
R61510K_4
R312*10K_4
R62510K_4
+3V_PCH_ME
C254
0.1u/10V_4
+3V_S5
SMBALERT/GPIO11
+3V_S5
LPC
+3V_S5
SMBUS
+3V_S5
SML0ALERT/GPIO60
+3V_S5
+3V_S5
+3V_S5
SML1ALERT/PCHHOT/GPIO73
+3V_S5
SML1CLK/GPIO75
+3V_S5
SML1DATA/GPIO74
C-LINKSPI
7 OF 19
+3V
SMBus
SMBus(PCH)
SMB_PCH_DAT
SMB_PCH_CLK
PCH_XDP_WLAN/S5 DDR_TP/S0
SMBus(EC)
2ND_MBCLK[19,31]
2ND_MBDATA[19,31]
EC/S5 PCH/S5
1
AN2
SMBALERT#SRTC_RST#
AP2
SMB_PCH_CLK
SMBCLK
AH1
SMB_PCH_DAT
SMBDATA
SMB0ALERT#
AL2
VGA_MBCL K
AN1
SML0CLK
AK1
VGA_MBDAT A
SML0DATA
SMB1ALERT#
AU4
SMB_ME1_CLK
AU3
AH3
SMB_ME1_DAT
AF2
CL_CLKPCH_SPI_CS0#
CL_CLK
AD2
CL_DAT
CL_DATA
AF4
CL_RST#
CL_RST
+3V_S5
R589 10K_4
R556 10K_4
R271 10K_4
R238 2.2K_4
R249 2.2K_4
R595 2.2K_4
R258 2.2K_4
+3V
Q18
5
621
2N7002DW
+3V_S5
Q19
5
621
*2N7002DW
R240 *short_4
2ND_MBDATA
R263 *short_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LPT 2/6 (SATA/HDA/SPI)
LPT 2/6 (SATA/HDA/SPI)
LPT 2/6 (SATA/HDA/SPI)
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Date: Sheet
Date: Sheet of
Date: Sheet of
SMB1ALERT# [29]
TP83
TP85
TP40
SMB0ALERT#
SMB1ALERT#
SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
VGA_MBDAT A
VGA_MBCL K
R252
R235
4.7K_4
4.7K_4
43
CLK_SDATA [13,14,15,29]
CLK_SCLK [13,14,15,29]
R241
R259
*2.2K_4
*2.2K_4
SMB_ME1_CLK
43
SMB_ME1_DAT
SMB_ME1_CLK2ND_MBCLK
SMB_ME1_DAT
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
ZRT/ZRTA
PROJECT :
ZRT/ZRTA
PROJECT :
ZRT/ZRTA
844
844
1
844
of
3A
3A
3A
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5
1A-6 2013/10/21 reversal PEG lan for layout.
1A-8 2013/10/21 Swap PEG to nomroal mode.
PEG_RX#0[16]
D D
C C
B B
PEG_RX0[16]
PEG_TX#0[16]
PEG_TX0[16]
PEG_RX#1[16]
PEG_RX1[16]
PEG_TX#1[16]
PEG_TX1[16]
PEG x4
PEG_RX#2[16]
PEG_RX2[16]
PEG_TX#2[16]
PEG_TX2[16]
PEG_RX#3[16]
PEG_RX3[16]
PEG_TX#3[16]
PEG_TX3[16]
PCIE_RX3-_LAN[2 5]
PCIE_RX3+_LAN[25]
PCIE_TX3-_LAN[25]
LANWLAN
PCIE_TX3+_LAN[25]
PCIE_RX4-_WLAN[28]
PCIE_RX4+_WLAN[28]
PCIE_TX4-_WLAN[28]
PCIE_TX4+_WLAN[28 ]
+V1.05S_AUSB3PLL
Haswell ULT PCH (PCIE,USB3.0,USB2.0)
U37K
F10
PERN5_L0
E10
PERP5_L0
C23
C532 EV@0.22u/10V_4
C533 EV@0.22u/10V_4
C525 EV@0.22u/10V_4
C526 EV@0.22u/10V_4
C530 EV@0.22u/10V_4
C531 EV@0.22u/10V_4
C527 EV@0.22u/10V_4
C528 EV@0.22u/10V_4
C538 0.1u/10V_4
C537 0.1u/10V_4
C536 0.1u/10V_4
C535 0.1u/10V_4
R339 3.01K/F_4
R338 *short_4
C_PEG_TX#0
C_PEG_TX0
C_PEG_TX#1
C_PEG_TX1
C_PEG_TX#2
C_PEG_TX2
C_PEG_TX#3
C_PEG_TX3
PCIE_TX3ÂPCIE_TX3+
PCIE_TX4ÂPCIE_TX4+
PCIE_RCOMP
PCIE_IREF
C22
F8
E8
B23
A23
H10
G10
B21
C21
E6
F6
B22
A21
G11
F11
C29
B30
F13
G13
B29
A29
G17
F17
C30
C31
F15
G15
B31
A31
E15
E13
A27
B27
PETN5_L0
PETP5_L0
PERN5_L1
PERP5_L1
PETN5_L1
PETP5_L1
PERN5_L2
PERP5_L2
PETN5_L2
PETP5_L2
PERN5_L3
PERP5_L3
PETN5_L3
PETP5_L3
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
+3V_S5
+3V_S5
+3V_S5
+3V_S5
4
HSW_ULT_D DR3L
PCIE USB
11 OF 19
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
1A-1 2013/10/15 following up acer define and swap USB3 and USB2
USB2 port.
AN8
DSW
DSW
DSW
DSW
DSW
DSW
DSW
DSW
DSW
DSW
DSW
DSW
DSW
DSW
DSW
DSW
USB3RN1
USB3RP 1
USB3RN2
USB3RP 2
USBRBI AS
USBRBI AS
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB3TN1
USB3TP 1
USB3TN2
USB3TP 2
RSVD
RSVD
USBP0- [30]
AM8
USBP0+ [3 0]
AR7
USBP1- [30]
AT7
USBP1+ [3 0]
AR8
AP8
AR10
USBP3- [3 0]
AT10
USBP3+ [3 0]
AM15
USBP4- [28]
AL15
USBP4+ [2 8]
AM13
USBP5- [23]
AN13
USBP5+ [2 3]
AP11
USBP6- [23]
AN11
USBP6+ [2 3]
AR13
USBP7- [30]
AP13
USBP7+ [3 0]
G20
USB3_RX N0 [3 0]
H20
USB3_RX P0 [30 ]
C33
USB3_TX N0 [30]
B34
USB3_TX P0 [30]
E18
USB3_RX N1 [3 0]
F18
USB3_RX P1 [30 ]
B33
USB3_TX N1 [30]
A33
USB3_TX P1 [30]
AJ10
USBCOMP
R257 22.6/F_4
AJ11
AN10
AM10
AL3
USB_OC0 #
USB_OC1 #
USB_OC2 #
USB_OC3 #
USB_OC0 # [3 0]
USB_OC1 # [3 0]
AT1
AH2
AV3
MB USB3.0
MB USB3.0
DB USB2.0
DB USB2.0
BT
Touch screen
CCD
Card reader
MB USB3.0
USBCOMP
Impedance = 50 ohm
Trace length < 500 mils
Trace spacing = 15 mils
MB U3
DB U2
3
CLK_PCIE_N0
TP111
CLK_PCIE_P0
TP108
CLK_PCIE_REQ0#
TP96
CLK_PCIE_REQ1#
USB Overcurrent
+3V_S5
USB_OC0 #
USB_OC1 #
USB_OC2 #
USB_OC3 #
TP42
R608 *short_4
R647 *short_4
R344 *short_4
RP2
10
9
8
7 4
10K_10P8R
CLK_PCIE_REQ2#
CLK_PCIE_REQ3#
CLK_PCIE_REQ4#
CLK_PCIE_REQ5#
1
2
3
56
CLK_PCIE_LANN[25]
CLK_PCIE_LANP[2 5]
LANWLANVGA
CLK_PCIE_LAN_REQ#[25]
CLK_PCIE_WLANN[28]
CLK_PCIE_WLANP[28]
PCIE_CLKREQ_WLAN#[28]
CLK_PCIE_VGA#[16 ]
CLK_PCIE_VGA[16]
CLK_PEGA_REQ#[16]
2
Haswell ULT PCH (CLOCK)
HSW_ULT_D DR3L
U37F
C43
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
U2
B41
A41
Y5
C41
B42
AD1
B38
C37
N1
A39
B39
U5
B37
A37
T2
PCIECLKRQ0/GPIO18
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
+3V
+3V
+3V
+3V
+3V
+3V
CLK_PCIE_REQ0#
CLK_PCIE_REQ1#
CLK_PCIE_REQ2#
CLK_PCIE_REQ3#
CLK_PCIE_REQ5#
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLK_PCIE_REQ4#
CLOCK
SIGNALS
6 OF 19
R630 10K_4
R311 10K_4
R607 10K_4
R646 10K_4
R629 10K_4
R685 10K_4
R407 10K_4
R218 10K_4
R217 10K_4
R341 10K_4
R334 *1K_4
XTAL24_IN
XTAL24_OUT
DIFFCLK_BIASREF
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
+3V
+3V
RSVD
RSVD
XTAL24_IN
XTAL24_OUT
A25
B25
K21
M21
C26
C35
C34
AK8
AL8
AN15
AP15
B35
A35
XTAL24_IN
XTAL24_OUT
ICLK_BIAS
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLK_PCH_PCI3
CLK_PCH_PCI4
*18p/50V _4
R707
1M_4
C68
1
C539 12p/50V_4
Y3
24MHz
2 4
1 3
C541 12p/50V_4
R382 3.01K/F_4
R247 TPM@22_4
R248 22_4
R246 22_4
*18p/50V _4
+V1.05S_AXCK_L CPLL
PCLK_TPM [27]
CLK_PCI_LPC [28]
CLK_PCI_EC [31]
CLK_PCIE_XDPN [13]
CLK_PCIE_XDPP [13]
PCLK_TPMCLK_PCI_LPCCLK_PCI_EC
C86
C486
*18p/50V _4
https://t.me/schematicslaptop
A A
5
https://t.me/biosarchive
4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
ZRT/ZRTA
PROJECT :
ZRT/ZRTA
PROJECT :
1
ZRT/ZRTA
of
944
944
944
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LPT 3/6 (PCIE/USB/CLK )
LPT 3/6 (PCIE/USB/CLK )
LPT 3/6 (PCIE/USB/CLK )
Date: Sheet
Date: Sheet of
Date: Sheet of
Wednesday, February 11, 2015
Wednesday, February 11, 2015
3
2
Wednesday, February 11, 2015
3A
3A
3A
5
4
3
2
1
Haswell ULT PCH (GPIO,CPU/MISC,NCTF)
LowHigh
GPIO8
Touch panel No touch panel
TP36
TP72
TP31
TP21
TP30
TP39
BOARD_ID0
GPIO8
LAN_DISABLE#
GPIO15
SKU_ID0
DGPU_PWROK
GPIO24
WK_GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
DGPU_HOLD_RST#
DGPU_PWR_EN
DGPU_PW_CTRL#
MODPHY _EN
GPIO13
GPIO14
GPIO25
GPIO45
ACCEL_INTA
GPIO9
GPIO10
DEVSLP0
BOARD_ID3
DEVSLP1
SKU_ID1
SPKR
D D
C C
GPIO8[23]
GPIO15[8]
DGPU_PWROK[18]
DGPU_HOLD_RST#[16]
DGPU_PWR_EN[39]
MODPHY _EN[34]
ACCEL_INTA[29]
DEVSLP0[27]
SPKR[8,26]
Board ID
R642 SR@10K_4
R325 GS@10K_4
B B
R645 NAC@10K_4
R687 NTPM@10K_4
R656 10K_4
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
R632 DR@10K_4
R324 NGS@10K_4
R644 AC@10K_4
R684 TPM@10K_4
R655 *10K_4
BOARD_ID1[2]
BOARD_ID2[2]
BOARD_ID4[2]
+3V
P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3
AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3
AM3
AM2
P2
C4
L2
N5
V2
RAM ID
U37J
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
SKU ID
UMA Only
dGPU Only
Switchable
(Mux)
Optimize
(Muxless)
R624 IV@10K_4
R331 IV@10K_4
Low
BOARD_ID0
BOARD_ID1
A A
(Default)
BOARD_ID2
BOARD_ID3
BOARD_ID4
No TPM
Non-Dolly
(Default)
5
High
Dual rank SKUsingle rank SKU
ReserveReserved
IOACNo IOAC
TPM
Dolly
HSW_ULT_DDR3L
+3V
+3V_S5
+3V_S5
+3V
+3V
+3V_S5
DSW
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V
+3V
+3V
+3V_S5
+3V_S5
DSW
+3V_S5
+3V_S5
+3V_S5
+3V_S5
SKU_ID1 SKU_ID0 VGA H/W
0
0
1
1
+3V
GPIO
+3V
+3V
+3V
+3V
+3V
SKU_ID0
SKU_ID1
0
1
0
1
4
+3V_S5
10 OF 19
Signal
UMA
GPU
UMA+GPU dGPU/SG UMA boot
UMA
+3V
CPU/
MISC
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
UART0_RTS/GPIO93
SERIAL IO
+3V
UART0_CTS/GPIO94
+3V
+3V
+3V
UART1_RST/GPIO2
+3V
UART1_CTS/GPIO3
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
R623 EV@10K_4
R330 EV@10K_4
Setup
Menu
Hidden
UMA boot
Hidden
GPU boot
UMA/SG
UMA boot
THRMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART1_RXD/GPIO0
UART1_TXD/GPIO1
I2C0 _SDA/G PIO4
I2C0 _SCL /GPIO5
I2C1 _SDA/G PIO6
I2C1 _SCL /GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
+3V
D60
THRMTRIP#
V4
SIO_RCIN#
IRQ_SERIR Q
T4
OPI_COMP2
AW15
AF20
AB21
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
TP_INT_PCH
GPIO84
GPIO85
GPIO86
GPIO87
GPIO88
GPIO89
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
SIO_EXT_SMI#
SIO_EXT_SCI#
DGPU_EVENT#
GC6_FB_EN
I2C0_SDA_ GPIO4
I2C0_SCL _GPIO5
I2C1_SDA_ GPIO6
I2C1_SCL _GPIO7
PCH_ODD_EN
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
R547 49.9/F_4
CPU thermal trip
IMVP_PWR GD_3V
+1.05V_VCCST
THRMTRIP#
IMVP_PWR GD[5,36]
3
TP_INT_PCH [23]
SIO_EXT_SMI# [31]
SIO_EXT_SCI# [31]
DGPU_EVENT# [19]
GC6_FB_EN [17,19]
I2C0_SDA_ GPIO4 [ 29]
I2C0_SCL _GPIO5 [ 29]
I2C1_SDA_ GPIO6 [ 23]
I2C1_SCL _GPIO7 [ 23]
PCH_ODD_EN [27]
+1.05V_VCCST
3
2
1
R281
2
1K_4
1 3
Q21 MMBT3904-7-F
U18
NC1VCC
2
A
GND3Y
74AUP1G07GW
SIO_RCIN# [31]
IRQ_SERIR Q [27,31 ]
GPIO86 [8]
GPIO66 [8]
GPU GC6 2.0 function use
GPIO2/3.
Q22
FDV301N
R292
1K_4
+1.05V_VCCST
5
C255
0.1u/10V_4
4
SYS_SHDN# [33,37]
+3V
12
R301
10K_4
IMVP_PWR GD_3V [7]
2
PCH GPIO PU/PD
IRQ_SERIR Q
DEVSLP0
DEVSLP1
SIO_RCIN#
SIO_EXT_SMI#
SIO_EXT_SCI#
GPIO85
GPIO87
GPIO88
GPIO89
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
R680 *10K_4
R621 *100K_4
R671 *10K_4
high UMA Only
low
R634 EV@100K_4
PCH_ODD_EN
GPIO65
TP_INT_PCH
GPIO84
I2C0_SDA_ GPIO4
I2C0_SCL _GPIO5
GPIO67
GPIO68
GPIO69
DGPU_PWR_EN
I2C1_SDA_ GPIO6
I2C1_SCL _GPIO7
DGPU_HOLD_RST#
GC6_FB_EN
1A-1 20131015 For GC6 NV DG GC6_FB_EN PD.
1A-8 20131022 Change GPIO83/84 GPU GC6 pin
to GPIO2/3.
1A-12 20131029 Change GPIO45 to PU S5,
duble GPIO58 one is GPIO56.
GPU power is control by PCH
GPIO (Discrete, SG or Optimize)
DGPU_PW_CTRL#
DGPU_PWROK
DGPU_PWROK PD on GPU side
LAN_DISABLE#
GPIO8
ACCEL_INTA
GPIO24
GPIO28
GPIO47
GPIO57
GPIO56
GPIO59
GPIO26
GPIO58
GPIO44
GPIO13
GPIO14
GPIO9
GPIO10
GPIO45
GPIO25
WK_GPIO27
1B-7 20131220 Change +3VPCU to +3V_S5
GPIO27 : If not used then use
8.2-kΩ to 10-kΩ pull-down to GND.
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
LPT 4/6 (GPIO/MISC)
LPT 4/6 (GPIO/MISC)
LPT 4/6 (GPIO/MISC)
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Wednesday, February 11, 2015
R643 10K_4
R641 *10K_4
R654 *10K_4
R627 10K_4
R342 10K_4
R668 10K_4
R336 10K_4
R326 10K_4
R348 10K_4
R329 10K_4
R660 10K_4
R661 10K_4
R337 10K_4
R670 10K_4
R669 10K_4
R679 10K_4
R673 10K_4
R322 10K_4
R352 10K_4
R674 2.2K_4
R675 2.2K_4
R677 10K_4
R683 10K_4
R678 10K_4
R620 *10K_4
R349 2.2K_4
R350 2.2K_4
R347 10K_4
R667 *10K_4
R633 IV@1K_4
R321 *10K_4
R224 10K_4
R243 10K_4
R303 *10K_4
R315 10K_4
R609 10K_4
R617 10K_4
R588 10K_4
R310 10K_4
R226 10K_4
R262 10K_4
R288 10K_4
R599 10K_4
R582 10K_4
R302 10K_4
R261 10K_4
R272 10K_4
R309 10K_4
R275 10K_4
R244 *10K_4
R278 *10K_4
R251 *10K_4
R245 10K_4
non deep sx
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZRT/ZRTA
ZRT/ZRTA
ZRT/ZRTA
10 44
10 44
10 44
1
+3V
+3V
+3V_S5
+3VPCU
of
3A
3A
3A
https://t.me/schematicslaptop
https://t.me/biosarchive
5
+1.05V_S5
+1.05V_DCPSUS2
R565 *0_6
+3VPCU
R566 *Short_6
+3V_S5
R380 *short_8
C242 1u/6.3V_4
+1.05V_MODPHY
1.741A
C284
*1u/6.3V_4
R377 *0_6
C278
10u/6.3V_6
C494
1u/6.3V_4
+3VCC_S5
10mA
1u/6.3V_4
0.114A
41mA
C274
22u/6.3V_8
63mA
+V1.05S_AIDLE
C271
+1.05V
+1.05V
25mA
C238
1u/6.3V_4
R397 *short_8
Deep Sx
D D
R286 *0_4
+1.05V_S5
Non Deep Sx
+3V
C C
+1.05V
WW15 4/10 Intel VCCDSW3
G3 can't boot issue.
C492
+PCH_VCCDSW+VCCPDSW
0.47u/25V_6
PCH VCCHSIO Power
B B
1A-1 2013/10/11 del LDO change to MOS.
+1.05V_MODPHY +V1.05S_AUSB3PLL +1.05V_MODPHY +V1.05S_ASATA3PLL
A A
L27 2.2uH/210mA_8
C542
C543
47u/6.3V_8
5
47u/6.3V_8
C524
1u/6.3V_4
2013/10/31 PN change to H=0.85.L17 H=0.9
4
C268 *1u/6.3V_4
C265 1u/6.3V_4
C262 1u/6.3V_4
+V1.05S_AUSB3PLL
+V1.05S_ASATA3PLL
+V1.05S_APLLOPI
+1.05V_DCPSUS3
+V3.3DX_1.5DX_1.8DX_AUDIO
C197 22u/6.3V_8
+3VCC_S5
+VCCPDSW
+V3.3S_VCCPCORE
+V1.05S_AXCK_DCB
+V1.05S_AXCK_LCPLL
C276 1u/6.3V_4
L26 2.2uH/120mA_6
C534
47u/4V_8
4
1.838A
Haswell ULT PCH (Power)
LPT LP POWER
C529
1u/6.3V_4
GPIO/LPC
HSW_ULT _DD R3L
HSIO
OPI
USB3
HDA
VRM
13 OF 19
VCCAPLL power
PCH HDA Power
AA21
AH14
AH13
AH10
AE20
AE21
B18
B11
Y20
W21
AC9
AA9
K19
A20
R21
K18
M20
V21
L10
M9
N8
P9
J13
V8
W9
J18
J17
T21
42mA41mA
K9
C540
47u/4V_8
U37M
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
RSVD
VCCAPLL
VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
3
RTC
SPI
DCPSUSBYP
CORE
DCPSUSBYP
THERMAL SENSOR
SERIAL IO
SUS OSCILLATOR
USB2
L21 2.2uH/210mA_8
*47u/6.3V_8
+V3.3DX_1.5DX_1.8DX_AUDIO
+3V_S5
R222 *Short_6
3
AH11
VCCSUS3_3
AG10
VCCRTC
AE7
DCPRTC
Y8
VCCSPI
AG14
VCCASW
AG13
VCCASW
J11
VCC1_05
H11
VCC1_05
H15
VCC1_05
AE8
VCC1_05
AF22
VCC1_05
AG19
AG20
AE9
VCCASW
AF9
VCCASW
AG8
VCCASW
AD10
DCPSUS1
AD8
DCPSUS1
J15
VCCTS1_5
K14
VCC3_3
K16
VCC3_3
U8
VCCSDIO
T9
VCCSDIO
AB8
DCPSUS4
AC20
RSVD
AG16
VCC1_05
AG17
VCC1_05
C303
11mA
C199
0.1u/10V_4
Place close to ball
+VCCRTCEXT
+V3.3M_PSPI
PCH_VCC_1_1_21
+V1.05S_CORE_PCH
+1.05V_DCPSUS1
+V1.05S_APLLOPI+1.05V
57mA
C293
*47u/6.3V_8
18mA
+PCH_VCCDSW
+V1.05M_VCCASW
109mA
R290 *0_4
C241
1u/6.3V_4
+V3.3S_VCCSDIO
+1.05V_DCPSUS4
+V1.05S_VCCUSBCORE
C282
1u/6.3V_4
2
C243
1u/6.3V_4
+3VCC_S5
1mA
C487
0.1u/10V_4
R320 *Short_6
R318 *0_6
C258
0.1u/10V_4
C232
1u/6.3V_4
C230
1u/6.3V_4
R314 *short_8
C247
22u/6.3V_8
R378 *Short_6
R379 *Short_6
C272
1u/6.3V_4
2.063A
C183
1u/6.3V_4
C239
10u/6.3V_6
R335 *Short_6
+V1.05M_VCCASW
+1.05V_S5
3mA
41mA
C257
0.1u/10V_4
C233
1u/6.3V_4
658mA
C248
1u/6.3V_4
+V1.5S_VCCATS
+V3.3S_VCCPTS
C184
0.1u/10V_4
+1.05V
+1.05V
17mA
R300 *0_ 4
C244
1u/6.3V_4
+1.05V_S5
+1.05V +V1.05S_AXCK_LCPLL
2
C266
1u/6.3V_4
R291 *short_8
C231
1u/6.3V_4
+1.05V +V1.05S_AXCK_DCB
L20 2.2uH/210mA_8
L19 2.2uH/210mA_8
+1.05V
C311
47u/6.3V_8
C292
47u/6.3V_8
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet
1
+3V_RTC
+3V_S5
+3V
R299 *short_8
+1.05V
R364 *Short_6
+1.5V
+3V
+1.05V
+3V
0.2A
C319
C273
1u/6.3V_4
47u/6.3V_8
31mA
C297
C288
1u/6.3V_4
47u/6.3V_8
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
LPT 5/6 (POWER)
LPT 5/6 (POWER)
LPT 5/6 (POWER)
1
ZRT/ZRTA
ZRT/ZRTA
ZRT/ZRTA
11 44
11 44
11 44
3A
3A
3A
of
https://t.me/schematicslaptop
https://t.me/biosarchive
5
4
3
2
1
Haswell ULT (GND)
HSW_UL T_DD R3L
AA58
AB10
AB20
AB22
AC61
AD21
AD63
AE10
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
U37N
A11
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
VSS
A52
VSS
A56
VSS
AA1
VSS
VSS
VSS
VSS
VSS
AB7
VSS
VSS
VSS
AD3
VSS
VSS
VSS
AE5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ13
VSS
AJ14
VSS
AJ23
VSS
AJ25
VSS
AJ27
VSS
AJ29
VSS
14 OF 19
AJ35
VSS
AJ39
VSS
AJ41
VSS
AJ43
VSS
AJ45
VSS
AJ47
VSS
AJ50
VSS
AJ52
VSS
AJ54
VSS
AJ56
VSS
AJ58
VSS
AJ60
VSS
AJ63
VSS
AK23
VSS
AK3
VSS
AK52
VSS
AL10
VSS
AL13
VSS
AL17
VSS
AL20
VSS
AL22
VSS
AL23
VSS
AL26
VSS
AL29
VSS
AL31
VSS
AL33
VSS
AL36
VSS
AL39
VSS
AL40
VSS
AL45
VSS
AL46
VSS
AL51
VSS
AL52
VSS
AL54
VSS
AL57
VSS
AL60
VSS
AL61
VSS
AM1
VSS
AM17
VSS
AM23
VSS
AM31
VSS
AM52
VSS
AN17
VSS
AN23
VSS
AN31
VSS
AN32
VSS
AN35
VSS
AN36
VSS
AN39
VSS
AN40
VSS
AN42
VSS
AN43
VSS
AN45
VSS
AN46
VSS
AN48
VSS
AN49
VSS
AN51
VSS
AN52
VSS
AN60
VSS
AN63
VSS
AN7
VSS
AP10
VSS
AP17
VSS
AP20
VSS
D D
C C
B B
AP22
AP23
AP26
AP29
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR52
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
HSW_UL T_DD R3L
U37O
VSS
VSS
VSS
VSS
AP3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AR5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AU1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
15 OF 19
AV59
VSS
AV8
VSS
AW16
VSS
AW24
VSS
AW33
VSS
AW35
VSS
AW37
VSS
AW4
VSS
AW40
VSS
AW42
VSS
AW44
VSS
AW47
VSS
AW50
VSS
AW51
VSS
AW59
VSS
AW60
VSS
AY11
VSS
AY16
VSS
AY18
VSS
AY22
VSS
AY24
VSS
AY26
VSS
AY30
VSS
AY33
VSS
AY4
VSS
AY51
VSS
AY53
VSS
AY57
VSS
AY59
VSS
AY6
VSS
B20
VSS
B24
VSS
B26
VSS
B28
VSS
B32
VSS
B36
VSS
B4
VSS
B40
VSS
B44
VSS
B48
VSS
B52
VSS
B56
VSS
B60
VSS
C11
VSS
C14
VSS
C18
VSS
C20
VSS
C25
VSS
C27
VSS
C38
VSS
C39
VSS
C57
VSS
D12
VSS
D14
VSS
D18
VSS
D2
VSS
D21
VSS
D23
VSS
D25
VSS
D26
VSS
D27
VSS
D29
VSS
D30
VSS
D31
VSS
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D50
D51
D53
D54
D55
D57
D59
D62
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
H13
HSW_UL T_DD R3L
U37P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G3
VSS
G5
VSS
G6
VSS
G8
VSS
VSS
16 OF 19
VSS_SENSE
H17
VSS
H57
VSS
J10
VSS
J22
VSS
J59
VSS
J63
VSS
K1
VSS
K12
VSS
L13
VSS
L15
VSS
L17
VSS
L18
VSS
L20
VSS
L58
VSS
L61
VSS
L7
VSS
M22
VSS
N10
VSS
N3
VSS
P59
VSS
P63
VSS
R10
VSS
R22
VSS
R8
VSS
T1
VSS
T58
VSS
U20
VSS
U22
VSS
U61
VSS
U9
VSS
V10
VSS
V3
VSS
V7
VSS
W20
VSS
W22
VSS
Y10
VSS
Y59
VSS
Y63
VSS
V58
VSS
AH46
VSS
V23
VSS
E62
VSS_SENS E_R
AH16
VSS
U37R
AT2
RSVD
AU44
RSVD
AV44
RSVD
D15
RSVD
F22
RSVD
H22
RSVD
J21
RSVD
R672 *short_4
R665 100/F_4
HSW_UL T_DD R3L
N23
RSVD
R23
RSVD
T23
RSVD
U10
RSVD
AL1
RSVD
AM11
RSVD
AP7
RSVD
AU10
RSVD
AU15
RSVD
AW14
RSVD
AY14
18 OF 19
VSS_SENS E [36]
RSVD
https://t.me/schematicslaptop
https://t.me/biosarchive
U37Q
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
TP_DC_TEST_AY60
TP66
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
A A
5
TP112
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
4
HSW_UL T_DD R3L
17 OF 19
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
3
A3
DC_TEST_A3_B3
A4
TP_DC_TEST_A4
TP_DC_TEST_A60
A60
A61
DC_TEST_A61_B61
TP_DC_TEST_A62
A62
AV1
TP_DC_TEST_AV1
AW1
TP_DC_TEST_AW 1
AW2
DC_TEST_AY2_AW2
AW3
DC_TEST_AY3_AW3
AW61
DC_TEST_AY61_AW61
AW62
DC_TEST_AY62_AW62
AW63
TP_DC_TEST_AW 63
TP113
TP110
TP107
TP69
TP71
TP67
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Wednesday, February 11, 2015
Wednesday, February 11, 2015
2
Wednesday, February 11, 2015
PROJECT :
LPT 6/6 (GND)
LPT 6/6 (GND)
LPT 6/6 (GND)
ZRT/ZRTA
ZRT/ZRTA
ZRT/ZRTA
1
of
12 44
12 44
12 44
3A
3A
3A
5
4
3
2
1
H_SYS_PW ROK_XDP
D D
C C
XDP_DBRESET_N
R274 *1K_4
R613 *1K_4
https://t.me/schematicslaptop
https://t.me/biosarchive
B B
R137 *0_6
APS
CN2
1
APS1
APS3
APS7
R133 *0_6
R130 *0_4
R132 *0_6
R138 *0_4
R139 *0_4
R142 *0_4
R131 *0_6
R144 *0_4
R146 *0_4
R149 *0_4
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
A A
14
14
15
15
16
16
17
17
18
18
*ACES_88511-180N
5
+3V_S5
+3V
HWPG_1.0 5V_S5[31,34]
SYS_PWROK[7]
APS3
+3VCC_S5
SYS_RESET#
R125 *1K_4
R273 *0_4
R136 *0_6
SUSB# [7,31]
PCH_SLP_S5# [7]
SUSC# [7,31]
PCH_SLP_A# [7]
RTC_RST# [8]
NBSWON# [ 29,31]
SYS_RESET# [7]
4
XDP_PREQ#[4]
XDP_PRDY#[4]
CFG0[6]
CFG1[6]
CFG2[6]
CFG3[6]
XDP_BPM#0[4]
XDP_BPM#1[4]
CFG4[6,8]
CFG5[6]
CFG6[6]
CFG7[6]
PWR_DEBUG[5]
CLK_SDATA[8,14,15,29]
CLK_SCLK[8,14,15,29]
XDP_TCK1[8]
XDP_TCK0[4,8]
APS7APS1
+3VPCU
+3VPCU
VCCST_PWRGD[5]
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
VCCST_PWRGD_XDP
NBSWON#
H_SYS_PW ROK_XDP
2
U14
NC1VCC
A
GND3Y
*74AUP1G07GW
3
TP98
TP101
TP33
TP73
TP80
TP78
TP48
TP105
TP81
TP82
TP38
TP64
TP12
TP45
TP27
TP23
TP24
TP76
TP50
5
C198
*0.1u/10V_4
4
TP79
TP75
TP84
TP86
TP34
TP41
TP89
TP90
TP94
TP92
TP93
TP95TP37
TP122
TP127
TP20
TP88
TP14
TP19
TP15
TP18
XDP_TDO[8]
XDP_TMS[8]
XDP_TDI[8]
+1.05V
+3V
12
XDP_TDO
XDP_TDI
XDP_TMS
XDP_TRST_N
R216
*10K_4
NOA_STBP_0
NOA_STBN_0
CFG8
CFG9
CFG10
CFG11
NOA_STBP_1
NOA_STBN_1
CFG12
CFG13
CFG14
CFG15
CK_XDP_P_R
CK_XDP_N_R
XDP_RST_R_N
XDP_DBRESET_N
XDP_TDO
XDP_TRST_N
XDP_TDI
XDP_TMS
+3V
NOA_STBP_0 [6]
NOA_STBN_0 [ 6]
CFG8 [6]
CFG9 [6]
CFG10 [6]
CFG11 [6]
NOA_STBP_1 [6]
NOA_STBN_1 [ 6]
CFG12 [6]
CFG13 [6]
CFG14 [6]
CFG15 [6]
R721 *0_4
R720 *0_4
R225 *1K_4
R616 *0_4
R198 *51_4
C180
*0.1u/10V_4
U13
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
*74CBTLV3126
2
SYS_RESET#
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Date: Sheet of
Date: Sheet of
CLK_PCIE_XDPP [9]
CLK_PCIE_XDPN [9]
PLTRST# [7,16,25,27,28,31]
+1.05V_S5
3
1B
6
2B
8
3B
11
4B
15
DPAD
7
GND
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CPU/PCH XDP
CPU/PCH XDP
CPU/PCH XDP
XDP_TDO_CPU [4]
XDP_TDI_CPU [4]
XDP_TMS_CPU [4]
XDP_TRST# [4,8]
ZRT/ZRTA
ZRT/ZRTA
ZRT/ZRTA
13 44
13 44
13 44
1
3A
3A
3A
of
https://t.me/schematicslaptop
https://t.me/biosarchive
1
M_A_A[15:0][3]
A A
M_A_BS#0[3]
M_A_BS#1[3]
M_A_BS#2[3]
M_A_CS#0[3]
M_A_CS#1[3]
M_A_CLK0[3]
M_A_CLK0#[3]
M_A_CLK1[3]
M_A_CLK1#[3]
M_A_CKE0[3]
M_A_CKE1[3]
M_A_CAS#[3]
M_A_RAS#[3]
R119 10K_4
R116 10K_4
1A-8
2013/10/23 Change DIMM1_SA0/SA1
B B
to DIMM0_SA0/SA1.
+1.35V_SUS
C78
10u/6.3V_6
+3V
1A-2
Place these Caps near SO-DIMM
C111
10u/6.3V_6
C77
10u/6.3V_6
C106
2.2u/6.3V_6
1
C C
D D
M_A_WE#[3]
CLK_SCLK[8,13,15,29]
CLK_SDATA[8,13,15,29]
M_A_ODT0_DIMM[4]
M_A_ODT1_DIMM[4]
M_A_DQS[7:0][3]
M_A_DQS#[7:0][3]
2013/10/16 Chage net name M_B_DQS#[7:0] to
M_A_DQS#[7:0].
C75
C110
10u/6.3V_6
10u/6.3V_6
C112
10u/6.3V_6
+DDR_VTT_RUN
C101
0.1u/10V_4
C81
1u/6.3V_4
C80
0.1u/10V_4
C113
0.1u/10V_4
C82
1u/6.3V_4
2
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
DIMM0_SA0
DIMM0_SA1
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
C114
0.1u/10V_4
2
C79
0.1u/10V_4
C115
0.1u/10V_4
C103
1u/6.3V_4
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
116
120
11
28
46
63
136
153
170
187
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
JDIM1A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
PC2100 DDR3 SDRAM SO-DIMM
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DDR3-DIMM1_H=4.0_STD
+SMDDR_VREF_D IMM
+
C107
C74
330u/2V_7343
0.1u/10V_4
C109
C98
1u/6.3V_4
4.7u/10V_6
3
(204P)
2.2u/6.3V_6
3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
C76
4.7u/10V_6
0.1u/10V_4
C84
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
+SMDDR_VREF_D Q0
C100
C99
2.2u/6.3V_6
C88
4.7u/10V_6
4
M_A_DQ2 [3]
M_A_DQ6 [3]
M_A_DQ7 [3]
M_A_DQ3 [3]
M_A_DQ0 [3]
M_A_DQ1 [3]
M_A_DQ5 [3]
M_A_DQ4 [3]
M_A_DQ9 [3]
M_A_DQ8 [3]
M_A_DQ15 [3]
M_A_DQ11 [3]
M_A_DQ12 [3]
M_A_DQ13 [3]
M_A_DQ14 [3]
M_A_DQ10 [3]
M_A_DQ16 [3]
M_A_DQ17 [3]
M_A_DQ19 [3]
M_A_DQ18 [3]
M_A_DQ21 [3]
M_A_DQ20 [3]
M_A_DQ23 [3]
M_A_DQ22 [3]
M_A_DQ25 [3]
M_A_DQ24 [3]
M_A_DQ31 [3]
M_A_DQ26 [3]
M_A_DQ28 [3]
M_A_DQ29 [3]
M_A_DQ27 [3]
M_A_DQ30 [3]
M_A_DQ33 [3]
M_A_DQ32 [3]
M_A_DQ35 [3]
M_A_DQ34 [3]
M_A_DQ36 [3]
M_A_DQ37 [3]
M_A_DQ39 [3]
M_A_DQ38 [3]
M_A_DQ46 [3]
M_A_DQ44 [3]
M_A_DQ41 [3]
M_A_DQ45 [3]
M_A_DQ40 [3]
M_A_DQ42 [3]
M_A_DQ43 [3]
M_A_DQ47 [3]
M_A_DQ49 [3]
M_A_DQ52 [3]
M_A_DQ54 [3]
M_A_DQ53 [3]
M_A_DQ48 [3]
M_A_DQ55 [3]
M_A_DQ51 [3]
M_A_DQ50 [3]
M_A_DQ56 [3]
M_A_DQ60 [3]
M_A_DQ58 [3]
M_A_DQ62 [3]
M_A_DQ57 [3]
M_A_DQ61 [3]
M_A_DQ63 [3]
M_A_DQ59 [3]
CHA
CHB
4
+VREF_CA_CP U
M3 solution
+VREFDQ_SA_ M3
M3 solution
SA0SA1
00
01
5
DDR3_DRAMRST#[4,15]
R80 *S hort_6
R129 *Short_6
5
R104 *10K_4
+3V
+SMDDR_VREF_D Q0
+SMDDR_VREF_D IMM
R81 2/F_6
C69
0.022u/16V_4
1 2
R89
24.9/F_4
R118 2/F_6
C104
0.022u/16V_4
1 2
R126
24.9/F_4
6
+1.35V_SUS
2.48A
+3V
PM_EXTTS#0
C83 *0.1u/10V_4
+SMDDR_VREF_D Q0
M1 solution
+1.35V_SUS
R90
1.8K/F_4
R79
1.8K/F_4
M1 solution
+1.35V_SUS
R127
1.8K/F_4
R128
1.8K/F_4
6
7
JDIM1B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDR3-DIMM1_H=4.0_STD
Vref_CA
+SMDDR_VREF_D IMM
C66
470p/50V_4
Vref_DQ
+SMDDR_VREF_D Q0
C105
470p/50V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Wednesday, February 11, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
190
VSS50
195
VSS51
196
VSS52
(204P)
PC2100 DDR3 SDRAM SO-DIMM
203
VTT1
204
VTT2
205
GND
206
GND
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
DDR3 MEMORY SO-DIMM A
DDR3 MEMORY SO-DIMM A
DDR3 MEMORY SO-DIMM A
7
+DDR_VTT_RUN
ZRT/ZRTA
ZRT/ZRTA
ZRT/ZRTA
8
of
14 44
14 44
14 44
8
3A
3A
3A
https://t.me/schematicslaptop
https://t.me/biosarchive
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