How it Works
Acer
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Aspire E5-476
Schematics
44 pgs1.46 Mb0
User manual
91 pgs1.32 Mb0

Acer Aspire E5-476 Schematics

5
www.schematic-x.blogspot.com
4
3
2
1
01
D D
Cardreader
C C
CONN. 2in 1
P28
I/O board
B B
Z8VR Serials SKL ULT SYSTEM BLOCK DIAGRAM
DDR4-SODIMM CHA
DDR4-SODIMM CHB
SATA - HDD
SATA ODD
RTS5170 (cardreader)
POA
CCD(Camera)
Touch Screen
Blue Tooth
I/O Board Conn.USB2 IO*1
Dual Channel DDR IV 1066/1333/1600 MHZ
P12
P13
P25
P25
USB2-3
P28
USB2-3
P25
USB2-7
P21
P21
P26
P28
USB2-6
USB2-5
USB2-4
Azalia
P6
SATA0
SATA1
BATTERY
SKY LAKE ULT 15W
MCP 1356pins
IMC
DC+GT3e
42 mm X 24 mm
SATA
Integrated PCH
USB2.0
DMIC_CLK0 DMIC_DATA0
RTC IHDA
P2~P10
LPC
PCI-E x4 TX/RX
CLK
eDP
USB3.0/2.0
CLK
PCI-E x1
CLK I2C_0
SPI
DP
PCIE1-4
EDP
DDI2
DDI1
USB3-1 & USB3-2
USB2-1 & USB2-2
X'TAL
32.768KHz
X'TAL 24MHz
SPI ROM 8M
N16S-GT
P7
GPU
P14~P18
RTD2166-CG
P20
PTN3366BS
P22
X'TAL 27MHz
PCIE-6
PCIE-5
VRAM
GDDR5
eDP Conn.
VGA Conn.
HDMI Conn.
P21
P21
P22
USB3 Port MB side CN13 -> USB3 port 2 ( up ) CN16 -> USB3 port 1 ( down )
MINI CARD WLAN+BT
RTL8111H
10/100/1G
P19
P26
P23
X'TAL 25MHz
IV@ : iGPU EV@ : Optimus KBL@ : Keyboard backlight TPM@ : TPM NTPM@: Non TPM GS@ : G-SENSOR NGS@ : NonG-SENSOR TDI@ : TOUCH PAD I2C TSU@ : TOUCH SCREEN USB TSI@ : TOUCH SCREEN I2C GT3@ : GT3 CPU NAC@ : Non IOAC IOAC@ : For IOAC FPD@ :PBA
P28
RJ45
P23
BOM
K/B BL Con.
EC
IT8987
P27
Touch PAD
TPM(option)
P29
HALL SENSOR
P27
3
P17
Fan Driver
(Fan signal)
P27
P25
2
BQ24780RUYR
Batery Charger
RT6575AGQ
+3V/+5V
RT8237CZQW
+1V_S5
NB681GD-Z
+VCCOPC/+VCCEOPIO
G5316RZ1D
+1.2VSUS
P30
MDV1528Q
+5V_S5/+3V_S5/+3V/+5V
P31
ISL95859HRTZ-T
+VCORE/VCCSA/VCCGT
P32
P33
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Thermal Protection
P34
UP1658RQKF
+VGPU_CORE
P31
RT8068AZQW
P35
+1.05V_GFX/+3V_GFX +1.5V_GFX
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
P7
Block Diagram
Block Diagram
Block Diagram
1
Z8VR
Z8VR
Z8VR
D-MIC
Int. D-MIC
P24
Universal HP
A A
5
ALC255
AUDIO CODEC
P24 P24
Speaker*2
P24
LED
4
K/B Con.
P27
P27
P38
P39
P40
1A
1A
1 46Thursday, June 22, 2017
1 46Thursday, June 22, 2017
1 46Thursday, June 22, 2017
1A
5
4
3
2
1
Skylake ULT (DISPLAY,eDP)
AT16 AU16
D63 A54 C65 C63 A65
C55 D55 B54 C56
A6
A7 BA5 AY5
H66 H65
SKL_ULT
DDI
DISPLAY SIDEBANDS
+3V_S5 +3V_S5
+3V_S5 +3V_S5
+3V_S5 +3V_S5
U34D
CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#
CPU MISC
BPM#[0] BPM#[1] BPM#[2] BPM#[3]
GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3
PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP
SKL_ULT/BGA
SKL_ULT
1 OF 20
+3V_S5 +3V_S5 +3V_S5 +3V_S5
EDP
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
4 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP
GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
JTAG
PROC_TCK
PROC_TDI PROC_TDO PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS
PCH_TRST#
JTAGX
EDP_TXN0
C47
EDP_TXP0
C46
EDP_TXN1
D46
EDP_TXP1
C45
EDP_TXN2
A45
EDP_TXP2
B45
EDP_TXN3
A47
EDP_TXP3
B47
EDP_AUXN
E45
EDP_AUXP
F45 B52 G50
F50
CRT_AUX#_C
E48
CRT_AUX_C
F48 G46 F46
INT_HDMI_HPD
L9
CRT_HPD
L7
SIO_EXT_SMI#
L6
SIO_EXT_SCI#
N9
EDP_HPD
L10
PCH_BLON
R12
PCH_BRIGHT
R11
EDP_VDD_EN
U13
XDP_TCK0
B61
XDP_TDI_CPU
D60
XDP_TDO_CPU
A61
XDP_TMS_CPU
C60
XDP_TRST#
B59
XDP_TCK1
B56
XDP_TDI_CPU
D59
XDP_TDO_CPU
A56
XDP_TMS_CPU
C59
XDP_TRST#
C61
XDP_TCK0
A59
If use Intel DCI USB 3.0 fixture need to short
1. XDP_TDO <--> XDP_TDO_CPU
2. XDP_TDI <--> XDP_TDI_CPU
3. XDP_TMS <--> XDP_TMS_CPU
R432 *0_4 R444 *0_4
R703 0_4 R704 0_4
EDP_TXN0[20] EDP_TXP0[20] EDP_TXN1[20] EDP_TXP1[20] EDP_TXN2[20] EDP_TXP2[20] EDP_TXN3[20] EDP_TXP3[20]
EDP_AUXN [20] EDP_AUXP [20]
PCH_BRIGHTDP_UTIL
PCH_BLON [20] PCH_BRIGHT [20]
EDP_VDD_EN [20]
CRT_AUXN [19] CRT_AUXP [19]
INT_HDMI_HPD [21] CRT_HPD [19]
TP14
SIO_EXT_SCI# [28] EDP_HPD [20]
eDP Panel
Reserve 2 Lane for 4K x 2K
PCH JTAG
JTAG_TCK,JTAG_TMS Trace Length < 9000mils
TCK,TMS Trace Length < 9000mils
H_PWRGOOD (50ohm) Trace Length: 1~11.25 inches
Don't stuff if we use DP to VGA IC
CRT_AUXN CRT_AUXP
CRT_DATA CRT_CLK
12/25 Change R134
SIO_EXT_SMI# SIO_EXT_SCI#
CRT_HPD EDP_HPD
R424 *100K_4 R423 *100K_4
R135 2.2K_4 R134 *2.2K_4
、
R135 pull-up to +3V_S5
R115 10K_4 R123 10K_4
R82 100K_4 R84 100K_4
100k pull-down on PCH side
XDP_TDO_CPU XDP_TMS_CPU XDP_TDI_CPU
XDP_TCK0 XDP_TCK1 XDP_TRST#
,XDP_TCK1,XDP_TMS don't need pull up or pull down
R448 51_4 R408 *51_4 R409 *51_4
R447 51_4 R425 *51_4 R446 *51_4
TP53
DGPU_PW_CTRL#
R590 49.9/F_4 R595 49.9/F_4 R100 49.9/F_4 R96 49.9/F_4
U34A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKL_ULT/BGA
CATERR# H_PECI H_PROCHOT#_RH_PROCHOT# CPU_THRMTRIP#
XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3
D D
HDMICRT
+VCCIO
C C
+1V_VCCST
CPU_THRMTRIP#
R4001K_4 R40749.9/F_4
Stuff only for Debug Ramp will not stuff
+VCCIO
R441 1K_4
B B
CATERR#
H_PROCHOT#
H_PROCHOT#[28,29,34]
Avoid 125Mhz
BPM#[0:7] Trace Length 1~6 inches Length match < 300 mils
H_PECI (50ohm) Route on microstrip only Spacing >18 mils Trace Length: 0.4~6.125 iches
INT_HDMITX2N[21] INT_HDMITX2P[21] INT_HDMITX1N[21] INT_HDMITX1P[21] INT_HDMITX0N[21] INT_HDMITX0P[21]
INT_HDMICLK-[21] INT_HDMICLK+[21]
CRT_TXN0[19] CRT_TXP0[19] CRT_TXN1[19]
ITE FAE suggest CAP should be at PCH side.
HDMI_DDCCLK_SW[21]
HDMI_DDCDATA_SW[21]
SM_RCOMP[0:2] Trace length < 500 mils Trace width = 12~15 mils Trace spacing = 20 mils
CRT_TXP1[19]
TP8071
PCH_ODD_EN[24]
eDP_RCOMP Trace length < 100 mils Trace width = 20 mils Trace spacing = 25 mils
H_PECI[28]
THRMTRIP#
DGPU_PW_CTRL#[4]
HDMI_DDCCLK_SW HDMI_DDCDATA_SW
CRT_CLK CRT_DATA
EDP_RCOMP
R8724.9/F_4
R442 499/F_4 R395 100/F_4
TP54 TP52 TP59 TP56
02
+3V
+3V_S5
+3V
MP remove(Intel)
+1V_VCCST
XDP_TCK0 R558 Stuff
+1V_VCCST
+1V_VCCST
2
R414 *1K_4
1 3
Q33 MMBT3904-7-F
3
Q34 FDV301N_G
1
R454 1K_4
2
SYS_SHDN# [28,30,37]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
3
2
Thursday, June 22, 2017
PROJECT :
Skylake 1/4 (DDI/eDP)
Skylake 1/4 (DDI/eDP)
Skylake 1/4 (DDI/eDP)
Z8VR
Z8VR
Z8VR
2 46
2 46
2 46
1
1A
1A
1A
CPU thermal trip
+1V_VCCST
C537
+3V
12
R402 10K_4
IMVP_PWRGD_3V [8]
U27
5
NC1VCC
A A
IMVP_PWRGD[34]
2
A
*0.1u/16V_4
4
GND3Y
*74AUP1G07GW
R401 *0_4
5
IMVP_PWRGD_3V
THRMTRIP#
4
5
4
3
2
1
Change Data and DQS to interleave.
03
SKL ULT (DDR4)SKL ULT (DDR4)
U34C
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKL_ULT/BGA
M_A_ALERT# M_B_ALERT#
REV:E connect to GND
R8746 *10_5%_4
R312 *0_4 R291 *0_4
12
DDR3_DRAMRST# [11,12]
C8795
*0.1u/16V_4
Reserved for ESD Power sequence issue no stuff
2
SKL_ULT
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]
DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]
DDR1_ALERT#
DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1]
DDR CH - B
3 OF 20
DDR_RCOMP[2]
DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]
DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]
DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]
DDR1_MA[3] DDR1_MA[4]
DDR1_PAR
AN45 AN46 AP45 AP46
AN56 AP55 AN55 AP53
BB42 AY42 BA42 AW42
AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52
BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47
AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21
AN43 AP43 AT13 AR18 AT18 AU18
M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7
M_B_A12 M_B_A11 M_B_ACT#
M_B_A13
M_B_A2 M_B_A10
M_B_A1 M_B_A0 M_B_A3 M_B_A4
M_B_DQS#0
M_B_DQS0
M_B_DQS#1
M_B_DQS1
M_B_DQS#2
M_B_DQS2
M_B_DQS#3
M_B_DQS3
M_B_DQS#4
M_B_DQS4
M_B_DQS#5
M_B_DQS5
M_B_DQS#6
M_B_DQS6
M_B_DQS#7
M_B_DQS7
M_B_ALERT# M_B_PARITY
CPU_DRAMRST#
SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2
M_B_A[13:0] M_B_DQS#[7:0] M_B_DQS[7:0]
M_B_CLK0# [12] M_B_CLK1# [12]
M_B_CLK0 [12] M_B_CLK1 [12]
M_B_CKE0 [12] M_B_CKE1 [12]
M_B_CS#0 [12] M_B_CS#1 [12] M_B_ODT0_DIMM [12] M_B_ODT1_DIMM [12]
M_B_BG#0 [12]
M_B_ACT# [12] M_B_BG#1 [12]
M_B_CAS# [12] M_B_WE# [12] M_B_RAS# [12] M_B_BA#0 [12]
M_B_BA#1 [12]
M_B_ALERT# [12]
M_B_PARITY [12]
M_B_A[13:0] [12] M_B_DQS#[7:0] [12] M_B_DQS[7:0] [12]
DRAM COMP
SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
PROJECT :
Skylake 2/3 (DDR3 I/F)
Skylake 2/3 (DDR3 I/F)
Skylake 2/3 (DDR3 I/F)
R598120/F_4 R58980.6/F_4 R596100/F_4
Z8VR
Z8VR
Z8VR
3 46
3 46
1
3 46
1A
1A
1A
M_A_A[13:0] M_A_DQS#[7:0] M_A_DQS[7:0]
SKL_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]
DDR CH - A
2 OF 20
M_A_A[13:0] [11] M_A_DQS#[7:0] [11] M_A_DQS[7:0] [11]
DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]
DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]
DDR0_MA[3] DDR0_MA[4]
DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ
DDR_VTT_CNTL
AU53 AT53 AU55 AT55
BA56 BB56 AW56 AY56
AU45 AU43 AT45 AT43
M_A_A5
BA51
M_A_A9
BB54
M_A_A6
BA52
M_A_A8
AY52
M_A_A7
AW52 AY55
M_A_A12
AW54
M_A_A11
BA54
M_A_ACT#
BA55 AY54
M_A_A13
AU46 AU48 AT46 AU50 AU52
M_A_A2
AY51 AT48
M_A_A10
AT50
M_A_A1
BB50
M_A_A0
AY50
M_A_A3
BA50
M_A_A4
BB52
M_A_DQS#0
AM70
M_A_DQS0
AM69
M_A_DQS#1
AT69
M_A_DQS1
AT70
M_A_DQS#2
BA64
M_A_DQS2
AY64
M_A_DQS#3
AY60
M_A_DQS3
BA60
M_A_DQS#4
BA38
M_A_DQS4
AY38
M_A_DQS#5
AY34
M_A_DQS5
BA34
M_A_DQS#6
BA30
M_A_DQS6
AY30
M_A_DQS#7
AY26
M_A_DQS7
BA26 AW50
AT52 AY67
+VREFDQ_SA_M3
AY68 BA67
AW67
R545 *10K_4
M_A_CLK0# [11]
M_A_CLK0 [11]
M_A_CLK1# [11]
M_A_CLK1 [11]
M_A_CKE0 [11] M_A_CKE1 [11]
M_A_CS#0 [11] M_A_CS#1 [11] M_A_ODT0_DIMM [11] M_A_ODT1_DIMM [11]
M_A_BG#0 [11]
M_A_ACT# [11] M_A_BG#1 [11]
M_A_CAS# [11] M_A_WE# [11] M_A_RAS# [11] M_A_BA#0 [11]
M_A_BA#1 [11]
M_A_ALERT# M_A_PARITY
DDR_VTT_CTRL
M_A_ALERT# [11]
M_A_PARITY [11]
+VREF_CA_CPU
TP77
+VREFDQ_SB_M3
+1.2VSUS +3V_S5
2
1 3
Q36 *DTC144EU
12
C755
0.1u/16V_4
Stuff Q54 for both UMA and GPU in DDR_VTT_CNTL
R544 *100K_4
DDR_VTTT_PG_CTRL [33]
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8
M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
D D
M_A_DQ[63:0][11] M_B_DQ[63:0][12]
C C
B B
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8
M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
U34B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
SKL_ULT/BGA
DRAMRST
+1.2VSUS
A A
CPU DRAM
CPU_DRAMRST#
5
4
12
R577 470_4
R593 0_4
3
5
4
3
2
1
SKL ULT (SIDEBAND ) GPIO
H_PECI (50ohm) If route on microstrip, Spacing need >18 mils Trace Length: 2~15 iches
H_PWRGOOD (50ohm)
D D
+3V_S5
I2C0_SDA
R1372.2K_4
I2C0_SCL
R1252.2K_4
I2C1_SDA
R119*2.2K_4
I2C1_SCL
R126*2.2K_4
Trace Length: 1~11.25 inches
Touch PAD Touch Screen
PU 2.2K for touch pad I2C bus(400 KHz)
+3V
+3V
C C
DGPU_PW_CTRL#
DGPU_PW_CTRL#[2]
R208 EV@100K_4
UMA Only
SG/Optimise
GPU Control PU/PD
DGPU_PWR_EN
R575*EV@10K_4
R192GC6@10K_4
20131015 For GC6 NV DG GC6_FB_EN PD.1A-1
R197 EV@10K_4
UMA Only
high
GPU power is control by PCH GPIO (Discrete, SG or Optimize)
low
DGPU_PW_CTRL#
DGPU_PWROK
DGPU_PWROK PD on GPU side
DGPU_PW_CTRL#
1
0
GC6_FB_EN
DGPU_HOLD_RST#
VGA H/W Signal
UMA
GPU
R587*EV@100K_4
R209 IV@1K_4
R104 *EV@10K_4
Setup Menu
Hidden
UMA boot
Hidden
GPU boot
R188*GC6@10K_4
+3V
SPKR
PCH_AZ_CODEC_SYNC[23]
PCH_AZ_CODEC_BITCLK[23]
PCH_AZ_CODEC_SDOUT[23]
PCH_AZ_CODEC_SDIN0[23]
PCH_AZ_CODEC_RST#[23]
545659-103
UART2 for RMT
Touch PAD
Touch Screen
HDA
R549 *20K/F_4
Add GPU Power Control Siganls
TP4398
DGPU_HOLD_RST#[14]
DGPU_PWR_EN[40]
DGPU_PWROK[14,16] GC6_FB_EN[15,17]
DGPU_EVENT#[17]
ACCEL_INTA[26]
ODD_PRSNT#[24]
TPD_INT#[26,28]
TP_INT_PCH[20]
I2C0_SDA[26] I2C0_SCL[26]
I2C1_SDA[20] I2C1_SCL[20]
C644 *10p/50V_4 R583 33_4
R553 33_4 R569 33_4
R560 33_4
C636 *10p/50V_4
TP70 TP57
Strapping
SPKR[23]
TPD_INT#
UART2_RXD UART2_TXD UART2_RTS# UART2_CTS#
I2C0_SDA I2C0_SCL
I2C1_SDA I2C1_SCL
HDA_SYNC_R HDA_BCLK_R HDA_SDO_R
HDA_RST#_R
C8796 *10p/50V_4
DMIC_CLK0_R DMIC_DATA0_R
SPKR
GSPI0_MOSI
GSPI1_MOSI
Skylake-U Strapping Table
Pin Name Strap description
GPP_B14 (SPKR)
B B
GPP_B18 (GSPI0_MOSI)
GPP_C2 (SMBALERT#)
GPP_B22 (GSPI1_MOSI)
GPP_C5 (SML0ALERT#)
SPI0_MOSI
SPI0_MISO
GPP_B23 (SML1ALERT# /PCHHOT#)
SPI0_IO2
A A
SPI0_IO3
HDA_SDO / I2S_TXD0
GPP_E19 (DDPB_CTRLDATA)
GPP_E21 (DDPC_CTRLDATA)
Top-Block Swap override PCH_PWROK
No reboot PCH_PWROK
TLS Confidentiality
Boot BIOS Strap Bit (BBS)
eSPI or LPC
Reserved
Reserved
Reserved
Reserved
Reserved
Flash Descriptor Security Override / Intel ME Debug Mode
Display Port B Detected
Display Port C Detected
5
Sampled
RSMRST#
PCH_PWROK
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
PCH_PWROK
PCH_PWROK
PCH_PWROK
Configuration note
0 = *Disable Top Swap (iPD 20K)
1 = Enable Top Swap Mode
0 = *Disable No Reboot (iPD 20K)
1 = Enable No Reboot Mode
0 = *Disable Intel ME Cryp to TLS(iPD 20K)
1 = Enable Intel ME Cryp to TLS
0 = *SPI (iPD 20K)
1 = LPC
0 = *LPC is selected for EC (iPD 20K)
1 = eSPI selected for EC
+3V
+3V
+3V_S5
+3V
+3V_S5
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
(iPD 20K)
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
0 = *Enable security in the Flash Description (iPD 20K)
1 = Disable Flash Descriptor Security (Override)
0 = *Port B is not detected (iPD 20K)
1 =Port B is detected
0 = *Port C is not detected (iPD 20K)
1 =Port C is detected
4
change location to near CPU to prevent impact HDA_SDO signal
HDA_SDO_R
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
R550 *1K_4
R543 *1K_4
R144 *10K_4
R191 *1K_4
R481 *1K_4
R570 1K_4
U34F
LPSS ISH
SKL_ULT/BGA
U34G
AUDIO
+3V_S5
SKL_ULT/BGA
SPKR
GSPI0_MOSI
GSPI1_MOSI
3
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5
+3V_S5 +3V_S5
+1.8V_S5 +1.8V_S5
+1.8V_S5 +1.8V_S5
+1.8V_S5 +1.8V_S5
+3V_S5
+1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5
+3V_S5 +3V_S5
+3V_S5 +3V_S5
ME_WR#[28]
SKL_ULT
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5
SKL_ULT
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5
SMBALERT#[7]
SML0ALERT#[7]
+3V_S5 +3V_S5 +3V_S5 +3V_S5
GPP_D5/ISH_I2C0_SDA
+3V_S5
GPP_D6/ISH_I2C0_SCL
+3V_S5
GPP_D7/ISH_I2C1_SDA
+3V_S5
GPP_D8/ISH_I2C1_SCL
+3V_S5
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
+1.8V_S5
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
+1.8V_S5
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
6 OF 20
SD GPI SD GPI SD GPI SD GPI SD GPI SD GPI SD GPI SD GPI
GPP_A17/SD_PWR_EN#/ISH_GP7
7 OF 20
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
GPP_A12/BM_BUSY#/ISH_GP6
+3V_S5
SDIO/SDXC
GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3
GPP_G5/SD_CD# GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
+1.8V_S5
GPP_D9 GPP_D10 GPP_D11 GPP_D12
GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5
AB11 AB13 AB12 W12 W11 W10 W8 W7
BA9 BB9
AB7
AF13
P2 P3 P4 P1
M4 N3
N1 N2
AD11 AD12
U1 U2 U3 U4
AC1 AC2 AC3 AB4
AY8 BA8 BB7 BA7 AY7 AW7 AP13
R148200/F_4
2
Reserve UART FFC TP for Win 7 debug
UART2_RXD
TP68
UART2_TXD
TP69
UART2_RTS#
TP67
UART2_CTS#
TP66
Touchpad INT
TPD_INT#
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
R490 *49.9K/F_4 R489 *49.9K/F_4 R484 *49.9K/F_4 R488 *49.9K/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Skylake 6/7 (PEG/DMI/FDI)
Skylake 6/7 (PEG/DMI/FDI)
Skylake 6/7 (PEG/DMI/FDI)
Thursday, June 22, 2017
Thursday, June 22, 2017
Thursday, June 22, 2017
+3V_S5
R117TDI@10K_4
1
+3V_S5
Z8VR
Z8VR
Z8VR
4 46
4 46
4 46
04
1A
1A
1A
5
Backside cap
C203 1U/6.3V_2
C247 22u/6.3V_6
C227 22u/6.3V_6
C132 22u/6.3V_6
C301 22u/6.3V_6
C273 22u/6.3V_6
C209 22u/6.3V_6
C228 22u/6.3V_6
Backside cap
C300
C235 1U/6.3V_2
C275 22u/6.3V_6
C575 10u/6.3V_4
C208 22u/6.3V_6
C312 1U/6.3V_2
D D
C107 22u/6.3V_6
C269
10u/6.3V_4
10u/6.3V_4
Backside cap
C327 22u/6.3V_6
C545 10u/6.3V_4
C223 1U/6.3V_2
10u/6.3V_4
C204 1U/6.3V_2
Backside cap
C279 10u/6.3V_4
C230 10u/6.3V_4
C267 10u/6.3V_4
C581 10u/6.3V_4
C287 1U/6.3V_2
Backside cap
C314
C214
C246
C221 1U/6.3V_2
C8794 *22u/6.3V_6
上件
上件
1U/6.3V_2
C8791 *22u/6.3V_6
+1.2VSUS
1U/6.3V_2
C8792
C8793
*22u/6.3V_6
*22u/6.3V_6
C C
B B
A A
R109 U42@0.0002_5%_8
+VCCCORE
R8740 *U42@0.0002_5%_8
R8741 U22@0_5%_8
+VCCGT
R116 *U22@0_5%_8
Backside cap
For 2+3e CPU
Backside cap
For 2+3e CPU
Backside cap
For 2+3e CPU
1.0V_CPU 3A
+VCCGT_+VCORE
For U42
+VCCGT_+VCORE
For U22
5
10u/6.3V_4
C8789 *22u/6.3V_6
Reserved 01/17
+VCCGT
C375 10u/6.3V_4
Backside cap
+1V_SUS
+VCCIO
+1V_SUS
C195 10u/6.3V_4
C8788 *22u/6.3V_6
R181 0_4
4
C248 22u/6.3V_6
10u/6.3V_4
C580 10u/6.3V_4
C243 10u/6.3V_4
C307 10u/6.3V_4
C8790 *22u/6.3V_6
Under CPU
C140 10u/6.3V_4
C316 10u/6.3V_4
Backside cap
C262
C263
1U/6.3V_2
1U/6.3V_2
C238
C211
1U/6.3V_2
1U/6.3V_2
Backside cap
C407 C360 10u/6.3V_4
1U/6.3V_2
Primary side cap
C421
C466
10u/6.3V_4
10u/6.3V_4
+VDDQC
C322 1U/6.3V_2
R430 0_6
Primary side cap
R81 0_6
R431 0_6
4
+VCCCORE
C284 22u/6.3V_6
C252 10u/6.3V_4
C217 10u/6.3V_4
C315 1U/6.3V_2
C256 10u/6.3V_4
C8787 *22u/6.3V_6
C250
C224
10u/6.3V_4
10u/6.3V_4
C116
C131
10u/6.3V_4
10u/6.3V_4
C261
C212
1U/6.3V_2
1U/6.3V_2
C237
C210
1U/6.3V_2
1U/6.3V_2
+VCCGT
VCCGT_SENSE[34] VSSGT_SENSE[34]
100 ohm Near CPU
C329 1U/6.3V_2
C450
C435
10u/6.3V_4
10u/6.3V_4
+1V_VCCST
C308 10u/6.3V_4
Backside cap
Primary side cap
TP13 TP27
Remove (2017/01/17)
+VCCGT_+VCORE
+VCCGT
C80
C92
10u/6.3V_4
10u/6.3V_4
C241
C215
10u/6.3V_4
10u/6.3V_4
+VCCGT_+VCORE
+VCCGT
+VCCGT
+VCCGT_+VCORE
R8739 U22@0_4
C213
C260
1U/6.3V_2
1U/6.3V_2
C265
C239
1U/6.3V_2
1U/6.3V_2
R83 100/F_4
R78 100/F_4
C410
C355
1U/6.3V_2
1U/6.3V_2
C576
+VCCSTG
1U/6.3V_4
C136 1U/6.3V_4
+VCCPLL
+1.2VSUS
C577 1U/6.3V_4
A30 A34 A39
A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40
AM32 AM33 AM35 AM37 AM38
G30
K32 AK32 AB62
P62
V62
H63
G61
AC63
AE63 AE62
AG62
AL63 AJ62
A48 A53 A58 A62
A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71
AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62 N63 N64 N66 N67 N69
J70
J69
AU23 AU28 AU35 AU42
BB23 BB32 BB41 BB47 BB51
AM40
A18 A22
AL23
K20 K21
SKL_ULT
U34L
CPU POWER 1 OF 4
VCC_A30
S0
VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30
RSVD_K32 RSVD_AK32 VCCOPC_AB62
VCCOPC_P62 VCCOPC_V62
VCC_OPC_1P8_H63 VCC_OPC_1P8_G61 VCCOPC_SENSE
VSSOPC_SENSE VCCEOPIO
S0
VCCEOPIO VCCEOPIO_SENSE
VSSEOPIO_SENSE
SKL_ULT/BGA
SKL_ULT
U34M
CPU POWER 2 OF 4
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
S0
VCCGT
0.55~1.5V
VCCGT VCCGT VCCGT VCCGT
2+3e peak 6A
VCCGT
2+3e TPY 4A
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
VCCGT_SENSE VSSGT_SENSE
SKL_ULT/BGA
SKL_ULT
U34N
CPU POWER 3 OF 4
S3
DDR4
VDDQ_AU23 VDDQ_AU28
1.2V
VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51
VDDQC VCCST
S3
1.0V 120mA
VCCSTG_A22
S0
VCCPLL_OC
S0
1.0V
VCCPLL_K20 VCCPLL_K21
S3
120mA
1.0V
SKL_ULT/BGA
3
VCC
0.55V~1.5V
2+2 peak 24A 2+2 TPY 17A
2+3e peak 24A 2+3e TPY 17A
1.0V
S0
Sx
1.8V
GT3 CPU
3A
1.0V
12 OF 20
VCCGT
S0
0.55~1.5V
2+2 peak 31A 2+2 TPY 15A
2+3e peak 56A 2+3e TPY 17A
VCCGTX
2+2 X
13 OF 20
S0
0.85V/0.95V
3.0A
2A
S0
1.15V
2+2 peak 5A 2+2 TPY 4A 2+3e peak 5.1A 2+3e TPY 5A
1.0V
40mA
260mA
VCCIO_SENSE
VSSSA_SENSE VCCSA_SENSE
14 OF 20
3
3A
50mA
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56 VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66
VCCGTX_SENSE VSSGTX_SENSE
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA
VSSIO_SENSE
VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42
VCC_J30 VCC_J33 VCC_J37
VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43
VCC_SENSE VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62
AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66
AK62 AL61
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
+VCCCORE
G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43
E32 E33
B63 A63 D64
G20
+VCCGT
TP28 TP26
R90 100/F_4
VSASS_SENSE[34] VSA_SENSE[34]
R89 100/F_4
100 ohm near CPU
R29 100/F_4
R32 100/F_4
C119 1U/6.3V_4
Close CPU
C61 47u/6.3V_8
C599 22u/6.3V_6
C598 22u/6.3V_6
C294 U42@22u/6.3V_6
C293 U42@22u/6.3V_6
C291 U42@22u/6.3V_6
+VCCSA
Primary side cap
C66
C531
47u/6.3V_8
47u/6.3V_8
Primary side cap
C106 10u/6.3V_4
+VCCSTG
C83 10u/6.3V_4
+VCCCORE
C122 10u/6.3V_4
100 ohm Near CPU
H_CPU_SVIDART# H_CPU_SVIDCLK H_CPU_SVIDDAT
Primary side cap
C244
C59
47u/6.3V_8
47u/6.3V_8
Primary side cap
C620
C134
22u/6.3V_6
22u/6.3V_6
Primary side cap
C619
C600
22u/6.3V_6
22u/6.3V_6
+VCCGTX_+VCORE
C292 U42@22u/6.3V_6
+VCCGTX_+VCORE
+VCCGTX_+VCORE +VCCGTX_+VCORE
C317 U42@22u/6.3V_6
+VCCIO
Backside cap
C305 10u/6.3V_4
C304 10u/6.3V_4
Primary side cap
C608
C627
1U/6.3V_4
Backside cap
C280 10u/6.3V_4
Backside cap
C194 1U/6.3V_2
1U/6.3V_4
C249 10u/6.3V_4
C303 1U/6.3V_2
+VCCSA
Primary side cap
C245
C133
10u/6.3V_4
10u/6.3V_4
2
C74
C538
47u/6.3V_8
47u/6.3V_8
C573 10u/6.3V_4
VCORE_SENSE [34] VCORESS_SENSE [34]
C302
C219
47u/6.3V_8
47u/6.3V_8
C621
C114
22u/6.3V_6
22u/6.3V_6
C597 22u/6.3V_6
C296 1U/6.3V_2
C605 1U/6.3V_4
C266 10u/6.3V_4
C207 1U/6.3V_2
C231 10u/6.3V_4
2
C534
C56
47u/6.3V_8
47u/6.3V_8
C574
C100
10u/6.3V_4
10u/6.3V_4C558
SVID
H_CPU_SVIDDAT
Place PU resistor close to CPU
Place PU resistor close to CPU
H_CPU_SVIDART#
H_CPU_SVIDCLK
C60 47u/6.3V_8
C617
C277
22u/6.3V_6
22u/6.3V_6
Remove (2017/01/17)
Primary side cap Backside cap
1.U22--->R8744/R8745
2.U42--->R8744/R8745
Imax 3(A)
C297
C320
1U/6.3V_2
1U/6.3V_2
C628 1U/6.3V_4
C222
C236
10u/6.3V_4
10u/6.3V_4
C285
C259
1U/6.3V_2
1U/6.3V_2
C87
C115
10u/6.3V_4
10u/6.3V_4
C138
C570
10u/6.3V_4
10u/6.3V_4C552
+1V_VCCST
Must close to CPU
C535
R418
1000P/50V_4
100/F_4
+1V_VCCST
R393
54.9/F_4
R419 220/F_4
C96 22u/6.3V_6
R8744 U42@0.0002_5%_8
R8745 *U42@0.0002_5%_8
C321 1U/6.3V_2
C311
C288
10u/6.3V_4
10u/6.3V_4
C276
C295
1U/6.3V_2
1U/6.3V_2
C102 10u/6.3V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
+VCCCORE
不上件
上件
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Skylake 12/13/14 (POWER)
Skylake 12/13/14 (POWER)
Skylake 12/13/14 (POWER)
Thursday, June 22, 2017
Thursday, June 22, 2017
Thursday, June 22, 2017
1
H_CPU_SVIDDAT [34]
VR_SVID_ALERT#_VCORE [34]
H_CPU_SVIDCLK [34]
1
Z8VR
Z8VR
Z8VR
05
5 46
5 46
5 46
1A
1A
1A
5
4
3
2
1
Skylake ULT (GPU, SATA , ODD, CLK ,USB2&3)
U34H
PCIE/USB3/SATA
PEG_RX#0[14]
PEG_RX0[14]
SSD
PEG_TX#0[14]
PEG_TX0[14]
PEG_RX#1[14]
PEG_RX1[14]
PEG_TX#1[14]
PEG_TX1[14]
PEG_RX#2[14]
PEG_RX2[14]
PEG_TX#2[14]
PEG_TX2[14]
PEG_RX#3[14]
PEG_RX3[14]
PEG_TX#3[14]
PEG_TX3[14]
SATA_RXN0[24] SATA_RXP0[24]
SATA_TXN0[24] SATA_TXP0[24]
SATA_RXN1[24] SATA_RXP1[24]
SATA_TXN1[24] SATA_TXP1[24]
PCIE_RX5-_LAN[22]
PCIE_RX5+_LAN[22] PCIE_TX5-_LAN[22]
PCIE_TX5+_LAN[22]
PCIE_RX6-_WLAN[25]
PCIE_RX6+_WLAN[25] PCIE_TX6-_WLAN[25] PCIE_TX6+_WLAN[25]
SATA_RXN1/PEG_RXN10_L2[25]
SATA_RXP1/PEG_RXP10_L2[25] SATA_TXN1/PEG_TXN10_L2[25]
SATA_TXP1/PEG_TXP10_L2[25] SATA_RXN3/PEG_RXN9_L0[25]
SATA_RXP3/PEG_RXP9_L0[25] SATA_TXN3/PEG_TXN9_L0[25]
SATA_TXP3/PEG_TXP9_L0[25]
CLK_PCIE_VGA#[14]
CLK_PCIE_VGA[14]
CLK_PEGA_REQ#[14]
CLK_PCIE_NGFF1_N[25] CLK_PCIE_NGFF1_P[25]
PCIE_CLKREQ_NGFF1#[25]
CLK_PCIE_LANN[22] CLK_PCIE_LANP[22]
CLK_PCIE_LAN_REQ#[22]
CLK_PCIE_WLANN[25] CLK_PCIE_WLANP[25]
PCIE_CLKREQ_WLAN#[25]
CLK_PCIE_REQ0# CLK_PCIE_REQ1# CLK_PCIE_REQ2# CLK_PCIE_REQ3# CLK_PCIE_REQ4# CLK_PCIE_REQ5#
5
D D
dGPU PEG*4
HDD
ODD
C C
LAN
WIFI
B B
N16S VGALANWLAN
M.2
A A
C564 EV@0.22u/10V_4 C563 EV@0.22u/10V_4
C550 EV@0.22u/10V_4 C549 EV@0.22u/10V_4
C547 EV@0.22u/10V_4 C548 EV@0.22u/10V_4
C542 EV@0.22u/10V_4 C543 EV@0.22u/10V_4
C560 0.1u/16V_4 C561 0.1u/16V_4
C541 0.1u/16V_4 C540 0.1u/16V_4
R440 100/F_4
TP55 TP51
R258 10K_4 R205 10K_4 R223 *10K_4 R574 *10K_4 R227 10K_4 R210 10K_4
XDP_PRDY# XDP_PREQ# PIRQA#
SATA_RXN1/PEG_RXN10_L2 SATA_RXP1/PEG_RXP10_L2
SATA_TXN1/PEG_TXN10_L2 SATA_TXP1/PEG_TXP10_L2 SATA_RXN3/PEG_RXN9_L0
SATA_RXP3/PEG_RXP9_L0 SATA_TXN3/PEG_TXN9_L0
SATA_TXP3/PEG_TXP9_L0
CLK_PCIE_REQ0#
R259 0_4
CLK_PCIE_REQ1#
R211 0_4
CLK_PCIE_REQ2#
TP31
CLK_PCIE_REQ3#
TP78
CLK_PCIE_REQ4#
R230 0_4
CLK_PCIE_REQ5#
R213 0_4 R330
+3V
C_PEG_TX#0 C_PEG_TX0
C_PEG_TX#1 C_PEG_TX1
C_PEG_TX#2 C_PEG_TX2
C_PEG_TX#3 C_PEG_TX3
PCIE_TX5­PCIE_TX5+
PCIE_TX6­PCIE_TX6+
PCIE_RCOMPN PCIE_RCOMPP
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKL_ULT/BGA
U34J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKL_ULT/BGA
+3V_S5
4
SKL_ULT
+3V_S5 +3V_S5 +3V_S5
8 OF 20
SKL_ULT
CLOCK SIGNALS
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
10 OF 20
add for EC reset RTC
CLR_CMOS[28]
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP
USB2
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5
GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#
GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2
+3V_S5
CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1 RTCX2
SRTCRST#
RTCRST#
R594 100K_4
USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP
USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP
USB2N_1 USB2P_1
USB2N_2 USB2P_2
USB2N_3 USB2P_3
USB2N_4 USB2P_4
USB2N_5 USB2P_5
USB2N_6 USB2P_6
USB2N_7 USB2P_7
USB2N_8 USB2P_8
USB2N_9 USB2P_9
USB2N_10 USB2P_10
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2
GPP_E8/SATALED#
CLK_PCIE_XDPN
F43
CLK_PCIE_XDPP
E43 BA17
SUSCLK
XTAL24_IN
E37
XTAL24_OUT
E35
XCLK_BIASREF
E42
RTC_X1
AM18
RTC_X2
AM20
SRTC_RST#
AN18
RTC_RST#
AM16
3
2
1
Q41 *2N7002K
SRTC_RST#
H8 G8 C13 D13
J6 H6 B13 A13
J10 H10 B15 A15
E10 F10 C15 D15
AB9 AB10
AD6 AD7
AH3 AJ3
AD9 AD10
AJ1 AJ2
AF6 AF7
AH1 AH2
AF8 AF9
AG1 AG2
AH7 AH8
AB6
USBCOMP USB2_ID
AG3 AG4
USB_OC0#
A9
USB_OC1#
C9
USB_OC2#
D9
USB_OC3#
B9 J1
DEVSLP0
J2
DEVSLP1
J3
DEVSLP2
H2
SATAGP0
H3
SATAGP1
G4
R436 0_4
H1
R452 2.7K/F_4
3
USB3_RXN0[27] USB3_RXP0[27] USB3_TXN0[27] USB3_TXP0[27]
USB3_RXN1[27] USB3_RXP1[27] USB3_TXN1[27] USB3_TXP1[27]
1A-1
USBP0-[27] USBP0+[27]
USBP1-[27] USBP1+[27]
USBP2-[27] USBP2+[27]
USBP3-[24] USBP3+[24]
USBP4-[25] USBP4+[25]
USBP5-[20] USBP5+[20]
USBP6-[20] USBP6+[20]
USBP7-[27] USBP7+[27]
R138 113/F_4 R492 1K_4 R185 1K_4
TP6 TP9
SUSCLK[25]
1V power plane
0.71 checklist p14
MB USB3.0 CN16 ( Charger IC ) Down
MB USB3.0 CN13 -> Up
DB USB2.0 POA (Reserved)
BT
Touch Screen
CCD
Card reader
DEVSLP0[24] DEVSLP2[25]
NGFF3_DET[25]
+1V_S5
CLR_CMOS
2
MB USB3.0 CN16 ( Charger IC ) Down
MB USB3.0 CN13 -> Up
USBCOMP Impedance = 50 ohm Trace length < 500 mils Trace spacing = 15 mils
C87970.1u/16V_4
C87980.1u/16V_4
Near CPU 01/17
RTC_RST#
3
Q39 2N7002K
1
C87990.1u/16V_4
C88000.1u/16V_4
USB_OC0#[27] USB_OC1#[27] USB_OC2#[27]
Add SSD ID 1/14
Hight is SSD , Low is ODD
SSD_ID[24]
Skylake-U userd 24 MHz (50 Ohm ESR) XTAL
XTAL24_IN
MB U3 MB U3 DB U2
XTAL24_OUT
Note: Change Y4 to 38.4 MHz(ESR 30 ohm) for Cannonlake U
RTC Clock 32.768KHz (RTC)
Trace length < 1000 mils
RTC Circuitry (RTC)
+3VPCU
On SKL voltage at VCCRTC does not exceed 3.2V
R329
1.5K/F_4
VCCRTC_2
45.3K/F_4
2013/10/16 Chage +3V_RTC_0 to VCCTC_2.
1A-2
1. AHL03003057 DBV CR2032
2. AHL03003003 VDE CR2032
2
PCH PU/PD
USB_OC0# USB_OC1# USB_OC2# USB_OC3#
DEVSLP0 DEVSLP1 DEVSLP2 PIRQA#
SATAGP1
R438 10K_4
C349 6.8p/50V_4
C350 6.8p/50V_4
1B-1
R335 1K_4
12
BT1
BAT_CONN
SATAGP0
R8753 U22@0_4
01/17
R8754 U22@0_4
12
+3V_RTC_2
+3V_RTC_1
+3V_RTC_[0:2] Trace width = 20 mils
BAT54CW_0.2A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
+3V_S5
R411 10K_4 R405 10K_4 R404 10K_4 R422 10K_4
R469 *10K_4 R470 *10K_4 R471 *10K_4 R572 10K_4
R439 *10K_4
+3V_S5
R437 100K_4
C556 U22@10P/50V_4
R426 U22@1M_4
4
3
Y3 U22@24MHz
1
2
C544 U22@10P/50V_4
RTC_X1
R225
Y2
10M_4
32.768KHZ
RTC_X2
+3V_RTC
+3V_RTC
Trace width = 30 mils
D9
R237
20K/F_4
R233
20K/F_4
C363 1u/6.3V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Skylake 9/10 (PEG/USB/CLK)
Skylake 9/10 (PEG/USB/CLK)
Skylake 9/10 (PEG/USB/CLK)
06
+3V
BG624000078 -> HHE(1st) BG624000044 -> TXC(2nd)
CH01006JB08 -> 10p CH01506JB06 -> 15p CH-6806TB01 -> 6.8p
BG3327680C6 -> HHE(1st)
BG332768099 -> TXC(2nd)--EOD Change to BG332768104
RTC_RST#
12
C357
J1
1u/6.3V_4
*JUMP
SRTC_RST#
C354 1u/6.3V_4
Z8VR
Z8VR
Z8VR
6 46
6 46
1
6 46
1A
1A
1A
5
4
3
2
1
+3V_S5
+3V_S5
43
1
+3V_S5
07
R464
2.2K_4
CLK_SDATA [11,12,19,26]
CLK_SCLK [11,12,19,26]
SMB_ME1_CLK SMB_ME1_DAT
U34E
PCH_SPI_CLK PCH_SPI_SO PCH_SPI_SI PCH_SPI_IO2
D D
PCH_SPI_IO3 PCH_SPI_CS0#
For M.2 wifi module must
EC_RCIN#
SIO_RCIN#[28]
IRQ_SERIRQ[24,28]
C C
PCH_SPI_CLK_EC[28]
PCH_SPI_SO_EC[28]
R573 0_4
IRQ_SERIRQ
PCH_SPI_CLK_EC
PCH_SPI_SI_EC[28]
PCH_SPI_SI_EC PCH_SPI_SO_EC
AW13
SP@ socket P/N: DFHS08FS023 only for A-TEST
SPI ROM
Skylake
3.3V
B B
Vender Size Quanta P/N Vender P/N
WND GGD
AKE3EFP0N07
8M
AKE2EZN0Q00
8M
16M
AKE3DZN0Q02 GD25B127DSIGR
16M
W25Q64FVSSIQWND GD25B64CSIGRGGD
W25Q128FVSIQAKE3DZN0N01
SPI - FLASH
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
SPI - TOUCH
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
C LINK
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
GPP_A0/RCIN#
AY11
GPP_A6/SERIRQ
SKL_ULT/BGA
PCH SPI ROM(8M)
15ohm CS01502JB12 33ohm CS03302JB29
PCH_SPI_SO PCH_SPI_SO_EC
1A-13
+3V_S5 +3V_S5
+3V_PCH_ME
SKL_ULT
+3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
PCH_SPI_CS0#
R453 15_4 R457 15_4
3.3K is original and for no support fast read function
LPC
R433 1K_4
SMBUS, SMLINK
+3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5
GPP_B23/SML1ALERT#/PCHHOT#
+3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
GPP_A14/SUS_STAT#/ESPI_RESET#
+3V_S5
+3V_S5
GPP_A9/CLKOUT_LPC0/ESPI_CLK
+3V_S5 +3V_S5
5 OF 20
+3V_LDO_EC
+3V_S5
SPI_SO_8M
SPI_WP_IO2_ME
PCH_SPI_IO2
PCH_SPI_IO3
SPI_CS0#_UR_ME[28]
+3V_PCH_ME
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
R462 *0_6 R475 0_6
1
CS#
2
IO1/DO
3
IO2/WP#
4
GND
W25Q128FV -- 8MB
IO3/HOLD#
PCH_SPI_CLK_EC PCH_SPI_SI_EC
R415 15_4
R477 15_4
R445 10K_4
VCC
CLK
IO0/DI
R428 0_4
PCH_MBCLK0_R
R7
PCH_MBDAT0_R
R8 R10
SMBALERT#
VGA_MBCLK
R9
VGA_MBDATA
W2 W1
SML0ALERT#
SMB_ME1_CLK
W3
SMB_ME1_DAT
V3 AM7
SMB1ALERT#
eSPI change to 15 ohm
AY13
R559 0_4
BA13
R547 0_4
BB13
R556 0_4
AY12
R548 0_4
BA12 BA11
R226 *0_4
C348 *0.1u/16V_4
eSPI change to 15 ohm
AW9
R551 22/J_4
AY9 AW11
R557 22/J_4
R558 22/J_4
CLKRUN#
C8801
C8802
*10p/50V_4
*10p/50V_4
01/17
+3V_PCH_ME
8
SPI_HOLD_IO3_ME
7
SPI_CLK_8M
6
SPI_SI_8M
5
R463 15_4 R468 15_4
SPI_HOLD_IO3_ME
PCH_SPI_CS0#
SPI_CS0#_UR_ME
LPC_LAD0 [24,25,28] LPC_LAD1 [24,25,28] LPC_LAD2 [24,25,28] LPC_LAD3 [24,25,28]
LPC_LFRAME# [24,25,28]
TP36
CLK_PCI_EC [28] PCLK_TPM[24]
C582 0.1u/16V_4U29
R466 1K_4 R461 15_4 R465 15_4
SPI_WP_IO2_ME
reserve for SPI fast read
only 0ohm option
Strapping
SMBALERT# [4]
SML0ALERT# [4]
SMB1ALERT# [26]
ckl v0.71 p.24
CLKRUN# [24,28]
+3V_PCH_ME
PCH_SPI_CLK PCH_SPI_SI
C587 *22p/50V_4
CLK_PCI_LPC [25]
CLKRUN# IRQ_SERIRQ EC_RCIN#
R564 8.2K/F_4 R566 10K_4 R546 10K_4
SMBus
PCH_MBCLK0_R PCH_MBDAT0_R VGA_MBDATA VGA_MBCLK
SMB1ALERT#
Termination Resistor Requirement for PCH PCHHOT# Pin Reserve PU 150K resister
+3V
S5 S0
SMBus(PCH)
PCH_MBDAT0_R
PCH_MBCLK0_R
PCH_XDP_WLAN/S5 DDR_TP/S0
R4732.2K_4 R4722.2K_4 R4792.2K_4 R1452.2K_4
R187*150K_4
Change to 2.2k
Q35
5
2 6
DMN601DWK-7
R456
2.2K_4
SMBus(EC)
2ND_MBCLK[17,28] 2ND_MBDATA[17,28]
2ND_MBCLK 2ND_MBDATA
R480 0_4 R476 0_4
EC/S5
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
5
4
3
2
Thursday, June 22, 2017
PROJECT :
Skylake 5 (SATA/HDA/SPI)
Skylake 5 (SATA/HDA/SPI)
Skylake 5 (SATA/HDA/SPI)
Z8VR
Z8VR
Z8VR
7 46
7 46
1
7 46
1A
1A
1A
5
4
3
2
1
PCI_PLTRST#
SYS_RESET#
R451 10K_4
VCCST_PWRGD
01/17
Near CPU
1 2
C8805 0.1u/16V_4
TP29
PCIE_LAN_WAKE#
For 15" / 17" (R501)
ReserveReserved
(R520)
PCH_RSMRST#
PROC_PWRGD
SYS_PWROK_R EC_PWROK_R
DPWROK_R PCH_ACPRESENT
PCH_SUSPWRDNACK_C
SUSACK#_R
TP25
HighLow
R420 0_4
R568 *0_4
R597 *0_4
+1.8V_S5
For 14" (R495)
(Default) Z8V
(R519)
R580 0_4
+VCCIO
Reserve PU 10K
R450 *10K_4
D D
PROC_PWRGD
EC only PD, so PD 10K
R579 10K_4
RSMRST#[28]
EC_PWROK
PCH_SUSPWRDNACK[28]
PCIE_LAN_WAKE#[22,25]
Board ID
C C
B B
01/17
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
R526 U22@10K_4 R524 10K_4
R506 10K_4 R504 NAC@10K_4 R521 NGS@10K_4 R498 NTPM@10K_4
R495 10K_4 R493 10K_4 R519 *10K_4
VRAM X32 (R506)
Non IOAC (R504)
Non G-sensor (R521)
No TPM (R498)
No-Touch panel
RAM_ID1
R527 U42@10K_4
RAM_ID2
R525 *10K_4
RAM_ID3
R540 *10K_4
Board_ID0
R507 *10K_4
Board_ID1
R505 IOAC@10K_4
Board_ID2
R522 GS@10K_4
Board_ID3
R499 TPM@10K_4
Board_ID4
R500 TSU@10K_4
Board_ID5
R501 *10K_4
Board_ID6
R494 *10K_4
Board_ID7
R520 10K_4
Low
High
VRAM X16 (R507)
IOAC (R505)
G-sensor (R522)
TPM (R499)
Touch panel (R500)
BOARD_ID5
BOARD_ID6
BOARD_ID7 Z8VR
U34K
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
SKL_ULT/BGA
U34I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
SKL_ULT/BGA
Power Sequence
PCH_PWROK[28]
For platforms not supporting Deep Sx, connect directly to RSMRST#
PLTRST# Buffer
+3V
C341 0.1u/16V_4
2
A A
PCI_PLTRST#
1
U8
3 5
MC74VHC1G08
4
12
R212 100K_4
5
R8747 *10_5%_4
C8803
0.1u/16V_4
Reserved for ESD 01/17
PLTRST#[14,22,24,25,28]
SYSPWOK
EC_PWROK
4
SKL_ULT
SYSTEM POWER MANAGEMENT
+3V_S5
I I
+3V_S5
+3V_S5 +3V_S5 +3V_S5
SKL_ULT
+1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5
+1.8V_S5 +1.8V_S5 +1.8V_S5
DPWROK_R PCH_RSMRST#
+3V_S5
+3V_S5 +3V_S5
11 OF 20
GPP_D4/FLASHTRIG
+3V_S5
EMMC
GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
9 OF 20
No Deep Sx
R582 0_4
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5
+3V_S5
GPP_B11/EXT_PWR_GATE#
CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3
CSI2_COMP
EMMC_RCOMP
Remove
R403 *0_4
GPP_B12/SLP_S0#
GPD4/SLP_S3# GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B2/VRALERT#
C37 D37 C32 D32 C29 D29 B26 A26
E13 B7
AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1
AM2 AM3 AP4
AT1
Non Deep Sx
R552 0_4
R410 *10K_4
AT11 AP15 BA16 AY16
AN15 AW15 BB17 AN16
BA15 AY15 AU13
AU11 AP16
INTRUDER# MPHY_EXT_PWR
AM10
PCH_VRALERT#
AM11
R86 100/F_4
RAM_ID1 RAM_ID2 RAM_ID3 Board_ID0 Board_ID1 Board_ID2 Board_ID3 Board_ID4
Board_ID5 Board_ID6 Board_ID7
R542200/F_4
EC_PWROK_R
EC_PWROK[28]
3
SUS0# SUSB# SUSC# PCH_SLP_S5#
PCH_SLP_SUS# PCH_SLP_LAN# PCH_SLP_WLAN# PCH_SLP_A#
PCH_PWRBTN# PCH_BATLOW#
R585 0_4 R584 0_4
R222 1M_4
TP58
Board_ID4[20]
REV:E tPLT17(max 200us) ->SLP_S3# assertion to IMVP VR_ON(VRON) deassertion
VRON_R[34]
SUS0#[31] SUSB#[28,31] SUSC#[28]
TP79 TP23
TP33 TP72
TP75
TP35
TP32
TP30
4
U13 *MC74VHC1G08DFT2G
R244 0_4
Close to CPU
VCCST_PWRGD
C557 1000P/50V_4
Stuff 1000P/50V
DNBSWON#[28] SB_ACDC[28]
+3V_RTC
+3V_S5
C368 *0.1u/16V_4
2
SUSB#
1
VRON
3 5
+1V_VCCST
R427 60.4/F_4
Shortpad change to 60.4 ohm. 11/6
VCCST_PWRGD_EN
2013/10/21 Del APWORK.1A-6
REV:E tPLT15(max 200us)
->SLP_S4# assertion to VDDQ(+1.35VSUS) ramp down start(SUSON)
SUSON_R
SUSON_R[31,33]
VRON[28]
CRB is via +1.05V PGVCCST PWRGD
+3V_S5
U25
5
VCC
C528
R416
0.1u/16V_4
1K_4
VCCST_PWRGD_R
4
R390 *0_4 R391 0_4
2
Y
74AUP1G07GW
08
+3V
+3V_S5
SUSON[28]
B2A S0->S5 & S0->S3 Power of sequence 1us SUSB# -> VCCST_PWRGD
+3V_S5
C529 0.1u/16V_4
2
4
U24 MC74VHC1G08DFT2G
R388 *0_4
Skylake 9/11 (PWROK/Board_ID)
Skylake 9/11 (PWROK/Board_ID)
Skylake 9/11 (PWROK/Board_ID)
SUSB#
VCCST_PWRGD_EN
1
3 5
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Z8VR
Z8VR
Z8VR
1
4
U12 *TC7SH08FU
R235 0_4R538 10K_4
SYS_RESET#
PCH_ACPRESENT PCH_BATLOW#
PCIE_LAN_WAKE# MPHY_EXT_PWRPCH_SUSPWRDNACK_C PCH_VRALERT#
PCH_RSMRST# PCH_PWROK SYS_PWROK_R
+3V_S5
3 5
R429 10K_4
R565 8.2K/F_4 R229 8.2K/F_4
R236 10K_4
R184 *1K_4
R206 10K_4
12/25 Change R206 pull-up to +3V_S5
R567 10K_4 R555 10K_4 R435 10K_4
C361 *0.1u/16V_4
2 1
12/28 Delete U12/C361 & Add R695
SUSC# SUSON
12/28 Delete U14/R245/C372 & Change "MAINON_R" to "MAINON"
1
NC
VCCST_PWRGD_EN_L
2
A
3
GND
PCH_PWROK HWPG
Rev:D change netmane for HWPG
C527
C530
*1000P/50V_4
*1000P/50V_4
HWPG[28]IMVP_PWRGD_3V[2]
Reserve 1000P/50V
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
8 46
8 46
8 46
1A
1A
1A
5
4
3
2
1
U34S
E68
AL25 AL27
BA70 BA68
B67 D65 D67
E70 C68 D68 C67
F71 G69
F70 G68 H70 G71 H69 G70
E63
F63
E66
F66
E60
E8
AY2 AY1
D1 D3
K46
K45
C71
B70
F60
A52
J71 J68
F65 G65
F61
E61
CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]
CFG[16] CFG[17]
CFG[18] CFG[19]
CFG_RCOMP ITP_PMODE RSVD_AY2
RSVD_AY1 RSVD_D1
RSVD_D3 RSVD_K46
RSVD_K45 RSVD_AL25
RSVD_AL27 RSVD_C71
RSVD_B70 RSVD_F60 RSVD_A52 RSVD_TP_BA70
RSVD_TP_BA68 RSVD_J71
RSVD_J68 VSS_F65
VSS_G65 RSVD_F61
RSVD_E61
SKL_ULT/BGA
D D
CFG4
R79 49.9/F_4
+1V_S5
C C
B B
CFG_RCOMP
R88 1.5K/F_4
SKL_ULT
RESERVED SIGNALS-1
19 OF 20
RSVD_TP_BB68 RSVD_TP_BB69
RSVD_TP_AK13 RSVD_TP_AK12
RSVD_BB2 RSVD_BA3
RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2
RSVD_B3 RSVD_A3
RSVD_AW1
RSVD_E1 RSVD_E2
RSVD_BA4 RSVD_BB4
RSVD_A4 RSVD_C4
RSVD_A69 RSVD_B69
RSVD_AY3 RSVD_D71
RSVD_C70 RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
RSVD_TP_AW71 RSVD_TP_AW70
MSM#
PROC_SELECT#
TP5 TP6
TP4
TP1 TP2
BB68 BB69
AK13 AK12
Rev:F reserve TP
BB2 BA3
AU5 AT5
D5 D4 B2 C2
B3 A3
AW1 E1
E2 BA4
BB4 A4
C4 BB5 A69
B69 AY3
R8748 *0_4
D71 C70
C54 D54
AY4 BB3
AY71
R8749 *0_4
AR56 AW71
AW70 AP56
C64
R417 *100K_4
TP24
+1V_VCCST
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5 +1V_S5
+3VPCU +3V_S5
+1.5V
+3V_S5
+1V_S5
+3V_S5 +1V_S5 +1V_S5
+3V
VCCPRIM_1P0 & VCCPRIM_CORE Short
AB19 AB20
C199 1U/6.3V_4
C603 1U/6.3V_4 C8810 22u/6.3V_6 C8811 22u/6.3V_6
C233 1U/6.3V_4
C121 1U/6.3V_4 C117 47u/6.3V_8
C8807 Near CPU
R155 0_6
C111 1U/6.3V_4 C8807 0.1U/16V_4
C8808 0.1U/16V_4
C282 *1U/6.3V_4
R200 *0_6 R194 0_6
R588 0_6 R600 *0_6
C652 1U/6.3V_4
R174 0_6
C108 1U/6.3V_4
C278 1U/6.3V_4 C8815 0.1U/16V_4
C110 1U/6.3V_4
For 2+3e CPU No Stuff
+VCCDSW_1P0
C6231U/6.3V_4
C602 1U/6.3V_4
+VCCPDSW_3P3
C3360.1U/16V_4
+VCCHDA
+VCCPSPI
+VCCPRIM_3P3
AF18 AF19
AB17
AD17 AD18
AJ17 AJ19 AJ16
AF20 AF21
AJ21
AK20
P18
V20 V21
AL1 K17
N15 N16 N17
P15 P16
K15 L15
V15
Y18
T19 T20
N18
U34O
VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0
VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE
DCPDSW_1P0 VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0 VCCMPHYGT_1P0_N15
VCCMPHYGT_1P0_N16 VCCMPHYGT_1P0_N17 VCCMPHYGT_1P0_P15 VCCMPHYGT_1P0_P16
VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0
VCCAPLL_1P0 VCCPRIM_1P0_AB17
VCCPRIM_1P0_Y18 VCCDSW_3P3_AD17
VCCDSW_3P3_AD18 VCCDSW_3P3_AJ17
VCCHDA VCCSPI VCCSRAM_1P0
VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0
VCCPRIM_3P3_AJ21 VCCPRIM_1P0_AK20 VCCAPLLEBB
SKL_ULT/BGA
SKL_ULT
CPU POWER 4 OF 4
1.5V
3.3V
1.0V
1.0V
S5
1.0V
1.0V
30mA 11mA
1.0V
642mA
1.0V
S5
1.0V
22mA
S5
1.0V
1.258A
1.0V
S5
1.0V
S5
3.3V
118mA
3.3V
1.0V
33mA
696mA
2.574A
75mA with AJ21 pin
6mA
26mA
696mA
S5
S5
+3V
75mA 696mA
15 OF 20
44mA
S5
33mA 41mA
VCCPRIM_3P3_V19
1.0V
VCCPRIM_1P0_T1
1.8V
<1mA
VCCRTCPRIM_3P3
3.0V+
RTC
1.0V
135mA
S5
GPP_B0/CORE_VID0 GPP_B1/CORE_VID1
S5 S5
VCCATS_1P8
VCCRTC_AK19 VCCRTC_BB14
GPIO Group Power Plane
AK15
VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF
VCCPGPPG
DCPRTC VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6
+VCCPGPPA
AG15
+VCCPGPPB
Y16
+VCCPGPPC
Y15
+VCCPGPPD
T16
+VCCPGPPE
AF16
+VCCPGPPF
AD15
+VCCPGPPG
+VCCPRIM_3P3
V19
+VCCPRIM_1P0
T1
+VCCATS_1P8
AA1
+VCCPRTCPRIM_3P3
AK17 AK19
BB14 BB10 A14 K19 L21 N20 L19 A10
V0P85A_VID0
AN11 AN13
C8812 0.1U/16V_4
C286 1U/6.3V_4
C358 1U/6.3V_4
+VCCPRTC
C352 1U/6.3V_4
C353 0.1U/16V_4
DCPRTC
C198 *1U/6.3V_4
C578 1U/6.3V_4
C325 *1U/6.3V_4 C309 1U/6.3V_4 C255 1U/6.3V_4
C274 *1U/6.3V_4 R186 0_6 R180 0_6 R154 0_6 R153 0_6 R161 0_6 R166 0_6 R171 0_6
C283 1U/6.3V_4
C299 *1U/6.3V_4
R165 0_6 R248 0_6
C362 0.1U/16V_4
R231 0_6
C641 0.1U/16V_4
TP37
+3V_S5 +3V_S5
+3V_S5 +3V_S5
+3V_S5
+1.8V_S5
+3V_S5
C8812 Near CPU
+1V_S5 +1.8V_S5
+3V_S5
+3V_RTC
+1V_S5
09
Pin Name Strap description Configuration
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[6:5]
A A
CFG[7]
CFG[19:8]
Stall reset sequence after PCU PLL lock until de-asserted
Reserved Configuration lane
PCI Express* Static x16 Lane Numbering Reversal
Reserved Configuration lane
eDP enable
PCI Express* Bifunction
PEG Training
Reserved Configuration lane
5
1 = *Normal Operation; No stall (iPU 3K)
0 = Stall
1 = *Normal Operation(iPU 3K)
0 = Lan number reversed
1 = Disabled (iPU 3K)
0 = *Enabled
00 = 1x8, 2x4 PCI Express* 01 = reserved 10 = 2x8 PCI Express* 11 = 1x16 PCI Express*
1 = *PEG Train immediatedly follow RESET# de-assertion (iPU 3K)
0 = PEG wait for BIOS for training
4
Note
H & S processor used only
R455 1K_4
CFG4
H & S processor used only
H & S processor used only
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
2
Thursday, June 22, 2017
PROJECT :
Skylake PCH-LP 15/19 (POWER)
Skylake PCH-LP 15/19 (POWER)
Skylake PCH-LP 15/19 (POWER)
Z8VR
Z8VR
Z8VR
1A
1A
9 46
9 46
1
9 46
1A
5
4
3
2
1
Skylake ULT (GND)
G10 G22 G43 G45 G48
G52 G55 G58
G60 G63 G66
H15 H18 H71
K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71
F8
G5
G6
J11 J13 J25 J28 J32 J35 J38 J42
J8
L11 L16 L17
SKL_ULT
GND 3 OF 3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SKL_ULT/BGA
18 OF 20
U34R
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21
AW69
+1.8V_S5
XTAL24_OUT_C7
R491 *0_4
*1U/6.3V_4
Reserve 1uF no stuff in CPU U11,U12 ball support Cannonlake-U PCH
XTAL24_IN_E3
XTAL24_OUT_C7
2
R8751 U42@0_5%_4
R8752 U42@0_5%_4
AW68
AU56
AW48
C7 U12 U11 H11
C614
REV = 1
R8750
U42@1M_5%_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
U34T
RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11
SKL_ULT/BGA
Skylake 10/17/18 (GND)
Skylake 10/17/18 (GND)
Skylake 10/17/18 (GND)
AA2
AA4 AA65 AA68 AB15 AB16 AB18 AB21
AB8 AD13 AD16 AD19 AD20 AD21 AD62
AD8 AE64 AE65 AE66 AE67 AE68 AE69
AF1
AF10 AF15 AF17
AF2
AF4
AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13
AH6 AH63 AH64 AH67
AJ15 AJ18 AJ20
AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69
AK8
AL28 AL32 AL35 AL38
AL45 AL48 AL52 AL55 AL58 AL64
A67 A70
AJ4
AL2
AL4
A5
SKL_ULT
GND 1 OF 3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SKL_ULT/BGA
D D
C C
B B
A A
5
16 OF 20
U34P
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58
4
AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38
AV1 AV68 AV69 AV70 AV71
AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57
AW6 AW60 AW62 AW64 AW66
AW8
AY66
B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71
BA1 BA10 BA14 BA18
BA2 BA23 BA28 BA32 BA36
F68
BA45
SKL_ULT
GND 2 OF 3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SKL_ULT/BGA
17 OF 20
U34Q
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41
3
?
SKL_ULT
SPARE
20 OF 20
RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52
RSVD_F6
RSVD_E3
?
F6
XTAL24_IN_E3
E3 C11 B11 A11 D12 C12 F52
For KBL R U42 (i)Non-stuff on KBL-U
XTAL24_IN_E3_R
XTAL24_OUT_C7_R
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
C232 U42@27p/50V_4
4
3
Y8004 U42@24MHZ/20ppm
1
2
C8806U42@27p/50V_4
Z8VR
Z8VR
Z8VR
10 46
10 46
10 46
1
1A
1A
1A
5
4
3
2
1
M_A_A[13:0][3] M_A_DQ[63:0][3]
D D
M_A_WE#[3] M_A_CAS#[3] M_A_RAS#[3]
+1.2VSUS
R315 240/F_4
M_A_EVENT#
+3V
C C
B B
R311
R313
*10K_4
*10K_4
CHA_SA0 CHA_SA1 CHA_SA2
R322
R320
10K_4
10K_4
R332 *10K_4
R333 10K_4
DDR3_DRAMRST#[3,12]
+1.2VSUS
M_A_ACT#[3] M_A_PARITY[3] M_A_ALERT#[3]
M_A_BA#0[3] M_A_BA#1[3] M_A_BG#0[3] M_A_BG#1[3]
M_A_CS#0[3] M_A_CS#1[3] M_A_CKE0[3] M_A_CKE1[3]
M_A_CLK0[3] M_A_CLK0#[3] M_A_CLK1[3] M_A_CLK1#[3]
M_A_ODT0_DIMM[3] M_A_ODT1_DIMM[3]
CLK_SCLK[7,12,19,26] CLK_SDATA[7,12,19,26]
C460 0.1U/16V_4
CHA_SA0 CHA_SA1 CHA_SA2
R319 240/F_4 R305 240/F_4 R308 240/F_4 R309 240/F_4 R318 240/F_4 R304 240/F_4 R317 240/F_4 R316 240/F_4
+1.2VSUS
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13
TP41 TP40
M_A_EVENT#
M_A_CB0 M_A_CB1 M_A_CB2 M_A_CB3 M_A_CB4 M_A_CB5 M_A_CB6 M_A_CB7
P/N and F/P
JDIM2A
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10/AP
120
A11
119
A12
158
A13
151
A14/WE#
156
A15/CAS#
152
A16/RAS#
162
S2#/C0
165
S3#/C1
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
150
BA0
145
BA1
115
BG0
113
BG1
149
S0#
157
S1#
109
CKE0
110
CKE1
137
CK0
139
CK0#
138
CK1
140
CK1#
155
ODT0
161
ODT1
253
SCL
254
SDA
256
SA0
260
SA1
166
SA2
92
CB0
91
CB1
101
CB2
105
CB3
88
CB4
87
CB5
100
CB6
104
CB7
12
DM0
33
DM1
54
DM2
75
DM3
178
DM4
199
DM5
220
DM6
241
DM7
96
DM8
DDR4 SODIMM 260 PIN
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48
(260P)
DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 DQS#8
M_A_DQ0
8
M_A_DQ1
7
M_A_DQ3
20
M_A_DQ6
21
M_A_DQ5
4
M_A_DQ4
3
M_A_DQ7
16
M_A_DQ2
17
M_A_DQ9
28
M_A_DQ8
29
M_A_DQ11
41
M_A_DQ10
42
M_A_DQ13
24
M_A_DQ12
25
M_A_DQ14
38
M_A_DQ15
37
M_A_DQ21
50
M_A_DQ16
49
M_A_DQ19
62
M_A_DQ22
63
M_A_DQ17
46
M_A_DQ20
45
M_A_DQ23
58
M_A_DQ18
59
M_A_DQ25
70
M_A_DQ28
71
M_A_DQ27
83
M_A_DQ30
84
M_A_DQ24
66
M_A_DQ29
67
M_A_DQ26
79
M_A_DQ31
80
M_A_DQ33
174
M_A_DQ37
173
M_A_DQ35
187
M_A_DQ34
186
M_A_DQ36
170
M_A_DQ32
169
M_A_DQ38
183
M_A_DQ39
182
M_A_DQ45
195
M_A_DQ41
194
M_A_DQ46
207
M_A_DQ42
208
M_A_DQ44
191
M_A_DQ40
190
M_A_DQ47
203
M_A_DQ43
204
M_A_DQ52
216
M_A_DQ53
215
M_A_DQ50
228
M_A_DQ51
229
M_A_DQ48
211
M_A_DQ49
212
M_A_DQ55
224
M_A_DQ54
225
M_A_DQ63
237
M_A_DQ58
236
M_A_DQ56
249
M_A_DQ61
250
M_A_DQ59
232
M_A_DQ62
233
M_A_DQ60
245
M_A_DQ57
246
M_A_DQS0
13
M_A_DQS1
34
M_A_DQS2
55
M_A_DQS3
76
M_A_DQS4
179
M_A_DQS5
200
M_A_DQS6
221
M_A_DQS7
242
M_A_DQS8
97
M_A_DQS#0
11
M_A_DQS#1
32
M_A_DQS#2
53
M_A_DQS#3
74
M_A_DQS#4
177
M_A_DQS#5
198
M_A_DQS#6
219
M_A_DQS#7
240
M_A_DQS#8
95
0-7
8-15
16-23
24-31
32-39
40-47
48-55
R306
56-63
M_A_DQS[7:0][3]
M_A_DQS#[7:0][3]
M_A_DQS8
M_A_DQS#8
240/F_4
R307
240/F_4
12/21 Change JDIM2 footprint to "ddr4-d4as0-26001-1p52-std-smt " for SMT requset
VREF DQ0 M1 Solution
+1.2VSUS
+1.2VSUS
+1.2VSUS
+VREF_CA_CPU
2250mA
2 1
C473
0.022U/25V_4
JDIM2B
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
141
VDD11
142
VDD12
147
VDD13
148
VDD14
153
VDD15
154
VDD16
159
VDD17
160
VDD18
163
VDD19
1
VSS1
5
VSS2
9
VSS3
15
VSS4
19
VSS5
23
VSS6
27
VSS7
31
VSS8
35
VSS9
39
VSS10
43
VSS11
47
VSS12
51
VSS13
57
VSS14
61
VSS15
65
VSS16
69
VSS17
73
VSS18
77
VSS19
81
VSS20
85
VSS21
89
VSS22
93
VSS23
99
VSS24
103
VSS25
107
VSS26
167
VSS27
171
VSS28
175
VSS29
181
VSS30
185
VSS31
189
VSS32
193
VSS33
197
VSS34
201
VSS35
205
VSS36
209
VSS37
213
VSS38
217
VSS39
223
VSS40
227
VSS41
231
VSS42
235
VSS43
239
VSS44
243
VSS45
247
VSS46
251
VSS47
R327 2/F_6
R334 24.9/F_4
DDR4 SODIMM 260 PIN
+1.2VSUS
VDDSPD
VPP1 VPP2
VTT
VREF_CA
VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68
(260P)
VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94
GND GND
R321 1K/F_4
VREF_CA_DIMM0
R328 1K/F_4
255
257 259
258
164
2 6 10 14 18 22 26 30 36 40 44 48 52 56 60 64 68 72 78 82 86 90 94 98 102 106 168 172 176 180 184 188 192 196 202 206 210 214 218 222 226 230 234 238 244 248 252
261 262
VREF_CA_DIMM0
C379 2.2U/6.3V/X7R_6
C377 0.1U/25V_4
R271 *0_4 R282 0_4
0.5A
600mA
R325*0_4
+2.5V_SUS
+VDDQ_VTT
11
+2.5V +3V
12/4 Change for +3.3V to +3V
+VDDQ
Place these Caps near So-Dimm1.
1uF/10uF 4pcs on each side of connector
+1.2VSUS
C399 1U/6.3V_4 C391 1U/6.3V_4 C408 1U/6.3V_4 C381 1U/6.3V_4 C449 1U/6.3V_4 C414 1U/6.3V_4
A A
+1.2VSUS[3,5,12,33,40]
+VDDQ_VTT[12,33]
+3V[2,4,6,7,8,9,12,14,15,16,17,19,20,21,22,23,24,25,26,27,28,30,31,33,34,37,38,39,40]
5
4
C427 1U/6.3V_4 C438 1U/6.3V_4 C392 10U/6.3V_6
C385 10U/6.3V_6 C383 10U/6.3V_6
C382 10U/6.3V_6 C393 10U/6.3V_6
C426 10U/6.3V_6 C416 10U/6.3V_6
C386 10U/6.3V_6
3
+VDDQ_VTT
+3V
C425 1U/6.3V_4 C412 1U/6.3V_4 C423 1U/6.3V_4 C415 1U/6.3V_4 C409 10U/6.3V_6
C444 0.1U/16V_4 C441 2.2U/6.3V_6
VREF_CA_DIMM0
+2.5V_SUS
C465 0.1U/16V_4 C464 2.2U/6.3V_6
C374 0.1U/16V_4 C378 2.2U/6.3V_6
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
2
Thursday, June 22, 2017
PROJECT :
DDR4 DIMM-RVS(5.2H) CHA
DDR4 DIMM-RVS(5.2H) CHA
DDR4 DIMM-RVS(5.2H) CHA
Z8VR
Z8VR
Z8VR
11 46
11 46
11 46
1
1A
1A
1A
5
4
3
2
1
M_B_A[13:0][3]
D D
M_B_WE#[3] M_B_CAS#[3] M_B_RAS#[3]
M_B_ACT#[3] M_B_PARITY[3]
R290 *10K_4
R287 10K_4
DDR3_DRAMRST#[3,11]
+1.2VSUS
M_B_ALERT#[3]
M_B_BA#0[3] M_B_BA#1[3] M_B_BG#0[3] M_B_BG#1[3]
M_B_CS#0[3] M_B_CS#1[3] M_B_CKE0[3] M_B_CKE1[3]
M_B_CLK0[3] M_B_CLK0#[3] M_B_CLK1[3] M_B_CLK1#[3]
M_B_ODT0_DIMM[3] M_B_ODT1_DIMM[3]
CLK_SCLK[7,11,19,26] CLK_SDATA[7,11,19,26]
+1.2VSUS
R301 240/F_4
M_B_EVENT#
+3V
C C
R300
R302
*10K_4
10K_4
CHB_SA0 CHB_SA1 CHB_SA2
R294
R295
10K_4
*10K_4
B B
M_B_A0 M_B_A1 M_B_DQ8 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13
M_B_EVENT#
C461 0.1U/16V_4
CHB_SA0 CHB_SA1 CHB_SA2
R292 240/F_4 R272 240/F_4 R280 240/F_4 R275 240/F_4 R293 240/F_4 R273 240/F_4 R288 240/F_4 R303 240/F_4
+1.2VSUS
TP39 TP38
M_B_CB0
M_B_CB1 M_B_CB2 M_B_CB3
M_B_CB4
M_B_CB5 M_B_CB6 M_B_CB7
JDIM1A
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10/AP
120
A11
119
A12
158
A13
151
A14/WE#
156
A15/CAS#
152
A16/RAS#
162
S2#/C0
165
S3#/C1
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
150
BA0
145
BA1
115
BG0
113
BG1
149
S0#
157
S1#
109
CKE0
110
CKE1
137
CK0
139
CK0#
138
CK1
140
CK1#
155
ODT0
161
ODT1
253
SCL
254
SDA
256
SA0
260
SA1
166
SA2
92
CB0
91
CB1
101
CB2
105
CB3
88
CB4
87
CB5
100
CB6
104
CB7
12
DM0
33
DM1
54
DM2
75
DM3
178
DM4
199
DM5
220
DM6
241
DM7
96
DM8
DDR4 SODIMM 260 PIN
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48
(260P)
DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 DQS#8
M_B_DQ9
8 7
M_B_DQ10
20
M_B_DQ15
21
M_B_DQ13
4
M_B_DQ12
3
M_B_DQ11
16
M_B_DQ14
17
M_B_DQ5
28
M_B_DQ1
29
M_B_DQ6
41
M_B_DQ7
42
M_B_DQ4
24
M_B_DQ0
25
M_B_DQ2
38
M_B_DQ3
37
M_B_DQ17
50
M_B_DQ21
49
M_B_DQ23
62
M_B_DQ19
63
M_B_DQ16
46
M_B_DQ20
45
M_B_DQ22
58
M_B_DQ18
59
M_B_DQ28
70
M_B_DQ25
71
M_B_DQ26
83
M_B_DQ27
84
M_B_DQ29
66
M_B_DQ24
67
M_B_DQ30
79
M_B_DQ31
80
M_B_DQ37
174
M_B_DQ32
173
M_B_DQ39
187
M_B_DQ34
186
M_B_DQ36
170
M_B_DQ33
169
M_B_DQ38
183
M_B_DQ35
182
M_B_DQ44
195
M_B_DQ45
194
M_B_DQ42
207
M_B_DQ47
208
M_B_DQ41
191
M_B_DQ40
190
M_B_DQ43
203
M_B_DQ46
204
M_B_DQ49
216
M_B_DQ53
215
M_B_DQ54
228
M_B_DQ50
229
M_B_DQ52
211
M_B_DQ48
212
M_B_DQ51
224
M_B_DQ55
225
M_B_DQ56
237
M_B_DQ60
236
M_B_DQ58
249
M_B_DQ62
250
M_B_DQ61
232
M_B_DQ57
233
M_B_DQ59
245
M_B_DQ63
246
M_B_DQS1
13
M_B_DQS0
34
M_B_DQS2
55
M_B_DQS3
76
M_B_DQS4
179
M_B_DQS5
200
M_B_DQS6
221
M_B_DQS7
242
M_B_DQS8
97
M_B_DQS#1
11
M_B_DQS#0
32
M_B_DQS#2
53
M_B_DQS#3
74
M_B_DQS#4
177
M_B_DQS#5
198
M_B_DQS#6
219
M_B_DQS#7
240
M_B_DQS#8
95
M_B_DQ[63:0][3]
8-15
0-7
16-23
24-31
32-39
40-47
48-55
56-63
M_B_DQS[7:0][3]
M_B_DQS#[7:0][3]
M_B_DQS8
M_B_DQS#8
R277
240/F_4
R278
240/F_4
+1.2VSUS
2250mA
+1.2VSUS
+1.2VSUS
JDIM1B
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
141
VDD11
142
VDD12
147
VDD13
148
VDD14
153
VDD15
154
VDD16
159
VDD17
160
VDD18
163
VDD19
1
VSS1
5
VSS2
9
VSS3
15
VSS4
19
VSS5
23
VSS6
27
VSS7
31
VSS8
35
VSS9
39
VSS10
43
VSS11
47
VSS12
51
VSS13
57
VSS14
61
VSS15
65
VSS16
69
VSS17
73
VSS18
77
VSS19
81
VSS20
85
VSS21
89
VSS22
93
VSS23
99
VSS24
103
VSS25
107
VSS26
167
VSS27
171
VSS28
175
VSS29
181
VSS30
185
VSS31
189
VSS32
193
VSS33
197
VSS34
201
VSS35
205
VSS36
209
VSS37
213
VSS38
217
VSS39
223
VSS40
227
VSS41
231
VSS42
235
VSS43
239
VSS44
243
VSS45
247
VSS46
251
VSS47
12/21 Change JDIM1 footprint to "ddr4-d4ar0-26001-1p52-rvs-smt " for SMT requset
DDR4 SODIMM 260 PIN
VDDSPD
VPP1 VPP2
VTT
VREF_CA
VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68
(260P)
VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94
GND GND
C395 2.2U/6.3V/X7R_6
255
257 259
258
VREF_CA_DIMM1
164
2 6 10 14 18 22 26 30 36 40 44 48 52 56 60 64 68 72 78 82 86 90 94 98 102 106 168 172 176 180 184 188 192 196 202 206 210 214 218 222 226 230 234 238 244 248 252
261 262
C401 0.1U/25V_4
R276 *0_4
R281 0_4
0.5A
600mA
+2.5V +3V
+2.5V_SUS
12/4 Change for +3.3V to +3V
+VDDQ_VTT
+3V[2,4,6,7,8,9,11,14,15,16,17,19,20,21,22,23,24,25,26,27,28,30,31,33,34,37,38,39,40]
+1.2VSUS[3,5,11,33,40]
+VDDQ_VTT[11,33]
12
For EMI RESERVE
+1.2VSUS
EC1 *120P/50V_4 C448 1U/6.3V_4 EC8 *120P/50V_4 EC2 *120P/50V_4 EC3 120P/50V_4 EC4 *120P/50V_4 EC5 *120P/50V_4 EC6 *120P/50V_4
A A
+VDDQ_VTT
EC7 *120P/50V_4 EC14 *120P/50V_4
5
+1.2VSUS
EC16 *120P/50V_4 EC10 *120P/50V_4 EC12 *120P/50V_4
EC11 *0.1U/16V_4 EC15 *0.1U/16V_4 EC13 *0.1U/16V_4
4
Place these Caps near So-Dimm0.
1uF/10uF 4pcs on each side of connector
+1.2VSUS +VDDQ_VTT
C380 1U/6.3V_4
C458 1U/6.3V_4 C454 1U/6.3V_4 C457 1U/6.3V_4 C456 1U/6.3V_4 C436 1U/6.3V_4 C432 1U/6.3V_4
C469 10U/6.3V_6 C437 10U/6.3V_6 C470 10U/6.3V_6 C468 10U/6.3V_6 C439 10U/6.3V_6 C463 10U/6.3V_6 C462 10U/6.3V_6 C440 10U/6.3V_6
VREF_CA_DIMM1
+2.5V_SUS
+3V
C471 1U/6.3V_4 C453 1U/6.3V_4 C459 1U/6.3V_4 C467 1U/6.3V_4 C424 1U/6.3V_4EC9 *0.1U/16V_4
C411 0.1U/16V_4 C413 2.2U/6.3V_6
C434 0.1U/16V_4 C430 2.2U/6.3V_6
C428 0.1U/16V_4 C431 2.2U/6.3V_6
3
VREF DQ1 M1 Solution
+VREFDQ_SB_M3
+1.2VSUS
R286
+VREFDQ_SB_M3 VREF_CA_DIMM1
R298 2/F_6
C419
0.022U/25V_4
2 1
R299
24.9/F_4
2
1K/F_4
R297 1K/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
R296*0_4
+VDDQ
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
DDR4 DIMM-STD(5.2H) CHB
DDR4 DIMM-STD(5.2H) CHB
DDR4 DIMM-STD(5.2H) CHB
Z8VR
Z8VR
Z8VR
12 46
12 46
12 46
1
1A
1A
1A
1
+1.03_GFX
A A
Near GPU
C8672 EV@22u/6.3V_6 C8372 EV@22u/6.3V_6 C8373 EV@4.7U/10V_6 C8376 EV@4.7U/10V_6 C8380 EV@4.7U/10V_6
C8384 EV@1U/6.3V_4 C8383 EV@1U/6.3V_4
Under GPU
PEX_IOVDD + PEX_IOVDDQ = 1.042A
+1.03_GFX
+1.8_GFX_MAIN
N16_1.03V-->R1008/R1009 N17_1.8V--->R1010/R1011
PEX_PLL_HVDD + PEX_SVDD_3V3 = 143mA
B B
C C
N16-->R8240 Mount N17--->R8240 N/A
+1.03_GFX
D D
R1008 N16@0_6 R1009 N16@0_6
R1010 N17@0_6 R1011 N17@0_6
N16-->R1012 Mount N17--->R1013Mount
C8381EV@0.1U/16V_4 C8379 EV@4.7U/10V_6
100 ohm near GPU
VGA_VCCSENSE[38]
VGA_VSSSENSE[38]
R8597 *200/F_4
R8240 N16@0_6
Near GPU
Under GPU
EV@10K/F_4
1
C8378 EV@22u/6.3V_6 C8374 EV@22u/6.3V_6 C8369 EV@10U/10V_6 C8375 EV@4.7U/10V_6 C8670 EV@4.7U/10V_6
Near GPU
Under GPU
C8395 EV@1U/6.3V_4
+3V_GFX+1.8_GFX_MAIN
R1013
N17@0_6
C8388 EV@4.7U/10V_6
Near GPU
R1014 N16@0_6
N16-->R1014 Mount N17--->R1014 N/A
+VGPU_CORE
R8311 EV@100_4
R8315 EV@100_4
PEX_TSTCLK PEX_TSTCLK#
CX300T30001 Change to 0ohm
PEX_PLLVDD
C8344EV@4.7U/10V_6 C8394EV@1U/6.3V_4
C8391EV@0.1U/16V_4
PEX_PLLVDD = 130mA
TESTMODE
R8259
PEX_TERMP
R8599EV@2.49K/F_4
R1012
N16@0_6
AA22 AB23 AC24 AD25 AE26 AE27
AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27
AF22 AE22
AA14 AA15
AF25
AA8 AA9
AB8
F2
F1
AD9
2
U8039A
PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD
PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ
PEX_PLL_HVDD PEX_PLL_HVDD
PEX_SVDD_3V3
VDD_SENSE
GND_SENSE
PEX_TSTCLK_OUT PEX_TSTCLK_OUT
PEX_PLLVDD PEX_PLLVDD
TESTMODE
PEX_TERMP
2
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
1/14 PCI_EXPRESS
PEX_WAKE
PEX_RST
PEX_CLKREQ
PEX_REFCLK PEX_REFCLK
PEX_TX0 PEX_TX0
PEX_RX0 PEX_RX0
PEX_TX1 PEX_TX1
PEX_RX1 PEX_RX1
PEX_TX2 PEX_TX2
PEX_RX2 PEX_RX2
PEX_TX3 PEX_TX3
PEX_RX3 PEX_RX3
PEX_TX4 PEX_TX4
PEX_RX4 PEX_RX4
PEX_TX5 PEX_TX5
PEX_RX5 PEX_RX5
PEX_TX6 PEX_TX6
PEX_RX6 PEX_RX6
PEX_TX7 PEX_TX7
PEX_RX7 PEX_RX7
PEX_TX8 PEX_TX8
PEX_RX8 PEX_RX8
PEX_TX9 PEX_TX9
PEX_RX9 PEX_RX9
PEX_TX10 PEX_TX10
PEX_RX10 PEX_RX10
PEX_TX11 PEX_TX11
PEX_RX11 PEX_RX11
PEX_TX12 PEX_TX12
PEX_RX12 PEX_RX12
PEX_TX13 PEX_TX13
PEX_RX13 PEX_RX13
PEX_TX14 PEX_TX14
PEX_RX14 PEX_RX14
PEX_TX15 PEX_TX15
PEX_RX15 PEX_RX15
GF119GF117
COMMONbga595-nvidia-n13p-gv2-s-a2
3
AB6
AC7 AC6 AE8
AD8 AC9
AB9 AG6
AG7 AB10
AC10 AF7
AE7 AD11
AC11 AE9
AF9 AC12
AB12 AG9
AG10 AB13
AC13 AF10
AE10 AD14
AC14 AE12
AF12 AC15
AB15 AG12
AG13 AB16
AC16 AF13
AE13 AD17
AC17 AE15
AF15 AC18
AB18 AG15
AG16 AB19
AC19 AF16
AE16 AD20
AC20 AE18
AF18 AC21
AB21 AG18
AG19 AD23
AE23 AF19
AE19 AF24
AE24 AE21
AF21 AG24
AG25 AG21
AG22
3
C8352 *0.1U/16V_4
VGA_RST#
R8243 EV@0_4
PEX_CLKREQ#
PEG_RXP0_C PEG_RXN0_C
PEG_RXP1_C PEG_RXN1_C
PEG_RXP2_C PEG_RXN2_C
PEG_RXP3_C PEG_RXN3_C
R8281 N16@10K/F_4 R8282 N17@10K/F_4
C8684 EV@0.22U/10V_4 C8685 EV@0.22U/10V_4
C8682 EV@0.22U/10V_4 C8683 EV@0.22U/10V_4
C8687 EV@0.22U/10V_4 C8686 EV@0.22U/10V_4
C8681 EV@0.22U/10V_4 C8680 EV@0.22U/10V_4
+1V8_AON
R11321 N17@0_4
DGPU_HOLD_RST#[4]
PLTRST#[8,22,24,25,28]
N16V stuff it, not support GC6 2.0
GPU_PEX_RST_HOLD#[17]
EV@NL17SZ08DFT2G
SYS_PEX_RST_MON#
SYS_PEX_RST
PEX_CLKREQ#
4
PEGX_RST#[17]
+3V_GFX +1V8_AON
CLK_PCIE_VGA [6] CLK_PCIE_VGA# [6]
PEG_RX0[6] PEG_RX#0[6]
PEG_TX0[6] PEG_TX#0[6]
PEG_RX1[6] PEG_RX#1[6]
PEG_TX1[6] PEG_TX#1[6]
PEG_RX2[6] PEG_RX#2[6]
PEG_TX2[6] PEG_TX#2[6]
PEG_RX3[6] PEG_RX#3[6]
PEG_TX3[6] PEG_TX#3[6]
+3V
U8018
2 1
R8317 N17@0_4
GPU_PEX_RST_HOLD#
4
R11320
N16@0_4
C8398 EV@0.1U/16V_4
SYS_PEX_RST
4
3 5
SYS_PEX_RST_MON# [17]
U8021
N16@MC74VHC1G08DFT2G
2 1
+3V_GFX+1.8_GFX_MAIN
R90031
R90030
N16@0_4
N17@0_4
Follow Z09 to isolate CLK_REQ#
2
Q8017
EV@PJA138K
3
1
R8267 *0_4
5
12
+
SYS_PEX_RST_MON#
C8469
N16@0.1U/16V_4
PEGX_RST#
R8316 EV@100K/F_4
CLK_PEGA_REQ# [6]
5
+VGPU_CORE
K10 K12 K14 K16 K18 L11 L13 L15 L17 M10 M12 M14 M16 M18 N11 N13 N15 N17 P10 P12 P14 P16 P18 R11 R13 R15 R17 T10 T12 T14 T16 T18 U11 U13 U15 U17 V10 V12 V14 V16 V18
R8329
N16@100K/F_4
U8039E
11/14 NVVDD
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
bga595-nvidia-n13p-gv2-s-a2 COMMON
NVDD = 32.22 ~ 26.66 A
Under GPU
C8393 EV@1U/6.3V_4 C8403 EV@1U/6.3V_4 C8424 EV@1U/6.3V_4 C8414 EV@1U/6.3V_4 C8426 EV@4.7U/10V_6 C8435 EV@4.7U/10V_6 C8434 EV@4.7U/10V_6 C8441 EV@4.7U/10V_6 C8416 EV@4.7U/10V_6 C8428 EV@4.7U/10V_6 C8415 EV@4.7U/10V_6 C8408 EV@4.7U/10V_6 C8400 EV@4.7U/10V_6 C8432 EV@4.7U/10V_6
C8413 EV@330u_2.5V_3528
C8402 EV@22U/6.3V_8 C8401 EV@47u/6.3V_8
C8417 EV@4.7U/6.3VS_6 C8404 EV@4.7U/6.3VS_6 C8405 EV@4.7U/6.3VS_6 C8406 EV@4.7U/6.3VS_6 C8418 EV@4.7U/6.3VS_6
Near GPU
R8318 N16@0_4
+3V
4
3 5
change power from +3V-GFX to DGPU_PWROK 02/20 add N17/N16 option to avoid leakage 03/21
PU at page 9
6
+1.8_GFX_MAIN
R1015
N17@0_6
AD10
AD7 B19
F11
V5 V6
G1 G2 G3 G4 G5 G6 G7
W1 W2 W3 W4
ALL 3.3V +3VGFX(+1.8V_AON)
ALL 3.3V 3V3_MAIN(+1.8_GFX_MAIN)
+VGACORE
PEX_VDD +1.05V_GFX
FBVDDQ +1.5V_GFX
6
N16-->R1015 N/A N17--->R1015 Mount
VDD33 = 56mA
U8039C
14/14 XVDD/VDD33
NC NC NC
3V3AUX_NC
FERMI_RSVD1_NC FERMI_RSVD2_NC
CONFIGURABLE POWER CHANNELS * nc on substrate
XPWR_G1 XPWR_G2 XPWR_G3 XPWR_G4 XPWR_G5 XPWR_G6 XPWR_G7
V1
XPWR_V1
V2
XPWR_V2
XPWR_W1 XPWR_W2 XPWR_W3 XPWR_W4
bga595-nvidia-n13p-gv2-s-a2 COMMON
t>0NVVDD
7
N16-->R1017
VDD33 VDD33
VDD33 VDD33
R1016 N17@0_6
G10
R1017
G12
C8452 EV@0.1U/16V_4 C8461 EV@4.7U/10V_6
C8460 EV@1U/10V_6
G8 G9
C8449 EV@4.7U/10V_6 C8448 EV@1U/10V_6
C8443 EV@0.1U/16V_4 C8444 EV@0.1U/16V_4C8386 EV@1U/6.3V_4
N17--->R1016(
N16@0_6
1 2
1 2
+1V8_AON +3V_GFX
Under GPU
Near GPU
初始
)
N16-->R1031 N17--->R1030(
Under GPU
Power up sequence
t>=0
Power down sequence
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
Date: Sheet of
Thursday, June 22, 2017
7
PROJECT :
N16S-GT (PCIE I/F) /NVDD
N16S-GT (PCIE I/F) /NVDD
N16S-GT (PCIE I/F) /NVDD
N16@0_6
N17@0_6
Z8VR
Z8VR
Z8VR
8
R1031 R1030
14 47
14 47
14 47
8
14
+3V_MAIN
+1.8_GFX_MAIN
初始
)
2A
2A
2A
1
R8644 EV@10K/F_4
A A
FBA_CMD0[18] FBA_CMD1[18] FBA_CMD2[18] FBA_CMD3[18] FBA_CMD4[18] FBA_CMD5[18] FBA_CMD6[18] FBA_CMD7[18]
B B
C C
+1.35V_GFX
FB_PLLAVDD = 55mA
+1.8_GFX_MAIN
+1.03_GFX
D D
N16_L8007-->1.05V N17_L8010--->1.8V
L8010
N17@BLM15PX330SN1DEV_4
N16@BLM15PX330SN1DEV_4
L8007
C8365EV@22u/6.3V_6 C8453EV@0.1U/16V_4 C8447EV@0.1U/16V_4 C8445EV@0.1U/16V_4
FBA_CMD8[18]
FBA_CMD9[18] FBA_CMD10[18] FBA_CMD11[18] FBA_CMD12[18] FBA_CMD13[18] FBA_CMD14[18] FBA_CMD15[18] FBA_CMD16[18]
FBA_CMD17[18]
FBA_CMD18[18] FBA_CMD19[18] FBA_CMD20[18] FBA_CMD21[18] FBA_CMD22[18] FBA_CMD23[18] FBA_CMD24[18] FBA_CMD25[18] FBA_CMD26[18] FBA_CMD27[18] FBA_CMD28[18] FBA_CMD29[18] FBA_CMD30[18] FBA_CMD31[18]
R8339 *60.4_4 R8341 *60.4_4
VMA_CLK0[18]
VMA_CLK0#[18]
VMA_CLK1[18]
VMA_CLK1#[18]
VMA_WCK01[18]
VMA_WCK01#[18]
VMA_WCK23[18]
VMA_WCK23#[18]
VMA_WCK45[18]
VMA_WCK45#[18]
VMA_WCK67[18]
VMA_WCK67#[18]
FB_DLLAVDD = 15mA
1
PS_FB_CLAMP
+FB_PLLAVDD
2
F3
C27 C26 E24 F24 D27 D26 F25 F26 F23 G22 G23 G24 F27 G25 G27 G26 M24 M23 K24 K23 M27 M26 M25 K26 K22 J23 J25 J24 K27 K25 J27 J26
F22 J22
D24 D25 N22 M22
D18 C18 D17 D16 T24 U24 V24 V25
F16 P22 H22
2
U8039B
FB_CLAMP
FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31
FBA_DEBUG0 FBA_DEBUG1
FBA_CLK0 FBA_CLK0 FBA_CLK1 FBA_CLK1
FBA_WCK01 FBA_WCK01 FBA_WCK23 FBA_WCK23 FBA_WCK45 FBA_WCK45 FBA_WCK67 FBA_WCK67
FB_PLLAVDD
FB_PLLAVDD
FB_DLLAVDD
INT
bga595-nvidia-n13p-gv2-s-a2
GF119NC
GF117
GF119
GF117FB_PLLAVDD
3
3
2/14 FBA
FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8
FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63
FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7
FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7
FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7
FB_VREF_PROBE
COMMON
VMA_DQ0
E18
VMA_DQ1
F18
VMA_DQ2
E16
VMA_DQ3
F17
VMA_DQ4
D20
VMA_DQ5
D21
VMA_DQ6
F20
VMA_DQ7
E21
VMA_DQ8
E15
VMA_DQ9
D15
VMA_DQ10
F15
VMA_DQ11
F13
VMA_DQ12
C13
VMA_DQ13
B13
VMA_DQ14
E13
VMA_DQ15
D13
VMA_DQ16
B15
VMA_DQ17
C16
VMA_DQ18
A13
VMA_DQ19
A15
VMA_DQ20
B18
VMA_DQ21
A18
VMA_DQ22
A19
VMA_DQ23
C19
VMA_DQ24
B24
VMA_DQ25
C23
VMA_DQ26
A25
VMA_DQ27
A24
VMA_DQ28
A21
VMA_DQ29
B21
VMA_DQ30
C20
VMA_DQ31
C21
VMA_DQ32
R22
VMA_DQ33
R24
VMA_DQ34
T22
VMA_DQ35
R23
VMA_DQ36
N25
VMA_DQ37
N26
VMA_DQ38
N23
VMA_DQ39
N24
VMA_DQ40
V23
VMA_DQ41
V22
VMA_DQ42
T23
VMA_DQ43
U22
VMA_DQ44
Y24
VMA_DQ45
AA24
VMA_DQ46
Y22
VMA_DQ47
AA23
VMA_DQ48
AD27
VMA_DQ49
AB25
VMA_DQ50
AD26
VMA_DQ51
AC25
VMA_DQ52
AA27
VMA_DQ53
AA26
VMA_DQ54
W26
VMA_DQ55
Y25
VMA_DQ56
R26
VMA_DQ57
T25
VMA_DQ58
N27
VMA_DQ59
R27
VMA_DQ60
V26
VMA_DQ61
V27
VMA_DQ62
W27
VMA_DQ63
W25
FBA_DBI0
D19
FBA_DBI1
D14
FBA_DBI2
C17
FBA_DBI3
C22
FBA_DBI4
P24
FBA_DBI5
W24
FBA_DBI6
AA25
FBA_DBI7
U25
FBA_EDC0
E19
FBA_EDC1
C15
FBA_EDC2
B16
FBA_EDC3
B22
FBA_EDC4
R25
FBA_EDC5
W23
FBA_EDC6
AB26
FBA_EDC7
T26
F19 C14 A16 A22
GDDR5 NO USE
P25 W22 AB27 T27
D23
TP8038
4
VMA_DQ[63:0]
FBVDDQ + FBVDD = 3.116A
C8385 EV@0.1U/16V_4 C8450 EV@0.1U/16V_4
1 2
C8451 EV@1U/10V_6 C8440 EV@1U/10V_61 2 C8433 EV@4.7U/10V_6 C8387 EV@4.7U/10V_6 C8397 EV@10U/6.3V_6 C8425 EV@22u/6.3V_6 C8816 *EV@22u/6.3V_6
FBA_DBI[7:0] [18]
FBA_EDC[7:0] [18]
4
5
VMA_DQ[63:0] [18]
+1.35V_GFX
5
U8039D
12/14 FBVDDQ
B26
FBVDDQ
C25
FBVDDQ
E23
FBVDDQ
E26
FBVDDQ
F14
FBVDDQ
F21
FBVDDQ
G13
FBVDDQ
G14
FBVDDQ
G15
FBVDDQ
G16
FBVDDQ
G18
FBVDDQ
G19
FBVDDQ
G20
FBVDDQ
G21
FBVDDQ
H24
FBVDDQ
H26
FBVDDQ
J21
FBVDDQ
K21
FBVDDQ
L22
FBVDDQ
L24
FBVDDQ
L26
FBVDDQ
M21
FBVDDQ
N21
FBVDDQ
R21
FBVDDQ
T21
FBVDDQ
V21
FBVDDQ
W21
FBVDDQ
bga595-nvidia-n13p-gv2-s-a2 COMMON
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CALTERM_GND
6
FB_CAL_PD_VDDQ
D22
FB_CAL_PU_GND
C24
FB_CAL_TERM_GND
B25
6
7
R8340 EV@40.2/F_4
+1.35V_GFX
R8320 EV@40.2/F_4
R8319 EV@60.4/F_4
For support GC6 1.0
For support GC6 2.0
GC6_FB_EN[4,17]
GPU_PWR_GD[38,40]
R8292 EV@0_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
7
U8039F
A2 AB17 AB20 AB24
AC2 AC22 AC26
AC5
AC8 AD12 AD13
A26 AD15 AD16 AD18 AD19 AD21 AD22 AE11 AE14 AE17 AE20 AB11
AF1
AF11 AF14 AF17 AF20 AF23
AF5
AF8
AG2 AG26 AB14
B1 B11 B14 B17 B20 B23 B27
B5
B8 E11 E14 E17
E2 E20 E22 E25
E5
E8
H2 H23 H25
H5 K11 K13 K15 K17
L10 L12 L14 L16 L18
L2 L23 L25
L5
M11
bga595-nvidia-n13p-gv2-s-a2 COMMON
+3V
C8370 EV@0.1U/16V_4
EV@NL17SZ32DFT2G2
1
Thursday, June 22, 2017
Thursday, June 22, 2017
Thursday, June 22, 2017
4
U8017
3 5
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
N16S-GT (MEMORY/GND)
N16S-GT (MEMORY/GND)
N16S-GT (MEMORY/GND)
13/14 GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
R8272 EV@100K/F_4
Z8VR
Z8VR
Z8VR
8
15
M13
GND
M15
GND
M17
GND
N10
GND
N12
GND
N14
GND
N16
GND
N18
GND
P11
GND
P13
GND
P15
GND
P17
GND
P2
GND
P23
GND
P26
GND
P5
GND
R10
GND
R12
GND
R14
GND
R16
GND
R18
GND
T11
GND
T13
GND
T15
GND
T17
GND
U10
GND
U12
GND
U14
GND
U16
GND
U18
GND
U2
GND
U23
GND
U26
GND
U5
GND
V11
GND
V13
GND
V15
GND
V17
GND
Y2
GND
Y23
GND
Y26
GND
Y5
GND
AA7
GND
AB7
GND
FBVDDQ_EN [39]
15 47
15 47
15 47
8
2A
2A
2A
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