Acer Aspire E5-474G Schematics
A
1 1
2 2
Co
B
C
D
mpal Confidential
E
A4
3 3
WAS MB Schematic Document
LA-C611
P
Rev: 1.0
2015.07.17
4 4
DAX
Number
Part
1DR00100 PCB A4WAS LA-C611P LS-C341P
DAZ
WAS_PCB_REV10
A4
Description
A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
TH
TH
TH
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
C
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
2014/
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
Cover Sheet
Cover Sheet
Cover Sheet
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
Date: Sheet
Date: Sheet
D
Date: Sheet
160Friday, July 17, 2015
160Friday, July 17, 2015
160Friday, July 17, 2015
of
of
E
of
0
0
0
1.
1.
1.
A
VG
A
32
page
1 1
DP
to VGA
Realtek RTD2168
31
page
x 2 lanes
DP
HDMI Conn.
I
HDM
PS8407A
page 30
Nv
idia N16x
DD
HDM
I2DDI1
I x 4 lanes
B
eD
P
page
eD
DD
C
29
P
I
Intel Skylake U
ylake U
Sk
Skylake PCH-LP(MCP)
(SKL-U_2+2)
Me
mory BUS
Du
al Channel
35V DDR3L 1333/1600
1.
US
conn x2
USB port 1,2
B 3.0
D
nterleaved Memory
I
Fan Control
204pi
204pi
B 2.0
US
conn x1
(p
B/B
US
E
41
page
n DDR3L-SO-DIMM X1
BAN
K 0, 1, 2, 3
n DDR3L-SO-DIMM X1
K 4, 5, 6, 7
BAN
OS
CM
Camera
ort 3)
US
B port 7
page
page
18
19
with DDR3 x4
Pr
35
FF
NG
AN
WL
US
B port 5
2 2
page
PC
Ie 1.0
2.5GT/s
t 6
por
PCIe 1.0
2.5GT/s
por
t 5
TA HDD
LA
N(GbE)/ Card Reader
altek 8411B
Re
page
33
SA
Conn.
20~28
page
PC
Ie 3.0 x4
8GT/s
t 1-4
por
SA
TA3.0 SATA3.0
por
t 7
(S
ATA0) (SATA1)
TA CDROM
SA
Conn.
Fl
exible IO
6.0 Gb/s6.0 Gb/s
por
t 8
ocessor
al Core + GT2
Du
15
W
1356pi
page
n BGA
06~17
US
Bx8
HD
SP
48M
Audio
I
Hz
37 page 29
page
3.3V 24MHz
page
HDA
C255
AL
37
Codec
page
Touch
Screen
I2
C (PORT1)
B port 6
40
US
page
29
Ca
rd Reader
in 1 (SD)
2
3 3
page
34
RT
C CKT.
Power On/Off CKT.
DC/DC Interface CKT.
4 4
wer Circuit DC/DC
Po
RJ
45 conn.
page
14
page
39
page
page
42
page 43~55
A
C/eSPI BUS
LP
page 36
34
Sub
Board
LS-C341
US
B+Audio/B
page
37
page
36
Int.KBD
B
page
ENE
KB9022
39
CLK
=24MHz
TP
page
38
Touch Pad
2 (from EC) / I2C (from SOC)
PS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
M
page
39
page
39
2014/11/10 2016/11/10
2014/11/10 2016/11/10
2014/11/10 2016/11/10
C
I ROM x2
SP
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
Deciphered Date
Deciphered Date
Deciphered Date
page
UA
In
8
D
t. Speaker
page
tle
tle
tle
Ti
Ti
Ti
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
Date: Sheet
Date: Sheet
Date: Sheet
In
t. MIC
40
WAS M/B LA-C611P
WAS M/B LA-C611P
WAS M/B LA-C611P
A4
A4
A4
page
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
Bl
Bl
Bl
ock Diagrams
ock Diagrams
ock Diagrams
40 page 37
E
J
on Sub/B
260Tuesday, June 16, 2015
260Tuesday, June 16, 2015
260Tuesday, June 16, 2015
of
of
of
0
0
0
1.
1.
1.
A
ard ID Table for AD channel
Bo
Vcc 3.3V
Board
ID
0
1
2
3
1 1
4
5
6
7
M Structure Table
BO
em BOM Structure
It
pop
Un
onnector
C
C requirement
EM
MC requirement depop
E
DEC(ALC255)
+/- 5%
100K +/- 5%Ra
Rb V min
D
BI
00 V
12K
+/- 1% 0.347 V 0.345 V 0.360 V
15K +/- 1%
+/- 1%
20K
0.423 V 0.430 V 0.438 V
Vtyp
D
BI
0 V 0.300 V
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
BO
M Option Table
@
CONN@
EMC@
@EMC@
255@CO
BO
M Option Table
em BOM Structure
It
PU
dG
6S-GT
N1
6V-GM SKU
N1
GPU
CG6 / Non GC6
VRAM BOM Select X76@/X7601@ ~
CODEC(ALC283) 283@
SPI ROM 8M*2 8M_DUAL@
8M
SP
I ROM 8M*1
2 2
UMA only
TP
M
_SINGLE@
A@
UM
TP
M@
CMC@For Intel CMC
@For ES Sampel Only
Keyboard bac klight
LPC MODE for EC
ES
KB@
LPC@
Memory
Door/
No Memory Door
IC*2 2DMIC@
DM
No Acer IOAC NIOAC@
CPU Code PreES:QH7Y@
ESPI@ESPI MODE for EC
BA
Serial
BA
@
HDD@EA Seria l
C Address Table
I2
ess(7 bit)
S
BU
I2C_0 (+3VS)
3 3
SO
C_SMBCLK +3VS
vice
De
Reserved (Touch Panel)
TM
-P2969-001 (TP)I2C_1 (+3VS)
SB8
787-1200 (TP-ELAN)
MM1
DI
DIMM2
LIS3D
HTR(G-Sensor)
N1
6S-GT (VGA)
PCH-LP (SOC)
BQ
EC_SMB_CK1 +3VLP
24780 (Charger IC)
BATTERY PACK
Addr
0x
2C
0x15
0x
A0
0xA4
0x
30
9ESOC_SML1CLK +3VS
0x
0x
90
0x
12
16
0x
B
V
max
D
BI
VGA@
SGT@
M@
VG
/
GC6@
NGC6@
X7614@
SR@/DR@Single/Dual Rank
MD
Y@/ MDN@
1DMIC@DMIC*1
IOAC@For Acer IOAC
ES:QHMF@, QHM G@
QS:QJFC@, QJ8N@,
QJ8L@
:SR2EU@,
MP
SR2EY@, SR2EZ@
Address(8bit)
Wr
ite
EC AD3
0x00 - 0x0B
0x0C - 0x1C
0x1D - 0x26
0x27
- 0x300.541 V 0.550 V 0.559 V
0x31 - 0x3B0.691 V 0.702 V 0.713 V
0x3C - 0x460.807 V 0.819 V 0.831 V
0x47 - 0x540.978 V 0.992 V 1.006 V
0x55 - 0x641.169 V 1.185 V 1.200 V
ad
Re
C
Po
wer State
E
STAT
S0 (Full ON) ON ON ON ONHIGH HIGH HIGH
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Vo
ltage Rail s
wer Plane
Po
+1
9V_VIN
+17.4V_BATT
+19VB
+VCC_CORE
+VCC_GT
CC_SA
+V
+0
.675VS_VTT
.0VALW_PRIM +1.0V Always power rail
+1
+1
.0V_VCCSTU Sustain voltage for processor in Standby modes
+VCCIO
.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST
+1
+1
.35V_VDDQ
+1.8VALW_P RIM +1.8V Always power rail
+1
.8VS System +1.8V power rail
VLP +19VB to +3VLP power rail for suspend power
+3
+3
VALW System +3VALW always on power rail
VS
+3
+5VALW
VS System +5V power rail
+5
+RTCVCC
+1
.05VSDGPU +1.05VS power rail for GPU
.5VSDGPU +1.5VS power rail for GPU
+1
+3VSDGPU_AON +3VS pow er rail for GPU(AON rails)
VSDGPU_MAIN +3VS power rail for GPU GC 62.0
+3
+VGA_CORE
te : ON*1 means power plane is ON only when WOL enable and RTC w ake at BIOS setting, otherwise it is OFF.
No
SIGNAL
SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
LOW HIGH
scription
De
Adap ter p owe r sup ply
Ba
ttery power supply
AC or ba tte ry pow er ra il for p owe r c irc uit .
Pr
ocessor IA Cores Power Rail
Processor Graphics Power Rails
Sy
stem Agent power rail
DDR
+0.675VS power rail for DDR terminator .
CP
U IO power rail
DDRIIIL +1.35V Power Rail
stem +3V power rail
Sy
+5V Always power rail
RT
C Battery Power
re power for descrete GPU
Co
HIGH
LOWLOW
HIGH
ONONON
ON
OFF
OFFLOW LOW LOW
S0
N/A
N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
S3
N/A N/A
OFF
OFF
OFF
ON
ON
OFF OFF
ON
ON
OFF
ON
ON
OFF
ON
ON ON
OFF OFF
OFF
OFF
OFF
OFF
OFF
S4
N/AN/A
N/AN/A
OFF
OFF
OFF
OFFOFF
ON
OFF
OFFOFF
OFF
ON*1
OFF
ON
ON
OFF
ON
OFFOFF
OFFOFF
OFF
OFF
OFFOFF
D
BO
ARD ID Table
Board ID
0
1
2
3
4
PCB Revision
0.
1
2
0.
0.3
0
1.
E
5
6
7
/S5
*1
*1
4 4
curity Classification
curity Classificat ion
curity Classificat ion
Se
Se
Se
Is
Is
Is
sued Date
sued Date
sued Date
S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THI
THI
THI
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2014/
2014/
2014/
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Dat e
Deciphered Dat e
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Ti
Ti
Ti
tle
tle
tle
tes List
tes List
tes List
No
No
No
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
Date: Sheet
Date: Sheet
D
Date: Sheet
E
360Thursday, July 16, 2015
360Thursday, July 16, 2015
360Thursday, July 16, 2015
0
0
0
1.
1.
1.
of
of
of
5
D D
C C
4
3
2
1
B B
A A
Se
Se
Se
curity Clas sification
curity Clas sification
curity Clas sification
sued Da te
sued Da te
sued Da te
Is
Is
Is
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPA L ELE CTRONI CS, I NC. AND CONTA INS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPA L ELE CTRONI CS, I NC. AND CONTA INS CONFIDENTIAL
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPA L ELE CTRONI CS, I NC. AND CONTA INS CONFIDENTIAL
TH
TH
TH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USE D BY O R DI SCLO SED TO ANY THI RD PA RTY WIT HOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USE D BY O R DI SCLO SED TO ANY THI RD PA RTY WIT HOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
MAY BE USE D BY O R DI SCLO SED TO ANY THI RD PA RTY WIT HOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
2014/
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Power Map
Power Map
Power Map
Size
Size
Size
cument Number Rev
cument Number Rev
cument Number Rev
Do
Do
Do
stom
stom
stom
Cu
Cu
Cu
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
Date: Sheet
Date: Sheet
Date: Sheet
1
1.
1.
1.
of
of
of
460Thursday, July 16, 2015
460Thursday, July 16, 2015
460Thursday, July 16, 2015
0
0
0
A
R Sequence_SKL-U2+2_DDR3L_NON CS
PW
+RTCVCC
tPCH01_Min : 9 ms
B
C
D
E
SOC_RTCRST#
+19VB
+3
1 1
VLP
_ON
EC
VALW/+3VALW(+3VALW_DSW...)
+5
tPCH04_Min : 9 ms
tPCH34_Max : 20 ms
SPOK tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM starting to ramp)
+1.8VALW_PRIM
+1.8VALW_PG
+V
CCPRIM_CORE/+1.0VALW_PRIM
_RSMRST#
EC
tPCH03_Min : 10 ms
ON/OFF
PB
TN_OUT#
2 2
_SLP_S5#
PM
tPCH43_Min : 95 ms
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
tP
CH18_Min : 90 us
ESPI_RST#
PM_SLP_S4#
SYSON
+1.0V_VCCSTU
+1.35V_VDDQ
PM_SLP_S3#
SUSP#
+1.0VS_VCCSTG
U04 Min : 100 ns
tCP
tCPU10 Min : 1 ms
+VCCIO
3 3
+5VS/+3VS/+1.8VS/+1.5VS
_VCCST_PG
EC
VR
_ON
SM_PG_CTRL
+0.675VS_VTT
tCPU00 Min : 1 ms
tCPU19 Max : 100 ns
tCPU18 Max : 35 us
tCPU09 Min : 1 ms
+VCC_SA
VR_PWRGD
PCH_PWROK (SYS_PWROK)
tCPU16 Min : 0 ns
tPLT05 Min : Platform dependent
H_CPUPWRGD
4 4
PLT_RST#
+V
CC_CORE / +VCC_GT
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
TH
TH
TH
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
2014/
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
Power Sequence
Power Sequence
Power Sequence
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
Date: Sheet
Date: Sheet
D
Date: Sheet
560Thursday, July 16, 2015
560Thursday, July 16, 2015
560Thursday, July 16, 2015
of
of
E
of
0
0
0
1.
1.
1.
A
Func
tional Strap Definitions
PDG0.9 P.775
#543016
B_CTRLDATA/ GPP_E19 (Internal Pull Down):
DDP
DDPC_CTRLDATA/ GPP_E21 (Internal Pull Down):
DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down):
(Sampled:Rising edge of PCH_PWROK)
Display Port B/C/ D Detected
0 =Port is not detected.
1 1
1 =Port is detected.
CO
MPENSATION PU FOR eDP
+V
CCIO
ED
RC1
1 2
#5
43016 PDG0.9 P.186
Trace widt h=20 m ils, Spac ing= 25mi l,Ma x le ngth= 100m ils
.0V_VCCST
+1
1 2
RC2
+3
VS
RC1
57 100K_0402_5%
2 2
Reserved for ESD 2014/9/17
P_COMP
24.9_0402_1%
#5
43016 PDG0.9 P.753
PH 1K to VCCST
CPU over 130 degree will output low force S0->S5
THERMTRIP#
H_
1K_0402_5%
_INT#
H_
PECI
PROCHOT#_R
H_
TP
1 2
CC5
.1U_0402_16V7K
CC5
.1U_0402_16V7K
2
12
3
12
@EMC@
@EMC@
HDMI DDC (Port C)
SPI touch RST follow CRB #544669 P.8
+1
H_
PROCHOT#38,45
SPI touch INT follow CRB
_TP_INT#38,39
EC
PDG0.9
P.771
PROC_POPIR COMP/PCH_ OPIRCOMP
PD 50ohm
CRB RVP7 1.0
#544669
EDRAM_OPIO_ RCOMP/EOP IO_RCOMP
PD50ohm
+3
<DP
<HDMI>
VS
+3
R4
955 2.2K_0402_5%
.0VS_VCCSTG
12
RC3
1K
_0402_5%
RC4
15 100K_0402_5%
R6
VS
D2
2
RB751V-40_SOD323-2
RC1
B
to VGA>
SO
C_DP2_CTRL_CLK30
SO
C_DP2_CTRL_DATA30
1 2
1 2
1 2
37 0_0402_5%@
RC5
RC6
RC7
RC8
12
Reserved
sightings issue check
499_0402_1%
C_TS_INT#29
I2
12
12
49.9_0402_1%
12
49.9_0402_1%
49.9_0402_1%
12
12
49.9_0402_1%
H_
SO
C_DP1_N031
SO
C_DP1_P031
SO
C_DP1_N131
SO
C_DP1_P131
SO
C_DP2_N030
SO
C_DP2_P030
SO
C_DP2_N130
C_DP2_P130
SO
C_DP2_N230
SO
C_DP2_P230
SO
SO
C_DP2_N330
SO
C_DP2_P330
T166@
PECI38
T1
T1
C_DP1_CTRL_DATA
SO
SO
C_DP2_CTRL_CLK
SO
C_DP2_CTRL_DATA
P_COMP
ED
CATERR# for
60@
61@
I2
C_TS_INT#
CP
U_POPIRCOMP
PC
H_OPIRCOMP
RAM_OPIO_RCOMP
ED
PIO_RCOMP
EO
H_
CATERR#
H_
PECI
H_
PROCHOT#_R
THERMTRIP#
H_
P_BPM#0
XD
XD
P_BPM#1
C_TS_INT#
I2
_INT#
TP
UC1A
E55
DDI
1_TXN[0]
F55
DDI
1_TXP[0]
E58
1_TXN[1]
DDI
F58
1_TXP[1]
DDI
F53
DDI1_TXN[2]
G53
DDI
1_TXP[2]
F56
DDI
1_TXN[3]
G56
DDI
1_TXP[3]
C50
2_TXN[0]
DDI
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI
2_TXP[1]
A50
DDI
2_TXN[2]
B50
2_TXP[2]
DDI
D51
2_TXN[3]
DDI
C51
2_TXP[3]
DDI
L13
P_E18/DDPB_CTRLCLK
GP
L12
P_E19/DDPB_CTRLDATA
GP
N7
P_E20/DDPC_CTRLCLK
GP
N8
GPP_E21/DDPC_CTRLDATA
N11
GP
P_E22/DDPD_CTRLCLK
N12
GP
P_E23/DDPD_CTRLDATA
E52
P_RCOMP
ED
SKL-U_BGA1356
@
UC1D
D63
CATERR#
A54
PEC
I
C65
PR
OCHOT#
C63
TH
ERMTRIP#
A65
OCC#
SKT
C55
BPM#[0]
D55
BPM
#[1]
B54
BPM
#[2]
C56
BPM
#[3]
A6
P_E3/CPU_GP0
GP
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GP
P_B4/CPU_GP3
AT16
PR
OC_POPIRCOMP
AU16
H_OPIRCOMP
PC
H66
CE_RCOMP
OP
H65
OPC_RCOMP
SKL-U_BGA1356
@
CP
U MISC
C
DDI
DISPLAY SIDEBANDS
SKL-U
OF 20
4
-U
SKL
1
OF 20
JT
AG
PR
PROC_TDO
PR
PR
PC
H_JTAG_TCK
H_JTAG_TDI
PC
PCH_JTAG_TDO
PCH_JTAG_TMS
PC
ED
P
Rev_0.53
OC_TCK
OC_TDI
PR
OC_TMS
OC_TRST#
H_TRST#
JT
AGX
Rev
_0.53
ED
P_TXN[0]
ED
P_TXP[0]
P_TXN[1]
ED
P_TXP[1]
ED
EDP_TXN[2]
ED
P_TXP[2]
ED
P_TXN[3]
ED
P_TXP[3]
P_AUXN
ED
EDP_AUXP
ED
P_DISP_UTIL
1_AUXN
DDI
1_AUXP
DDI
2_AUXN
DDI
DDI2_AUXP
DDI3_AUXN
DDI
3_AUXP
P_E13/DDPB_HPD0
GP
P_E14/DDPC_HPD1
GP
P_E15/DDPD_HPD2
GP
GPP_E16/DDPE_HPD3
GP
P_E17/EDP_HPD
ED
P_BKLTEN
ED
P_BKLTCTL
P_VDDEN
ED
U_XDP_TCK0
CP
B61
C_XDP_TDI
SO
D60
C_XDP_TDO
SO
A61
SO
C_XDP_TMS
C60
SO
C_XDP_TRST#
B59
H_JTAG_TCK1
PC
B56
C_XDP_TDI
SO
D59
C_XDP_TDO
SO
A56
C_XDP_TMS
SO
C59
SO
C_XDP_TRST#
C61
CP
U_XDP_TCK0
A59
D
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
C_DP1_AUXN
SO
G50
C_DP1_AUXP
SO
F50
E48
F48
G46
F46
C_DP1_HPD
SO
L9
C_DP2_HPD
SO
L7
L6
EC
_SCI#
N9
CP
U_EDP_HPD
L10
R12
EN
BKL
C_BKL_PWM
SO
R11
C_ENVDD
SO
U13
#545659 PCH EDS 0.7 P.108
SCI capability is available on all GPIOs,
while NMI and SMI capability is available on
selected GPIOs only.
Below are the PCH GPIOs that can be routed to
generate SMI# or NMI:
î¡„
î¡„
î¡„
î¡„
ED
P_TXN0 29
ED
P_TXP0 29
ED
P_TXN1 29
ED
P_TXP1 29
ED
P_TXN2 29
P_TXP2 29
ED
P_TXN3 29
ED
ED
P_TXP3 29
ED
P_AUXN 29
ED
P_AUXP 29
C_DP1_AUXN 31
SO
SO
C_DP1_AUXP 31
SO
C_DP1_HPD 31
SO
C_DP2_HPD 30
EC
_SCI# 38
CP
U_EDP_HPD 29
BKL 38
EN
C_BKL_PWM 29
SO
C_ENVDD 29
SO
GPP_B14, GPP_B20, GPP_B23
GPP
_C[23: 22]
GPP_
D[4:0]
GPP_E[8:0],
GPP_E[16:13]
<eDP>
DP Aux (Port B for VGA)
From VGA Trans.
From HDMI
eDP
From
E
12
RC2
10K_0402_5%
_SCI#
EC
1 2
EC_SCI# SOC internal PU
VS
+3
@
+1
.0VS_VCCSTG
SO
B
C_XDP_TMS
SO
C_XDP_TDI
C_XDP_TDO
SO
C_XDP_TDO
SO
P_ITP_PMODE
XD
XDP_PRSENT_CPU
P_PRSENT_PCH
XD
CPU_XDP_TCK0
H_JTAG_TCK1
PC
CF
G0
P_SPI_SI
XD
CMC@
C2
SO
C_XDP_TMS
SO
C_XDP_TDI
C_XDP_TRST#
SO
C_XDP_TDO
SO
CF
G3
P_ITP_PMODE17
XD
P_SPI_SI8
XD
P_SPI_IO28
XD
EC
_RSMRST#10,38
XDP_ITP_PMODE XDP_HOOK6
P_SPI_SI
XD
H_JTAG_TCK1
PC
CPU_XDP_TCK0 XDP_TCK0
P_SPI_IO2
XD
RP
1 8
2 7
3 6
4 5
0_0804_8P4R_5%
1 2
RC5
5 0_0402_5%CMC@
RC56 0_0402_5%CMC@
1 2
CMC@
RPC15
1 8
2 7
3 6
4 5
0_0804_8P4R_5%
RC23 1K_0402_5%CMC@
1 2
curity Classification
curity Classificat ion
curity Classificat ion
Se
Se
Se
Is
Is
Is
sued Date
sued Date
sued Date
S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THI
THI
THI
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
XD
P_TMS
XD
P_TDI
P_TRST#
XD
P_TDO
XD
P_PRSENT_CPU
XD
P_HOOK3
XD
P_TCK1
XD
P_PRSENT_PCH
XD
XDP_HOOK0EC_RSMRST#
JPCMC1
1
CF
CF
G017
CF
G117
CF
G217
CF
G317
CFG417
CF
G517
CFG617
CF
G717
CFG1717
CF
G1617
CF
G817
CFG917
CFG1017
CF
G1117
CFG1217
CF
G1317
CFG1417
G1517
CF
CFG1917
CF
G1817
Compal Secret Data
Compal Secret Data
2014/
2014/
2014/
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
Compal Secret Data
G0
CF
G1
CF
G2
G3
CF
CF
G4
CF
G5
CF
G6
CF
G7
CF
G17
CFG16
CF
G8
CF
G9
CF
G10
CFG11
CF
G12
CFG13
CF
G14
CF
G15
CF
G19
CFG18
Deciphered Date
Deciphered Dat e
Deciphered Dat e
D
DATA_0
3
DATA_1
5
TA_2
DA
7
TA_3
DA
9
DA
TA_4
11
DA
TA_5
13
DA
TA_6
15
DATA_7
17
TA_CLK_1P
DA
21
DA
TA_CLK_1N
2
DA
TA_8
4
DA
TA_9
6
DATA_10
8
TA_11
DA
10
TA_12
DA
12
DA
TA_13
14
DA
TA_14
16
DA
TA_15
18
DATA_CLK_2P
20
TA_CLK_2N
DA
INTEL_CMC_PRIMARY
CONN@
+1
.0VALW_PRIM
OB
S DATA
XD
P CONN
1 2
RC1
2 0_0603_5%@
CMC_
+1
.0V_XDP
DEBUG_36P
JT
AG/RC/HOOKS
VCCOBS_AB
XD
P_TRST*
XD
XD
XDP_TCK0
XDP_TCK1
XD
XD
P_PREQ*
XD
P_PRDY*
HOOK_0
HO
HO
XD
P_PRSNT_PCH*
XD
P_PRSNT_CPU*
<M
Ti
Ti
Titl e
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
Date: Sheet
Date: Sheet
Date: Sheet
+1
.0V_XDP
22
P_TRST#
XD
28
P_TDI
XD
29
P_TDI
XDP_TMS
30
P_TMS
P_TDO
OK_3
OK_6
T> GND
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SKL-U(1/12)DDI,MSIC,XDP,EDP
SKL-U(1/12)DDI,MSIC,XDP,EDP
SKL-U(1/12)DDI,MSIC,XDP,EDP
P_TCK0
XD
32
XDP_TCK1
31
P_TDO
XD
35
P_PREQ#
XD
33
P_PRDY#
XD
34
P_HOOK0
XD
27
P_HOOK3
XD
25
P_HOOK6
XD
26
P_PRSENT_PCH
XD
24
P_PRSENT_CPU
XD
23
19
GND
36
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
E
XD
XD
660Monday, Jun e 22, 2015
660Monday, Jun e 22, 2015
660Monday, Jun e 22, 2015
P_PREQ# 12
P_PRDY# 12
of
of
of
0
0
0
1.
1.
1.
12
1 51_0402_5%CMC@
RC1
3 51_0402_5%CMC@
+1
.0V_XDP
VALW_PRIM
+3
RC1
RC1
RC1
RC3
RC43 0_0402_5%@
RC4
RC35 51_0402_1%CMC@
RC37 51_0402_5%@
RC151 1K_0402_5%@
RC9 1K_0402_5%CMC@
Place to CPU side
3 3
S CONN
AP
+3VALW_PRIM+3VALW
JA
PS1
1
1
_SLP_S3#10,38,42
PM
_SLP_S5#10
PM
PM
_SLP_S4#10,38,42
_SLP_A#10
PM
C_RTCRST#10
SO
SYS_
RESET#10
PM
_SLP_S0#10, 38
4 4
PBTN_OUT#10,38
ON
/OFFBTN#38,39
PBT
N_OUT#_R2
RC5
RC5
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GN
D
20
GND
ACES_50506-01841-P01
CONN@
AC
ES_50506-01841-P01_1 8P-NPM
12
3 0_0402_5%@
12
4 0_0402_5%@
A
Place to CPU side
PBT
N_OUT#_R2
12
12
5 51_0402_5%CMC@
12
7 51_0402_5%CMC@
1 2
1 1K_0402_5%CMC@
12
12
6 0_0402_5%@
12
12
12
Follow 544924_Skylake_EDS_Vol_1_ Rev_0.93
1 2
A
nterleaved Memory
I
1 1
SKL
UC1B
A_D[0..15]18
DDR_
DDR_
A_D[16..31]18
2 2
DDR_
A_D[32..47]18
DDR_
A_D[48..63]18
3 3
Sample
Pre_ES
UC1
CP
U_QH7Y_A2_1.6G
QH7Y@
SA0
0008A400
ES Sample
UC1
CPU_QHMF_C0_2.3G
QHMF@
SA0
0008M420
4 4
QS Sample
UC1
UC1
CPU_QHMG_C0_1.6G
QHMG@
SA0
UC1
0008M320
A_D0
DDR_
DDR_
A_D1
DDR_
A_D2
DDR_
A_D3
A_D4
DDR_
A_D5
DDR_
A_D6
DDR_
A_D7
DDR_
A_D8
DDR_
DDR_
A_D9
DDR_
A_D10
A_D11
DDR_
A_D12
DDR_
A_D13
DDR_
A_D14
DDR_
A_D15
DDR_
DDR_
A_D16
DDR_
A_D17
DDR_
A_D18
A_D19
DDR_
A_D20
DDR_
A_D21
DDR_
A_D22
DDR_
DDR_
A_D23
DDR_
A_D24
DDR_
A_D25
A_D26
DDR_
A_D27
DDR_
A_D28
DDR_
A_D29
DDR_
DDR_
A_D30
DDR_
A_D31
DDR_
A_D32
DDR_
A_D33
A_D34
DDR_
A_D35
DDR_
A_D36
DDR_
DDR_
A_D37
DDR_
A_D38
DDR_
A_D39
DDR_
A_D40
A_D41
DDR_
A_D42
DDR_
A_D43
DDR_
DDR_
A_D44
DDR_
A_D45
DDR_
A_D46
DDR_
A_D47
DDR_
A_D48
A_D49
DDR_
A_D50
DDR_
DDR_
A_D51
DDR_
A_D52
A_D53
DDR_
DDR_
A_D54
DDR_
A_D55
A_D56
DDR_
A_D57
DDR_
A_D58
DDR_
DDR_
A_D59
DDR_A_D60
DDR_
A_D61
DDR_A_D62
A_D63
DDR_
AL71
DDR0
AL68
DDR0
AN68
DDR0_DQ[2]
AN69
DDR0
AL70
DDR0
AL69
DDR0
AN70
DDR0
AN71
DDR0
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0
AU68
DDR0
AR71
DDR0
AR69
DDR0
AU70
DDR0
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0
AW63
DDR0
AY63
DDR0
BA65
DDR0
AY65
DDR0
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0
BA61
DDR0
AW61
DDR0
BB59
DDR0
AW59
DDR0
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0
AY59
DDR0
AY39
DDR0
AW39
DDR0
AY37
DDR0
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0
BA37
DDR0
BB37
DDR0
AY35
DDR0
AW35
DDR0
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0
BB35
DDR0
BA35
DDR0
BA33
DDR0
BB33
DDR0
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0
AW29
DDR0
BB31
DDR0
BA31
DDR0
BA29
DDR0
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0
AY25
DDR0
AW25
DDR0
BB27
DDR0
BA27
DDR0
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0
SKL-U_BGA1356
@
UC1
_DQ[0]
_DQ[1]
_DQ[3]
_DQ[4]
_DQ[5]
_DQ[6]
_DQ[7]
_DQ[10]
_DQ[11]
_DQ[12]
_DQ[13]
_DQ[14]
_DQ[17]/DDR0_DQ[33]
_DQ[18]/DDR0_DQ[34]
_DQ[19]/DDR0_DQ[35]
_DQ[20]/DDR0_DQ[36]
_DQ[21]/DDR0_DQ[37]
_DQ[23]/DDR0_DQ[39]
_DQ[24]/DDR0_DQ[40]
_DQ[25]/DDR0_DQ[41]
_DQ[26]/DDR0_DQ[42]
_DQ[27]/DDR0_DQ[43]
_DQ[30]/DDR0_DQ[46]
_DQ[31]/DDR0_DQ[47]
_DQ[32]/DDR1_DQ[0]
_DQ[33]/DDR1_DQ[1]
_DQ[34]/DDR1_DQ[2]
_DQ[37]/DDR1_DQ[5]
_DQ[38]/DDR1_DQ[6]
_DQ[39]/DDR1_DQ[7]
_DQ[40]/DDR1_DQ[8]
_DQ[41]/DDR1_DQ[9]
_DQ[43]/DDR1_DQ[11]
_DQ[44]/DDR1_DQ[12]
_DQ[45]/DDR1_DQ[13]
_DQ[46]/DDR1_DQ[14]
_DQ[47]/DDR1_DQ[15]
_DQ[50]/DDR1_DQ[34]
_DQ[51]/DDR1_DQ[35]
_DQ[52]/DDR1_DQ[36]
_DQ[53]/DDR1_DQ[37]
_DQ[54]/DDR1_DQ[38]
_DQ[57]/DDR1_DQ[41]
_DQ[58]/DDR1_DQ[42]
_DQ[59]/DDR1_DQ[43]
_DQ[60]/DDR1_DQ[44]
_DQ[61]/DDR1_DQ[45]
_DQ[63]/DDR1_DQ[47]
-U
_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0
_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0
_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0
_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0
_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0
_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0
_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0
_CAS#/DDR0_CAB[1]/DDR0_MA[15]
_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0
_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0
_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0
_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0
_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0
DDR0
DDR0
DDR0
DDR
CH - A
2 OF 20
B
_CKN[0]
DDR0
_CKP[0]
DDR0
_CKN[1]
DDR0
DDR0_CKP[1]
DDR0
_CKE[0]
DDR0
_CKE[1]
DDR0
_CKE[2]
_CKE[3]
DDR0
DDR0_CS#[0]
DDR0
_CS#[1]
DDR0
_ODT[0]
DDR0
_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0
_DQSN[0]
DDR0
_DQSP[0]
_DQSN[1]
DDR0
_DQSP[1]
DDR0
_DQSP[2]/DDR0_DQSP[4]
_DQSN[3]/DDR0_DQSN[5]
_DQSP[3]/DDR0_DQSP[5]
_DQSN[4]/DDR1_DQSN[0]
_DQSP[4]/DDR1_DQSP[0]
_DQSN[6]/DDR1_DQSN[4]
_DQSP[6]/DDR1_DQSP[4]
_DQSN[7]/DDR1_DQSN[5]
_DQSP[7]/DDR1_DQSP[5]
DDR0_ALERT#
DDR0_PAR
DDR_
VREF_CA
DDR0
_VREF_DQ
_VREF_DQ
DDR1
DDR_VTT_CNTL
A_CLK#0
DDR_
AU53
A_CLK0
DDR_
AT53
DDR_
A_CLK#1
AU55
DDR_
A_CLK1
AT55
A_CKE0
DDR_
BA56
A_CKE1
DDR_
BB56
AW56
AY56
DDR_
A_CS#0
AU45
DDR_
A_CS#1
AU43
A_ODT0
DDR_
AT45
A_ODT1
DDR_
AT43
A_MA5
DDR_
BA51
A_MA9
DDR_
BB54
DDR_
A_MA6
BA52
DDR_
A_MA8
AY52
DDR_
A_MA7
AW52
A_BS2
DDR_
AY55
A_MA12
DDR_
AW54
A_MA11
DDR_
BA54
A_MA15
DDR_
BA55
DDR_
A_MA14
AY54
DDR_
A_MA13
AU46
A_CAS#
DDR_
AU48
A_WE#
DDR_
AT46
A_RAS#
DDR_
AU50
A_BS0
DDR_
AU52
DDR_
A_MA2
AY51
DDR_
A_BS1
AT48
DDR_
A_MA10
AT50
DDR_
A_MA1
BB50
A_MA0
DDR_
AY50
A_MA3
DDR_
BA50
A_MA4
DDR_
BB52
DDR_
A_DQS#0
AM70
DDR_
A_DQS0
AM69
DDR_
A_DQS#1
AT69
A_DQS1
DDR_
AT70
A_DQS#2
DDR_
BA64
A_DQS2
DDR_
AY64
DDR_
A_DQS#3
AY60
DDR_
A_DQS3
BA60
DDR_
A_DQS#4
BA38
DDR_
A_DQS4
AY38
DDR_
A_DQS#5
AY34
A_DQS5
DDR_
BA34
A_DQS#6
DDR_
BA30
DDR_
A_DQS6
AY30
DDR_
A_DQS#7
AY26
A_DQS7
DDR_
BA26
AW50
AT52
.675V_VREFCA
+0
AY67
+0
.675V_A_VREFDQ
AY68
+0.675V_B_VREFDQ
BA67
DDR_PG_CTRL
AW67
D
DR_VTT_CNTL to DDR
VTT supplied ramped
<35uS
(tCPU18)
DDR_PG_CTRL
Re
serve for cost test.
4@
T1
T1
5@
2@
T2
+0
+0.675V_A_VREFDQ
+0
DDR_
A_CLK#0 18
DDR_
A_CLK0 18
DDR_
A_CLK#1 18
DDR_
A_CLK1 18
A_CKE0 18
DDR_
A_CKE1 18
DDR_
DDR_
A_CS#0 18
DDR_
A_CS#1 18
DDR_
A_ODT0 18
A_ODT1 18
DDR_
DDR_
A_MA5 18
DDR_
A_MA9 18
DDR_
A_MA6 18
DDR_
A_MA8 18
DDR_
A_MA7 18
A_BS2 18
DDR_
A_MA12 18
DDR_
A_MA11 18
DDR_
DDR_
A_MA15 18
DDR_
A_MA14 18
DDR_
A_MA13 18
DDR_A_CAS# 18
A_WE# 1 8
DDR_
A_RAS# 18
DDR_
DDR_
A_BS0 18
DDR_
A_MA2 18
DDR_
A_BS1 18
DDR_
A_MA10 18
DDR_A_MA1 18
A_MA0 18
DDR_
A_MA3 18
DDR_
A_MA4 18
DDR_
DDR_
A_DQS#0 18
DDR_
A_DQS0 18
DDR_A_DQS#1 18
A_DQS1 18
DDR_
A_DQS#2 18
DDR_
A_DQS2 18
DDR_
DDR_
A_DQS#3 18
DDR_
A_DQS3 18
DDR_
A_DQS#4 18
DDR_A_DQS4 18
A_DQS#5 18
DDR_
A_DQS5 18
DDR_
A_DQS#6 18
DDR_
A_DQS6 18
DDR_
DDR_
A_DQS#7 18
DDR_
A_DQS7 18
.675V_VREFCA
.675V_B_VREFDQ
NC1VC
2
A
3
D
GN
74AUP1G07GW_TSS OP5
.35V_VDDQ
+1
G
S
Q2009
@
MESS138W -G_SOT3 23-3
C
B_D[0..15]19
DDR_
DDR_
B_D[16..31]19
DDR_
B_D[32..47]19
DDR_
B_D[48..63]19
Trace
width/Spacing >= 20mils
Place componment near SODIMM
#543016 PDG0.9 P.163 RC place near SODIMM
+1.35V_VDDQ
+3VS
12
CC57.1U_0402_16V7K
UC7
C
Y
12
5
4
RC10
220K_0402_5%
RC16
2M_0402_5%@
1 2
123
D
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_B_D60
DDR_
DDR_B_D62
DDR_
SM_PG_CTRL 47
B_D0
B_D1
B_D2
B_D3
B_D4
B_D5
B_D6
B_D7
B_D8
B_D9
B_D10
B_D11
B_D12
B_D13
B_D14
B_D15
B_D16
B_D17
B_D18
B_D19
B_D20
B_D21
B_D22
B_D23
B_D24
B_D25
B_D26
B_D27
B_D28
B_D29
B_D30
B_D31
B_D32
B_D33
B_D34
B_D35
B_D36
B_D37
B_D38
B_D39
B_D40
B_D41
B_D42
B_D43
B_D44
B_D45
B_D46
B_D47
B_D48
B_D49
B_D50
B_D51
B_D52
B_D53
B_D54
B_D55
B_D56
B_D57
B_D58
B_D59
B_D61
B_D63
UC1C
AF65
_DQ[0]/DDR0_DQ[16]
DDR1
AF64
_DQ[1]/DDR0_DQ[17]
DDR1
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1
_DQ[3]/DDR0_DQ[19]
AF66
DDR1
_DQ[4]/DDR0_DQ[20]
AF67
DDR1
_DQ[5]/DDR0_DQ[21]
AK67
DDR1
_DQ[6]/DDR0_DQ[22]
AK66
_DQ[7]/DDR0_DQ[23]
DDR1
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1
_DQ[10]/DDR0_DQ[26]
AH68
DDR1
_DQ[11]/DDR0_DQ[27]
AF71
DDR1
_DQ[12]/DDR0_DQ[28]
AF69
_DQ[13]/DDR0_DQ[29]
DDR1
AH70
_DQ[14]/DDR0_DQ[30]
DDR1
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1
_DQ[17]/DDR0_DQ[49]
AP65
DDR1
_DQ[18]/DDR0_DQ[50]
AN65
DDR1
_DQ[19]/DDR0_DQ[51]
AN66
_DQ[20]/DDR0_DQ[52]
DDR1
AP66
_DQ[21]/DDR0_DQ[53]
DDR1
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1
_DQ[23]/DDR0_DQ[55]
AT61
DDR1
_DQ[24]/DDR0_DQ[56]
AU61
DDR1
_DQ[25]/DDR0_DQ[57]
AP60
DDR1
_DQ[26]/DDR0_DQ[58]
AN60
_DQ[27]/DDR0_DQ[59]
DDR1
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1
_DQ[30]/DDR0_DQ[62]
AU60
DDR1
_DQ[31]/DDR0_DQ[63]
AU40
DDR1
_DQ[32]/DDR1_DQ[16]
AT40
_DQ[33]/DDR1_DQ[17]
DDR1
AT37
_DQ[34]/DDR1_DQ[18]
DDR1
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1
_DQ[37]/DDR1_DQ[21]
AP37
DDR1
_DQ[38]/DDR1_DQ[22]
AR37
DDR1
_DQ[39]/DDR1_DQ[23]
AT33
_DQ[40]/DDR1_DQ[24]
DDR1
AU33
_DQ[41]/DDR1_DQ[25]
DDR1
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1
_DQ[43]/DDR1_DQ[27]
AR33
DDR1
_DQ[44]/DDR1_DQ[28]
AP33
DDR1
_DQ[45]/DDR1_DQ[29]
AR30
DDR1
_DQ[46]/DDR1_DQ[30]
AP30
_DQ[47]/DDR1_DQ[31]
DDR1
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1
_DQ[50]
AU25
DDR1
_DQ[51]
AP27
DDR1
_DQ[52]
AN27
_DQ[53]
DDR1
AN25
_DQ[54]
DDR1
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1
_DQ[57]
AU21
DDR1
_DQ[58]
AT21
DDR1
_DQ[59]
AN22
_DQ[60]
DDR1
AP22
DDR1
_DQ[61]
AP21
DDR1_DQ[62]
AN21
_DQ[63]
DDR1
SKL-U_BGA1356
@
D
-U
SKL
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1
_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1
_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1
_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1
_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1
_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1
_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1
_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1
_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1
_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1
_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1
_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1
DDR1
DDR1
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1
DDR
CH - B
3 OF 20
Rev
_0.53Rev_0.53
_CKN[0]
DDR1
_CKN[1]
DDR1
DDR1_CKP[0]
DDR1
_CKP[1]
DDR1
_CKE[0]
DDR1
_CKE[1]
_CKE[2]
DDR1
DDR1_CKE[3]
DDR1
_CS#[0]
DDR1
_CS#[1]
DDR1
_ODT[0]
_ODT[1]
DDR1
DDR1_MA[3]
DDR1
_DQSN[0]/DDR0_DQSN[2]
_DQSP[0]/DDR0_DQSP[2]
_DQSN[1]/DDR0_DQSN[3]
_DQSN[2]/DDR0_DQSN[6]
_DQSP[2]/DDR0_DQSP[6]
_DQSN[3]/DDR0_DQSN[7]
_DQSP[3]/DDR0_DQSP[7]
_DQSN[4]/DDR1_DQSN[2]
_DQSP[5]/DDR1_DQSP[3]
_MA[4]
DDR1
_DQSN[6]
DDR1
_DQSP[6]
_DQSN[7]
DDR1
_DQSP[7]
DDR1
DDR1_ALERT#
DDR1
_PAR
DRA
M_RESET#
DDR_
RCOMP[0]
RCOMP[1]
DDR_
DDR_
RCOMP[2]
MP Sample Add on 7/14
UC1
CP
U_ i3-6100U_D1_2.3G
SR2EU@
00092NB0
SA0
B_CLK#0
DDR_
AN45
DDR_
B_CLK#1
AN46
DDR_
B_CLK0
AP45
DDR_
B_CLK1
AP46
B_CKE0
DDR_
AN56
B_CKE1
DDR_
AP55
AN55
AP53
DDR_
B_CS#0
BB42
B_CS#1
DDR_
AY42
B_ODT0
DDR_
BA42
B_ODT1
DDR_
AW42
B_MA5
DDR_
AY48
DDR_
B_MA9
AP50
DDR_
B_MA6
BA48
DDR_
B_MA8
BB48
B_MA7
DDR_
AP48
B_BS2
DDR_
AP52
B_MA12
DDR_
AN50
B_MA11
DDR_
AN48
DDR_
B_MA15
AN53
DDR_
B_MA14
AN52
B_MA13
DDR_
BA43
B_CAS#
DDR_
AY43
B_WE#
DDR_
AY44
B_RAS#
DDR_
AW44
DDR_
B_BS0
BB44
DDR_
B_MA2
AY47
DDR_
B_BS1
BA44
DDR_
B_MA10
AW46
B_MA1
DDR_
AY46
B_MA0
DDR_
BA46
B_MA3
DDR_
BB46
DDR_
B_MA4
BA47
DDR_
B_DQS#0
AH66
DDR_
B_DQS0
AH65
B_DQS#1
DDR_
AG69
B_DQS1
DDR_
AG70
B_DQS#2
DDR_
AR66
DDR_
B_DQS2
AR65
DDR_
B_DQS#3
AR61
DDR_
B_DQS3
AR60
DDR_
B_DQS#4
AT38
DDR_
B_DQS4
AR38
B_DQS#5
DDR_
AT32
B_DQS5
DDR_
AR32
DDR_
B_DQS#6
AR25
DDR_
B_DQS6
AR27
B_DQS#7
DDR_
AR22
DDR_
B_DQS7
AR21
AN43
AP43
DRAMRST#
DDR_
AT13
AR18
AT18
SM
_RCOMP0
AU18
SM_RCOMP1
_RCOMP2
SM
#543016 PDG0.9 P.117
W=12-15 Space= 20/25 L=500mil
UC1
CP
U_i5-6200U_D1_2.3G
SR2EY@
00092OB0
SA0
T1
7@
T1
8@
E
3@
T2
RC3
8 121_0402_1%
1 2
1 2
RC3
9 80.6_0402_1%
1 2
RC4
0 100_0402_1%
UC1
CP
U_i7-6500U_D1_2.5G
SR2EZ@
SA0
DDR_
B_CLK#0 19
DDR_
B_CLK#1 19
DDR_
B_CLK0 19
DDR_
B_CLK1 19
B_CKE0 19
DDR_
B_CKE1 19
DDR_
DDR_
B_CS#0 19
DDR_
B_CS#1 19
B_ODT0 1 9
DDR_
B_ODT1 1 9
DDR_
DDR_
B_MA5 19
DDR_
B_MA9 19
DDR_
B_MA6 19
DDR_
B_MA8 19
B_MA7 19
DDR_
B_BS2 19
DDR_
B_MA12 19
DDR_
DDR_
B_MA11 19
DDR_
B_MA15 19
DDR_
B_MA14 19
DDR_B_MA13 19
B_CAS# 19
DDR_
B_WE# 19
DDR_
DDR_
B_RAS# 19
DDR_
B_BS0 19
DDR_
B_MA2 19
DDR_
B_BS1 19
DDR_B_MA10 19
B_MA1 19
DDR_
B_MA0 19
DDR_
B_MA3 19
DDR_
DDR_
B_MA4 19
DDR_
B_DQS#0 19
DDR_B_DQS0 19
B_DQS#1 19
DDR_
B_DQS1 19
DDR_
B_DQS#2 19
DDR_
DDR_
B_DQS2 19
DDR_
B_DQS#3 19
DDR_
B_DQS3 19
DDR_B_DQS#4 19
B_DQS4 19
DDR_
B_DQS#5 19
DDR_
B_DQS5 19
DDR_
B_DQS#6 19
DDR_
DDR_
B_DQS6 19
DDR_
B_DQS#7 19
DDR_B_DQS7 19
DRAMRST# 18,19
DDR_
00092P90
U_ i3-6100U_D0_2.3G
CP
QJFC@
SA0
00092N30
U_i5-6200U_D0_2.3G
CP
QJ8N@
SA0
00092O30
A
U_i7-6500U_D0_2.5G
CP
QJ8L@
SA0
00092P20
curity Classification
curity Classificat ion
curity Classificat ion
Se
Se
Se
Is
Is
Is
sued Date
sued Date
sued Date
S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S SHEE T OF ENGINEERI NG DR AWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THI
THI
THI
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORM ATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2014/
2014/
2014/
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Dat e
Deciphered Dat e
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Ti
Ti
Ti
tle
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
Date: Sheet
Date: Sheet
D
Date: Sheet
L-U(2/12)DDRIII
L-U(2/12)DDRIII
L-U(2/12)DDRIII
SK
SK
SK
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
Tuesday, July 14, 2015
Tuesday, July 14, 2015
Tuesday, July 14, 2015
E
0
0
0
1.
1.
1.
60
60
60
7
7
7
of
of
of
A
C_SPI_SI
ROM
SO
C_SPI_IO2
SO
SO
C_SPI_CLK
SO
C_SPI_SO
SOC_SPI_SI
C_SPI_IO2
SO
C_SPI_IO3
SO
C_SPI_CS#0
SO
SO
C_SPI_CS#1
1 2
4 1K_0402_1%CMC@
XDP_
SPI_SI6
SPI_IO26
XDP_
RC2
1/44 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP
RC4
RC2
1 1K_0402_1%CMC@
1 2
SPI
1 1
SPI Touch
KBRST#_R
LPC
SO
SO
SO
SO
SO
15_0402_5%
1 2
C_SPI_IO3_0_R
C_SPI_CLK_0_R
C_SPI_SI_0_R
_SPI
C_SPI_CLK_0_R
C_SPI_SI_0_R
C_SPI_SO_0_R
EC_
M_SERIRQ
TP
Mode
C_SPI_IO3
C_SPI_SI
C_SPI_CLK
C_SPI_SO
C_SPI_IO2
CC8
.1
U_0402 _16V7K
1 2
EC_
KBRST#_R38
M_SERIRQ38,39
To TPM
2 2
RPC5
33_0804_8P
4R_5%
8M_DUAL@
SD
309330A80
3 3
Single SPI ROM_CS0#
To SPI ROM
SPI
ROM ( 8MByte )
SO
C_SPI_CS#0
SO
C_SPI_SO_0_R
SO
C_SPI_IO2_0_R
M Socket
4 4
RO
SO
C_SPI_CS#0
SO
C_SPI_IO2_0_R
SO
C_SPI_IO3_0_R
RC5
2
33_0402_5%
8M
_DUAL@
SD
028330A80
RPC5
UC2
1
/C
S
2
DO
(IO1)
3
P(IO2)
/W
4
D
GN
W25Q64FVSSIQ_SO8
8M_SINGLE@
JC
1
1
CS#
3
WP#
7
LD#
HO
4
D
GN
ACES_91960-0084N_MX25L3206EM2I
CONN@
A
TP
UC2
W2
5Q64FVSSIQ_SO8
8M_DUAL@
SA0
00039A30
and RC52 are close UC2
C_SPI_IO3_0_R
SO
C_SPI_SI_0_R
SO
C_SPI_CLK_0_R
SO
SO
C_SPI_SO_0_R
C_SPI_IO2_0_R
SO
/H
OLD(IO3)
DI
VCC
SCLK
/SIO0
SI
/SIO1
SO
VC
CL
(IO0)
RC5
8M
_SINGLE@
C
K
8
6
5
2
2
8
7
6
5
RPC5
1 8
2 7
3 6
4 5
15_0804_8P4R_5%
8M_SINGLE@
1 2
+3VALW_SPI
SO
SO
SO
+3VALW
SO
SO
SO
C_SPI_CLK_0_R
SO
RC2
0_0402_5%@EMC@
AW3
AW2
AW13
AY11
AV2
SPI
SPI0_MISO
AV3
SPI
SPI
AU4
SPI
AU3
SPI
AU2
SPI
AU1
SPI
M2
GP
M3
GP
J4
GP
V1
GP
V2
GP
M1
GP
G3
CL_CLK
G2
CL
G1
CL
GP
GP
SKL-U_BGA1356
@
4
B
UC1E
SPI
- FLASH
0_CLK
0_MOSI
0_IO2
0_IO3
0_CS0#
0_CS1#
0_CS2#
SPI - TOUCH
P_D1/SPI1_CLK
P_D2/SPI1_MISO
P_D3/SPI1_MOSI
P_D21/SPI1_IO2
P_D22/SPI1_IO3
P_D0/SPI1_CS#
C LINK
_DATA
_RST#
P_A0/RCIN#
P_A6/SERIRQ
1 2
CC9
_0402_50V8J
10P
@EMC@
B
Dua
l SPI ROM_CS1#
ROM ( 2/4/8/16MByte )
SPI
C_SPI_CS#1
SO
C_SPI_SO_1_R
SO
C_SPI_IO2_1_R
SO
C
-U
SKL
SMBUS, SMLINK
GPP_C0/SMBCLK
GP
GP
P_C2/SMBALERT#
GP
GP
GP
P_C5/SML0ALERT#
GP
GP
P_B23/SML1ALERT#/PCHHOT#
P_A1/LAD0/ESPI_IO0
GP
P_A2/LAD1/ESPI_IO1
GP
GP
P_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
P_A5/LFRAME#/ESPI_CS#
GP
P_A14/SUS_STAT#/ESPI_RESET#
P_A9/CLKOUT_LPC0/ESPI_CLK
GP
P_A10/CLKOUT_LPC1
GP
1 2
1 2
LPC
PM_
CLKRUN#
M_SERIRQ
TP
GP
GP
GP
5
OF 20
RC107 10K_0402_5%
RC1
12 10K_0402_5%
2015MOW06 no need PU1K on SPI_IO2/IO3
C_SPI_IO2
SO
SO
C_SPI_IO3
add PD 1K depop PH 1K
MOW36
only for SKL U ES sample
7 1K_0402_1%@
RC4
RC4
8 1K_0402_1%@
1 1K_0402_1%ES@
RC5
1 2
1 2
1 2
RPC23 and RC59 are close UC9
RPC2
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
8M_DUAL@
8M_DUAL@
RC5
9 33_0402_5%
+3VALW_SPI
8
C
C_SPI_IO3_1_R
SO
7
C_SPI_CLK_1_R
SO
6
K
C_SPI_SI_1_R
SO
5
SO
C_SPI_CLK_1_R
C
To SPI ROM
C_SPI_IO3_1_R
SO
SO
C_SPI_CLK_1_R
SO
C_SPI_SI_1_R
SO
C_SPI_SO_1_R
SO
C_SPI_IO2_1_R
UC9
1
S
/C
2
(IO1)
DO
3
P(IO2)
/W
4
GN
D
W2
5Q16DVSSIQ_SO8
8M_DUAL@
Security Classification
Security Classification
Security Classification
TH
TH
TH
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VC
OLD(IO3)
/H
CL
DI
(IO0)
Issued Date
Issued Date
Issued Date
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
Rev_0.5
3
SO
C_SMBCLK_1
R7
SOC_SMBDATA_1
P_C1/SMBDATA
P_C3/SML0CLK
P_C4/SML0DATA
P_C6/SML1CLK
P_C7/SML1DATA
P_A8/CLKRUN#
+1.
3
12
1 2
R8
C_SMBALERT#
SO
R10
C_SML0CLK
SO
R9
SO
C_SML0DATA
W2
SO
C_SML0ALERT#
W1
SO
C_SML1CLK
W3
C_SML1DATA
SO
V3
C_SML1ALERT#
SO
AM7
C_AD0
LP
AY13
C_AD1
LP
BA13
C_AD2
LP
BB13
C_AD3
LP
AY12
LP
C_FRAME#
BA12
ESPI
_RST#
BA11
_CLK
ESPI
AW9
LPC_TPM_R
CK_
AY9
CLKRUN#
PM_
AW11
8VS_3VS_PGPPA
+3VALW
_SPI
C_SPI_IO3
SO
SO
C_SPI_CLK
SO
C_SPI_SI
SO
C_SPI_SO
SO
C_SPI_IO2
CC1
01
.1U_040 2_16V7K
8M_DUAL@
RC2
6
1 2
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
2014/
0_0402_5%@EMC@
CC7
Co
Co
Co
1 2
0
10P_0402_50V8J
mpal Secret Data
mpal Secret Data
mpal Secret Data
1 2
44 0_0402_5%@
RC1
1 2
45 0_0402_5%@
RC1
1 2
RC1
46 0_0402_5%@
1 2
RC1
47 0_0402_5%@
5 22_0402_5%
RC4
LP
R3
TP
95 22_0402_5 %
C_SML0CLK
SO
SO
C_SML0DATA
C_SMBCLK_1
SO
C_SMBDATA_1
SO
C_SML1CLK
SO
SO
C_SML1DATA
@EMC@
Deciphered Date
Deciphered Date
Deciphered Date
T239@
SO
C_SML1CLK 20,31,38
SO
C_SML1DATA 20,31,38
T234@
C_FRAME# 38,39
LP
ESPI
_RST# 38
12
C@
12
M@
CLKRUN# 39
PM_
1 2
RC4
9 499_0402_1%
1 2
RC5
0 499_0402_1%
1 8
2 7
3 6
4 5
SO
C_SMBCLK_1
C_SMBDATA_1
SO
D
+3VALW
12
RC2
024.7K_0402_5% ESPI@
RPC7
2K_0804_8P4R_5%
2.
D
_PRIM
St
rap Pin
LP
C_AD0_R 38,39
LPC_AD1_R 38,39
C_AD2_R 38,39
LP
C_AD3_R 38,39
LP
ESPI
_CLK_R 38
LPC_TPM 39
CK_
For TPM
+3VALW
+3VS
5
3 4
6 1
2
+3VS
E
SM
B
(Link to XDP, DDR)
SML1
(Link to EC,DGPU)
ESPI
/ LPC Bus
ESPI
: +1.8V
LPC : +3.3V
Change RC144~RC147, RC45 to
15ohm when use ESPI
To
EC
_PRIM
+3VS
C_SMBCLK
SO
C_SMBDATA
SO
Q2
017B
DMN66D0LDW-7_SOT363-6
SO
C_SMBCLK
C_SMBDATA
SO
Q2
017A
DM
N66D0LDW-7_SOT363-6
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
L-U(3/12)SPI,ESPI,SMB,LPC
L-U(3/12)SPI,ESPI,SMB,LPC
L-U(3/12)SPI,ESPI,SMB,LPC
SK
SK
SK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
Date: Sheet
Date: Sheet
Date: Sheet
1 2
22 2.2K_0402_5%
RC2
1 2
RC2
23 2.2K_0402_5%
SO
C_SMBCLK 18,19,41
C_SMBDATA 18,19,41
SO
860Tuesday, June 16, 2015
860Tuesday, June 16, 2015
860Tuesday, June 16, 2015
of
of
E
of
0
0
0
1.
1.
1.
A
SKL_PCH_EDS_R0.7 P.84
#545659
1 1
tional Strap Definitions
Func
SPK
R / GPP_B14 (Internal Pull Down):
(Sampled:Rising edge of PCH_PWROK)
TOP Swap Overr ide
0 = Disable TOP Swap mode.---> AAX05 Use
1 = Enable TOP Swap Mode.
2 2
PCH_
PCH_
DMIC_CLK40
DMIC_DATA40
B
UC1G
AU
HDA_SYNC
HDA_
HDA_
HDA_
HDA_
PCH_
PCH_
SPKR40
BIT_CLK
SDOUT
SDIN0
RST#
DMIC_CLK
DMIC_DATA
SPKR
BA22
AY22
BB22
BA21
AY21
AW22
AY20
AW20
AK7
AK6
AK9
AK10
AW5
J5
H5
D7
D8
C8
SKL-U_BGA1356
@
DIO
_SYNC/I2S0_SFRM
HDA
HDA
_BLK/I2S0_SCLK
HDA
_SDO/I2S0_TXD
_SDI0/I2S0_RXD
HDA
_SDI1/I2S1_RXD
HDA
HDA
_RST#/I2S1_SCLK
GP
P_D23/I2S_MCLK
S1_SFRM
I2
S1_TXD
I2
GP
P_F1/I2S2_SFRM
P_F0/I2S2_SCLK
GP
P_F2/I2S2_TXD
GP
GP
P_F3/I2S2_RXD
P_D19/DMIC_CLK0
GP
GP
P_D20/DMIC_DATA0
P_D17/DMIC_CLK1
GP
GP
P_D18/DMIC_DATA1
P_B14/SPKR
GP
HDA
for AUDIO
HDA_
HDA_
HDA_
HDA_
SYNC_R40
SDOUT_R40
BIT_CLK_R40
RST#_R40
HDA_
ME_
EN38
SDIN040
C
-U
SKL
7
OF 20
RPC9
1 8
2 7
3 6
4 5
33_0804_8P
1 2
7 0_0402_5%
RC7
SDIO/SDX C
GP
GP
GP
GP
GP
P_A17/SD_PWR_EN#/ISH_GP7
GP
P_A16/SD_1P8_SEL
HDA_
SYNC
HDA_
SDOUT
HDA_BIT_CLK
RST#
HDA_
4R_5%
HDA_
HDA_
SDOUT
SDIN0
@
Rev_0.5
P_G0/SD_CMD
GP
P_G1/SD_DATA0
P_G2/SD_DATA1
P_G3/SD_DATA2
P_G4/SD_DATA3
GP
P_G5/SD_CD#
GP
P_G6/SD_CLK
P_G7/SD_WP
GP
_RCOMP
SD
P_F23
GP
D
3
#543016 PDG0.9 P.321
Terminating Unused SDIO/SDXC Signals
SDIO signals are multiplexed with GPIOs and
default to GPIO functionality (as input). If
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
SDIO interface is not used, the signals
can be used as GPIOs instead. If the GPIO
functionality is also not used, the signals can
be left as no-connect.
RCOMP
SD_
RC7
6 200_0402_1%
12
E
_ULT
UC1I
CSI-2
A36
CS
I2_DN0
B36
CS
I2_DP0
C38
CSI2_DN1
D38
I2_DP1
CS
C36
I2_DN2
CS
D36
CS
I2_DP2
A38
I2_DN3
CS
B38
I2_DP3
CS
3 3
4 4
A
B
C31
CS
D31
CS
C33
CS
D33
CS
A31
CS
B31
CS
A33
CS
B33
CS
A29
CS
B29
CS
C28
CS
D28
CSI2_DP9
A27
CS
B27
CS
C27
CS
D27
CS
SKL-U_BGA1356
@
I2_DN4
I2_DP4
I2_DN5
I2_DP5
I2_DN6
I2_DP6
I2_DN7
I2_DP7
I2_DN8
I2_DP8
I2_DN9
I2_DN10
I2_DP10
I2_DN11
I2_DP11
SKL
GP
GP
GP
GP
GP
GP
GP
GPP_F20/EMMC_DATA7
GP
9
OF 20
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
TH
TH
TH
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Rev_0.53
CS
CS
CSI2_CLKN1
CS
CS
CS
CS
CS
CS
P_D4/FLASHTRIG
GP
MC
EM
P_F13/EMMC_DATA0
P_F14/EMMC_DATA1
P_F15/EMMC_DATA2
P_F16/EMMC_DATA3
P_F17/EMMC_DATA4
P_F18/EMMC_DATA5
P_F19/EMMC_DATA6
P_F21/EMMC_RCLK
GP
P_F22/EMMC_CLK
P_F12/EMMC_CMD
GP
EM
MC_RCOMP
2014/
2014/
2014/
C37
I2_CLKN0
D37
I2_CLKP0
C32
D32
I2_CLKP1
C29
I2_CLKN2
D29
I2_CLKP2
B26
I2_CLKN3
A26
I2_CLKP3
I2_COMP
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2_COMP
CSI
E13
DG
PU_PRSNT#
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
EMMC_
AT1
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
RC8
0 100_0402_1%
RCOMP
RC8
9 200_0402_1%
Deciphered Date
Deciphered Date
Deciphered Date
12
12
D
_1.8VALW_PGPPD
+3VALW
12
33
RC1
UMA@
10K_0402_5%
PU_PRSNT#
DG
12
RC1
VGA@
34
10K_0402_5%
GPIO67
DG
PU_PRSNT#
DIS,Optim
us10
UMA
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
L-U(4/12)HDA,EMMC,SDIO,CSI2
L-U(4/12)HDA,EMMC,SDIO,CSI2
L-U(4/12)HDA,EMMC,SDIO,CSI2
SK
SK
SK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
Date: Sheet
Tuesday, June 16, 2015
Date: Sheet
Tuesday, June 16, 2015
Date: Sheet
Tuesday, June 16, 2015
E
9
9
9
60
60
60
of
of
of
0
0
0
1.
1.
1.
A
CVCC
+RT
SO
PWROK
RSMRST#
S_RESET#
N_WAKE#
BATLOW#
PM_
WA
KE#
AC_
PRESENT
SO
C_VRALERT#
C_SRTCRST#
PH at DGPU side
SO
C_RTCRST#
NGFF WL+BT(KEY E)
CLR
CMOS
SM_
INTRUDER#
DG
PU_PWROK20,42,54,55
Pull high @ VGA side
PEG
_CLKREQ#20
Note for PCH_PWROK
PDG1.0 Figure43-4 note20: PCH_PWROK
does not glitch when RSMRST# is
de-asserted
#543016
PDG0.9 P.526
PROCPWRGD is used only for power sequence
debug and is not required to be connected to
anything on the platform.
WAKE#
(DSX wake event)
10 KΩ pull-up to VccDSW3_3.
The pull-up is required even
if PCIe* interface is not
used on the platform.
1 2
RC9
1 20K_0402_5%
1 2
0 1U_0402_6.3V6K
CC1
1 2
RC9
1 1
+3VS
RC1
RC1
RC1
RC1
RC1
2 2
_DSW
+3VALW
Follow
+3VALW
_DSW
_PRIM
+3VALW
3 3
_DSW
+3VALW
3 20K_0402_5%
1 2
1 1U_0402_6.3V6K
CC1
1 2
MOS1 0_0603_5%@
JC
at RAM DOOR
Place
1 2
4 1M_0402_5%
RC9
_PRIM
RPC1
10K_0804_8P4R_5%
CL
CL
CL
CL
CL
1 2
65 10K_0402_5%
1 2
05 10K_0402_5%
1 2
21 10K_0402_5%
1 2
23 10K_0402_5%
1 2
24 10K_0402_5%
+3VALW
543016_SKL_U_Y_PDG_0_9
1 2
RC1
03 10K_0402_5%
1 2
RC1
04 1K_0402_5%
1 2
@
06 10K_0402_5%
RC1
1 2
15 10K_0402_5%@
RC1
KREQ_PCIE#4
KREQ_PCIE#5
KREQ_PCIE#1
KREQ_PCIE#2
KREQ_PCIE#3
1
18
27
36
45
PCH_
EC_
SY
LA
LAN WAKE: LAN Wake Indicator from the GbE PHY.
+1.0V_VCCST
12
PBTN_OUT#_R
Note for VCCST_PWRGD
1. 1.0V tolerance
2. PDG1.0 Figure43-4 note17: when failure events,
VCCST_PWRGD and PCH_PWROK de-assert at the same time
RC1
13
1K_0402_5%
RC1
1 2
16 60.4_0402_1%
CC5
1
.1U_040 2_16V7K
12
CC5
0
.1U_040 2_16V7K
12
@EMC@
@EMC@
EC_
SY
S_RESET#
H_
CPUPWRGD
VCCST_PG
11 100K_0402_5%@
RC1
From
EC_VCCST_PG_R38,42
4 4
12
EC(open-drain)
Reserved for ESD 2014/9/17
A
B
DGPU
GLAN
7002LT1G_SOT23-3
12
07
R1
2.2K_0402_5%
@
B
C
_ULT
CLOCK SIGNALS
+3VS
5
P
B
Y
A
G
3
12
@
-U
SKL
OF 20
11
@
@
@
1 2
10 10K_0402_5%
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
SKL
OF 20
10
PL
T_RST_BUF#
4
GP
GP
GP
P_B11/EXT_PWR_GATE#
GP
GP
PBT
N_OUT#_R
12
PCH_
DPWROK
12
PWROK
PCH_
12
Deciphered Date
Deciphered Date
Deciphered Date
12
57
R1
100K_0402_5%
P_B12/SLP_S0#
GP
D4/SLP_S3#
D5/SLP_S4#
GP
GP
D10/SLP_S5#
SLP_SUS#
SL
D9/SLP_WLAN#
GP
D6/SLP_A#
D3/PWRBTN#
GP
D1/ACPRESENT
GP
D0/BATLOW#
GP
P_A11/PME#
IN
TRUDER#
P_B2/VRALERT#
UC1J
CL
K_PCIE_N020
CL
CL
K_PCIE_P020
CL
K_PCIE_N133
K_PCIE_P133
CL
KREQ_PCIE#133
CL
K_PCIE_N235
CL
CL
K_PCIE_P235
CL
KREQ_PCIE#235
+3VS
12
R1
12
15
10K_0402_5%
CL
T_RST#
PL
S_RESET#
SY
RSMRST#
EC_
H_
CPUPWRGD
EC_
VCCST_PG
S_PWROK
SY
PCH_
PCH_
SUSPW
SUSACK#
KE#
WA
N_WAKE#
LA
VGA@
G
2
Q2L2N
13
D
S
SY
EC_
SY
S_PWROK38,42
PCH_
SUSPW
S_RESET#6
RSMRST#6,38
PLT_RST#20,38,39
PWROK38,42
T92
T95 @
T89 @
RDNACK38
@
12
R1
2.2K_0402_5%
@
K_PCIE_N0
CL
K_PCIE_P0
CL
KREQ_PCIE#0
K_PCIE_N1
CL
K_PCIE_P1
CL
KREQ_PCIE#1
CL
CL
K_PCIE_N2
CL
K_PCIE_P2
CL
KREQ_PCIE#2
KREQ_PCIE#3
CL
KREQ_PCIE#4
CL
CL
KREQ_PCIE#5
KREQ_PCIE#0
AN10
B5
AY17
A68
B65
PWROK
DPWROK
Security Classification
Security Classification
Security Classification
TH
TH
TH
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B6
BA20
BB20
AR13
RDNACK
AP11
BB15
AM15
AW17
AT15
Issued Date
Issued Date
Issued Date
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
D42
KOUT_PCIE_N0
CL
C42
CL
KOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CL
KOUT_PCIE_N1
A42
CL
KOUT_PCIE_P1
AT7
P_B6/SRCCLKREQ1#
GP
D41
CL
KOUT_PCIE_N2
C41
CL
KOUT_PCIE_P2
AT8
P_B7/SRCCLKREQ2#
GP
D40
CL
KOUT_PCIE_N3
C40
CL
KOUT_PCIE_P3
AT10
P_B8/SRCCLKREQ3#
GP
B40
CL
KOUT_PCIE_N4
A40
CL
KOUT_PCIE_P4
AU8
P_B9/SRCCLKREQ4#
GP
E40
CL
KOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
P_B10/SRCCLKREQ5#
GP
SKL-U_BGA1356
@
PCH
PLTRST Buffer
PL
T_RST#
UC3
MC
RC1
UC1K
P_B13/PLTRST#
GP
SYS_
RS
MRST#
OCPWRGD
PR
CST_PWRGD
VC
SYS_
H_PWROK
PC
DS
W_PWRO K
P_A13/SUSWARN#/SUSPWRDNACK
GP
P_A15/SUSACK#
GP
WA
KE#
D2/LAN_WAKE#
GP
D11/LANPHYPC
GP
GP
D7/RSVD
SKL-U_BGA1356
@
PBT
N_OUT#6,38
RESET#
PWROK
C
EM POWER MANAGEMENT
SYST
EC_
RSMRST#
S_PWROK
SY
SY
S_PWROK
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
2014/
2
1
74VHC1G08DFT2G_SC70-5
25 0_0402_5%
RC1
09 0_0402_5%
14 0_0402_5%
RC1
22 0_0402_5%
RC1
RC1
CL
KOUT_ITPXDP_N
KOUT_ITPXDP_P
CL
GP
D8/SUSCLK
XT
AL24_OUT
XT
XC
LK_BIASREF
SR
RT
PL
T_RST_BUF# 33,35
Rev_0.53
P_LAN#
D
Rev_0.5
AL24_IN
RT
RT
TCRST#
CRST#
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
D
CX1
CX2
PM_
PM_
PM_
PM_
SL
SL
SL
PM_
PBT
AC_
PM_
SM_
EXT
SO
3
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
SLP_S0#
SLP_S3#
SLP_S4#
SLP_S5#
P_SUS#
P_LAN#
P_WLAN#
SLP_A#
N_OUT#_R
PRESENT
BATLOW#
INTRUDER#
_PWR_GATE#
C_VRALERT#
K_CPU_ITP#
CL
K_CPU_ITP
CL
SUSCL
K
SO
C_XTAL24_IN
C_XTAL24_OUT
SO
K_BIASREF
XCL
SO
C_RTCX1
SO
C_RTCX2
C_SRTCRST#
SO
C_RTCRST#
SO
T164 @
T165 @
T3807@
1 2
RC9
6 2.7K_0402_1%
1 2
@
RC1
36 60.4_0402_1%
SOC_RTCRST# 6
SO
SO
T84@
T85@
PM_
SLP_S0# 6,38
PM_
SLP_S3# 6,38,42
PM_SLP_S4# 6,38,42
SLP_S5# 6
PM_
T86@
T90@
T87@
T88@
PM_
SLP_A# 6
PRESENT 38
AC_
T91@
T93@
SO
SO
5
CC1
2P_0402_50V8D
8.
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
L-U(5/12)CLK,GPIO
L-U(5/12)CLK,GPIO
L-U(5/12)CLK,GPIO
SK
SK
SK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
Date: Sheet
Date: Sheet
Date: Sheet
E
Follow 2014MOW48
Skylake U PU 2.7k ohm to 1V
Cannonlake U PD 60.4 ohm
XCLK_BI
ASREF
T:50ohm S:12/15 L:1000 Via:2
0VALW_CLK5_F24NS
+1.
2014MOW48:
Skylake U use 24M 50 ohm ESR
Cannonlake U use 38.4M 30 ohm ESR
C_XTAL24_IN
C_XTAL24_OUT
12
C_RTCX2
C_RTCX1
32.768KHZ_9PF_CM7V-T1A9.0PF20PPM
Change PN to SJ10000L000
1
2
1 2
RC9
2 1M_0402_5%
1
YC
24MHZ_12PF_7V24000020
3
3
15P_0402_50V8J
CC12
GN
4
1 2
RC9
8 10M_0402_5%
YC2
1 2
6
CC1
2P_0402_50V8D
8.
E
1
1
GN
D
D
2
1
2
10 60Tuesday, June 16, 2015
10 60Tuesday, June 16, 2015
10 60Tuesday, June 16, 2015
of
of
of
15P_0402_50V8J
CC1
12
3
0
0
0
1.
1.
1.
A
_EN
35 @
34 @
31 @
30 @
28 @
29 @
T1
T1
11@
12@
TS
GC
GS
EC
GS
12
@
GP
UA
UA
UA
UA
6_FB_EN_R
PI0_MOSI
_LID_OUT#
PI1_MOSI
C_AC_DET
SO
U_EVENT_ R#
RT_2_CRXD_DTXD
RT_2_CTXD_DRXD
RT_2_CRTS_DCTS
RT_2_CCTS_DRTS
I2
C_0_SDA
I2C_0_SCL
C_1_SDA
I2
C_1_SCL
I2
C_2_SDA
I2
I2
C_2_SCL
C_3_SDA
I2
C_3_SCL
I2
I2
C_4_SDA
C_4_SCL
I2
TS
_EN29,38
1 1
_LID_OUT#38
EC
RC1
DG
PU_AC_DETECT20,38
UART_2_CRXD_DTXD35
UA
eserved for Touch PNL>
<R
<T
ouch PAD/PNL>
no use
no use
no use
2 2
Functional
R / GPP_B14 (Internal Pull Down):
SPK
(Sampled:Rising edge of PCH_PWROK)
TOP Sw ap Overr ide
0 = Disable TOP Swap mode. ---> AAX05 Use
*
1 = Enable TOP Swap Mode.
GSPI0_MOSI /GPP_B18 (Internal Pull Down):
(Rising edge of PCH_PWROK)
No Reboot
0 = Disable No Reboot mode. --> AAX05 Use
*
1 = Enable No Reboot Mode. (PCH will disable the TCO
Timer system reboot feature). This function is useful
when running ITP/XDP.
3 3
GSPI1_MOSI / GPP_B22 (Internal Pull Dow n):
(Rising edge of PCH_PWROK)
Boot BIOS Strap Bit
0 = SPI Mode --> AAX05 Use
*
1 = LPC Mode
SML0ALERT# / GPP_C5 (Internal Pull Down):
(Sampled: Rising edge of RSMRST# )
eSPI or LPC
0 = LPC is selected for EC --> For KB9022/9032 Use
*
1 = eSPI is selected for EC --> For KB9032 Only.
Strap Definitions
89
0_0402_5%
RT_2_CTXD_DRXD35
I2
C_0_SDA29
C_0_SCL29
I2
C_1_SDA39
I2
C_1_SCL39
I2
T1
T1
T1
T1
T1
T1
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
W4
AB3
AD1
AD2
AD3
AD4
U7
U6
U8
U9
AH9
AH10
AH11
AH12
AF11
AF12
U_EVENT_ R#
GP
GC
6_FB_EN_R
A_ID
VG
RA
NK_ID
VG
RA
B
UC1F
LP
P_B15/GSPI0_CS#
GP
GPP_B16/GSPI0_CLK
P_B17/GSPI0_MISO
GP
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS#
GP
P_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GP
P_B22/GSPI1_MOSI
GP
P_C8/UART0_RXD
P_C9/UART0_TXD
GP
GP
P_C10/UART0_RTS#
P_C11/UART0_CTS#
GP
P_C20/UART2_RXD
GP
P_C21/UART2_TXD
GP
P_C22/UART2_RTS#
GP
P_C23/UART2_CTS#
GP
GP
P_C16/I2C0_SDA
P_C17/I2C0_SCL
GP
GP
P_C18/I2C1_SDA
GP
P_C19/I2C1_SCL
GP
P_F4/I2C2_SDA
GP
P_F5/I2C2_SCL
GP
P_F6/I2C3_SDA
P_F7/I2C3_SCL
GP
P_F8/I2C4_SDA
GP
GPP_F9/I2C4_SCL
SKL-U_BGA1356
@
1 2
RC2
04 0_0402_5%
1 2
95 0_0402_5%
RC1
15 10K_0402_5%@
RC2
RC2
16 10K_0402_5%
17 10K_0402_5%SR@
RC2
18 10K_0402_5%DR@
RC2
A_ID
GL
GM
NK_ID
DR
SR
L-U
SS ISH
GC6@
GC6@
1 2
1 2
1 2
1 2
GPP_D9
0
1
SK
6 OF 20
U_EVENT#
GP
GC
6_FB_EN
+3
VALW_1.8VALW_PGPPD
GP
GP
GP
P_F10/I2C5_SDA/ISH_I2C2_SDA
P_F11/I2C5_SCL/ISH_I2C2_SCL
GP
P_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GP
P_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GP
GP
P_D16/ISH_UART0_CTS#/SML0BALERT#
GP
GP
PR
PR
P_D15/ISH_UART0_RTS#
GP
GP
P_C12/UART1_RXD/ISH_UART1_RXD
P_C13/UART1_TXD/ISH_UART1_TXD
GP
P_C14/UART1_RTS#/ISH_UART1_RTS#
P_C15/UART1_CTS#/ISH_UART1_CTS#
GP
P_A12/BM_BUSY#/ISH_GP6
GP
U_EVENT# 20
GC
6_FB_EN 20
OJECT_ID0
OJECT_ID1
Project ID
*
A4WAS
Reserved
GPP_D10
0
Reserved
served
Re
1
C
Rev_0.
GPP_D9
P_D10
GP
GPP_D11
GP
P_D12
P_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
P_D7/ISH_I2C1_SDA
GP
P_D8/ISH_I2C1_SCL
GP
P_A18/ISH_GP0
GP
P_A19/ISH_GP1
GP
P_A20/ISH_GP2
P_A21/ISH_GP3
GP
GP
P_A22/ISH_GP4
P_A23/ISH_GP5
GP
TO DGPU
07 10K_0402_5%@
RC2
1 2
RC2
10 10K_0402_5%
11 10K_0402_5%@
RC2
1 2
13 10K_0402_5%
RC2
# 543016 SKY PDG 0.9 P.401
53
VG
A_ID
P2
RA
NK_ID
P3
OJECT_ID0
PR
P4
OJECT_ID1
PR
P1
IS
H_I2C0_SD A
M4
IS
H_I2C0_SC L
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
12
12
H_I2C1_SD A
IS
H_I2C1_SC L
IS
I2
C_5_SDA
C_5_SCL
I2
SO
C_GPIOD13
SO
C_GPIOD14
SO
C_GPIOD15
C_GPIOD16
SO
DG
PU_PWR_EN
DGPU_HOLD_RST#
GYRO_INT1#
INT#
M_
G_
INT#
RO_INT2#
GY
S_INT#
AL
+3
VALW_1.8VALW_PGPPD
ISH sensor HUB
(Reserve for Verify)
05 @
T1
T106 @
07 @
T1
08 @
T1
13 @
T1
10 @
T1
Project_ID0Project_ID1
GPP_D11GPP_D12
00
0
1
1
0
11
no use
no use
DG
PU_PWR_EN 42
PU_HOLD_RST# 20
DG
G_
INT# 41
I2C/ISH Port(From PDG 0.9)
D
DGPU_PWR_EN
DGPU_HOLD_RST#
S_INT#
AL
RO_INT1#
GY
INT#
M_
RO_INT2#
GY
G_
INT#
C_0_SDA
I2
I2
C_0_SCL
C_1_SDA
I2
C_1_SCL
I2
H_I2C1_SC L
IS
IS
H_I2C1_SD A
H_I2C0_SC L
IS
IS
H_I2C0_SD A
UA
RT_2_CRXD_DTXD
RT_2_CTXD_DRXD
UA
UA
RT_2_CRTS_DCTS
RT_2_CCTS_DRTS
UA
1 2
RC2
14 10K_0402_5%VGA@
1 2
RC2
19 10K_0402_5%VGA@
1 2
RC2
05 10K_0402_5%@
RP
1 8
2 7
3 6
4 5
@
10K_0804_8P4R_5%
17
@
RC1
100K_0402_5%
1 2
RC1
26 1K_0402_5%
1 2
RC1
27 1K_0402_5%
1 2
RC1
28 2.2K_0402_5%
1 2
RC129 2.2K_0402_5%
RP
1 8
2 7
3 6
4 5
@
1K_0804_8P4R_5%
1 2
2 49.9K_0402_1%
RC6
1 2
RC6
3 49.9K_0402_1%
1 2
@
4 49.9K_0402_1%
RC6
1 2
@
RC6
5 49.9K_0402_1%
C12
C19
.8VS_3VS_PGPPA
+1
12
VALW_1.8VALW_PGPPD
+3
E
VS
+3
RC177
0_0402_5% ESPI@
0_0402_5% @
+3
VALW_PGPPC
+3VS
+3
VS
RC1
+3
VS
.8VS
+1
78
12
12
SMBALERT# / GPP_C2 (Internal Pull Down):
(Sampled: Rising edge of RSMRST# )
TLS Confidentiality
0 = Disable Intel ME Crypto Transport Layer Security
4 4
*
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto (TLS) (with confidentiality).
Must be pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
A
HDA_SDO/I2S_TXD0 (Internal Pull Down):
(Sampled: Rising edge of PCH_PWROK )
Flash Descriptor Security Override
0 = Enable security measures defined in the Flash
Descript or.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted hi gh using external
pull-up in manufacturing/debug environments ONLY.
B
DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down):
DDPC_CTRLDATA/ GPP_E21 (Internal Pull Down):
DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down):
(Sampled:Rising edge of PCH_PWROK)
Display Port B/ C/D Detected
0 =Port D is not detected.
1 =Port D is detected.
Security Classifica tio n
Security Classifica tio n
Security Classifica tio n
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
C
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
2014/
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Ti
Ti
Ti
tle
tle
tle
SK
SK
SK
L-U(6/12)GPIO
L-U(6/12)GPIO
L-U(6/12)GPIO
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
E
11 60Tuesday, June 16, 2015
11 60Tuesday, June 16, 2015
11 60Tuesday, June 16, 2015
0
0
0
1.
1.
1.
A
PCI
E_CRX_GTX_N120
PCI
E_CRX_GTX_P120
PCI
E_CTX_C_GRX_N120
PCIE_CTX_C_GRX_P120
E_CRX_GTX_N220
1 1
DGPU
GLAN+CR
NGFF
WLAN+BT(Key E)
HDD
2 2
ODD
When PCIE8/SATA1A is used
as SATA Port 1 (ODD), then
PCIE11/SATA1B (M.2 SSD)
cannot be used as SATA
Port 1.
3 3
4 4
A
PCI
E_CRX_GTX_P220
PCI
PCI
E_CTX_C_GRX_N220
PCI
E_CTX_C_GRX_P220
PCI
E_CRX_GTX_N320
E_CRX_GTX_P320
PCI
E_CTX_C_GRX_N320
PCI
E_CTX_C_GRX_P320
PCI
PCI
E_CRX_GTX_N420
PCI
E_CRX_GTX_P420
PCIE_CTX_C_GRX_N420
E_CTX_C_GRX_P420
PCI
IE_CRX_DTX_N533
PC
PC
IE_CRX_DTX_P533
PCI
E_CTX_C_DRX_N533
PCI
E_CTX_C_DRX_P533
IE_CRX_DTX_N635
PC
IE_CRX_DTX_P635
PC
E_CTX_C_DRX_N635
PCI
PCI
E_CTX_C_DRX_P635
SAT
A_CRX_DTX_N036
SATA_CRX_DTX_P036
A_CTX_DRX_N036
SAT
A_CTX_DRX_P036
SAT
SAT
A_CRX_DTX_N136
SAT
A_CRX_DTX_P136
SAT
A_CTX_DRX_N136
A_CTX_DRX_P136
SAT
+3VALW
CC1
CC2
CC1
CC1
CC2
CC2
CC2
CC2
_PRIM
#543016
BO=4 W=12 S=12 R=100ohm
B
PCI
PCIE_CRX_GTX_P1
RQA#
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
7 0.22U_0402_16V7KVGA@
1 0.22U_0402_16V7KVGA@
8 0.22U_0402_16V7KVGA@
9 0.22U_0402_16V7KVGA@
0 0.22U_0402_16V7KVGA@
2 0.22U_0402_16V7KVGA@
3 0.22U_0402_16V7KVGA@
4 0.22U_0402_16V7KVGA@
CC2
CC2
C3
803 .1U_0402_16V7K
C3
804 .1U_0402_16V7K
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
5 .1U_0402_16V7K
6 .1U_0402_16V7K
1 2
1 2
12
12
12
3510K_0402_5% @
PI
RC1
P.239 PCIE_RCOMPN/PCIE_RCOMPP
RC1
1 2
20 100_0402_1%
B
XDP_
PRDY#6
XDP_PREQ#6
Ac
er HSIO def i ne
PCI
PCI
XDP_
XDP_
PI
E_CRX_GTX_N1
E_CTX_GRX_N1
E_CTX_GRX_P1
E_CRX_GTX_N2
E_CRX_GTX_P2
E_CTX_GRX_N2
E_CTX_GRX_P2
E_CRX_GTX_N3
E_CRX_GTX_P3
E_CTX_GRX_N3
E_CTX_GRX_P3
E_CRX_GTX_N4
E_CRX_GTX_P4
E_CTX_GRX_N4
E_CTX_GRX_P4
E_CRX_DTX_N5
E_CRX_DTX_P5
E_CTX_DRX_N5
E_CTX_DRX_P5
E_CRX_DTX_N6
E_CRX_DTX_P6
E_CTX_DRX_N6
E_CTX_DRX_P6
E_RCOMPN
E_RCOMPP
PRDY#
PREQ#
RQA#
C
SKL
UC1H
PC
IE/USB3 /SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
IE1_RXP/USB3_5_RXP
PC
B17
PC
IE1_TXN/USB3_5_TXN
A17
PC
IE1_TXP/USB3_5_TXP
G11
IE2_RXN/USB3_6_RXN
PC
F11
PC
IE2_RXP/USB3_6_RXP
D16
PC
IE2_TXN/USB3_6_TXN
C16
IE2_TXP/USB3_6_TXP
PC
H16
PC
IE3_RXN
G16
PC
IE3_RXP
D17
IE3_TXN
PC
C17
IE3_TXP
PC
G15
PC
IE4_RXN
F15
IE4_RXP
PC
B19
IE4_TXN
PC
A19
PC
IE4_TXP
F16
IE5_RXN
PC
E16
PC
IE5_RXP
C19
PC
IE5_TXN
D19
IE5_TXP
PC
G18
PC
IE6_RXN
F18
PC
IE6_RXP
D20
IE6_TXN
PC
C20
IE6_TXP
PC
F20
PC
IE7_RXN/SATA0_RXN
E20
IE7_RXP/SATA0_RXP
PC
B21
IE7_TXN/SATA0_TXN
PC
A21
PC
IE7_TXP/SATA0_TXP
G21
IE8_RXN/SATA1A_RXN
PC
F21
IE8_RXP/SATA1A_RXP
PC
D21
PC
IE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PC
IE9_RXN
E23
PC
IE9_RXP
B23
IE9_TXN
PC
A23
IE9_TXP
PC
F25
PC
IE10_RXN
E25
IE10_RXP
PC
D23
IE10_TXN
PC
C23
PC
IE10_TXP
F5
IE_RCOMPN
PC
E5
IE_RCOMPP
PC
D56
PR
OC_PRDY#
D61
OC_PREQ#
PR
BB11
GP
P_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
IE11_RXP/SATA1B_RXP
PC
D24
IE11_TXN/SATA1B_TXN
PC
C24
PC
IE11_TXP/SATA1B_TXP
E30
IE12_RXN/SATA2_RXN
PC
F30
IE12_RXP/SATA2_RXP
PC
A25
PC
IE12_TXN/SATA2_TXN
B25
PC
IE12_TXP/SATA2_TXP
SKL-U_BGA1356
@
GPIO
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
DEVSLP0
DEVSLP1
DEVSLP2
SATA_GP0
SATA_GP1
SATA_GP2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
TH
TH
TH
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
2014/
-U
USB2
OF 20
8
DEVICE CONTROL
USB2 Port 1
Port 2
USB2
NA
NA
NA
NA
NA
NA
NA
NA
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
SSIC / USB3
US
B3_2_RXN/SSIC_1_RXN
B3_2_RXP/SSIC_1_RXP
US
B3_2_TXN/SSIC_1_ TXN
US
US
B3_2_TXP/SSIC_1_ TXP
B3_3_RXN/SSIC_2_RXN
US
B3_3_RXP/SSIC_2_RXP
US
US
B3_3_TXN/SSIC_2_ TXN
US
B3_3_TXP/SSIC_2_ TXP
B2_VBUSSENSE
US
GP
P_E9/USB2_OC0#
GP
P_E10/USB2_OC1#
P_E11/USB2_OC2#
GP
GP
P_E12/USB2_OC3#
GPP_E4/DEVSLP0
GP
GP
P_E0/SATAXPCIE0/SATAGP0
GP
P_E1/SATAXPCIE1/SATAGP1
GP
GP
P_E2/SATAXPCIE2/SATAGP2
P_E8/SATALED#
GP
Deciphered Date
Deciphered Date
Deciphered Date
P_E5/DEVSLP1
P_E6/DEVSLP2
Rev_0.5
B3_1_RXN
US
US
B3_1_RXP
USB3_1_TXN
B3_1_TXP
US
B3_4_RXN
US
US
B3_4_RXP
US
B3_4_TXN
B3_4_TXP
US
US
B2N_1
USB2P_1
US
B2N_2
US
B2P_2
B2N_3
US
US
B2P_3
B2N_4
US
B2P_4
US
US
B2N_5
B2P_5
US
US
B2N_6
US
B2P_6
B2N_7
US
US
B2P_7
B2N_8
US
US
B2P_8
B2N_9
US
B2P_9
US
US
B2N_10
B2P_10
US
US
B2_COMP
US
B2_ID
D
3
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
USB2
AB9
USB2
AB10
USB2
AD6
USB2
AD7
USB2
AH3
USB2
AJ3
AD9
AD10
USB2
AJ1
USB2
AJ2
USB2
AF6
USB2
AF7
USB2
AH1
USB2
AH2
AF8
AF9
AG1
AG2
AG3,AG4
AH7
2015MOW10, USB2_ID Connected to GND Directly
AH8
USB2
AB6
USB2
AG3
USB2
AG4
USB_
A9
USB_
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
DEVSLP[2:0] Implementation
DEVSLP is a host-controlled hardware signal which enables a SATA host and device to
enter an ultra-low interface power state, including the possibility to completely power
down host and device PHYs.
The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U.
When high, DEVSLP requests the SATA device to enter into the DEVSLP power state.
î¡„
When low, DEVSLP requests the SATA device to exit from the DEVSLP power state
î¡„
and transition to active state.
SATA General Purpose (SATAGP[2:0]) Signals
The processor provides three SATA general purpose input signals,SATAGP[2:0] for SKL U.
î¡„
These signals can be configured as interlock switch inputs corresponding to a given SATA port.
When used as an interlock switch status indication, this signal should be driven to 0
î¡„
to indicate that the switch is closed and to a 1 to indicate that the switch is open.
If mechanical presence switches will not be used on the platform, SATAGP[2:0]
î¡„
signals can be configured as GPP_E[2:0] GPIOs signals.
D
E
_CRX_DTX_N1 37
USB3
USB3
0_N1
0_P1
0_N2
0_P2
0_N3
0_P3
0_N5
0_P5
0_N6
0_P6
0_N7
0_P7
_CRX_DTX_P1 37
USB3
_CTX_DRX_N1 37
USB3
_CTX_DRX_P1 37
USB3_CRX_DTX_N2 37
_CRX_DTX_P2 37
USB3
_CTX_DRX_N2 37
USB3
_CTX_DRX_P2 37
USB3
0_N1 37
USB2
0_P1 37
USB2
USB2
0_N2 37
USB2
0_P2 37
USB2
0_N3 37
0_P3 37
USB2
USB2
0_N5 35
USB2
0_P5 35
0_N6 29
USB2
0_P6 29
USB2
USB2
0_N7 29
USB2
0_P7 29
US
US
USB3 MB
USB3 MB
US
B2/B
BT
TS
Camera
B3 MB
B3 MB
PD1K for DCI warm boot fail issue (follow PCH EDS1.2)
_COMP
_ID
_VBUSSENSE
OC0#
OC1#
1 2
RC1
19 113_0402_1%
1 2
RC1
30
1 2
RC1
31
USB_
USB_
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
SK
SK
SK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
Date: Sheet
Date: Sheet
Date: Sheet
0_0402_5%
0_0402_5%
OC0# 37
OC1# 37
USB_
OC0#
OC1#
USB_
L-U(7/12)PCIE,USB,SATA
L-U(7/12)PCIE,USB,SATA
L-U(7/12)PCIE,USB,SATA
RC1
RC2
1 2
32 10K_0402_5%
1 2
00 10K_0402_5%
12 60Thursday, July 16, 2015
12 60Thursday, July 16, 2015
12 60Thursday, July 16, 2015
E
+3VALW
of
of
of
_PRIM
0
0
0
1.
1.
1.
A
B
C
D
E
+1.0VALW_PRIM TO +1.0V_VCCSTU / +1.0VCCST
CC9
CC9
1 2
5
1 2
4
2
0V_VCCSTU
+1.
+1.
8VS
+1.
0VS_VCCSTG
+VCCI
ax : 2 .73 A
Im
1
CC9
6
.1U_040 2_16V7K
2
1
CC1
00
.1U_040 2_16V7K
2
O
+1.
35V_VDDQ_CPU
0V_VCCSTU
+1.
35V_VDDQ_CPU
+1.
+1.
RC2
RC1
RC1
RC1
35V_VDDQ
1 2
08 0_0402_5%@
1 2
40 0_0402_5%@
1 2
43 0_0402_5%@
1 2
41 0_0402_5%@
For
Power consumption
Measure ment
JP
1 2
@
JUMP_43X118
JP
1 2
@
JUMP_43X118
+1.
35V_VCCSFR_OC
+1.
+1.
0VS_VCCSTG
35V_VDDQ_CPU
+1.
22U_0603_6.3V6M
CC3
1
7
2
C1
C2
35V_VDDQC
+1.
0V_VCCST
+1.
0VS_VCCSTG
0V_VCCSFR
+1.
+1.
0V_VCCST
+1.
0V_VCCSFR
+1.
35V_VCCSFR_OC
+1.
22U_0603_6.3V6M
CC41
1
2
+1.
35V_VDDQ_CPU
35V_VDDQC
PSC
1 2
7 10U_0603_6.3V6M
CC4
PSC Side
1 2
8 1U_0402_6.3V6K
CC4
PSC
1 2
CC5
5 1U_0402_6.3V6K
BSC Side
1 2
CC4
9 1U_0402_6.3V6K
1 2
CC5
6 1U_0402_6.3V6K
22U_0603_6.3V6M
10U_0603_6.3V6M
CC54
1
1
2
2
CC3
8
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
A18
A22
AL23
K20
K21
Side
Side
@
UC1N
CP
DQ_AU23
VD
VD
DQ_AU28
VD
DQ_AU35
DQ_AU42
VD
DQ_BB23
VD
VD
DQ_BB32
VD
DQ_BB41
DQ_BB47
VD
DQ_BB51
VD
DQC
VD
VC
CST
CSTG_A22
VC
VC
CPLL_OC
CPLL_K20
VC
VC
CPLL_K21
SKL-U_BGA1356
@
BSC Side
10U_0603_6.3V6M
1
CC3
9
2
+VCCI
SKL
-U
OF 20
Rev_0.53
VC
VC
2.73A
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
6A
VC
VC
VC
VC
VCCSA
VC
VC
VC
CIO_SENSE
VC
VSSI
O_SENSE
SENSE
VSSSA_
CSA_SENSE
VC
SKL_PDG_1_0
CIO
CIO
CIO
CIO
CIO
CIO
CIO
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
U POWER 3 OF 4
6.35A
0.09A
0.04A
0.04A
0.26A
0.12A
14
543016_
+1.35V_VDDQC : 1x 1uF 0201 (Placeholder)
1x 10uF 0402
543016_SKL_PDG_1_0
+1.0V_VCCST : 1x 1uF 0402
543016_SKL_PDG_1_0
+1.0V_VCCSFR : 1x 1uF 0402
543016_SKL_PDG_1_0
+1.35V_VCCSFR_OC : 1x 1uF 0201
543016_SKL_PDG_1_0
+1.0VS_VCCSTG : 1x 1uF 0402 (Placeholder)
BSC
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC4
0
2
1
CC4
2
@
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC4
3
@
2
O
+VCC_SA
O_SENSE
VCCI
O_SENSE
VSSI
VSSSA_
SENSE
VCCSA_
SENSE
SidePSC Side
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC45
@
2
CC4
4
1
@
2
CC4
6
T124 @
T125 @
VSSSA_
VCCSA_
SENSE 50
SENSE 50
+1.
1U_0402_6.3V6K
CC9
1
8
2
+1.
2
AS
902
U4
1
N
VI
2
VI
N
3
ON
4
VBIAS
AOZ1336_DFN8_2X2
@
0VALW_PRIM
CC9
1
7
@
2
1.0V_VCCSTU
EN_
EN_
1.8VS
8VALW_VS
CC9
1
9
@
2
VO
UT
GN
D
UT
VO
VO
UT
CT
D
GN
D
GN
1U_0402_6.3V6K
UC5
1
N1
VI
2
N1
VI
3
ON
1
4
AS
VBI
5
ON
2
6
N2
VI
7
VI
N2
209VF_DFN14_2X3
1U_0402_6.3V6K
+1
EM5
.8VALW_PRIM TO +1.8VS
VCCSTG
+1.
0VS_VCCSTG_IO
6
5
0VS_VCCSTG_IO
+1.
7
8
1 2
6
5
9
PSC
C977
1000P_0402_50V7K
@
SideBSC Side
14
UT1
VO
13
UT1
VO
12
CT
1
11
1000P_0402_50V7K
D
GN
10
CT
2
9
1000P_0402_50V7K
UT2
VO
8
VO
UT2
15
AD
GP
and VCCIO SLEW RATE <=65us
1 2
88 0_0402_5%@
RC1
J1
@
112
JUMP_43X79
6
+5VALW
1 1
SON38,42,47
SY
42,45,47,49
2 2
0VALW_PRIM
+1.
Imax : 2.77 A
For
Measure ment
3 3
SUSP#38,
JUMP_43X79
@
Power consumption
CC1
07
.1U_040 2_16V7K
12
@
SUSP#
RC1
0_0402_5%
+VCCIO
JP
C4
112
+5VALW
1 2
86
CC1
RC1
RC1
+1.
+1.
2
@
12
05 .1U_0402_16V7K
1 2
42 20K_0402_5%
1 2
68 0_0402_5%@
12
04
CC1
1U_0402_6.3V6K@
8VALW_PRIM
+1
.0VALW_PRIM TO +1.0VS_VCCSTG
0VALW_PRIM_JP
1U_0402_6.3V6K
CC1
1
17
2
_R1
SUSP#
@
1
2
7
3
4
1U_0402_6.3V6K
CC1
1
06
2
+1.
0VALW_PRIM_JP
SUSP#
_R1
+5VALW
112
C8
JP
JUMP_43X39
@
UC6
N1
VI
N2
VI
VI
N thermal
VBI
ON
S22961DNYR_WSON8
TP
22U_0603_6.3V6M
22U_0603_6.3V6M
CC5
1
4 4
@
2
543016_SKL_PDG_1_0
+VCCIO : 2x10uF 0402 (Placeholder)
4x 1uF 0201 (Placeholder)
4x 1uF 0402
CC5
1
8
9
@
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC2
7
@
@
2
A
1
1
CC2
8
@
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC2
9
@
2
CC3
0
1U_0402_6.3V6K
1
1
CC3
1
@
@
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CC3
CC3
3
2
2
2
1U_0402_6.3V6K
CC3
5
1U_0402_6.3V6K
1
CC3
6
2
Security Classification
Security Classification
Security Classification
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
Issued Date
Issued Date
Issued Date
TH
TH
TH
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2014/
C
Co
Co
Co
543016_
+1.35V_VDDQ_CPU : 2x 10uF 0402 (Placeholder)
4x 1uF 0201 (Placeholder)
4x 10uF 0402
3x 22uF 0603
mpal Secret Data
mpal Secret Data
mpal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1U_0402_6.3V6K
1
CC3
4
2
B
SKL_PDG_1_0
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
Date: Sheet
Date: Sheet
Date: Sheet
L-U(8/12)Power
L-U(8/12)Power
L-U(8/12)Power
SK
SK
SK
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
E
13 60Tuesday, June 16, 2015
13 60Tuesday, June 16, 2015
13 60Tuesday, June 16, 2015
0
0
0
1.
1.
1.
of
of
of
A
+1.
1 1
+1.
0VALW_PRIM
1 2
75 0_0402_5%@
RC1
+1.
0VALW_PRIM
1 2
48 0_0603_5%@
RC1
+3VALW
1 2
RC1
73 0_0402_5%@
+3VALW
_PRIM
1 2
98 0_0402_5%@
RC1
2 2
3 3
RC1
+3VALW
1 2
54 0_0402_5%@
C7
JP
112
JUMP_43X39
@
+1.
0VALW_PRIM
0VALW_MPHYAON
1 2
CC87 near K17 (<3 mm)
+1.
0VALW_APLL
1 2
_DSW
+3VALW
+3VALW
_HDA
1 2
CC63 near AJ19 (<10 mm)
+3VALW
_SPI
+3VALW
_PRIM
2
O
HSI
ax : 3 .5 A
Im
C9
JP
2
112
JUMP_43X79
@
7
CC8
1U_0402_6.3V6K
23
CC1
22U_0603_6.3V6M@
3
CC6
1U_0402_6.3V6K@
0VALW_MPHYPLL
+1.
RC2
RC1
RC176 0_0603_5%@
RC1
+1.0V_MPHYPLL
1 2
09 0_0603_5%@
CC80 near N15 (<3mm)
CC81,CC82 near N15 (<10mm)
1 2
49 0_0603_5%@
1 2
1 2
56 0_0402_5%@
B
CC9
1
12
1U_0402_6.3V6K
@
AB19 (<10 mm)
Near
+1.0VALW_PRIM
12
CC7
6
1U_0402_6.3V6K@
near AF18 (<10 mm)
5
CC8
1U_0402_6.3V6K
0VALW_MPHYAON
+1.
0VALW_MPHYGT
+1.
0VALW_AMPHYPLL
+1.
+1.
0VALW_APLL
+1.
0VALW_PRIM
+3VALW
+3VALW
+1.
0VALW_SRAM
+3VALW
0VALW_PRIM
+1.
+1.
0VALW_APLLEBB
0VALW_MPHYGT
+1.
+1.
0VALW_AMPHYPLL
+1.
0VALW_SRAM
0VALW_APLLEBB
+1.
12
_DSW
_HDA
_SPI
+3VALW
_PRIM
VCCMPHYGT
1 2
CC8
2 22U_0603_6.3V6M
@
1 2
CC8
1 22U_0603_6.3V6M
@
1 2
0 1U_0402_6.3V6K
CC8
CC61 near K15 (<3 mm)
CC6
CC122 near AF20 (<10mm)
CC122 1U_0402_6.3V6K
CC68 near N18 (<3mm)
CC6
1 2
1 1U_0402_6.3V6K
@
1 2
@
1 2
8 1U_0402_6.3V6K
+1.
0VALW_PRIM
DCPDSW
_1P0
AB19
AB20
P18
AF18
AF19
V20
V21
AL1
K17
N15
N16
N17
P15
P16
K15
V15
AB17
Y18
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
T19
T20
AJ21
AK20
N18
L1
L15
UC1O
VCCPRIM_1P0
CPRIM_1P0
VC
VC
CPRIM_1P0
CPRIM_CORE
VC
CPRIM_CORE
VC
VC
CPRIM_CORE
VC
CPRIM_CORE
DSW_1P0
DCP
VC
CMPHYAON_1P0
CMPHYAON_1P0
VC
VC
CMPHYGT_1P0_N15
VC
CMPHYGT_1P0_N16
CMPHYGT_1P0_N17
VC
CMPHYGT_1P0_P15
VC
VC
CMPHYGT_1P0_P16
CAMPHYPLL_1P0
VC
VC
CAMPHYPLL_1P0
CAPLL_1P0
VC
VC
CPRIM_1P0_AB17
VC
CPRIM_1P0_Y18
CDSW_3P3_AD17
VC
VC
CDSW_3P3_AD18
VC
CDSW_3P3_AJ17
CHDA
VC
VC
CSPI
CSRAM_1P0
VC
VC
CSRAM_1P0
VCCSRAM_1P0
CSRAM_1P0
VC
VC
CPRIM_3P3_AJ21
CPRIM_1P0_AK20
VC
VC
CAPLLEBB
SKL-U_BGA1356
@
C
-U
89A
2.57A
HSIO
HSIO
HSIO
HSIO
2.1A
SKL
VC
VC
VC
VC
VC
VC
VC
CPRIM_3P3_V19
VC
VC
CPRIM_1P0_T1
VC
VC
CRTCPRIM_3P3
CRTC_AK19
VC
VC
CRTC_BB14
GP
P_B0/CORE_VID0
P_B1/CORE_VID1
GP
OF 20
15
U POWER 4 OF 4
CP
0.
Per 543016_SKL_U_Y_PDG_0_9
VCCRTC does not exceed 3.2 V From PDG
Power Rail Vol tage
RTC
+CHG
BAT54C(VF)
+3VL_RTC
3.383V(MAX)
240 mV
3.143V
Result : Pass
Rev_0.5
CPGPPA
CPGPPB
CPGPPC
CPGPPD
CPGPPE
CPGPPF
CPGPPG
CATS_1P8
RTC
DCP
VC
CCLK1
CCLK2
VC
VC
CCLK3
CCLK4
VC
VC
CCLK5
CCLK6
VC
3
+R
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
TCBATT
W=
RT
20mils
cap
+3VALW
+3VALW
+3VALW_PGPPC
+3VALW
+3VALW
8VALW_PRIM
+1.
+3VALW
+3VALW
0VALW_DTS
+1.
8VALW_PRIM
+1.
+3VALW
+RT
CVCC
1 2
CC7
1 .1U_0402_16V7K
+1.
0VALW_CLK6_24TBT
+1.
0VALW_VCCCLK2
0VALW_APLL
+1.
0VALW_CLK4_F100OC
+1.
+1.
0VALW_CLK5_F24NS
+1.
PRI
MCORE_VID0
PRI
MCORE_VID1
0VALW_CLK6_24TBT
C Battery
HGRTC
+C
DC1
2
10mil
BAS4
W=
3
0-04_SOT23-3
1
Place close AK19.
_1.8VALW_PGPPA
_PGPPB
_1.8VALW_PGPPD
_PGPPE
No
_PGPPG
_PRIM
_RTC
T136 @
T138 @
W=20mils
+R
TCVCC
1
C1
.1U_040 2_16V7K
2
D
+3VALW
use
51
_1.8VALW_PGPPA
SPI Touch
8VALW_PRIM
+1.
EC
LPC/ESPI
12
RC1
12
RC1970_0402_5% @
CC1
02
1U_0402_6.3V6K @
CC102 near AG15 (<3 mm)
CC7
3
1U_0402_6.3V6K @
CC73 near Y16 (<10 mm)
CC74 near T16 (<10 mm)
CC67 near V19 (<3 mm)
+1.
0VALW_DTS
CC8
1U_0402_6.3V6K @
CC86 near A10 (<3 mm)
CC7
1U_0402_6.3V6K @
22U_0603_6.3V6M @
22U_0603_6.3V6M @
+3VALW
CC1
03
1U_0402_6.3V6K
CC7
4
1U_0402_6.3V6K @
CC8
3
1U_0402_6.3V6K @
CC67
1U_0402_6.3V6K @
2
CC7
1U_0402_6.3V6K
CC72 near AA1 (<10 mm)
8
CC7
.1U_040 2_16V7K
7
CC7
1U_0402_6.3V6K
CC77,CC78 near AK17 (<3 mm)
+1.
6
5
CC1
24
25
CC1
+3VALW
_PRIM
960_0402_5% ESPI@
_PGPPB
+3VALW
12
_PGPPC
+3VALW
12
_1.8VALW_PGPPD
12
_PGPPE
+3VALW
12
+3VALW
_PGPPG
12
12
12
RC1
12
+3VALW
_RTC
12
12
0VALW_CLK6_24TBT
12
+1.
0VALW_VCCCLK2
12
12
0VALW_CLK4_F100OC
+1.
12
+1.
0VALW_CLK5_F24NS
+3VALW
+1.
0VALW_PRIM
620_0402_5% @
E
1 2
_PRIM
+1.
12
12
8VALW_PRIM
+1.
12
12
12
8VALW_PRIM
12
+1.
12
+1.
12
+1.
12
+1.0VALW_PRIM
12
+3VALW
RC1
610_0402_5% @
+3VALW_PRIM
RC1
630_0402_5% @
+3VALW
_PRIM
RC2
060_0402_5% @
RC1
720_0402_5% @
+3VALW
RC1
670_0402_5% @
_PRIM
+3VALW
RC1
870_0402_5% @
+3VALW
710_0402_5% @
RC1
0VALW_PRIM
690_0402_5% @
RC1
0VALW_PRIM
640_0603_5% @
RC1
0VALW_PRIM
900_0603_5% @
RC1
RC1
520_0603_5% @
_PRIM
_PRIM
_PRIM
low 543016_SKL_U_Y_PDG_0_9
Fol
+1.
0VALW_PRIM
4 4
1
@
2
+3VALW
22U_0603_6.3V6M
CC1
1
11
@
2
22U_0603_6.3V6M
22U_0603_6.3V6M
CC1
1
12
@
2
_PRIM
A
CC1
13
+1.
8VALW_PRIM
22U_0603_6.3V6M
22U_0603_6.3V6M
CC1
1
14
@
@
2
22U_0603_6.3V6M
CC1
1
2
CC1
1
16
15
@
2
Security Classification
Security Classification
Security Classification
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
Issued Date
Issued Date
Issued Date
TH
TH
TH
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2014/
C
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
Date: Sheet
Date: Sheet
D
Date: Sheet
L-U(9/12)Power
L-U(9/12)Power
L-U(9/12)Power
SK
SK
SK
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
E
0
0
0
1.
1.
1.
14 60Tuesday, June 16, 2015
14 60Tuesday, June 16, 2015
14 60Tuesday, June 16, 2015
of
of
of
A
VCC
27A (U 15W Dual Core GT2) VCCGT / VCCGTX(2+3e only) 40A(need confirm)
#544924 Skylake EDS P.125
1 1
#544924 Skylake EDS P.125
VCCOPC 1V 2.8 A
VCC_OPC _1P8 1.8V 50mA
VCCEOPIO 0V,0.8V,1V 2.9 A
2 2
3 3
For CPU2+3e SKU
SVID
ALERT
T132 @
T133 @
T137 @
T139 @
VCCO
VSSO
VCCEO
VSSEO
PC_SENSE
PC_SENSE
PIO_SENSE
PIO_SENSE
+1.
UC1L
A30
C_A30
VC
A34
C_A34
VC
A39
VC
C_A39
A44
VC
C_A44
AK33
C_AK33
VC
AK35
C_AK35
VC
AK37
VC
C_AK37
AK38
VC
C_AK38
AK40
C_AK40
VC
AL33
C_AL33
VC
AL37
VC
C_AL37
AL40
VC
C_AL40
AM32
C_AM32
VC
AM33
C_AM33
VC
AM35
VC
C_AM35
AM37
VCC_AM37
AM38
C_AM38
VC
G30
VC
C_G30
K32
VD_K32
RS
AK32
RS
VD_AK32
AB62
COPC_AB62
VC
P62
COPC_P62
VC
V62
VC
COPC_V62
H63
C_OPC_1P8_H63
VC
G61
VC
C_OPC_1P8_G61
AC63
COPC_SENSE
VC
AE63
AE62
AG62
0V_VCCST
12
PC_SENSE
VSSO
VCCEOPIO
CEOPIO
VC
AL63
VC
CEOPIO_SENSE
AJ62
PIO_SENSE
VSSEO
SKL-U_BGA1356
@
the PU
Place
resistors close to CPU
RC1
79
56_0402_5%
U POWER 1 OF 4
CP
B
-U
SKL
VC
12
OF 20
Rev_0.5
C_G32
VC
C_G33
VC
VC
C_G35
VC
C_G37
C_G38
VC
C_G40
VC
VC
C_G42
VC
VC
VC
VC
VC
C_K33
C_K35
VC
C_K37
VC
VC
C_K38
VCC_K40
C_K42
VC
VC
C_K43
C_SENSE
VC
SENSE
VSS_
VI
DALERT#
VI
DSOUT
VI
CSTG_G20
C_J30
C_J33
C_J37
C_J40
DSCK
3
#5
44924 Skylake EDS P.120
VCC U(15W)-du al co re GT2 27A(Typ )-33A(MAX )
0.55-1.15 V
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
C_SVID_ALERT#
SO
SO
C_SVID_CLK
SO
C_SVID_DAT
+1.0VS(SUSP# )
Trace Length < 25 mils
+1.
VCCSENSE
VSSSENSE
C_SVID_CLK 50
SO
0VS_VCCSTG
C
+VCC_GT +VCC_GT+VCC_CORE +VCC_CORE
#544924 Skylake EDS P.121
VCCGT U(15W)-d ual co re GT2 40A(MA X)
0.55-1.15 V
50
50
VCCG
VCCG
T_SENSE50
VSSG
T_SENSE50
Length < 25 mils
Trace
VSSG
T_SENSE
T_SENSE
A48
A53
A58
A62
A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
K48
K50
K52
K53
K55
K56
K58
K60
M62
N63
N64
N66
N67
N69
D
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
UC1M
CP
U POWER 2 OF 4
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VCCGT
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VCCGT
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
VC
CGT
VC
CGT
VCCGT
CGT
VC
VC
CGT_SENSE
T_SENSE
VSSG
SKL-U_BGA1356
@
SKL
13
-U
OF 20
VC
VSSG
Rev_0.53
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VCCGT
CGT
VC
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
CGT
VC
VC
CGTX_AK42
CGTX_AK43
VC
CGTX_AK45
VC
VC
CGTX_AK46
VC
CGTX_AK48
CGTX_AK50
VC
CGTX_AK52
VC
VC
CGTX_AK53
VCCGTX_AK55
CGTX_AK56
VC
VC
CGTX_AK58
VC
CGTX_AK60
CGTX_AK70
VC
CGTX_AL43
VC
VC
CGTX_AL46
VC
CGTX_AL50
CGTX_AL53
VC
CGTX_AL56
VC
VC
CGTX_AL60
VC
CGTX_AM48
CGTX_AM50
VC
CGTX_AM52
VC
VC
CGTX_AM53
VC
CGTX_AM56
CGTX_AM58
VC
VC
CGTX_AU58
VC
CGTX_AU63
VCCGTX_BB57
CGTX_BB66
VC
CGTX_SENSE
TX_SENSE
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
VCCG
VSSG
TX_SENSE
TX_SENSE
E
For CPU2+3e SKU
T155 @
T219 @
543016
SO
C_SVID_ALERT#
1 2
RC180 220_0402_5%
SVID DATA
C_SVID_DAT
SO
4 4
A
0V_VCCST
+1.
12
C_SVID_ALERT#_R 50
SO
Place the PU
resistors close to CPU
RC1
81
100_0402_1%
SOC_SVID_DAT 50
(To
VR)
(To VR)
B
PDG0.9 P.189
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
TH
TH
TH
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Need
C
check
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
2014/
Co
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
Date: Sheet
Date: Sheet
D
Date: Sheet
L-U(10/12)Power,SVID
L-U(10/12)Power,SVID
L-U(10/12)Power,SVID
SK
SK
SK
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
E
0
0
0
1.
1.
1.
15 60Tuesday, June 16, 2015
15 60Tuesday, June 16, 2015
15 60Tuesday, June 16, 2015
of
of
of
A
B
C
D
E
1 1
2 2
3 3
AA6
AA6
AB1
AB16
AB1
AB2
AD
AD
AD
AD
AD
AD
AE6
AE6
AE6
AE6
AE6
AE6
AF
AF15
AF
AF
AG
AG
AG
AG
AG
AG
AG
AH
AH
AH
AH
AJ
AJ
AJ20
AK1
AK1
AK1
AK2
AK2
AK2
AK6
AK6
AK6
AL
AL
AL
AL
AL
AL48
AL
AL
AL
AL
AA2
AA4
AB8
AD
AF
AF
AF
AH
AK8
AL
AL
A5
7
A6
0
A7
5
8
5
8
1
13
16
19
20
21
62
8
4
5
6
7
8
9
1
10
17
2
4
63
16
17
18
19
20
21
71
13
6
63
64
67
15
18
4
AJ
1
6
8
1
2
7
3
8
9
2
28
32
35
38
4
45
52
55
58
64
UC1P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-U_BGA1356
@
GN
D 1 OF 3
-U
SKL
16
OF 20
3 Rev_0.53
Rev_0.5
AL
65
VSS
66
AL
VSS
13
AM
VSS
21
AM
VSS
AM
25
VSS
27
AM
VSS
43
AM
VSS
45
AM
VSS
AM46
VSS
55
AM
VSS
60
AM
VSS
AM
61
VSS
68
AM
VSS
71
AM
VSS
8
AM
VSS
AN
20
VSS
23
AN
VSS
28
AN
VSS
30
AN
VSS
AN
32
VSS
33
AN
VSS
35
AN
VSS
37
AN
VSS
AN
38
VSS
40
AN
VSS
42
AN
VSS
58
AN
VSS
AN63
VSS
0
AP1
VSS
8
AP1
VSS
AP2
0
VSS
3
AP2
VSS
8
AP2
VSS
2
AP3
VSS
AP3
5
VSS
8
AP3
VSS
2
AP4
VSS
8
AP5
VSS
AP6
3
VSS
8
AP6
VSS
0
AP7
VSS
AR
11
VSS
AR
15
VSS
16
AR
VSS
20
AR
VSS
23
AR
VSS
AR28
VSS
35
AR
VSS
42
AR
VSS
AR
43
VSS
45
AR
VSS
46
AR
VSS
48
AR
VSS
AR
5
VSS
50
AR
VSS
52
AR
VSS
53
AR
VSS
AR
55
VSS
58
AR
VSS
63
AR
VSS
8
AR
VSS
AT
2
VSS
20
AT
VSS
23
AT
VSS
28
AT
VSS
AT35
VSS
4
AT
VSS
42
AT
VSS
AT
56
VSS
58
AT
VSS
AT
AT
AT
AU
AU
AU
AU
AU
AV1
AV6
AV6
AV7
AV7
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW41
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW
AW
AY6
B1
B1
B1
B22
B3
B3
B3
B4
B4
B5
B5
B6
B6
B7
BA1
BA1
BA1
BA1
BA2
BA2
BA2
BA3
BA36
BA4
63
68
71
10
15
20
32
38
8
9
0
1
10
12
14
16
18
21
23
26
28
30
32
34
36
38
43
45
47
49
51
53
55
57
6
60
62
64
66
8
6
0
4
8
0
4
9
4
8
3
8
2
6
1
0
4
8
3
8
2
8
F6
5
UC1Q
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-U_BGA1356
@
GN
D 2 OF 3
-U
SKL
BA4
9
VSS
3
BA5
VSS
7
BA5
VSS
BA6
VSS
BA6
2
VSS
6
BA6
VSS
1
BA7
VSS
8
BB1
VSS
BB26
VSS
0
BB3
VSS
4
BB3
VSS
BB3
8
VSS
3
BB4
VSS
5
BB5
VSS
BB6
VSS
BB6
0
VSS
4
BB6
VSS
7
BB6
VSS
0
BB7
VSS
C1
VSS
5
C2
VSS
C5
VSS
0
D1
VSS
D1
1
VSS
4
D1
VSS
8
D1
VSS
2
D2
VSS
D25
VSS
6
D2
VSS
0
D3
VSS
D3
4
VSS
9
D3
VSS
4
D4
VSS
5
D4
VSS
D4
7
VSS
8
D4
VSS
3
D5
VSS
8
D5
VSS
D6
VSS
2
D6
VSS
6
D6
VSS
D6
9
VSS
E1
1
VSS
5
E1
VSS
8
E1
VSS
1
E2
VSS
E46
VSS
0
E5
VSS
3
E5
VSS
E5
6
VSS
E6
VSS
5
E6
VSS
1
E7
VSS
F1
VSS
3
F1
VSS
F2
VSS
2
F2
VSS
F2
3
VSS
7
F2
VSS
8
F2
VSS
2
F3
VSS
F3
3
VSS
5
F3
VSS
7
F3
VSS
8
F3
VSS
F4
VSS
0
F4
VSS
2
F4
VSS
BA4
1
VSS
17
OF 20
UC1R
F8
0
G1
2
G2
3
G4
G4
5
8
G4
G5
2
G5
G55
8
G5
G6
G6
0
3
G6
6
G6
5
H1
H1
8
1
H7
1
J1
3
J1
J2
5
8
J2
2
J3
5
J3
J3
8
2
J4
J8
6
K1
K18
2
K2
1
K6
K6
3
4
K6
5
K6
6
K6
K6
7
8
K6
0
K7
1
K7
L11
L16
L17
SKL-U_BGA1356
@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GN
D 3 OF 3
SKL
-U
Rev_0.53
L18
VSS
L2
VSS
L20
VSS
L4
VSS
L8
VSS
0
N1
VSS
3
N1
VSS
9
N1
VSS
N21
VSS
N6
VSS
5
N6
VSS
N6
8
VSS
7
P1
VSS
9
P1
VSS
0
P2
VSS
P2
1
VSS
3
R1
VSS
R6
VSS
5
T1
VSS
T1
7
VSS
8
T1
VSS
T2
VSS
1
T2
VSS
T4
VSS
0
U1
VSS
3
U6
VSS
4
U6
VSS
U66
VSS
7
U6
VSS
9
U6
VSS
U7
0
VSS
6
V1
VSS
7
V1
VSS
8
V1
VSS
W1
3
VSS
W6
VSS
W9
VSS
7
Y1
VSS
Y1
9
VSS
0
Y2
VSS
1
Y2
VSS
OF 20
18
4 4
Security Classification
Security Classification
Security Classification
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
Issued Date
Issued Date
Issued Date
TH
TH
TH
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
2014/
C
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
Date: Sheet
Date: Sheet
D
Date: Sheet
L-U(11/12)GND
L-U(11/12)GND
L-U(11/12)GND
SK
SK
SK
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
E
0
0
0
1.
1.
1.
16 60Tuesday, June 16, 2015
16 60Tuesday, June 16, 2015
16 60Tuesday, June 16, 2015
of
of
of
A
1 1
CF
T213 @
T215 @
T220 @
T222 @
G0
G1
CF
G2
CF
G3
CF
G4
CF
CF
G5
CF
G6
CF
G7
CF
G8
G9
CF
G10
CF
G11
CF
CF
G12
CF
G13
CF
G14
CF
G15
G16
CF
G17
CF
CF
G18
CF
G19
CF
G_RCOMP
XDP_ITP_PMODE
G06
CF
G16
CF
CF
G26
CF
G36
CF
G46
G56
CF
G66
CF
G76
CF
G86
CF
CF
XDP_
G96
CF
G106
CF
G116
CF
G126
G136
CF
G146
CF
G156
CF
CF
G166
CF
G176
G186
CF
G196
CF
ITP_PMODE6
CFG
Signals
(For Strap & XDP)
2 2
#544924 SKylake EDS 0.75 P.117
RSVD - these signals should not be connected
î¡„
- these signals should be routed to a test point
RSVD_TP
î¡„
RSVD_NCTF
î¡„
and
3 3
- these signals are non-critical to function
may be left un-connected
G69
G68
G71
G70
AY2
AY1
AL25
AL27
BA70
BA68
G65
E68
B67
D65
D67
E70
C68
D68
C67
F71
F70
H70
H69
E63
F63
E66
F66
E60
K46
K45
C71
B70
F60
A52
F65
F61
E61
E8
D1
D3
J71
J68
B
UC1S
G[0]
CF
CF
G[1]
CF
G[2]
G[3]
CF
G[4]
CF
CF
G[5]
CFG[6]
G[7]
CF
CF
G[8]
CF
G[9]
G[10]
CF
G[11]
CF
CF
G[12]
CF
G[13]
G[14]
CF
G[15]
CF
CF
G[16]
G[17]
CF
CF
G[18]
CF
G[19]
G_RCOMP
CF
ITP_PMODE
RS
VD_AY2
RS
VD_AY1
VD_D1
RS
RS
VD_D3
VD_K46
RS
VD_K45
RS
RS
VD_AL25
VD_AL27
RS
RS
VD_C71
RS
VD_B70
RS
VD_F60
RSVD_A52
VD_TP_BA70
RS
RS
VD_TP_BA68
VD_J71
RS
RS
VD_J68
F65
VSS_
G65
VSS_
RS
VD_F61
VD_E61
RS
SKL-U_BGA1356
@
SERVED SIGNALS-1
RE
C
-U
SKL
19
OF 20
VD_TP_BB68
RS
RS
VD_TP_BB69
VD_TP_AK13
RS
VD_TP_AK12
RS
RSVD_BB2
RS
RS
RS
RS
RS
RS
RS
RS
RS
RS
RSVD_D54
VSS_
VD_TP_AW71
RS
VD_TP_AW70
RS
OC_SELECT#
PR
Rev_0.5
VD_BA3
TP
TP
VD_D5
RS
VD_D4
RS
RS
VD_B2
RS
VD_C2
VD_B3
RS
RS
VD_A3
VD_AW1
RS
VD_E1
RSVD_E2
VD_BA4
VD_BB4
VD_A4
RS
RS
VD_C4
TP
VD_A69
VD_B69
VD_AY3
VD_D71
VD_C70
VD_C54
TP
TP
AY71
ZV
MS
3
5
6
4
1
2
M#
M#
Follow
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
PM_
PM_
SKL
82 0_0402_5%@
RC1
83 0_0402_5%@
RC1
ZVM#
MSM#
_CNL#
T156 @
T157 @
T158 @
T159 @
T162 @
T163 @
T199 @
1 2
T214 @
T216 @
1 2
T225 @
T221 @
T223 @
T230 @
RC1
+1.
8VALW_PRIM
RC5
0_0402_5%
1 2
@
84 100K_0402_5%
544669_SKL_U_DDR3L_RVP7_schematic_rev1.0
7
0V_VCCST
+1.
@
D
AW69
AW68
AU56
AW48
+1.8VALW_PRIM_U11
12
1
CC7
1U_0402_6.3V6K
2
@
CC79 near U11,U12 (<10 mm)
14MOW52, Connect U11, U12 to
1.8V for Cannonlake-U PCH
compatibilit y
C7
U12
U11
H11
9
For
PM_ZVM#
Zero Voltage Mode: Control Signal to OPC
VR, when low OPC VR output is 0V.
PM_MSM#
Minimum Speed Mode: Control signal to
VccEOPIO VR (connected only in 2 VR
solution for OPC).
PROC_SELECT#
Processor Select: This pin is for
compatibility with future platforms. It should
NC with Skylake
SKL-U_BGA1356
@
2+3e Solution
UC1T
RS
VD_AW69
RS
VD_AW68
VD_AU56
RS
VD_AW48
RS
RS
VD_C7
RSVD_U12
VD_U11
RS
RS
VD_H11
E
-U
SKL
SP
ARE
Rev_0.53
F6
RS
VD_F6
E3
RS
VD_E3
C11
VD_C11
RS
B11
VD_B11
RS
A11
RS
VD_A11
D12
RSVD_D12
C12
VD_C12
RS
F52
RS
OF 20
VD_F52
20
CF
G_RCOMP
G4
CF
4 4
Port Presence Strap
Display
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
: Enabled; An external Display Port device is
0
connected to the Embedded Display Port
1 2
RC1
85 49.9_0402_1%
1 2
93 1K_0402_1%
RC1
A
Security Classification
Security Classification
Security Classification
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
Issued Date
Issued Date
Issued Date
TH
TH
TH
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
IS SHEET OF ENGINEE RING D RAWING IS THE PROPRIE TARY PRO PERTY OF C OMPAL ELEC TRONIC S, INC. A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2014/
C
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
tle
tle
tle
Ti
Ti
Ti
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
Date: Sheet
Date: Sheet
D
Date: Sheet
L-U(12/12)RSVD
L-U(12/12)RSVD
L-U(12/12)RSVD
SK
SK
SK
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
E
0
0
0
1.
1.
1.
17 60Tuesday, June 16, 2015
17 60Tuesday, June 16, 2015
17 60Tuesday, June 16, 2015
of
of
of
A
.675V_A_VREFDQ
DDR_A_DQS#[0..7]7
DDR_
A_D[0..63]7
A_DQS[0..7]7
DDR_
DDR_
A_MA[0..15]7
A_BS07
DDR_
A_BS17
DDR_
A_BS27
DDR_
DDR_
@
1
2
DDR_
DDR_A_CKE07
DDR_
DDR_
DDR_
SO
SO
DDR_
DDR_
1U
_0402_6.3V6K
1
CD5
2
10U_0603_6.3V6M
@
CD1
1
+0.675VS_VTT
DDR_
DDR_
DDR_
DDR_
DDR_
A_WE#7
A_CAS#7
A_RAS#7
A_CLK07
A_CLK#07
A_CLK17
A_CLK#17
A_CKE17
A_CS#07
A_CS#17
C_SMBDATA8,19,41
C_SMBCLK8,19,41
A_ODT07
A_ODT17
1U
_0402_6.3V6K
1
2
10U_0603_6.3V6M
CD1
1
2
2
1U_0402_6.3V6K
1
2
1 1
Note:
Layout
Place near JDIMM1
2 2
.35V_VDDQ
+1
1U
_0402_6.3V6K
1
CD4
2
+1.35V_VDDQ
10U_0603_6.3V6M
10U_0603_6.3V6M
CD1
1
0
3 3
4 4
2
Layout Note:
Place near JDIMM1.203,204
DDR_
A_BS0
DDR_
A_BS1
A_BS2
DDR_
A_WE#
DDR_
A_CAS#
DDR_
DDR_
A_RAS#
A_CLK0
DDR_
A_CLK#0
DDR_
DDR_
A_CLK1
DDR_
A_CLK#1
A_CKE0
DDR_
DDR_
A_CKE1
DDR_
A_CS#0
DDR_
A_CS#1
SO
C_SMBDATA
SOC_SMBCLK
A_ODT0
DDR_
DDR_A_ODT1
Note:
voltage tolerance of
Check
VREF_DQ at the DIMM socket
1U
1U
_0402_6.3V6K
_0402_6.3V6K
1
1
@
CD7
CD6
2
10U_0603_6.3V6M
@
CD1
CD1
1
1
3
4
2
2
1U_0402_6.3V6K
1
CD2
CD2
4
5
2
A
@
@
CD8
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD1
1
1
9
2
2
Layout Note:
Place near JDIMM1.199
+0
0
RD1
2_0402_1%
1
1
CD2
0.022U_0402_16V7K
2
12
2
RD1
24.9_0402_1%
Place near to SO-DIMM connector.
1U
_0402_6.3V6K
1
CD9
2
Fo
1
2
CD2
0
@
+3VS
llow MA51
1
+
CD16
330U_D2_2V_Y
2
SG
A00009S00
330U 2V H1.9
9mohm POLY
1
CD2
7
.1U_0402_16 V7K
2
10U_0603_6.3V6M
CD1
5
RD9
12
1
RD1
+1
.35V_VDDQ
12
8K_0402_1%
1.
12
1.8K_0402_1%
B
.675V_DDRA_VREFDQ
+0
+0
B
1
CD1
.1
U_0402_16V 7K
2
.675VS_VTT
10mils
+3
VS
DDR_
A_D0
DDR_
A_D4
DDR_
A_D6
DDR_
A_D7
A_D9
DDR_
A_D8
DDR_
DDR_
A_DQS#1
A_DQS1
DDR_
A_D11
DDR_
DDR_
A_D15
A_D20
DDR_
A_D17
DDR_
DDR_
A_DQS#2
DDR_
A_DQS2
A_D23
DDR_
A_D18
DDR_
DDR_A_D29
DDR_
A_D28
A_D30
DDR_
DDR_
A_D31
.35V_VDDQ
+1
A_CKE0
DDR_
A_BS2
DDR_
A_MA12
DDR_
DDR_
A_MA9
DDR_
A_MA8
A_MA5
DDR_
DDR_
A_MA3
DDR_
A_MA1
A_CLK0
DDR_
A_CLK#0
DDR_
DDR_
A_MA10
DDR_
A_BS0
A_WE#
DDR_
DDR_A_CAS#
DDR_
A_MA13
A_CS#1
DDR_
DDR_
A_D37
A_D32
DDR_
A_DQS#4
DDR_
DDR_
A_DQS4
DDR_
A_D39
A_D38
DDR_
DDR_
A_D45
DDR_
A_D44
DDR_
A_D46
DDR_
A_D47
DDR_
A_D48
DDR_A_D53
DDR_A_DQS#6
DDR_
A_DQS6
A_D54
DDR_
DDR_A_D55
DDR_A_D58
A_D59
DDR_
A_D60
DDR_
DDR_
A_D61
C
IMM1
JD
1
EF_DQ
VR
3
VSS
5
0
DQ
7
DQ
1
9
VSS
11
DM0
13
VSS
15
DQ2
17
3
DQ
19
VSS
21
DQ
8
23
DQ9
25
VSS
27
DQS1#
29
DQ
S1
31
VSS
33
DQ
10
35
11
DQ
37
VSS
39
16
DQ
41
17
DQ
43
VSS
45
S2#
DQ
47
S2
DQ
49
VSS
51
DQ
18
53
19
DQ
55
VSS
57
24
DQ
59
DQ
25
61
VSS
63
DM
3
65
VSS
67
DQ
26
69
DQ
27
71
VSS
73
CK
E0
75
D
VD
77
NC
79
BA2
81
VDD
83
2/BC#
A1
85
A9
87
VD
D
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VD
D
101
0
CK
103
CK
0#
105
D
VD
107
0/AP
A1
109
BA0
111
D
VD
113
#
WE
115
S#
CA
117
VD
D
119
3
A1
121
S1
#
123
D
VD
125
TE
ST
127
VSS
129
DQ
32
131
DQ
33
133
VSS
135
DQ
S4#
137
S4
DQ
139
VSS
141
34
DQ
143
DQ
35
145
VSS
147
DQ40
149
41
DQ
151
VSS
153
5
DM
155
VSS
157
DQ
42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
BELLW_80001-1021
SP07000P700
CONN@
Security Classifica tio n
Security Classifica tio n
Security Classifica tio n
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
C
DQ
RE
DQ
VR
EF_CA
DQS5#
DQS7#
EVENT#
BOSS2
VSS
DQ
DQ
VSS
S0#
DQS0
VSS
DQ6
DQ
VSS
DQ
DQ13
VSS
DM1
SET#
VSS
DQ
DQ
VSS
DQ
DQ
VSS
DM
VSS
DQ
DQ
VSS
DQ
DQ
VSS
S3#
DQ
VSS
DQ
DQ
VSS
CK
VD
A15
A1
VDD
A1
VD
VDD
VD
CK
CK
VD
BA1
RA
VD
S0
OD
VD
OD
VD
VSS
DQ
DQ
VSS
DM
VSS
DQ
DQ
VSS
DQ
DQ45
VSS
DQ
VSS
DQ
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7
VSS
DQ62
DQ63
VSS
SDA
SCL
VTT
GND2
2
4
4
6
5
8
10
12
14
16
18
7
20
22
12
24
26
28
30
32
34
14
36
15
38
40
20
42
21
44
46
2
48
50
22
52
23
54
56
28
58
29
60
62
64
S3
66
68
30
70
31
72
74
E1
76
D
78
80
4
82
84
1
86
A7
88
D
90
A6
92
A4
94
96
A2
98
A0
100
D
102
1
104
1#
106
D
108
110
S#
112
D
114
#
116
T0
118
D
120
T1
122
NC
124
D
126
128
130
36
132
37
134
136
4
138
140
38
142
39
144
146
44
148
150
152
154
S5
156
158
46
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
DDR_A_D1
DDR_
A_D5
A_DQS#0
.35V_VDDQ
+1
DDR_
DDR_A_DQS0
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_A_D25
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_A_ODT0
DDR_
A_D3
A_D2
A_D13
A_D12
DRAMRST#
A_D10
A_D14
A_D21
A_D19
A_D16
A_D22
A_D24
A_DQS#3
A_DQS3
A_D26
A_D27
A_CKE1
A_MA15
A_MA14
A_MA11
A_MA7
A_MA6
A_MA4
A_MA2
A_MA0
A_CLK1
A_CLK#1
A_BS1
A_RAS#
A_CS#0
A_ODT1
+1.35V_VDDQ
12
RD1
470_0402_5%
1
CD3
U_0402_16V 7K
.1
2
@
NOTE
CAD
PLACE THE CAP NEAR TO
DIMM RESET PIN
2015MOW02,
.675V_DDRA_VREFCA
+0
10mils
DDR_
A_D33
A_D36
DDR_
DDR_
A_D35
DDR_
A_D34
A_D41
DDR_
DDR_
A_D40
A_DQS#5
DDR_
DDR_
A_DQS5
DDR_
A_D42
DDR_
A_D43
DDR_
A_D52
DDR_A_D49
DDR_A_D51
A_D50
DDR_
A_D56
DDR_
DDR_A_D57
DDR_
A_DQS#7
A_DQS7
DDR_
A_D62
DDR_
DDR_
A_D63
C_SMBDATA
SO
SO
C_SMBCLK
.675VS_VTT
+0
11/10 2016/11/10
11/10 2016/11/10
11/10 2016/11/10
2014/
2014/
2014/
+0
mpal Secret Data
mpal Secret Data
mpal Secret Data
Co
Co
Co
.675VS_VTT
Deciphered Date
Deciphered Date
Deciphered Date
1
2
D
From
CPU to CHB
DRAMRST# 7,19
DDR_
Can't install Cap on DRAMRST
.675V_DDR_VREFCA
+0
1 2
RD8
@
0_0402_5%
7
CD1
.1U_0402_16 V7K
D
E
Reverse
2-3A
to 1 DIMMs/channel
terleaved Memory
In
Compal Electronics, Inc.
Compal Electronics, Inc.
Ti
Ti
Ti
tle
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Cu
Cu
Cu
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDR3L_DIMMA
DDR3L_DIMMA
stom
stom
stom
DDR3L_DIMMA
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
A4WAS M/B LA-C611P
E
Type
18 60Tuesday, June 16, 2015
18 60Tuesday, June 16, 2015
18 60Tuesday, June 16, 2015
0
0
0
1.
1.
1.
Loading...