Acer Aspire 7330, Aspire 7730 Extenza 7230, Extenza 7630 Schematics

5

4

3

2

1

BOM MARK

ZY2 SYSTEM BLOCK DIAGRAM

X'TAL

P16

P17

14.318MHZ

P2

Dual Channel DDR2

667/800 MHz

Dual Channel DDR3

667/800 MHz

Penryn 479
uFCPGA

FSB

NB
Cantiga
PM965

P5,P6,P7,P8,P9,P10,P11

P3,P4

667/800/1067 Mhz

X4 DMI interface

要打

要打

要打

要打

要打

要打

要打

要打

要打

要打

要打

要打

要打

要打

要打

要打

要打

CLOCK GENERATOR

ICS: ICS9LPRS365BGLFT
SELGO: SLG8SP512K05

DDRII
SO-DIMM 0
SO-DIMM 1

DDRIII
SO-DIMM 0
SO-DIMM 1

E@ EXT VGA

D D

C C

268@ AUDIO 268
D@ DOCK
D2@ DDR2
SP@ 特殊(EXT VGA OR DDR2)
LC@ LOW COST
ED2@ EXT VGA & DDR2
CB@ CARDBUS
NSF@ Non ASF

I@ INT VGA
888@ AUDIO 888
D3@ DDR3
ND@ NON DOCK
NLC@ NON LOW COST
TPM@ INT TPM
ID2@ INT VGA & DDR2
ED3@ EXT VGA & DDR3
ID3@ INT VGA & DDR3
ASF@ ASF
NCB@ NON CARDBUS

HDD (SATA)*2

LOW COST

1. MINI CARD 1 SLOT

2. NON DOCK

3. NON CARDBUS

4. NON ASF

5. NON HDMI

ODD (SATA)

Bluetooth

B B

USB4 P22

USB Port x 4

USB0~3

CCD

P25

P19USB7

Int MIC

P25

P25

P27

SATA0

SATA1

SATA4

USB 2.0

Azalia

SB
ICH9M

P12,P13,P14,P15

LPC

X'TAL

32.768KHZ

EC (WPC8769LDG)

Azalia Audio

SPDIF

P28

Controller
ALC268 & 888

Connector

P28

P27

MDC 1.5

MIC Jack

P28

4

P27

Audio Amplifier

A A

Speaker

P27 & 28

Phone Jack Line in

5

P28P28

TPM

P23

SUBWOOFER

P28

SPI ROM

Touch Pad

K/B COON.

P32

P32

P32

P32

3

CPU

Thermal Sensor

PCIE

MXM-NB8P-GS
( nVidia )

VRAM 256M
VRAM 512M

LVDS

RGB

DVI Level Shift IC
PI3VDP411LSZDE

Page:20

PCI-Express

PCI Bus

Cardreader
Controller

OZ601T

X'TAL

32.768K

Media Card Reader

VR

P27

CIR

P32

P3

P18

P29

P29

Fan Header

EXT_LVDS

EXT_CRT

EXT_DVI

INT_LVDS

INT_CRT

INT_DVI

BROADCOM

10/100/1G LAN

SWITCH CIRCUIT

Transformer

P31

2

5764M

RJ45

P22

CRT

Page:19

SWITCH
CIRCUIT

PCIE-1

New Card

PCIE-4

PCIE-6

X'TAL
25M

P21

Page:22

P22

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Mini Card /
WLAN / TV

Quanta Computer Inc.

Quanta Computer Inc.
PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

Block Diagram

Block Diagram

Block Diagram

LVDS

Page:19

HDMI

Page:20

DOCKING/DVI

Page: 31

USB5

P23

P23

USB6

DOCK/LAN

Page: 33

1

140Tuesday, April 08, 2008

140Tuesday, April 08, 2008

140Tuesday, April 08, 2008

1A

1A

1A

of

of

of

5

4

3

2

1

Clock Generator

U25

U25

R255 BKP1608HS181-TR255 BKP1608HS181-T

+3V +1.05V

C257

C215

C219

C216

C216

.1U/10V_4

D D

.1U/10V_4

C219

.1U/10V_4

.1U/10V_4

C215

.1U/10V_4

.1U/10V_4

C257

.1U/10V_4

.1U/10V_4

R254 Change from 33 to 475

SATACLKREQ#<14>

NEW_CLKREQ#<29>

PCLK_DEBUG<23>

PCLK_591<32>

PCLK_PCM<27>

PCLK_ICH<13>

CLKUSB_48<14>

14M_ICH<14>

CLK_DREFCLK<6>
CLK_DREFCLK#<6>

C C

+3V

PCLK_ICH

CPU_BSEL0

MCH_BSEL1

CPU_BSEL2

CGCLK_SMB
CGDAT_SMB

Clock Gen I2C

R237

R237

R243

10K_4

10K_4

R243

10K_4

10K_4

CGDAT_SMB

Q26

Q26
RHU002N06

RHU002N06

PDAT_SMB<14,16,20,21,23,29>

2

3

1

+3V_CLK

C262

C262

.1U/10V_4

.1U/10V_4

R246 475/F_4R246 475/F_4
R254 475/F_4R254 475/F_4
R253 33_4R253 33_4
R252 33_4R252 33_4
R264 33_4R264 33_4
R263 33_4R263 33_4

R258 2.2K_4R258 2.2K_4
R261 33_4R261 33_4

R230 10K_4R230 10K_4

C209*30P/50V_4 C209*30P/50V_4

R229 33_4R229 33_4

RP16 I@0X2RP16 I@0X2

4
2

C260

C260

.1U/10V_4

.1U/10V_4

3
1

C263

C263

10U/6.3V_6

10U/6.3V_6

CG_XOUT
CG_XIN
SATACLKREQ#_R
NEW_CLKREQ#_R
PCLK_MINI_R
PCLK_591_R
PCLK_PCM_R
PCLK_ICH_R

FSA

DREFCLK_R
DREFCLK#_R

FSC

2

VDD_PCI

9

VDD_48

16

VDD_PLL3

39

VDD_SRC

55

VDD_CPU

61

VDD_REF

59

XTAL_OUT

60

XTAL_IN

1

PCI_0/CLKREQ_A#

3

PCI_1/CLKREQ_B#

4

PCI_2

5

PCI_3

6

^PCI_4/LCDCLK_SEL

7

PCIF_5/ITP_EN

10

USB_48MHz/FS_A

57

FS_B/TEST_MODE

62

REF/FS_C/TEST_SEL

13

SRC_0/DOT_96

14

SRC_0#/DOT_96#

64

SCL

63

SDA

8

VSS_PCI

11

VSS_48

15

VSS_I/O

19

VSS_PLL3

23

VSS_SRC_1

29

VSS_SRC_2

42

VSS_SRC_3

52

VSS_CPU

58

VSS_REF

SLG8SP512

SLG8SP512

VDD_I/O

VDD_PLL3_I/O
VDD_SRC_I/O_1
VDD_SRC_I/O_2
VDD_SRC_I/O_3

VDD_CPU_I/O

CPU_STOP#

PCI_STOP#

CKPWRGD/PD#

CPU_0

CPU_0#

CPU_1_MCH

CPU_1_MCH#

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

LCDCLK/27M

LCDCLK#/27M_SS

SRC_2

SRC_2#

SRC_3/CLKREQ_C#

SRC_3#/CLKREQ_D#

SRC_7/CLKREQ_F#

SRC_7#/CLKREQ_E#

SRC_11/CLKREQ_H#

SRC_11#/CLKREQ_G#

SRC_4

SRC_4#

SRC_6

SRC_6#

SRC_9
SRC_9#
SRC_10

SRC_10#

12
20
26
36
45
49

37
38
56

54
53
51
50
47
46

48

NC

17
18

21
22
24
25
27
28
41
40
44
43
30
31
34
35
33
32

C272

C272

10U/6.3V_6

10U/6.3V_6

CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R
CLK_MCH_BCLK_R
CLK_MCH_BCLK#_R
CLK_PCIE_CARD_R
CLK_PCIE_CARD#_R

CLK_DREFSSCLK_R
CLK_DREFSSCLK#_R

CLK_PCIE_SATA_R
CLK_PCIE_SATA#_R
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
CLK_PCIE_NEW_C_R
CLK_PCIE_NEW_C#_R
CLK_PCIE_ICH_R
CLK_PCIE_ICH#_R
PECLK_VGA_R
PECLK_VGA#_R
CLK_PCIE_MINI1_R
CLK_PCIE_MINI1#_R
CLK_PCIE_3GPLL_R
CLK_PCIE_3GPLL#_R
CLK_PCIE_TV_R
CLK_PCIE_TV#_R

Rev:C Change C 205 & C204 P/N to CH03306JB04

QCI P/N

B B

PCLK_SMB<14,16,20,21,23,29>

Q27

Q27
RHU002N06

RHU002N06

3

+3V

2

1

CGCLK_SMB

ICS9LPRS365BGLFT

AL8SP512K05

ALPRS365K13

+1V05_CLK

C265

C213

C213

.1U/10V_4

.1U/10V_4

RP13 0X2_4RP13 0X2_4

1
3

RP12 0X2_4RP12 0X2_4

1
3

RP11 0X2_4RP11 0X2_4

1
3

RP15 I@0X2RP15 I@0X2

3
1

RP18 0X2_4RP18 0X2_4

3
1

RP17 0X2_4RP17 0X2_4

3
1

RP20 0X2_4RP20 0X2_4

3
1

RP9 0X2_4RP9 0X2_4

1
3

RP10 E@0X2RP10 E@0X2

1
3

RP19 0X2_4RP19 0X2_4

3
1

RP8 0X2_4RP8 0X2_4

3
1

RP14 0X2_4RP14 0X2_4

1
3

C205 33P/50V_4C205 33P/50V_4

C204 33P/50V_4C204 33P/50V_4

C265

.1U/10V_4

.1U/10V_4

2
4
2
4
2
4

4
2

4
2
4
2
4
2
2
4
2
4
4
2
4
2
2
4

Strap table

C214

C214

.1U/10V_4

.1U/10V_4

Y8

Y8

14.318MHz

14.318MHz

CG_XIN

CG_XOUT

C212

C212

.1U/10V_4

.1U/10V_4

PM_STPCPU# <14>
PM_STPPCI# <14>
CK_PWRGD <14>

CLK_CPU_BCLK <3>
CLK_CPU_BCLK# <3>
CLK_MCH_BCLK <5>
CLK_MCH_BCLK# <5>
CLK_PCIE_CARD <28>
CLK_PCIE_CARD# <28>

CLK_DREFSSCLK <6>
CLK_DREFSSCLK# <6>

CLK_PCIE_SATA <12>
CLK_PCIE_SATA# <12>
CLK_PCIE_LAN <21>
CLK_PCIE_LAN# <21>
CLK_PCIE_NEW_C <29>
CLK_PCIE_NEW_C# <29>
CLK_PCIE_ICH <13>
CLK_PCIE_ICH# <13>
CLK_MXM <18>
CLK_MXM# <18>
CLK_PCIE_MINI1 <23>
CLK_PCIE_MINI1# <23>
CLK_PCIE_3GPLL <6>
CLK_PCIE_3GPLL# <6>
CLK_PCIE_TV <23>
CLK_PCIE_TV# <23>

CLK VDD power range 1.05V~3.3V

C261

C261

.1U/10V_4

.1U/10V_4

C267

C267

.1U/10V_4

.1U/10V_4

Pin 56 : It acts as a
level sensitive strobe
to latch the FS pins
and other multiplexed
inputs.

Rev:B Swap SRC9 & SRC4

SATACLKREQ#_R

NEW_CLKREQ#_R

PCLK_MINI_R

Rev:B for vendor requestSLG8SP512

R219BKP1608HS181-T R219BKP1608HS181-T

+3V

R475 10K_4R475 10K_4

R531 10K_4R531 10K_4

R532 10K_4R532 10K_4

CPU Clock select

BSEL Frequency Select Table

FSC FSB FSA Frequency

Pin 10/57/62 : For Pin CPU frequency selection

CPU_BSEL0<3>

A A

CPU_BSEL1<3>

CPU_BSEL2<3>

5

R262 0_4R262 0_4

R226 0_4R226 0_4

R231 0_4R231 0_4

MCH_BSEL0 <6>

MCH_BSEL1 <6>

CRB Rev0.7 : 110(CBA)

MCH_BSEL2 <6>

4

0

0

0

1

0

1

0

1

1

1

1

0

1

0

0

1

1

0

01

1

1

0

3

266Mhz0

133Mhz

166Mhz

200Mhz

400Mhz

Reserved

100Mhz

333Mhz

2

PCLK_PCM_R

Pin 6 : For Pin 13/14 and 17/18 selection
0 = LCDCLK & DOT96 for internal graphic controller support
1 = 27M & 27M_SS &SRC_0 for external graphic controller support

PCLK_ICH_R

R260 10K_4R260 10K_4

R259 10K_4R259 10K_4

Pin 7 : For Pin 46/47 selection
1 = CPU_ITP
0 = SRC_8

Quanta Computer Inc.

Quanta Computer Inc.
PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CLOCK GENERATOR CK505 W/REGULATOR

CLOCK GENERATOR CK505 W/REGULATOR

CLOCK GENERATOR CK505 W/REGULATOR

Date: Sheet

Date: Sheet

Date: Sheet

240Tuesday, April 08, 2008

240Tuesday, April 08, 2008

240Tuesday, April 08, 2008

of

of

1

of

1A

1A

1A

5

4

3

2

1

H_A#[3..16]<5>

D D

H_ADSTB#0<5>

H_REQ#[0..4]<5>

H_A#[17..35]<5>

C C

H_ADSTB#1<5>

H_A20M#<12>
H_FERR#<12>
H_IGNNE#<12>

H_STPCLK#<12>
H_INTR<12>
H_NMI<12>
H_SMI#<12>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

R494 0_4R494 0_4

AA4
AB2
AA3

D22

W6

W2
W5

W3

J4
L5

L4
K5
M3
N2

J1
N3
P5
P2

L2
P4
P1
R1
M1

K3
H2
K2

J3

L1

Y2
U5
R3

U4
Y5
U1
R4
T5
T3

Y4
U2
V4

V1

A6
A5
C4

D5
C6
B4
A3

M4
N5
T2
V3
B2
D2

D3
F6

U40A

U40A

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

ADDR GROUP_0

ADDR GROUP_0

ADDR GROUP_1

ADDR GROUP_1

THERMAL

THERMAL

ICH

ICH

THERMTRIP#

RESERVED

RESERVED

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

PROCHOT#

THERMDA

THERMDC

H CLK

H CLK

BCLK[0]
BCLK[1]

U40B

AD26

AF26

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24

H22
F26
K22
H23

H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

C23
D25
C24

AF1
A26

B22
B23
C21

J24
J23

J26

C3

U40B

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

Penryn

Penryn

DATA GRP 0

DATA GRP 0

MISC

MISC

DATA GRP 1

DATA GRP 1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0

R500 27.4/F_6R500 27.4/F_6

COMP1

R501 54.9/F_4R501 54.9/F_4

COMP2

R144 27.4/F_6R144 27.4/F_6

COMP3

R147 54.9/F_4R147 54.9/F_4

H_D#[32..47]

H_D#[48..63]

H_DSTBN#3 <5>
H_DSTBP#3 <5>
H_DINV#3 <5>

ICH_DPRSTP# <6,12,35>
H_DPSLP# <12>
H_DPWR# <5>
H_PWRGD <12>
H_CPUSLP# <5>
PSI# <35>

H_D#[32..47] <5>

H_DSTBN#2 <5>
H_DSTBP#2 <5>
H_DINV#2 <5>

H_D#[48..63] <5>

Layout note:
comp0,2: Zo=27.4ohm, L<0.5"
comp1,3: Zo=55ohm, L<0.5"

Layout note:
DPRSTP# , Daisy Chain
(SB>Power>NB>CPU)

H1
E2
G5

H5
F21
E1

F1

H_IERR#

D20
B3

H4

C1
F3
F4
G3
G2

G6
E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

H_PROCHOT#_D
H_THERMDA
H_THERMDC

PM_THRMTRIP#

R162 56.2/F_4R162 56.2/F_4

H_RS#0
H_RS#1
H_RS#2

R491 0_4R491 0_4

H_ADS# <5>
H_BNR# <5>
H_BPRI# <5>

H_DEFER# <5>
H_DRDY# <5>
H_DBSY# <5>

H_BREQ# <5>

H_INIT# <12>
H_LOCK# <5>

T16T16

H_CPURST# <5>
H_RS#[0..2] <5>

H_TRDY# <5>

H_HIT# <5>
H_HITM# <5>

T10T10
T15T15
T13T13
T11T11
T14T14

Connect it to CPU DBR# is for ITP debug port
or CPU interposer (like ICE) to reset the system

+1.05V

SYS_RST# <14>

CLK_CPU_BCLK <2>
CLK_CPU_BCLK# <2>

+1.05V

R113

R113
1K/F_4

1K/F_4

R115

R115
2K/F_6

2K/F_6

H_D#[0..15]<5>

H_DSTBN#0<5>
H_DSTBP#0<5>
H_DINV#0<5>

H_D#[16..31]<5>

H_DSTBN#1<5>
H_DSTBP#1<5>
H_DINV#1<5>

Layout note:
H_GTLREF: Zo=55 ohm
L<0.5", 2/3*VCCP+-2%

CPU_BSEL0<2>
CPU_BSEL1<2>
CPU_BSEL2<2>

H_D#[0..15]

H_D#[16..31]

T18T18
T17T17
T19T19
T72T72
T12T12
T70T70
T71T71

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

H_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
CPU_TEST7

Penryn

Penryn

Thermal Trip

B B

DELAY_VR_PWRGOOD<6,14,32,35>

+1.05V

R495

R495

56.2/F_4

+1.05V

56.2/F_4

R163

R163

56_4

56_4

5

PM_THRMTRIP#

A A

Processor hot

H_PROCHOT#_D

+1.05V

3

Q41

Q41

2

FDV301N

FDV301N

1

2

Q40

Q40
MMBT3904

MMBT3904

1 3

No use Thermal trip CPU side still PU 56ohm.
Use Thermal trip can share PU at SB side

No use PROCHOT CPU side still PU 56ohm.
Use PROCHOT to optional receiver CPU side PU
68ohm and through isolat 2.2K ohm to receiver
side

R164 *0_4R164 *0_4

SYS_SHDN# <34,38>

PM_THRMTRIP# <6,12>

H_PROCHOT# <35>

CPU Thermal monitor

2ND_MBCLK<32>

2ND_MBDATA<32>

THERM_ALERT#<14,18>

CPUFAN#_ON<31>

4

R540

R540

10K_4

10K_4

+3V

U39

U39

8

SCLK

7

SDA

6

ALERT#

4

OVERT#

G780

G780

ADDRESS: 98H

R490

R490

200_6

200_6

VCC

DXP

DXN

GND

LM86VCC

1

2

3

5

C552

C552

.1U/10V_4

.1U/10V_4

H_THERMDA

C551

C551

100P/X7R/50V_4

100P/X7R/50V_4

H_THERMDC

2

Rev:B Add R540

+3V

Q39

Q39

2

RHU002N06

RHU002N06

3

3

R465 *0_4R465 *0_4

+5V

R493 *10K_4R493 *10K_4

1

+3V

Q38

Q38

2

RHU002N06

RHU002N06

1

R466

R466

10K_4

10K_4

CPUFAN#_ON

3

R467

R467

10K_4

10K_4

XDP PU/PD

XDP_DBRESET#

XDP_TDO

XDP_TDI

XDP_TMS

XDP_BPM#5

XDP_TCK

XDP_TRST#

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CPU Host Bus

CPU Host Bus

CPU Host Bus

Date: Sheet

Date: Sheet

Date: Sheet

R492 *1K_4R492 *1K_4

XDP_DBRESET# and XDP_TDO
reserve for XDP

R128 *54.9/F_4R128 *54.9/F_4

R149 54.9/F_4R149 54.9/F_4

R131 54.9/F_4R131 54.9/F_4

R121 54.9/F_4R121 54.9/F_4

R127 54.9/F_4R127 54.9/F_4

R124 54.9/F_4R124 54.9/F_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

+3V

+1.05V

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

340Tuesday, April 08, 2008

340Tuesday, April 08, 2008

340Tuesday, April 08, 2008

of

of

of

1A

1A

1A

5

4

3

2

1

U40D

U40D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

D D

C C

B B

A A

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

Penryn

5

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

.

.

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

C557

C557

*10U/6.3V_8

*10U/6.3V_8

C565

C565

10U/6.3V_8

10U/6.3V_8

C156

C156

10U/6.3V_8

10U/6.3V_8

C573

C573

*10U/6.3V_8

*10U/6.3V_8

C154

C154

10U/6.3V_8

10U/6.3V_8

C572

C572

10U/6.3V_8

10U/6.3V_8

C140

C140

*10U/6.3V_8

*10U/6.3V_8

Layout Note:
Place these parts
reference to Intel demo
board.

C158

C158

*10U/6.3V_8

*10U/6.3V_8

C563

C563

10U/6.3V_8

10U/6.3V_8

10/12 :Modify BOM

4

C558

C155

C155

*10U/6.3V_8

*10U/6.3V_8

C571

C571

*10U/6.3V_8

*10U/6.3V_8

C153

C153

*10U/6.3V_8

*10U/6.3V_8

C574

C574

10U/6.3V_8

10U/6.3V_8

C558

10U/6.3V_8

10U/6.3V_8

C553

C553

*10U/6.3V_8

*10U/6.3V_8

C141

C141

*10U/6.3V_8

*10U/6.3V_8

C152

C152

10U/6.3V_8

10U/6.3V_8

C570

C570

10U/6.3V_8

10U/6.3V_8

C80

C80

+

+

*330U/2V_7343

*330U/2V_7343

Montevina platform : Early Reference Board Schematics Feb 2007. Rev 1.0
stuff 22U*34, NC 22U*2
stuff 330U*2, NC330U*2

C568

C568

*10U/6.3V_8

*10U/6.3V_8

C556

C556

10U/6.3V_8

10U/6.3V_8

C139

C139

*10U/6.3V_8

*10U/6.3V_8

C142

C142

*10U/6.3V_8

*10U/6.3V_8

C151

C151

*10U/6.3V_8

*10U/6.3V_8

C569

C569

*10U/6.3V_8

*10U/6.3V_8

C576

C576

+

+

330U/2V_7343

330U/2V_7343

C566

C566

*10U/6.3V_8

*10U/6.3V_8

C119

C119

*10U/6.3V_8

*10U/6.3V_8

C560

C560

10U/6.3V_8

10U/6.3V_8

C120

C120

*10U/6.3V_8

*10U/6.3V_8

C567

C567

10U/6.3V_8

10U/6.3V_8

C554

C554

10U/6.3V_8

10U/6.3V_8

C81

C81

+

+

330U/2V_7343

330U/2V_7343

3

+

+

VCC_CORE VCC_CORE

U40C

U40C

A7

C157

C157

*10U/6.3V_8

*10U/6.3V_8

C559

C559

*10U/6.3V_8

*10U/6.3V_8

C118

C118

10U/6.3V_8

10U/6.3V_8

C121

C121

10U/6.3V_8

10U/6.3V_8

C564

C564

*10U/6.3V_8

*10U/6.3V_8

C555

C555

*10U/6.3V_8

*10U/6.3V_8

C577

C577

*330U/2V_7343

*330U/2V_7343

A10
A12
A13
A15
A17
A18
A20

B10
B12
B14
B15
B17
B18
B20

C10
C12
C13
C15
C17
C18

D10
D12
D14
D15
D17
D18

E10
E12
E13
E15
E17
E18
E20

F10
F12
F14
F15
F17
F18
F20
AA7

AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

A9

B7
B9

C9

D9

E7
E9

F7
F9

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

Penryn

Penryn

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

.

.

VCCA : 2.5A(Supply after VCC Stable)

4.5A(Supply before VCC Stable)

2

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

VCC:38A

VCCP:130mA

H_VID0 <35>
H_VID1 <35>
H_VID2 <35>
H_VID3 <35>
H_VID4 <35>
H_VID5 <35>
H_VID6 <35>

CPU Power

CPU Power

CPU Power

Layout Note:
Inside CPU center cavity in 2 rows

C129

C129

.1U/16V_6

.1U/16V_6

C128

C128

.1U/16V_6

.1U/16V_6

+

+

C575

C575

330U/2.5V_7

330U/2.5V_7

Layout Note:
VCCA CAP closr to Pin
VCCA : 2.5A(Supply after VCC Stable)

4.5A(Supply before VCC Stable)

R84 100/F_6R84 100/F_6

R77

R77

100/F_6

100/F_6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

C135

C135

.1U/16V_6

.1U/16V_6

C136

C136

.1U/16V_6

.1U/16V_6

C562

C562

.01U/16V_4

.01U/16V_4

Layout Note:
Z0=27.4,PU/PD L<1"

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

1

+1.05V

C561

C561

10U/6.3V_8

10U/6.3V_8

VCC_CORE

VCCSENSE <35>

VSSSENSE <35>

of

of

of

440Tuesday, April 08, 2008

440Tuesday, April 08, 2008

440Tuesday, April 08, 2008

C147

C147

.1U/16V_6

.1U/16V_6

C148

C148

.1U/16V_6

.1U/16V_6

+1.5V

1A

1A

1A

5

4

3

2

1

U38A

H_D#[0..63]<3>

D D

QCI P/N

Intel Cantiga (G)M

Intel Cantiga (P)M

+1.05V

C C

B B

A A

0.3125*VCCP
WIDE(10):SPACING(20) ,

R177

R177

L<0.5"

221/F_4

221/F_4

H_SWING

R175

R175

100/F_4

100/F_4

R464

R464

24.9/F_4

24.9/F_4

2/3*VCCP
WIDE(10):SPACING(20),
L<0.5"

5

AJ0QT620T01

AJ0QT780T03

Capacitor close

C178

C178

to the pin

0.1U/10V_4

0.1U/10V_4

H_RCOMP

WIDE(10):SPACING(20) ,
L<0.5"

+1.05V

R484

R484

1K/F_4

1K/F_4

R482

R482

2K/F_4

2K/F_4

H_CPURST#<3>

4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_AVREF

U38A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

SP@CANTIGA_1p2

SP@CANTIGA_1p2

3

H_ADSTB#_0
H_ADSTB#_1

HOST

HOST

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

2

H_A#[3..35] <3>

H_ADS# <3>

H_ADSTB#0 <3>

H_ADSTB#1 <3>
H_BNR# <3>
H_BPRI# <3>
H_BREQ# <3>
H_DEFER# <3>
H_DBSY# <3>
CLK_MCH_BCLK <2>
CLK_MCH_BCLK# <2>
H_DPWR# <3>
H_DRDY# <3>
H_HIT# <3>
H_HITM# <3>
H_LOCK# <3>
H_TRDY# <3>

H_DINV#[3..0] <3>

H_DSTBN#[3..0] <3>

H_DSTBP#[3..0] <3>

H_REQ#[0..4] <3>

H_RS#[0..2] <3>H_CPUSLP#<3>

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH HOST

GMCH HOST

GMCH HOST

Date: Sheet

Date: Sheet

Date: Sheet

PROJECT :

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

of

of

of

540Tuesday, April 08, 2008

540Tuesday, April 08, 2008

540Tuesday, April 08, 2008

1

1A

1A

1A

5

4

3

2

1

Strap table

Pin Name Strap description

CFG[2:0]

CFG[4:3]

CFG5

CFG6

D D

CFG7

CFG8

CFG9

CFG10

FSB Frequency Select

Reserved

DMI X2 Select

iTPM Host Interface

ME TLS Confidentiality

Reserved

PCIE Graphics Lane Reversal

PCIE Loopback enable

ReservedCFG11

CFG12

CFG13

CFG[15:14]

CFG16

CFG[18:17]

CFG19

C C

CFG20

ALLZ

XOR

Reserved

FSB Dynamic ODT

Reserved

DMI Lane Reversal

Digital Display Port
(SDVO/DP/iHDMI)
Concurrent with PCIE

SDVO_CTRLDATA SDVO Present

DDPC_CTRLDATA Digital Display Present

Strap pin

+3V

R477 *4.02K/F_4R477 *4.02K/F_4
R478 *4.02K/F_4R478 *4.02K/F_4

B B

A A

R207 TPM@2.21K/F_4R207 TPM@2.21K/F_4
R479 *4.02K/F_4R479 *4.02K/F_4
R196 *4.02K/F_4R196 *4.02K/F_4
R487 *4.02K/F_4R487 *4.02K/F_4
R488 *4.02K/F_4R488 *4.02K/F_4
R222 *4.02K/F_4R222 *4.02K/F_4
R216 *4.02K/F_4R216 *4.02K/F_4
R200 *4.02K/F_4R200 *4.02K/F_4

REV: E Modify TPM (R207)

+3V

R184 I@2.21K/F_4R184 I@2.21K/F_4
R188 I@2.21K/F_4R188 I@2.21K/F_4
R206 *2.21K/F_4R206 *2.21K/F_4
R217 *2.21K/F_4R217 *2.21K/F_4
R481 10K_4R481 10K_4
R485 10K_4R485 10K_4
R209 10K_4R209 10K_4

5

Configuration

000= FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz

0 = DMI X2
1 = DMI X4(Default)

0 = iTPM Host Interface is enabled
1 = iTPM Host Interface is disabled(Default)

0 = AMT Firmware will use TLS cipher suite
with no confidentiality
1 = AMT Firmware will use TLS cipher suite
with confidentiality(Default)

0 = Reverse Lanes
1 = Normal operation(Default)

0 = Enabled
1 = Disabled (Default)

0 = ALLZ mode enable
1 = disable(Default)

0 = XOR mode enable
1 = disable(Default)

0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)

0 = Normal (Default)
1 = Lanes Reversed

0 = Only Digital Display port (SDVO/DP/iHDMI)
or PCIE is operational (Default)
1 = Digital Display port (SDVO/DP/iHDMI) and
PCIE are operating simultaneously via PEG
port

0 = No SDVO/HDMI Device Present(Default)
1 = SDVO/HDMI Device present

0 = Digital display(HDMI/DP) device
absent(Default)
1 = Digital display(HDMI/DP) device present

MCH_CFG_19
MCH_CFG_20

MCH_CFG_5
MCH_CFG_7

MCH_CFG_9
MCH_CFG_10
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16

MCH_CFG_6_R <13>

SDVO_CTRLDATA
SDVO_CTRLCLK

DDPC_DDCDATA
DDPC_CTRLCLK
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1

MCH_CFG_6<13>

PM_SYNC#<14>

ICH_DPRSTP#<3,12,35>
PM_EXTTS#0<16,17>

PM_EXTTS#1<16,17>

DELAY_VR_PWRGOOD<3,14,32,35>

PLT_RST#<13>

PM_THRMTRIP#<3,12>

PM_DPRSLPVR<14,35>

No use Thermal trip NB side can
NC.(NB has ODT)

PM_DPRSTP#
The Daisy chain topology should
be routed from ICH9M to IMVP ,
then to (G)MCH and CPU, in that
order.

4

T30T30

T28T28

T31T31

T29T29

MCH_BSEL0<2>
MCH_BSEL1<2>
MCH_BSEL2<2>

T25T25
T27T27

T21T21

T24T24

T26T26
T20T20

T22T22
T23T23

R213 0_4R213 0_4
R483 0_4R483 0_4
R470 0_4R470 0_4
R212 0_4R212 0_4

R247 100/F_4R247 100/F_4
R221 *0_4R221 *0_4
R218 0_4R218 0_4

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

MCH_CFG_3
MCH_CFG_4
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
MCH_CFG_15
MCH_CFG_16
MCH_CFG_17
MCH_CFG_18
MCH_CFG_19
MCH_CFG_20

PM_SYNC#_R
ICH_DPRSTP#_R

PM_EXTTS#0_1_EC_R

TS#DIMM0_1_R

RST_IN#_MCH
THRMTRIP#_R
DPRSLPVR_R

U38B

U38B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

T24

RSVD14

B31

RSVD15

M1

RSVD17

AY21

RSVD20

B2

RSVD21

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

AL34

ME_JTAG_TCK

AK34

ME_JTAG_TDI

AN35

ME_JTAG_TDO

AM35

ME_JTAG_TMS

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

SP@CANTIGA_1p2

SP@CANTIGA_1p2

3

CFG

CFG

PM

PM

NC

NC

SM_VREF.Default use voltage divider
for poor layout cause +SMDDR_VREF not
meet spec.And Intel circuit PU/PD is
1K,But Check list PU/PD is 10K.

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

RSVD

RSVD

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_DRAMRST#

DPLL_REF_CLK

DDR CLK/ CONTROL/COMPENSATION

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

ME JTAG

ME JTAG

CLK

CLK

DMI

DMI

GRAPHICS VID

GRAPHICS VID

MEHDA

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

MISC

SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

BB36

BA17
AY16
AV16
AR13

BD17
AY17
BF15
AY13

BG22
BH21

BF28
BH28

AV42
AR36
BF17
BC36

B38
A38
E41
F41

F43
E43

AE41
AE37
AE47
AH39

AE40
AE38
AE48
AH40

AE35
AE43
AE46
AH42

AD35
AE44
AF46
AH43

B33
B32
G33
F33
E33

C34

AH37
AH36
AN36
AJ35
AH34

N28
M28
G36
E36
K36
H36

B12

B28
B30
B29
C29
A28

M_CLK0
M_CLK1
M_CLK2
M_CLK3

M_CLK#0
M_CLK#1
M_CLK#2
M_CLK#3

M_RCOMP
M_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF
SM_PWROK
SM_REXT

R256 499/F_4R256 499/F_4
R257 D3@0_4R257 D3@0_4

CLK_DREFCLK
CLK_DREFCLK#
CLK_DREFSSCLK
CLK_DREFSSCLK#

CLK_PCIE_3GPLL
CLK_PCIE_3GPLL#

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

MCH_CLVREF_R

DDPC_CTRLCLK
DDPC_DDCDATA

CLK_MCH_OE#

TSATN#

R180 56_4R180 56_4

HDA_BIT_CLK_HDMI
HDA_RST#_HDMI
HDA_SDIN_HDMI
HDA_SDOUT_HDMI
HDA_SYNC_HDMI

Impact ICH9M VCCHDA and VCCSUSHDA supply 1.5V/3.3V

NOTE:
If (G)MCH's HD Audio signals are connected to ICH9M
for iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be
only on 1.5V. These power pins on ICH9M can be
supplied with 3.3V if and only if (G)MCH's HDA is not
connected to ICH9M. Consequently, only 1.5V
audio/modem codecs can be used on the platform.

M_CLK0 <16,17>
M_CLK1 <16,17>
M_CLK2 <16,17>
M_CLK3 <16,17>

M_CLK#0 <16,17>
M_CLK#1 <16,17>
M_CLK#2 <16,17>
M_CLK#3 <16,17>

M_CKE0 <16,17>
M_CKE1 <16,17>
M_CKE2 <16,17>
M_CKE3 <16,17>

M_CS#0 <16,17>
M_CS#1 <16,17>
M_CS#2 <16,17>
M_CS#3 <16,17>

M_ODT0 <16,17>
M_ODT1 <16,17>
M_ODT2 <16,17>
M_ODT3 <16,17>

SM_VREF=0.5*VCC_SM

SM_PWROK only for
DDR3.DDR2 PD only

SM_DRAMRST# only
for DDR3.DDR2 NC.

DDR3_DRAMRST# <17>

CLK_DREFCLK <2>
CLK_DREFCLK# <2>
CLK_DREFSSCLK <2>
CLK_DREFSSCLK# <2>

CLK_PCIE_3GPLL <2>
CLK_PCIE_3GPLL# <2>

DMI_TXN[3:0] <13>

DMI_TXP[3:0] <13>

DMI_RXN[3:0] <13>

DMI_RXP[3:0] <13>

CL_CLK0 <14>

CL_DATA0 <14>
MPWROK <14,32>
CL_RST#0 <14>

SDVO_CTRLCLK <20>

SDVO_CTRLDATA <20>

MCH_ICH_SYNC# <14>

HDA_BIT_CLK_HDMI <12>
HDA_RST#_HDMI <12>
HDA_SDIN_HDMI <12>
HDA_SDOUT_HDMI <12>
HDA_SYNC_HDMI <12>

2

Check list note : CL_REF=0.35VNB Thermal trip pin

+1.05V

C207

C207

0.1U/10V_4

0.1U/10V_4

DDPC_CTRL for HDMI port C
SDVO_CTRL for HDMI port B

If HDMI not support
HDA --> NC
VCC_HDA-->GND
Differential signal-->NC

M_RCOMP

R458 80.6/F_4R458 80.6/F_4

M_RCOMP#

R457 80.6/F_4R457 80.6/F_4

SM_VREF

SM_PWROK

R251 D3@10K/F_4R251 D3@10K/F_4
R248 10K/F_4R248 10K/F_4

INTEL FAE Suggest PD for Ext graphics

CLK_DREFCLK#
CLK_DREFCLK
CLK_DREFSSCLK#
CLK_DREFSSCLK

SM_RCOMP_VOH

C516

C516

2.2U/6V_6

2.2U/6V_6

SM_RCOMP_VOL

SM_RCOMP_VOL

C514

C514

2.2U/6V_6

2.2U/6V_6

+1.05V

R224

R224

1K/F_4

1K/F_4

R233

R233

511/F_4

511/F_4

<Checklist ver0.8>
If TSATN# is not used, then it must be terminated
with a 56-Ω pull-up resistor to VCCP.

<Pin out check issue>
Cantiga EDS 0.7 change Ball B12 to TSATN# from TSATN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH DMI

GMCH DMI

GMCH DMI

Date: Sheet of

Date: Sheet of

Date: Sheet of

+VDR_SUS

R250 10K/F_4R250 10K/F_4
R249 10K/F_4R249 10K/F_4

+VDR_SUS

HWPG_VDR <32,37>

R174 E@0_4R174 E@0_4
R182 E@0_4R182 E@0_4
R193 E@0_4R193 E@0_4
R183 E@0_4R183 E@0_4

C517

C517

R453

R453

0.01U/16V_4

0.01U/16V_4

3.01K/F_4

3.01K/F_4

R452

R452

C515

C515

1K/F_4

1K/F_4

0.01U/16V_4

0.01U/16V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

+VDR_SUS

R4541K/F_4 R4541K/F_4

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

1A

1A

640Tuesday, April 08, 2008

640Tuesday, April 08, 2008

640Tuesday, April 08, 2008

1A

5

4

3

2

1

U38C

IV&EV Dis/Enable setting

If LVDS no use,all signal can NC

L_BKLT_CTRL<19>

D D

INT_LVDS_BLON<19>

+3V

INT_LVDS_EDIDCLK<19>
INT_LVDS_EDIDDATA<19>

INT_LVDS_DIGON<19>

10/15: R178 Change to I@

INT_TXLCLKOUT-<18>

INT_TXLCLKOUT+<18>

INT_TXUCLKOUT-<18>

INT_TXUCLKOUT+<18>

INT_TXLOUT0-<18>

INT_TXLOUT1-<18>

INT_TXLOUT2-<18>

INT_TXLOUT0+<18>

INT_TXLOUT1+<18>

C C

INT_TXLOUT2+<18>

INT_TXUOUT0-<18>

INT_TXUOUT1-<18>
INT_TXUOUT2-<18>

INT_TXUOUT0+<18>

INT_TXUOUT1+<18>

INT_TXUOUT2+<18>

IV&EV Dis/Enable setting

Note :REV B: remove R475
& R471 short to GND

B B

INT_CRT_DDCCLK<18>
INT_CRT_DDCDAT<18>

INT_HSYNC<18>

HSYNC/VSYNC serial R place close to NB

A A

INT_VSYNC<18>

R203 I@10K_4R203 I@10K_4

R469 I@10K_4R469 I@10K_4

R178 I@2.37K/F_4R178 I@2.37K/F_4

INT_TXLCLKOUT­INT_TXLCLKOUT+
INT_TXUCLKOUT­INT_TXUCLKOUT+

INT_TXLOUT0­INT_TXLOUT1­INT_TXLOUT2-

INT_TXLOUT0+
INT_TXLOUT1+
INT_TXLOUT2+

INT_TXUOUT0­INT_TXUOUT1­INT_TXUOUT2-

INT_TXUOUT0+
INT_TXUOUT1+
INT_TXUOUT2+

R189 75_4R189 75_4
R195 75_4R195 75_4
R205 75_4R205 75_4

INT_CRT_BLU<18>

INT_CRT_GRN<18>

INT_CRT_RED<18>

R473 I@30.1_4R473 I@30.1_4

R474 I@30.1_4R474 I@30.1_4

CRTIREF pull down
for Teenah 1.3k ohm/F
for cantiga 1.02k ohm/F

L_CTRL_CLK

L_CTRL_DATA

INT_TV_COMP
INT_TV_Y/G
INT_TV_C/R

INT_CRT_BLU

INT_CRT_GRN

INT_CRT_RED

HSYNC_G
CRTIREF
VSYNC_G

U38C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

SP@CANTIGA_1p2

SP@CANTIGA_1p2

L<0.5" , If PCIE not support
still connect to +VCC_PEG

EXP_A_COMPX

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6

LVDS

LVDS

TV

TV

VGA

VGA

PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

T37
T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8

PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8

PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

C_PEG_TXN0
C_PEG_TXN1
C_PEG_TXN2
C_PEG_TXN3
C_PEG_TXN4
C_PEG_TXN5
C_PEG_TXN6
C_PEG_TXN7
C_PEG_TXN8
C_PEG_TXN9
C_PEG_TXN10
C_PEG_TXN11
C_PEG_TXN12
C_PEG_TXN13
C_PEG_TXN14
C_PEG_TXN15

C_PEG_TXP0
C_PEG_TXP1
C_PEG_TXP2
C_PEG_TXP3
C_PEG_TXP4
C_PEG_TXP5
C_PEG_TXP6
C_PEG_TXP7
C_PEG_TXP8
C_PEG_TXP9
C_PEG_TXP10
C_PEG_TXP11
C_PEG_TXP12
C_PEG_TXP13
C_PEG_TXP14
C_PEG_TXP15

R215 49.9/F_4R215 49.9/F_4

C189 .1U/10V_4C189 .1U/10V_4
C196 .1U/10V_4C196 .1U/10V_4
C197 .1U/10V_4C197 .1U/10V_4
C208 .1U/10V_4C208 .1U/10V_4
C218 E@.1U/10V_4C218 E@.1U/10V_4
C228 E@.1U/10V_4C228 E@.1U/10V_4
C233 E@.1U/10V_4C233 E@.1U/10V_4
C242 E@.1U/10V_4C242 E@.1U/10V_4
C249 E@.1U/10V_4C249 E@.1U/10V_4
C250 E@.1U/10V_4C250 E@.1U/10V_4
C252 E@.1U/10V_4C252 E@.1U/10V_4
C264 E@.1U/10V_4C264 E@.1U/10V_4
C269 E@.1U/10V_4C269 E@.1U/10V_4
C270 E@.1U/10V_4C270 E@.1U/10V_4
C274 E@.1U/10V_4C274 E@.1U/10V_4
C276 E@.1U/10V_4C276 E@.1U/10V_4

C188 .1U/10V_4C188 .1U/10V_4
C194 .1U/10V_4C194 .1U/10V_4
C195 .1U/10V_4C195 .1U/10V_4
C206 .1U/10V_4C206 .1U/10V_4
C220 E@.1U/10V_4C220 E@.1U/10V_4
C224 E@.1U/10V_4C224 E@.1U/10V_4
C230 E@.1U/10V_4C230 E@.1U/10V_4
C236 E@.1U/10V_4C236 E@.1U/10V_4
C245 E@.1U/10V_4C245 E@.1U/10V_4
C251 E@.1U/10V_4C251 E@.1U/10V_4
C254 E@.1U/10V_4C254 E@.1U/10V_4
C256 E@.1U/10V_4C256 E@.1U/10V_4
C259 E@.1U/10V_4C259 E@.1U/10V_4
C271 E@.1U/10V_4C271 E@.1U/10V_4
C275 E@.1U/10V_4C275 E@.1U/10V_4
C277 E@.1U/10V_4C277 E@.1U/10V_4

PEG_RXN[15:0] <18>

Can support reversal routing.If CFG9=1, PCI
Express is normal operation. If CFG9=0,
then PEG_TXP0 becomes PEG_TXP15, PEG_TXP1
becomes PEG_TXP14, PEG_TXP2 becomes
PEG_TXP13, etc. similarly for PEG_RXP[15:0]
and PEG_RXN[15:0]

PEG_RXP[15:0] <18>

Rev: B Change P/N

+1.05V

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

IV&EV Dis/Enable setting

<5/31>Montevina_Schematics_Checklist_Rev0_8
a)For TVOUT Disabled, TV_DCONSEL[1:0] Connect to GND. But
design guide Rev0.7 show NC.What is correct.
b)For CRT DAC Disable, CRT_DDC_CLK, CRT_DDC_DATA .
CRT_HSYNC, CRT_VSYNCThese signals should be connected to
GND. But design guide Rev0.7 show NC, Intel suggest follow
Design guide.

PEG_TXN[15:0] <18>

PEG_TXP[15:0] <18>

<check list>
For EV@
Connect to GND
CRT R/G/B
HSYNC/VSYNC
CRTIREF

R181 SP@0 & 1.02K/F_4R181 SP@0 & 1.02K/F_4

<check list>
For IV@
Connect to 150ohm
CRT R/G/B
Connect to 1.02Kohm
CRTIREF

CRTIREF

11/28: Change R181 1.02K ohm P/N

R472 E@0_4R472 E@0_4

R468 E@0_4R468 E@0_4

R186 SP@150_4R186 SP@150_4

R190 SP@150_4R190 SP@150_4

R197 SP@150_4R197 SP@150_4

HSYNC_G

VSYNC_G

INT_CRT_BLU

INT_CRT_GRN

INT_CRT_RED

10/15: Change to SP@

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH VGA

GMCH VGA

GMCH VGA

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT :

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

of

of

of

740Tuesday, April 08, 2008

740Tuesday, April 08, 2008

740Tuesday, April 08, 2008

1

1A

1A

1A

5

4

3

2

1

M_A_DQ[63:0]<16,17>

D D

C C

B B

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

U38D

U38D

AJ38
AJ41
AN38

AM38

AJ36

AJ40
AM44
AM42
AN43
AN44

AU40

AT38

AN41

AN39

AU44

AU42

AV39

AY44

BA40

BD43

AV41

AY43

BB41

BC40

AY37

BD38

AV37

AT36

AY38

BB38

AV36

AW36

BD13
AU11
BC11

BA12
AU13

AV13
BD12
BC12

BB9
BA9

AU10

AV9

BA11

BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6

AT5
AN10
AM11

AM5

AJ9

AJ8
AN12
AM13

AJ11
AJ12

SP@CANTIGA_1p2

SP@CANTIGA_1p2

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

AM37

SA_DM_0

AT41

SA_DM_1

AY41

SA_DM_2

AU39

SA_DM_3

BB12

SA_DM_4

AY6

SA_DM_5

AT7

SA_DM_6

AJ5

SA_DM_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_10

SA_MA_11

SA_MA_12

SA_MA_13

SA_MA_14

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6

M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14

M_A_BS0 <16,17>
M_A_BS1 <16,17>
M_A_BS2 <16,17>

M_A_RAS# <16,17>
M_A_CAS# <16,17>
M_A_WE# <16,17>

M_A_DM[7:0] <16,17>

M_A_DQS[7:0] <16,17>

M_A_DQS#[7:0] <16,17>

M_A_A[14:0] <16,17>

M_B_DQ[63:0]<16,17>

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

U38E

U38E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

SP@CANTIGA_1p2

SP@CANTIGA_1p2

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

AM47

SB_DM_0

AY47

SB_DM_1

BD40

SB_DM_2

BF35

SB_DM_3

BG11

SB_DM_4

BA3

SB_DM_5

AP1

SB_DM_6

AK2

SB_DM_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_10

SB_MA_11

SB_MA_12

SB_MA_13

SB_MA_14

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6

M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14

M_B_BS0 <16,17>
M_B_BS1 <16,17>
M_B_BS2 <16,17>

M_B_RAS# <16,17>
M_B_CAS# <16,17>
M_B_WE# <16,17>

M_B_DM[7:0] <16,17>

M_B_DQS[7:0] <16,17>

M_B_DQS#[7:0] <16,17>

M_B_A[14:0] <16,17>

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH DDRII

GMCH DDRII

GMCH DDRII

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT :

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

840Tuesday, April 08, 2008

840Tuesday, April 08, 2008

840Tuesday, April 08, 2008

1

1A

1A

1A

of

of

of

5

Power consumption reference to Intel
644135 Cantiga chipset EDS Volume1.
Section 10

GM TDP 10.5~12W
GS TDP 7~8W
PM TDP 7W

D D

U38G

+VDR_SUS

+

+

C244

C519

C519

22U/6V_8

22U/6V_8

Place on the edga

VCC_SM(1.8V)
DDR2(800M)
3000mA_S0 , 1mA_S3
DDR2(667M) : 2600mA_S0
DDR3(1067M) : 4140mA_S0

C C

B B

C244

C521

C521

0.1U/10V_4

0.1U/10V_4

22U/6V_8

22U/6V_8

1.05V
Graphics core
VCC_AXG
VCC_AXG_NCTF

6326.84mA

Voltage regulator is
shared between the
Graphics Core Rail,
VCCA_HPLL, VCCA_MPLL,
VCCA_PEG_PLLVCCD_PEG_PLL,
VCCA_SM_CK, VCCA_DPLLA,
VCCA_DPLLB, VCCD_HPLL,
VCCA_SM, VCC_AXF

C518

C518

330U/2.5V_7

330U/2.5V_7

+1.05V_AXG

R242 I@10/F_4R242 I@10/F_4
R238 I@10/F_4R238 I@10/F_4

+1.05V_AXG

AP33
AN33
BH32

BG32

BF32
BD32
BC32
BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31

BG31

BF31

BG30

BH29

BG29

BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16

BB21
AW16
AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21
AG21

AE21

AC21

AA21

AH20

AF20

AE20

AC20

AB20

AA20

AM15

AL15

AE15

AJ15

AH15
AG15

AF15

AB15

AA15

AN14
AM14

AJ14

AH14

Y26

Y24

Y21

T17
T16

Y15
V15
U15

U14
T14

U38G

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC SMVCC GFX

VCC SMVCC GFX

4

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22

POWER

POWER

VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

+1.05V_AXG

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

1.8V
Internal connect to power

VCC_SM_LF1

AV44

VCC_SM_LF2

BA37

VCC_SM_LF3

AM40

VCC_SM_LF4

AV21

VCC_SM_LF5

AY5

VCC_SM_LF6

AM10

VCC_SM_LF7

BB13

C268

C268

.1U/10V_4

.1U/10V_4

3

Intel check list(Rev 0.8)
270U*1 near to power(+V1.05M).
270U*2 near to NB
Intel CRB(Rev 0.7)

+1.05V

C217

C217

I@10U/10V_8

I@10U/10V_8

C258

C258

1U/6V_4

1U/6V_4

C231

C231

.1U/10V_4

.1U/10V_4

270U*3 near to power(+V1.05M).
270U*1 near to NB
ESR=12m ohm

C225

C225

.22U/6V_4

.22U/6V_4

C201

C201

I@22U/6V_8

I@22U/6V_8

Intel check list(Rev 0.8)
No description for VCC_SM bulk CAP
Intel CRB(Rev 0.7)
330U*1 Reserve near to power
330U*1 near to NB

+1.05V +1.05V_AXG

R227 I@0_8R227 I@0_8

R228 I@0_8R228 I@0_8

C200

C200

I@.47U/6V_4

I@.47U/6V_4

C238

C238

.47U/6V_4

.47U/6V_4

SP@:INT 上 1 U
EXT

上

0 ohm

C237

C237

SP@0_6

SP@0_6

C266

C266

1U/6V_4

1U/6V_4

+1.05V_AXG

+

+

C191

C191

I@330U/2.5V_7343

I@330U/2.5V_7343

IV&EV Dis/Enable setting

Design guide(Table 72)
For INT VGA diasble.VCC_AXG power can connect to GND

+

+

C192

C192

I@330U/2.5V_7343

I@330U/2.5V_7343

Place close to the GMCH Cavity Capacitors

Intel check list(Rev 0.8)
220U*2 near to NB(ESR=15m ohm)
Intel CRB(Rev 0.7)
270U*4 near to power(+V1.05S).
330U*2 near to NB

C239

C239

.1U/10V_4

.1U/10V_4

C255

C255

.22U/6V_4

.22U/6V_4

C253

C253

.22U/6V_4

.22U/6V_4

C226

C226

.22U/6V_4

.22U/6V_4

C210

C210

22U/6V_8

22U/6V_8

C247

C247

I@.1U/10V_4

I@.1U/10V_4

2

+

+

C524

C524

330U/2.5V_7

330U/2.5V_7

Place close to
the GMCH

C203

C203

I@.1U/10V_4

I@.1U/10V_4

VCC
VCC_NCTF

1210.34mA_EV

1930.4mA_IV
ME Engine

508.12mA
Total Max=2438.52mA

AG34
AC34
AB34
AA34

Y34
V34

U34
AM33
AK33
AJ33
AG33
AF33

AE33
AC33
AA33

Y33

W33

V33

U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23

T32

U38F

U38F

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

VCC_35

SP@CANTIGA_1p2

SP@CANTIGA_1p2

VCC CORE

VCC CORE

POWER

POWER

1

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31

VCC NCTF

VCC NCTF

VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+1.05V

1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm

A A

and VSS_AXG_SENSE PD with 10ohm for Intel suggest

5

SP@CANTIGA_1p2

SP@CANTIGA_1p2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH VCC,NCTF

GMCH VCC,NCTF

GMCH VCC,NCTF

Date: Sheet

Date: Sheet

4

3

2

Date: Sheet

PROJECT :

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

940Tuesday, April 08, 2008

940Tuesday, April 08, 2008

1

940Tuesday, April 08, 2008

1A

1A

1A

of

of

of

5

Power consumption reference to Intel
644135 Cantiga chipset EDS Volume1.
Section 10

1210 10UH, 10%

0.45A DCR_max = 0.39

D D

C C

B B

A A

L48 I@10UH_8L48 I@10UH_8

+1.05V

SP@:INT

上

EXT

上

L44 I@10UH_8L44 I@10UH_8

+1.05V

R245 0_6R245 0_6

+1.05V

+3V

CRB no 10U
Check list need min 10U~100U for VCCA_TV_DAC

1.05V
50mA

L47 I@BLM18PG181SN1D_6L47 I@BLM18PG181SN1D_6

C549

C549

I@10U/6.3V_8

I@10U/6.3V_8

+1.5V

1.5V
50mA

Design guide table 72
VCCD_TVDAC always keep 0.1U/0.022U/10U to +1.5V

+1.5V

+1.05V

R244 0_6R244 0_6

1.05V
24mA

+1.05VM_MCH_PLL2

L29 BLM18PG181SN1D_6L29 BLM18PG181SN1D_6

+1.05VM_MPLL_RC

C227

C227

22U/6V_8

22U/6V_8

FB 180@100 MHz, 25% 1.5A
DCR_max=90 m

3.3V

24.15mA for VCCA_TVA_DAC

39.48mA for VCCA_TVB_DAC

24.15mA for VCCA_TVC_DAC
Total 87.78mA

R486 I@0_6R486 I@0_6

R179 0_6R179 0_6

L49 I@BLM18PG181SN1D_6L49 I@BLM18PG181SN1D_6

FB 180@100 MHz, 25% 1.5A

C548

C548

DCR_max=90 m

10U/6.3V_8

10U/6.3V_8

CRB no 10U
Check list need min 10U~100U
for VCCA_QDAC

L43 BLM18PG181SN1D_6L43 BLM18PG181SN1D_6

+1.05VM_PEGPLL_RC

C527

C527

10U/10V_8

10U/10V_8

ESR=60m ohm

5

+

+

C550

C550

220U/2.5V_7343

220U/2.5V_7343

ESR=15 m

0.1U
0 ohm

C229

C229

4.7U/10V_6

4.7U/10V_6

1210 0.1uH, 20%, 1A,
DCR_max=0.078Ω

R234 0.5/F_6R234 0.5/F_6

SP@:INT
EXT

1.5V

48.363mA for CRT
5mA for TV

IV&EV Dis/Enable setting

C546

C546

SP@0_4

SP@0_4

1210 10UH, 10%

0.45A DCR_max = 0.39

+

+

C535

C535

220U/2.5V_7343

220U/2.5V_7343

ESR=15 m

C223

C223

.1U/10V_4

.1U/10V_4

1.05V
DDR2-800
26mA

IV&EV Dis/Enable setting

上

0.1U

上

0 ohm

1.5V

58.67mA

FB 220 @100 MHz, 25%, 2A

R463 1/F_4R463 1/F_4

+3V

1.05V

139.2mA

C221

C221

.1U/10V_4

.1U/10V_4

+1.05V

C544

C544

I@.1U/10V_4

I@.1U/10V_4

C185

C185

.1U/10V_4

.1U/10V_4

C184

C184

I@.1U/10V_4

I@.1U/10V_4

R480 I@0_6R480 I@0_6

R476 I@0_6R476 I@0_6

1.05V

64.8mA for A/B

Design guide table 72
VCCA_DPLLA/B always keep to +1.05V(If no use IV dynamic core power)

C533

C533

SP@.1U/10V_4

SP@.1U/10V_4

1.05V
DDR2-800
720mA

R241 0_6R241 0_6

C541

C541

SP@0_4

SP@0_4

C175

C175

SP@0_4

SP@0_4

C183

C183

.01U/16V_4

.01U/16V_4

C181

C181

SP@0_4

SP@0_4

SP@:INT
EXT

Design guide Table 72

1.5V
414uA

3.9 nH, 0.2 nH, 1A
, DCR_max=32 m

+1.05V

SP@:INT
EXT

上

0.01U

上

0 ohm

C529

C529

.1U/10V_4

.1U/10V_4

4

+3V_A_CRT_DAC

C542

C542

I@.1U/10V_4

I@.1U/10V_4

+3V_A_DAC_BG

C543

C543

I@.1U/10V_4

I@.1U/10V_4

IV&EV Dis/Enable setting

R462 0_8R462 0_8

+1.5V

R240 0_6R240 0_6

CRB : 0 ohm
Check list : 2.2nH

上

0.01U

上

0 ohm

IV&EV Dis/Enable setting

+1.8V

1.8V

60.31mA

4

C540

C540

SP@0_4

SP@0_4

SP@:INT 上 0.01U
EXT

上

0 ohm

C179

C179

SP@0_4

SP@0_4

3.3V

2.68mA

+1.05VM_DPLLA

+1.05VM_DPLLB

+1.05VM_HPLL

+1.05VM_MPLL

+1.8VSUS_TXLVDS

C538

C528

C528

.1U/10V_4

.1U/10V_4

C248

C248

22U/6V_8

22U/6V_8

+1.05VM_A_SM_CK

C241

C241

*2.2U/10V_6

*2.2U/10V_6

C234

C234

.1U/10V_4

.1U/10V_4

R176 I@0_6R176 I@0_6

C538

I@1000P/50V_4

I@1000P/50V_4

+VCCA_PEG_BG

+1.05VM_PEGPLL

VCCA_PEG_PLL
+1.25V for Teenah use(100mA)

C240

C240

C246

C246

1U/6V_4

1U/6V_4

4.7U/10V_6

4.7U/10V_6

C243

C243

C235

C235

.1U/10V_4

.1U/10V_4

22U/6V_8

22U/6V_8

+3V_TV_DAC

+VCC_HDA

+1.5V_TVDAC

+1.5V_QDAC

+1.05VM_MCH_PLL2

+1.05VM_PEGPLL

C531

C531

.1U/10V_4

.1U/10V_4

+1.8VSUS_DLVDS

上

1 U

SP@:INT
EXT

上

0 ohm

1.8V

13.2mA

+1.05VM_A_SM

VCCD_QDAC share to TV and CRT

1.05V

157.2mA

1.05V
50mA

C187

C187

SP@0_4

SP@0_4

3.3V
73mA

AD48

AR20

AN20
AR17

AN17

AR16

AN28

AN25
AN24
AM28
AM26
AM25

AM24

AM23

AA48

AP20

AP17

AT16

AP16

AP28

AP25

AL25

AL24

AL23

AA47

AD1

AE1

M25

AF1

M38

3

U38H

U38H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

VCCD_TVDAC

L28

VCCD_QDAC

VCCD_HPLL

VCCD_PEG_PLL

VCCD_LVDS_1

L37

VCCD_LVDS_2

SP@CANTIGA_1p2

SP@CANTIGA_1p2

3

U13

VTT_1

T13

VTT_2

U12

VTT_3

T12

VTT_4

U11

VTT_5

T11

VTT_6

U10

VTT_7

T10

VTT_8

U9

CRTPLLA PEGA SM

CRTPLLA PEGA SM

A LVDS

A LVDS

POWER

POWER

A CK

A CK

TV

TV

HDA

HDA

D TV/CRT

D TV/CRT

LVDS

LVDS

Power Rail Differences between
the Teenah and Cantiga Chipset Family

Power Net Name

VCC_AXG_#
VCC_AXG_NCTF_#

VCCA_PEG_BG

VCCA_DPLLA

VCCA_DPLLB

VCCA_SM_#

VCCA_HPLL

VCCA_MPLL

VCCA_SM_CK_#

VCCA_PEG_PLL

VCC_AXF_#

VCCD_HPLL

VCCD_PEG_PLL

VTT_9

T9

VTT_10

U8

VTT_11

T8

VTT_12

U7

VTT_13

T7

VTT_14

U6

VTT_15

VTT

VTT

T6

VTT_16

U5

VTT_17

T5

VTT_18

V3

VTT_19

U3

VTT_20

V2

VTT_21

U2

VTT_22

T2

VTT_23

V1

VTT_24

U1

VTT_25

B22

VCC_AXF_1

B21

VCC_AXF_2

A21

VCC_AXF_3

AXF

AXF

BF21

VCC_SM_CK_1

BH20

VCC_SM_CK_2

BG20

VCC_SM_CK_3

BF20

VCC_SM_CK_4

SM CK

SM CK

DMI

DMI

K47

VCC_TX_LVDS

C35

VCC_HV_1

B35

VCC_HV_2

A35

VCC_HV_3

HV

HV

V48

VCC_PEG_1

U48

VCC_PEG_2

V47

VCC_PEG_3

U47

VCC_PEG_4

U46

VCC_PEG_5

PEG

PEG

AH48

VCC_DMI_1

AF48

VCC_DMI_2

AH47

VCC_DMI_3

AG47

VCC_DMI_4

A8

VTTLF1

L1

VTTLF2

AB2

VTTLF3

VTTLF

VTTLF

Cantiga(V)

1.05V 1.25V 6326.84mA

1.5V

1.05V

1.05V

1.05V

1.05V

1.05V

1.05V

1.05V

1.05V

1.05V

1.05V

Tennah(V)

3.3V

1.25V

1.25V

1.25V

1.25V

1.25V

1.25V

1.25V

1.25V

1.25V

1.25V

C198

C198

.47U/6V_4

.47U/6V_4

+1.05VM_AXF

+1.8VSUS_VCC_SM_CK

+1.8VSUS_TXLVDS

3.3V

105.3mA

C211

C211

.47U/6V_4

.47U/6V_4

Tennah Current

Cantiga use

400uA

100mA

100mA

1065mA

50mA

150mA

35mA

100mA

495mA

250mA

100mA

2

C193

C193

2.2U/6V_6

2.2U/6V_6

Check list : 0.1UH
CRB : 0 ohm
1210 0.1 ?H, 20% 1A
DCR max = 78 m

C545

C545

1U/6V_4

1U/6V_4

C522

C522

.1U/10V_4

.1U/10V_4

SP@:INT
EXT

C534

C534

.47U/6V_4

.47U/6V_4

2

C199

C199

4.7U/10V_6

4.7U/10V_6

C547

C547

*10U/10V_8

*10U/10V_8

ESR = 60 m

R4551/F_4 R4551/F_4

IV&EV Dis/Enable setting

上

1000 P

上

0 ohm

+3V

C182

C182

.1U/10V_4

.1U/10V_4

C526

C526

.1U/10V_4

.1U/10V_4

C539

C539

.47U/6V_4

.47U/6V_4

+

+

C190

C190

C180

C180

4.7U/10V_6

4.7U/10V_6

330U/2.5V_7

330U/2.5V_7

ESR= 12m ohm

L46 1UH_8L46 1UH_8

1.05V

321.35mA

+1.8VSUS_SMCK_RC

C537

C537

SP@1000P/50V_4

SP@1000P/50V_4

R489 10_4R489 10_4

C530

C530

4.7U/10V_6

4.7U/10V_6

1

External Graphics
(GMCH Integrated Graphics Disable)

VCCSYNC_CRT

VCCA_CRT_DAC

VCCD_LVDS

VCC_TX_LVDS

VCCA_LVDS

VCCA_TVDAC

VCCD_QDAC

+1.05V

1.05V
FSB-1067
852mA

+1.05V

0805 1UH , Rdc = 0.14 - 0.26.
Max rated current = 220 mA

L42 1UH_8L42 1UH_8

C520 10U/10V_8C520 10U/10V_8

0805 100 nH, DCR=160 m

L45 I@0.1UH_1.5L45 I@0.1UH_1.5

C536

C536

I@22U/6V_8

I@22U/6V_8

+1.05V_SD

+1.05V

+

+

C532

C532

C525

C525

220U/6_7343

220U/6_7343

22U/6V_8

22U/6V_8

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH POWER

GMCH POWER

GMCH POWER

Date: Sheet

Date: Sheet

Date: Sheet

VCCA_DAC_BG

VCC_AXG

VCC_AXG_NCTF

+VDR_SUS

1.8V
DDR2-800
124mA

1.8V

118.8mA

D38 BAT54D38 BAT54

21

1.05V
1782mA

1.05V
Internal connect to power

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

+1.8V

+1.05V

ESL=2.4 nH
ESR =15 m

1.05V
456mA

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

10 40Tuesday, April 08, 2008

10 40Tuesday, April 08, 2008

10 40Tuesday, April 08, 2008

of

of

of

1A

1A

1A

5

U38I

U38I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

D D

C C

B B

A A

5

AD47
AB47

G47
BD46
BA46
AY46
AV46
AR46

AM46

BF44
AH44
AD44
AA44

M44

BC43
AV43
AU43

AM43

BG42

AY42
AT42
AN42

AJ42

AE42

BD41
AU41

AM41

AH41
AD41
AA41

M41

G41

BG40

BB40
AV40
AN40

AT39

AM39

AJ39

AE39

BH38
BC38
BA38
AU38
AH38
AD38
AA38

BF37
BB37

AW37

AT37
AN37

AJ37

BG36

BD36
AK15
AU36

Y47
T47
N47
L47

V46
R46
P46
H46
F46

Y44
U44
T44

F44

C43

N42
L42

Y41
U41
T41

B41

H40
E40

N39
L39
B39

Y38
U38
T38

F38
C38

H37
C37

J43

J38

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

SP@CANTIGA_1p2

SP@CANTIGA_1p2

VSS

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23

4

3

U38J

U38J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

M17

H17
C17

BA16

AU16
AN16

N16
K16
G16

E16
BG15
AC15

W15

A15
BG14
AA14

C14
BG13
BC13
BA13

AN13

AJ13

AE13

N13

L13
G13
E13

BF12
AV12
AT12

AM12

AA12

J12
A12

BD11
BB11
AY11
AN11
AH11

Y11
N11
G11
C11

BG10
AV10
AT10

AJ10
AE10
AA10

M10

BF9
BC9
AN9
AM9
AD9

G9
B9

BH8

BB8

AV8

AT8

3

VSS

VSS

VSS_230
VSS_231
VSS_232
VSS_233

VSS_235

VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

SP@CANTIGA_1p2

SP@CANTIGA_1p2

VSS NCTF

VSS NCTF

VSS SCB

VSS SCB

NC

NC

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354
VSS_355

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4

VSS_SCB_6

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43

2

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29
AJ6

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1

A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
A47

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH VSS

GMCH VSS

GMCH VSS

Date: Sheet

Date: Sheet

2

Date: Sheet

PROJECT :

1

1

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

of

of

of

11 40Tuesday, April 08, 2008

11 40Tuesday, April 08, 2008

11 40Tuesday, April 08, 2008

1A

1A

1A

5

C410 15P/50V_4C410 15P/50V_4

C409 15P/50V_4C409 15P/50V_4

+VCCRTC

D D

24.9 Ohm pull up to 1.5V
for GLAN_COMPI/O is
required, no matter
intel LAN is used or
not.

Internal pull-down
resistors that are
always enabled

ACZ_SDIN0<25>
ACZ_SDIN1<25>

C C

OC Pin need PU, ZS2 PU at LED side.

SATA_LED#<31>

SATA_RXN0<24>
SATA_RXP0<24>

SATA_TXN0<24>
SATA_TXP0<24>

SATA_RXN1<24>
SATA_RXP1<24>

SATA_TXN1<24>
SATA_TXP1<24>

23

Y9

Y9

32.768KHZ

32.768KHZ

4 1

R360 1M/F_6R360 1M/F_6

R393 332K/F_4R393 332K/F_4

Internal VRM enabled for
VccSus1_05, VccSus1_5,
VccCL1_5, VccLAN1_05 and
VccCL1_05.

+3V_S5

R376 10K_4R376 10K_4

R351 24.9/F_4R351 24.9/F_4

+1.5V

T38T38
T40T40

11/8 REV:B Y9 change footprint
11/26 REV:B C410 &C409 change to 15p
97/03/25 REV: C Change to NPO

R368

R368

CLK_32KX1

10M_6

10M_6

CLK_32KX2

RTC_RST#
SRTC_RST#

SM_INTRUDER#

ICH_INTVRMEN

ICH_GPIO56

HDA_BIT_CLK_R
HDA_SYNC_R

HDA_RST#_R

HDA_SDIN2
HDA_SDIN3

HDA_SDOUT_R

4

U35A

U35A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD0

D12

LAN_TXD1

E13

LAN_TXD2

B10

GLAN_DOCK#/GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9M REV 1.0

ICH9M REV 1.0

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

RCIN#

STPCLK#

THRMTRIP#

SATA4RXN

IHDA

IHDA

SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATA_CLKN
SATA_CLKP

SATA

SATA

SATARBIAS#

SATARBIAS

INTR

SMI#

NMI

TP8

K5
K4
L6
K2

K3

J3
J1

N7
AJ27

AJ25
AE23

AJ26

AD22

AF25

AE22
AG25
L3

AF23
AF24

AH27

AG26

AG27

AH11
AJ11
AG12
AF12

AH9
AJ9
AE10
AF10

AH18
AJ18

AJ7
AH7

T44T44
T65T65

H_DPRSTP#_R
H_DPSLP#_R

H_FERR#_R

H_SMI#_R

H_THERMTRIP_R

SATA_RBIAS_PN

3

LDRQ0/1# : Internal PU

R326 8.2K_4R326 8.2K_4

R435 0_4R435 0_4
R312 0_4R312 0_4

R432 56_4R432 56_4

R343 10K_4R343 10K_4

R299 0_4R299 0_4

R311 54.9/F_4R311 54.9/F_4

T39T39

SATABIAS L<0.5"

R426

R426

24.9/F_4

24.9/F_4

+3V

+3V

H_THERMTRIP_RR

LAD0 <23,32>
LAD1 <23,32>
LAD2 <23,32>
LAD3 <23,32>

LFRAME# <23,32>

GATEA20 <32>
H_A20M# <3>

H_PWRGD <3>

H_IGNNE# <3>

H_INIT# <3>
H_INTR <3>

RCIN# <32>
H_NMI <3>
H_SMI# <3>

H_STPCLK# <3>

SATA_RXN4 <24>
SATA_RXP4 <24>
SATA_TXN4 <24>
SATA_TXP4 <24>

CLK_PCIE_SATA# <2>

CLK_PCIE_SATA <2>

2

+1.05V

R298

R298

R434

R434

*56_4

*56_4

R297 56.2/F_4R297 56.2/F_4

R296 *0_4R296 *0_4

No use Thermal trip SB side still PU 56ohm.(Serial R use 0ohm)
Use Thermal trip can share PU for CPU and SB side(And Serial R use 54.9 ohm)
PU L<2"

Layout note:
DPRSTP# , Daisy Chain

*56_4

*56_4

(SB>Power>NB>CPU)

ICH_DPRSTP# <3,6,35>
H_DPSLP# <3>

+1.05V

PM_THRMTRIP# <3,6>

+1.05V

R433

R433

56_4

56_4

H_FERR# <3>

1

HD Audio

R513 E@33_4R513 E@33_4
R279 I@33_4R279 I@33_4

B B

HDA_SDOUT_R

Weak integrated PD on the HDA_SDOUT pin.

HDA_SYNC_R

Weak integrated PD on the HDA_SYNC pins

R295 33_4R295 33_4
R294 33_4R294 33_4

R514 E@33_4R514 E@33_4
R427 I@33_4R427 I@33_4
R429 33_4R429 33_4
R428 33_4R428 33_4

MXM_SDOUT_HDMI <18>
HDA_SDOUT_HDMI <6>
ACZ_SDOUT_MDC <25>
ACZ_SDOUT_AUDIO <25>

C344

C344

*10P/50V_4

*10P/50V_4

MXM_SYNC_HDMI <18>
HDA_SYNC_HDMI <6>
ACZ_SYNC_MDC <25>

ACZ_SYNC_AUDIO <25> ACZ_RST#_AUDIO <25>

C479

C479

*10P/50V_4

*10P/50V_4

HDA_BIT_CLK_R

24.000 MHz is output from the ICH9M.

HDA_RST#_R

HDA_SDIN3
HDA_SDIN2

R517 E@33_4R517 E@33_4
R285 I@33_4R285 I@33_4
R282 33_4R282 33_4
R309 33_4R309 33_4

R516 E@33_4R516 E@33_4
R308 I@33_4R308 I@33_4
R307 33_4R307 33_4
R306 33_4R306 33_4

R515 E@0_4R515 E@0_4
R289 I@0_4R289 I@0_4

South Bridge Strap Pin (1/3)

Pin Name

HDA_DOCK_EN/
GPIO33

A A

SATALED#

TP3

HDA_SDOUT

Strap description

Flash Descriptor Security
Override Strap

PCI Express Lane Reversal
(Lanes 1-4)

XOR Chain Entrance

XOR Chain Entrance /PCI Express*
Port Config 1 bit 1(Port 1-4)

5

Sampled

PWROK

PWROK

PWROK

PWROK

Configuration PU/PD

0 = The Flash Descriptor Security will be overridden.
1 = The security measures defined
in the Flash Descriptor will be in effect

Internal PU

ICH_TP3

HDA_SDOUT

0

0

0

11

4

RSVD

Enter XOR Chain

1

Normal opration(Default)

01

Set PCIE port config bit 1

Description

10/16: R517 Change to E@

C354

C354

*10P/50V_4

*10P/50V_4

C402

C402

*10P/50V_4

*10P/50V_4

MXM_RST#_HDMI <18>
HDA_RST#_HDMI <6>
ACZ_RST#_MDC <25>

MXM_SDIN_HDMI <18>
HDA_SDIN_HDMI <6>

This strap should only be enabled in manufacturing
environments using an external pull-up resistor.

ICH_TP3<14>

HDA_SDOUT_R

ICH_TP3

3

MXM_BIT_CLK_HDMI <18>
HDA_BIT_CLK_HDMI <6>
BIT_CLK_MDC <25>
BIT_CLK_AUDIO <25>

C330

C330

*10P/50V_4

*10P/50V_4

R406 *1K_4R406 *1K_4

R310 *1K_4R310 *1K_4

+3V

RTC

+3VPCU

VCCRTC_1

20MIL

R272

R272

1K_4

1K_4

VCCRTC_2

20MIL

12

D19 CH500HD19 CH500H

D20 CH500HD20 CH500H

1 3

CN26

CN26

RTC_CONN

RTC_CONN

2

2

RTC_N01

Q28

Q28

MMBT3904

MMBT3904

RTC_N03

+VCCRTC

20MIL

1

C391

C391

1U/6V_4

1U/6V_4

C458

C458

1U/6V_4

1U/6V_4

SRTC_RST#

12

RTC_RST#

12

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

12 40Tuesday, April 08, 2008

12 40Tuesday, April 08, 2008

12 40Tuesday, April 08, 2008

R440 20K_6R440 20K_6

C314

C314

1U/10V_4

1U/10V_4

R439 20K_6R439 20K_6

R271 16K_6R271 16K_6

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

+5VPCU

R270

R270

68.1K/F_4

68.1K/F_4

R268

R268

150K/F_6

150K/F_6

ICH9M HOST

ICH9M HOST

ICH9M HOST

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

G8

G8

*SHORT_ PAD

*SHORT_ PAD

G7

G7

*SHORT_ PAD

*SHORT_ PAD

of

of

of

1A

1A

1A

5

AD[0..31]<27>

D D

PLT_RST-R#

INTA#<27>

+3V

2

1

3 5

4

U30

U30

TC7SH08FU

TC7SH08FU

C C

B B

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

INTA#
INTB#
INTC#
INTD#

C408

C408

.1U/50V_6

.1U/50V_6

R357

R357

100K_6

100K_6

D11

E12

E10

G11

F11

F10

D10

U35B

U35B

AD0

C8

PCI

PCI

AD1

D9

AD2
AD3

E9

AD4

C9

AD5
AD6

B7

AD7

C7

AD8

C5

AD9
AD10

F8

AD11
AD12

E7

AD13

A3

AD14

D2

AD15
AD16

D5

AD17
AD18

B3

AD19

F7

AD20

C3

AD21

F3

AD22

F4

AD23

C1

AD24

G7

AD25

H7

AD26

D1

AD27

G5

AD28

H6

AD29

G1

AD30

H3

AD31

Interrupt I/F

Interrupt I/F

J5

PIRQA#

E1

PIRQB#

J6

PIRQC#
PIRQD#C4PIRQH#/GPIO5

ICH9M REV 1.0

ICH9M REV 1.0

PLTRST# <18,21,23,28,29,32>

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4

F1
G4
B6
A7
F13
F12
E6
F6

D8
B4
D6
A5

D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

C14
D4
R2

H4
K6
F2
G2

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
LOCK#
SERR#
STOP#
TRDY#
FRAME#

PLT_RST-R#

PCI_PME#

INTE#
INTF#
INTG#
INTH#

South Bridge Strap Pin (2/3)

Pin Name Strap description

HDA_SYNC

GNT2# / GPIO53

GNT1# / GPIO51

GNT3# / GPIO55

A A

SPI_MOSI

GNT0#

SPI_CS1# /
GPIO58 / CLGPIO6

PCI Express Port
Config 1 bit 0 (Port 1-4)

PCI Express Port
Config 2 bit 2 (Port 5-6)

ESI Strap(Server Only)

Top-Block Swap Override

Integrated TPM Enable

Boot BIOS Selection 0

5

Sampled

PWROK

PWROK

PWROK

PWROK

CLPWROK

PWROK

CLPWROKBoot BIOS Selection 1

0 = Default
1 = Setting bit 0

0 = Setting bit 2
1 = Default

0 = DMI for ESI-compatible
1 = Default

0 = "top-block swap" mode
1 = Default

0 = INT TPM disable(Default)
1 = INT TPM enable

4

REQ0# <27>
GNT0# <27>

T59T59

T46T46

GNT3#

CBE0# <27>
CBE1# <27>
CBE2# <27>

CBE3# <27>

IRDY# <27>
PAR <27>
PCIRST# <23,27>
DEVSEL# <27>

STOP# <27>
TRDY# <27>

R367 0_4R367 0_4

FRAME# <27>

PLT_RST# <6>

PCLK_ICH <2>

PCI_PME# <27>

PME# internal PU 18K~42K

TM & AS

LOW COST

Y

N

TPM SPI FLASH

U31

SPI_MOSO

R370 SP@15_4R370 SP@15_4

SPI_MOSO_R

SPI_MOSI_R

SPI_CLK_R

SPI_CS0#_R

Configuration PU/PD

GNT3#

SPI_MOSI_H

Boot Location

SPI_CS#1PCI_GNT#0

SPI(Default)

10

PCI

01

LPC

11

4

GNT0#

SPI_CS1#

U31

2

SO

5

SI

6

SCK

1

CE

SP@W25X16VSSIG

SP@W25X16VSSIG

R347 *1K_4R347 *1K_4

R329 TPM@10K_4R329 TPM@10K_4

R344 *1K_4R344 *1K_4

R340 *1K_4R340 *1K_4

HOLD

VDD

WP

VSS

NEW CARD

CARD READER

Wireless

+3V_S5

8

7

3

4

+3V_S5

TV CARD

C411

C411

SP@.1U/16V_4

SP@.1U/16V_4

3

PCIE_RXN1<29>

PCIE_RXN2<23>
PCIE_RXP2<23>
PCIE_TXN2<23>
PCIE_TXP2<23>

JMB_RXN<28>
JMB_RXP<28>
JMB_TXN<28>
JMB_TXP<28>

GLAN_RXN<21>
GLAN_RXP<21>
GLAN_TXN<21>
GLAN_TXP<21>

PCIE_RXP1<29>

PCIE_TXN1<29>
PCIE_TXP1<29>

PCIE_RXN4<23>
PCIE_RXP4<23>

PCIE_TXN4<23>
PCIE_TXP4<23>

SPI_CLK_R
SPI_CS0#_R

SPI_MOSI_R

C378 .1U/10V_4C378 .1U/10V_4
C376 .1U/10V_4C376 .1U/10V_4

C385 .1U/10V_4C385 .1U/10V_4
C387 .1U/10V_4C387 .1U/10V_4

C386 .1U/10V_4C386 .1U/10V_4
C392 .1U/10V_4C392 .1U/10V_4

C393 .1U/10V_4C393 .1U/10V_4
C397 .1U/10V_4C397 .1U/10V_4

C464 .1U/10V_4C464 .1U/10V_4
C463 .1U/10V_4C463 .1U/10V_4

R369 SP@15_4R369 SP@15_4
R350 SP@15_4R350 SP@15_4

R348 SP@15_4R348 SP@15_4

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN3_C
PCIE_TXP3_C

PCIE_TXN4_C
PCIE_TXP4_C

GLAN_TXN_SB
GLAN_TXP_SB

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MOSO

USBOC#0
USBOC#1
USBOC#2
USBOC#3
USBOC#4
USBOC#5
USBOC#6
USBOC#7
USBOC#8
USBOC#9
USBOC#10
USBOC#11

SB_USBBIAS

R301

R301

22.6/F_4

22.6/F_4

L<0.5",Avoid routing next to clock/high speed signals.

TPM SW

MCH_CFG_6<6>

3

MCH_CFG_6 MCH_CFG_6_R

TPM@DHN-02F-T-V-T/R

TPM@DHN-02F-T-V-T/R

USBOC#6

USBOC#2
USBOC#4 USBOC#1

+3V_S5

USBOC#8
USBOC#9
USBOC#10
USBOC#11

U35D

U35D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9M REV 1.0

ICH9M REV 1.0

R564 *0_4R564 *0_4

U44

U44

1

OFF

ON

2

ON3OFF

R563 *0_4R563 *0_4

RN22

RN22

6
7
8
9

10

10K_10P8R

10K_10P8R

RN21

RN21

6
4
2

10K_8P4R

10K_8P4R

2

4

5
4
3
2
1

78
5
3
1

2

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB27

DMI2RXN

AB26

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

T26

DMI_CLKN

PCI-Express

PCI-Express

USB

USB

USBOC#0USBOC#3
USBOC#7

USBOC#5

T25

DMI_CLKP

Direct Media Interface

Direct Media Interface

AF29

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N

SPI

SPI

USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

PCI ROUTING
TABLE

REQ0# / GNT0# OZ601T

MCH_CFG_6_R <6>

SPI_MOSISPI_MOSI_H

+3V_S5

+3V_S5

AF28

AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2

DMI_IRCOMP_R

USBP8­USBP8+
USBP9­USBP9+

R423 24.9/F_4R423 24.9/F_4

INTERUPT

IDSEL

AD20

INTA#

STOP#
REQ2#
FRAME#
REQ1#

+3V

SERR#
INTA#
INTE#
INTC#

+3V

INTH#

REQ0#

+3V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ICH9M PCIE / PCI / USB

ICH9M PCIE / PCI / USB

ICH9M PCIE / PCI / USB

Date: Sheet

Date: Sheet

Date: Sheet

1

DMI_RXN0 <6>
DMI_RXP0 <6>
DMI_TXN0 <6>
DMI_TXP0 <6>

DMI_RXN1 <6>
DMI_RXP1 <6>
DMI_TXN1 <6>
DMI_TXP1 <6>

DMI_RXN2 <6>
DMI_RXP2 <6>
DMI_TXN2 <6>
DMI_TXP2 <6>

DMI_RXN3 <6>
DMI_RXP3 <6>
DMI_TXN3 <6>
DMI_TXP3 <6>

CLK_PCIE_ICH# <2>
CLK_PCIE_ICH <2>

+1.5V

USBP0- <30>
USBP0+ <30>

USBP1- <30>
USBP1+ <30>
USBP2- <23>

USBP2+ <23>

USBP3- <23>

USBP3+ <23>

USBP5- <22>

USBP5+ <22>
USBP6- <29>
USBP6+ <29>

USBP7- <29>

USBP7+ <29>

USBP8- <29>

USBP8+ <29>

USBP9- <30>

USBP9+ <30>
USBP10- <31>
USBP10+ <31>

USBP11- <19>

USBP11+ <19>

M/B USB PortGLAN
M/B USB Port
Wireless
MINI_TV

BLUETOOTH
NEW CARD
D/B USB Port
D/B USB Port
Finger Printer
DOCKING
CCD

DEVICE

RN25

RN25

6
7
8
9

10

8.2K_10P8R

8.2K_10P8R

RN23

RN23

6
7
8
9

10

8.2K_10P8R

8.2K_10P8R

RN24

RN24

6
7
8
9

10

8.2K_10P8R

8.2K_10P8R

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

+3V

5
4
3
2
1

+3V

5
4
3
2
1

+3V

5
4
3
2
1

1

REQ3#
INTD#
DEVSEL#
TRDY#

INTG#
INTF#

IRDY#
PERR#
INTB#
LOCK#

ZY2 & ZY6

ZY2 & ZY6

ZY2 & ZY6

13 40Wednesday, April 09, 2008

13 40Wednesday, April 09, 2008

13 40Wednesday, April 09, 2008

of

of

of

1A

1A

1A