A
B
C
D
E
MYALL Block Diagram
(Ref. rename from 12/6)
4 4
CLK GEN.
IDT CV125
3 4, 5
Mobile CPU
Dothan
G792
19
RGB
HOST BUS
DDR II
400 MHz LVDS
11,12
DDR II
400MHz
Intel 910GM (UMA)
Intel 915PM (DIS)
400MHz
400 MHz
11,12
3 3
Line In
Mic In
Int.
MIC In
Line Out
27
27
Codec
ALC861
27
27
Azalia
26
OP AMP
INT.SPKR
2 2
27
G1421B
27
MODEM
MDC Card
21
SATA
PCB Layer Stackup
L1: Signal 1
1 1
L2:VCC
L3: Signal 2
SATA
24,25
L4: Signal 3
L5: GND
L6: Signal 4
A
DMI I/F
ICH6-M
PATA
HDD
20
SATA
24,25
(co-lay)
400MHz
100MHz
CDROM
20
B
6,7,8,9,10
LPC BUS
15,16,17,18
USB
USB
5 PORT
21
MINI USB
BlueTooth
21
PCI BUS
Nvidia
G72M-V
ENE
CB1410
10/100
RTL8110CL
Golden
Finger
LAN
PCIE X1
30
C
24,25
24,25
22, 23
ENE KB3910
Pad
VRAMx4
24,25
PWR SW
CP2211
Mini-PCI
802.11A/B/G
TXFM
KBC
INT_KB Touch
30 30
25
28
23
Xbus
RJ45
PCI MINI CARD
BIOS ROM
512 K
PM39LV040-70JCE
Project Code: 91.4G501.001
PCB: 05244-Rev.
CRT
14
LCD
13
PCMCIA
ONE SLOT
25
23
25
31 29
LED BDx1
(another circuit)
D
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
CPU DC/DC
ISL6218CV-T
INPUTS
DCBATOUT
SYSTEM DC/DC
TPS51120
INPUTS
DCBATOUT
APL5912-LAC
APL5308-25AC
INPUTS OUTPUTS
5V_S5
3D3V_S0 2D5V_S0
SYSTEM DC/DC
INPUTS OUTPUTS
DCBATOUT
TPS51100DGQ
5V_S5
CHARGER
DCBATOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
MYALL
MYALL
MYALL
E
OUTPUTS
VCC_CORE
0.844~1.3V
27A
OUTPUTS
3D3V_S5
5V_S5
1D5V_S0
ISL6227
5V_S5
3D3V_S3
DDR_VREF
DDR_VREF_S3
ISL6255
OUTPUTS INPUTS
BT+
16.8V 3A
15 2 Friday, February 10, 2006
15 2 Friday, February 10, 2006
15 2 Friday, February 10, 2006
of
of
of
34
35
36
37
37
38
SA
SA
SA
A
B
C
D
E
Alviso Strapping Signals
and Configuration
Pin Name
CFG[2:0]
4 4
CFG[3:4]
CFG5
CFG6
CFG7
CFG[8:11]
CFG[12:13]
CFG[14:15]
CFG16
CFG17
CFG18
3 3
CFG19
CFG20
SDVOCRTL
_DATA
All strap signals are sampled with respect to the leading
NOTE:
edge of the Alviso GMCH PWORK In signal.
Strap Description
FSB Frequency Select
Reversed
DMI x2 Select
DDR I / DDR II
CPU Strap
Reversed
XOR/ALL Z test
straps
Reversed
FSB Dynamic ODT 0 = Dynamic ODT Disabled
Reversed
CPU core VCC
Select
CPU VTT Select
Reversed
SDVO Present
Configuration
000 = Reserved
001 = FSB533
010 = FSB800
011-111 = Reversed
0 = DMI x2
1 = DMI x4
0 = DDR II
1 = DDR I
0 = Prescott
1 = Dothan
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
(Default)
1 = Dynamic ODT Enabled
(Default)
0 = 1.05V
1 = 1.5V
0 = 1.05V
1 = 1.2V
0 = No SDVO device present
(Default)
1= SDVO device present
(Default)
(Default)
(Default)
(Default)
page 7
PCI Routing
1410
MiniPCI
LAN
25
21
23
IRQ
B.F.G
F
E
REQ/GNT IDSEL
0
1
2
ICH6-M Integrated Pull-up
and Pull-down Resistors
ACZ_BIT_CLK,
EE_DOUT,
GNT[6]#/GPO[16],
LAD[3:0]#/FB[3:0]#, LDRQ[0],
PME#, PWRBTN#,
LAN_RXD[2:0]
ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC,
ACZ_SDOUT,ACZ_BITCLK,
SPKR,
USB[7:0][P,N]
DD[7],
LAN_CLK
DPRSLP#, EE_DIN,
GNT[5]#/GPO[17],
TP[3]
EE_CS,
SDDREQ
LDRQ[1]/GPI[41],
DPRSLPVR,
ICH6 internal 20K pull-ups
ICH6 internal 10K pull-ups
ICH6 internal 20K pull-downs
ICH6 internal 15K pull-downs
ICH6 internal 11.5K pull-downs
ICH6 internal 100K pull-downs
ICH6-M EDS 14308 0.8V1
ICH6-M IDE Integrated Series
Termination Resistors
DD[15:0],
DDACK#,
DCS3#,
IORDY,
IDEIRQ
DIOR#, DREQ, DIOW#,
DA[2:0],
DCS1#,
approximately 33 ohm
2 2
<Core Design>
<Core Design>
1 1
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Memo
Memo
Memo
MYALL
MYALL
MYALL
25 2 Friday, February 10, 2006
25 2 Friday, February 10, 2006
25 2 Friday, February 10, 2006
of
of
of
SA
SA
SA
3D3V_S0 3D3V_S0 3D3V_S0
3D3V_APWR_S0 3D3V_CLKGEN_S0 3D3V_48MPWR_S0
R408
R408
1 2
0R0603-PAD
0R0603-PAD
1 2
C565
C565
1 2
C557
C557
SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
R444
R444
1 2
2R3J-2-GP
2R3J-2-GP
R411
R411
1 2
0R0603-PAD
1 2
C591
C591
1 2
C580
C580
SCD1U16V2ZY-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
0R0603-PAD
1 2
C574
C574
1 2
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C556
C556
1 2
1 2
C555
C555
C558
C558
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
IN
(3D3V_S0)
H
EN
(6218_PGOOD)
L
X
1D05V_S0
1 2
1 2
DY
DY
R401
R401
R438
R438
1KR2J-1-GP
R427
R427
1KR2J-1-GP
1 2
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
FS_C
0
0
0
1
1 100M
1
1
6218_PGOOD 32,34
MYALL SB
FS_A
FS_B
0
0
1
1
0
0
1
1
OUT
(VTT_PWRGD#)
Hi - Z H
MYALL SC
CPU_SEL1 7
CPU_SEL0 4,7
FS_A
0
01200M
1
00333M
1
0
1 Reserved
G
G
H
CPU
266M
133M
166M
400M
1
VTT_PWRGD#
D
D
Q33
Q33
2 3
S
S
2N7002PT-U
2N7002PT-U
PCLK_MINI 28
PCLK_KBC 29
PCLK_PCM 24
PCLK_LAN 22
CLK_ICHPCI 16
PCLK_FWH 31
3D3V_S0
SC22P50V2JN-4GP
SC22P50V2JN-4GP
C571
C571
1 2
1 2
C568
C568
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
678
RN78
RN78
SRN10KJ-4-GP
SRN10KJ-4-GP
123
4 5
? CHECK
R436 33R2J-2-GP R436 33R2J-2-GP
1 2
R400 33R2J-2-GP R400 33R2J-2-GP
1 2
1
8
2
7
3
6
4 5
RN79
RN79
SRN33J-4-GP
SRN33J-4-GP
PM_STPPCI# 16
SMBC_ICH 11,18
SMBD_ICH 11,18
DREFCLK 7
DREFCLK# 7
X4
X4
X-14D31818M-31GP
X-14D31818M-31GP
1 2
CLK_ICH14 & CLK14_SIO
need equal length
1 2
DY
DY
R434
R434
10KR2J-2-GP
10KR2J-2-GP
CLK_ICH14 16
ITP_EN
SS_SEL
1 2
DY
DY
R435
R435
10KR2J-2-GP
10KR2J-2-GP
SC MYALL
PCLK_MINI_1
PCLK_KBC_1
PCLK_PCM_1
PCLK_LAN_1
H/L: 100/96MHz
ITP_EN
H/L : CPU_ITP/SRC7
RN73 SRN33J-5-GP-U RN73 SRN33J-5-GP-U
4
1 2
R520
R520
1 2
R402 475R2F-L1-GP R402 475R2F-L1-GP
VTT_PWRGD#
SS_SEL
DREFCLK_1
2 3
DREFCLK#_1
1
33R2J-2-GP
33R2J-2-GP
XTAL_IN
XTAL_OUT
56
3
4
5
9
8
55
46
47
14
15
50
49
52
39
10
2
6
51
45
38
13
29
IDTCV125PAG-GP
IDTCV125PAG-GP
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_ICH
CLK_PCIE_ICH#
DREFSSCLK
DREFSSCLK#
DREFCLK
DREFCLK#
PCI0
PCI1
PCI2
PCI3
PCIF1/SEL100/96#
PCIF0/ITP_EN
PCI_STOP#
SCL
SDA
DOT96
DOT96#
XTAL_IN
XTAL_OUT
REF
IREF
VTT_PWRGD#/PD
VSS_PCI
VSS_PCI
VSS_REF
VSS_CPU
VSSA
VSS48
VSS_SRC
RN66 SRN49D9F-GP RN66 SRN49D9F-GP
1
2 3
RN67 SRN49D9F-GP RN67 SRN49D9F-GP
1
2 3
RN64 SRN49D9F-GP RN64 SRN49D9F-GP
1
2 3
RN65 SRN49D9F-GP RN65 SRN49D9F-GP
1
2 3
2 3
1
RN81 SRN49D9F-GP RN81 SRN49D9F-GP
2 3
1
RN80
RN80
LVDS
LVDS#
SRC1
SRC1#
SRC2
SRC2#
SRC3
SRC3#
SRC4
SRC4#
SRC5
SRC5#
SRC6
SRC6#
CPU2_ITP/SRC7
CPU2_ITP#/SRC7#
CPU0
CPU0#
CPU1
CPU1#
CPU_STOP#
FSC/TEST_SEL
FSB/TEST_MODE
USB48/FSA
VDD_SRC
VDD_SRC
VDD_PCI
VDD_PCI
VDD_REF
VDD_CPU
VDDA
VDD48
VDD_SRC
4
4
4
4
4
4
SRN49D9F-GP
SRN49D9F-GP
U58
U58
<2nd>
<2nd>
17
18
19
20
22
23
CLK_SRCT3
24
CLK_SRCN3
25
CLK_SRCT4
26
CLK_SRCN4
27
CLK_PCIE_ICH1
31
CLK_PCIE_ICH#1
30
CLK_MCH_3GPLL1
33
CLK_MCH_3GPLL#1
32
36
35
CLK_CPU_BCLK1
44
CLK_CPU_BCLK#1
43
CLK_MCH_BCLK1
41
CLK_MCH_BCLK#1
40
54
CPU_SEL0
53
CPU_SEL1
16
12
34
21
7
1
48
42
37
11
28
2 3
DREFSSCLK1
DREFSSCLK#1
CLK_PCIE_MINI1_1
CLK_PCIE_MINI1_1#
FS_A
3D3V_CLKGEN_S0
3D3V_APWR_S0
3D3V_48MPWR_S0
1
SRN33J-5-GP-U
SRN33J-5-GP-U
RN75 SRN33J-5-GP-U RN75 SRN33J-5-GP-U
RN72 SRN33J-5-GP-U RN72 SRN33J-5-GP-U
1
2 3
RN71 SRN47J-7-GP RN71 SRN47J-7-GP
1
2 3
RN69 SRN33J-5-GP-U RN69 SRN33J-5-GP-U
RN70 SRN33J-5-GP-U RN70 SRN33J-5-GP-U
R437
R437
1 2
22R2J-2-GP
22R2J-2-GP
RN74
RN74
2 3
1
RN76
RN76
2 3
1
RN77
RN77
2 3
1
4
4
1
2 3
1
2 3
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
CLK_PCIE_SATA#
CLK_PCIE_SATA
CLK_PCIE_PEG#
CLK_PCIE_PEG
4
4
SRN33J-5-GP-U
SRN33J-5-GP-U
4
SRN33J-5-GP-U
SRN33J-5-GP-U
4
4
CLK48_ICH 16
4
SRN49D9F-GP
SRN49D9F-GP
SRN49D9F-GP
SRN49D9F-GP
SB
Delete EMI CAP(EC1-EC6) by EMI request
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
Clock Generator - IDT125
Clock Generator - IDT125
Clock Generator - IDT125
MYALL
MYALL
MYALL
35 2 Friday, February 10, 2006
35 2 Friday, February 10, 2006
35 2 Friday, February 10, 2006
DREFSSCLK 7
DREFSSCLK# 7
CLK_PCIE_MINI1 25
CLK_PCIE_MINI1# 25
CLK_PCIE_PEG 42
CLK_PCIE_PEG# 42
CLK_PCIE_SATA 15
CLK_PCIE_SATA# 15
CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
PM_STPCPU# 16,34
RN82
RN82
1
2 3
RN84
RN84
1
2 3
SRN49D9F-G P
SRN49D9F-GP
RN83
RN83
1
2 3
of
4
4
4
SA
SA
SA
A
U31A
U31A
BGA479-SKT6-GPU1
BGA479-SKT6-GPU1
H_A#3
4 4
3 3
2 2
1 1
H_A#[31..3] 6
H_ADSTB#0 6
H_REQ#[4..0] 6
H_ADSTB#1 6
H_A20M# 15
H_FERR# 15
H_IGNNE# 15
H_STPCLK# 15
H_INTR 15
H_NMI 15
H_SMI# 15
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
P4
A3#
U4
A4#
ADDR GROUP 0
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
ADDR GROUP 1
A31#
ADSTB#1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
62.10079.001
62.10079.001
<connector> <CHANGE>
<connector> <CHANGE>
AA3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
Y3
U3
R2
P3
T2
P1
T1
C2
D3
A3
C6
D1
D4
B4
THERMTRIP#
HCLK THERM XTP/ITP SIGNALS CONTROL
All place within 2" to CPU
A
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
CPU_PROCHOT#
XDP_TDI
XDP_TMS
XDP_TDO
H_CPURST#
XDP_DBRESET#
XDP_TCK
XDP_TRST#
B
TP36
TP36
TPAD28
H_RS#0
H_RS#1
H_RS#2
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
CPU_PROCHOT#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R99
R99
1 2
680R2F-GP
680R2F-GP
TPAD28
N2
L1
J3
L4
H2
M2
N4
A4
B5
J2
B11
H1
K1
L2
M3
K3
K4
C8
B8
A9
C9
A10
B10
A13
C12
A12
C11
B13
A7
B17
B18
A18
C17
A15
A16
B14
B15
R90 56R2F-1-GP R90 56R2F-1-GP
R93 150R2F-1-GP R93 150R2F-1-GP
R100 39D2R3F-GP R100 39D2R3F-GP
R92 54D9R2F-L1-GP R92 54D9R2F-L1-GP
R89 54D9R2F-L1-GP R89 54D9R2F-L1-GP
R94 150R2F-1-GP R94 150R2F-1-GP
R91 27D4R2F-L1-GP R91 27D4R2F-L1-GP
B
H_IERR#
TP18 TPAD28 TP18 TPAD28
TP23 TPAD28 TP23 TPAD28
TP20 TPAD28 TP20 TPAD28
TP26 TPAD28 TP26 TPAD28
TP19 TPAD28 TP19 TPAD28
TP22 TPAD28 TP22 TPAD28
1D05V_S0
H_RS#[2..0] 6
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_INIT# 15
H_LOCK# 6
H_CPURST# 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
H_THERMDA 19
H_THERMDC 19
PM_THRMTRIP-I# 7,15,19
CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
1D05V_S0
3D3V_S0
1 2
R95
R95
56R2J-4-GP
56R2J-4-GP
Place testpoint on
H_IERR# with a GND
0.1" away
PM_THRMTRIP#
should connect to
ICH6 and Alviso
without T-ing
( No stub)
CPU_SEL0 3,7
TP25 TPAD28 TP25 TPAD28
R358
R358
1KR2F-3-GP
1KR2F-3-GP
R360
R360
2KR3F-L-GP
2KR3F-L-GP
C
1D05V_S0
C
1 2
1 2
MYALL SB
To V-CORE SWITCH
R98 0R3-0-U-GP R98 0R3-0-U-GP
1 2
TP28 TPAD28 TP28 TPAD28
TP47 TPAD28 TP47 TPAD28
TP41 TPAD28 TP41 TPAD28
TP97 TPAD28 TP97 TPAD28
Layout Note:
0.5" max length.
BSEL[1:0] Freq.(MHz)
(A Stepping)
L L 100
L H 133
BSEL[1:0] Freq.(MHz)
(B Stepping)
L H 100
L L 133
TP33
TP33
TPAD28
TPAD28
GTLREF0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25
H23
G25
M26
H24
G24
M23
N24
M25
H26
N25
K25
K24
C16
C14
AF7
AC1
E26
AD26
L23
F25
J23
J25
L26
L24
J26
E1
C3
62.10079.001
62.10079.001
<connector>
<connector>
<CHANGE>
<CHANGE>
D
U31B
U31B
BGA479-SKT6-GPU1
BGA479-SKT6-GPU1
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
DATA GRP 2
DATA GRP 0 DATA GRP 1
D13#
D14#
D15#
DSTBN0#
DSTBN2#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
PSI#
BSEL0
BSEL1
RSVD2
RSVD3
RSVD4
RSVD5
GTLREF0
MISC
DSTBP2#
DATA GRP 3
DSTBN3#
DSTBP3#
DPRSTP#
DPSLP#
PWRGOOD
D
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPWR#
SLP#
TEST1
TEST2
E
H_D#32
Y26
H_D#33
AA24
H_D#34
T25
H_D#35
U23
H_D#36
V23
H_D#37
R24
H_D#38
R26
H_D#39
R23
H_D#40
AA23
H_D#41
U26
H_D#42
V24
H_D#43
U25
H_D#44
V26
H_D#45
Y23
H_D#46
AA26
H_D#47
Y25
H_DSTBN#2
W25
H_DSTBP#2
W24
H_DINV#2
T24
H_D#48
AB25
H_D#49
AC23
H_D#50
AB24
H_D#51
AC20
H_D#52
AC22
H_D#53
AC25
H_D#54
AD23
H_D#55
AE22
H_D#56
AF23
H_D#57
AD24
H_D#58
AF20
H_D#59
AE21
H_D#60
AD21
H_D#61
AF25
H_D#62
AF22
H_D#63
AF26
H_DSTBN#3
AE24
H_DSTBP#3
AE25
H_DINV#3
AD20
COMP0
P25
COMP1
P26
COMP2
AB2
COMP3
AB1
G1
B7
C19
E4
A6
TEST1
C5
TEST2
F23
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
R121 27D4R2F-L1-GP R121 27D4R2F-L1-GP
1 2
R124 54D9R2F-L1-GP R124 54D9R2F-L1-GP
1 2
R140 27D4R2F-L1-GP R140 27D4R2F-L1-GP
1 2
R141 54D9R2F-L1-GP R141 54D9R2F-L1-GP
1 2
H_DPRSLP# 15
H_DPSLP# 15
H_DPWR# 6
H_CPUSLP# 6,15
TP27 TPAD28 TP27 TPAD28
TP34 TPAD28 TP34 TPAD28
H_D#[63..0] 6
H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6
1D05V_S0
1 2
R96
R96
200R2F-L-GP
200R2F-L-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU (1 of 2)
CPU (1 of 2)
CPU (1 of 2)
MYALL SA
MYALL SA
MYALL SA
45 2 Friday, February 10, 2006
45 2 Friday, February 10, 2006
45 2 Friday, February 10, 2006
E
H_PWRGD 15,19
of
A
VCC_CORE_S0
U31C
U31C
BGA479-SKT6-GPU1
BGA479-SKT6-GPU1
AA11
VCC0
AA13
VCC1
AA15
VCC2
AA17
VCC3
AA19
VCC4
AA21
VCC5
AA5
VCC6
4 4
3 3
2 2
1 1
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
D6
D8
E17
E19
E21
E5
E7
E9
F18
F20
F22
F6
F8
G21
Layout Note:
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
62.10079.001
62.10079.001
<connector>
<connector>
<CHANGE>
<CHANGE>
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCA1
VCCA2
VCCA3
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VID0
VID1
VID2
VID3
VID4
VID5
VCCSENSE
VSSSENSE
VCCSENSE and VSSSENSE lines
should be of equal length.
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
AE7
AF6
VCC_CORE_S0
1D05V_S0
TP_VCCSENSE
TP_VSSSENSE
C416
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
C416
H_VID0 34
H_VID1 34
H_VID2 34
H_VID3 34
H_VID4 34
H_VID5 34
1D5V_S0
1 2
TP44 TPAD28 TP44 TPAD28
TP48 TPAD28 TP48 TPAD28
VCC_CORE_S0
A
1 2
C417
C417
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1D05V_S0
1 2
VCC_CORE_S0
1 2
1 2
DY
DY
VCC_CORE_S0
1 2
B
1 2
C203
C199
C199
C443
C443
C210
C210
C442
C442
C203
SCD1U16V2ZY-2GP
DY
DY
SCD1U16V2ZY-2GP
1 2
1 2
C421
C421
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
1 2
C212
C212
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
B
1 2
1 2
C444
C444
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C158
C158
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C202
C202
DY
DY
C190
C190
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C423
C423
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
1 2
C155
C155
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
1 2
1 2
C159
C159
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C211
C211
C422
C422
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C
1 2
C164
C164
TC9
TC9
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
ST100U6D3VBM-9GP
ST100U6D3VBM-9GP
1 2
1 2
C445
C445
C420
C420
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C
D
U31D BGA479-SKT6-GPU1
U31D BGA479-SKT6-GPU1
A2
VSS0
A5
VSS1
A8
VSS2
A11
VSS3
A14
VSS4
A17
VSS5
A20
VSS6
A23
VSS7
A26
VSS8
AA1
VSS9
AA4
VSS10
AA6
VSS11
AA8
VSS12
AA10
VSS13
AA12
VSS14
AA14
VSS15
AA16
VSS16
AA18
VSS17
AA20
VSS18
AA22
VSS19
AA25
VSS20
AB3
VSS21
AB5
VSS22
AB7
VSS23
AB9
VSS24
AB11
VSS25
AB13
VSS26
AB15
VSS27
AB17
VSS28
AB19
VSS29
AB21
VSS30
AB23
VSS31
AB26
VSS32
AC2
VSS33
AC5
VSS34
AC8
VSS35
AC10
VSS36
AC12
VSS37
AC14
VSS38
AC16
VSS39
AC18
VSS40
AC21
VSS41
AC24
VSS42
AD1
VSS43
AD4
VSS44
AD7
VSS45
AD9
VSS46
AD11
VSS47
AD13
VSS48
AD15
VSS49
AD17
VSS50
AD19
VSS51
AD22
VSS52
AD25
VSS53
AE3
VSS54
AE6
VSS55
AE8
VSS56
AE10
VSS57
AE12
VSS58
AE14
VSS59
AE16
VSS60
AE18
VSS61
AE20
VSS62
AE23
VSS63
AE26
VSS64
AF2
VSS65
AF5
VSS66
AF9
VSS67
AF11
VSS68
AF13
VSS69
AF15
VSS70
AF17
VSS71
AF19
VSS72
AF21
VSS73
AF24
VSS74
B3
VSS75
B6
VSS76
B9
VSS77
B12
VSS78
B16
VSS79
B19
VSS80
B22
VSS81
B25
VSS82
C1
VSS83
C4
VSS84
C7
VSS85
C10
VSS86
C13
VSS87
C15
VSS88
C18
VSS89
C21
VSS90
C24
VSS91
D2
VSS92
D5
VSS93
D7
VSS94
D9
VSS95
D11
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
D
Date: Sheet
VSS96
CPU (2 of 2)
CPU (2 of 2)
CPU (2 of 2)
MYALL SA
MYALL SA
MYALL SA
E
D13
VSS97
D15
VSS98
D17
VSS99
D19
VSS100
D21
VSS101
D23
VSS102
D26
VSS103
E3
VSS104
E6
VSS105
E8
VSS106
E10
VSS107
E12
VSS108
E14
VSS109
E16
VSS110
E18
VSS111
E20
VSS112
E22
VSS113
E25
VSS114
F1
VSS115
F4
VSS116
F5
VSS117
F7
VSS118
F9
VSS119
F11
VSS120
F13
VSS121
F15
VSS122
F17
VSS123
F19
VSS124
F21
VSS125
F24
VSS126
G2
VSS127
G6
VSS128
G22
VSS129
G23
VSS130
G26
VSS131
H3
VSS132
H5
VSS133
H21
VSS134
H25
VSS135
J1
VSS136
J4
VSS137
J6
VSS138
J22
VSS139
J24
VSS140
K2
VSS141
K5
VSS142
K21
VSS143
K23
VSS144
K26
VSS145
L3
VSS146
L6
VSS147
L22
VSS148
L25
VSS149
M1
VSS150
M4
VSS151
M5
VSS152
M21
VSS153
M24
VSS154
N3
VSS155
N6
VSS156
N22
VSS157
N23
VSS158
N26
VSS159
P2
VSS160
P5
VSS161
P21
VSS162
P24
VSS163
R1
VSS164
R4
VSS165
R6
VSS166
R22
VSS167
R25
VSS168
T3
VSS169
T5
VSS170
T21
VSS171
T23
VSS172
T26
VSS173
U2
VSS174
U6
VSS175
U22
VSS176
U24
VSS177
V1
VSS178
V4
VSS179
V5
VSS180
V21
VSS181
V25
VSS182
W3
VSS183
W6
VSS184
W22
VSS185
W23
VSS186
W26
VSS187
Y2
VSS188
Y5
VSS189
Y21
VSS190
Y24
VSS191
<connector> <CHANGE>
<connector> <CHANGE>
62.10079.001
62.10079.001
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
55 2 Friday, February 10, 2006
55 2 Friday, February 10, 2006
55 2 Friday, February 10, 2006
E
of
A
H_XRCOMP
1 2
R351
R351
24D9R2F-L-GP
24D9R2F-L-GP
4 4
1D05V_S0
54D9R2F-L1-GP
54D9R2F-L1-GP
R349
R349
1 2
H_XSCOMP
1D05V_S0
1 2
R354
R354
221R2F-2-GP
221R2F-2-GP
H_XSWING
R366
R366
R355
R355
1D05V_S0
1D05V_S0
1 2
1 2
R369
R369
24D9R2F-L-GP
24D9R2F-L-GP
54D9R2F-L1-GP
54D9R2F-L1-GP
R363
R363
1 2
1 2
R367
R367
221R2F-2-GP
221R2F-2-GP
1 2
3 3
2 2
100R2F-L1-GP-U
100R2F-L1-GP-U
100R2F-L1-GP-U
100R2F-L1-GP-U
H_YRCOMP
H_YSCOMP
H_YSWING
1 2
C460
C460
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C487
C487
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
C
U35A
U35A
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
C1
C2
D1
T1
L1
P1
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
71.0GMCH.08U
71.0GMCH.08U
HCPURST#
HOST
HOST
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HCPUSLP#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB#0
HADSTB#1
HVREF
HBNR#
HBPRI#
HBREQ0#
HCLKINN
HCLKINP
HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS0#
HRS1#
HRS2#
HTRDY#
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
F8
B9
E13
J11
A5
D5
E7
H10
AB1
AB2
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_VREF
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
TP_H_EDRDY#
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
D
H_A#[31..3] 4 H_D#[63..0] 4
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 4
CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3
H_DBSY# 4
H_DEFER# 4
H_DPWR# 4
H_DRDY# 4
TP42 TPAD28 TP42 TPAD28
H_HIT# 4
H_HITM# 4
H_LOCK# 4
TP37 TPAD28 TP37 TPAD28
H_CPUSLP# 4,15
H_TRDY# 4
1 2
C218
C218
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D05V_S0
1 2
1 2
H_DINV#[3..0] 4
H_DSTBN#[3..0] 4
H_DSTBP#[3..0] 4
H_REQ#[4..0] 4
H_RS#[2..0] 4
E
R153
R153
100R2F-L1-GP-U
100R2F-L1-GP-U
R155
R155
200R2F-L-GP
200R2F-L-GP
1 1
Place them near to the chip
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
GMCH (1 of 5)
GMCH (1 of 5)
GMCH (1 of 5)
MYALL SA
MYALL SA
MYALL SA
65 2 Friday, February 10, 2006
65 2 Friday, February 10, 2006
65 2 Friday, February 10, 2006
E
of
A
U35B
U35B
DMI_TXN0
DMI_TXN0 16
M_CLK_DDR0 11
M_CLK_DDR1 11
M_CLK_DDR3 11
M_CLK_DDR4 11
M_CLK_DDR#0 11
M_CLK_DDR#1 11
M_CLK_DDR#3 11
M_CLK_DDR#4 11
1 2
DDR_VREF_S3
1 2
C517 SC2D2U6D3V3MX-1-GP C517 SC2D2U6D3V3MX-1-GP
DMI_TXN1 16
DMI_TXN2 16
DMI_TXN3 16
DMI_TXP0 16
DMI_TXP1 16
DMI_TXP2 16
DMI_TXP3 16
DMI_RXN0 16
DMI_RXN1 16
DMI_RXN2 16
DMI_RXN3 16
DMI_RXP0 16
DMI_RXP1 16
DMI_RXP2 16
DMI_RXP3 16
M_CKE0 11,12
M_CKE1 11,12
M_CKE2 11,12
M_CKE3 11,12
M_CS#0 11,12
M_CS#1 11,12
M_CS#2 11,12
M_CS#3 11,12
M_OCDCOMP0
M_OCDCOMP1
M_ODT0 11,12
M_ODT1 11,12
M_ODT2 11,12
M_ODT3 11,12
1 2
1 2
BC3 SCD1U16V2ZY-2GP BC3 SCD1U16V2ZY-2GP
C520 SC2D2U6D3V3MX-1-GP C520 SC2D2U6D3V3MX-1-GP
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
1 2
BC4 SCD1U16V2ZY-2GP BC4 SCD1U16V2ZY-2GP
4 4
3 3
Layout Note:
Route as short
as possible
1 2
R158
R158
R160
R160
40D2R2F-GP
40D2R2F-GP
40D2R2F-GP
40D2R2F-GP
2 2
1 1
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
2D5V_S0
1D8V_S3
1 2
1 2
AA31
DMIRXN0
AB35
DMIRXN1
AC31
DMIRXN2
AD35
DMIRXN3
Y31
DMIRXP0
AA35
DMIRXP1
AB31
DMIRXP2
AC35
DMIRXP3
AA33
DMITXN0
AB37
DMITXN1
AC33
DMITXN2
AD37
DMITXN3
Y33
DMITXP0
AA37
DMITXP1
AB33
DMITXP2
AC37
DMITXP3
AM33
SM_CK0
AL1
SM_CK1
AE11
SM_CK2
AJ34
SM_CK3
AF6
SM_CK4
AC10
SM_CK5
AN33
SM_CK0#
AK1
SM_CK1#
AE10
SM_CK2#
AJ33
SM_CK3#
AF5
SM_CK4#
AD10
SM_CK5#
AP21
SM_CKE0
AM21
SM_CKE1
AH21
SM_CKE2
AK21
SM_CKE3
AN16
SM_CS0#
AM14
SM_CS1#
AH15
SM_CS2#
AG16
SM_CS3#
AF22
SM_OCDCOMP0
AF16
SM_OCDCOMP1
AP14
SM_ODT0
AL15
SM_ODT1
AM11
SM_ODT2
AN10
SM_ODT3
AK10
SMRCOMPN
AK11
SMRCOMPP
AF37
SMVREF0
AD1
SMVREF1
AE27
SMXSLEWIN
AE28
SMXSLEWOUT
AF9
SMYSLEWIN
AF10
SMYSLEWOUT
2 3
1
R161
R161
80D6R2F-L-GP
80D6R2F-L-GP
R162
R162
80D6R2F-L-GP
80D6R2F-L-GP
71.0GMCH.08U
71.0GMCH.08U
SRN10KJ-5-GP
SRN10KJ-5-GP
RN59
RN59
M_RCOMPN
M_RCOMPP
DMI
DMI
DDR MUXING
DDR MUXING
PM_EXTTS#0
PM_EXTTS#1
4
A
CFG/RSVD
CFG/RSVD
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PM
PM
PWROK
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
CLK
CLK
DREF_SSCLKP
NC
NC
B
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSTIN#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
B
10KR2J-3-GP
10KR2J-3-GP
G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
PM_EXTTS#0
J21
PM_EXTTS#1
H22
F5
AD30
AE29
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
CFG0
CFG6
1D05V_S0
1D05V_S0
1 2
R152
R152
CFG[2:0] Freq.(MHz)
101 400
001 533
CPU_SEL1 3
CPU_SEL0 3,4
R145
R145
2K2R2J-2-GP
2K2R2J-2-GP
?CHECK DISABLE VGA
0R2J-GP
0R2J-GP
R122
R122
1 2
G72
G72
PM_BMBUSY# 16
PM_THRMTRIP-I# 4,15,19
VGATE_PWRGD
0R2J-GP
0R2J-GP
R146
R146
1 2
G72
G72
0R2J-GP
0R2J-GP
R149
R149
1 2
G72
G72
VGATE_PWRGD 16,32
DREFCLK# 3
DREFCLK 3
DREFSSCLK# 3
DREFSSCLK 3
DY
DY
GMCH_VSYNC_1
1 2
R159 150R2J-L1-GP-U R159 150R2J-L1-GP-U
1 2
R123
R123
0R2J-GP
0R2J-GP
UMA
UMA
1 2
PLT_RST1# 16,18,25,29,31,42,47
MYALL SC
10KR2J-2-GP
10KR2J-2-GP
1 2
R156
R156
GMCH_HSYNC_1
G72
G72
G72
G72
G72
G72
R129 150R2F-1-GP
R129 150R2F-1-GP
R131 150R2F-1-GP
R131 150R2F-1-GP
R134 150R2F-1-GP
R134 150R2F-1-GP
C
Alviso will provide SDVO_CTRLCLK
and CTRLDATA pulldowns on-die
UMA
UMA
UMA
UMA
UMA
UMA
GMCH_DDCCLK 14
G MCH_DDCDATA 14
1 2
R130 0R2J-GP
R130 0R2J-GP
1 2
1 2
R132 0R2J-GP
R132 0R2J-GP
1 2
1 2
R133 0R2J-GP
R133 0R2J-GP
1 2
GMCH_VSYNC 14
GMCH_HSYNC 14
1D05V_S0
GMCH_GREEN 14
0R2J-GP
0R2J-GP
C
TP45 TPAD28 TP45 TPAD28
TP46 TPAD28 TP46 TPAD28
CLK_MCH_3GPLL# 3
CLK_MCH_3GPLL 3
GMCH_BLUE 14
GMCH_RED 14
R335
R335
1 2
UMA
UMA
267R2F-1-GP
267R2F-1-GP
R336
R336
1 2
G72
G72
BL_ON 29
CLK_DDC_EDID 13
DAT_DDC_EDID 13
GMCH_LCDVDD_ON 13
TP39 TPAD28 TP39 TPAD28
TP43 TPAD28 TP43 TPAD28
TP40 TPAD28 TP40 TPAD28
GMCH_TXACLK- 13
GMCH_TXACLK+ 13
GMCH_TXBCLK- 13
GMCH_TXBCLK+ 13
GMCH_TXAOUT0- 13
GMCH_TXAOUT1- 13
GMCH_TXAOUT2- 13
GMCH_TXAOUT0+ 13
GMCH_TXAOUT1+ 13
GMCH_TXAOUT2+ 13
GMCH_TXBOUT0- 13
GMCH_TXBOUT1- 13
GMCH_TXBOUT2- 13
GMCH_TXBOUT0+ 13
GMCH_TXBOUT1+ 13
GMCH_TXBOUT2+ 13
LCTLA_CLK
LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID
BL_ON
LBKLT_CRTL
LIBG
SDVOC_CTRLDATA
SDVOC_CTRLCLK
1 2
R147 39R2J-L-GP
R147 39R2J-L-GP
1 2
R148 39R2J-L-GP
R148 39R2J-L-GP
UMA
UMA
UMA
UMA
0R2J-GP
0R2J-GP
1 2
G72
G72
SRN2K2J-1-GP
SRN2K2J-1-GP
SRN2K2J-1-GP
SRN2K2J-1-GP
SRN100KJ-6-GP
SRN100KJ-6-GP
R344
R344
1 2
0R2J-GP
0R2J-GP
R345
R345
LBKLT_CRTL
LCTLA_CLK
LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID
LIBG
DY
DY
RN14
RN14
1
4
2 3
RN13
RN13
1
4
2 3
1
4
2 3
R143 1K5R2F-2-GP R143 1K5R2F-2-GP
1 2
RN12
RN12
CRTIREF
GMCH_VSYNC_1
GMCH_HSYNC_1
UMA
UMA
L_LVBG
L_VREFH
L_VREFL
2D5V_S0
AB29
AC29
H24
H25
A15
C16
A17
J18
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
U35G
U35G
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CRTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
71.0GMCH.08U
71.0GMCH.08U
D
EXP_COMPI
EXP_ICOMPO
EXP_RXN0
MISC TV VGA LVDS
MISC TV VGA LVDS
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D
E
1D5V_S0
R144
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
R144
1 2
24D9R2F-L-GP
24D9R2F-L-GP
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
SDVOB_RN_1
SDVOB_GN_1
SDVOB_BN_1
SDVOB_CLKN_1
SDVOC_RN_1
SDVOC_GN_1
SDVOC_BN_1
SDVOC_CLKN_1
TXN8
TXN9
TXN10
TXN11
TXN13
TXN14
TXN15
SDVOB_RP_1
SDVOB_GP_1
SDVOB_BP_1
SDVOB_CLKP_1
SDVOC_RP_1
SDVOC_GP_1
SDVOC_BP_1
SDVOC_CLKP_1
TXP8
TXP9
TXP10
TXP11
TXP12
TXP13
TXP14
TXP15
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
PEG_RXN[15..0] 42
PEG_RXP[15..0] 42
C466 SCD1U16V
C466 SCD1U16V
1 2
C468 SCD1U16V
C468 SCD1U16V
1 2
C473 SCD1U16V
C473 SCD1U16V
1 2
G72
G72
C474 SCD1U16V
C474 SCD1U16V
1 2
G72
G72
C477 SCD1U16V
C477 SCD1U16V
1 2
G72
G72
C478 SCD1U16V
C478 SCD1U16V
1 2
G72
G72
C483 SCD1U16V
C483 SCD1U16V
1 2
G72
G72
C484 SCD1U16V
C484 SCD1U16V
1 2
G72
G72
C489 SCD1U16V
C489 SCD1U16V
1 2
G72
G72
C491 SCD1U16V
C491 SCD1U16V
1 2
G72
G72
C495 SCD1U16V
C495 SCD1U16V
1 2
G72
G72
C497 SCD1U16V
C497 SCD1U16V
1 2
G72
G72
C500 SCD1U16V
C500 SCD1U16V
1 2
G72
G72
C503 SCD1U16V
C503 SCD1U16V
1 2
G72
G72
C508 SCD1U16V
C508 SCD1U16V
1 2
G72
G72
C509 SCD1U16V
C509 SCD1U16V
1 2
G72
G72
G72
G72
C463 SCD1U16V
C463 SCD1U16V
1 2
G72
G72
C465 SCD1U16V
C465 SCD1U16V
1 2
C469 SCD1U16V
C469 SCD1U16V
1 2
G72
G72
C472 SCD1U16V
C472 SCD1U16V
1 2
G72
G72
C475 SCD1U16V
C475 SCD1U16V
1 2
G72
G72
C476 SCD1U16V
C476 SCD1U16V
1 2
G72
G72
C479 SCD1U16V
C479 SCD1U16V
1 2
G72
G72
C482 SCD1U16V
C482 SCD1U16V
1 2
G72
G72
C485 SCD1U16V
C485 SCD1U16V
1 2
G72
G72
C488 SCD1U16V
C488 SCD1U16V
1 2
G72
G72
C492 SCD1U16V
C492 SCD1U16V
1 2
G72
G72
C494 SCD1U16V
C494 SCD1U16V
1 2
G72
G72
C498 SCD1U16V
C498 SCD1U16V
1 2
G72
G72
C499 SCD1U16V
C499 SCD1U16V
1 2
G72
G72
C504 SCD1U16V
C504 SCD1U16V
1 2
G72
G72
C507 SCD1U16V
C507 SCD1U16V
1 2
G72
G72
G72
G72
G72
G72
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
GMCH (2 of 5)
GMCH (2 of 5)
GMCH (2 of 5)
MYALL SA
MYALL SA
MYALL SA
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12 TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
of
of
of
75 2 Friday, February 10, 2006
75 2 Friday, February 10, 2006
75 2 Friday, February 10, 2006
E
PEG_TXN[15..0] 42
PEG_TXP[15..0] 42
A
4 4
U35C
M_A_DQ[63..0] 11 M_B_DQ[63..0] 11
3 3
2 2
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
U35C
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_RCVENIN#
SA_RCVENOUT#
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_WE#
B
AK15
AK16
AL21
M_A_DM0
AJ37
M_A_DM1
AP35
M_A_DM2
AL29
M_A_DM3
AP24
M_A_DM4
AP9
M_A_DM5
AP4
M_A_DM6
AJ2
M_A_DM7
AD3
M_A_DQS0
AK36
M_A_DQS1
AP33
M_A_DQS2
AN29
M_A_DQS3
AP23
M_A_DQS4
AM8
M_A_DQS5
AM4
M_A_DQS6
AJ1
M_A_DQS7
AE5
M_A_DQS#0
AK35
M_A_DQS#1
AP34
M_A_DQS#2
AN30
M_A_DQS#3
AN23
M_A_DQS#4
AN8
M_A_DQS#5
AM5
M_A_DQS#6
AH1
M_A_DQS#7
AE4
M_A_A0
AL17
M_A_A1
AP17
M_A_A2
AP18
M_A_A3
AM17
M_A_A4
AN18
M_A_A5
AM18
M_A_A6
AL19
M_A_A7
AP20
M_A_A8
AM19
M_A_A9
AL20
M_A_A10
AM16
M_A_A11
AN20
M_A_A12
AM20
M_A_A13
AM15
AN15
AP16
SA_RCVENIN#
AF29
SA_RCVENOUT#
AF28
AP15
Place Test PAD Near to Chip
as could as possible
C
U35D
U35D
M_A_BS#0 11,12
M_A_BS#1 11,12
M_A_BS#2 11,12
M_A_DM[7..0] 11
M_A_DQS[7..0] 11
M_A_DQS#[7..0] 11
M_A_A[13..0] 11,12
M_A_CAS# 11,12
M_A_RAS# 11,12
TP51 TPAD28 TP51 TPAD28
TP49 TPAD28 TP49 TPAD28 TP50 TPAD28 TP50 TPAD28
M_A_WE# 11,12
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
D
AJ15
SB_BS0#
AG17
SB_BS1#
AG21
SB_BS2#
AF32
SB_DM0
AK34
SB_DM1
AK27
SB_DM2
AK24
SB_DM3
AJ10
SB_DM4
AK5
SB_DM5
AE7
SB_DM6
AB7
SB_DM7
AF34
SB_DQS0
AK32
SB_DQS1
AJ28
SB_DQS2
AK23
SB_DQS3
AM10
SB_DQS4
AH6
SB_DQS5
AF8
SB_DQS6
AB4
SB_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_WE#
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
Place Test PAD Near to Chip
ascould as possible
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_RCVENIN#
SB_RCVENOUT#
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
SB_RCVENIN#
SB_RCVENOUT#
M_B_BS#0 11,12
M_B_BS#1 11,12
M_B_BS#2 11,12
M_B_DM[7..0] 11
M_B_DQS[7..0] 11
M_B_DQS#[7..0] 11
M_B_A[13..0] 11,12
M_B_CAS# 11,12
M_B_RAS# 11,12
TP52 TPAD28 TP52 TPAD28
M_B_WE# 11,12
E
71.0GMCH.08U
71.0GMCH.08U
1 1
A
B
C
71.0GMCH.08U
71.0GMCH.08U
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
D
Date: Sheet of
GMCH (3 of 5)
GMCH (3 of 5)
GMCH (3 of 5)
MYALL SA
MYALL SA
MYALL SA
85 2 Friday, February 10, 2006
85 2 Friday, February 10, 2006
85 2 Friday, February 10, 2006
E
of
A
4 4
1D5V_DLVDS_S0
UMA
UMA
3 3
F17
E17
D18
C18
Route ASSATVBG gnd from GMCH to
decoupling cap groung lead and
then connect to the gnd plane
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
R343
R343
0R2J-GP
0R2J-GP
F18
E18
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
H18
1 2
VCCA_TVBG
G18
1 2
VSSA_TVBG
R342
R342
0R2J-GP
0R2J-GP
G72
G72
H17
D19
VCCD_TVDAC
VCCDQ_TVDAC
B26
B25
VCCD_LVDS0
UMA
UMA
1 2
A25
VCCD_LVDS1
2D5V_ALVDS_S0
VCCD_LVDS2
R346
R346
0R2J-GP
0R2J-GP
R3470R2J-GP
R3470R2J-GP
G72
G72
A35
B22
VCCA_LVDS
B
1 2
B21
A21
VCCHV0
VCCHV1
VCCHV2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C526
C526
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C521
C521
1 2
V1.8_DDR_ CAP1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
V1.8_DDR_CAP2
V1.8_DDR_CAP5
AM37
AH37
AP29
AD28
AD27
AC27
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
2D5V_TVDAC_S0
1 2
C451
C451
Note: All VCCSM
pins shorted
internally
1 2
C540
C540
AK26
AJ26
AP26
AN26
AM26
AL26
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
C
1D5V_S0
R334
R334
1 2
0R0603-PAD
0R0603-PAD
2D5V_S0 2D5V_ALVDS_S0
R340
R340
1 2
0R0603-PAD
0R0603-PAD
2D5V_S0
2D5V_S0 2D5V_TXLVDS_S0
R339
R339
1 2
0R0603-PAD
0R0603-PAD
C447
C447
1 2
R341
R341
1 2
0R0603-PAD
0R0603-PAD
1 MYALL DIS 0206
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
C542
C542
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
POWER
POWER
1D8V_S3
1 2
AE16
VCCSM33
1 2
C233
C233
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AE15
AE14
AP13
AN13
AM13
AL13
AK13
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
C541
C541
AJ13
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AH13
VCCSM42
VCCSM43
AG13
AF13
AE13
VCCSM44
VCCSM45
VCCSM46
1D5V_DLVDS_S0
1 2
C425
C425
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
C452
C452
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1 2
C446
C446
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
AP12
AN12
AM12
AL12
AK12
AJ12
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
Note: All VCCSM
pins shorted
internally
C539
C539
AH12
AG12
AF12
AE12
VCCSM53
VCCSM54
VCCSM55
D
1 2
C248
C248
ST100U6D3VBM-9GP
ST100U6D3VBM-9GP
E
R383
R383
1 2
0R0603-PAD
0R0603-PAD
1D5V_S0
1 MYALL DIS 0206
1D5V_S0
1 2
1 2
C527
C527
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C237
C237
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2D5V_TXLVDS_S0
UMA
UMA
R348
R348
0R2J-GP
0R2J-GP
1 2
AD11
AC11
AB11
AB10
VCCSM56
VCCSM57
VCCSM58
VCCSM59
1 2
R3370R2J-GP
R3370R2J-GP
1 2
G72
G72
V1.8_DDR_CAP4
V1.8_DDR_CAP3
V1.8_DDR_CAP6
B28
A28
AB9
AP8
VCCSM60
VCCSM61
A27
AM1
AE1
VCCSM62
VCCSM63
AF20
AP19
VCCSM64
VCCA_SM0
VCCA_SM1
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
AF19
AF18
VCCA_SM2
VCCA_SM3
ST330U2D5VDM-9GP
ST330U2D5VDM-9GP
AE37
W37
U37
R37
VCC3G0
VCC3G1
VCC3G2
TC32
TC32
N37
VCC3G3
VCC3G4
L37
J37
VCC3G5
Y29
VCC3G6
VCCA_3GPLL0
1 2
C513
C513
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
C234
C234
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
F37
Y27
Y28
G37
VSSA_3GBG
VCCA_3GBG
VCCA_3GPLL2
VCCA_3GPLL1
1 MYALL DIS
0207 REMOVE
R142
R157
R157
1 2
0R0603-PAD
0R0603-PAD
1 MYALL DIS 0206
R352
R352
1 2
1 2
0R0603-PAD
0R0603-PAD
C462
C462
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
U35E
U35E
71.0GMCH.08U
71.0GMCH.08U
Route ASSA3GBG gnd from GMCH to
decoupling cap groung lead and
then connect to the gnd plane
1D5V_S0
2D5V_S0
VCC 1D05_S0 for low speed
graphic clock.1D5V_S0 for
high speed clock.default
1 2
C227
C227
use 1D05V_S0
1D05V_S0
1 2
C220
C220
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1 2
1 2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C215
C215
C222
C222
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
2 2
1 1
A
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCC_SYNC
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51
J29
T29
R29
1 2
1 2
C225
C225
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
T28
K29
V28
N29
U28
1 2
C226
C226
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
ST330U2D5VDM-9GP
ST330U2D5VDM-9GP
R28
M29
C224
C224
1D5V_S0
BLM18BB221SN1D-GP
BLM18BB221SN1D-GP
J28
L28
P28
K28
N28
M28
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
L26
L26
T27
V27
H28
U27
R27
G28
C219
C219
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
TC33
TC33
B
L27
P27
N27
M27
R375
R375
0R0805-PAD
0R0805-PAD
L14
L14
1 2
0R0805-PAD
0R0805-PAD
L27
L27
1 2
0R0805-PAD
0R0805-PAD
L32
L32
1 2
0R0805-PAD
0R0805-PAD
L31
L31
1 2
0R0805-PAD
0R0805-PAD
J27
K27
H27
1 2
J25
K26
K25
K24
K23
H26
1 2
C204
C204
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
C453
C453
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
C511
C511
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
C505
C505
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
T20
K22
K21
K20
U20
W20
T18
V19
K19
V18
K18
U19
W18
1D5V_HMPLL_S0
1D5V_DPLLA_S0
1 2
C209
C209
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D5V_DPLLB_S0
1 2
C455
C455
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D5V_HPLL_S0
1 2
C510
C510
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D5V_MPLL_S0
1 2
C506
C506
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
K17
AC2
AC1
F19
B23
E19
C35
AA1
AA2
G19
C
J13
K13
K12
H20
GMCH_VCC_SYNC
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Layout Notes: VSSA_CRTDAC
Route caps within 250mil
of Alviso. Route FB connect to the gnd plane.
within 3" of Alviso.
V11
U11
W11
R135
R135
1 2
0R2J-GP
0R2J-GP
G72
G72
2D5V_CRTDAC_S0
C450
C450
R136
R136
1 2
0R2J-GP
0R2J-GP
UMA
UMA
T11
R11
G72
G72
L11
P11
N11
M11
1 2
T10
K11
V10
U10
W10
R338
R338
1 2
DY
DY
0R3-0-U-GP
0R3-0-U-GP
L25
L25
1 2
1 2
BLM18BB221SN1D-GP
BLM18BB221SN1D-GP
C449
C449
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C201
C201
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Route VSSA_CRTDAC gnd from GMCH to
decoupling cap ground lead and then
R10
P10
N10
2D5V_S0
J10
K10
M10
1D05V_S0
1 2
1KR2J-1-GP
1KR2J-1-GP
D
R126
R126
G72
G72
VCCP_GMCH_CAP1
SCD47U1 0V3ZY-GP
SCD47U10V3ZY-GP
C454
C454
1D05V_S0
C223
C223
1 2
C496
C496
1 2
1 2
C448
SCD47U10V3ZY-GP
SCD47U10V3ZY-GP
C448
1D05V_S0
D4
D4
2 1
SSM5818SLPT-GP
SSM5818SLPT-GP
G72
G72
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
G1
VCCP_GMCH_CAP3
VCCP_GMCH_CAP4
VCCP_GMCH_CAP2
1 2
1 2
C470
C470
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
1 2
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
GMCH (4 of 5)
GMCH (4 of 5)
GMCH (4 of 5)
MYALL SA
MYALL SA
MYALL SA
1 2
C228
C228
C481
C481
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
95 2 Friday, February 10, 2006
95 2 Friday, February 10, 2006
95 2 Friday, February 10, 2006
E
of
A
H29
G29
F29
E29
D29
A29
AC28
AB28
AA28
W28
E28
AN27
AL27
AJ27
AG27
AF27
AB27
AA27
W27
G27
E27
B27
J26
G26
E26
A26
AN24
U35F
U35F
4 4
71.0GMCH.08U
71.0GMCH.08U
AL24
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS259P2VSS258T2VSS257V2VSS256
VSS255
VSS254
VSS253
VSS252
VSS251A3VSS250C3VSS249
VSS248
VSS247
VSS246
AA3
AB3
AC3
VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239
AJ3
AF4
VSSALVDS
B36
VSS260L2VSS268J2VSS269G2VSS270D2VSS271
Y1
AL2
AE2
AD2
AH2
AN2
B
V31
U31
T31
R31
P31
N31
M31
L31
K31
J31
H31
G31
F31
E31
D31
AP30
AE30
AC30
AB30
AA30
Y30
C30
AM29
AJ29
AG29
AD29
AA29
W29
V29
U29
P29
L29
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS238
VSS237E5VSS236W5VSS235
VSS234
VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228
AL5
AP5
AN4
AA6
VSS227
VSS226
VSS225
VSS224G7VSS223V7VSS222
VSS221
VSS220
VSS219
VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213
AJ6
AE6
AA7
AC6
AK7
AN7
AG7
VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207
AL8
AA9
W31
AC9
C
C34
AL33
AF33
AD33
W33
V33
U33
T33
R33
P33
N33
M33
L33
K33
J33
H33
G33
F33
E33
D33
AN32
AJ32
AD32
AC32
AB32
AA32
Y32
C32
A32
AL31
AG31
AD31
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS
VSS
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
J12
AE9
L10
F11
Y11
Y10
D10
AH9
AN9
H11
AA11
AA10
B12
AJ11
AL11
AF11
AN11
AG11
D12
J14
F14
A14
B14
K14
AG14
VSS175
K15
A16
C15
AJ14
D16
AL14
AN14
D
AF36
AE36
AD36
AC36
AB36
AA36
C36
AE35
Y35
W35
V35
U35
T35
R35
P35
N35
M35
L35
K35
J35
H35
G35
F35
E35
D35
B35
AN34
AH34
AD34
AC34
AB34
AA34
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
J19
H16
K16
AL16
C17
G17
A18
B18
AJ17
AF17
AN17
U18
T19
C19
H19
W19
AL18
F20
G20
F21
V20
A22
C21
D22
AF21
AK20
AN21
A20
E20
D20
AN19
AG19
E
AL36
AJ36
K37
H37
E37
AN36
VSS7
VSS8
VSS9
VSS10
VSS11
VSS141
VSS140
VSS139
VSS138
VSS137
J22
E22
H23
AL22
AF23
AH22
M37
VSS6
VSS136
B24
P37
VSS5
VSS135
D24
T37
VSS4
VSS134
F24
V37
VSS3
VSS133
J24
Y37
VSS2
VSS132
AG24
AG37
VSS1
VSS131
AJ24
VSS0
VSS130
1D8V_S3
1 2
3 3
AD13
AC13
AB13
AD12
AC12
U35H
U35H
71.0GMCH.08U
2 2
71.0GMCH.08U
AB12
VCCSM_NCTF27
VCCSM_NCTF28
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
C235
C235
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AC16
AD15
AC15
AD14
AC14
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
1 2
AD16
VCCSM_NCTF21
C231
C231
AD17
AC17
VCCSM_NCTF19
VCCSM_NCTF20
1D05V_S0
Place these Hi-Freq decoupling caps near GMCH
VCCSM_NCTF8
VTT_NCTF14
AC23
R12
C236
C236
VCCSM_NCTF7
VTT_NCTF13
AD23
T12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
VCCSM_NCTF6
VTT_NCTF12
AC24
U12
VCCSM_NCTF5
VTT_NCTF11
AD24
V12
VCCSM_NCTF4
VTT_NCTF10
AC25
W12
1 2
AD25
VCCSM_NCTF3
VTT_NCTF9
L13
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
AD19
AC19
AD18
AC18
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
1 2
C232
C232
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
AD21
AC21
AD20
AC20
AD22
AC22
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VCCSM_NCTF13
VCCSM_NCTF14
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
L12
P12
N12
M12
VCCSM_NCTF2
VTT_NCTF8
AC26
M13
VCCSM_NCTF1
VTT_NCTF7
1 2
C240
AD26
N13
VCCSM_NCTF0
VTT_NCTF6
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
L17
VCC_NCTF78
VTT_NCTF5
VTT_NCTF4
P13
R13
C240
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
T17
P17
N17
M17
VCC_NCTF74
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
T13
V13
U13
W13
U17
W17
V17
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
C239
C239
1D05V_S0
M18
P18
N18
L18
VCC_NTTF69
VCC_NCTF68
VCC_NCTF70
VSS_NCTF68
Y12
AA12
P19
N19
M19
L19
Y18
R18
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
L14
Y13
P14
N14
M14
AA13
P20
N20
M20
L20
Y19
R19
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
NCTF
NCTF
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
T14
V14
Y14
R14
U14
W14
P21
N21
M21
L21
Y20
R20
VCC_NCTF54
VCC_NCTF55
VSS_NCTF55
VSS_NCTF54
AA14
AB14
U21
T21
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF48
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
L15
T15
P15
N15
R15
M15
P22
N22
M22
L22
W21
V21
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
V15
Y15
U15
W15
AA15
AB15
R22
L16
M23
L23
W22
V22
U22
T22
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
T16
P16
N16
R16
U16
M16
V23
U23
T23
R23
P23
N23
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
V16
Y16
R17
W16
AA16
AB16
R24
P24
N24
M24
L24
W23
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
Y17
AA17
AB17
AA18
AB18
AA19
M25
L25
W24
V24
U24
T24
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
Y21
R21
AB19
AA20
AB20
AA21
V25
U25
T25
R25
P25
N25
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
Y22
AB21
AA22
AB22
N26
M26
L26
W25
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
Y23
Y24
AA23
AB23
AA24
AB24
VCC_NCTF6
VSS_NCTF6
W26
V26
U26
T26
R26
P26
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
Y25
Y26
AA25
AB25
AA26
AB26
1 1
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
GMCH (5 of 5)
GMCH (5 of 5)
GMCH (5 of 5)
MYALL
MYALL
MYALL
E
10 52 Friday, February 10, 2006
10 52 Friday, February 10, 2006
10 52 Friday, February 10, 2006
SA
SA
SA
A
DM1
M_B_A[13..0] 8,12
4 4
M_B_BS#2 8,12
M_B_BS#0 8,12
M_B_BS#1 8,12
M_B_DQ[63..0] 8
3 3
2 2
M_B_DQS#[7..0] 8
M_B_DQS[7..0] 8
C280
C280
M_ODT3 7,12
1 2
DDR_VREF_S3
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1 1
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
1 2
BC1
BC1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DM1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
/DQS0
29
/DQS1
49
/DQS2
68
/DQS3
129
/DQS4
146
/DQS5
167
/DQS6
186
/DQS7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
ODT0
119
ODT1
1
VREF
2
VSS
202
GND
DDR2-200P-2-GP
DDR2-200P-2-GP
High 5.2mm
2nd source:62.10017.661
108
/RAS
109
/WE
113
/CAS
110
/CS0
115
/CS1
79
CKE0
80
CKE1
30
CK0
32
/CK0
164
CK1
166
/CK1
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
195
SDA
197
SCL
199
VDDSPD
198
SA0
200
SA1
50
NC#50
69
NC#69
83
NC#83
120
NC#120
163
NC#163/TEST
81
VDD
82
VDD
87
VDD
88
VDD
95
VDD
96
VDD
103
VDD
104
VDD
111
VDD
112
VDD
117
VDD
118
VDD
3
VSS
8
VSS
9
VSS
12
VSS
15
VSS
18
VSS
21
VSS
24
VSS
27
VSS
28
VSS
33
VSS
34
VSS
39
VSS
40
VSS
41
VSS
42
VSS
47
VSS
48
VSS
53
VSS
54
NORMAL TYPE
VSS
59
VSS
60
VSS
65
VSS
66
VSS
71
VSS
72
VSS
77
VSS
78
VSS
121
VSS
122
VSS
127
VSS
128
VSS
132
VSS
133
VSS
138
VSS
139
VSS
144
VSS
145
VSS
149
VSS
150
VSS
155
VSS
156
VSS
161
VSS
162
VSS
165
VSS
168
VSS
171
VSS
172
VSS
177
VSS
178
VSS
183
VSS
184
VSS
187
VSS
190
VSS
193
VSS
196
VSS
201
GND
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SMBD_ICH_1
SMBC_ICH_1
1 2
R206
R206
A
10KR2J-3-GP
10KR2J-3-GP
1D8V_S3
B
M_B_RAS# 8,12
M_B_WE# 8,12
M_B_CAS# 8,12
M_CS#2 7,12
M_CS#3 7,12
M_CKE2 7,12
M_CKE3 7,12
M_CLK_DDR3 7
M_CLK_DDR#3 7
M_CLK_DDR4 7
M_CLK_DDR#4 7
SRN33J-5-GP-U
SRN33J-5-GP-U
RN22
RN22
1
2 3
3D3V_S0
3D3V_S0
B
M_B_DM[7..0] 8
4
M_A_DQ[63..0] 8
SMBD_ICH 3,18
SMBC_ICH 3,18
M_A_DQS[7..0] 8
M_A_DQS#[7..0] 8
DDR_VREF_S3
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C
DM2
M_A_A[13..0] 8,12
M_A_BS#2 8,12
M_A_BS#0 8,12
M_A_BS#1 8,12
M_ODT0 7,12
M_ODT1 7,12 M_ODT2 7,12
1 2
C311
C311
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
1 2
BC2
BC2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C
DM2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
/DQS0
29
/DQS1
49
/DQS2
68
/DQS3
129
/DQS4
146
/DQS5
167
/DQS6
186
/DQS7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
ODT0
119
ODT1
1
VREF
2
VSS
202
GND
DDR2-200P-3-UGP
DDR2-200P-3-UGP
High 9.2mm
2nd source:62.10017.A61
/RAS
/WE
/CAS
/CS0
/CS1
CKE0
CKE1
CK0
/CK0
CK1
/CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
SA0
SA1
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NORMAL TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
108
109
113
110
115
79
80
30
32
164
166
M_A_DM0
10
M_A_DM1
26
M_A_DM2
52
M_A_DM3
67
M_A_DM4
130
M_A_DM5
147
M_A_DM6
170
M_A_DM7
185
SMBD_ICH_1
195
SMBC_ICH_1
197
199
198
200
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
3D3V_S0
1D8V_S3
D
M_A_RAS# 8,12
M_A_WE# 8,12
M_A_CAS# 8,12
M_CS#0 7,12
M_CS#1 7,12
M_CKE0 7,12
M_CKE1 7,12
M_CLK_DDR0 7
M_CLK_DDR#0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
M_A_DM[7..0] 8
D
E
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
DDR Socket
DDR Socket
DDR Socket
MYALL
MYALL
MYALL
E
11 52 Friday, February 10, 2006
11 52 Friday, February 10, 2006
11 52 Friday, February 10, 2006
of
of
of
SA
SA
SA
A
PARALLEL TERMINATION
DDR_VREF
R222 56R2J-4-GP R222 56R2J-4-GP
1 2
R221 56R2J-4-GP R221 56R2J-4-GP
1 2
RN23
RN23
1
4
4 4
3 3
2 2
1 1
SRN56J-4-GP
SRN56J-4-GP
RN19
RN19
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN20
RN20
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN28
RN28
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN27
RN27
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN26
RN26
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN21
RN21
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN38
RN38
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN37
RN37
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN34
RN34
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN35
RN35
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN36
RN36
8
7
6
SRN56J-2-GP
SRN56J-2-GP
RN33
RN33
8
7
6
SRN56J-2-GP
SRN56J-2-GP
2 3
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
Put decap near power(0.9V) and pull-up resistor
M_CKE0 7,11
M_ODT1 7,11
M_CS#3 7,11
M_ODT3 7,11
M_CKE2 7,11
M_B_A12
M_B_A8
M_B_A9
M_B_A5
M_B_A3
M_B_A1
M_B_A13
M_B_A0
M_B_A2
M_B_A4
M_B_A6
M_B_A7
M_B_A11
M_B_A10
M_A_A13
M_A_A0
M_A_A2
M_A_A4
M_A_A9
M_A_A12
M_A_A8
M_A_A6
M_A_A11
M_A_A7
M_A_A5
M_A_A3
M_A_A1
M_A_A10
M_B_BS#2 8,11
M_ODT2 7,11
M_CS#2 7,11
M_B_RAS# 8,11
M_B_BS#1 8,11
M_CKE3 7,11
M_B_WE# 8,11
M_B_BS#0 8,11
M_B_CAS# 8,11
M_ODT0 7,11
M_CS#0 7,11
M_A_RAS# 8,11
M_A_BS#1 8,11
M_A_WE# 8,11
M_A_BS#0 8,11
M_A_CAS# 8,11
M_CS#1 7,11
M_A_BS#2 8,11
M_CKE1 7,11
A
B
B
M_A_A[13..0] 8,11
M_B_A[13..0] 8,11
DDR_VREF
1D8V_S3
1D8V_S3
1 2
1 2
C275
C275
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
1 2
C292
C292
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C320
C320
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
C
Put decap near power(0.9V)
and pull-up resistor
1 2
1 2
C274
C274
C276
C276
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C294
C294
C295
C295
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Place these Caps near DM1
1 2
C288
C288
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
Place these Caps near DM2
1 2
C
1 2
C278
C278
C277
C277
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
1 2
C309
C309
C308
C308
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C285
C285
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
C318
C318
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
D
Decoupling Capacitor
1 2
1 2
C279
C279
C293
C293
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
1 2
1 2
C310
C310
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
1 2
C624
C624
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
1 2
C307
C307
C325
C325
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C270
C270
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
1 2
C622
C622
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
1 2
C326
C326
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C271
C271
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
D
C327
C327
E
1 2
C328
C328
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C272
C272
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
1 2
C319
C319
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
DDR2 Termination Resistor
DDR2 Termination Resistor
DDR2 Termination Resistor
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
MYALL
MYALL
MYALL
12 52 Friday, February 10, 2006
12 52 Friday, February 10, 2006
12 52 Friday, February 10, 2006
E
SA
SA
of
SA
5V_S0
BAV99PT-GP-U
WLAN_LED#
BLT_LED#_1
1
2
3
4 5
UMA
UMA
1
2
3
4 5
G72
G72
1
2
3
4 5
UMA
UMA
1
2
3
4 5
G72
G72
1
2
3
4 5
UMA
UMA
1
2
3
4 5
G72
G72
1
2
3
4 5
UMA
UMA
1
2
3
4 5
G72
G72
BAV99PT-GP-U
3
BAV99PT-GP-U
BAV99PT-GP-U
3
RN57
RN57
SRN0J-4-GP
SRN0J-4-GP
RN53
RN53
SRN0J-4-GP
SRN0J-4-GP
RN58
RN58
SRN0J-4-GP
SRN0J-4-GP
RN54
RN54
SRN0J-4-GP
SRN0J-4-GP
RN56
RN56
SRN0J-4-GP
SRN0J-4-GP
RN52
RN52
SRN0J-4-GP
SRN0J-4-GP
RN55
RN55
SRN0J-4-GP
SRN0J-4-GP
RN51
RN51
SRN0J-4-GP
SRN0J-4-GP
D13
D13
D12
D12
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
2
DY
DY
1
2
DY
DY
1
GMCH_TXAOUT2+ 7
GMCH_TXAOUT2- 7
LVDS_TXAOUT2- 44
LVDS_TXAOUT2+ 44
GMCH_TXAOUT0+ 7
GMCH_TXAOUT0- 7
GMCH_TXAOUT1+ 7
GMCH_TXAOUT1- 7
LVDS_TXAOUT1- 44
LVDS_TXAOUT1+ 44
LVDS_TXAOUT0- 44
LVDS_TXAOUT0+ 44
GMCH_TXBOUT0- 7
GMCH_TXBOUT0+ 7
GMCH_TXBOUT1- 7
GMCH_TXBOUT1+ 7
LVDS_TXBOUT1+ 44
LVDS_TXBOUT1- 44
LVDS_TXBOUT0+ 44
LVDS_TXBOUT0- 44
GMCH_TXBOUT2- 7
GMCH_TXBOUT2+ 7
GMCH_TXBCLK- 7
GMCH_TXBCLK+ 7
LVDS_TXBCLK+ 44
LVDS_TXBCLK- 44
LVDS_TXBOUT2+ 44
LVDS_TXBOUT2- 44
0R2J-GP
0R2J-GP
R281
R281
1 2
G72
G72
0R2J-GP
0R2J-GP
R280
R280
1 2
G72
G72
GMCH_TXACLK+ 7
GMCH_TXACLK- 7
LVDS_TXACLK- 44
LVDS_TXACLK+ 44
1 MYALL DIS 0206
Q20
Q20
FDN337N-1-GP
FDN337N-1-GP
MEDIA_LED#
R357;R359
2D5V_S0
G
S D
UMA
UMA
Q21
Q21
FDN337N-1-GP
FDN337N-1-GP
WLAN_LED# 25,28
FRONT_PWRLED# 29
STDBY_LED# 29
CHARGE_LED# 29
DC_BATFULL# 29
BLT_LED#_1 29
2005/11/11 add R between connector and LED signal
6
5
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
G
S D
UMA
UMA
WLAN_LED#
FRONT_PWRLED#
STDBY_LED#
CHARGE_LED#
DC_BATFULL#
LED BD CONN
D23
D23
1
2
3 4
RB731U-1GP-U
RB731U-1GP-U
LEDBD1
LEDBD1
13
1
2
3
4
5
6
7
8
9
10
11
12
14
ACES-CON12-GP
ACES-CON12-GP
3D3V_S0
EC52
EC52
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
R253 120R2F-GP R253 120R2F-GP
R254 120R2F-GP R254 120R2F-GP
R257 120R2F-GP R257 120R2F-GP
R255 120R2F-GP R255 120R2F-GP
R256 120R2F-GP R256 120R2F-GP
R252
R252
470R2J-2-GP
470R2J-2-GP
SATA_LED# 15
C200
C200
SC1U16V3KX-2GP
SC1U16V3KX-2GP
1 2
EC21
EC21
1 2
1 2
1 2
1 2
1 2
1 2
100R2F-L1-GP-U
100R2F-L1-GP-U
1 2
1 2
DY
DY
DY
DY
C457
C457
C459
C459
SC1000P50V3JN-GP
SC1000P50V3JN-GP
SC1000P50V3JN-GP
SC1000P50V3JN-GP
SC1000P50V3JN-GP
SC1000P50V3JN-GP
1
2 3
SRN2K2J-1-GP
SRN2K2J-1-GP
RN47
RN47
4
12
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
DY
DY
LCD CONN & LED
LCD CONN & LED
LCD CONN & LED
1 2
1 2
1 2
1 2
12
1 2
R492
R492
0R2J-GP
0R2J-GP
ODD_LED# 20
1 2
1 2
5V_S0
R361
R361
10KR2J-3-GP
10KR2J-3-GP
680R2F-GP
680R2F-GP
1 2
1 2
1 2
1 2
1 2
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
C471
C471
C458
C458
C464
C464
C456
C456
C467
C467
SC1000P50V3JN-GP
SC1000P50V3JN-GP
SC1000P50V3JN-GP
SC1000P50V3JN-GP
R278
R278
1 2
0R0603-PAD
0R0603-PAD
R279
R279
1 2
0R0603-PAD
0R0603-PAD
EC51
EC51
SC MYALL
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
MYALL
MYALL
MYALL
LED-Y-47-GP
LED-Y-47-GP
LED-G-62-GP
LED-G-62-GP
LED-Y-47-GP
LED-Y-47-GP
LED-Y-47-GP
LED-Y-47-GP
LED-G-62-GP
LED-G-62-GP
LED5
LED5
LED-B-27-U-GP
LED-B-27-U-GP
MYALL SB
MEDIA_LED#
SC1000P50V3JN-GP
SC1000P50V3JN-GP
1 MYALL DIS 0206
LCDVDD
Layout 40 mil
R276
R276
3D3V_S0
1 2
R277
R277
10KR2J-2-GP
10KR2J-2-GP
R275 0R2J-L1-GP
R275 0R2J-L1-GP
D
D
2 3
G72
G72
S
S
1 2
UMA
UMA
1 2
G72
G72
2N7002PT-U
2N7002PT-U
Q19
Q19
1KR2J-1-GP
1KR2J-1-GP
SB
1 2
GMCH_LCDVDD_ON 7
G72
G72
NV_LCDVDD_ON# 47
1
G
G
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
DY
DY
R274
R274
0R2J-L1-GP
0R2J-L1-GP
LCDVDD_ON_1
C367
C367
1 2
LCD/INVERTER CONN
U18
U18
1
OUT
2
GND
ON/OFF#3IN
1 2
C370
C370
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
IN
GND
AAT4280IGU-1-T1GP
AAT4280IGU-1-T1GP
6
5
4
SC MYALL CHANGE 2006.01.11
LCD1
LCD1
46
45
47
48
49
50
51
52
53
54 55
IPEX-CON44-2-GP
IPEX-CON44-2-GP
NP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NP2
EDID_CLK
EDID_DAT
BRIGHTNESS 29
C360 SC100P50V2JN-U C360 SC100P50V2JN-U
DY
DY
SC10U10V5ZY
SC10U10V5ZY
LCD_TXACLKLCD_TXACLK+
LCD_TXAOUT2LCD_TXAOUT2+
LCD_TXAOUT1LCD_TXAOUT1+
LCD_TXAOUT0LCD_TXAOUT0+
LCD_TXBOUT0LCD_TXBOUT0+
LCD_TXBOUT1LCD_TXBOUT1+
LCD_TXBOUT2LCD_TXBOUT2+
LCD_TXBCLKLCD_TXBCLK+
C358 SC100P50V2JN-U C358 SC100P50V2JN-U
1 2
FPBACK 29
1 2
1 2
1 2
C363
C363
C364
C364
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
3D3V_S0
EVEN CHANNEL
ODD CHANNEL
SC MYALL
1 2
C655
C655
SC10U35V0ZY-GP
SC10U35V0ZY-GP
LCDVDD
1 2
DY
DY
C361
C361
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
1 2
EC65
EC65
SCD1U50V3ZY
SCD1U50V3ZY
DY
DY
DCBATOUT
3D3V_S0
1 2
C371
C371
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
LCD_TXAOUT0+
LCD_TXAOUT0LCD_TXAOUT1+
LCD_TXAOUT1-
LCD_TXAOUT2+
LCD_TXAOUT2LCD_TXACLK+
LCD_TXACLK-
LCD_TXBOUT0LCD_TXBOUT0+
LCD_TXBOUT1LCD_TXBOUT1+
LCD_TXBOUT2LCD_TXBOUT2+
LCD_TXBCLKLCD_TXBCLK+
G72_LCD_EDID_DAT 47
CLK_DDC_EDID 7
G72_LCD_EDID_CLK 47
DAT_DDC_EDID 7
LED
LED6
LED6
A K
LED3
LED3
1 2
LED8
LED8
A K
LED4
LED4
A K
LED7
LED7
1 2
1 2
IDE_LED# 20
3D3V_S0
4
RN61
RN61
SRN10KJ-5-GP
SRN10KJ-5-GP
1
2 3
CAP_LED# 29
NUM_LED# 29
WLAN_LED# 25,28
BLT_LED#_2 29
WIRELESS_BTN# 29
BLT_BTN# 29
INT_MIC 27
SC1000P50V3JN-GP
SC1000P50V3JN-GP
CAP_LED# /
NUM_LED# /
IDE_LED# DY
1000p near
LEDBD1 BY EMI
REQUEST
EDID_CLK
EDID_DAT
13 52 Friday, February 10, 2006
13 52 Friday, February 10, 2006
13 52 Friday, February 10, 2006
of
of
of
5V_S0
5V_S5
5V_S0
220R2J-L2-GP
220R2J-L2-GP
220R2J-L2-GP
220R2J-L2-GP
220R2J-L2-GP
220R2J-L2-GP
R350
R350
R353
R353
R359
R359
R357
R357
R356
R356
SA
SA
SA
CRT CONNECTOR
0R2J-GP
CRT_RED 43
GMCH_RED 7
CRT_GREEN 43
GMCH_GREEN 7
CRT_BLUE 43
GMCH_BLUE 7
G72
G72
UMA
UMA
G72
G72
UMA
UMA
G72
G72
UMA
UMA
0R2J-GP
0R2J-GP
0R2J-GP
0R2J-GP
0R2J-GP
0R2J-GP
0R2J-GP
0R2J-GP
0R2J-GP
0R2J-GP
0R2J-GP
R260
R260
1 2
R259
R259
1 2
R267
R267
1 2
R266
R266
1 2
R4
R4
1 2
R5
R5
1 2
GMCH_O_RED
GMCH_O_GREEN
GMCH_O_BLUE
1 2
R258
R258
Hsync & Vsync level shift
0R2J-GP
0R2J-GP
0R2J-GP
0R2J-GP
1 2
1 2
0R2J-GP
0R2J-GP
1 2
0R2J-GP
0R2J-GP
1 2
R16
R16
R15
R15
G72
G72
UMA
UMA
HSYNC 43
GMCH_HSYNC 7
VSYNC 43
GMCH_VSYNC 7
R14
R14
R13
R13
G72
G72
UMA
UMA
SC33P50V2JN-3GP
SC33P50V2JN-3GP
GMCH_O_HSYNC
GMCH_O_VSYNC
C12
C12
DY
DY
14
5 6
7
1 2
4
U1B TSAHCT125PW-GP U1B TSAHCT125PW-GP
1 2
50 Ohm Impedance
1 2
1 2
R265
R265
R1
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
5V_S0
1 2
14
1
2 3
7
C11
C11
SC33P50V2JN-3GP
SC33P50V2JN-3GP
DY
DY
1 2
EC45
EC45
SC3P50V2CN-1-GP
SC3P50V2CN-1-GP
150R2F-1-GPR1150R2F-1-GP
DY
DY
C5
C5
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
TSAHCT125PW-GP
TSAHCT125PW-GP
U1A
U1A
Ferrite bead impedance: 75ohm@100MHz
1 2
EC47
EC47
SC3P50V2CN-1-GP
SC3P50V2CN-1-GP
DY
DY
CRT_HSYNC1
CRT_VSYNC1
1 2
EC3
EC3
SC3P50V2CN-1-GP
SC3P50V2CN-1-GP
DY
DY
CRT_HSYNC1
CRT_VSYNC1
L20
L20
1 2
BLM18BA100SN1DGP
BLM18BA100SN1DGP
L19
L19
1 2
BLM18BA100SN1DGP
BLM18BA100SN1DGP
L1
L1
1 2
BLM18BA100SN1DGP
BLM18BA100SN1DGP
EC1
EC1
75 Ohm Impedance
DAT_DDC1_5
CLK_DDC1_5
1 2
1 2
EC40
EC40
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
CRT_R
CRT_G
CRT_B
EC44
EC44
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
1 2
EC43
EC43
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
1 2
EC2
EC2
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
CRT_DEC 29
R552
R552
DY
DY
0R2J-GP
0R2J-GP
1 2
5V_S0
1 2
R550
R550
DY
DY
10KR2J-3-GP
10KR2J-3-GP
1 2
5V_CRT_S0 add
0.1u near CRT1
request by EMI
R551
R551
0R2J-GP
0R2J-GP
1 2
CRT_R
DAT_DDC1_5
CRT_B
CRT_VSYNC1
ESD Protection Diode ESD Protection Diode
5V_S0
BAV99PT-GP-U
BAV99PT-GP-U
3
DY
DY
BAV99PT-GP-U
BAV99PT-GP-U
3
DY
DY
BAV99PT-GP-U
BAV99PT-GP-U
3
DY
DY
2
D16
D16
1
2
D15
D15
1
2
D1
D1
1
CRT_R
CRT_G
1 2
1 2
EC41
EC41
EC42
EC42
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
CRT_B
17
6
1
12
8
3
14
10
5
16
VIDEO-15-21-U1GP
VIDEO-15-21-U1GP
CRT1
CRT1
MH1
11
7
2
13
9
4
15
MH2
CRT_G
CRT_HSYNC1
5V_CRT_S0
5V_CRT_S0
1 2
CLK_DDC1_5
C1
C1
SCD1U16V3KX-3GP
SCD1U16V3KX-3GP
DDC_CLK & DATA level shift
5V_S0
R264
R264
0R2J-2-GP
0R2J-2-GP
G
Q18
Q18
5V_CRT_S0
1
2 3
SRN2K2J-1-GP
SRN2K2J-1-GP
RN43
RN43
4
DAT_DDC1_5
CLK_DDC1_5
2D5V_S0 3D3V_S0
1
2 3
SRN2K2J-1-GP
SRN2K2J-1-GP
RN45
RN45
4
G72
G72
UMA
UMA
0R2J-GP
0R2J-GP
R2
R2
G72_CRT_EDID_DAT 43
GMCH_DDCDATA 7
G72_CRT_EDID_CLK 43
GMCH_DDCCLK 7
1 2
0R2J-GP
0R2J-GP
R3
R3
1 2
G72
G72
UMA
UMA
0R2J-GP
0R2J-GP
R262
R262
1 2
0R2J-GP
0R2J-GP
R261
R261
1 2
G72
G72
UMA
UMA
1
2 3
RN44
RN44
4
SRN2K2J-1-GP
SRN2K2J-1-GP
EDIT_DAT_Q_S
S D
FDN337N-1-GP
FDN337N-1-GP
EDIT_CLK_Q_S
3D3V_S0 2D5V_S0
1 2
1 2
R263
R263
0R2J-2-GP
0R2J-2-GP
UMA
UMA
G72
G72
G
Q1
Q1
S D
FDN337N-1-GP
FDN337N-1-GP
1 2
EC46
EC46
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
DY
DY
D14
D14
5V_CRT_S0
2 1
RB751V-40-1-GP
RB751V-40-1-GP
MYALL SC CHANGE
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRT Connector
CRT Connector
CRT Connector
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
MYALL
MYALL
MYALL
14 52 Friday, February 10, 2006
14 52 Friday, February 10, 2006
14 52 Friday, February 10, 2006
of
of
SA
SA
SA
A
B
C
D
E
SC20P50V2JN-1GP
SC20P50V2JN-1GP
1 2
C587
C587
4
3D3V_AUX_S5
D8
D8
BATBAT
4
BAT_D
1 2
123
1
2
BAT54C-1-GP
BAT54C-1-GP
RTC1
RTC1
ACES-CON3-GP
ACES-CON3-GP
5
3
4 4
R199
R199
1KR2J-1-GP
1KR2J-1-GP
3 3
2nd source: 20.F0736.003
BAT
EC64 SCD01U16V2KX-3GP
EC64 SCD01U16V2KX-3GP
1 2
DY
DY
RTC_AUX_S5
1 2
C268
C268
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
R430 20KR2F-L-GP R430 20KR2F-L-GP
1 2
R200 1MR2J-1-GP R200 1MR2J-1-GP
1 2
C583
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C583
1 2
MYALL SB
ACZ_BTCLK_MDC 21
ACZ_BITCLK 26
ACZ_SYNC 21,26
ACZ_RST# 21,26
ACZ_SDATAOUT 21,26
X-32D768KHZ-38GPU
X-32D768KHZ-38GPU
INTRUDER# 19
SC MYALL
X5
X5
1 2
C586
C586
SC20P50V2JN-1GP
SC20P50V2JN-1GP
1 2
1 2
1 2
1 2
1 2
R226 39R2J-L-GP R226 39R2J-L-GP
SATA_RXN0 20
SATA_RXP0 20
SATA_TXN0 20
SATA_TXP0 20
2 3
R233 39R2J-L-GP R233 39R2J-L-GP
R232 39R2J-L-GP R232 39R2J-L-GP
R466
R466
200R2J-L1-GP
200R2J-L1-GP
ACZ_SDATAIN0 26
ACZ_SDATAIN1 21
SATA_LED# 13
1 2
R429
R429
10MR2J-L-GP
10MR2J-L-GP
1
R229
R229
1 2
10KR2J-3-GP
10KR2J-3-GP
ACZ_SYNC_R
R467 39R2J-L-GP R467 39R2J-L-GP
ACZ_RST#_R
TP103 TPAD28 TP103 TPAD28
ACZ_SDATAOUT_R
R197 0R0603-PAD R197 0R0603-PAD
1 2
R202 0R0603-PAD R202 0R0603-PAD
1 2
1 MYALL DIS 0206
RTC_AUX_S5
2 2
1 2
R189
R189
100KR2J-1-GP
100KR2J-1-GP
1 2
R190
R190
0R2J-GP
0R2J-GP
DY
DY
P.H. for internal VCCSUS1_5
INTVRMEN
Place within 500 mils
CLK_PCIE_SATA# 3
CLK_PCIE_SATA 3
1 2
R196
R196
24D9R2F-L-GP
24D9R2F-L-GP
SATA_RBIAS#_PN
IDE_PDIORDY 20
INT_IRQ14 20
IDE_PDDACK# 20
IDE_PDIOW# 20
IDE_PDIOR# 20
MYALL SB CHANGE TO 20P
FROM 22P;C586/587
RCT_X1
Y1
AA2
AA3
AA5
D12
B12
D11
B11
E12
E11
C13
C12
C11
E13
C10
A10
B10
AC19
AE3
AD3
AG2
AF2
AD7
AC7
AF6
AG6
AC2
AC1
AG11
AF11
AF16
AB16
AB15
AC14
AE16
Y2
F13
F12
B9
F11
F10
C9
RTCX1
RTCX2
RTCRST#
INTRUDER#
INTVRMEN
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LAN_CLK
LAN_RSTSYNC
LANRXD[0]
LANRXD[1]
LANRXD[2]
LANTXD[0]
LANTXD[1]
LANTXD[2]
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN[0]
ACZ_SDIN[1]
ACZ_SDIN[2]
ACZ_SDO
SATALED#
SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP
SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
RCT_X2
RCT_RST#
INTRUDER#
INTVRMEN
BIT_CLK
U61A
U61A
LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]
LPC
LPC
RTC LAN
RTC LAN
LDRQ[0]#
LDRQ[1]#/GPI[41]
LFRAME#/FWH[4]
A20GATE
CPUSLP#
DPRSLP#
DPSLP#
CPU
CPU
CPUPWRGD/GPO[49]
IGNNE#
INIT3_3V#
STPCLK#
THRMTRIP#
SATA AC-97/AZALIA
SATA AC-97/AZALIA
IDE
IDE
DDREQ
A20M#
FERR#
INIT#
INTR
RCIN#
SMI#
DA[0]
DA[1]
DA[2]
DCS1#
DCS3#
DD[0]
DD[1]
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]
NMI
P2
N3
N5
N4
N6
P4
P3
AF22
AF23
AE27
AE24
AD27
AF24
AG25
AG26
AE22
AF27
AG24
AD23
AF25
AG27
AE26
AE23
AC16
AB17
AC17
AD16
AE17
AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13
AB14
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LDRQ#0
LPC_LDRQ1
H_FERR_R
H_THERMTRIP_R
1D05V_S0
1 2
H_DPSLP#
LPC_LAD[0..3] 29,31
TP70 TPAD28 TP70 TPAD28
TP69 TPAD28 TP69 TPAD28
LPC_LFRAME# 29,31
KA20GATE_1 29
H_A20M# 4
H_CPUSLP# 4,6
H_DPRSLP# 4
H_DPSLP# 4
R413 56R2J-4-GP R413 56R2J-4-GP
1 2
H_PWRGD 4,19
H_IGNNE# 4
H_INTR 4
KBRCIN#_1 29
H_NMI 4
H_SMI# 4
H_STPCLK# 4
1 2
IDE_PDA0 20
IDE_PDA1 20
IDE_PDA2 20
IDE_PDCS1# 20
IDE_PDCS3# 20
IDE_PDD0 20
IDE_PDD1 20
IDE_PDD2 20
IDE_PDD3 20
IDE_PDD4 20
IDE_PDD5 20
IDE_PDD6 20
IDE_PDD7 20
IDE_PDD8 20
IDE_PDD9 20
IDE_PDD10 20
IDE_PDD11 20
IDE_PDD12 20
IDE_PDD13 20
IDE_PDD14 20
IDE_PDD15 20
IDE_PDDREQ 20
R198
R198
56R2J-4-GP
56R2J-4-GP
DY
DY
R195
R195
56R2J-4-GP
56R2J-4-GP
FWH_INIT# 31
1 2
C265
C265
SC4700P50V2KX-1GP
SC4700P50V2KX-1GP
DY
DY
10KR2J-3-GP
10KR2J-3-GP
R210
LPC_LDRQ1
KBRCIN#_1
KA20GATE_1
1D05V_S0
H_INIT# 4
Layout Note: R632 needs to placed
within 2" of ICH6, R634 must be placed
within 2" of R632 w/o stub.
1 2
1
2 3
RN16
RN16
SRN10KJ-5-GP
SRN10KJ-5-GP
1 2
R407
R407
56R2J-4-GP
56R2J-4-GP
1D05V_S0
1 2
R210
R187
R187
75R2F-2-GP
75R2F-2-GP
3D3V_S0
4
H_FERR# 4
PM_THRMTRIP-I# 4,7,19
1 1
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
ICH6-M (1 of 4)
ICH6-M (1 of 4)
ICH6-M (1 of 4)
MYALL
MYALL
MYALL
15 52 Friday, February 10, 2006
15 52 Friday, February 10, 2006
15 52 Friday, February 10, 2006
E
of
SA
SA
SA
A
U61B
AD[0]
PCI
PCI
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
FRAME#
Interrupt I/F
Interrupt I/F
PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#
RESERVED
RESERVED
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
U61B
REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#
REQ[4]#/GPI[40]
GNT[4]#/GPO[48]
REQ[5]#/GPI[1]
GNT[5]#/GPO[17]
REQ[6]#/GPI[0]
GNT[6]#/GPO[16]
C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
PLTRST#
PCICLK
PME#
PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#/GPI[4]
PIRQ[H]#/GPI[5]
RSVD[6]
RSVD[7]
RSVD[8]
TP[3]
PCI_REQ#0
L5
PCI_GNT#0
C1
PCI_REQ#1
B5
B6
PCI_REQ#2
M5
F1
PCI_REQ#3
B8
C8
BOOT_BLOCK#
F7
E7
PCI_REQ#5
E8
PCI_GNT#5
F6
PCI_REQ#6
B7
PCI_GNT#6
D8
J6
H6
G4
G2
A3
E1
R450 10R2J-2-GP R450 10R2J-2-GP
R2
C3
E3
PCI_LOCK#
C5
G5
J1
J2
PLT_RST1#_1
R5
G6
P6
D9
C7
C6
M3
AD9
AF8
AG8
U3
PCI_AD[31..0] 22,24,28
4 4
PCI_FRAME# 22,24,28
INT_PIRQB# 24
3 3
TP64 TPAD28 TP64 TPAD28
TP60 TPAD28 TP60 TPAD28
TP59 TPAD28 TP59 TPAD28
TP57 TPAD28 TP57 TPAD28
TP65 TPAD28 TP65 TPAD28
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
AC5
AD5
AG4
AC9
AF4
E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4
J3
N2
L2
M1
L3
ICH6 Pullups
RN32
INT_PIRQD#
INT_PIRQF#
PCI_REQ#5
PCI_SERR#
3D3V_S0
PCI_LOCK#
INT_PIRQG#
PCI_DEVSEL#
PCI_IRDY#
3D3V_S0
2 2
PCI_REQ#0
INT_PIRQH#
INT_PIRQC#
INT_PIRQA#
3D3V_S0
SMLINK1
SMLINK0
SMB_ALERT#
SMB_LINK_ALERT#
3D3V_S5
1 1
RN32
1
2
3
4
5 6
SRN10KJ-L3-GP
SRN10KJ-L3-GP
RN40
RN40
1
2
3
4
5 6
SRN10KJ-L3-GP
SRN10KJ-L3-GP
RN29
RN29
1
2
3
4
5 6
SRN10KJ-L3-GP
SRN10KJ-L3-GP
RN24
RN24
1
2
3
4
5 6
SRN10KJ-L3-GP
SRN10KJ-L3-GP
10
PCI_FRAME#
9
PCI_STOP#
8
PCI_TRDY#
7
PCI_PERR#
10
PCI_REQ#3
9
INT_PIRQE#
8
PM_CLKRUN#
7
PCI_REQ#2
10
INT_SERIRQ
9
THRM#
8
MCH_SYNC#
7
INT_PIRQB#
10
9
8
7
3D3V_S0
3D3V_S0
3D3V_S0
DBRESET#
PM_RI#
CHK_PW#
ICH6_WAKE#
PM_BATLOW#_R
ECSMI#
ECSWI#
PM_SLP_S3#_ICH
PM_DPRSLPVR_R
3D3V_S5
1 2
R204 1KR2J-1-GP R204 1KR2J-1-GP
1 2
R205 8K2R2J-3-GP R205 8K2R2J-3-GP
1 2
R207 100KR2J-1-GP
R207 100KR2J-1-GP
1 2
R209 100KR2J-1-GP
R209 100KR2J-1-GP
1 MYALL DIS 0206
R214 0R0603-PAD R214 0R0603-PAD
1 2
DY
DY
1 2
TP76 TPAD28 TP76 TPAD28
TP73 TPAD28 TP73 TPAD28
1 2
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
DY
DY
DY
DY
R193
R193
100KR2J-1-GP
100KR2J-1-GP
B
PCI_REQ#0 24
PCI_GNT#0 24
PCI_REQ#1 28
PCI_GNT#1 28
PCI_REQ#2 22
PCI_GNT#2 22
PCI_C/BE#0 22,24,28
PCI_C/BE#1 22,24,28
PCI_C/BE#2 22,24,28
PCI_C/BE#3 22,24,28
PCI_DEVSEL# 22,24,28
PCI_PERR# 22,24,28
PCI_SERR# 22,24,28
PCI_STOP# 22,24,28
PCI_TRDY# 22,24,28
R211 47R2J-2-GP R211 47R2J-2-GP
1 2
CLK_ICHPCI 3
ICH_PME# 22
INT_PIRQE# 22
INT_PIRQF# 28
INT_PIRQG# 24
TP61 TPAD28 TP61 TPAD28
TP56 TPAD28 TP56 TPAD28
TP55 TPAD28 TP55 TPAD28
TP67 TPAD28 TP67 TPAD28
3D3V_S5
PCI_REQ#1
PCI_REQ#6
BOOT_BLOCK#
ECSCI#_1
R213
R213
100KR2J-1-GP
100KR2J-1-GP
DY
DY
1 2
3D3V_S0
TP72 TPAD28 TP72 TPAD28
PCI_IRDY# 22,24,28
PCI_PAR 22,24,28
1 2
Int. PH
1
2
3
4 5
R191 100KR2J-1-GP R191 100KR2J-1-GP
Need to check what power we will use
PM_SLP_S3# 18,29,32,36,37,41,52
RN17
RN17
SRN10KJ-4-GP
SRN10KJ-4-GP
1
8
2
7
3
6
4 5
PCIRST1# 22,24,28
C595
C595
SC22P50V2JN-4GP
SC22P50V2JN-4GP
PLT_RST1# 7,18,25,29,31,42,47
PM_CLKRUN# 22,24,28,29
RN85
RN85
SRN10KJ-4-GP
SRN10KJ-4-GP
1 2
PM_DPRSLPVR 34
3D3V_S0
8
7
6
C
?CHECK SATA PRESENT
SATA0_R2
SATA0_R3
SATA0_R0
SATA0_R1
SMB_CLK 18,25
SMB_DATA 18,25
ACZ_SPKR 26
PM_SUS_STAT# 29
PM_BMBUSY# 7
ECSCI#_1 29
ECSMI# 29
TP71 TPAD28 TP71 TPAD28
ECSWI# 29
PM_STPPCI# 3
TP66 TPAD28 TP66 TPAD28
PM_STPCPU# 3,34
TP63 TPAD28 TP63 TPAD28
KBC_SLP_WAKE 29
PCB_VER1 31
PCB_VER0 31
CHK_PW# 31
INT_SERIRQ 24,28,29
THRM# 19
VGATE_PWRGD 7,32
CLK_ICH14 3
CLK48_ICH 3
PM_SUS_CLK 18
PM_SLP_S4# 29,37
PWROK 19
PM_PWRBTN# 29
RSMRST#_KBC 29,32
TP58 TPAD28 TP58 TPAD28
TP62 TPAD28 TP62 TPAD28
TP68 TPAD28 TP68 TPAD28
1 2
R192
R192
100R2J-2-GP
100R2J-2-GP
100KR2J-1-GP
100KR2J-1-GP
1 2
LAN_RST#
R201
R201
PM_RI#
SATA0_R0
SATA0_R1
SATA0_R2
SATA0_R3
SMB_LINK_ALERT#
SMLINK0
SMLINK1
MCH_SYNC#
DBRESET#
SMB_ALERT#
ICH_GPI12
ICH_GPO19
ICH_GPO21
KBC_SLP_WAKE
R215 10KR2J-3-GP R215 10KR2J-3-GP
CHK_PW#
ICH_GPIO33
ICH_GPIO34
ICH6_WAKE#
THRM#
PM_SLP_S3#_ICH
PM_SLP_S5#
PM_DPRSLPVR_R
PM_BATLOW#_R
PM_PWRBTN#
1 2
1 2
T2
AF17
AE18
AF18
AG18
Y4
W5
Y5
W4
U6
AG21
F8
W3
U2
AD19
AE19
R1
W6
M2
R6
AC21
AB21
AD22
AD20
AD21
V3
P5
R3
T3
AF19
AF20
AC18
U5
AB20
AC20
AF21
E10
A27
V6
T4
T5
T6
AA1
AE20
V2
U1
V5
Y3
R203
R203
10KR2J-3-GP
10KR2J-3-GP
RI#
SATA[0]GP/GPI[26]
SATA[1]GP/GPI[29]
SATA[2]GP/GPI[30]
SATA[3]GP/GPI[31]
SMBCLK
SMBDATA
LINKALERT#
SMLINK[0]
SMLINK[1]
MCH_SYNC#
SPKR
SUS_STAT#/LPCPD#
SYS_RESET#
BMBUSY#
GPI[7]
GPI[8]
SMBALERT#/GPI[11]
GPI[12]
GPI[13]
STP_PCI#
GPO[19]
STP_CPU#
GPO[21]
GPO[23]
GPIO[24]
GPIO[25]
GPIO[27]
GPIO[28]
CLKRUN#
GPIO[33]
GPIO[34]
WAKE#
SERIRQ
THRM#
VRMPWRGD
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
DPRSLPVR
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
D
U61C
U61C
ICH_PCIE_RXN
H25
PERn[1]
PERp[1]
PETn[1]
PETp[1]
PERn[2]
PERp[2]
PETn[2]
PETp[2]
PERn[3]
PERp[3]
PETn[3]
GPIO
GPIO
PETp[3]
PCI-EXPRESS Direct Media Interface
PCI-EXPRESS Direct Media Interface
PERn[4]
PERp[4]
PETn[4]
PETp[4]
DMI[0]RXN
DMI[0]RXP
DMI[0]TXN
DMI[0]TXP
DMI[1]RXN
DMI[1]RXP
DMI[1]TXN
DMI[1]TXP
DMI[2]RXN
DMI[2]RXP
DMI[2]TXN
DMI[2]TXP
DMI[3]RXN
DMI[3]RXP
DMI[3]TXN
DMI[3]TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]
OC[0]#
OC[1]#
OC[2]#
OC[3]#
USBP[0]N
USBP[0]P
USBP[1]N
USBP[1]P
USBP[2]N
USBP[2]P
USBP[3]N
USBP[3]P
USBP[4]N
USBP[4]P
USBP[5]N
USBP[5]P
USBP[6]N
USB
USB
USBP[6]P
USBP[7]N
USBP[7]P
POWER MGT CLOCKS
POWER MGT CLOCKS
USBRBIAS#
USBRBIAS
ICH_PCIE_RXP
H24
ICH_PCIE_TXN
G27
ICH_PCIE_TXP
G26
K25
K24
J27
J26
M25
M24
L27
L26
P24
P23
N27
N26
T25
T24
R27
R26
V25
V24
U27
U26
Y25
Y24
W27
W26
AB24
AB23
AA27
AA26
AD25
AC25
F24
F23
C23
D23
C25
C24
C27
B27
B26
C26
C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14
A22
B22
Place within 500 mils of ICH
Layout Note:
PCIE AC coupling caps
need to be within 250 mils of the driver.
C299
C299
1 2
C298
C298
1 2
C306
C306
1 2
C305
C305
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7
DMI_RXN1 7
DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7
DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7
DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7
CLK_PCIE_ICH# 3
CLK_PCIE_ICH 3
DMI_IRCOMP_R
USB_OC#3
USB_RBIAS_PN
PCIE_RXN1 25
PCIE_RXP1 25
PCIE_TXN1 25
PCIE_TXP1 25
Layout Note:
PCIE AC coupling caps
need to be within 250 mils of the driver.
MYALL SB
USB_OC#6 21
USB_OC#0 21
USB_OC#1 21
MYALL SB
USBPN0 21
USBPP0 21
USBPN6 21
USBPP6 21
USBPN7 21
USBPP7 21
USBPN4 21
USBPP4 21
TP75 TPAD28 TP75 TPAD28
TP79 TPAD28 TP79 TPAD28
USBPN3 25
USBPP3 25
USBPN1 21
USBPP1 21
USBPN2 21
USBPP2 21
R228
R228
1 2
22D6R2F-L1-GP
22D6R2F-L1-GP
ICH6-M Strapping Options
REF
R7F9
R7F8
R7F7
<Core Design>
<Core Design>
<Core Design>
FUNCTION
No Reboot
A16 Swap
Override
Boot BIOS
DEFAULT OPTIONAL OVERRIDE
NO_STUFF
NO_STUFF
NO_STUFF
E
MiniC
1D5V_S0
Place within 500 mils of ICH
1 2
R224
R224
24D9R2F-L-GP
24D9R2F-L-GP
USB_OC#3
4 5
USB_OC#1
3
USB_OC#6
2
USB_OC#0
1
3D3V_S0
1 2
DY
DY
R223 1KR2J-1-GP
R223 1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
R225
R225
1 2
DY
DY
1KR2J-1-GP
1KR2J-1-GP
R227
R227
1 2
DY
DY
100KR2J-1-GP
100KR2J-1-GP
R428
R428
1 2
DY
DY
STUFF
STUFF
STUFF
SRN10KJ-4-GP
SRN10KJ-4-GP
6
7
8
RN39
RN39
R7F9
R7F8
PCI_GNT#6
R7F7
PCI_GNT#5
PWROK
3D3V_S5
ACZ_SPKR
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A
B
C
D
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
ICH6-M (2 of 4)
ICH6-M (2 of 4)
ICH6-M (2 of 4)
MYALL
MYALL
MYALL
SA
SA
16 52 Friday, February 10, 2006
16 52 Friday, February 10, 2006
16 52 Friday, February 10, 2006
E
of
SA