Acer Aspire 4715 Schematics
A
B
Volvi2 Block Diagram
C
D
E
Project code: 91.4X101.001
PCB P/N : 48.4X101.011
REVISION : 07220-1
4 4
CLK GEN.
RTM875T-605
(ICS 9LPRS502)
DDR2
3
533/667MHz
533/667 MHz
12,13
DDR2
3 3
2 2
1 1
533/667 MHz
Audio BD
MIC In
25
INT.MIC
25
INT.SPKR
Line Out
(No-SPDIF)
REVISION:07551-1
RJ11
22
12,13
Codec
ALC268
OP AMP
APA2031
OP AMP
G1412
MDC Card
533/667MHz
AZALIA
24
25
25
MODEM
21
Mobile CPU
Merom 479
Celeron M
2.0G : 71.MEROM.A0U
2.33G : 71.MEROM.B0U
HOST BUS
533/800MHz@1.05V
4, 5
Intel GL960/GM965
AGTL+ CPU I/F
DDR Memory I/F
INTEGRATED GRAHPICS
GL960:71.GL960.A0U, QN79
GM965:KI.96501.005, SLA5T
X4 DMI
400MHz
LVDS, CRT I/F
6,7,8,9,10,11
C-Link0
ICH8M
6 PCIe ports
PCI/PCI BRIDGE
ACPI 1.1
3 SATA
1 PATA 66/100
10 USB 2.0/1.1 ports
ETHERNET (10/100/1000MbE)
High Definition Audio
LPC I/F
Serial Peripheral I/F
Matrix Storage Technology(DO)
Active Managemnet Technology(DO)
71.ICH8M.A0U, QN23
16,17,18,19
USB
USB
1 PORT
HDD
SATA
21
PATA
CDROM
21
G792
PCIex1
LPC BUS
USB BD
2 PORT
21
REVISION:07570-1
KBC
Winbond
WPC8763L
Touch
Pad
27 27
21
-1-0703
20
SVIDEO/COMP
LVDS
RGB CRT
10/100 LAN
Marvell 88E8039
Mini Card
abgn/bg
New card
SPI I/F
26
INT.
KB
CRT
15
14
15
TVOUT
14" WXGA
LCD
TXFM RJ45
22
23
PWR SW
23 23
P2231NFC
BIOS
W25X80-VSS
27
TOP
VCC
S
S
GND
BOTTOM
LPC
DEBUG
CONN.
PCB STACKUP
2222
36
RTM
RTM
RTM
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet
Date: Sheet
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
SYSTEM DC/DC
MAX8744
INPUTS
DCBATOUT
5V_S5(6A)
3D3V_S5(6A)
SYSTEM DC/DC
TPS51124
INPUTS OUTPUTS
DCBATOUT
TPS51100(G2997)
1D8V_S3
APL5913
1D8V_S3 1D25V_S0
G909
5V_AUX_S5 3D3V_AUX_S5
APL5915
1D8V_S3 1D5V_S0
CHARGER
DCBATOUT
CPU DC/DC
INPUTS
DCBATOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Volvi2
Volvi2
Volvi2
1D05V_S0(8A)
1D8V_S3(12A)
DDR_VREF_S0
(1.5A)
DDR_VREF_S3
(1.5A)
(100mA)
(1.5A)
MAX8731
OUTPUTSINPUTS
CHG_PWR
18V 4.0A
UP+5V
5V 100mA
MAX8770
OUTPUTS
VCC_CORE_S0
0~1.3V
47A
136Thursday, July 05, 2007
136Thursday, July 05, 2007
136Thursday, July 05, 2007
OUTPUTS
of
of
31
32
33
33
28
33
34
30
-1
-1
-1
A
B
C
D
E
ICH8M Functional Strap Definitions
Signal
HDA_SDOUT
HDA_SYNC
4 4
GNT2#
GPIO20
GNT1#/
GPIO51
GNT3#
GNT0#/
SPI_CS1#
INTVRMEN
3 3
LAN100_SLP
SATALED#
SPKR
TP3
GPIO33/
HDA_DOCK
_EN#
Usage/When Sampled
XOR Chain Entrance/
PCIE Port Config1 bit1,
Rising Edge of PWROK
PCIE config1 bit0,
Rising Edge of PWROK.
PCIE config2 bit0,
Rising Edge of PWROK.
Reserved
ESI Strap (Server Only)
Rising Edge of PWROK
Top-Block
Swap Override.
Rising Edge of PWROK.
Boot BIOS Destination
Selection.
Rising Edge of PWROK.
Integrated VccSus1_05,
VccSus1_5 and VccCL1_5
VRM Enable/Disable.
Always sampled.
Integrated VccLAN1_05
and VccCL1_05 VRM
Enable/Disable.
Always sampled.
PCI Express Lane
Reversal. Rising Edge
of PWROK.
No Reboot.
Rising Edge of PWROK.
XOR Chain Entrance.
Rising Edge of PWROK.
Flash Descriptor
Security Override Strap
Rising Edge of PWROK
Allows entrance to XOR Chain testing when TP3
pulled low.When TP3 not pulled low at rising edge
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h)
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
This signal has a weak internal pull-up.
Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)
This signal should not be pulled high.
ESI compatible mode is for server platforms only.
This signal should not be pulled low for desttop
and mobile.
Sampled low:Top-Block Swap mode(inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
Enables integrated VccSus1_05, VccSus1_5 and
VccCL1_5 VRM's when sampled high
Enables integrated VccLAN1_05 and VccCL1_05 VRM's
when sampled high
Signal has weak internal pull-up. Sets bit 27
of MPC.LR(Device 28:Function 0:Offset D8)
If sampled high, the system is strapped to the
"No Reboot" mode(ICH8 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.
This signal should not be pull low unless using
XOR Chain testing.
This signal has a weak internal pull-up.
Sampled low:the Flash Descriptor Security will be
overridden. If high,the security measures will be
in effect.This should only be used in manufacturing
environments.
ICH8-M EDS 21762 2.0V1
Comment
page 16
2 2
ICH8M IDE Integrated Series
Termination Resistors
DIOR#,DIOW#,DD[15:0],
DDACK#, IORDY,
DCS3#,
IDEIRQ
DA[2:0],
DREQ,
DCS1#,
approximately 33 ohm
ICH8M Integrated Pull-up
and Pull-down Resistors
SIGNAL Resistor Type/Value
HDA_BIT_CLK
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GNT[3:0]
GPIO[20]
LDA[3:0]#/FHW[3:0]#
LAN_RXD[2:0]
LDRQ[0]
LDRQ[1]/GPIO23
PME#
PWRBTN#
SATALED#
SPI_CS1#
SPI_CLK
SPI_MOSI
SPI_MISO
TACH_[3:0]
SPKR
TP[3]
USB[9:0][P,N]
CL_RST#
ICH8-M EDS 21762 2.0V1
PULL-DOWN 20K
NONE
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K ?
PULL-UP 20K
PULL-UP 10K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 15K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K ?
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 15K
PULL-UP 13K
History
2007/05/02
1 Based on Tahoe to modify schematics.
===========================================================
2007/05/14
1.Page 34:Replace "D25" with "BAS16-1-GP".
2.Page 27:Replace "R485" with "2K7R2j".
3.Page 27:DY:C379"
4.Page 27:Add "C682" D1u capacitor on "LID1.PIN1"
5.Page 27:Replace "R238" with "0R2".
6.Page 25:Replace "INTMIC1" & "SPKR1" with main source follow connector list.
7.Page 5:Add C115, C116, C141, C149, C169, C171 for Colay with TC25.
8.Page 10:Replace "L20" with "68.00217.141".
9.Page 10:Replace "L10" & "L23" with "68.00217.101"
===========================================================
Crestline Strapping Signals and
Configuration
Pin Name
CFG[2:0]
CFG[4:3]
CFG5
CFG9
CFG[11:10] Reserved
CFG[13:12]
CFG[15:14]
CFG16
CFG[18:17]
CFG19
CFG20
SDVOCRTL
_DATA
All strap signals are sampled with respect to the leading
NOTE:
Strap Description
FSB Frequency Select
Reserved
DMI x2 Select
ReservedCFG[8:6]
Low Power PCI Express
PCI Express Graphics
Lane Reversal
XOR/ALL Z test
straps
Reserved
FSB Dynamic ODT
Reserved
DMI Lane Reversal
SDVO/PCIE
Concurrent
SDVO Present
edge of the Crestline GMCH PWORK in signal.
001 = FSB533
011 = FSB667
010 = FSB800
others = Reserved
0 = DMI x2
1 = DMI x4
0 = Normal mode
1 = Low Power mode
0 = Reverse Lanes,15->0,14->1 ect..
1= Normal operation(Default):Lane
Numbered in order
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled
0 = Normal operation (Default):lane
Numbered in order
1 =Reverse Lane,4->0,3->1 ect...
0 = Only SDVO or PCIE x1 is
operational (Default)
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
0 = No SDVO Card present
1= SDVO Card present
Crestline EDS 20954 1.0
Configuration
(Default)
(Default)
Reserved
page 7
(Default)
(Default)
(Default)
USB Table
PCIE Routing
LANE1
LANE2
LANE3 NewCard WLAN
1 1
LAN Marvell
MiniCard WLAN
USB
Pair
0
1
2
3
4
5
6
7
8
9 NEW1
Device
USB1
NC
USB2
NC
USB3
NC
NC
MINICARD
CCD
RTM
RTM
RTM
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet
Date: Sheet
Reference
Reference
Reference
Volvi2
Volvi2
Volvi2
of
of
236Thursday, July 05, 2007
236Thursday, July 05, 2007
236Thursday, July 05, 2007
-1
-1
-1
3D3V_S0
0R0603-PAD
0R0603-PAD
1 2
R244
R244
A
B
-1
3D3V_48MPWR_S0 3D3V_CLKPLL_S0
12
C407
C407
DY
DY
12
C404
C404
SC1U16V3ZY-GP
SC1U16V3ZY-GP
12
C400
C400
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C124
C124
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
12
C398
C398
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C397
C397
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C396
C396
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C
-1 -1
R63
R63
0R0603-PAD
0R0603-PAD
1 2
12
C394
C394
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
DY
DY
12
C154
C154
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
D
12
C403
C403
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C393
C393
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_CLKGEN_S0
12
C409
C409
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
E
R74
R74
0R0603-PAD
0R0603-PAD
1 2
12
C399
C399
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
4 4
PCLKCLK2
PCLKCLK3
PCLKCLK4
PCLKCLK5
3 3
2 2
1 2
1 2
PCLK_KBC
CLK48_ICH
R243
R243
10KR2J-3-GP
10KR2J-3-GP
DY
DY
R242
R242
10KR2J-3-GP
10KR2J-3-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
3D3V_S0
DY
DY
R240
R240
10KR2J-3-GP
10KR2J-3-GP
1 2
R236
R236
10KR2J-3-GP
10KR2J-3-GP
1 2
RTM
RTM
1 2
1 2
DY
DY
1 2
1 2
SC22P50V3JN-GP
SC22P50V3JN-GP
SC10P50V3JN-GP
SC10P50V3JN-GP
DY
DY
R233
R233
10KR2J-3-GP
10KR2J-3-GP
R230
R230
10KR2J-3-GP
10KR2J-3-GP
EC86
EC86
EC85
EC85
DY
DY
R229
R229
10KR2J-3-GP
10KR2J-3-GP
1 2
R231
R231
10KR2J-3-GP
10KR2J-3-GP
1 2
CL=20pF±0.2pF
C159
C159
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
1 2
12
C158
C158
1 2
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
GEN_XTAL_IN
X2
X2
X-14D31818M-44GP
X-14D31818M-44GP
GEN_XTAL_OUT_R
-1_0627
PCLK_KBC26
PCLK_ICH17
DY
DY
R77 10MR2J-L-GP
R77 10MR2J-L-GP
R76 0R0402-PADR76 0R0402-PAD
1 2
CLK48_ICH17
CPU_SEL04,7
CPU_SEL14,7
CPU_SEL24,7
CLK_ICH1417
12
-1
-1_0628
3D3V_CLKGEN_S0
3D3V_48MPWR_S0
3D3V_CLKPLL_S0
TP27TPAD30 TP27TPAD30
TP26TPAD30 TP26TPAD30
R238 22R2J-2-GPR238 22R2J-2-GP
R224 22R2J-2-GPR224 22R2J-2-GP
R226 22R2J-2-GPR226 22R2J-2-GP
R223 2K2R2J-2-GPR223 2K2R2J-2-GP
R241 2K2R2J-2-GPR241 2K2R2J-2-GP
R237 33R2J-2-GPR237 33R2J-2-GP
GEN_XTAL_OUT
12
12
12
12
12
12
PCLKCLK0
PCLKCLK1
PCLKCLK2
PCLKCLK3
PCLKCLK4
PCLKCLK5
CLK48
CPU_SEL2_R
CPU_SEL2_R
U12
U12
2
VDDPCI
9
VDD48
16
VDD
53
VDDREF
31
VDDSRC
47
VDDCPU
12
VDD96I/O
20
VDDPLL3I/O
26
VDDSRCI/O
37
VDDSRCI/O
41
VDDCPUI/O
1
PCICLK0/CR#_A
3
PCICLK1/CR#_B
4
PCICLK2/LTE
5
PCICLK3
6
PCICLK4/SRC5_EN
7
PCI_F5/ITP_EN
51
X2
52
X1
10
USB_48MHZ/FSLA
49
FSLB/TEST_MODE
54
FSLC/TEST_SEL/REF0
8
GNDPCI
11
GND48
15
GND
19
GND
23
GNDSRC
34
GNDSRC
44
GNDCPU
50
GNDREF
ICS9LPRS502PGLFT-GP
ICS9LPRS502PGLFT-GP
71.09502.B0W
71.09502.B0W
RTM:71.00875.B0W
SDATA
SCLK
DOTT_96/SRCCLKT0
DOTC_96/SRCCLKC0
SRCCLKT1/SE1
SRCCLKC1/SE2
SRCCLKT2/SATACLKT
SRCCLKC2/SATACLKC
SRCCLKT3/CR#_C
SRCCLKC3/CR#_D
SRCCLKT4
SRCCLKC4
PCI_STOP#/SRCCLKT5
CPU_STOP#/SRCCLKC5
SRCCLKT6
SRCCLKC6
SRCCLKT7/CR#_F
SRCCLKC7/CR#_E
CPUCLKT2_ITP/SRCCLKT8
CPUCLKC2_ITP/SRCCLKC8
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
CK_PWRGD/PD#
NC#40
55
56
DREFCLK_1
13
DREFCLK#_1
14
CLK_PCIE_NEW_R
17
CLK_PCIE_NEW#_R
18
CLK_PCIE_SATA_1
21
CLK_PCIE_SATA_1#
22
CLK_MCH_3GPLL_1
24
CLK_MCH_3GPLL_1#
25
CLK_PCIE_MINI_12
27
CLK_PCIE_MINI_12#
28
30
29
CLK_PCIE_ICH_1
33
CLK_PCIE_ICH_1#
32
DREFSSCLK_1
36
DREFSSCLK#_1
35
CLK_PCIE_LAN_R
39
CLK_PCIE_LAN#_R
38
CLK_MCH_BCLK_1
43
CLK_MCH_BCLK_1#
42
CLK_CPU_BCLK_1
46
CLK_CPU_BCLK_1#
45
48
40
SMBD_ICH 12,19
SMBC_ICH 12,19
PM_STPPCI# 17
PM_STPCPU# 17
CLK_PWRGD 17
10KR2J-3-GP
10KR2J-3-GP
1 2
DY
DY
R232
R232
-1_0628
1 2
R384 0R0402-PADR384 0R0402-PAD
1 2
R385 0R0402-PADR385 0R0402-PAD
1 2
R386 0R0402-PADR386 0R0402-PAD
1 2
R387 0R0402-PADR387 0R0402-PAD
1 2
R388 0R0402-PADR388 0R0402-PAD
1 2
R389 0R0402-PADR389 0R0402-PAD
1 2
R390 0R0402-PADR390 0R0402-PAD
1 2
R391 0R0402-PADR391 0R0402-PAD
1 2
R392 0R0402-PADR392 0R0402-PAD
1 2
R393 0R0402-PADR393 0R0402-PAD
1 2
R394 0R0402-PADR394 0R0402-PAD
1 2
R395 0R0402-PADR395 0R0402-PAD
1 2
R396 0R0402-PADR396 0R0402-PAD
1 2
R397 0R0402-PADR397 0R0402-PAD
1 2
R398 0R0402-PADR398 0R0402-PAD
1 2
R399 0R0402-PADR399 0R0402-PAD
1 2
R400 0R0402-PADR400 0R0402-PAD
1 2
R401 0R0402-PADR401 0R0402-PAD
1 2
R402 0R0402-PADR402 0R0402-PAD
1 2
R403 0R0402-PADR403 0R0402-PAD
DREFCLK 7
DREFCLK# 7
CLK_PCIE_NEW 23
CLK_PCIE_NEW# 23
CLK_PCIE_SATA 16
CLK_PCIE_SATA# 16
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_MINI1 23
CLK_PCIE_MINI1# 23
CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17
DREFSSCLK 7
DREFSSCLK# 7
CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
3D3V_CLKGEN_S0
Tahoe
EMI capacitor
ICS9LPR502HGLFT-GP setting table
PIN NAME DESCRIPTION
Byte 5, bit 7
0 = PCI0 enabled (default)
PCI0/CR#_A
PCI1/CR#_B
1 1
PCI2/TME
PCI4/SRC5_EN
PCI_F5/ITP_EN
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
0 = Pin29 as CPU_STOP# , pin 30 as PCI_STOP#.
1 = Pins29,30 as SRC-5 differential pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
A
B
RTM875T-605 setting table
PIN NAME
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3/SRC-5_EN
PCI4/27M_SEL
PCI_F5/ITP_EN
DESCRIPTION
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
0 = Pin29 as CPU_STOP# , pin 30 as PCI_STOP#.
1 = Pins29,30 as SRC-5 differential pair.
0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96#
1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#
0 =SRC8/SRC8#
1 = ITP/ITP#
C
SEL2
FSC
SEL1
FSB
1
0
0101
RTM
RTM
RTM
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
Clock Generator
Clock Generator
Clock Generator
SEL0
FSA
01
01
01
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Volvi2
Volvi2
Volvi2
E
CPU
100M
133M
166M
200M
336Thursday, July 05, 2007
336Thursday, July 05, 2007
336Thursday, July 05, 2007
FSB
X
X
667M
800M
-1
-1
of
of
of
-1
A
B
C
D
E
H_A#[35..3]6
4 4
H_ADSTB#06
H_REQ#[4..0]6
3 3
H_ADSTB#16
H_A20M#16
H_FERR#16
H_IGNNE#16
H_STPCLK#16
H_INTR16
H_NMI16
H_SMI#16
2 2
H_A#[35..3]
1 OF 4
1 OF 4
U38A
U38A
H_A#3
J4
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
Tahoe
RSVD_CPU_B1 TEST6
TP53TPAD30 TP53TPAD30
A3#
L5
A4#
L4
A5#
K5
A6#
M3
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L2
A13#
P4
A14#
P1
A15#
R1
A16#
M1
ADSTB0#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L1
REQ4#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U1
A23#
R4
A24#
T5
A25#
T3
A26#
W2
A27#
W5
A28#
Y4
A29#
U2
A30#
V4
A31#
W3
A32#
AA4
A33#
AB2
A34#
AA3
A35#
V1
ADSTB1#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD#M4
N5
RSVD#N5
T2
RSVD#T2
V3
RSVD#V3
B2
RSVD#B2
C3
RSVD#C3
D2
RSVD#D2
D22
RSVD#D22
D3
RSVD#D3
F6
RSVD#F6
B1
KEY_NC
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
ICH
ICH
RESERVED
RESERVED
62.10079.001
62.10079.001
XDP/ITP SIGNALS CONTROL
XDP/ITP SIGNALS CONTROL
THERMAL
THERMAL
PROCHOT#
THERMTRIP#
HCLK
HCLK
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
THRMDA
THRMDC
BCLK0
BCLK1
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AS14 -SA
AC4
AC2
AC1
AC5
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
H_RS#0
H_RS#1
H_RS#2
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
PM_THRMTRIP#
should connect to
ICH8 and MCH
without T-ing
( No stub)
TP11 TPAD30TP11 TPAD30
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_IERR#
H_INIT# 16,27
H_LOCK# 6
H_CPURST# 6,36
H_TRDY# 6
H_HIT# 6
H_HITM# 6
TP24 TPAD30TP24 TPAD30
TP23 TPAD30TP23 TPAD30
TP16 TPAD30TP16 TPAD30
TP22 TPAD30TP22 TPAD30
TP21 TPAD30TP21 TPAD30
TP19 TPAD30TP19 TPAD30
TP8 TPAD30TP8 TPAD30
CPU_PROCHOT#_R
H_THERMDA 20
H_THERMDC 20
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
1D05V_S0
12
R40
R40
56R2J-4-GP
56R2J-4-GP
Place testpoint on
H_IERR# with a GND
0.1" away
H_RS#[2..0] 6
1D05V_S0
12
56R2J-4-GP
56R2J-4-GP
R42
R42
PM_THRMTRIP-A# 7,16,28
Layout Note:
"CPU_GTLREF0"
0.5" max length.
H_THERMDA
H_THERMDC
R65
R65
2KR2F-3-GP
2KR2F-3-GP
1D05V_S0
1 2
12
12
C35
C35
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
1KR2F-3-GP
1KR2F-3-GP
R67
R67
H_DSTBN#06
H_DSTBP#06
H_DINV#06
CPU_GTLREF0
2nd source: 62.10053.401
1D05V_S0
XDP_TMS
XDP_TDI
R66 39R2F-GPR66 39R2F-GP
1 2
R62 150R2F-1-GPR62 150R2F-1-GP
1 2
2 OF 4
2 OF 4
U38B
U38B
H_D#0
E22
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_DSTBN#16
H_DSTBP#16
H_DINV#16
TP25TPAD30 TP25TPAD30
TP6TPAD30 TP6TPAD30
TP7TPAD30 TP7TPAD30
CPU_SEL03,7
CPU_SEL13,7
CPU_SEL23,7
Net "TEST4" as short as possible,
make sure "TEST4" routing is
reference to GND and away other
noisy signals
H_D#31
TEST4
TEST5
D0#
F24
D1#
E26
D2#
G22
D3#
F23
D4#
G25
D5#
E25
D6#
E23
D7#
K24
D8#
G24
D9#
J24
D10#
J23
D11#
H22
D12#
F26
D13#
K22
D14#
H23
D15#
J26
DSTBN0#
H26
DSTBP0#
H25
DINV0#
N22
D16#
K25
D17#
P26
D18#
R23
D19#
L23
D20#
M24
D21#
L22
D22#
M23
D23#
P25
D24#
P23
D25#
P22
D26#
T24
D27#
R24
D28#
L25
D29#
T25
D30#
N25
D31#
L26
DSTBN1#
M26
DSTBP1#
N24
DINV1#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL0
B23
BSEL1
C21
BSEL2
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
DATA GRP0 DATA GRP1
DATA GRP0 DATA GRP1
MISC
MISC
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
DATA GRP2DATA GRP3
DATA GRP2DATA GRP3
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_D#[63..0]
H_D#32
Y22
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
V23
H_D#37
T22
H_D#38
U25
H_D#39
U23
H_D#40
Y25
H_D#41
W22
H_D#42
Y23
H_D#43
W24
H_D#44
W25
H_D#45
AA23
H_D#46
AA24
H_D#47
AB25
Y26
AA26
U22
H_D#48
AE24
H_D#49
AD24
H_D#50
AA21
H_D#51
AB22
H_D#52
AB21
H_D#53
AC26
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AC25
H_D#58
AE21
H_D#59
AD21
H_D#60
AC22
H_D#61
AD23
H_D#62
AF22
H_D#63
AC23
AE25
AF24
AC20
COMP0
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
R200 27D4R2F-L1-GPR200 27D4R2F-L1-GP
COMP1
COMP2
R64 27D4R2F-L1-GPR64 27D4R2F-L1-GP
COMP3
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6
H_D#[63..0] 6
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
1 2
R202 54D9R2F-L1-GPR202 54D9R2F-L1-GP
1 2
1 2
R60 54D9R2F-L1-GPR60 54D9R2F-L1-GP
1 2
H_DPRSTP# 7,16,30
H_DPSLP# 16
H_DPWR# 6
H_PWRGD 16,28,36
H_CPUSLP# 6
PSI# 30
1 1
XDP_TCK
XDP_TRST#
R68 27D4R2F-L1-GPR68 27D4R2F-L1-GP
1 2
R69 649R2F-GPR69 649R2F-GP
1 2
All place within 2" to CPU
A
B
C
D
RTM
RTM
RTM
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet of
CPU (1 of 2)
CPU (1 of 2)
CPU (1 of 2)
Volvi2
Volvi2
Volvi2
E
436Thursday, July 05, 2007
of
436Thursday, July 05, 2007
of
436Thursday, July 05, 2007
SA
SA
SA
A
VCC_CORE_S0
4 4
3 3
AA10
AA12
2 2
1 1
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
U38C
U38C
A7
VCC
A9
VCC
A10
VCC
A12
VCC
A13
VCC
A15
VCC
A17
VCC
A18
VCC
A20
VCC
B7
VCC
B9
VCC
B10
VCC
B12
VCC
B14
VCC
B15
VCC
B17
VCC
B18
VCC
B20
VCC
C9
VCC
C10
VCC
C12
VCC
C13
VCC
C15
VCC
C17
VCC
C18
VCC
D9
VCC
D10
VCC
D12
VCC
D14
VCC
D15
VCC
D17
VCC
D18
VCC
E7
VCC
E9
VCC
E10
VCC
E12
VCC
E13
VCC
E15
VCC
E17
VCC
E18
VCC
E20
VCC
F7
VCC
F9
VCC
F10
VCC
F12
VCC
F14
VCC
F15
VCC
F17
VCC
F18
VCC
F20
VCC
AA7
VCC
AA9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
3 OF 4
3 OF 4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCA
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
VCC_CORE_S0
H_VID0 30
H_VID1 30
H_VID2 30
H_VID3 30
H_VID4 30
H_VID5 30
H_VID6 30
12
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C119
C119
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C55
C55
VCC_CORE_S0
12
12
1D05V_S0
layout note: "1D5V_VCCA_S0"
as short as possible
R71
R71
100R2F-L1-GP-U
100R2F-L1-GP-U
R72
R72
100R2F-L1-GP-U
100R2F-L1-GP-U
B
VCC_CORE_S0
12
C339
C339
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
POLY
POLY
DY
DY
VCC_CORE_S0
12
12
C38
C38
C37
C37
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
POLY
POLY
POLY
DY
DY
1D5V_VCCA_S0
POLY
12
C36
C36
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VCC_SENSE 30
VSS_SENSE 30
Layout Note:
VCCSENSE and VSSSENSE lines
should be of equal length.
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
12
12
C344
C344
C362
C362
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
POLY
POLY
12
12
C45
C45
C46
C46
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
1 2
0R3-0-U-GP
0R3-0-U-GP
12
C39
C39
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
C351
C351
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
POLY
POLY
12
12
C59
C59
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
DY
DY
1D5V_S0
L5
L5
UMA
UMA
C132
C132
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
C135
C135
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
1D05V_S0
12
C104
C104
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
VCC_CORE_S0
12
12
C136
C136
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
POLY
POLY
POLY
POLY
12
C87
C87
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C
TC1
TC1
ST1200U2D5VM-GP
ST1200U2D5VM-GP
77.E1281.001
77.E1281.001
3 4
PROADLIZER
PROADLIZER
12
12
C144
C144
C145
C145
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
12
12
C126
C126
C95
C95
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
POLY
POLY
C338
C338
12
C63
C63
12
12
C340
C340
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
DY
DY
12
C72
C72
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C374
C374
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
POLY
POLY
D
4 OF 4
4 OF 4
U38D
U38D
A4
VSS
A8
VSS
A11
VSS
A14
VSS
A16
VSS
A19
VSS
A23
CPU_AF2
TP42TPAD30 TP42TPAD30
12
C375
C375
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
VSS
AF2
VSS
B6
VSS
B8
VSS
B11
VSS
B13
VSS
B16
VSS
B19
VSS
B21
VSS
B24
VSS
C5
VSS
C8
VSS
C11
VSS
C14
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C25
VSS
D1
VSS
D4
VSS
D8
VSS
D11
VSS
D13
VSS
D16
VSS
D19
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E11
VSS
E14
VSS
E16
VSS
E19
VSS
E21
VSS
E24
VSS
F5
VSS
F8
VSS
F11
VSS
F13
VSS
F16
VSS
F19
VSS
F2
VSS
F22
VSS
F25
VSS
G4
VSS
G1
VSS
G23
VSS
G26
VSS
H3
VSS
H6
VSS
H21
VSS
H24
VSS
J2
VSS
J5
VSS
J22
VSS
J25
VSS
K1
VSS
K4
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L21
VSS
L24
VSS
M2
VSS
M5
VSS
M22
VSS
M25
VSS
N1
VSS
N4
VSS
N23
VSS
N26
VSS
P3
VSS
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
CPU_AE1
CPU_AE26
CPU_A2
CPU_A25
CPU_AF25
E
TP41 TPAD30TP41 TPAD30
TP44 TPAD30TP44 TPAD30
TP39 TPAD30TP39 TPAD30
TP40 TPAD30TP40 TPAD30
TP43 TPAD30TP43 TPAD30
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet
CPU (2 of 2)
CPU (2 of 2)
CPU (2 of 2)
Volvi2
Volvi2
Volvi2
E
SB
SB
of
536Thursday, July 05, 2007
536Thursday, July 05, 2007
536Thursday, July 05, 2007
SB
A
4 4
H_SWING
C315
C315
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
H_RCOMP
1D05V_S0
12
R173
R173
221R2F-2-GP
221R2F-2-GP
12
R174
R174
100R2F-L1-GP-U
100R2F-L1-GP-U
H_SWING routing Trace width and
Spacing use 10 / 20 mil
H_SWING Resistors and
Capacitors close MCH
500 mil ( MAX )
12
H_SCOMP and H_SCOMP# Resistors and
Capacitors close MCH 500 mil ( MAX )
3 3
1D05V_S0
54D9R2F-L1-GP
54D9R2F-L1-GP
54D9R2F-L1-GP
54D9R2F-L1-GP
1 2
H_SCOMP
H_SCOMP#
24D9R2F-L-GP
24D9R2F-L-GP
1 2
R184
R184
1D05V_S0
1 2
R185
R185
H_RCOMP routing Trace width and
Spacing use 10 / 20 mil
R182
R182
Place them near to the chip ( < 0.5")
2 2
H_REF Decoupling Crestline
close Crestline 100 mil
1D05V_S0
R169
R169
1KR2F-3-GP
1KR2F-3-GP
1 2
12
R177
R177
2KR2F-3-GP
2KR2F-3-GP
H_D#[63..0]4
B
H_D#[63..0]
H_AVREF
C313
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C313
C
1 OF 10
1 OF 10
U37A
U37A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#4,36
H_CPUSLP#4
1 2
E2
H_D#0
G2
H_D#1
G7
H_D#2
M6
H_D#3
H7
H_D#4
H3
H_D#5
G4
H_D#6
F3
H_D#7
N8
H_D#8
H2
H_D#9
M10
H_D#10
N12
H_D#11
N9
H_D#12
H5
H_D#13
P13
H_D#14
K9
H_D#15
M2
H_D#16
W10
H_D#17
Y8
H_D#18
V4
H_D#19
M3
H_D#20
J1
H_D#21
N5
H_D#22
N3
H_D#23
W6
H_D#24
W9
H_D#25
N2
H_D#26
Y7
H_D#27
Y9
H_D#28
P4
H_D#29
W3
H_D#30
N1
H_D#31
AD12
H_D#32
AE3
H_D#33
AD9
H_D#34
AC9
H_D#35
AC7
H_D#36
AC14
H_D#37
AD11
H_D#38
AC11
H_D#39
AB2
H_D#40
AD7
H_D#41
AB1
H_D#42
Y3
H_D#43
AC6
H_D#44
AE2
H_D#45
AC5
H_D#46
AG3
H_D#47
AJ9
H_D#48
AH8
H_D#49
AJ14
H_D#50
AE9
H_D#51
AE11
H_D#52
AH12
H_D#53
AJ5
H_D#54
AH5
H_D#55
AJ6
H_D#56
AE7
H_D#57
AJ7
H_D#58
AJ2
H_D#59
AE5
H_D#60
AJ3
H_D#61
AH2
H_D#62
AH13
H_D#63
B3
H_SWING
C2
H_RCOMP
W1
H_SCOMP
W2
H_SCOMP#
B6
H_CPURST#
E5
H_CPUSLP#
B9
H_AVREF
A9
H_DVREF
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
HOST
HOST
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_HIT#
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_A#[35..3]
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3
H_DPWR# 4
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
D
H_A#[35..3] 4
H_DINV#[3..0] 4
H_DSTBN#[3..0] 4
H_DSTBP#[3..0] 4
H_REQ#[4..0] 4
H_RS#[2..0] 4
E
1 1
A
CRB v0.9 REQUEST
RTM
RTM
RTM
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GMCH (1 of 6)
GMCH (1 of 6)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
B
C
D
Date: Sheet of
GMCH (1 of 6)
Volvi2
Volvi2
Volvi2
E
SA
SA
636Thursday, July 05, 2007
of
636Thursday, July 05, 2007
of
636Thursday, July 05, 2007
SA
A
AR12
AR13
AM12
AN13
AR37
4 4
3 3
AM36
AM37
BK22
BH20
BK18
BG23
BC23
BD24
BH39
AW20
BK20
P36
P37
R35
N35
AL36
D20
H10
B51
BJ20
BF19
BJ18
BF23
B44
C44
C34
J12
A35
B37
B36
B34
2 OF 10
2 OF 10
U37B
U37B
RSVD#P36
RSVD#P37
RSVD#R35
RSVD#N35
RSVD#AR12
RSVD#AR13
RSVD#AM12
RSVD#AN13
RSVD#J12
RSVD#AR37
RSVD#AM36
RSVD#AL36
RSVD#AM37
RSVD#D20
RSVD#H10
RSVD#B51
RSVD#BJ20
RSVD#BK22
RSVD#BF19
RSVD#BH20
RSVD#BK18
RSVD#BJ18
RSVD#BF23
RSVD#BG23
RSVD#BC23
RSVD#BD24
RSVD#BH39
RSVD#AW20
RSVD#BK20
RSVD#B44
RSVD#C44
RSVD#A35
RSVD#B37
RSVD#B36
RSVD#B34
RSVD#C34
-1
R175
R175
1 2
0R0402-PAD
0R0402-PAD
PWROK_GD
RSTIN#
NB_THERMTRIP#
CPU_SEL0_1
CPU_SEL1_1
CPU_SEL2_1
CFG9
PM_EXTTS#0
PM_EXTTS#1
P27
CFG0
N27
CFG1
N24
CFG2
C21
CFG3
C23
CFG4
F23
CFG5
N23
CFG6
G23
CFG7
J20
CFG8
C20
CFG9
R24
CFG10
L23
CFG11
J23
CFG12
E23
CFG13
E20
CFG14
K23
CFG15
M20
CFG16
M24
CFG17
L32
CFG18
N33
CFG19
L35
CFG20
G41
PM_BM_BUSY#
L39
PM_DPRSTP#
L36
PM_EXT_TS#0
J36
PM_EXT_TS#1
AW49
PWROK
AV20
RSTIN#
N20
THERMTRIP#
G36
DPRSLPVR
BJ51
NC#BJ51
BK51
NC#BK51
BK50
NC#BK50
BL50
NC#BL50
BL49
NC#BL49
BL3
NC#BL3
BL2
NC#BL2
BK1
NC#BK1
BJ1
NC#BJ1
E1
NC#E1
A5
NC#A5
C51
NC#C51
B50
NC#B50
A50
NC#A50
A49
NC#A49
BK2
NC#BK2
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
R153 0R0402-PADR153 0R0402-PAD
CPU_SEL03,4
CPU_SEL13,4
CPU_SEL23,4
2 2
H_DPRSTP#4,16,30
VGATE_PWRGD17,30
PWROK17,20
PLT_RST1#17,26,36
1 2
R157 0R0402-PADR157 0R0402-PAD
1 2
R154 0R0402-PADR154 0R0402-PAD
1 2
PM_BMBUSY#17
R2120R2J-2-GPDYR2120R2J-2-GP
12
DY
R216 0R0402-PADR216 0R0402-PAD
1 2
12
R207 100R2J-2-GPR207 100R2J-2-GP
-1
0R0402-PAD
0R0402-PAD
R152
R152
PM_THRMTRIP-A#4,16,28
PM_DPRSLPVR17,30
1 1
1 2
A
B
RSVD
RSVD
DDR MUXING
DDR MUXING
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF#AR49
SM_VREF#AW4
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLK
CLK
DMI
DMI
CFG PM NC
CFG PM NC
SDVO_CTRL_CLK
SDVO_CTRL_DATA
MISC ME GRAPHICS VID
MISC ME GRAPHICS VID
B
SM_CK0
SM_CK1
SM_CK3
SM_CK4
SM_CK#0
SM_CK#1
SM_CK#3
SM_CK#4
SM_CKE0
SM_CKE1
SM_CKE3
SM_CKE4
SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SM_RCOMP
SM_RCOMP#
PEG_CLK
PEG_CLK#
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
CLKREQ#
ICH_SYNC#
TEST1
TEST2
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BK31
BL31
BL15
BK14
AR49
AW4
B42
C42
H48
H47
K44
K45
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
AM50
H35
K36
G39
G40
A37
R32
SM_RCOMP_VOH
SM_RCOMP_VOL
M_RCOMPP
M_RCOMPN
DDR_VREF_S3
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
Tahoe
MCH_CLVREF
CLK_3GPLLREQ#
MCH_ICH_SYNC# 17
TEST2_GMCH
12
M_CLK_DDR0 12
M_CLK_DDR1 12
M_CLK_DDR2 12
M_CLK_DDR3 12
M_CLK_DDR#0 12
M_CLK_DDR#1 12
M_CLK_DDR#2 12
M_CLK_DDR#3 12
M_CKE0 12,13
M_CKE1 12,13
M_CKE2 12,13
M_CKE3 12,13
M_CS0# 12,13
M_CS1# 12,13
M_CS2# 12,13
M_CS3# 12,13
M_ODT0 12,13
M_ODT1 12,13
M_ODT2 12,13
M_ODT3 12,13
DREFCLK 3
DREFCLK# 3
DREFSSCLK 3
DREFSSCLK# 3
CLK_MCH_3GPLL 3
CLK_MCH_3GPLL# 3
DMI_TXN0 17
DMI_TXN1 17
DMI_TXN2 17
DMI_TXN3 17
DMI_TXP0 17
DMI_TXP1 17
DMI_TXP2 17
DMI_TXP3 17
DMI_RXN0 17
DMI_RXN1 17
DMI_RXN2 17
DMI_RXN3 17
DMI_RXP0 17
DMI_RXP1 17
DMI_RXP2 17
DMI_RXP3 17
R38
R38
10KR2J-3-GP
10KR2J-3-GP
R46
R46
20KR2J-L2-GP
20KR2J-L2-GP
C
CL_CLK0 17
CL_DATA0 17
PWROK 17,20
CL_RST#0 17
3D3V_S0
C359
C359
12
C
M_RCOMPP
M_RCOMPN
1D25V_S0
R195
R195
1KR2F-3-GP
1KR2F-3-GP
1 2
12
12
R194
R194
392R2F-GP
392R2F-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R31
R31
150R2F-1-GP
150R2F-1-GP
12
R30
R30
150R2F-1-GP
150R2F-1-GP
12
R39
R39
150R2F-1-GP
150R2F-1-GP
12
R35
R35
150R2F-1-GP
150R2F-1-GP
12
R34
R34
150R2F-1-GP
150R2F-1-GP
12
R36
R36
150R2F-1-GP
150R2F-1-GP
12
R234 1KR2F-3-GPR234 1KR2F-3-GP
12
R239
R239
3K01R2F-3-GP
3K01R2F-3-GP
R235
R235
1KR2F-3-GP
1KR2F-3-GP
1 2
CLK_DDC_EDID14
DAT_DDC_EDID14
GMCH_LCDVDD_ON14
1D8V_S3
R22820R2F-GP R22820R2F-GP
R22720R2F-GP R22720R2F-GP
GMCH_BLUE
GMCH_GREEN
GMCH_RED
GMCH_BL_ON26
12
12
TV_DACA
TV_DACB
TV_DACC
12
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
GMCH_DDCDATA15
1D8V_S3
C401
C401
C402
C402
D
3D3V_S0
678
RN27
RN27
SRN10KJ-6-GP
SRN10KJ-6-GP
123
TV_DACA15
TV_DACB15
TV_DACC15
3D3V_S0
RN3
RN3
8
7
6
SRN10KJ-6-GP
SRN10KJ-6-GP
GMCH_BLUE15
GMCH_GREEN15
GMCH_RED15
GMCH_DDCCLK15
GMCH_VSYNC15
GMCH_HSYNC15
R176 1K3R2F-1-GPR176 1K3R2F-1-GP
SM_RCOMP_VOH
12
C405
C405
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SM_RCOMP_VOL
12
C406
C406
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
D
L_BKLTCTL14
4 5
LCTLA_CLK
LCTLB_DATA
LIBG
R43
R43
12
2K4R2F-GP
2K4R2F-GP
GMCH_TXACLK-14
GMCH_TXACLK+14
GMCH_TXBCLK-14
GMCH_TXBCLK+14
GMCH_TXAOUT0-14
GMCH_TXAOUT1-14
GMCH_TXAOUT2-14
GMCH_TXAOUT3-
TP3TPAD30 TP3TPAD30
GMCH_TXAOUT0+14
GMCH_TXAOUT1+14
GMCH_TXAOUT2+14
GMCH_TXAOUT3+
TP4TPAD30 TP4TPAD30
GMCH_TXBOUT0-14
GMCH_TXBOUT1-14
GMCH_TXBOUT2-14
GMCH_TXBOUT0+14
GMCH_TXBOUT1+14
GMCH_TXBOUT2+14
PM_EXTTS#1
1
PM_EXTTS#0
2
3
45
GMCH_BLUE
GMCH_GREEN
GMCH_RED
1 2
UMA
UMA
R165 33R2F-3-GP
R165 33R2F-3-GP
1 2
UMA
UMA
R164 33R2F-3-GP
R164 33R2F-3-GP
1 2
FOR Calero: 255 ohm
Crestline: 1.3k ohm
CRT_IREF routing Trace
width use 20 mil
L_LVBG
TP9TPAD30 TP9TPAD30
TV_DCONSEL0
TV_DCONSEL1
GMCH_DDCCLK
GMCH_DDCDATA
GMCH_VS
GMCH_HS
CRT_IREF
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
U37C
U37C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#0
E51
LVDSA_DATA#1
F49
LVDSA_DATA#2
C48
LVDSA_DATA#3
G50
LVDSA_DATA0
E50
LVDSA_DATA1
F48
LVDSA_DATA2
D47
LVDSA_DATA3
G44
LVDSB_DATA#0
B47
LVDSB_DATA#1
B45
LVDSB_DATA#2
E44
LVDSB_DATA0
A47
LVDSB_DATA1
A45
LVDSB_DATA2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL0
P33
TV_DCONSEL1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
E33
CRT_VSYNC
C32
CRT_TVO_IREF
F33
CRT_HSYNC
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
3 OF 10
3 OF 10
GMCH (2 of 6)
GMCH (2 of 6)
GMCH (2 of 6)
Volvi2
Volvi2
Volvi2
E
PEG_COMPI
PEG_COMPO
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
LVDS
LVDS
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
TV VGA
TV VGA
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PCI_EXPRESS GRAPHICS
PCI_EXPRESS GRAPHICS
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
736Thursday, July 05, 2007
736Thursday, July 05, 2007
736Thursday, July 05, 2007
E
1D05V_S0
24D9R2F-L-GP
24D9R2F-L-GP
PEG_CMP
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
of
R50
R50
12
SA
SA
SA
A
B
C
D
E
4 4
M_A_DQ[63..0]12
3 3
2 2
M_A_DQ[63..0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BG47
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BH45
BG40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BG10
AN10
AN11
U37D
U37D
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
BF48
SA_DQ9
SA_DQ10
BJ45
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
BF44
SA_DQ20
SA_DQ21
SA_DQ22
BF40
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
BD8
SA_DQ42
AY9
SA_DQ43
SA_DQ44
AW9
SA_DQ45
BD7
SA_DQ46
BB9
SA_DQ47
BB5
SA_DQ48
AY7
SA_DQ49
AT5
SA_DQ50
AT7
SA_DQ51
AY6
SA_DQ52
BB7
SA_DQ53
AR5
SA_DQ54
AR8
SA_DQ55
AR9
SA_DQ56
AN3
SA_DQ57
AM8
SA_DQ58
SA_DQ59
AT9
SA_DQ60
AN9
SA_DQ61
AM9
SA_DQ62
SA_DQ63
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
4 OF 10
4 OF 10
BB19
SA_BS0
BK19
SA_BS1
BF29
SA_BS2
BL17
SA_CAS#
AT45
SA_DM0
BD44
SA_DM1
BD42
SA_DM2
AW38
SA_DM3
AW13
SA_DM4
BG8
SA_DM5
AY5
SA_DM6
AN6
SA_DM7
AT46
SA_DQS0
BE48
SA_DQS1
BB43
SA_DQS2
BC37
SA_DQS3
BB16
SA_DQS4
BH6
SA_DQS5
BB2
SA_DQS6
AP3
SA_DQS7
AT47
SA_DQS#0
BD47
SA_DQS#1
BC41
SA_DQS#2
BA37
SA_DQS#3
BA16
SA_DQS#4
BH7
SA_DQS#5
BC1
SA_DQS#6
AP2
SA_DQS#7
BJ19
SA_MA0
BD20
SA_MA1
BK27
SA_MA2
BH28
SA_MA3
BL24
SA_MA4
BK28
SA_MA5
BJ27
SA_MA6
BJ25
SA_MA7
BL28
SA_MA8
BA28
SA_MA9
BC19
SA_MA10
DDR SYSTEM MEMORRY A
DDR SYSTEM MEMORRY A
SA_RCVEN#
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_RAS#
SA_WE#
BE28
BG30
BJ16
BJ29
BE18
AY20
BA19
M_A_DM[7..0]
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_RCVEN#
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
TP17 TPAD30TP17 TPAD30
Place Test PAD Near to Chip
as could as possible
M_A_BS#0 12,13
M_A_BS#1 12,13
M_A_BS#2 12,13
M_A_CAS# 12,13
M_A_DM[7..0] 12
M_A_DQS[7..0] 12
M_A_DQS#[7..0] 12
M_A_A[14..0] 12,13
M_A_RAS# 12,13
M_A_WE# 12,13
5 OF 10
5 OF 10
U37E
M_B_DQ[63..0]12
M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U37E
AP49
SB_DQ0
AR51
SB_DQ1
AW50
SB_DQ2
AW51
SB_DQ3
AN51
SB_DQ4
AN50
SB_DQ5
AV50
SB_DQ6
AV49
SB_DQ7
BA50
SB_DQ8
BB50
SB_DQ9
BA49
SB_DQ10
BE50
SB_DQ11
BA51
SB_DQ12
AY49
SB_DQ13
BF50
SB_DQ14
BF49
SB_DQ15
BJ50
SB_DQ16
BJ44
SB_DQ17
BJ43
SB_DQ18
BL43
SB_DQ19
BK47
SB_DQ20
BK49
SB_DQ21
BK43
SB_DQ22
BK42
SB_DQ23
BJ41
SB_DQ24
BL41
SB_DQ25
BJ37
SB_DQ26
BJ36
SB_DQ27
BK41
SB_DQ28
BJ40
SB_DQ29
BL35
SB_DQ30
BK37
SB_DQ31
BK13
SB_DQ32
BE11
SB_DQ33
BK11
SB_DQ34
BC11
SB_DQ35
BC13
SB_DQ36
BE12
SB_DQ37
BC12
SB_DQ38
BG12
SB_DQ39
BJ10
SB_DQ40
BL9
SB_DQ41
BK5
SB_DQ42
BL5
SB_DQ43
BK9
SB_DQ44
BK10
SB_DQ45
BJ8
SB_DQ46
BJ6
SB_DQ47
BF4
SB_DQ48
BH5
SB_DQ49
BG1
SB_DQ50
BC2
SB_DQ51
BK3
SB_DQ52
BE4
SB_DQ53
BD3
SB_DQ54
BJ2
SB_DQ55
BA3
SB_DQ56
BB3
SB_DQ57
AR1
SB_DQ58
AT3
SB_DQ59
AY2
SB_DQ60
AY3
SB_DQ61
AU2
SB_DQ62
AT2
SB_DQ63
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
AY17
SB_BS0
BG18
SB_BS1
BG36
SB_BS2
BE17
SB_CAS#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_RAS#
SB_RCVEN#
SB_WE#
M_B_DM0
AR50
M_B_DM1
BD49
M_B_DM2
BK45
M_B_DM3
BL39
M_B_DM4
BH12
M_B_DM5
BJ7
M_B_DM6
BF3
M_B_DM7
AW2
M_B_DQS0
AT50
M_B_DQS1
BD50
M_B_DQS2
BK46
M_B_DQS3
BK39
M_B_DQS4
BJ12
M_B_DQS5
BL7
M_B_DQS6
BE2
M_B_DQS7
AV2
M_B_DQS#0
AU50
M_B_DQS#1
BC50
M_B_DQS#2
BL45
M_B_DQS#3
BK38
M_B_DQS#4
BK12
M_B_DQS#5
BK7
M_B_DQS#6
BF2
M_B_DQS#7
AV3
M_B_A0
BC18
M_B_A1
BG28
M_B_A2
BG25
M_B_A3
AW17
M_B_A4
BF25
M_B_A5
BE25
M_B_A6
BA29
M_B_A7
BC28
M_B_A8
AY28
M_B_A9
BD37
M_B_A10
BG17
M_B_A11
BE37
M_B_A12
BA39
M_B_A13
BG13
M_B_A14
BE24
AV16
SB_RCVEN#
AY18
BC17
Place Test PAD Near to Chip
ascould as possible
M_B_DM[7..0]
M_B_DQS[7..0]
M_B_DQS#[7..0]
M_B_A[14..0]
M_B_DQS[7..0] 12
M_B_DQS#[7..0] 12
M_B_A[14..0] 12,13
M_B_RAS# 12,13
TP18TPAD30TP18TPAD30
M_B_WE# 12,13
M_B_BS#0 12,13
M_B_BS#1 12,13
M_B_BS#2 12,13
M_B_CAS# 12,13
M_B_DM[7..0] 12
1 1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
GMCH (3 of 6)
GMCH (3 of 6)
GMCH (3 of 6)
Volvi2
Volvi2
Volvi2
836Thursday, July 05, 2007
836Thursday, July 05, 2007
836Thursday, July 05, 2007
E
SA
SA
SA
A
1D05V_S0
FOR VCC CORE
12
C345
C345
4 4
12
Coupling CAP 370 mils from the Edge
12
12
C102
C102
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C98
C98
C91
C91
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C78
C78
C101
C101
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C85
C85
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R48
R48
1 2
0R0402-PAD
0R0402-PAD
1D8V_S3
3138mA
FOR VCC SM
Place CAP where
LVDS and DDR2 taps
3 3
2 2
1 1
12
C140
C140
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
DY
DY
C127
C127
DY
12
C142
C142
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Place on the Edge
12
12
C146
C146
C143
C143
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1D05V_S0
12
C316
C316
UMA
UMA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
A
12
12
DY
DY
VCC_NCTF + VCC=1573mA
6 OF 10
6 OF 10
U37F
1573mA
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
U37F
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
-1
VCC_GMCH1
R30
VCC
POWER
POWER
AU32
VCC_SM
AU33
VCC_SM
AU35
VCC_SM
AV33
VCC_SM
AW33
VCC_SM
AW35
VCC_SM
AY35
VCC_SM
BA32
VCC_SM
BA33
VCC_SM
BA35
VCC_SM
BB33
VCC_SM
BC32
VCC_SM
TC3
C125
C125
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
BC33
ST220U4VDM-23GPDYTC3
ST220U4VDM-23GP
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
BL33
AU30
R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
C76
C76
AJ20
AN14
UMA
UMA
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
VCC CORE
VCC CORE
VCC SM
VCC SM
VCC GFX
VCC GFX
B
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC SM LF
VCC SM LF
B
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
1D05V_S0
VCC_AXG_NCTF + VCC_AXG=7700mA
12
C115
C115
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
UMA
UMA
UMA
UMA
SM_LF1_GMCH
SM_LF2_GMCH
SM_LF3_GMCH
SM_LF4_GMCH
SM_LF5_GMCH
SM_LF6_GMCH
SM_LF7_GMCH
12
C107
C107
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
UMA
UMA
12
12
C121
C121
C128
C128
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C100
C100
12
UMA
UMA
12
C99
C99
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
C137
C137
C139
C133
C133
C139
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C
ST220U2D5VBM-2GP
ST220U2D5VBM-2GP
C89
C89
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
UMA
UMA
12
12
C138
C138
C382
C382
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
C
TC9
TC9
DY
DY
308 mils from
the Edge
-1
R57
R57
0R0603-PAD
0R0603-PAD
1 2
1D25V_S0
0R6J-3-GP
0R6J-3-GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
D
FOR VCC CORE AND VCC NCTF
1D05V_S0
12
C88
C88
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Coupling CAP
12
C117
C117
C114
C114
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
C80
C80
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
C118
C118
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Coupling CAP
R58
R58
12
FOR VCC AXM NCTF AND VCC AXM
VCC_AXM_S01D05V_S0
12
DY
DY
12
12
C109
C109
C79
C79
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
C108
C108
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
Place on the Edge
VCC_AXM_NCTF + VCC_AXM=540mA
D
C86
C86
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C110
C110
C106
C106
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
E
7 OF 10
7 OF 10
U37G
U37G
AB33
VCC_NCTF
AB36
VCC_NCTF
AB37
VCC_NCTF
AC33
VCC_NCTF
AC35
VCC_NCTF
AC36
VCC_NCTF
AD35
VCC_NCTF
AD36
VCC_NCTF
AF33
VCC_NCTF
AF36
VCC_NCTF
AH33
VCC_NCTF
AH35
VCC_NCTF
AH36
VCC_NCTF
AH37
VCC_NCTF
AJ33
VCC_NCTF
AJ35
VCC_NCTF
AK33
VCC_NCTF
AK35
VCC_NCTF
AK36
VCC_NCTF
AK37
VCC_NCTF
AD33
VCC_NCTF
AJ36
VCC_NCTF
AM35
VCC_NCTF
AL33
VCC_NCTF
AL35
VCC_NCTF
AA33
VCC_NCTF
AA35
VCC_NCTF
AA36
VCC_NCTF
AP35
VCC_NCTF
AP36
VCC_NCTF
AR35
VCC_NCTF
AR36
VCC_NCTF
Y32
VCC_NCTF
Y33
VCC_NCTF
Y35
VCC_NCTF
Y36
VCC_NCTF
Y37
VCC_NCTF
T30
VCC_NCTF
T34
VCC_NCTF
T35
VCC_NCTF
U29
VCC_NCTF
U31
VCC_NCTF
U32
VCC_NCTF
U33
VCC_NCTF
U35
VCC_NCTF
U36
VCC_NCTF
V32
VCC_NCTF
V33
VCC_NCTF
V36
VCC_NCTF
V37
VCC_NCTF
AL24
VCC_AXM_NCTF
AL26
VCC_AXM_NCTF
AL28
VCC_AXM_NCTF
AM26
VCC_AXM_NCTF
AM28
VCC_AXM_NCTF
AM29
VCC_AXM_NCTF
AM31
VCC_AXM_NCTF
AM32
VCC_AXM_NCTF
AM33
VCC_AXM_NCTF
AP29
VCC_AXM_NCTF
AP31
VCC_AXM_NCTF
AP32
VCC_AXM_NCTF
AP33
VCC_AXM_NCTF
AL29
VCC_AXM_NCTF
AL31
VCC_AXM_NCTF
AL32
VCC_AXM_NCTF
AR31
VCC_AXM_NCTF
AR32
VCC_AXM_NCTF
AR33
VCC_AXM_NCTF
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
VSS NCTF
VSS NCTF
VCC NCTF
VCC NCTF
POWER
POWER
VSS SCBVSS AXM
VSS SCBVSS AXM
VSS AXM NCTF
VSS AXM NCTF
GMCH (4 of 6)
GMCH (4 of 6)
GMCH (4 of 6)
Volvi2
Volvi2
Volvi2
T27
VSS_NCTF
T37
VSS_NCTF
U24
VSS_NCTF
U28
VSS_NCTF
V31
VSS_NCTF
V35
VSS_NCTF
AA19
VSS_NCTF
AB17
VSS_NCTF
AB35
VSS_NCTF
AD19
VSS_NCTF
AD37
VSS_NCTF
AF17
VSS_NCTF
AF35
VSS_NCTF
AK17
VSS_NCTF
AM17
VSS_NCTF
AM24
VSS_NCTF
AP26
VSS_NCTF
AP28
VSS_NCTF
AR15
VSS_NCTF
AR19
VSS_NCTF
AR28
VSS_NCTF
NB_A3
A3
VSS_SCB
B2
VSS_SCB
C1
VSS_SCB
BL1
VSS_SCB
BL51
VSS_SCB
A51
VSS_SCB
AT33
VCC_AXM
AT31
VCC_AXM
AK29
VCC_AXM
AK24
VCC_AXM
AK23
VCC_AXM
AJ26
VCC_AXM
AJ23
VCC_AXM
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
936Thursday, July 05, 2007
936Thursday, July 05, 2007
936Thursday, July 05, 2007
E
NB_B2
NB_C1
NB_BL1
NB_BL51
NB_A51
1D05V_S0
Tahoe
TP84 TPAD30TP84 TPAD30
TP47 TPAD30TP47 TPAD30
TP46 TPAD30TP46 TPAD30
TP45 TPAD30TP45 TPAD30
TP92 TPAD30TP92 TPAD30
TP85 TPAD30TP85 TPAD30
SA
SA
SA
A
1D25V_S0
R181
R181
0R0603-PAD
0R0603-PAD
1 2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
R183
4 4
R183
0R0603-PAD
0R0603-PAD
1 2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
C327
C327
C331
C331
M_VCCA_DPLLA
12
C326
C326
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VCCA_DPLLB
12
C332
C332
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R166 with 68.00217.481 in PD BOM
Tahoe
1D25V_S0
120ohm 100MHz
1 2
L22
L22
FCM1608KF-121-GP
FCM1608KF-121-GP
C347
C347
DY
DY
2nd source:68.00206.021
M_VCCA_HPLL
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
C357
C357
12
C358
C358
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
120ohm 100MHz
3 3
2 2
1 1
1 2
L9
L9
FCM1608KF-121-GP
FCM1608KF-121-GP
2nd source:68.00206.021
1D25V_S0
L21
L21
0R0603-PAD
0R0603-PAD
1 2
3D3VTVDAC 3D3V_S0
220ohm 100MHz
180ohm 100MHz
L19
L19
1 2
FCM1608CF-1-GP
FCM1608CF-1-GP
2nd source:68.00206.041
R168
R168
12
0R0402-PAD
0R0402-PAD
R163
R163
12
0R0402-PAD
0R0402-PAD
R161
R161
12
0R0402-PAD
0R0402-PAD
12
C44
C44
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
180ohm 100MHz
A
M_VCCA_MPLL
1D25V_RUN_PEGPLL
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C336
C336
M_VCCA_TVDACA
12
C318
C318
UMA
UMA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VCCA_TVDACB
12
C319
C319
UMA
UMA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VCCA_TVDACC
12
C320
C320
UMA
UMA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
0R0603-PAD
0R0603-PAD
12
C49
C49
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
L7
L7
0R0603-PAD
0R0603-PAD
1 2
12
C122
C122
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
-1_0705
12
TC16
TC16
SE330U2VDM-6-GP
SE330U2VDM-6-GP
DY
12
12
C50
C50
UMA
UMA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
VCCD_CRT
1D5VRUN_QDAC
12
C312
C312
UMA
UMA
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
12
C309
C309
UMA
UMA
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
12
C310
C310
UMA
UMA
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
R45
R45
12
C51
C51
UMA
UMA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
B
3D3VTVDAC
-1_0628
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
-1_0703
B
10mA
UMA
UMA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
180ohm 100MHz
R166
R166
0R3-0-U-GP
0R3-0-U-GP
C548
C548
DY
DY
1D8V_TXLVDS_S3
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
400uA
1D25V_S0
DY
DY
1D25V_S0
12
C111
C111
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
60mA
1D25V_S0
Tahoe
12
1D8V_S3
3D3V_S0
12
R28
R28
0R0402-PAD
0R0402-PAD
3D3V_SYNC_S0
12
C43
C43
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VCCA_DAC_BG
M_VCCA_DAC_BG
12
12
C321
C321
10mA
C323
C323
UMA
UMA
C334
C334
C130
C130
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
12
C131
C131
SC1U10V3KX-3GP
SC1U10V3KX-3GP
Tahoe
C369
C369
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
0R0603-PAD
0R0603-PAD
-1_0702
3D3VTVDAC
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
C30
C30
UMA
UMA
5mA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
80mA
80mA
50mA
150mA
1 2
12
0R0402-PAD
0R0402-PAD
12
C47
C47
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D25V_RUN_PEGPLL
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
C134
C134
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
40mA
40mA
40mA
1D5V_S0
60mA
1D5VRUN_QDAC
1D25V_RUN_PEGPLL
12
C337
C337
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R37
R37
1D8V_SUS_DLVDS
12
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
80mA
180ohm 100MHz
R172
R172
12
0R0603-PAD
0R0603-PAD
C546
C546
UMA
UMA
3D3V_CRTDAC_S0
12
M_VCCA_DAC_BG
M_VCCA_DPLLA
M_VCCA_DPLLB
M_VCCA_HPLL
M_VCCA_MPLL
1D8V_TXLVDS
R179
R179
3D3V_S0
Tahoe
12
C116
C116
C105
C105
SC1U10V3KX-3GP
SC1U10V3KX-3GP
M_VCCA_TVDACA
M_VCCA_TVDACB
M_VCCA_TVDACC
VCCD_CRT
5mA
250mA
100mA
150mA
C41
C41
UMA
UMA
UMA
UMA
12
J32
A33
B33
A30
B32
B49
H49
AL2
AM2
A41
B41
K50
K49
U51
AW18
AV19
AU19
AU18
AU17
AT22
SC1U10V3KX-3GP
SC1U10V3KX-3GP
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
C25
B25
C27
B27
B28
A28
M32
L29
N28
AN2
U48
J41
H42
12
C40
C40
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C
8 OF 10
8 OF 10
U37H
U37H
VCC_SYNC
VCCA_CRT_DAC
VCCA_CRT_DAC
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_PEG_BG
VSSA_PEG_BG
VCCA_PEG_PLL
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM_NCTF
VCCA_SM_NCTF
VCCA_SM_CK
VCCA_SM_CK
VCCA_TVA_DAC
VCCA_TVA_DAC
VCCA_TVB_DAC
VCCA_TVB_DAC
VCCA_TVC_DAC
VCCA_TVC_DAC
VCCD_CRT
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS
VCCD_LVDS
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
C
POWER
POWER
A LVDS PLL CRT
A LVDS PLL CRT
AXD
AXD
VCC_AXD_NCTF
A PEG
A PEG
SM CK
SM CK
TV A CK A SM
TV A CK A SM
DMI
DMI
LVDS TV/CRT
LVDS TV/CRT
VTT
VTT
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXF
VCC_AXF
VCC_AXF
AXF
AXF
VCC_DMI
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_TX_LVDS
VCC_HV
HV
HV
VCC_HV
VCC_PEG
VCC_PEG
VCC_PEG
PEG
PEG
VCC_PEG
VCC_PEG
VCC_RXR_DMI
VCC_RXR_DMI
VTTLF
VTTLF
VTTLF
VTTLF
VTTLF
5V_S0
12
C295
C295
SC1U16V3ZY-GP
SC1U16V3ZY-GP
DY
DY
Place on the edge
U13
VTT
U12
VTT
U11
VTT
U9
VTT
U8
VTT
U7
VTT
U5
VTT
U3
VTT
U2
VTT
U1
VTT
T13
VTT
T11
VTT
T10
VTT
T9
VTT
T7
VTT
T6
VTT
T5
VTT
T3
VTT
T2
VTT
R3
VTT
R2
VTT
R1
VTT
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
Tahoe
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
U34
U34
1
2
G909-330T1U-GP
G909-330T1U-GP
74.00909.03F
74.00909.03F
2nd source:74.09198.G7F
100mA
250mA
VTTLF1
VTTLF2
VTTLF3
C349
C349
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
-1_0629
I max = 150 mA
VIN
VOUT
DY
DY
GND
SHDN#3NC#4
200mA
1D8V_TXLVDS_S3
12
D
12
12
C53
C53
C64
C64
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
350mA
12
C322
C322
100mA
3D3V_S0
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
1200mA
12
C317
C317
C330
C330
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VCCA_DAC_BG
5
4
12
DY
DY
D
12
12
C68
C68
C54
C54
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
C361
C361
SC1U10V3KX-3GP
12
C34
C34
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
C325
C325
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C324
C324
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC1U10V3KX-3GP
1D25V_S0
12
C141
C141
12
C96
C96
12
C350
C350
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1D05V_S0
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1D25V_S0
SC1U10V3KX-3GP
SC1U10V3KX-3GP
12
C410
C410
SC1U16V3ZY-GP
SC1U16V3ZY-GP
12
12
C69
C69
C333
C333
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
C129
C129
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
C120
C120
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
200mA
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
100mA
12
1D05V_S0
12
C341
C341
DY
DY
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
D3
D3
1
BAS16-1-GP
BAS16-1-GP
83.00016.B11
83.00016.B11
2
1D05V_S0
12
850mA
C58
C58
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D25V_S0
1D8V_S3
1D8V_S3
R180
R180
12
0R0603-PAD
0R0603-PAD
12
C67
C67
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1D05V_HV_S0
3
GMCH (5 of 6)
GMCH (5 of 6)
GMCH (5 of 6)
Volvi2
Volvi2
Volvi2
E
Tahoe
Tahoe
1D05V_S0
3D3V_S0
R29
R29
12
10R3J-3-GP
10R3J-3-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
10 36Thursday, July 05, 2007
10 36Thursday, July 05, 2007
10 36Thursday, July 05, 2007
E
-1
-1
-1
5
AA21
AA24
AA29
AB20
AB23
AB26
D D
C C
B B
A A
5
AB28
AB31
AC10
AC13
AC39
AC43
AC47
AD21
AD26
AD29
AD41
AD45
AD49
AD50
AE10
AE14
AG38
AG43
AG47
AG50
AH40
AH41
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM41
AM45
AN38
AN39
AN43
AP48
AP50
AR11
AR39
AR44
AR47
AT10
AT14
AT41
AT49
AU23
AU29
AU36
AU49
AU51
AV39
AV48
AW12
AW16
U37I
U37I
A13
VSS
A15
VSS
A17
VSS
A24
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AC3
VSS
VSS
VSS
VSS
AD1
VSS
VSS
VSS
VSS
AD3
VSS
VSS
VSS
VSS
AD5
VSS
VSS
AD8
VSS
VSS
VSS
AE6
VSS
AF20
VSS
AF23
VSS
AF24
VSS
AF31
VSS
AG2
VSS
VSS
VSS
VSS
VSS
AH3
VSS
VSS
VSS
AH7
VSS
AH9
VSS
AJ11
VSS
AJ13
VSS
AJ21
VSS
AJ24
VSS
AJ29
VSS
AJ32
VSS
AJ43
VSS
AJ45
VSS
AJ49
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL1
VSS
VSS
VSS
AM3
VSS
AM4
VSS
VSS
VSS
AN1
VSS
VSS
VSS
VSS
AN5
VSS
AN7
VSS
AP4
VSS
VSS
VSS
VSS
AR2
VSS
VSS
VSS
VSS
AR7
VSS
VSS
VSS
VSS
VSS
AU1
VSS
VSS
VSS
AU3
VSS
VSS
VSS
VSS
VSS
VSS
AW1
VSS
VSS
VSS
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
9 OF 10
9 OF 10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
4
4
3
10 OF 10
10 OF 10
U37J
U37J
C46
VSS
C50
VSS
C7
VSS
D13
VSS
D24
VSS
D3
VSS
D32
VSS
D39
VSS
D45
VSS
D49
VSS
E10
VSS
E16
VSS
E24
VSS
E28
VSS
E32
VSS
E47
VSS
F19
VSS
F36
VSS
F4
VSS
F40
VSS
F50
VSS
G1
VSS
G13
VSS
G16
VSS
G19
VSS
G24
VSS
G28
VSS
G29
VSS
G33
VSS
G42
VSS
G45
VSS
G48
VSS
G8
VSS
H24
VSS
H28
VSS
H4
VSS
H45
VSS
J11
VSS
VSS
VSS
J16
VSS
J2
VSS
J24
VSS
J28
VSS
J33
VSS
J35
VSS
J39
VSS
K12
VSS
K47
VSS
K8
VSS
L1
VSS
L17
VSS
L20
VSS
L24
VSS
L28
VSS
L3
VSS
L33
VSS
L49
VSS
M28
VSS
M42
VSS
M46
VSS
M49
VSS
M5
VSS
M50
VSS
M9
VSS
N11
VSS
N14
VSS
N17
VSS
N29
VSS
N32
VSS
N36
VSS
N39
VSS
N44
VSS
N49
VSS
N7
VSS
P19
VSS
P2
VSS
P23
VSS
P3
VSS
P50
VSS
R49
VSS
T39
VSS
T43
VSS
T47
VSS
U41
VSS
U45
VSS
U50
VSS
V2
VSS
V3
VSS
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
GMCH (6 of 6)
GMCH (6 of 6)
GMCH (6 of 6)
Volvi2
Volvi2
Volvi2
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
11 36Thursday, July 05, 2007
11 36Thursday, July 05, 2007
11 36Thursday, July 05, 2007
1
SA
SA
SA
Loading...