Acer Aspire3 A315-51 Schematic
5
Vinaļ¬x
4
3
2
1
ZAV KabyLake-U/R series UMA Platform Block Diagram
D D
DDR4 1866/2133/2400 MT/s
P12
Port 1
DDR4-SoDIMM
SATA/PCIe-SSD
P18
Port 2
DDR4-Memory Down
CH. B CH. A
Port 0
C C
SATA - HDD
P18
Re-Driver
VCP601R
P18
SATA - ODD
(Reserve)
Port 9~12
Port 5
25MHz
LAN / Card reader
RTL8411B-CG
P14
POA
P18
Port 8
RJ45
SD
P14
P14
B B
CCD
DMIC
Touch Screen
P17
PCB 8L STACK UP
LAYER 1 : TOP
LAYER 2 : SGND
Port 6
Wifi / BT
P19
Port 5
Port 6Port 7
P15P15
Daughter Board
Port 2Port 3
M/B Type-C
(Reserve)
P13
Port 2 Port 1
Port 4
D/B USB 2.0
P20
D/B Head Phone
LED
Speaker
Port 1
M/B USB 3.0
Port 3
D/B USB 2.0
Audio Codec
ALC255-CG
LAYER 3 : IN1
LAYER 4 : SVCC
A A
LAYER 5 : IN2
P11
P19
P21
P21P21
P17
P17P17
DDR
Kaby Lake ULT 15W
MCP 1356pins
SATA
PCI-e
USB 3.0
Integrated PCH
USB 2.0
HDA
LAYER 6 : IN3
LAYER 7 : SGND
DDI
eDP
eDP
EMMC
LPC Interface
I2C
SPI
HDMI/DVI level shifter
LCD Panel
2 Lane for 4k2k
P16PTN3366BS (Reserve)
P15
eMMC
P21
Battery
P6
32.768kHz
24MHz
TPM
NPCT650ABAYX
Touch Pad
SPI ROM
24MHz
U42 Reserve
P18
Embedded Controller
P20
P7 P15
HDMI
P16
IT8987E/CX
LAYER 8 : BOT
5
4
3
Power solution
Batery Charger
BQ24780RUYR
+3V/+5V
TPS51225RUKR
+1V_S5
G5335QT2U
+12V_Panel
TPS61087 P31
P22
2
P23
P25 P26
FAN
Keyboard BL
Keyboard
Hall Sensor
+1.2VSUS
RT8231BGQW
+5V_S5/+3V_S5/+5V/+3V
AOZ1331DI
P24 P24
+2.5V_SUS
G5719CTB1U
+1.8V_S5/+1.5V
G5719CTB1U
+VCORE/VCCSA/VCCGT
ISL95829HRTZ-T
P26 P27
+VCCGT
AOZ5049QI
Thermal protection
TMP708AIDBVR
P30 P30
BOM option
U@ : CPU Type
U22@ : Kabylake U-U22
U42@ : Kabylake R-U42
TPC@ : Type-C function
TSI@ : Touch screen I2C
TPM@ : Trusted Platform Module
POA@ : Finger Print on touch pad
KBL@ : Keyboard back light
GS@ : G-Sensor function
SSD@ : Solid State Disk
P20
P20
P20
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
ODD@ : Optical Disc Drive
EMC@ : eMMC function
RAM@ : On Board Memory
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Block Diagram
Block Diagram
Block Diagram
+VCCCORE
AOZ5049QI
P29 P29
1
P28
+VCCSA
AOZ5049QI-5
ZAV
ZAV
ZAV
1 34Wednesday, March 15, 2017
1 34Wednesday, March 15, 2017
1 34Wednesday, March 15, 2017
1A
1A
1A
5
4
3
2
1
KabyLake ULT (DISPLAY,eDP)
D D
HDMICRT
+VCCIO
C C
+1V_VCCST
R14 1K_5%_4
R15 49.9_1%_4
Stuff only for Debug
Ramp will not stuff
+VCCIO
R18 1K_5%_4
B B
CPU_THRMTRIP#
CATERR#
Avoid 125Mhz
H_PROCHOT#
H_PECI (50ohm)
Route on microstrip only
Spacing >18 mils
Trace Length: 0.4~6.125 iches
H_PROCHOT#22,23,27
BPM#[0:7]
Trace Length 1~6 inches
Length match < 300 mils
SM_RCOMP[0:2]
Trace length < 500 mils
Trace width = 12~15 mils
Trace spacing = 20 mils
INT_HDMITX2N16
INT_HDMITX2P16
INT_HDMITX1N16
INT_HDMITX1P16
INT_HDMITX0N16
INT_HDMITX0P16
INT_HDMICLK-16
INT_HDMICLK+16
HDMI_DDCCLK_SW16
HDMI_DDCDATA_SW16
R11 24.9_1%_4
eDP_RCOMP
Trace length < 100
mils
Trace width = 20 mils
Trace spacing = 25
mils
H_PROCHOT#
THRMTRIP#
DGPU_PW_CTRL#4
H_PECI22
HDMI_DDCCLK_SW
HDMI_DDCDATA_SW
CRT_CLK
CRT_DATA
EDP_RCOMP
R16 499_1%_4
R17 100_1%_4
U1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22
N12
GPP_E23
E52
eDP_RCOMP
U@BGA1356P
1 OF 20
CATERR#
TP2
H_PECI
H_PROCHOT#_R
CPU_THRMTRIP#
XDP_BPM#0
TP3
XDP_BPM#1
TP4
XDP_BPM#2
TP5
XDP_BPM#3
TP6
DGPU_PW_CTRL#
R19 49.9_1%_4
R20 49.9_1%_4
R22 49.9_1%_4
R24 49.9_1%_4
AT16
AU16
D63
A54
C65
C63
A65
C55
D55
B54
C56
BA5
AY5
H66
H65
U1D
A6
A7
U@BGA1356P
4 OF 20
KBL_U/R
DDI
DISPLAY SIDEBANDS
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
CPU MISC
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
KBL_U/R
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
EDP
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
RSVD_G46
RSVD_F46
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
eDP_BKLTEN
eDP_BKLTCTL
eDP_VDDEN
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
C47
EDP_TXN0
C46
EDP_TXP0
D46
EDP_TXN1
C45
EDP_TXP1
A45
EDP_TXN2
B45
EDP_TXP2
A47
EDP_TXN3
B47
EDP_TXP3
E45
EDP_AUXN
F45
EDP_AUXP
B52
DP_UTIL
G50
F50
E48
F48
G46
F46
L9
INT_HDMI_HPD
L7
CRT_HPD
L6
PCH_TypeC_UPFb#
N9
SIO_EXT_SCI#
L10
EDP_HPD
R12
PCH_BLON
R11
PCH_BRIGHT
U13
EDP_VDD_EN
B61
XDP_TCK0
D60
XDP_TDI_CPU
A61
XDP_TDO_CPU
C60
XDP_TMS_CPU
B59
XDP_TRST#
B56
XDP_TCK1
D59
XDP_TDI_CPU
A56
XDP_TDO_CPU
C59
XDP_TMS_CPU
C61
XDP_TRST#
A59
XDP_TCK0
If use Intel DCI USB 3.0 fixture need to short
1. XDP_TDO <--> XDP_TDO_CPU
2. XDP_TDI <--> XDP_TDI_CPU
3. XDP_TMS <--> XDP_TMS_CPU
EDP_TXN0 15
EDP_TXP0 15
EDP_TXN1 15
EDP_TXP1 15
EDP_TXN2 15
EDP_TXP2 15
EDP_TXN3 15
EDP_TXP3 15
EDP_AUXN 15
EDP_AUXP 15
R3 *0_5%_4
R4 *0_5%_4
PCH_BLON 15
PCH_BRIGHT 15
EDP_VDD_EN 15
PCH_BRIGHT
INT_HDMI_HPD 16
PCH_TypeC_UPFb# 13
SIO_EXT_SCI# 22
EDP_HPD 15
eDP Panel
Reserve 2 Lane for 4K x 2K
PCH JTAG
JTAG_TCK,JTAG_TMS
Trace Length < 9000mils
TCK,TMS
Trace Length < 9000mils
H_PWRGOOD (50ohm)
Trace Length: 1~11.25 inches
CRT_DATA
CRT_CLK
R5 *2.2K_5%_4
R7 *2.2K_5%_4
Type C change
PCH_TypeC_UPFb#
SIO_EXT_SCI#
CRT_HPD
EDP_HPD
R648 20K_1%_4
R10 10K_5%_4
R12 *100K_5%_4
R13 100K_5%_4
100k pull-down on PCH side
XDP_TDO_CPU
XDP_TMS_CPU
XDP_TDI_CPU
XDP_TCK0
XDP_TCK1
XDP_TRST#
,XDP_TCK1,XDP_TMS
don't need pull up or pull down
R21 51_5%_4
R23 *51_5%_4
R25 *51_5%_4
R26 51_5%_4
R27 *51_5%_4
R28 *51_5%_4
02
+3V_S5
+3V_S5
+3V
MP remove(Intel)
+1V_VCCST
XDP_TCK0 R558 Stuff
+1V_VCCST
R31
*1K_5%_4
+1V_VCCST
2
1 3
Q2
METR3904-G
3
1
2
Q1
FDV301N_G
R30
1K_5%_4
SYS_SHDN# 22,24,30
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
2
Wednesday, March 15, 2017
PROJECT :
Kabylake DISPLAY/eDP
Kabylake DISPLAY/eDP
Kabylake DISPLAY/eDP
ZAV
ZAV
ZAV
1A
1A
2 34
2 34
2 34
1
1A
CPU thermal trip
U2
NC
1
A
5
2
3
GND
*74AUP1G07GW
R32 *0_5%_4
A A
IMVP_PWRGD27
+1V_VCCST
VCC
5
*0.1u/16V_4
Y
4
+3V
C1
R29
10K_5%_4
IMVP_PWRGD_3V 8
IMVP_PWRGD_3V
THRMTRIP#
4
5
4
3
2
1
Change Data and DQS to interleave.
03
D D
M_A_DQ[63:0]11 M_B_DQ[63:0]12
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
U1B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
U@BGA1356P
2 OF 20
M_A_A[13:0]
M_A_DQS#[7:0]
M_A_DQS[7:0]
KBL_U/R
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
M_A_A[13:0] 11
M_A_DQS#[7:0] 11
M_A_DQS[7:0] 11
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
M_A_A5
BB54
M_A_A9
BA52
M_A_A6
AY52
M_A_A8
AW52
M_A_A7
AY55
AW54
M_A_A12
BA54
M_A_A11
BA55
M_A_ACT#
AY54
AU46
M_A_A13
AU48
AT46
AU50
AU52
AY51
M_A_A2
AT48
AT50
M_A_A10
BB50
M_A_A1
AY50
M_A_A0
BA50
M_A_A3
BB52
M_A_A4
AM70
M_A_DQS#0
AM69
M_A_DQS0
AT69
M_A_DQS#1
AT70
M_A_DQS1
BA64
M_A_DQS#2
AY64
M_A_DQS2
AY60
M_A_DQS#3
BA60
M_A_DQS3
BA38
M_A_DQS#4
AY38
M_A_DQS4
AY34
M_A_DQS#5
BA34
M_A_DQS5
BA30
M_A_DQS#6
AY30
M_A_DQS6
AY26
M_A_DQS#7
BA26
M_A_DQS7
AW50
M_A_ALERT#
AT52
M_A_PARITY
AY67
AY68
+VREFDQ_SA_M3
BA67
AW67
DDR_VTT_CTRL
R34 *10K_5%_4
Stuff Q54 for both UMA and GPU in DDR_VTT_CNTL
M_A_CLK0# 11
M_A_CLK0 11
M_A_CLK1# 11
M_A_CLK1 11
M_A_CKE0 11
M_A_CKE1 11
M_A_CS#0 11
M_A_CS#1 11
M_A_ODT0_DIMM 11
M_A_ODT1_DIMM 11
M_A_BG#0 11
M_A_ACT# 11
M_A_BG#1 11
M_A_CAS# 11
M_A_WE# 11
M_A_RAS# 11
M_A_BA#0 11
M_A_BA#1 11
TP7
1 3
Q3
*DDTC144EUA-7-F
M_A_ALERT# 11
M_A_PARITY 11
+VREF_CA_CPU 11
+VREFDQ_SB_M3 12
+1.2VSUS
C2
0.1u/16V_4
2
+3V_S5
R33
*100K_5%_4
DDR_VTTT_PG_CTRL 26
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AH71
AH68
AF71
AF69
AH70
AH69
AT66
AU66
AP65
AN65
AN66
AP66
AT65
AU65
AT61
AU61
AP60
AN60
AN61
AP61
AT60
AU60
AU40
AT40
AT37
AU37
AR40
AP40
AP37
AR37
AT33
AU33
AU30
AT30
AR33
AP33
AR30
AP30
AU27
AT27
AT25
AU25
AP27
AN27
AN25
AP25
AT22
AU22
AU21
AT21
AN22
AP22
AP21
AN21
DRAMRST
+1.2VSUS
R40
A A
5
4
CPU DRAM
CPU_DRAMRST#
3
470_5%_4
R41 *Short_0402
KabyLake ULT (DDR4)KabyLake ULT (DDR4)
U1C
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
DDR1_DQ[10]/DDR0_DQ[26]
DDR1_DQ[11]/DDR0_DQ[27]
DDR1_DQ[12]/DDR0_DQ[28]
DDR1_DQ[13]/DDR0_DQ[29]
DDR1_DQ[14]/DDR0_DQ[30]
DDR1_DQ[15]/DDR0_DQ[31]
DDR1_DQ[16]/DDR0_DQ[48]
DDR1_DQ[17]/DDR0_DQ[49]
DDR1_DQ[18]/DDR0_DQ[50]
DDR1_DQ[19]/DDR0_DQ[51]
DDR1_DQ[20]/DDR0_DQ[52]
DDR1_DQ[21]/DDR0_DQ[53]
DDR1_DQ[22]/DDR0_DQ[54]
DDR1_DQ[23]/DDR0_DQ[55]
DDR1_DQ[24]/DDR0_DQ[56]
DDR1_DQ[25]/DDR0_DQ[57]
DDR1_DQ[26]/DDR0_DQ[58]
DDR1_DQ[27]/DDR0_DQ[59]
DDR1_DQ[28]/DDR0_DQ[60]
DDR1_DQ[29]/DDR0_DQ[61]
DDR1_DQ[30]/DDR0_DQ[62]
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_DQ[32]/DDR1_DQ[16]
DDR1_DQ[33]/DDR1_DQ[17]
DDR1_DQ[34]/DDR1_DQ[18]
DDR1_DQ[35]/DDR1_DQ[19]
DDR1_DQ[36]/DDR1_DQ[20]
DDR1_DQ[37]/DDR1_DQ[21]
DDR1_DQ[38]/DDR1_DQ[22]
DDR1_DQ[39]/DDR1_DQ[23]
DDR1_DQ[40]/DDR1_DQ[24]
DDR1_DQ[41]/DDR1_DQ[25]
DDR1_DQ[42]/DDR1_DQ[26]
DDR1_DQ[43]/DDR1_DQ[27]
DDR1_DQ[44]/DDR1_DQ[28]
DDR1_DQ[45]/DDR1_DQ[29]
DDR1_DQ[46]/DDR1_DQ[30]
DDR1_DQ[47]/DDR1_DQ[31]
DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]
DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]
DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]
DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]
U@BGA1356P
3 OF 20
M_A_ALERT#
M_B_ALERT#
REV:E connect to GND
C3
*0.1u/16V_4
R2
*10_5%_4
KBL_U/R
R35 *0_5%_4
R36 *0_5%_4
DDR_DRAMRST# 11,12
Reserved for ESD
2
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
M_B_A5
AP50
M_B_A9
BA48
M_B_A6
BB48
M_B_A8
AP48
M_B_A7
AP52
AN50
M_B_A12
AN48
M_B_A11
AN53
M_B_ACT#
AN52
BA43
M_B_A13
AY43
AY44
AW44
BB44
AY47
M_B_A2
BA44
AW46
M_B_A10
AY46
M_B_A1
BA46
M_B_A0
BB46
M_B_A3
BA47
M_B_A4
AH66
M_B_DQS#0
AH65
M_B_DQS0
AG69
M_B_DQS#1
AG70
M_B_DQS1
AR66
M_B_DQS#2
AR65
M_B_DQS2
AR61
M_B_DQS#3
AR60
M_B_DQS3
AT38
M_B_DQS#4
AR38
M_B_DQS4
AT32
M_B_DQS#5
AR32
M_B_DQS5
AR25
M_B_DQS#6
AR27
M_B_DQS6
AR22
M_B_DQS#7
AR21
M_B_DQS7
AN43
M_B_ALERT#
AP43
M_B_PARITY
AT13
CPU_DRAMRST#
AR18
SM_RCOMP_0
AT18
SM_RCOMP_1
AU18
SM_RCOMP_2
M_B_A[13:0]
M_B_DQS#[7:0]
M_B_DQS[7:0]
DRAM COMP
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Kabylake MEMORY
Kabylake MEMORY
Kabylake MEMORY
Wednesday, March 15, 2017
Wednesday, March 15, 2017
Wednesday, March 15, 2017
M_B_CLK0# 12
M_B_CLK0 12
M_B_CKE0 12
M_B_CS#0 12
M_B_ODT0_MD 12
M_B_BG#0 12
M_B_ACT# 12
M_B_BG#1 12
M_B_A15 12
M_B_A14 12
M_B_A16 12
M_B_BS#0 12
M_B_BS#1 12
M_B_ALERT# 12
M_B_PARITY 12
R37 200_1%_4
R38 80.6_1%_4
R39 100_1%_4
ZAV
ZAV
ZAV
1
M_B_A[13:0] 12
M_B_DQS#[7:0] 12
M_B_DQS[7:0] 12
3 34
3 34
3 34
1A
1A
1A
5
4
3
2
1
KabyLake ULT (SIDEBAND ) GPIO
H_PECI (50ohm)
If route on microstrip,
Spacing need >18 mils
Trace Length: 2~15 iches
H_PWRGOOD (50ohm)
D D
+3V_S5
R50 2.2K_5%_4
R51 2.2K_5%_4
R52 *2.2K_5%_4
R53 *2.2K_5%_4
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
PU 2.2K for touch pad I2C bus(400 KHz)
GPU Control PU/PD
Trace Length: 1~11.25 inches
Touch PAD
Touch Screen
UART2 for RMT
Touch PAD
Touch Screen
+3V
R64 *10K_5%_4
DGPU_PW_CTRL#
C C
high
low
DGPU_PW_CTRL#2
R80 *EV@100K_5%_4
UMA Only
SG/Optimise
DGPU_HOLD_RST#
UMA Only
GPU power is control by PCH
GPIO (Discrete, SG or Optimize)
DGPU_PW_CTRL#
DGPU_PWROK
R83 *10K_5%_4
DGPU_PWROK PD on GPU side
Setup
DGPU_PW_CTRL#
VGA H/W
Menu
Signal
UMA
1
0
Hidden
Hidden
GPU
UMA boot
GPU boot
+3V
SPKR
PCH_AZ_CODEC_SYNC17
PCH_AZ_CODEC_BITCLK17
PCH_AZ_CODEC_SDOUT17
PCH_AZ_CODEC_SDIN017
PCH_AZ_CODEC_RST#17
R88 *20K_1%_4
HDA
545659-103
TP88
TP89
TP90
TP91
TP92
TP93
ACCEL_INTA20
ODD_PRSNT#18
TPD_INT#20,22
TP_INT_PCH15
I2C0_SDA20
I2C0_SCL20
I2C1_SDA15
I2C1_SCL15
C4 *10p/50V_4
R74 33_5%_4
R68 33_5%_4
R70 33_5%_4
R84 33_5%_4
C5
*10p/50V_4
TP12
Strapping
SPKR17
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
HDA_BCLK_R
HDA_SDO_R
HDA_RST#_R
C810
*10p/50V_4
DMIC_CLK0_R
VGPU_EN
DGPU_HOLD_RST#
DGPU_PWR_EN
GSPI0_MOSI
DGPU_PWROK
GC6_FB_EN
DGPU_EVENT#
GSPI1_MOSI
ODD_PRSNT#
TPD_INT#
UART2_RXD
UART2_TXD
UART2_RTS#
UART2_CTS#
HDA_SYNC_R
SPKR
Skylake-U Strapping Table
Pin Name Strap description
GPP_B14 (SPKR)
B B
GPP_B18
(GSPI0_MOSI)
GPP_C2
(SMBALERT#)
GPP_B22
(GSPI1_MOSI)
GPP_C5
(SML0ALERT#)
SPI0_MOSI
SPI0_MISO
GPP_B23
(SML1ALERT#
/PCHHOT#)
SPI0_IO2
A A
SPI0_IO3
HDA_SDO /
I2S_TXD0
GPP_E19
(DDPB_CTRLDATA)
GPP_E21
(DDPC_CTRLDATA)
Top-Block Swap override PCH_PWROK
No reboot PCH_PWROK
TLS Confidentiality
Boot BIOS Strap Bit (BBS)
eSPI or LPC
Reserved
Reserved
Reserved
Reserved
Reserved
Flash Descriptor Security
Override / Intel ME Debug Mode
Display Port B Detected
Display Port C Detected
5
Sampled
RSMRST#
PCH_PWROK
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
PCH_PWROK
PCH_PWROK
PCH_PWROK
Configuration note
0 = *Disable Top Swap (iPD 20K)
1 = Enable Top Swap Mode
0 = *Disable No Reboot (iPD 20K)
1 = Enable No Reboot Mode
0 = *Disable Intel ME Cryp to TLS(iPD 20K)
1 = Enable Intel ME Cryp to TLS
0 = *SPI (iPD 20K)
1 = LPC
0 = *LPC is selected for EC (iPD 20K)
1 = eSPI selected for EC
+3V
+3V
+3V_S5
+3V
+3V_S5
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
(iPD 20K)
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
0 = *Enable security in the Flash
Description (iPD 20K)
1 = Disable Flash Descriptor Security (Override)
0 = *Port B is not detected (iPD 20K)
1 =Port B is detected
0 = *Port C is not detected (iPD 20K)
1 =Port C is detected
4
change location to near CPU to prevent impact HDA_SDO signal
HDA_SDO_R
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
W4
AB3
AD1
AD2
AD3
AD4
U7
U6
U8
U9
AH9
AH10
AH11
AH12
AF11
AF12
BA22
AY22
BB22
BA21
AY21
AW22
J5
AY20
AW20
AK7
AK6
AK9
AK10
H5
D7
D8
C8
AW5
R89 *1K_5%_4
R90 *1K_5%_4
R91 *10K_5%_4
R92 *1K_5%_4
R93 *1K_5%_4
R95 1K_5%_4
U1F
LPSS ISH
GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
U@BGA1356P
6 OF 20
U1G
AUDIO
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1
+3V_S5
GPP_B14/SPKR
U@BGA1356P
7 OF 20
SPKR
GSPI0_MOSI
GSPI1_MOSI
3
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+3V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
ME_WR# 22
KBY_U/R
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
KBY_U/R
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
SMBALERT# 7
SML0ALERT# 7
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
GPP_F23
GPP_D9
R87 200_1%_4
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+1.8V_S5
+1.8V_S5
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
Sx_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6
SDIO/SDXC
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
+1.8V_S5
Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
2
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
RAM_ID0
RAM_ID1
RAM_ID2
RAM_ID3
RAM ID
ID0ID1ID2ID3
RAM_ID0
RAM_ID1
RAM_ID2
RAM_ID3
Hynix 8Gb
Samsung 8Gb
Micron 8Gb
R43 RAMID0_H@10K_5%_4
R45 RAMID1_H@10K_5%_4
R47 RAMID2_H@10K_5%_4
R49 RAMID3_H@10K_5%_4
R42 RAMID0_L@10K_5%_4
R44 RAMID1_L@10K_5%_4
R46 RAMID2_L@10K_5%_4
R48 RAMID3_L@10K_5%_4
0 0 0 0
0 0 0
0 0 110
1 1 1 1 With out on board memory
UART
UART2_RXD
TP8
UART2_TXD
TP9
UART2_RTS#
UART2_CTS#
TP11
R58 *49.9K_1%_4
R61 *49.9K_1%_4
R62 *49.9K_1%_4TP10
R63 *49.9K_1%_4
Board ID
R72 EMC_N@10K_5%_4
R73 10K_5%_4
R75 GS_N@10K_5%_4
R76 TPM_N@10K_5%_4
R59 *10K_5%_4
R78 TPC_N@10K_5%_4
R81 10K_5%_4
R85 10K_5%_4
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7 Reserve
Touchpad INT
Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
Low
Reserved (Default) Reserve
Non G-sensor
Non TPM
Non Touch panel Touch panel
Reserved (Default)
Reserved (Default)
TPD_INT#
R94 10K_5%_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Kabylake HDA/GPIO/ID
Kabylake HDA/GPIO/ID
Kabylake HDA/GPIO/ID
Wednesday, March 15, 2017
Wednesday, March 15, 2017
Wednesday, March 15, 2017
Quanta PNVendor
AKD5QGSTW05
AKD5QZ0T504
AKD5QGSTL18
+3V_S5
R65 EMC@10K_5%_4
R66 *10K_5%_4
R67 GS@10K_5%_4
R69 TPM@10K_5%_4
R77 10K_5%_4
R79 TPC@10K_5%_4
R82 *10K_5%_4R71 1K_5%_4
R86 *10K_5%_4
eMMCNon eMMC
G-sensor
TPM
Type-CNon Type-C
Reserve
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
High
+3V_S5
ZAV
ZAV
ZAV
04
+3V_S5
+3V_S5
4 34
4 34
4 34
1A
1A
1A
5
Vinaļ¬x
Backside cap
C6
1u/6.3V_4
C9
22u/6.3V_6
C10
22u/6.3V_6
C11
22u/6.3V_6
C12
22u/6.3V_6
C13
22u/6.3V_6
C7
22u/6.3V_6
C14
22u/6.3V_6
Backside cap
C818
C819
*22u/6.3V_6
*22u/6.3V_6
D D
C23
1u/6.3V_4
C24
10u/6.3V_4
C22
1u/6.3V_4
C820
C817
*22u/6.3V_6
*22u/6.3V_6
Backside cap
C25
C27
10u/6.3V_4
10u/6.3V_4
C821
*22u/6.3V_6
C33
10u/6.3V_4
C822
*22u/6.3V_6
C34
10u/6.3V_4
Backside cap
C39
22u/6.3V_6
C40
22u/6.3V_6
C41
22u/6.3V_6
C42
22u/6.3V_6
C43
1u/6.3V_4
C44
10u/6.3V_4
Backside cap
C51
C48
10u/6.3V_4
C49
10u/6.3V_4
C50
10u/6.3V_4
10u/6.3V_4
C52
1u/6.3V_4
C53
10u/6.3V_4
C54
1u/6.3V_4
Backside cap
C57
1u/6.3V_4
C58
1u/6.3V_4
C56
1u/6.3V_4
C C
10u/6.3V_4
C60
10u/6.3V_4
C61
10u/6.3V_4
C62
10u/6.3V_4
C59
Backside cap
For 2+3e CPU
R109 U42@0.0002_5%_8
+VCCCORE
R110 *U42@0.0002_5%_8
R115 U22@0.0002_5%_8
+VCCGT
B B
R116 *U22@0.0002_5%_8
Backside cap
Remove (2016/11/07)
Backside cap
Remove (2016/11/07)
A A
5
Remove (2016/11/07)
+VCCGT_+VCORE
For U42
+VCCGT_+VCORE
For U22
For 2+3e CPU
For 2+3e CPU
ó°µó°µó°µó°µó°øæó°øæó°øæó°øæ
ó°µó°µó°µó°µó°øæó°øæó°øæó°øæ
+1.2VSUS
Backside cap
+1V_SUS
+VCCIO
+1V_SUS
C121
1u/6.3V_4
C129
1u/6.3V_4
C135
10u/6.3V_4
C151
10u/6.3V_4
R121 *Short_0402
4
+VCCCORE
C15
C8
22u/6.3V_6
22u/6.3V_6
C815
C816
22u/6.3V_6
*22u/6.3V_6
C35
C38
10u/6.3V_4
10u/6.3V_4
C46
C45
10u/6.3V_4
1u/6.3V_4
Under CPU
C79
C69
10u/6.3V_4
10u/6.3V_6
C87
C86
10u/6.3V_6
10u/6.3V_4
C123
C122
1u/6.3V_4
1u/6.3V_4
C131
C130
1u/6.3V_4
1u/6.3V_4
100 ohm Near CPU
Backside cap
C138
C136
10u/6.3V_4
1u/6.3V_4
Primary side cap
C152
C153
10u/6.3V_4
10u/6.3V_4
+VDDQC
C163
C162
10u/6.3V_4
1u/6.3V_4
R122 *Short_0603
Primary side cap
R124 *Short_0603
R126 *Short_0603
Backside cap
4
11/23 Reserved
Remove (2016/11/07)
+VCCGT_+VCORE
C70
C71
10u/6.3V_6
10u/6.3V_4
C88
C89
10u/6.3V_6
10u/6.3V_6
+VCCGT
+VCCGT
R108 *U22@0_5%_4
C125
C124
1u/6.3V_4
1u/6.3V_4
C133
C132
1u/6.3V_4
1u/6.3V_4
+VCCGT
VCCGT_SENSE27
VSSGT_SENSE27
C139
1u/6.3V_4
C154
10u/6.3V_4
+1V_VCCST
C164
1u/6.3V_4
C140
1u/6.3V_4
+VCCSTG
C137
1u/6.3V_4
Primary side cap
TP14
TP15
+VCCGT
C73
10u/6.3V_6
C90
10u/6.3V_4
+VCCGT_+VCORE
+VCCGT_+VCORE
+VCCGT
C126
1u/6.3V_4
C134
1u/6.3V_4
R119 100_1%_4
R120 100_1%_4
+1.2VSUS
C172
1u/6.3V_4
+VCCPLL
C179
1u/6.3V_4
A30
A34
A39
A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
A48
A53
A58
A62
A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
A18
A22
AL23
K20
K21
U1L
VCORE_A30
VCORE_A34
VCORE_A39
VCORE_A44
VCORE_AK33
VCORE_AK35
VCORE_AK37
VCORE_AK38
VCORE_AK40
VCORE_AL33
VCORE_AL37
VCORE_AL40
VCORE_AM32
VCORE_AM33
VCORE_AM35
VCORE_AM37
VCORE_AM38
VCORE_G30
RSVD_K32
RSVD_AK32
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO_AE62
VCCEOPIO_AG62
VCCEOPIO_SENSE
VSSEOPIO_SENSE
U@BGA1356P
12 OF 20
KBY_U/R
U1M
CPU POWER 2 OF 4
VCCGT/VCORE_A48
VCCGT/VCORE_A53
VCCGT_A58
VCCGT_A62
VCCGT_A66
VCCGT_AA63
VCCGT_AA64
VCCGT_AA66
VCCGT_AA67
VCCGT_AA69
VCCGT_AA70
VCCGT_AA71
VCCGT_AC64
VCCGT_AC65
VCCGT_AC66
VCCGT_AC67
VCCGT_AC68
VCCGT_AC69
VCCGT_AC70
VCCGT_AC71
VCCGT/VCORE_J43
VCCGT/VCORE_J45
VCCGT/VCORE_J46
VCCGT/VCORE_J48
VCCGT/VCORE_J50
VCCGT/VCORE_J52
VCCGT_J53
VCCGT_J55
VCCGT_J56
VCCGT_J58
VCCGT_J60
VCCGT/VCORE_K48
VCCGT/VCORE_K50
VCCGT/RSVD
VCCGT_K53
VCCGT_K55
VCCGT_K56
VCCGT_K58
VCCGT_K60
VCCGT_L62
VCCGT_L63
VCCGT_L64
VCCGT_L65
VCCGT_L66
VCCGT_L67
VCCGT_L68
VCCGT_L69
VCCGT_L70
VCCGT_L71
VCCGT_M62
VCCGT_N63
VCCGT_N64
VCCGT_N66
VCCGT_N67
VCCGT_N69
VCCGT_SENSE
VSSGT_SENSE
U@BGA1356P
13 OF 20
U1N
KBY_U/R
CPU POWER 3 OF 4
S3
VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51
VDDQC
VCCST
S3
VCCSTG_A22
S0
VCCPLL_OC
S0
1.0V
VccPLL_K20
VccPLL_K21
S3
1.0V
U@BGA1356P
14 OF 20
3
KBY_U/R
CPU POWER 1 OF 4
S0
0.55V~1.5V
2+2 peak 24A
2+2 TPY 17A
2+3e peak 24A
2+3e TPY 17A
1.0V
S0
Sx
1.8V
GT3 CPU
1.0V
S0
co-lay
KBY-R/U
57A
co-lay
KBY-U/R
VccGTx/VCORE_AK42
VccGTx/VCORE_AK43
VccGTx/VCORE_AK45
VccGTx/VCORE_AK46
VccGTx/VCORE_AK48
VccGTx/VCORE_AK50
co-lay
KBY-U/R
VccGTx/VCORE_AL43
VccGTx/VCORE_AL46
7A
VccGTx/VCORE_AL50
co-lay
KBY-U/R
VccGTx/VCORE_AM48
VccGTx/VCORE_AM50
VccGTx/VCORE_AM52
co-lay
KBY-U/R
DDR4
1.2V
2A
S0
2+2 peak 5A
2+2 TPY 4A
2+3e peak 5.1A
2+3e TPY 5A
1.0V
120mA
1.0V
40mA
260mA
120mA
3
VCC
3A
50mA
3A
VCCGT_N70
VCCGT_N71
VCCGT_R63
VCCGT_R64
VCCGT_R65
VCCGT_R66
VCCGT_R67
VCCGT_R68
VCCGT_R69
VCCGT_R70
VCCGT_R71
VCCGT_T62
VCCGT_U65
VCCGT_U68
VCCGT_U71
VCCGT_W63
VCCGT_W64
VCCGT_W65
VCCGT_W66
VCCGT_W67
VCCGT_W68
VCCGT_W69
VCCGT_W70
VCCGT_W71
VCCGT_Y62
VccGTx/RSVD
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTx_SENSE
VSSGTx_SENSE
S0
0.85V/0.95V
VCCIO_AK28
3.0A
VCCIO_AK30
VCCIO_AL30
VCCIO_AL42
VCCIO_AM28
VCCIO_AM30
VCCIO_AM42
1.15V
VCCSA_AK23
VCCSA_AK25
VCCSA_G23
VCCSA_G25
VCCSA_G27
VCCSA_G28
VCCSA_J22
VCCSA_J23
VCCSA_J27
VCCSA_K23
VCCSA_K25
VCCSA_K27
VCCSA_K28
VCCSA_K30
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
+VCCCORE
G32
VCORE_G32
G33
VCORE_G33
G35
VCORE_G35
G37
VCORE_G37
G38
VCORE_G38
G40
VCORE_G40
G42
VCORE_G42
J30
VCORE_J30
J33
VCORE_J33
J37
VCORE_J37
J40
VCORE_J40
K33
VCORE_K33
K35
VCORE_K35
K37
VCORE_K37
K38
VCORE_K38
K40
VCORE_K40
K42
VCORE_K42
K43
VCORE_K43
E32
VCC_SENSE
E33
VSS_SENSE
B63
VIDALERT#
A63
VIDSCK
D64
VIDSOUT
G20
VCCSTG_G20
+VCCGT
N70
Close CPU
N71
R63
R64
R65
R66
R67
C65
R68
47u/6.3V_8
R69
R70
R71
T62
U65
C75
U68
22u/6.3V_6
U71
W63
W64
W65
W66
C91
W67
22u/6.3V_6
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
1.U22---C103/C104/C120/C127/C128
AK62
AL61
2.U42---C103/C104/C120/C127/C128
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
R123 100_1%_4
R125 100_1%_4
TP17
TP18
VSASS_SENSE 27
VSA_SENSE 27
TP16
C55
1u/6.3V_4
+VCCSA
C16
47u/6.3V_8
C26
10u/6.3V_4
R96 100_1%_4
R97 100_1%_4
C66
47u/6.3V_8
C80
22u/6.3V_6
C92
22u/6.3V_6
C103
U42@22u/6.3V_6
C120
U42@22u/6.3V_6
C127
U42@22u/6.3V_6
+VCCIO
+VCCSA
100 ohm near CPU
+VCCSTG
C17
47u/6.3V_8
C28
10u/6.3V_4
+VCCCORE
C67
47u/6.3V_8
C76
22u/6.3V_6
C93
22u/6.3V_6
+VCCGTX_+VCORE
C104
U42@22u/6.3V_6
+VCCGTX_+VCORE
+VCCGTX_+VCORE
C128
U42@22u/6.3V_6
C141
10u/6.3V_4
C147
1u/6.3V_4
C155
10u/6.3V_4
C165
1u/6.3V_4
C173
10u/6.3V_4
2
Primary side cap
C18
C19
47u/6.3V_8
47u/6.3V_8
Primary side cap
C29
C30
10u/6.3V_4
10u/6.3V_4
100 ohm Near CPU
VCORE_SENSE 27
VCORESS_SENSE 27
H_CPU_SVIDART#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
C77
C68
47u/6.3V_8
47u/6.3V_8
C81
C82
22u/6.3V_6
22u/6.3V_6
C94
22u/6.3V_6
Remove (2016/11/07)
Remove (2016/11/07)
+VCCGTX_+VCORE
ó°µó°µó°µó°µó°µó°µó°µó°µó°øæó°øæó°øæó°øæ
ó°µó°µó°µó°µó°øæó°øæó°øæó°øæ
Backside cap
C142
C143
10u/6.3V_4
1u/6.3V_4
Primary side cap
C149
C148
1u/6.3V_4
1u/6.3V_4
Backside cap
C157
C156
10u/6.3V_4
10u/6.3V_4
Backside cap
C167
C166
1u/6.3V_4
1u/6.3V_4
Primary side cap
C174
C175
10u/6.3V_4
10u/6.3V_4
2
C20
47u/6.3V_8
C31
10u/6.3V_4
C78
47u/6.3V_8
C83
22u/6.3V_6
Imax 3(A)
C144
1u/6.3V_4
C150
1u/6.3V_4
C158
10u/6.3V_4
C168
1u/6.3V_4
C176
10u/6.3V_4
C21
47u/6.3V_8
C32
10u/6.3V_4
SVID
H_CPU_SVIDDAT
Place PU resistor
close to CPU
Place PU resistor
close to CPU
H_CPU_SVIDART#
H_CPU_SVIDCLK
C145
1u/6.3V_4
C159
10u/6.3V_4
C169
1u/6.3V_4
C177
10u/6.3V_4
C84
22u/6.3V_6
C37
C36
10u/6.3V_4
10u/6.3V_4
+1V_VCCST
Must close to CPU
C47
R98
1000p/50V_4
100_1%_4
+1V_VCCST
R107 220_1%_4
C85
22u/6.3V_6
Primary side cap
Backside cap
R117 U42@0.0002_5%_8
R118 *U42@0.0002_5%_8
C146
1u/6.3V_4
C161
C160
10u/6.3V_4
10u/6.3V_4
C171
C170
1u/6.3V_4
1u/6.3V_4
C178
10u/6.3V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
R106
54.9_1%_4
1.U22--->R117
2.U42--->R117
+VCCCORE
Kabylake POWER/U42
Kabylake POWER/U42
Kabylake POWER/U42
Wednesday, March 15, 2017
Wednesday, March 15, 2017
Wednesday, March 15, 2017
1
05
H_CPU_SVIDDAT 27
VR_SVID_ALERT#_VCORE 27
H_CPU_SVIDCLK 27
ó°µó°µó°µó°µó°µó°µó°µó°µó°øæó°øæó°øæó°øæ
ó°µó°µó°µó°µó°øæó°øæó°øæó°øæ
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
ZAV
PROJECT :
ZAV
PROJECT :
ZAV
5 34
5 34
1
5 34
1A
1A
1A
5
4
3
2
1
KabyLake ULT (GPU, SATA , ODD, CLK ,USB2&3)
U1H
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
PCIE5_TXN
PCIE5_TXP
PCIE6_TXN
PCIE6_TXP
PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP
PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP
PCIE_RCOMPN
PCIE_RCOMPP
PCIE11_RXN
PCIE11_RXP
PCIE11_TXN
PCIE11_TXP
PCIE12_RXN
PCIE12_RXP
PCIE12_TXN
PCIE12_TXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
U@BGA1356P
8 OF 20
U1J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
U@BGA1356P
10 OF 20
+3V_S5
4
D D
GPU
PCIE5_RXN_LAN14
PCIE5_RXP_LAN14
PCIE5_TXN_LAN14
PCIE5_TXP_LAN14
PCIE6_RXN_WLAN19
WIFI
PCIE6_RXP_WLAN19
PCIE6_TXN_WLAN19
PCIE6_TXP_WLAN19
HDD
ODD
C C
SSD
B B
VGALANWLAN
CLK_PCIE_NGFF1_N19
CLK_PCIE_NGFF1_P19
M.2
SSD
PCIE_CLKREQ_NGFF1#19
CLK_PCIE_LANN14
CLK_PCIE_LANP14
CLK_PCIE_LAN_REQ#14
CLK_PCIE_WLANN19
CLK_PCIE_WLANP19
PCIE_CLKREQ_WLAN#19
A A
CLK_PCIE_REQ0#
CLK_PCIE_REQ1#
CLK_PCIE_REQ2#
CLK_PCIE_REQ3#
CLK_PCIE_REQ4#
CLK_PCIE_REQ5#
5
C180 0.1u/16V_4
C181 0.1u/16V_4
C182 0.1u/16V_4
C184 0.1u/16V_4
SATA_RXN018
SATA_RXP018
SATA_TXN018
SATA_TXP018
SATA_RXN118
SATA_RXP118
SATA_TXN118
SATA_TXP118
PCIE9_RXN19
PCIE9_RXP19
PCIE9_TXN19
PCIE9_TXP19
PCIE10_RXN19
PCIE10_RXP19
PCIE10_TXN19
PCIE10_TXP19
R137 100_1%_4
TP19
TP20
PCIE11_RXN19
PCIE11_RXP19
PCIE11_TXN19
PCIE11_TXP19
PCIE12_RXN19
PCIE12_RXP19
PCIE12_TXN19
PCIE12_TXP19
R143 *Short_0402
R146 *Short_0402
R149 *Short_0402
R152 10K_5%_4
R153 10K_5%_4
R154 *10K_5%_4
R155 *10K_5%_4
R156 10K_5%_4
R157 10K_5%_4
XDP_PRDY#
XDP_PREQ#
PIRQA#
CLK_PCIE_REQ0#
TP85
CLK_PCIE_REQ1#
CLK_PCIE_REQ2#
TP24
CLK_PCIE_REQ3#
TP25
CLK_PCIE_REQ4#
CLK_PCIE_REQ5#
+3V
KBY_U/R
+3V_S5
+3V_S5
+3V_S5
KBY_U/R
CLOCK SIGNALS
+3V_S5
+3V_S5
+3V_S5
+3V_S5
colay
KBY-U/R
+3V_S5
+3V_S5
+3V_S5
add for EC reset RTC
CLR_CMOS22
SSIC / USB3
USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP
USB2
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
+3V_S5
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN/NC
XTAL24_OUT/NC
XCLK_BIASREF
SRTCRST#
RTCRST#
R158
100K_5%_4
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E8/SATALED#
F43
E43
BA17
E37
XTAL24_IN
E35
XTAL24_OUT
E42
XCLK_BIASREF
AM18
RTC_X1
RTCX1
AM20
RTC_X2
RTCX2
AN18
SRTC_RST#
AM16
RTC_RST#
3
2
1
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
CLK_PCIE_XDPN
CLK_PCIE_XDPP
SUSCLK
SRTC_RST#
Q4
*2N7002K
USBCOMP
R135 113_1%_4
USB2_ID
R136 1K_5%_4
R138 1K_5%_4
USB_OC0#
USB_OC1#
USB_OC2#
EMMC_RST
DEVSLP0
DEVSLP1
DEVSLP2
SATAGP0
SATAGP1
R140 *Short_0402
R144 2.7K_1%_4
3
USB3_RXN1 21
USB3_RXP1 21
USB3_TXN1 21
USB3_TXP1 21
USB3_RXN2 13
USB3_RXP2 13
USB3_TXN2 13
USB3_TXP2 13
USB3_RXN3 13
USB3_RXP3 13
USB3_TXN3 13
USB3_TXP3 13
USB2N1 21
USB2P1 21
USB2N2 13
USB2P2 13
USB2N3 21
USB2P3 21
USB2N4 21
USB2P4 21
USB2N5 19
USB2P5 19
USB2N6 15
USB2P6 15
USB2N7 15
USB2P7 15
USB2N8 18
USB2P8 18
TP22
TP23
SUSCLK 19
1V power plane
0.71 checklist p14
CLR_CMOS
MB/UB3
Type - C
MB/UB3
TYPE-CLAN
DB/UB2
DB/UB2
BT
Touch Screen
CCD
POA
USBCOMP
Impedance = 50 ohm
Trace length < 500 mils
Trace spacing = 15 mils
DEVSLP0 18
DEVSLP2 19
NGFF3_DET 19
+1V_S5
3
2
1
C831 0.1u/16V_4
Q5
2N7002K
C830 0.1u/16V_4
RTC_RST#
PCH PU/PD
USB_OC0#
USB_OC1#
USB_OC2#
DEVSLP0
DEVSLP1
DEVSLP2
PIRQA#
SATAGP0
SATAGP1
R127 10K_5%_4
R128 10K_5%_4
R129 10K_5%_4
R130 *10K_5%_4
R131 *10K_5%_4
R132 *10K_5%_4
R133 10K_5%_4
R134 *10K_5%_4
R748 *10K_5%_4
+3V_S5
Skylake-U userd 24 MHz (50 Ohm ESR) XTAL
C183 U22@33p/50V_4
R139 U22@1M_5%_4
4
3
Y1
USB_OC0# 21
USB_OC1# 21
USB_OC2# 13
EMMC_RST 21
MB/UB3
DB/UB2
Type-C
eMMC
XTAL24_IN
XTAL24_OUT
U22@24MHZ/20ppm
1
2
C185 U22@33p/50V_4
Near CPU
C828 0.1u/16V_4
C829 0.1u/16V_4
RTC Clock 32.768KHz (CPU)
Trace length < 1000 mils
C186 10p/50V_4
C187 10p/50V_4
12
Y2
32.768KHZ/20ppm
RTC Circuitry (RTC)
+3VPCU
On SKL voltage at VCCRTC does not exceed 3.2V
R145
1.5K_1%_4
+3V_RTC_2
R148 1K_5%_4
VCCRTC_2
R150
45.3K_1%_4
12
+-
3 4
2
+3V_RTC_1
+3V_RTC_[0:2]
Trace width = 20 mils
53014-00201-V09
CN19
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3V_RTC
D1
2
1
Wednesday, March 15, 2017
Wednesday, March 15, 2017
Wednesday, March 15, 2017
R147
3
20K_1%_4
BAT54CW
R151
20K_1%_4
C189
1u/6.3V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Kabylake PCIe/USB/CLK/SAT
Kabylake PCIe/USB/CLK/SAT
Kabylake PCIe/USB/CLK/SAT
06
+3V
RTC_X1
R141
10M_5%_4
RTC_X2
+3V_RTC
Trace width = 30 mils
C188
1u/6.3V_4
C190
1u/6.3V_4
ZAV
ZAV
ZAV
6 34
6 34
1
6 34
RTC_RST#
12
J1
*JUMP
SRTC_RST#
1A
1A
1A
5
4
3
2
1
+3V_S5
+3V_S5
+3V_S5
07
R180
2.2K_5%_4
SMB_ME1_CLK
SMB_ME1_DAT
CLK_SDATA 11,20
CLK_SCLK 11,20
U1E
SPI - FLASH
EC_RCIN#
AW3
AW2
AW13
AY11
AV2
AV3
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
U@BGA1356P
5 OF 20
+3V_S5
+3V_S5
PCH SPI ROM(8M)
15ohm CS01502JB12
PCH_SPI_CLK
D D
PCH_SPI_SO
PCH_SPI_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#
For M.2 wifi module must
SIO_RCIN#22
IRQ_SERIRQ18,22
C C
R172 *Short_0402
IRQ_SERIRQ
33ohm CS03302JB29
PCH_SPI_CLK_EC22
PCH_SPI_SI_EC22
PCH_SPI_SO_EC22
SP@ socket P/N: DFHS08FS023 only for A-TEST
B B
SPI ROM
Skylake
3.3V
Kabylake
3.3V
Vender Size Quanta P/N Vender P/N
AKE3EFP0N07
8M
AKE2EZN0Q00
8M
WND AKE3DZN0N01
16M
GGD
16M
AKE3DF00Q00
PCH_SPI_CLK_EC
PCH_SPI_SI_EC
PCH_SPI_SO_EC
W25Q64FVSSIQWND
GD25B64CSIGRGGD
W25Q128FVSIQ
GD25B128CSIGR
PCH_SPI_SO
PCH_SPI_SO_EC
1A-13
+3V_PCH_ME
KBY_U/R
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
PCH_SPI_CS0#
R178 15_5%_4
R181 15_5%_4
3.3K is original and for no
support fast read function
LPC
R187 1K_5%_4
SMBUS, SMLINK
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
GPP_B23/SML1ALERT#/PCHHOT#
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
GPP_A5/LFRAME#/ESPI_CS#
+3V_S5
GPP_A14/SUS_STAT#/ESPI_RESET#
+3V_S5
+3V_S5
GPP_A9/CLKOUT_LPC0/ESPI_CLK
+3V_S5
+3V_S5
+3V_LDO_EC
+3V_S5
U3
1
SPI_SO_8M
SPI_CS0#_UR_ME22
2
3
4
W25Q64FVSSIQ
SPI_WP_IO2_ME
PCH_SPI_IO2
PCH_SPI_IO3
+3V_PCH_ME
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
*10p/50V_4
R176 *0_5%_6
R177 *Short_0603
VCC
CS
IO3/HOLD
IO1/DO
CLK
IO2/WP
IO0/DI
GND
PCH_SPI_CLK_EC
PCH_SPI_SI_EC
R188 15_5%_4
R189 15_5%_4
R190 *Short_0402
R193 10K_5%_4
R7
PCH_MBCLK0_R
R8
PCH_MBDAT0_R
R10
SMBALERT#
R9
VGA_MBCLK
W2
VGA_MBDATA
W1
SML0ALERT#
W3
SMB_ME1_CLK
V3
SMB_ME1_DAT
AM7
SMB1ALERT#
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
CLKRUN#
C812
+3V_PCH_ME
8
7
SPI_HOLD_IO3_ME
6
SPI_CLK_8M
5
SPI_SI_8M
R185 15_5%_4
R186 15_5%_4
PCH_SPI_CS0#
SPI_CS0#_UR_ME
R162 *Short_0402
R163 *Short_0402
R164 *Short_0402
R165 *Short_0402
R167 *0_5%_4
C191 *0.1u/16V_4
R171 22_5%_4
R173 22_5%_4
R174 22_5%_4
C811
*10p/50V_4
R183 15_5%_4
R184 15_5%_4
SPI_WP_IO2_ME
SPI_HOLD_IO3_ME
only 0ohm option
Strapping
SMBALERT# 4
SML0ALERT# 4
TP94
ckl v0.71 p.24
LPC_LAD0 18,19,22
LPC_LAD1 18,19,22
LPC_LAD2 18,19,22
LPC_LAD3 18,19,22
LPC_LFRAME# 18,19,22
TP26
CLK_PCI_EC 22
PCLK_TPM 18
CLK_PCI_LPC 19
CLKRUN# 18,22
+3V_PCH_ME
C192 0.1u/16V_4
R182 1K_5%_4
PCH_SPI_CLK
PCH_SPI_SI
C193
*22p/50V_4
reserve for SPI fast read
CLKRUN#
IRQ_SERIRQ
EC_RCIN#
R159 8.2K_1%_4
R160 10K_5%_4
R161 10K_5%_4
SMBus
PCH_MBCLK0_R
PCH_MBDAT0_R
VGA_MBDATA
VGA_MBCLK
SMB1ALERT#
Termination Resistor Requirement for PCH PCHHOT# Pin
Reserve PU 150K resister
S5 S0
SMBus(PCH)
PCH_MBDAT0_R
PCH_MBCLK0_R
R166 2.2K_5%_4
R168 2.2K_5%_4
R169 2.2K_5%_4
R170 2.2K_5%_4
R175 *150K_5%_4
+3V
Change to 2.2k
3 4
6 1
2.2K_5%_4
5
2
R179
Q6A
2N7002KDW
Q6B
2N7002KDW
PCH_XDP_WLAN/S5 DDR_TP/S0
SMBus(EC)
2ND_MBCLK22
2ND_MBDATA22
2ND_MBCLK
2ND_MBDATA
R191 *Short_0402
R192 *Short_0402
EC/S5
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
5
4
3
2
Wednesday, March 15, 2017
PROJECT :
Kabylake SPI
Kabylake SPI
Kabylake SPI
ZAV
ZAV
ZAV
1A
1A
7 34
7 34
1
7 34
1A
5
4
3
2
1
PCI_PLTRST#
SYS_RESET#
R195 10K_5%_4
VCCST_PWRGD
Near CPU
C827 0.1u/16V_4
TP34
PCIE_LAN_WAKE#
PCH_RSMRST#
PROC_PWRGD
SYS_PWROK_R
EC_PWROK_R
DPWROK_R PCH_ACPRESENT
PCH_SUSPWRDNACK_C
SUSACK#_R
TP35
+VCCIO
Reserve PU 10K
R197 *10K_5%_4
D D
PROC_PWRGD
EC only PD, so PD 10K
R209
10K_5%_4
C C
RSMRST#22
EC_PWROK
PCH_SUSPWRDNACK22
PCIE_LAN_WAKE#14,19
R194 *Short_0402
R198 *Short_0402
R199 *0_5%_4
R203 *0_5%_4
U1K
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
U@BGA1356P
11 OF 20
U1I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
U@BGA1356P
9 OF 20
KBY_U/R
SYSTEM POWER MANAGEMENT
+3V_S5
I
I
+3V_S5
+3V_S5
+3V_S5
+3V_S5
KBY_U/R
+3V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
GPP_B11/EXT_PWR_GATE#
+3V_S5
+3V_S5
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B2/VRALERT#
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
INTRUDER#
AM10
MPHY_EXT_PWR
AM11
PCH_VRALERT#
R213 100_1%_4
R215 200_1%_4
SUS0#
SUSB#
SUSC#
PCH_SLP_S5#
PCH_SLP_SUS#
PCH_SLP_LAN#
PCH_SLP_WLAN#
PCH_SLP_A#
PCH_PWRBTN#
PCH_BATLOW#
TP37
EMMC_DATA_0 21
EMMC_DATA_1 21
EMMC_DATA_2 21
EMMC_DATA_3 21
EMMC_DATA_4 21
EMMC_DATA_5 21
EMMC_DATA_6 21
EMMC_DATA_7 21
EMMC_RCLK 21
EMMC_CLK 21
EMMC_CMD 21
R200 *Short_0402
R201 *Short_0402
TP33
R205 1M_5%_4
TP36
REV:E ī£¢ī£¢ī£¢ī£¢tPLT17(max
200us) ->SLP_S3#
assertion to IMVP
VR_ON(VRON) deassertion
VRON_R27
SUS0# 25
SUSB# 22,25
SUSC# 22
TP27
TP28
TP29
TP30
TP31
DNBSWON# 22
SB_ACDC 22
TP32
+3V_RTC
REV:E tPLT15(max 200us)
->SLP_S4# assertion to
VDDQ(+1.35VSUS) ramp
down start(SUSON)
12/28 Delete U12/C361 & Add R695
3/21 Add U12/C361 & Delete R695
SUSON_R25,26
+3V_S5
C195 *0.1u/16V_4
1
4
U5
SUSB#
2
VRON
3 5
*MC74VHC1G08DFT2G
+3V
+3V_S5
SUSON 22
SUSON_R
SYS_RESET#
PCH_ACPRESENT
PCH_BATLOW#
PCIE_LAN_WAKE#
MPHY_EXT_PWRPCH_SUSPWRDNACK_C
PCH_VRALERT#
PCH_RSMRST#
PCH_PWROK
SYS_PWROK_R
4
U4
R637 *Short_0402
R196 10K_5%_4
R202 8.2K_1%_4
R204 8.2K_1%_4
R206 10K_5%_4
R207 *1K_5%_4
R208 10K_5%_4
12/25 Change R206 pull-up to +3V_S5
R210 10K_5%_4
R211 10K_5%_4
R212 10K_5%_4
+3V_S5
C194 *0.1u/16V_4
1
SUSC#
2
SUSON
3 5
*MC74VHC1G08DFT2G
12/28 Delete U14/R245/C372 & Change "MAINON_R" to "MAINON"
VRON 22
12/28 Change from "SUSB#" to "MAINON"
1/28 Change from "MAINON" to "SUSB#"
08
R638 *Short_0402
B B
PLTRST# Buffer
A A
PCI_PLTRST#
+3V
C201 0.1u/16V_4
1
2
U8
3 5
MC74VHC1G08DFT2G
5
Power Sequence
For platforms not supporting Deep
Sx, connect directly to RSMRST#
4
R225
100K_5%_4
R1
*10_5%_4
PCH_PWROK22
C824
0.1u/16V_4
DPWROK_R
PLTRST# 14,18,19,21,22
Reserved for ESD
Non Deep Sx
R217 *Short_0402
No Deep Sx
R218 *Short_0402
Remove
SYSPWOK
4
EC_PWROK
EC_PWROK_R
PCH_RSMRST#
R223 *0_5%_4
R226
*10K_5%_4
3
EC_PWROK 22
Close to CPU
VCCST_PWRGD
C200
1000p/50V_4
Stuff 1000P/50V
+1V_VCCST
R220 60.4_1%_4
Shortpad change
to 60.4 ohm. 11/6
VCCST_PWRGD_EN
2013/10/21 Del APWORK.1A-6
CRB is via +1.05V PGVCCST PWRGD
+3V_S5
R219
C197
1K_5%_4
0.1u/16V_4
VCCST_PWRGD_R
R222 *0_5%_4
R224 *Short_0402
2
U6
VCC
NC
5
4
1
A
2
Y
3
GND
74AUP1G07GW
PCH_PWROK
HWPG
Rev:D change netmane for HWPG
VCCST_PWRGD_EN_L
C198
*1000p/50V_4
HWPG 22IMVP_PWRGD_3V 2
B2A
S0->S5 & S0->S3
Power of sequence 1us
SUSB# -> VCCST_PWRGD
+3V_S5
C196 0.1u/16V_4
1
2
VCCST_PWRGD_EN
U7
3 5
MC74VHC1G08DFT2G
SUSB#
C199
*1000p/50V_4
4
R221 *0_5%_4
Reserve 1000P/50V
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
Wednesday, March 15, 2017
PROJECT :
Kabylake PM/eMMC
Kabylake PM/eMMC
Kabylake PM/eMMC
ZAV
ZAV
ZAV
8 34
8 34
1
8 34
1A
1A
1A
5
4
3
2
1
U1S
E68
AL25
AL27
BA70
BA68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
U@BGA1356P
19 OF 20
D D
CFG4
R237 49.9_1%_4
+1V_S5
C C
B B
CFG_RCOMP
R639 1.5K_1%_4
R779 U42@0_5%_4
R780 U42@0_5%_4
KBY_U/R
RESERVED SIGNALS-1
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
AR56
AW71
AW70
AP56
C64
TP38
Rev:F reserve TP
R244 *Short_0402
R246 *Short_0402
R248 100K_5%_4
+1V_VCCST
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+3VPCU
+3V_S5
+3V
+1.5V
+3V_S5
+1V_S5
R245 *Short_0603
+3V_S5
+1V_S5
+1V_S5
For 2+3e CPU No Stuff
TP40
C204 1u/6.3V_4
C205 1u/6.3V_4
C834 22u/6.3V_6
C206 22u/6.3V_6
C207 1u/6.3V_4
C212 1u/6.3V_4
R239 *0_5%_6
R640 *Short_0603
R641 *Short_0603
R642 *0_5%_6
R643 *Short_0603
C213 1u/6.3V_4
C215 1u/6.3V_4
C218 47u/6.3V_8
C222 1u/6.3V_4
C832 0.1u/16V_4
C224 *1u/6.3V_4
C833 0.1u/16V_4
C225*0.1u/16V_4
C2261u/6.3V_4
C228 1u/6.3V_4
+VCCPRIM_3P3
C229 1u/6.3V_4
C230 1u/6.3V_4
C836 0.1u/16V_4
Remove (2016/11/07)
+VCCDSW_1P0
+VCCHDA
+VCCPSPI
U1O
AB19
VCCPRIM_1P0_AB19
AB20
VCCPRIM_1P0_AB20
P18
VCCPRIM_1P0_P18
AF18
VCCPRIM_CORE_AF18
AF19
VCCPRIM_CORE_AF19
V20
VCCPRIM_CORE_V20
V21
VCCPRIM_CORE_V21
AL1
DCPDSW_1p0
K17
VCCMPHYAON_1P0_K17
L1
VCCMPHYAON_1P0_L1
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0_K15
L15
VCCAMPHYPLL_1P0_L15
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0_AF20
AF21
VCCSRAM_1P0_AF21
T19
VCCSRAM_1P0_T19
T20
VCCSRAM_1P0_T20
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB_1P0
U@BGA1356P
15 OF 20
KBY_U/R
CPU POWER 4 OF 4
2.899A
2.57A
1.714A
0.03A
0.09A
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1p8
VCCRTCPRIM_3p3
VCCRTC_AK19
VCCRTC_BB14
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
VCCPRIM_1P0 & VCCPRIM_CORE Short
GPIO Group Power Plane
AK15
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
+VCCPGPPA
AG15
+VCCPGPPB
Y16
+VCCPGPPC
Y15
+VCCPGPPD
T16
+VCCPGPPE
AF16
+VCCPGPPF
AD15
+VCCPGPPG
V19
+VCCPRIM_3P3
T1
AA1
+VCCATS_1P8
AK17
+VCCPRTCPRIM_3P3
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
V0P85A_VID0
AN13
C214 1u/6.3V_4
C217 1u/6.3V_4
+VCCPRTC
C219 1u/6.3V_4
DCPRTC
C223 *1u/6.3V_4
C227 1u/6.3V_4
C208 *1u/6.3V_4
C202 1u/6.3V_4
C203 1u/6.3V_4
C209 *1u/6.3V_4
R227 *Short_0603
R230 *Short_0603
R231 *Short_0603
R243 *Short_0603
R232 *Short_0603
R233 *Short_0603
R229 *Short_0603
C210 1u/6.3V_4
C211 *1u/6.3V_4
C837 0.1u/16V_4
R234 *Short_0603
R235 *Short_0603
C216 0.1u/16V_4
R236 *Short_0603
C220 0.1u/16V_4
C221 0.1u/16V_4
TP39
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+1.8V_S5
+3V_S5
+1V_S5
+1.8V_S5
+3V_S5
+3V_RTC
+1V_S5
09
Pin Name Strap description Configuration
CFG[0] Stall reset sequence after PCU PLL lock until de-asserted
CFG[1]
CFG[2]
Reserved Configuration lane
PCI Express* Static x16 Lane Numbering Reversal
1 = *Normal Operation; No stall (iPU 3K)
0 = Stall
1 = *Normal Operation(iPU 3K)
0 = Lan number reversed
Note
H & S processor used only
CFG[3] Reserved Configuration lane
CFG[4]
CFG[6:5] PCI Express* Bifunction
A A
eDP enable
CFG[7] PEG Training
CFG[19:8]
Reserved Configuration lane
5
1 = Disabled (iPU 3K)
0 = *Enabled
00 = 1x8, 2x4 PCI Express*
01 = reserved
10 = 2x8 PCI Express*
11 = 1x16 PCI Express*
1 = *PEG Train immediatedly follow
RESET# de-assertion (iPU 3K)
0 = PEG wait for BIOS for training
4
CFG4
R249 1K_5%_4
H & S processor used only
H & S processor used only
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
2
Wednesday, March 15, 2017
PROJECT :
Kabylake POWER
Kabylake POWER
Kabylake POWER
ZAV
ZAV
ZAV
1A
1A
9 34
9 34
1
9 34
1A
5
4
3
2
1
KabyLake ULT (GND)
KBY_U/R
A67
A70
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL2
AL28
AL32
AL35
AL38
AL4
AL45
AL48
AL52
AL55
AL58
AL64
A5
U1P
GND 1 OF 3
VSS_A5
VSS_A67
VSS_A70
VSS_AA2
VSS_AA4
VSS_AA65
VSS_AA68
VSS_AB15
VSS_AB16
VSS_AB18
VSS_AB21
VSS_AB8
VSS_AD13
VSS_AD16
VSS_AD19
VSS_AD20
VSS_AD21
VSS_AD62
VSS_AD8
VSS_AE64
VSS_AE65
VSS_AE66
VSS_AE67
VSS_AE68
VSS_AE69
VSS_AF1
VSS_AF10
VSS_AF15
VSS_AF17
VSS_AF2
VSS_AF4
VSS_AF63
VSS_AG16
VSS_AG17
VSS_AG18
VSS_AG19
VSS_AG20
VSS_AG21
VSS_AG71
VSS_AH13
VSS_AH6
VSS_AH63
VSS_AH64
VSS_AH67
VSS_AJ15
VSS_AJ18
VSS_AJ20
VSS_AJ4
VSS_AK11
VSS_AK16
VSS_AK18
VSS_AK21
VSS_AK22
VSS_AK27
VSS_AK63
VSS_AK68
VSS_AK69
VSS_AK8
VSS_AL2
VSS_AL28
VSS_AL32
VSS_AL35
VSS_AL38
VSS_AL4
VSS_AL45
VSS_AL48
VSS_AL52
VSS_AL55
VSS_AL58
VSS_AL64
U@BGA1356P
16 OF 20
5
VSS_AL65
VSS_AL66
VSS_AM13
VSS_AM21
VSS_AM25
VSS_AM27
VSS_AM43
VSS_AM45
VSS_AM46
VSS_AM55
VSS_AM60
VSS_AM61
VSS_AM68
VSS_AM71
VSS_AM8
VSS_AN20
VSS_AN23
VSS_AN28
VSS_AN30
VSS_AN32
VSS_AN33
VSS_AN35
VSS_AN37
VSS_AN38
VSS_AN40
VSS_AN42
VSS_AN58
VSS_AN63
VSS_AP10
VSS_AP18
VSS_AP20
VSS_AP23
VSS_AP28
VSS_AP32
VSS_AP35
VSS_AP38
VSS_AP42
VSS_AP58
VSS_AP63
VSS_AP68
VSS_AP70
VSS_AR11
VSS_AR15
VSS_AR16
VSS_AR20
VSS_AR23
VSS_AR28
VSS_AR35
VSS_AR42
VSS_AR43
VSS_AR45
VSS_AR46
VSS_AR48
VSS_AR5
VSS_AR50
VSS_AR52
VSS_AR53
VSS_AR55
VSS_AR58
VSS_AR63
VSS_AR8
VSS_AT2
VSS_AT20
VSS_AT23
VSS_AT28
VSS_AT35
VSS_AT4
VSS_AT42
VSS_AT56
VSS_AT58
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
4
D D
C C
B B
A A
U1Q
GND 2 OF 3
VSS_AT63
VSS_AT68
VSS_AT71
VSS_AU10
VSS_AU15
VSS_AU20
VSS_AU32
VSS_AU38
VSS_AV1
VSS_AV68
VSS_AV69
VSS_AV70
VSS_AV71
VSS_AW10
VSS_AW12
VSS_AW14
VSS_AW16
VSS_AW18
VSS_AW21
VSS_AW23
VSS_AW26
VSS_AW28
VSS_AW30
VSS_AW32
VSS_AW34
VSS_AW36
VSS_AW38
VSS_AW41
VSS_AW43
VSS_AW45
VSS_AW47
VSS_AW49
VSS_AW51
VSS_AW53
VSS_AW55
VSS_AW57
VSS_AW6
VSS_AW60
VSS_AW62
VSS_AW64
VSS_AW66
VSS_AW8
VSS_AY66
VSS_B10
VSS_B14
VSS_B18
VSS_B22
VSS_B30
VSS_B34
VSS_B39
VSS_B44
VSS_B48
VSS_B53
VSS_B58
VSS_B62
VSS_B66
VSS_B71
VSS_BA1
VSS_BA10
VSS_BA14
VSS_BA18
VSS_BA2
VSS_BA23
VSS_BA28
VSS_BA32
VSS_BA36
VSS_F68
VSS_BA45
U@BGA1356P
17 OF 20
KBY_U/R
VSS_BA49
VSS_BA53
VSS_BA57
VSS_BA6
VSS_BA62
VSS_BA66
VSS_BA71
VSS_BB18
VSS_BB26
VSS_BB30
VSS_BB34
VSS_BB38
VSS_BB43
VSS_BB55
VSS_BB6
VSS_BB60
VSS_BB64
VSS_BB67
VSS_BB70
VSS_C1
VSS_C25
VSS_C5
VSS_D10
VSS_D11
VSS_D14
VSS_D18
VSS_D22
VSS_D25
VSS_D26
VSS_D30
VSS_D34
VSS_D39
VSS_D44
VSS_D45
VSS_D47
VSS_D48
VSS_D53
VSS_D58
VSS_D6
VSS_D62
VSS_D66
VSS_D69
VSS_E11
VSS_E15
VSS_E18
VSS_E21
VSS_E46
VSS_E50
VSS_E53
VSS_E56
VSS_E6
VSS_E65
VSS_E71
VSS_F1
VSS_F13
VSS_F2
VSS_F22
VSS_F23
VSS_F27
VSS_F28
VSS_F32
VSS_F33
VSS_F35
VSS_F37
VSS_F38
VSS_F4
VSS_F40
VSS_F42
VSS_BA41
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
G10
G22
G43
G45
G48
G52
G55
G58
G60
G63
G66
H15
H18
H71
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
J11
J13
J25
J28
J32
J35
J38
J42
F8
G5
G6
J8
U1R
GND 3 OF 3
VSS_F8
VSS_G10
VSS_G22
VSS_G43
VSS_G45
VSS_G48
VSS_G5
VSS_G52
VSS_G55
VSS_G58
VSS_G6
VSS_G60
VSS_G63
VSS_G66
VSS_H15
VSS_H18
VSS_H71
VSS_J11
VSS_J13
VSS_J25
VSS_J28
VSS_J32
VSS_J35
VSS_J38
VSS_J42
VSS_J8
VSS_K16
VSS_K18
VSS_K22
VSS_K61
VSS_K63
VSS_K64
VSS_K65
VSS_K66
VSS_K67
VSS_K68
VSS_K70
VSS_K71
VSS_L11
VSS_L16
VSS_L17
U@BGA1356P
18 OF 20
KBY_U/R
VSS_L18
VSS_L2
VSS_L20
VSS_L4
VSS_L8
VSS_N10
VSS_N13
VSS_N19
VSS_N21
VSS_N6
VSS_N65
VSS_N68
VSS_P17
VSS_P19
VSS_P20
VSS_P21
VSS_R13
VSS_R6
VSS_T15
VSS_T17
VSS_T18
VSS_T2
VSS_T21
VSS_T4
VSS_U10
VSS_U63
VSS_U64
VSS_U66
VSS_U67
VSS_U69
VSS_U70
VSS_V16
VSS_V17
VSS_V18
VSS_W13
VSS_W6
VSS_W9
VSS_Y17
VSS_Y19
VSS_Y20
VSS_Y21
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
+1.8V_S5
U1T
AW69
AW68
AU56
AW48
XTAL24_OUT_C7
R250 *0_5%_4
C231
*1u/6.3V_4
Reserve 1uF no stuff in CPU U11,U12 ball
support Cannonlake-U PCH
U12
U11
H11
C7
U@BGA1356P
20 OF 20
KBY_U/R
SPARE
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD/XTAL24_OUT
RSVD_U12
RSVD_U11
RSVD_H11
colay
KBY-U/R
RSVD_F6
RSVD/XTAL24_IN
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
For KBL R U42
(i)Non-stuff on KBL-U
XTAL24_IN_E3_R
XTAL24_IN_E3
XTAL24_OUT_C7
3
2
R251 U42@0_5%_4
R252
U42@1M_5%_4
R253 U42@0_5%_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
Wednesday, March 15, 2017
XTAL24_OUT_C7_R
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Kabylake GND/U42
Kabylake GND/U42
Kabylake GND/U42
C232 U42@27p/50V_4
4
3
Y3
U42@24MHZ/20ppm
1
2
C233 U42@27p/50V_4
ZAV
ZAV
ZAV
1
10
F6
E3
XTAL24_IN_E3
C11
B11
A11
D12
C12
F52
10 34
10 34
10 34
1A
1A
1A
5
4
3
2
1
M_A_A[13:0]3 M_A_DQ[63:0] 3
D D
M_A_WE#3
M_A_CAS#3
M_A_RAS#3
M_A_ACT#3
M_A_PARITY3
M_A_ALERT#3
+1.2VSUS
R256
240_1%_4
M_A_EVENT#
C C
B B
+3V
R258
*10K_5%_4
R262
10K_5%_4
R259
*10K_5%_4
R263
10K_5%_4
R257
*10K_5%_4
CHA_SA0 CHA_SA1 CHA_SA2
R261
10K_5%_4
DDR_DRAMRST#3,12
M_A_BA#03
M_A_BA#13
M_A_BG#03
M_A_BG#13
M_A_CS#03
M_A_CS#13
M_A_CKE03
M_A_CKE13
M_A_CLK03
M_A_CLK0#3
M_A_CLK13
M_A_CLK1#3
M_A_ODT0_DIMM3
M_A_ODT1_DIMM3
CLK_SCLK7,20
CLK_SDATA7,20
R264 240_1%_4
R265 240_1%_4
R266 240_1%_4
R267 240_1%_4
R269 240_1%_4
R270 240_1%_4
R271 240_1%_4
R272 240_1%_4
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP42
TP41
M_A_EVENT#
C236 *0.1u/16V_4
CHA_SA0
CHA_SA1
CHA_SA2
+1.2VSUS
M_A_CB0
M_A_CB1
M_A_CB2
M_A_CB3
M_A_CB4
M_A_CB5
M_A_CB6
M_A_CB7
P/N and F/P
JDIM1A
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10/AP
120
A11
119
A12
158
A13
151
A14/WE#
156
A15/CAS#
152
A16/RAS#
162
CS2#/C0
165
CS3#/C1
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
150
BA0
145
BA1
115
BG0
113
BG1
149
CS0#
157
CS1#
109
CKE0
110
CKE1
137
CK0
139
CK0#
138
CK1
140
CK1#
155
ODT0
161
ODT1
253
SCL
254
SDA
256
SA0
260
SA1
166
SA2
92
CB0
91
CB1
101
CB2
105
CB3
88
CB4
87
CB5
100
CB6
104
CB7
12
DM0
33
DM1
54
DM2
75
DM3
178
DM4
199
DM5
220
DM6
241
DM7
96
DBI8#
D4AS0-26001-1P52
JDIM1B
C237
0.022u/25V_4
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
141
VDD11
142
VDD12
147
VDD13
148
VDD14
153
VDD15
154
VDD16
159
VDD17
160
VDD18
163
VDD19
1
VSS1
5
VSS2
9
VSS3
15
VSS4
19
VSS5
23
VSS6
27
VSS7
31
VSS8
35
VSS9
39
VSS10
43
VSS11
47
VSS12
51
VSS13
57
VSS14
61
VSS15
65
VSS16
69
VSS17
73
VSS18
77
VSS19
81
VSS20
85
VSS21
89
VSS22
93
VSS23
99
VSS24
103
VSS25
107
VSS26
167
VSS27
171
VSS28
175
VSS29
181
VSS30
185
VSS31
189
VSS32
193
VSS33
197
VSS34
201
VSS35
205
VSS36
209
VSS37
213
VSS38
217
VSS39
223
VSS40
227
VSS41
231
VSS42
235
VSS43
239
VSS44
243
VSS45
247
VSS46
251
VSS47
263
263
264
264
D4AS0-26001-1P52
R274 2_1%_6
R277 24.9_1%_4
VDDSPD
VPP1
VPP2
VTT
VREFCA
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
(260P)
DDR4 SODIMM 260 PIN
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
GND#1
GND#2
+1.2VSUS
R273
1K_1%_4
VREF_CA_DIMM0
R276
1K_1%_4
8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
(260P)
DDR4 SODIMM 260 PIN
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DQS#8
M_A_DQ1
7
M_A_DQ4
20
M_A_DQ6
21
M_A_DQ2
4
M_A_DQ5
3
M_A_DQ0
16
M_A_DQ3
17
M_A_DQ7
28
M_A_DQ8
29
M_A_DQ12
41
M_A_DQ15
42
M_A_DQ14
24
M_A_DQ13
25
M_A_DQ9
38
M_A_DQ10
37
M_A_DQ11
50
M_A_DQ21
49
M_A_DQ20
62
M_A_DQ19
63
M_A_DQ22
46
M_A_DQ17
45
M_A_DQ16
58
M_A_DQ23
59
M_A_DQ18
70
M_A_DQ24
71
M_A_DQ28
83
M_A_DQ30
84
M_A_DQ26
66
M_A_DQ25
67
M_A_DQ29
79
M_A_DQ31
80
M_A_DQ27
174
M_A_DQ32
173
M_A_DQ36
187
M_A_DQ34
186
M_A_DQ39
170
M_A_DQ37
169
M_A_DQ33
183
M_A_DQ35
182
M_A_DQ38
195
M_A_DQ45
194
M_A_DQ41
207
M_A_DQ43
208
M_A_DQ46
191
M_A_DQ44
190
M_A_DQ40
203
M_A_DQ42
204
M_A_DQ47
216
M_A_DQ49
215
M_A_DQ53
228
M_A_DQ54
229
M_A_DQ50
211
M_A_DQ52
212
M_A_DQ48
224
M_A_DQ51
225
M_A_DQ55
237
M_A_DQ56
236
M_A_DQ58
249
M_A_DQ57
250
M_A_DQ61
232
M_A_DQ62
233
M_A_DQ59
245
M_A_DQ63
246
M_A_DQ60
13
M_A_DQS0
34
M_A_DQS1
55
M_A_DQS2
76
M_A_DQS3
179
M_A_DQS4
200
M_A_DQS5
221
M_A_DQS6
242
M_A_DQS7
97
M_A_DQS8
11
M_A_DQS#0
32
M_A_DQS#1
53
M_A_DQS#2
74
M_A_DQS#3
177
M_A_DQS#4
198
M_A_DQS#5
219
M_A_DQS#6
240
M_A_DQS#7
95
M_A_DQS#8
0-7
8-15
16-23
24-31
32-39
40-47
48-55
R260
56-63
M_A_DQS[7:0] 3
M_A_DQS#[7:0] 3
240_1%_4
M_A_DQS8
240_1%_4
M_A_DQS#8
R268
12/21 Change JDIM2 footprint to "ddr4-d4as0-26001-1p52-std-smt " for SMT requset
VREF DQ0 M1 Solution
+1.2VSUS
2250mA
+1.2VSUS
+1.2VSUS+1.2VSUS
+VREF_CA_CPU
255
257
259
258
164
2
6
10
14
18
22
26
30
36
40
44
48
52
56
60
64
68
72
78
82
86
90
94
98
102
106
168
172
176
180
184
188
192
196
202
206
210
214
218
222
226
230
234
238
244
248
252
261
262
C234 2.2u/6.3V_6
C235 0.1u/25V_4
R254 *0_5%_4
R255 *Short_0402
0.5A
600mA
VREF_CA_DIMM0
R275 *0_5%_4
+2.5V_SUS
12/4 Change for +3.3V to +3V
+VDDQ_VTT
+2.5V
+3V
11
+VDDQ
Place these Caps near So-Dimm1.
1uF/10uF 4pcs on each side of connector
+1.2VSUS
C238 1u/6.3V_4
C241 1u/6.3V_4
C244 1u/6.3V_4
C246 1u/6.3V_4
C248 1u/6.3V_4
C251 1u/6.3V_4
A A
+VDDQ12,26
+2.5V_SUS12,26
+1.2VSUS3,5,12,26
+VDDQ_VTT12,26
+VREF_CA_CPU3
+3V2,4,6,7,8,9,14,15,16,17,18,19,20,21,22,24,25,26,27,30
5
4
C253 1u/6.3V_4
C255 1u/6.3V_4
C257 10u/6.3V_6
C258 10u/6.3V_6
C259 10u/6.3V_6
C260 10u/6.3V_6
C261 10u/6.3V_6
C262 10u/6.3V_6
C263 10u/6.3V_6
C264 10u/6.3V_6
3
+VDDQ_VTT
+3V
C240 1u/6.3V_4
C243 1u/6.3V_4
C245 1u/6.3V_4
C247 1u/6.3V_4
C250 10u/6.3V_6
C254 0.1u/16V_4
C256 2.2u/6.3V_6
VREF_CA_DIMM0
+2.5V_SUS
C239 0.1u/16V_4
C242 2.2u/6.3V_6
C249 0.1u/16V_4
C252 2.2u/6.3V_6
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
Wednesday, March 15, 2017
Date: Sheet of
2
Wednesday, March 15, 2017
PROJECT :
DDR4 DIMM-STD 4H (CH. A)
DDR4 DIMM-STD 4H (CH. A)
DDR4 DIMM-STD 4H (CH. A)
ZAV
ZAV
ZAV
11 34
11 34
11 34
1
1A
1A
1A
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