Acer 6120 Schematic

A
1 1
B
C
D
E
Compal Confidential
2 2
ZZZ
PAU30 M/B Schematics Document
ZZZ
DAZ@
DAZ@
DAZ0F900100
DAZ0F900100
PCB PAU30 LA-6392P LS-6391P/6392P/6393P/6394 P
PCB PAU30 LA-6392P LS-6391P/6392P/6393P/6394 P
ZZZ1
ZZZ1
DA1@
DA1@
DA80000KE10
DA80000KE10
PCB 0F9 LA-6392P REV1 M/B
PCB 0F9 LA-6392P REV1 M/B
ZZZ2
ZZZ2
DA2@
DA2@
DA20000KT10
ZZZ3
ZZZ3
ZZZ4
ZZZ4
ZZZ5
ZZZ5
DA20000KT10
DA2@
DA2@
DA20000KU10
DA20000KU10
DA2@
DA2@
DA20000KV10
DA20000KV10
DA2@
DA2@
DA20000LE10
DA20000LE10
A
3 3
PCB 0F9 LS-6391P REV1 POWER_BTN/B
PCB 0F9 LS-6391P REV1 POWER_BTN/B
PCB 0F9 LS-6392P REV1 SWITCH/B
PCB 0F9 LS-6392P REV1 SWITCH/B
PCB 0F9 LS-6393P REV1 LED/B
PCB 0F9 LS-6393P REV1 LED/B
4 4
PCB 0F9 LS-6394P REV1 LID SWITCH/B
PCB 0F9 LS-6394P REV1 LID SWITCH/B
Intel Arrandale Processo SV with DDRIII + Ibex Peak-M
2010-11-22
REV:1.0
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009/11/23 2010/11/23
2009/11/23 2010/11/23
2009/11/23 2010/11/23
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
1 51Monday, November 22, 2010
1 51Monday, November 22, 2010
1 51Monday, November 22, 2010
E
0.1
0.1
0.1
A
B
C
D
E
Compal Confidential
Model Name : PAU30 File Name : LA-6392P
1 1
HDMI Conn.
page 34
2 2
MINI Card x1
3G/GPS
page 36
port 4
port 3
port 2 port 1
CRT Conn.
page 33
HDMI(DDPC)
PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S)
Fan Control
page 46
LVDS Conn.
page 32
SDVO to LVDS Converter
page 31,32
LVDS Conn.
page 30
LVDS(UMA)
SDVO(DDPB)
Analog RGB(UMA)
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
Intel
Arrandale (UMA only)
Processor
rPGA988A
FDI x8 (UMA)
100MHz
2.7GT/s
Intel
Ibex Peak-M
100MHz
100MHz
PCH
page 15,16,17,18 19,20,21,22,23
page 4,5,6,7,8,9
DMI x4
100MHz
1GB/s x4
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 800/1066
USB conn x2
USB port 0 USB port 1
page 40 page 40 page 30
USBx14
HD Audio
3.3V 48MHz
3.3V 24MHz
SPI
204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
Bluetooth Conn
USB port 13
page 10,11
Camera
USB port 8
SIMM Card
USB port 5
Touch Screen x2
USB port 2, 3
page 40
3G Minicard
USB port 9
WLAN Minicard
USB port 4
page 36page 36page 36
PCI-E to USB3.0
µPD720200
page 39
MINI Card x1
WLAN
page 36 page 37
USB Conn. (USB 3.0 x 1
3 3
USB 2.0 x 1
page 39
RTC CKT.
page 15
Power On/Off CKT.
page 43
LAN(GbE)
AR8151
RJ45
page 38
port 0
SATA HDD Conn.
page 35
EC I/O Buffer
SM BUS
LPC BUS
33MHz
ENE KB926
page 41
BIOS ROM
page 42page 42
SPI ROM x1
page 15
G-Sensor
page 46
HDA Codec
ALC271X
page 44
Int. Speaker Phone Jack x 2
page 45 page 45
Clock Generator
IDT: 9LVS3199AKLFT SILEGO: SLG8LV597VTR Realtek: RTM890N-631-GRT
133/120/100/96/14.318MHZ to PCH
page 14
Int.MIC
page 45
DC/DC Interface CKT.
4 4
page 47,48
Power Circuit DC/DC
page 47,48
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPA L ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPA L ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPA L ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009/11/23 2010/11/23
2009/11/23 2010/11/23
2009/11/23 2010/11/23
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
E
2 51Tuesday, September 07, 2010
2 51Tuesday, September 07, 2010
2 51Tuesday, September 07, 2010
0.1
0.1
0.1
A
Voltage Rails
Power Plane Description
VIN
1 1
2 2
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+
+CPU_CORE
+VGA_CORE
+VGFX_CORE Core voltage for Arrandale GPU (only for arrandaleCPU)
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator
+1.0VSDGPU
+1.05VS_VTT
+1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH
+1.5V
+1.5VS
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
+3VALW +3VALW always on power rail
+3VALW_EC +3VALW always to KBC ON ON ON*
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON
+3VS
+5VALW
+5VS +5VALW to +5VS switched power rail OFFON OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON*
+RTCVCC RTC power
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC SM Bus1 address
Device
Smart Battery
PCH SM Bus address
3 3
Device
Clock Generator (9LVS3199AKLFT, RTM890N-631-GRT)
DDR DIMM0
DDR DIMM2
43level BOM Config
431954BOL01
4 4
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
Core voltage for GPU
+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
+1.05VS_VTTP to +1.05VS_VTT switched power rail for ARD CPU
+1.5VP to +1.5V power rail for DDRIII ON ON OFF
+1.5V to +1.5VS switched power rail
+3VALW to +3VS power rail
+5VALWP to +5VALW power rail
EC SM Bus2 address
Address Address
0001 011X b
Address
1101 0010b
1001 000Xb
1001 010Xb
SMT MB A6392 PAU30 W/3G
Device
BOM ConfigP/N Des.
DAZ@
B
S1 S3 S5
N/A N/A N/A
ON
ON OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
OFF
OFF
OFF
ON ON*
ON*
OFF
OFF
ON ON*
ONON
C
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
Rb / Rd / Rf V min
0 1 2 3 4 5 6 7 NC
BOARD ID Table
Board ID
0 1 2 3 4 5 6 7
USB Port Table
USB 2.0 USB 1.1 Port
UHCI0
EHCI1
EHCI2
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
100K +/- 5%Ra/Rc/Re
0
8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%
PCB Revision
0 1 2 3 4 5 6 7 8
9 10 11 12 13
D
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
LOW LOW LOW LOW
AD_BID
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
0 V
ON
ON
ON
ON
ON
V typ
AD_BID
0 V 0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
1.185 V 1.264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
BTO Option Table
BTO Item BOM Structure
0.1
0.2
0.3
1.0
VRAM VRAM
Connector CONN@
Blue Tooth BT@
3 External USB Port
USB Port (Left Side) USB Port (Left Side) USB/Touch Screen2 USB/Touch Screen1 Mini Card(WLAN) SIMM CARD
Camera Mini Card(3G)
Blue Tooth
Unpop
ON
ON
ON
OFF
OFF
V
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
ON ON
ON
OFF
OFF
OFF
max
E
LOW
OFF
OFF
OFF
X76@
VENTURA@Ventura
@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
2009/11/23 2010/11/23
2009/11/23 2010/11/23
2009/11/23 2010/11/23
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
3 51Tuesday, September 07, 2010
3 51Tuesday, September 07, 2010
3 51Tuesday, September 07, 2010
E
0.1
0.1
0.1
5
JCPU1A
JCPU1A
DMI_PTX_H RX_N0 DMI_PTX_H RX_N1 DMI_PTX_H RX_N2 DMI_PTX_H RX_N3
DMI_PTX_H RX_P0 DMI_PTX_H RX_P1 DMI_PTX_H RX_P2
H_FDI_INT(15)
DMI_PTX_H RX_P3
DMI_HTX_P RX_N0 DMI_HTX_P RX_N1 DMI_HTX_P RX_N2 DMI_HTX_P RX_N3
DMI_HTX_P RX_P0 DMI_HTX_P RX_P1 DMI_HTX_P RX_P2 DMI_HTX_P RX_P3
H_FDI_TXN 0 H_FDI_TXN 1 H_FDI_TXN 2 H_FDI_TXN 3 H_FDI_TXN 4 H_FDI_TXN 5 H_FDI_TXN 6 H_FDI_TXN 7
H_FDI_TXP 0 H_FDI_TXP 1 H_FDI_TXP 2 H_FDI_TXP 3 H_FDI_TXP 4 H_FDI_TXP 5 H_FDI_TXP 6 H_FDI_TXP 7
D D
C C
H_FDI_FSYNC0(15) H_FDI_FSYNC1(15)
H_FDI_LSYNC0(15) H_FDI_LSYNC1(15)
B B
A24
DMI_RX#[0]
C23
DMI_RX#[1]
B22
DMI_RX#[2]
A21
DMI_RX#[3]
B24
DMI_RX[0]
D23
DMI_RX[1]
B23
DMI_RX[2]
A22
DMI_RX[3]
D24
DMI_TX#[0]
G24
DMI_TX#[1]
F23
DMI_TX#[2]
H23
DMI_TX#[3]
D25
DMI_TX[0]
F24
DMI_TX[1]
E23
DMI_TX[2]
G23
DMI_TX[3]
E22
FDI_TX#[0]
D21
FDI_TX#[1]
D19
FDI_TX#[2]
D18
FDI_TX#[3]
G21
FDI_TX#[4]
E19
FDI_TX#[5]
F21
FDI_TX#[6]
G18
FDI_TX#[7]
D22
FDI_TX[0]
C21
FDI_TX[1]
D20
FDI_TX[2]
C18
FDI_TX[3]
G22
FDI_TX[4]
E20
FDI_TX[5]
F20
FDI_TX[6]
G19
FDI_TX[7]
F17
FDI_FSYNC[0]
E17
FDI_FSYNC[1]
C17
FDI_INT
F18
FDI_LSYNC[0]
D17
FDI_LSYNC[1]
IC,AUB_CFD _rPGA,R1P0
IC,AUB_CFD _rPGA,R1P0
CONN@
CONN@
DMI Intel(R) FDI
DMI Intel(R) FDI
PEG_ICOMPI
10mil
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
15mil
PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]
PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]
PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]
PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]
PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14]
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]
B26 A26 B27 A25
K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31
J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30
L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26
L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25
4
PEG_IRCOM P
EXP_RBIAS
R1419
R1419
1 2
R1420
R1420
1 2
3
49.9_040 2_1%
49.9_040 2_1%
750_040 2_1%
750_040 2_1%
6/22 remove unused pin net
DMI_PTX_H RX_N[0..3] (15) DMI_PTX_H RX_P[0..3] (15)
DMI_HTX_P RX_N[0..3] (15) DMI_HTX_P RX_P[0..3] (15)
H_FDI_TXN [0..7] (15)
H_FDI_TXP [0..7] (15)
CFG0
CFG3 CFG4
CFG7
2
JCPU1E
JCPU1E
AP25
RSVD1
AL25
RSVD2
AL24
RSVD3
AL22
RSVD4
AJ33
RSVD5
AG9 M27
H17 G25 G17
E31
E30
AM30 AM28 AP31
AL32
AL30 AM31 AN29 AM32 AK32 AK31 AK28
AJ28 AN30 AN32
AJ32
AJ29
AJ30 AK30
H16
B19 A19
A20 B20
AC9 AB9
A34 A33
C35 B35
L28 J17
U9
T9
C1
A3
J29 J28
RSVD6 RSVD7 RSVD8 SA_DIMM_VREF SB_DIMM_VREF RSVD11 RSVD12 RSVD13 RSVD14
CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86
RSVD15 RSVD16
RSVD17 RSVD18
RSVD19 RSVD20
RSVD21 RSVD22
RSVD_NCTF_23 RSVD_NCTF_24
RSVD26 RSVD27
RSVD_NCTF_28 RSVD_NCTF_29
RSVD_NCTF_30 RSVD_NCTF_31
(CFD Only) (CFD Only)
RSVD_NCTF_37
RSVD_NCTF_40 RSVD_NCTF_41
RSVD_NCTF_42 RSVD_NCTF_43
RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57
RSVD_TP_59 RSVD_TP_60
RESERVED
RESERVED
RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75
RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85
RSVD32 RSVD33
RSVD34 RSVD35
RSVD36
RSVD38 RSVD39
RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53
RSVD58
KEY RSVD62 RSVD63 RSVD64 RSVD65
VSS
AJ13 AJ12
AH25 AK26
AL26 AR2
AJ26 AJ27
AP1 AT2
AT3 AR1
AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32
E15 F15 A2 D15 C15 AJ15 AH15
AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3
V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9
AP34
1
IC,AUB_CFD _rPGA,R1P0
IC,AUB_CFD _rPGA,R1P0
CONN@
CONN@
eDP Signals Mapping eDP Singal
eDP_TX0
PEG Singals
PEG_HTX_C_GRX_P15 eDP_TX#0 PEG_HTX_C_GRX_N15 eDP_TX1 PEG_HTX_C_GRX_P14 eDP_TX#1
A A
eDP_TX2 eDP_TX#2 eDP_TX3 eDP_TX#3 eDP_AUX eDP_AUX# eDP_HPD#
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_P12
5
Lane Reversal
PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3
Security Class ification
Security Class ification
Security Class ification
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/11/ 23 2010/11/ 23
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
CFG0 - PCI-Express Configuration Select
*1:Single PEG 0:Bifurcation enabled
CFG3 - PCI-Express Static Lane Reversal
*1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CFG4 - Display Port Presence
*1:Disabled; No Physical Display Port attached to Embedd ed Display Port 0:Enabled; An externa l Display Port device is connected to the Emb edded Display Port
*:Default
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PROCESSOR (1/6) DMI,FDI,PEG
PROCESSOR (1/6) DMI,FDI,PEG
PROCESSOR (1/6) DMI,FDI,PEG
B
B
B
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
1
1.0
1.0
1.0
4 51Monday, November 22, 2 010
4 51Monday, November 22, 2 010
4 51Monday, November 22, 2 010
5
JCPU1B
R1421 20_0402 _1% R142 1 20_0402 _1%
R1422 20_0402 _1% R142 2 20_0402 _1%
R1423 49.9_040 2_1% R142 3 49.9_040 2_1%
R1424 49.9_040 2_1% R142 4 49.9_040 2_1%
D D
H_PECI(18)
H_PROCH OT#(47)
H_THERM TRIP#(18)
R1427
1 2
0_0402_ 5%
0_0402_ 5%
R1437
R1437
1 2
0_0402_ 5%
0_0402_ 5%
12
12
12
12
PAD
PAD
T48
T48
R142 7
del R1442 07/22
H_PM_SYNC(15)
R1443
R144 3
1 2
0_0402_ 5%
C C
H_CPUPW RGD(18)
PM_DRAM _PWRGD(15)
PLT_RST #(17)
2009/2/4 #414044 DG
Update Rev1.11
0_0402_ 5%
R1446 0_0402_ 5%
0_0402_ 5%
R1447
1 2
0_0402_ 5%
0_0402_ 5%
R1449
1 2
1.5K_040 2_1%
1.5K_040 2_1%
R144 6
1 2
R144 7
R14 49
H_COMP3
H_COMP2
H_COMP1
H_COMP0
SKTOCC# _R
@
@
H_CATER R#
H_PECI_R
H_PROCH OT#
H_THERM TRIP#_R
H_CPURS T#
H_CPUPW RGD_1
H_CPUPW RGD_0
PM_DRAM _PWRGD_R
H_VTTPW RGD_R
H_PW RGD_XDP_R
PLT_RST #_R
12
R1450
R1450 750_040 2_1%
750_040 2_1%
JCPU1B
AT23
AT24
G16
AT26
AH24
AK14
AT15
AN26
AK15
AP26
AL15
AN14
AN27
AK13
AM15
AM26
AL14
IC,AUB_CFD _rPGA,R1P0
IC,AUB_CFD _rPGA,R1P0
CONN@
CONN@
4
COMP3
COMP2
COMP1
COMP0
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
RESET_OBS#
PM_SYNC
VCCPWRGOOD_1
VCCPWRGOOD_0
SM_DRAMPWROK
VTTPWRGOOD
TAPPWRGOOD
RSTIN#
MISC THERMAL
MISC THERMAL
DPLL_REF_SSCLK#
CLOCKS
CLOCKS
DDR3
MISC
DDR3
MISC
PWR MANAGEMENT
PWR MANAGEMENT
JTAG & BPM
JTAG & BPM
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
SM_DRAMRST#
SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]
PM_EXT_TS#[0] PM_EXT_TS#[1]
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
TDI_M
TDO_M
DBR#
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
TDI
A16 B16
AR30 AT30
E16 D16
A18 A17
F6
AL1 AM1 AN1
AN15 AP15
AT28 AP27
AN28 AP28 AT27
AT29 AR27 AR29 AP29
AN25
AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23
3
CLK_CPU _DP_R CLK_CPU _DP#_R
SM_RCOM P_0 SM_RCOM P_1 SM_RCOM P_2
PM_EXTT S#0 PM_EXTT S#1_R
XDP_PRD Y# XDP_PRE Q#
XDP_TCL K XDP_TMS XDP_TRS T#
XDP_TDI_R XDP_TDO _R XDP_TDI_M XDP_TDO _M
XDP_DBR #_R
CLK_CPU _BCLK (18) CLK_CPU _BCLK# (18)
CLK_CPU _XDP CLK_CPU _XDP#
CLK_CPU _DMI (14) CLK_CPU _DMI# (14)
R1445 0_0402_ 5% R1445 0_0402_ 5%
1 2
XDP_OBS 0 XDP_OBS 1 XDP_OBS 2 XDP_OBS 3 XDP_OBS 4 XDP_OBS 5 XDP_OBS 6 XDP_OBS 7
T55 PAD @T55 P AD@ T56 PAD @T56 P AD@
SM_DRAM RST# (10)
1 2
R1429 10 0K_0402_5%
R1429 10 0K_0402_5%
R1433 10K_040 2_5% R143 3 10K_040 2_5%
1 2
R1435 10K_040 2_5% R143 5 10K_040 2_5%
1 2
R1436 0_0402_ 5% R1436 0_0402_ 5%
1 2
SM_RCOM P_0 SM_RCOM P_1 SM_RCOM P_2
R1439 100_040 2_1% R1439 100_040 2_1% R1440 24.9_040 2_1% R144 0 24.9_040 2_1% R1441 130_040 2_1% R1441 130_040 2_1%
XDP_DBR ESET#
2
5/26 add test point
2009/08/14 #4253 02 CP_S3PowerReduction WhitePaper_Rev1 .0
+1.05VS_ VTT_CPU
PM_EXTT S#0_1 (10,11)
1 2 1 2 1 2
XDP_DBR ESET# (15)
2009/08/14 remove DP REF SSCLK
CLK_CPU _DP_R CLK_CPU _DP#_R
XDP_PRD Y# XDP_TMS XDP_TDI_R XDP_PRE Q# XDP_TCL K
XDP_TRS T#
XDP_TDO _M
XDP_TDI_M
R1425 0_0402_ 5% R1425 0_0402_ 5% R1426 0_0402_ 5% R1426 0_0402_ 5%
1 2 1 2
R1428 51_0402 _5%@R1428 51_0402 _5%@
1 2
R1430 51_0402 _5%@R1430 51_0402 _5%@
1 2
R1431 51_0402 _5%@R1431 51_0402 _5%@
1 2
R1432 51_0402 _5%@R1432 51_0402 _5%@
1 2
R1434 51_0402 _5%@R1434 51_0402 _5%@
1 2
R1438 51_0402 _5% R1438 51_04 02_5%
1 2
12
R1444
R1444 0_0402_ 5%
0_0402_ 5%
1
+1.05VS_ VTT_CPU
B B
H_VTTPW RGD(31,45)
#425302 CP_S3PowerReduction WhitePaper_Rev0.7
H_VTTPW RGD
MC74VHC 1G08DFT2G_SC 70-5
MC74VHC 1G08DFT2G_SC 70-5
6/2 remove R1456
A A
PM_DRAM _PWRGD_R
5
U103
U103
2
1
12
R1457
R1457
1.5K_040 2_1%
1.5K_040 2_1%
12
R1459
R1459
750_040 2_1%
750_040 2_1%
+3VALW
5
P
B
Y
A
G
3
+3VALW
5
P
B
4
Y
A
G
MC74VHC 1G08DFT2G_SC 70-5
MC74VHC 1G08DFT2G_SC 70-5
3
2009/04/23 Intel CRB 1.55 Update Change R393 to 1.1K_1%, R394 to 3.01K_1%
4
1 2
R1454 2K_0402 _1%
R1454 2K_0402 _1%
U104
U104
H_VTTPW RGD
2
1
H_VTTPW RGD_R
12
R1455
R1455 1K_0402 _1%
1K_0402 _1%
4
+1.05VS_ VTT_CPU
R1451 49.9_ 0402_1% R1451 49.9_ 0402_1% R1452 68_0 402_5% R1452 68_0 402_5% R1453 68_0 402_5%@R145 3 6 8_0402_5%@ R1492 51_0 402_5%R1492 51_0 402_5%
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
12 12 12
H_CATER R# H_PROCH OT# H_CPURS T#
XDP_TDO _R
Compal Secret Data
Compal Secret Data
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR (2/6) CLK,JTAG
PROCESSOR (2/6) CLK,JTAG
PROCESSOR (2/6) CLK,JTAG
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
B
B
B
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
5 51Monday, November 22, 2 010
5 51Monday, November 22, 2 010
5 51Monday, November 22, 2 010
1
1.0
1.0
1.0
5
JCPU1C
C10
D10
H10
G10
AH5 AF5 AK6 AK7 AF6 AG5
AJ10
AL10
AK12
AK8
AK11
AN8 AM10 AR11
AL11
AM9
AN9
AT11 AP12 AM12 AN12 AM13
AT14
AT12
AL13 AR14 AP14
AC3 AB2
AE1 AB3 AE9
A10
B10
E10
F10
J10
AJ7 AJ6
AJ9
AL7
AL8
G8
G7
M6 M8
C7 A7
A8 D8
E6 F7 E9 B7 E7 C6
K7
J8
J7
L7
L9
L6 K8 N8 P9
U7
JCPU1C
SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]
SA_BS[0] SA_BS[1] SA_BS[2]
SA_CAS# SA_RAS# SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
DDR_A_D [0..63](10) DDR_A_D M[0..7](10)
DDR_A_D QS#[0..7](10)
DDR_A_D QS[0..7](10)
DDR_A_M A[0..15](10)
DDR_A_D 0 DDR_A_D 1
D D
C C
B B
DDR_A_B S0(10) DDR_A_B S1(10) DDR_A_B S2(10)
DDR_A_C AS#(10) DDR_A_R AS#(10)
DDR_A_W E#(10)
DDR_A_D 2 DDR_A_D 3 DDR_A_D 4 DDR_A_D 5 DDR_A_D 6 DDR_A_D 7 DDR_A_D 8 DDR_A_D 9 DDR_A_D 10 DDR_A_D 11 DDR_A_D 12 DDR_A_D 13 DDR_A_D 14 DDR_A_D 15 DDR_A_D 16 DDR_A_D 17 DDR_A_D 18 DDR_A_D 19 DDR_A_D 20 DDR_A_D 21 DDR_A_D 22 DDR_A_D 23 DDR_A_D 24 DDR_A_D 25 DDR_A_D 26 DDR_A_D 27 DDR_A_D 28 DDR_A_D 29 DDR_A_D 30 DDR_A_D 31 DDR_A_D 32 DDR_A_D 33 DDR_A_D 34 DDR_A_D 35 DDR_A_D 36 DDR_A_D 37 DDR_A_D 38 DDR_A_D 39 DDR_A_D 40 DDR_A_D 41 DDR_A_D 42 DDR_A_D 43 DDR_A_D 44 DDR_A_D 45 DDR_A_D 46 DDR_A_D 47 DDR_A_D 48 DDR_A_D 49 DDR_A_D 50 DDR_A_D 51 DDR_A_D 52 DDR_A_D 53 DDR_A_D 54 DDR_A_D 55 DDR_A_D 56 DDR_A_D 57 DDR_A_D 58 DDR_A_D 59 DDR_A_D 60 DDR_A_D 61 DDR_A_D 62 DDR_A_D 63
DDR_A_B S0 DDR_A_B S1 DDR_A_B S2
DDR_A_C AS# DDR_A_R AS# DDR_A_W E#
SA_CK[0] SA_CK#[0] SA_CKE[0]
SA_CK[1] SA_CK#[1] SA_CKE[1]
SA_CS#[0] SA_CS#[1]
SA_ODT[0] SA_ODT[1]
SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]
SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]
SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
4
AA6 AA7 P7
Y6 Y5 P6
AE2 AE8
AD8 AF9
B9 D7 H7 M7 AG6 AM7 AN10 AN13
C9 F8 J9 N9 AH7 AK9 AP11 AT13
C8 F9 H9 M9 AH8 AK10 AN11 AR13
Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9
DDR_A_D M0 DDR_A_D M1 DDR_A_D M2 DDR_A_D M3 DDR_A_D M4 DDR_A_D M5 DDR_A_D M6 DDR_A_D M7
DDR_A_D QS#0 DDR_A_D QS#1 DDR_A_D QS#2 DDR_A_D QS#3 DDR_A_D QS#4 DDR_A_D QS#5 DDR_A_D QS#6 DDR_A_D QS#7
DDR_A_D QS0 DDR_A_D QS1 DDR_A_D QS2 DDR_A_D QS3 DDR_A_D QS4 DDR_A_D QS5 DDR_A_D QS6 DDR_A_D QS7
DDR_A_M A0 DDR_A_M A1 DDR_A_M A2 DDR_A_M A3 DDR_A_M A4 DDR_A_M A5 DDR_A_M A6 DDR_A_M A7 DDR_A_M A8 DDR_A_M A9 DDR_A_M A10 DDR_A_M A11 DDR_A_M A12 DDR_A_M A13 DDR_A_M A14 DDR_A_M A15
DDR_A_C LK0 (10) DDR_A_C LK0# (10) DDR_A_C KE0 (10)
DDR_A_C LK1 (10) DDR_A_C LK1# (10) DDR_A_C KE1 (10)
DDR_A_C S0# (10) DDR_A_C S1# (10)
DDR_A_O DT0 (10 ) DDR_A_O DT1 (10 )
3
JCPU1D
AF3
AG1
AK1 AG4 AG3
AH4
AK3
AK4 AM6
AN2
AK5
AK2 AM4 AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10 AT10
AB1
AC5
AC6
JCPU1D
B5 A5
C3
B3 E4 A6
A4 C4 D1 D2
F2
F1 C2
F5
F3 G4 H6 G2
J6
J3 G1 G5
J2
J1
J5
K2 L3
M1
K5
K4 M4 N5
AJ3
AJ4
W5
R7
Y7
DDR_B_D [0..63](11)
DDR_B_D M[0..7](11)
DDR_B_D QS#[0..7](11)
DDR_B_D QS[0..7](11) DDR_B_M A[0..15](11)
DDR_B_D 0 DDR_B_D 1 DDR_B_D 2 DDR_B_D 3 DDR_B_D 4 DDR_B_D 5 DDR_B_D 6 DDR_B_D 7 DDR_B_D 8 DDR_B_D 9 DDR_B_D 10 DDR_B_D 11 DDR_B_D 12 DDR_B_D 13 DDR_B_D 14 DDR_B_D 15 DDR_B_D 16 DDR_B_D 17 DDR_B_D 18 DDR_B_D 19 DDR_B_D 20 DDR_B_D 21 DDR_B_D 22 DDR_B_D 23 DDR_B_D 24 DDR_B_D 25 DDR_B_D 26 DDR_B_D 27 DDR_B_D 28 DDR_B_D 29 DDR_B_D 30 DDR_B_D 31 DDR_B_D 32 DDR_B_D 33 DDR_B_D 34 DDR_B_D 35 DDR_B_D 36 DDR_B_D 37 DDR_B_D 38 DDR_B_D 39 DDR_B_D 40 DDR_B_D 41 DDR_B_D 42 DDR_B_D 43 DDR_B_D 44 DDR_B_D 45 DDR_B_D 46 DDR_B_D 47 DDR_B_D 48 DDR_B_D 49 DDR_B_D 50 DDR_B_D 51 DDR_B_D 52 DDR_B_D 53 DDR_B_D 54 DDR_B_D 55 DDR_B_D 56 DDR_B_D 57 DDR_B_D 58 DDR_B_D 59 DDR_B_D 60 DDR_B_D 61 DDR_B_D 62 DDR_B_D 63
DDR_B_B S0(11) DDR_B_B S1(11) DDR_B_B S2(11)
DDR_B_C AS#(11) DDR_B_R AS#(11)
DDR_B_W E#(11)
DDR_B_BS0 DDR_B_B S1 DDR_B_B S2
DDR_B_C AS# DDR_B_R AS# DDR_B_W E#
SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]
SB_BS[0] SB_BS[1] SB_BS[2]
SB_CAS# SB_RAS# SB_WE#
2
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0] SB_CS#[1]
SB_ODT[0] SB_ODT[1]
SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]
DDR SYSTEM MEMORY - B
DDR SYSTEM MEMORY - B
SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]
SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
W8 W9 M3
V7 V6 M2
AB8 AD6
AC7 AD1
D4 E1 H3 K1 AH1 AL2 AR4 AT8
D5 F4 J4 L4 AH2 AL4 AR5 AR8
C5 E3 H4 M5 AG2 AL5 AP5 AR7
U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1
DDR_B_D M0 DDR_B_D M1 DDR_B_D M2 DDR_B_D M3 DDR_B_D M4 DDR_B_D M5 DDR_B_D M6 DDR_B_D M7
DDR_B_D QS#0 DDR_B_D QS#1 DDR_B_D QS#2 DDR_B_D QS#3 DDR_B_D QS#4 DDR_B_D QS#5 DDR_B_D QS#6 DDR_B_D QS#7
DDR_B_D QS0 DDR_B_D QS1 DDR_B_D QS2 DDR_B_D QS3 DDR_B_D QS4 DDR_B_D QS5 DDR_B_D QS6 DDR_B_D QS7
DDR_B_M A0 DDR_B_M A1 DDR_B_M A2 DDR_B_M A3 DDR_B_M A4 DDR_B_M A5 DDR_B_M A6 DDR_B_M A7 DDR_B_M A8 DDR_B_M A9 DDR_B_M A10 DDR_B_M A11 DDR_B_M A12 DDR_B_M A13 DDR_B_M A14 DDR_B_M A15
1
DDR_B_C LK0 (11) DDR_B_C LK0# (11) DDR_B_C KE0 (11)
DDR_B_C LK1 (11) DDR_B_C LK1# (11) DDR_B_C KE1 (11)
DDR_B_C S0# (11) DDR_B_C S1# (11)
DDR_B_O DT0 (11 ) DDR_B_O DT1 (11 )
IC,AUB_CFD _rPGA,R1P0
IC,AUB_CFD _rPGA,R1P0
CONN@
CONN@
A A
Security Class ification
Security Class ification
Security Class ification
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/11/ 23 2010/11/ 23
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
IC,AUB_CFD _rPGA,R1P0
IC,AUB_CFD _rPGA,R1P0
CONN@
CONN@
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR (3/6) DDRIII
PROCESSOR (3/6) DDRIII
PROCESSOR (3/6) DDRIII
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
B
B
B
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
1
of
6 51Monday, November 22, 2 010
6 51Monday, November 22, 2 010
6 51Monday, November 22, 2 010
1.0
1.0
1.0
5
JCPU1F
JCPU1F
W15 MOW
+CPU_CORE
W
48A Continuous 18A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
D D
C C
B B
A A
5
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
CONN@
CONN@
1.1V RAIL POWER
1.1V RAIL POWER
CPU CORE SUPPLY
CPU CORE SUPPLY
POWER
POWER
CPU VIDS
CPU VIDS
SENSE LINES
SENSE LINES
Peak 21A
VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8
VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32
VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44
PSI#
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
PROC_DPRSLPVR
VTT_SELECT
ISENSE
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
4
AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11
AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15
AN33
AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34
H_VTTVID1
G15
H_VTTVID1 = low, 1.1V
H_VTTVID1 = high, 1.05V
AN35
VCCSENSE_R
AJ34
VSSSENSE_R
AJ35
B15
VSS_SENSE_VTT
A15
4
10U_0805_6.3V6M
1
C1344
C1344
2
10U_0805_6.3V6M
10U_0805_6.3V6M
+1.05VS_VTT_CPU
+
+
1
2
1 2
10U_0805_6.3V6M
1
C1345
C1345
2
1
+
+
C1360
C1360 330U_D2_2V_Y
330U_D2_2V_Y
2
+1.05VS_VTT_CPU
VTT_SENSE (45)
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1343
C1343
2
10U_0805_6.3V6M
10U_0805_6.3V6M
C1359,C1360 change to ESR9 6/29
330U_D2_2V_Y
330U_D2_2V_Y
1
C1359
C1359
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C1375
C1375
C1374
C1374
2
22U_0805_6.3V6M
22U_0805_6.3V6M
T49
@ T49
@
PAD
PAD
IMVP_IMON (47)
R1479 0_0402_5% R1479 0_0402_5%
1 2
R1480 0_0402_5% R1480 0_0402_5%
1 2
R1482 0_0402_5%R1482 0_0402_5%
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
C1346
C1346
C1347
C1347
<BOM Structure>
<BOM Structure>
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
H_PSI# (47)
CPU_VID0 (47) CPU_VID1 (47) CPU_VID2 (47) CPU_VID3 (47) CPU_VID4 (47) CPU_VID5 (47) CPU_VID6 (47) H_DPRSLPVR (47)
R1478 100_0402_1%
R1478 100_0402_1%
VCCSENSE VSSSENSE
R1481 100_0402_1%
R1481 100_0402_1%
VTT Rail
Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1.05VS_VTT_CPU
1
1
C1348
C1348
C1349
C1349
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
CSC (Current Sense Configuration) 8/25
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
H_DPRSLPVR
H_PSI#
1 2
1 2
3
R1460 1K_0402 _1% R1460 1K_0402 _1%
1 2
R1461 1K_0402 _1%@R1461 1K_0402_1%@
1 2
R1462 1K_0402 _1% R1462 1K_0402 _1%
1 2
R1463 1K_0402 _1%@R1463 1K_0402_1%@
1 2
R1464 1K_0402 _1% R1464 1K_0402 _1%
1 2
R1465 1K_0402 _1%@R1465 1K_0402_1%@
1 2
R1466 1K_0402 _1%@R1466 1K_0402_1%@
1 2
R1467 1K_0402 _1% R1467 1K_0402 _1%
1 2
R1468 1K_0402 _1%@R1468 1K_0402_1%@
1 2
R1469 1K_0402 _1% R1469 1K_0402 _1%
1 2
R1470 1K_0402 _1% R1470 1K_0402 _1%
1 2
R1471 1K_0402 _1%@R1471 1K_0402_1%@
1 2
R1472 1K_0402 _1%@R1472 1K_0402_1%@
1 2
R1473 1K_0402 _1% R1473 1K_0402 _1%
1 2
R1474 1K_0402 _1% R1474 1K_0402 _1%
1 2
R1475 1K_0402 _1%@R1475 1K_0402_1%@
1 2
R1476 1K_0402 _1%@R1476 1K_0402_1%@
1 2
R1477 1K_0402 _1% R1477 1K_0402 _1%
1 2
+CPU_CORE
VCCSENSE (47)
VSSSENSE (47)
Compal Secret Data
Compal Secret Data
2009/11/23 2010/11/23
2009/11/23 2010/11/23
2009/11/23 2010/11/23
Compal Secret Data
+CPU_CORE
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1350
C1350
2
+1.05VS_VTT_CPU
Deciphered Date
Deciphered Date
Deciphered Date
1
C1351
C1351
2
10U_0805_6.3V6M
10U_0805_6.3V6M
330U_D2_2V_Y
330U_D2_2V_Y
2
+CPU-CORE Decoupling SPCAP,Polymer
MLCC 0805 X5R
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1352
C1352
2
(Place these capacitors between inductor and socket on Bottom)
+CPU_CORE
1
C1361
C1361
2
10U_0805_6.3V6M
10U_0805_6.3V6M
+CPU_CORE
1
C1368
C1368
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+CPU_CORE
1
C1376
C1376
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+CPU_CORE
1
+
+
C1382
C1382
@
@
2
2
C,uF
4X470uF 4m ohm/4
16X22uF
ESR, mohm
3m ohm/12
Stuffing Option
2X470uF
16X10uF 3m ohm/16
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1353
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1362
2
(Place these capacitors under CPU socket, top layer)
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C1369
C1369
2
(Place these capacitors on CPU cavity, Bottom Layer)
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C1377
C1377
2
(Place these capacitors on CPU cavity, Bottom Layer)
C1353
C1354
C1362
C1363
10U_0805_6.3V6M
10U_0805_6.3V6M
C1370
C1370
22U_0805_6.3V6M
22U_0805_6.3V6M
C1378
C1378
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C1354
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1363
2
1
C1371
2
1
2
10U_0805_6.3V6M
1
C1355
C1355
2
1
C1364
C1364
2
10U_0805_6.3V6M
10U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C1371
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C1379
C1379
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C1356
2
1
C1365
2
1
C1372
C1372
2
1
C1380
C1380
2
4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)
1
+
+
C1383
C1383
2
330U_D2_2V_Y
330U_D2_2V_Y
TOP side (under inductor)
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
+
+
C1384
C1384
2
330U_D2_2V_Y
330U_D2_2V_Y
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PROCESSOR (4/6) PWR,Bypass
PROCESSOR (4/6) PWR,Bypass
PROCESSOR (4/6) PWR,Bypass
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
330U_D2_2V_Y
330U_D2_2V_Y
1
C1356
C1357
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
C1365
C1366
22U_0805_6.3V6M
22U_0805_6.3V6M
C1373
C1373
22U_0805_6.3V6M
22U_0805_6.3V6M
C1381
C1381
1
+
+
C1385
C1385
2
1
1
C1357
2
1
C1366
2
1
2
1
2
330U_D2_2V_Y
330U_D2_2V_Y
7 51Monday, November 22, 2010
7 51Monday, November 22, 2010
7 51Monday, November 22, 2010
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1358
C1358
2
1
C1367
C1367
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
+
+
C1386
C1386
2
1.0
1.0
1.0
5
4
3
2
1
+VGFX_C ORE
10U_080 5_6.3V6M
22U_080 5_6.3V6M
22U_080 5_6.3V6M
10U_080 5_6.3V6M
10U_080 5_6.3V6M
D D
C C
B B
C1470
C1470
1
2
C1388
C1388
330U_D2 _2V_Y
330U_D2 _2V_Y
1
1
C1389
C1389
+
+
2
2
22U_080 5_6.3V6M
22U_080 5_6.3V6M
C1400
C1400
22U_080 5_6.3V6M
22U_080 5_6.3V6M
C1404
C1404
22U_080 5_6.3V6M
22U_080 5_6.3V6M
C1390
C1390
+1.05VS_ VTT_CPU
1
2
+1.05VS_ VTT_CPU
1
2
10U_080 5_6.3V6M
1
1
C1391
C1391
C1387
C1387
2
2
10U_080 5_6.3V6M
10U_080 5_6.3V6M
1
C1401
C1401
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
C1405
C1405
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
2
JCPU1G
JCPU1G
AT21
VAXG1
AT19
VAXG2
AT18
VAXG3
AT16
VAXG4
AR21
VAXG5
AR19
VAXG6
AR18
VAXG7
AR16
VAXG8
AP21
VAXG9
AP19
VAXG10
AP18
VAXG11
AP16
VAXG12
AN21
VAXG13
AN19
VAXG14
AN18
VAXG15
AN16
VAXG16
AM21
VAXG17
AM19
VAXG18
AM18
VAXG19
AM16
VAXG20
AL21
VAXG21
AL19
VAXG22
AL18
VAXG23
AL16
VAXG24
AK21
VAXG25
AK19
VAXG26
AK18
VAXG27
AK16
VAXG28
AJ21
VAXG29
AJ19
VAXG30
AJ18
VAXG31
AJ16
VAXG32
AH21
VAXG33
AH19
VAXG34
AH18
VAXG35
AH16
VAXG36
J24
VTT1_45
J23
VTT1_46
H25
VTT1_47
K26
VTT1_48
J27
VTT1_49
J26
VTT1_50
J25
VTT1_51
H27
VTT1_52
G28
VTT1_53
G27
VTT1_54
G26
VTT1_55
F26
VTT1_56
E26
VTT1_57
E25
VTT1_58
IC,AUB_CFD _rPGA,R1P0
IC,AUB_CFD _rPGA,R1P0
CONN@
CONN@
15A
GRAPHICS
GRAPHICS
FDI PEG & DMI
FDI PEG & DMI
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
GRAPHICS VIDs
GRAPHICS VIDs
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8
VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
VTT0_59 VTT0_60 VTT0_61 VTT0_62
VTT1_63 VTT1_64 VTT1_65
1.1V1.8V
1.1V1.8V
VTT1_66 VTT1_67 VTT1_68
VCCPLL1 VCCPLL2 VCCPLL3
POWER
POWER
3A
0.6A
AR22 AT22
AM22 AP22 AN22 AP23 AM23 AP24 AN24
AR25 AT25 AM24
AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1
P10 N10 L10 K10
J22 J20 J18 H21 H20 H19
L26 L27 M26
GFXVR_E N GFXVR_D PRSLPVR
C1392
C1392
1U_0402 _6.3V4Z
1U_0402 _6.3V4Z
+1.05VS_ VTT_CPU
C140 3
+1.8VS_V CCSFR
C1406
C1406
1U_0402 _6.3V4Z
1U_0402 _6.3V4Z
VCC_AXG _SENSE (46) VSS_AXG _SENSE (46)
GFXVR_V ID_0 (46) GFXVR_V ID_1 (46) GFXVR_V ID_2 (46) GFXVR_V ID_3 (46) GFXVR_V ID_4 (46) GFXVR_V ID_5 (46) GFXVR_V ID_6 (46)
R1484 1K_0402 _5%@R1484 1K_0402 _5%@
1 2
1U_0402 _6.3V4Z
1U_0402 _6.3V4Z
1
1
C1393
C1393
2
2
+1.05VS_ VTT_CPU
1
2
1
C1403
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
1
C1407
C1407
2
2
1U_0402 _6.3V4Z
1U_0402 _6.3V4Z
GFXVR_D PRSLPVR (46)
1U_0402 _6.3V4Z
1U_0402 _6.3V4Z
1
C1395
C1395
C1394
C1394
2
1U_0402 _6.3V4Z
1U_0402 _6.3V4Z
C1402
C1402
10U_080 5_6.3V6M
10U_080 5_6.3V6M
2.2U_060 3_6.3V4Z
2.2U_060 3_6.3V4Z
1
C1408
C1408
2
4.7U_080 5_10V4Z
4.7U_080 5_10V4Z
1
1
C1396
C1396
2
2
1U_0402 _6.3V4Z
1U_0402 _6.3V4Z
40mil
1
C1409
C1409
2
GFXVR_E N (4 6)
GFXVR_IMO N (46)
22U_080 5_6.3V6M
22U_080 5_6.3V6M
1
C1398
C1398
C1397
C1397
2
22U_080 5_6.3V6M
22U_080 5_6.3V6M
1 2
1
C1410
C1410
2
22U_080 5_6.3V6M
22U_080 5_6.3V6M
GFXVR_E N
1
2
R1485
R1485 0_0805_ 5%
0_0805_ 5%
1 2
R1483 470_040 2_5% R14 83 470_ 0402_5%
Reserved for +1.5V to +1.5V_1
+1.5VS
1
+
+
C1399
C1399 330U_D2 _2V_Y
330U_D2 _2V_Y
2
+1.8VS
A A
Security Class ification
Security Class ification
Security Class ification
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/11/ 23 2010/11/ 23
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR (5/6) PWR
PROCESSOR (5/6) PWR
PROCESSOR (5/6) PWR
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
8 51Monday, November 22, 2 010
8 51Monday, November 22, 2 010
8 51Monday, November 22, 2 010
1
1.0
1.0
1.0
5
JCPU1H
JCPU1H
AT20
VSS1
AT17
VSS2
AR31
VSS3
AR28
VSS4
AR26
VSS5
AR24
VSS6
D D
C C
B B
AR23 AR20 AR17 AR15 AR12
AR9 AR6
AR3 AP20 AP17 AP13 AP10
AP7
AP4
AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11
AM8
AM5
AM2
AL34 AL31 AL23 AL20 AL17 AL12
AL9 AL6
AL3 AK29 AK27 AK25 AK20 AK17
AJ31 AJ23 AJ20 AJ17 AJ14 AJ11
AJ8
AJ5
AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13
AH9 AH6 AH3
AG10
AF8 AF4 AF2
AE35
VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80
4
VSS
VSS
VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160
AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30
3
JCPU1I
JCPU1I
K27
VSS161
K9
VSS162
K6
VSS163
K3
VSS164
J32
VSS165
J30
VSS166
J21
VSS167
J19
VSS168
H35
VSS169
H32
VSS170
H28
VSS171
H26
VSS172
H24
VSS173
H22
VSS174
H18
VSS175
H15
VSS176
H13
VSS177
H11
VSS178
H8
VSS179
H5
VSS180
H2
VSS181
G34
VSS182
G31
VSS183
G20
VSS184
G9
VSS185
G6
VSS186
G3
VSS187
F30
VSS188
F27
VSS189
F25
VSS190
F22
VSS191
F19
VSS192
F16
VSS193
E35
VSS194
E32
VSS195
E29
VSS196
E24
VSS197
E21
VSS198
E18
VSS199
E13
VSS200
E11
VSS201
E8
VSS202
E5
VSS203
E2
VSS204
D33
VSS205
D30
VSS206
D26
VSS207
D9
VSS208
D6
VSS209
D3
VSS210
C34
VSS211
C32
VSS212
C29
VSS213
C28
VSS214
C24
VSS215
C22
VSS216
C20
VSS217
C19
VSS218
C16
VSS219
B31
VSS220
B25
VSS221
B21
VSS222
B18
VSS223
B17
VSS224
B13
VSS225
B11
VSS226
B8
VSS227
B6
VSS228
B4
VSS229
A29
VSS230
A27
VSS231
A23
VSS232
A9
VSS233
2
VSS
VSS
NCTF
NCTF
VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7
AT35 AT1 AR34 B34 B2 B1 A35
H_NCTF1 H_NCTF2
H_NCTF6 H_NCTF7
1
@
@
PAD
PAD
T51
T51
@
@
PAD
PAD
T52
T52
@
@
PAD
PAD
T53
T53
@
@
PAD
PAD
T54
T54
IC,AUB_CFD _rPGA,R1P0
IC,AUB_CFD _rPGA,R1P0
CONN@
CONN@
A A
Security Class ification
Security Class ification
Security Class ification
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/11/ 23 2010/11/ 23
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
IC,AUB_CFD _rPGA,R1P0
IC,AUB_CFD _rPGA,R1P0
CONN@
CONN@
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR (6/6) VSS
PROCESSOR (6/6) VSS
PROCESSOR (6/6) VSS
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
9 51Tuesday, September 07, 2 010
9 51Tuesday, September 07, 2 010
9 51Tuesday, September 07, 2 010
1
1.0
1.0
1.0
5
DIMMA VREFDQ M1 Circuit
+1.5V
12
R1493
R1493
1K_0402_1%
1K_0402_1%
D D
C C
B B
10U_0805_6.3V6M
10U_0805_6.3V6M
12
DIMMA & DIMMB VREFCA circuit
+1.5V
12
R1495
R1495
1K_0402_1%
1K_0402_1%
12
Layout Note: Place near JDIMM1
+1.5V
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1438
C1438
C1439
C1439
2
Layout Note: Place near JDIMM1.203 & JDIMM1.204
+0.75VS
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C1451
C1451
C1452
C1452
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+DIMM_VREFDQA
20mil
R1494
R1494
1K_0402_1%
1K_0402_1%
+DIMM_VREFCA
20mil
R1496
R1496
1K_0402_1%
1K_0402_1%
Layout Note: Place these 4 Caps near Command and Control signals of DIMMA
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
1
C1441
C1441
C1440
C1440
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1453
C1453
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C1454
C1454
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
2
C1442
C1442
1
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1443
C1443
2
C1455
C1455
10U_0805_6.3V6M
10U_0805_6.3V6M
DDR_A_DQS#[0..7](6)
DDR_A_D[0..63](6)
DDR_A_DM[0..7](6)
DDR_A_DQS[0..7](6)
DDR_A_MA[0..15](6)
#425302 CP_S3PowerReduction WhitePaper_Rev1.0
SM_DRAMRST#(5)
RST_GATE(18)
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1444
C1444
1
C1445
C1445
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RST_GATE
1
C1446
C1446
2
R1497
R1497 0_0402_5%
0_0402_5%
@
@
1 2
S
S
G
G
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1447
C1447
2
+1.5V
12
D
D
13
Q107
Q107 BSS138LT1G_SOT23-3
BSS138LT1G_SOT23-3
<BOM Structure>
<BOM Structure>
C1435
C1435
1 2
0.047U_0402_16V7K
0.047U_0402_16V7K
1
+
+
C1448
C1448 330U_D2_2V_Y
330U_D2_2V_Y
2
4
R1498
R1498
1K_0402_1%
1K_0402_1%
DIMM_DRAMRST#
+DIMM_VREFDQA
DIMM_DRAMRST# (11)
C1434
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3
+1.5V +1.5V
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
DDR_A_D0
1
1
C1433
C1434
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C1433
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
2
DDR_A_CKE0(6)
DDR_A_BS2(6)
DDR_A_CLK0(6) DDR_A_CLK0#(6)
DDR_A_BS0(6)
DDR_A_WE#(6)
DDR_A_CAS#(6) DDR_A_ODT0 (6)
DDR_A_CS1#(6)
+3VS
C1449
C1449
1
2
DDR_A_D1
DDR_A_DM0
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_DM3
DDR_A_D26 DDR_A_D27
DDR_A_CKE0
DDR_A_BS2
DDR_A_MA12 DDR_A_MA9
DDR_A_MA8 DDR_A_MA5
DDR_A_MA3 DDR_A_MA1
DDR_A_CLK0 DDR_A_CLK0#
DDR_A_MA10 DDR_A_BS0
DDR_A_WE# DDR_A_CAS# DDR_A_ODT0
DDR_A_MA13 DDR_A_CS1#
DDR_A_D32 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_DM5
DDR_A_D42 DDR_A_D43
DDR_A_D48 DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_DM7
DDR_A_D58 DDR_A_D59
R1499 10K_0402_5% R1499 10K_0402_5%
1 2
1
C1450
C1450
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
12
R1500
R1500
10K_0402_5%
10K_0402_5%
VSS2
5
DQ0
7
DQ1 VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9 VSS925VSS10
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2 DQS247VSS17
49
VSS18
51
DQ18 DQ1953VSS19
55
VSS20
57
DQ24 DQ2559VSS21 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3 A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1 VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A626-U4RN-7F
FOX_AS0A626-U4RN-7F
CONN@
CONN@
VSS3
DQS0
VSS6
VSS8 DQ12 DQ13
DQ14 DQ15
DQ20 DQ21
DQ22 DQ23
DQ28 DQ29
DQS3
DQ30 DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
VTT2
2
DDR_A_D4
4
DQ4 DQ5
DQ6 DQ7
DM1
DM2
A15 A14
CK1
BA1
S0#
NC2
DM4
DM6
SDA SCL
G2
DDR_A_D5
6 8
DDR_A_DQS#0
10
DDR_A_DQS0
12 14
DDR_A_D6
16
DDR_A_D7
18 20
DDR_A_D12
22
DDR_A_D13
24 26
DDR_A_DM1
28
DIMM_DRAMRST#
30 32
DDR_A_D14
34
DDR_A_D15
36 38
DDR_A_D20
40
DDR_A_D21
42 44
DDR_A_DM2
46 48
DDR_A_D22
50
DDR_A_D23
52 54
DDR_A_D28
56
DDR_A_D29
58 60
DDR_A_DQS#3
62
DDR_A_DQS3
64 66
DDR_A_D30
68
DDR_A_D31
70 72
DDR_A_CKE1
74 76
DDR_A_MA15
78
DDR_A_MA14
80 82
DDR_A_MA11
84
DDR_A_MA7
86
A7
88
DDR_A_MA6
90
A6 A4
A2 A0
92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206
DDR_A_MA4
DDR_A_MA2 DDR_A_MA0
DDR_A_CLK1 DDR_A_CLK1#
DDR_A_BS1 DDR_A_RAS#
DDR_A_CS0#
DDR_A_ODT1
20mil
DDR_VREF_CA_DIMMA
DDR_A_D36 DDR_A_D37
DDR_A_DM4
DDR_A_D38 DDR_A_D39
DDR_A_D44DDR_A_D44 DDR_A_D45
DDR_A_DQS#5 DDR_A_DQS5
DDR_A_D46 DDR_A_D47
DDR_A_D52 DDR_A_D53
DDR_A_DM6
DDR_A_D54 DDR_A_D55
DDR_A_D60 DDR_A_D61
DDR_A_DQS#7 DDR_A_DQS7
DDR_A_D62 DDR_A_D63
PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK
2
+0.75VS
DDR_A_CKE1 (6)
DDR_A_CLK1 (6) DDR_A_CLK1# (6)
DDR_A_BS1 (6) DDR_A_RAS# (6)
DDR_A_CS0# (6)
DDR_A_ODT1 (6)
1
C1436
C1436
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
PM_EXTTS#0_1 (5,11)
D_CK_SDATA (11,12,14,28,38) D_CK_SCLK (11,12,14,28,38)
2
DDR3 SO-DIMM A
H=8mm
+DIMM_VREFCA
1
C1437
C1437
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
3
2009/11/23 2010/11/23
2009/11/23 2010/11/23
2009/11/23 2010/11/23
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet of
Date: Sheet of
2
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
10 51Monday, November 22, 2010
10 51Monday, November 22, 2010
10 51Monday, November 22, 2010
1
1.0
1.0
1.0
of
5
DDR_B_DQS#[0..7](6)
DDR_B_D[0..63](6)
DDR_B_DM[0..7](6)
DDR_B_DQS[0..7](6)
DDR_B_MA[0..15](6)
D D
DIMMB VREFDQ M1 Circuit
+1.5V
12
R1487
R1487
1K_0402_1%
1K_0402_1%
12
C C
B B
A A
R1489
R1489
1K_0402_1%
1K_0402_1%
10U_0805_6.3V6M
10U_0805_6.3V6M
+DIMM_VREFDQB
20mil
Layout Note: Place near JDIMM2
+1.5V
10U_0805_6.3V6M
10U_0805_6.3V6M
1
2
1
C1427
C1427
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C1415
C1415
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C1428
C1428
2
C1416
C1416
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1429
C1429
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C1414
C1414
C1413
C1413
2
10U_0805_6.3V6M
10U_0805_6.3V6M
Layout Note: Place near JDIMM2.203 & JDIMM2.204
+0.75VS
C1426
C1426
1U_0402_6.3V4Z
1U_0402_6.3V4Z
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1417
C1417
2
1
2
1K_0402_1%
1K_0402_1%
1
2
DIMMB VREFDQ CA Circuit
+1.5V
12
R1488
R1488
12
R1486
R1486
1K_0402_1%
1K_0402_1%
Layout Note: Place these 4 Caps near Command and Control signals of DIMMB
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C1418
C1418
2
10U_0805_6.3V6M
10U_0805_6.3V6M
C1430
C1430
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C1419
C1419
2
2
+DIMM_VREFCB
20mil
1
C1420
C1420
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1421
C1421
2
1
C1422
C1422
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
+
+
C1423
C1423 330U_D2_2V_Y
330U_D2_2V_Y
@
@
2
+DIMM_VREFDQB
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
+3VS
C1431
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C1411
C1411
C1431
3
1
C1412
C1412
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_CKE0(6)
DDR_B_BS2(6)
DDR_B_CLK0(6) DDR_B_CLK0#(6)
DDR_B_BS0(6)
DDR_B_WE#(6)
DDR_B_CAS#(6)
DDR_B_CS1#(6)
1
1
C1432
C1432
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
DDR_B_D0
1
DDR_B_D1
DDR_B_DM0
2
DDR_B_D2 DDR_B_D3
DDR_B_D8 DDR_B_D9
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D10 DDR_B_D11
DDR_B_D16 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_DM3
DDR_B_D26 DDR_B_D27
DDR_B_CKE0
DDR_B_BS2
DDR_B_MA12 DDR_B_MA9
DDR_B_MA8 DDR_B_MA5
DDR_B_MA3 DDR_B_MA1
DDR_B_CLK0 DDR_B_CLK0#
DDR_B_MA10 DDR_B_BS0
DDR_B_WE# DDR_B_CAS#
DDR_B_MA13 DDR_B_CS1#
DDR_B_D32 DDR_B_D33
DDR_B_DQS#4 DDR_B_DQS4
DDR_B_D34 DDR_B_D35
DDR_B_D40 DDR_B_D41
DDR_B_DM5
DDR_B_D42 DDR_B_D43
DDR_B_D48 DDR_B_D49
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51
DDR_B_D56 DDR_B_D57
DDR_B_DM7
DDR_B_D58 DDR_B_D59
R1490 10K_0402_5% R1490 10K_0402_5%
1 2
1 2
R1491 10K_0402_5%
R1491 10K_0402_5%
+1.5V
JDIMM2
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1 VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9 VSS925VSS10 DQS#127DM1 DQS129RESET# VSS1131VSS12 DQ1033DQ14 DQ1135DQ15 VSS1337VSS14 DQ1639DQ20 DQ1741DQ21 VSS1543VSS16 DQS#245DM2 DQS247VSS17 VSS1849DQ22 DQ1851DQ23 DQ1953VSS19 VSS2055DQ28 DQ2457DQ29 DQ2559VSS21 VSS2261DQS#3
63
DM3 VSS2365VSS24 DQ2667DQ30 DQ2769DQ31 VSS2571VSS26
CKE073CKE1 VDD175VDD2
77
NC1
79
BA2 VDD381VDD4 A12/BC#83A11
85
A9 VDD587VDD6
89
A8
91
A5 VDD793VDD8
95
A3
97
A1 VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A626-U4SN-7F
FOX_AS0A626-U4SN-7F
CONN@
CONN@
VSS3
DQS0
VSS6
VSS8 DQ12 DQ13
DQS3
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
VTT2
2
+1.5V
2
DDR_B_D4
4
DQ4 DQ5
DQ6 DQ7
A15 A14
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
DDR_B_D5
6 8
DDR_B_DQS#0
10
DDR_B_DQS0
12 14
DDR_B_D6
16
DDR_B_D7
18 20
DDR_B_D12
22
DDR_B_D13
24 26
DDR_B_DM1
28
DIMM_DRAMRST#
30 32
DDR_B_D14
34
DDR_B_D15
36 38
DDR_B_D20
40
DDR_B_D21
42 44
DDR_B_DM2
46 48
DDR_B_D22
50
DDR_B_D23DDR_B_D18
52 54
DDR_B_D28
56
DDR_B_D29
58 60
DDR_B_DQS#3
62
DDR_B_DQS3
64 66
DDR_B_D30
68
DDR_B_D31
70 72
DDR_B_CKE1
74 76
DDR_B_MA15
78
DDR_B_MA14
80 82
DDR_B_MA11
84
DDR_B_MA7
86
A7
88
DDR_B_MA6
90
A6 A4
A2 A0
92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206
DDR_B_MA4
DDR_B_MA2 DDR_B_MA0
DDR_B_CLK1 DDR_B_CLK1#
DDR_B_BS1 DDR_B_RAS#
DDR_B_CS0# DDR_B_ODT0
DDR_B_ODT1
20mil
DDR_VREF_CA_DIMMB
DDR_B_D36 DDR_B_D37
DDR_B_DM4
DDR_B_D38 DDR_B_D39
DDR_B_D44 DDR_B_D45
DDR_B_DQS#5 DDR_B_DQS5
DDR_B_D46 DDR_B_D47
DDR_B_D52 DDR_B_D53
DDR_B_DM6
DDR_B_D54 DDR_B_D55
DDR_B_D60 DDR_B_D61
DDR_B_DQS#7 DDR_B_DQS7
DDR_B_D62 DDR_B_D63
PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK
+0.75VS
DIMM_DRAMRST# (10)
DDR_B_CKE1 (6)
DDR_B_CLK1 (6) DDR_B_CLK1# (6)
DDR_B_BS1 (6) DDR_B_RAS# (6)
DDR_B_CS0# (6) DDR_B_ODT0 (6)
DDR_B_ODT1 (6)
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
PM_EXTTS#0_1 (5,10)
D_CK_SDATA (10,12,14,28,38) D_CK_SCLK (10,12,14,28,38)
C1424
C1424
+DIMM_VREFCB
1
C1425
2
DDR3 SO-DIMM B
1
C1425
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
H=4mm
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2009/11/23 2010/11/23
2009/11/23 2010/11/23
2009/11/23 2010/11/23
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
1
11 51Monday, November 22, 2010
11 51Monday, November 22, 2010
11 51Monday, November 22, 2010
of
1.0
1.0
1.0
A
B
C
D
E
F
G
H
C684
C684
10U_080 5_10V4Z
10U_080 5_10V4Z
+CLK_1.5 VS
C671
C671
10U_080 5_10V4Z
10U_080 5_10V4Z
+CLK_3V S
1
2
1
2
+CLK_1.0 5VS
+1.05VS_ VTT
1 1
1 2
R1155 0_ 0603_5%
R1155 0_ 0603_5%
1
C668
C668 10U_080 5_10V4Z
10U_080 5_10V4Z
2
1
C676
C676
10U_080 5_10V4Z
10U_080 5_10V4Z
2
L44 Change 0 Ω 0603 2/1
40mil
1
C675
C675
2
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
1
C679
C679
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
2
1
C1333
C1333 22P_040 2_50V8J
22P_040 2_50V8J
2
@
@
4/9 RF add, need report
+3VS
1
C669
C669
10U_080 5_10V4Z
10U_080 5_10V4Z
2
+1.5VS
R1156 0_ 0603_5%
R1156 0_ 0603_5%
R1157 0_ 0603_5%
R1157 0_ 0603_5%
R1158 0_ 0603_5%
R1158 0_ 0603_5%
1
C670
C670 10U_080 5_10V4Z
10U_080 5_10V4Z
2
1 2
@
@
1 2
1 2
40mil
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
1
C680
C680
2
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
40mil
1
C682
C682
2
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
1
2
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
1
2
C689
C689
C678
C678
1
2
@
@
1
C683
C683
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
2
4/9 RF add, need report
C1334
C1334 22P_040 2_50V8J
22P_040 2_50V8J
1
C1335
C1335 22P_040 2_50V8J
22P_040 2_50V8J
2
@
@
4/9 RF add, need report
L45.L46.L48 Change 0 0603 2/1
2 2
CLK_BUF _DREF_96M
CLK_BUF _DREF_96M#(14)
CLK_BUF _DREF_96M#
Del R710.C708.C704.C705 3/4
Del R707.C713 3/3
CLK_BUF _PCIE_SATA(14) CLK_BUF _PCIE_SATA#(14)
CLK_BUF _CPU_DMI(14) CLK_BUF _CPU_DMI#(14)
3 3
+3VS
IDT 9LVS3199AKLFT NC
Silego Have Internal Pull-Up
R293 10K_ 0402_5% R293 10K_0 402_5%
1 2
IDT Have Internal Pull-Down
FOR Realtek
R712 10K_ 0402_5% R712 10K_0 402_5%
1 2
CLK_BUF _PCIE_SATA CLK_BUF _PCIE_SATA#
CLK_BUF _CPU_DMI CLK_BUF _CPU_DMI#
REF_0/CP U_SEL
+CLK_1.0 5VS
H_STP_C PU#
CPU_1PIN 30 CPU_0
(Default)
4 4
A
0 133MHz
1
100MHz 100MHz
B
133MHz
+CLK_3V S
+CLK_1.5 VS
H_STP_C PU#
Clock Generator
U43
U43
1
VDD_DOT
2
VSS_DOT
3
DOT_96
4
DOT_96#
5
VDD_27
6
27MHZ
7
27MHZ_SS
8
USB_48
9
VSS_27M
10
SATA
11
SATA#
12
VSS_SRC
13
SRC_1
14
SRC_1#
15
VDD_SRC_IO
16
CPU_STOP#
33
TGND
SLG8SP5 87VTR_QFN32_ 5X5
SLG8SP5 87VTR_QFN32_ 5X5
IDT SA00003HR00
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC
SCL SDA
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
+CLK_3V S
D_CK_SC LK D_CK_SD ATA REF_0/CP U_SEL
CLK_XTA L_IN CLK_XTA L_OUT
CK505_P WRGD
CLK_BUF _CPU_BCLK CLK_BUF _CPU_BCLK#
R713 33_0 402_5%R713 3 3_0402_5%
+CLK_1.0 5VS +CLK_1.5 VS
1 2
1
C952
C952
22P_040 2_50V8J
22P_040 2_50V8J
2
CLK_BUF _CPU_BCLK (14) CLK_BUF _CPU_BCLK# (14)
D_CK_SC LK (10,1 1,14,28,38)
D_CK_SD ATA (10,11,1 4,28,38) CLK_BUF _ICH_14M (14)CLK_BUF _DREF_96M(14)
Add C952 1/12
C952 from un-stuff to stuff 7/26
Low Power:
IDT: 9LVS3199AKLFT, SA00003HR00
Realtek: RTM890N-631-GRT, SA00003HQ00
Silego: SLG8LV597VTR , SA00003MF00
Move Q50 and Q51 to PCH Side 1/12
Security Class ification
Security Class ification
Security Class ification
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2009/11/ 23 2010/11/ 23
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
E
+3VS
R695
R695 10K_040 2_5%
10K_040 2_5%
1 2
CK505_P WRGD
13
D
D
2
G
G
Q47
Q47
S
S
2N7002K W_1N_SOT3 23-3
2N7002K W_1N_SOT3 23-3
hange Crystal CL from 16p to 20p 7/29 (sourcer suggestion)
c
14.318MH Z_20PF_7A143 00003
14.318MH Z_20PF_7A143 00003
F
Del R694 3/9
CLK_XTA L_IN
CLK_XTA L_OUT
CLK_ENA BLE# (47)
C686
C686
12
12
27P_040 2_50V8J
27P_040 2_50V8J
Y3
Y3
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
C685
C685
27P_040 2_50V8J
27P_040 2_50V8J
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Clock Generator (CK505)
Clock Generator (CK505)
Clock Generator (CK505)
Custom
Custom
Custom
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
G
0.1
0.1
0.1
12 51Monday, November 22, 20 10
12 51Monday, November 22, 20 10
12 51Monday, November 22, 20 10
H
5
+RTCVCC
close to RAM door
D D
+RTCVCC
close to RAM door
HDA_SYNC On Die PLL VR is supplied by
1.5V when sampled High,
1.8V when sampled Low.
+3VS
C C
If GPIO33 pull down, ME will not working. For factory update ME, pull down resistor pull under door.
ME_OVER RIDE(33)
GPIO33 has a weak internal pull-up NOTE: Asserting the GPIO33 low on th e rising edge of PWROK will also halt Intel Mana gement Engine after chipset b ringup and disable runtime Intel Management Engine f eatures. This is a debug mode and must not be
B B
asserted after manfa cturing/ debug.
A A
1 2
R558
R558 20K_040 2_1%
20K_040 2_1%
1 2
R696 10K_060 3_5%
10K_060 3_5%
C588
C588
1U_0603 _10V6K
1U_0603 _10V6K
1 2
1 2
R551
R551 20K_040 2_1%
20K_040 2_1%
1 2
R700 10K_060 3_5%
10K_060 3_5%
C584
C584
1U_0603 _10V6K
1U_0603 _10V6K
1 2
R623
R623 1K_0402 _5%
1K_0402 _5%
@
@
1 2
1 2
R225
R225 10K_040 2_5%
10K_040 2_5%
+3VALW
Have internal PD
100K_04 02_5%
100K_04 02_5%
Del R621.R619.R620.R618 3/16 Change R596 From 100 to 10K 3/16
Follow SAN RAFAEL
+3VS
PCH_RTC RST#
RC Delay 18~25mS
@R696
@
PCH_SRT CRST#
RC Delay 18~25mS
@R700
@
HDA for AUDIO
(HDA_SYNC Have internal Pull-Down)
(SPKR Have internal Pull-Down)
PCH_SPK R
SERIRQ
PCH_GPIO3 3#
13
D
D
Q28
Q28
2
G
G
2N7002K W_1N_SOT3 23-3
R552
R552
1 2
12
12
12
C130322P_040 2_50V8J C130322P_0402 _50V8J
R59851_0402 _5% R59851_0 402_5%
12
R6111K_0402 _5% @ R6111K_0402_5% @
2N7002K W_1N_SOT3 23-3
S
S
R21520 0_0402_5% @ R215200_ 0402_5% @
12
PCH_JTA G_TMS
R59710 0_0402_5% @ R597100_ 0402_5% @
12
R21720 0_0402_5% @ R217200_ 0402_5% @
12
PCH_JTA G_TDO
R59510 0_0402_5% @ R595100_ 0402_5% @
12
R216200_0402_5% @ R216200_0402 _5% @
12
R59610K_040 2_5% @ R59610K_04 02_5% @
R21820K_040 2_5% @ R21820K_040 2_5% @
12
PCH_JTA G_RST#
R59410K_040 2_5% @ R59410K_040 2_5% @
12
HDA_BITCL K_AUDIO
PCH_JTA G_TCK
Add C1303 3/9 Change R598 From 4.7K to 51 3/16
PCH_SPI_M OSI
32.768KH Z_12.5PF_Q13M C14610002
32.768KH Z_12.5PF_Q13M C14610002
modify to 330K
INTVRMEN - Integrated SUS 1.05V VRM Enable High - Enable Internal VRs
HDA_BITCL K_AUDIO(36)
HDA_SYNC_ AUDIO(36)
C1480 12 P_0402_50V8JC148 0 12P_0402_50 V8J
1 2
HDA_RST _AUDIO#(36)
reserve C1480 9/10
hange C1480 BOM structure form @ to POP 9/14
c
HDA_SDO UT_AUDIO(36)
2009/08/23 Debug Port DG1.7 P27.28
TDO,TDI,TMS Pull Up for Production Units unpop TDO,TDI,TMS resister
2
010/5/24 R596=>@
PCH_JTA G_TDI
enable iTPM: SPI_MOSI High
MOSI This signal has a weak internal pul l-down resistor. This signal must be sampled low.
5
4
C590
C590
18P_040 2_50V8J
18P_040 2_50V8J
12
X1
X1
3
OSC
NC
2
OSC
NC
C594
C594
12
18P_040 2_50V8J
18P_040 2_50V8J
+RTCVCC
R554 1M_0 402_5% R554 1 M_0402_5%
1 2
R559 330K _0402_1% R559 3 30K_0402_1%
1 2
1 2
R158 33_040 2_5%
R158 33_040 2_5%
1 2
R160 33_040 2_5%
R160 33_040 2_5%
PCH_SPK R(36)
1 2
R159 33_040 2_5%
R159 33_040 2_5%
HDA_SDIN0(36)
HDA_SDO ,This signal has a weak internal pul l-down resistor. Should not be Pull High
1 2
R162 33_040 2_5%
R162 33_040 2_5%
PIO33 can not pull down
G (manufacturing environments)
PCH_SPI_C LK_1
PCH_SPI_C S0#_1
PCH_SPI_M ISO_1 PCH_SPI_M ISO
R612 22_0 402_5%R612 2 2_0402_5%
1 2
R609 22_0 402_5%R609 2 2_0402_5%
1 2
PAD
PAD
T33
T33
R610 22_0 402_5%R610 2 2_0402_5%
1 2
R608 22_0 402_5%R608 2 2_0402_5%
1 2
4
1
PCH_RTC X1
10M_040 2_5%
10M_040 2_5%
PCH_RTC X2
@
@
12
R569
R569
PCH_RTC RST#
PCH_SRT CRST#
SM_INTRUD ER#
PCH_INTVR MEN
HDA_BITCL K_PCH
HDA_SYNC_ PCH
PCH_SPK R
HDA_RST _PCH#
HDA_SDO UT_PCH
PCH_GPIO3 3#
PCH_JTA G_TCK
PCH_JTA G_TMS
PCH_JTA G_TDI
PCH_JTA G_TDO
PCH_JTA G_RST#
PCH_SPI_C LK
PCH_SPI_C S1#
PCH_SPI_M OSIPCH_SPI_M OSI_1
3
Change Netname From LOCAL_DIM to LOCAL_DIM_R 3/18
U30A
U30A
REV1.0
B13 D13
C14
D17
A16
A14
A30
D29
C30
G30
F30
E32
F32
B29
H32
BA2
AV3
AY3
AY1
AV1
P1
J30
M3
K3
K1
J2
J4
REV1.0
RTCX1 RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
TRST#
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO
IBEXPEAK-M _FCBGA107
IBEXPEAK-M _FCBGA107
Change U37 BOM from SA000021A00(MXIC 4M) to SA000041P00(MXIC 4M)
PCH_SPI_C S0#_1
R634 3.3K_ 0402_5% R 634 3.3K_0402_5 %
+3VS
1 2
R643 3.3K_ 0402_5% R 643 3.3K_0402_5 %
1 2
change C1303 BOM structure form @ to POP 9/14
SPI_WP 1# SPI_HOLD1 #
SPI ROM Footprint 200mil
R608.R609.R610.R612 Change From 0 to 22Ω 1/12
Change Netname From PCH_SPI_CS0#_R to PCH_SPI_CS0# 1/13
Change R609.1 Netname From PCH_SPI_CS0# to PCH_SPI_CS0#_1 1/28
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
3
LOCAL_D IM_R
FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3
FWH4 / LFRAME#
LDRQ1# / GPIO23
RTCIHDA
RTCIHDA
LPC
LPC
SATA
SATA
SATAICOMPO
SATAICOMPI
SATA0GP / GPIO21
SATA1GP / GPIO19
SPI JTAG
SPI JTAG
U37
U37
1
CS#
3
WP#
7
HOLD#
4
GND
MX25L32 05DM2I-12G SOP 8P
MX25L32 05DM2I-12G SOP 8P
SA00004 1P00 <BOM S tructure>
SA00004 1P00 <BOM S tructure>
VCC
SCLK
8 6 5
SI
2
SO
D33 B33 C32 A32
C34
A34
LDRQ0#
F34
AB9
SERIRQ
AK7
SATA0RXN
AK6
SATA0RXP
AK11
SATA0TXN
AK9
SATA0TXP
AH6
SATA1RXN
AH5
SATA1RXP
AH9
SATA1TXN
AH8
SATA1TXP
AF11
SATA2RXN
AF9
SATA2RXP
AF7
SATA2TXN
AF6
SATA2TXP
AH3
SATA3RXN
AH1
SATA3RXP
AF3
SATA3TXN
AF1
SATA3TXP
AD9
SATA4RXN
AD8
SATA4RXP
AD6
SATA4TXN
AD5
SATA4TXP
AD3
SATA5RXN
AD1
SATA5RXP
AB3
SATA5TXN
AB1
SATA5TXP
AF16
AF15
T3
SATALED#
Y9
V1
change R625 BOM structure form @ to pop 9/3
+3VS
PCH_SPI_C LK_1 PCH_SPI_M OSI_1 PCH_SPI_M ISO_1
Samsung 256MX8 : SA000041E00
Hynix 256MX8 : SA000042700
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
+3VS
@
@
1 2
R150 20K_04 02_5%
R150 20K_04 02_5%
1 2
R742
R742 10K_040 2_5%
10K_040 2_5%
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LPC_FRA ME#
LOCAL_D IM_R
SERIRQ
SATA_DT X_C_PRX_N0 SATA_DT X_C_PRX_P0 SATA_PT X_DRX_N0 SATA_PT X_DRX_P0
LPC_AD0 (33) LPC_AD1 (33) LPC_AD2 (33) LPC_AD3 (33)
LPC_FRA ME# (33)
2/10 SATA2, SATA3 not support on HM55
4/1 add JBATT1
5/18 DEL D59, Add D35, D36
6/8 change diode to BAS40CW
SATA_CO MP
PCH_SAT ALED#PCH_SPI_C S0#
PROJECT _ID2
R168 37.4_ 0402_1% R168 37.4_0 402_1%
1 2
@
@
R600 10K_ 0402_5%
R600 10K_ 0402_5%
1 2
PCH_SAT ALED# (3 4)
GPIO21 RAM ID2 M/B version
PCH_SPI_C LK_1
H
L
2
10K_040 2_5%
10K_040 2_5%
@
@
C603 10P_0 402_50V8J
C603 10P_0 402_50V8J
Samsung
Hynix
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
SERIRQ (33)
SATA_DT X_C_PRX_N0 (27)
SATA_DT X_C_PRX_P0 (2 7) SATA_PT X_DRX_N0 (27) SATA_PT X_DRX_P0 (27)
SATA for HDD1
+NEW RTCBAT_R
Del SATA for ODD 3/3
1K_0402 _5%
1K_0402 _5%
+
2
3
D65
D65 BAS40CW _SOT323-3
BAS40CW _SOT323-3
1
R625
R625
1 2
JBATT1
JBATT1
2
SUYIN_060003 FA002G202NL
SUYIN_060003 FA002G202NL
+NEW RTCBAT_R
+1.05VS_ VTT
+RTCVCC
+3VS
R207 10K_ 0402_5%R207 10K_040 2_5%
R602 10K_ 0402_5%
R602 10K_ 0402_5%
12
12
R187
R187
@
@
10K_040 2_5%
10K_040 2_5%
change R602 BOM structure form pop to @ 9/3
-
1 2
1 2
@
@
ID3ID2ID1ID0
256MX8
128MX8
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
2 channel
1 channel
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DVT
PVT
1
13 51Monday, November 22, 20 10
13 51Monday, November 22, 20 10
13 51Monday, November 22, 20 10
R1384
R1384
1
+3VS
1 2
+CHGRTC
0.1
0.1
0.1
5
PCIE_DTX_ C_PRX_N1(29)
For PCIE LAN
For Wireless LAN
D D
Add for USB30 3/1
For USB3.0
For 3G/GPS MiniCard
PCIE_DTX_ C_PRX_P1(29) PCIE_PTX_ C_DRX_N1(29) PCIE_PTX_ C_DRX_P1(29)
PCIE_DTX_ C_PRX_N2(28) PCIE_DTX_ C_PRX_P2(28) PCIE_PTX_ C_DRX_N2(28) PCIE_PTX_ C_DRX_P2(28)
PCIE_DTX_ C_PRX_N3(31) PCIE_DTX_ C_PRX_P3(31) PCIE_PTX_ C_DRX_N3(31) PCIE_PTX_ C_DRX_P3(31)
PCIE_DTX_ C_PRX_N4(28) PCIE_DTX_ C_PRX_P4(28) PCIE_PTX_ C_DRX_N4(28) PCIE_PTX_ C_DRX_P4(28)
C577 .1U_0 402_16V7K C577 .1U_0 402_16V7K C578 .1U_0 402_16V7K C578 .1U_0 402_16V7K
C284 .1U_040 2_16V7K C284 .1U_040 2_16V7K C275 .1U_040 2_16V7K C275 .1U_040 2_16V7K
C1244 .1U _0402_16V7K C1 244 .1U_0402_1 6V7K C1245 .1U _0402_16V7K C1 245 .1U_0402_1 6V7K
C273 .1U_040 2_16V7K C273 .1U_040 2_16V7K C272 .1U_040 2_16V7K C272 .1U_040 2_16V7K
12 12
12 12
12 12
12 12
2/10 PCIE7, PCIE8 not support on HM55
C C
For PCIE LAN
LAN_CLK REQ#(29 )
For Wireless LAN
MINI1_CLKREQ #(28)
LAN_CLKREQ# Pull High to 3V_LAN at Lan Chip Side
CLK_PCIE_ MINI1#(28)
CLK_PCIE_ MINI1(28)
Del R647,R646,Q39 1/7
Del PCH-GPIO18 off page 1/8
Change Netname From MINI1_CLKREQ# to PCH_GPIO18 1/12
Del PCH_GPIO20 off page 1/8
Add R1244 for USB30 3/1
1 2 1 2
5
USB30_C LKREQ#(31)
+3VALW
12
MINI2_CLKREQ #
+3VS
Del Q39.R647 3/12
Move R208 to MINI1 Side 3/18
B B
Move R638 to MINI2 Side 3/18
MINI2_CLKREQ #(28)
MINI1_CLKREQ # PCH_GPIO2 0
A A
R227 10K_ 0402_5% R227 10K_0 402_5% R622 10K_ 0402_5% R622 10K_0 402_5%
R633
R633 10K_040 2_5%
10K_040 2_5%
PCH_SMB CLK PCH_SMB DATA
PCH_GPIO6 0
PCH_SML 1CLK PCH_SML 1DAT
PCH_GPIO7 4
PCH_GPIO4 4 PCH_GPIO5 6
CLK_PCIE_ USB30#(31) CLK_PCIE_ USB30(31)
CLK_PCIE_ MINI2#(28)
CLK_PCIE_ MINI2(28)
4
PCIE_DTX_ C_PRX_N1 PCIE_DTX_ C_PRX_P1
PCIE_PTX_ DRX_N1 PCIE_PTX_ DRX_P1
PCIE_DTX_ C_PRX_N2 PCIE_DTX_ C_PRX_P2
PCIE_PTX_ DRX_N2 PCIE_PTX_ DRX_P2
PCIE_DTX_ C_PRX_N3 PCIE_DTX_ C_PRX_P3
PCIE_PTX_ DRX_N3 PCIE_PTX_ DRX_P3
PCIE_DTX_ C_PRX_N4 PCIE_DTX_ C_PRX_P4
PCIE_PTX_ DRX_N4 PCIE_PTX_ DRX_P4
CLK_PCIE_ LAN#(29) CLK_PCIE_ LAN(2 9)
R173 4 .7K_0402_5%R173 4 .7K_0402_5% R582 4.7K_0402 _5%R 582 4.7K_040 2_5%
R169 10K_ 0402_5% R169 10K_0 402_5%
R191 3.3K_ 0402_5%R191 3.3K_ 0402_5% R183 3.3K_ 0402_5%R183 3.3K_ 0402_5%
R214 10K_ 0402_5% R214 10K_0 402_5%
R190 10K_ 0402_5% R190 10K_0 402_5% R211 10K_ 0402_5% R211 10K_0 402_5%
LAN_CLK REQ#
MINI2_CLKREQ #
PCH_GPIO4 4
PCH_GPIO5 6
1 2 1 2
1 2
1 2 1 2
1 2
1 2 1 2
4
MINI1_CLKREQ #
PAD
PAD
T3
T3
PAD
PAD
T4
T4
PCH_GPIO2 0
PAD
PAD
T21
T21
PAD
PAD
T18
T18
PAD
PAD
T20
T20
PAD
PAD
T22
T22
U30B
U30B
BG30
PERN1
BJ30
PERP1
BF29
PETN1
BH29
PETP1
AW30
PERN2
BA30
PERP2
BC30
PETN2
BD30
PETP2
AU30
PERN3
AT30
PERP3
AU32
PETN3
AV32
PETP3
BA32
PERN4
BB32
PERP4
BD32
PETN4
BE32
PETP4
BF33
PERN5
BH33
PERP5
BG32
PETN5
BJ32
PETP5
BA34
PERN6
AW34
PERP6
BC34
PETN6
BD34
PETP6
AT34
PERN7
AU34
PERP7
AU36
PETN7
AV36
PETP7
BG34
PERN8
BJ34
PERP8
BG36
PETN8
BJ36
PETP8
AK48
CLKOUT_PCIE0N
AK47
CLKOUT_PCIE0P
P9
PCIECLKRQ0# / GPIO73
AM43
CLKOUT_PCIE1N
AM45
CLKOUT_PCIE1P
U4
PCIECLKRQ1# / GPIO18
@
@
AM47
CLKOUT_PCIE2N
@
@
AM48
CLKOUT_PCIE2P
N4
PCIECLKRQ2# / GPIO20
AH42
CLKOUT_PCIE3N
AH41
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
AM51
CLKOUT_PCIE4N
AM53
CLKOUT_PCIE4P
M9
PCIECLKRQ4# / GPIO26
@
@
AJ50
CLKOUT_PCIE5N
@
@
AJ52
CLKOUT_PCIE5P
H6
PCIECLKRQ5# / GPIO44
@
@
AK53
CLKOUT_PEG_B_N
@
@
AK51
CLKOUT_PEG_B_P
P13
PEG_B_CLKRQ# / GPIO56
IBEXPEAK-M _FCBGA107
IBEXPEAK-M _FCBGA107
+3VALW
REV1.0
REV1.0
3
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1ALERT# / GPIO74
SMBus
SMBus
PCI-E*
PCI-E*
Link
Link
Controller
Controller
PEG_A_CLKRQ# / GPIO47
PEG
PEG
CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P
From CLK BUFFER
From CLK BUFFER
CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P
CLKIN_PCILOOPBACK
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
Clock Flex
Clock Flex
CLKOUTFLEX3 / GPIO67
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLKOUT_DMI_N CLKOUT_DMI_P
CLKIN_DMI_N CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
B9
H14
C8
J14
C6
G8
M14
E10
G12
T13
T11
T9
PEG_CLK REQ#_R
H1
AD43 AD45
AN4 AN2
@
@
AT1
@
@
AT3
AW24 BA24
AP3 AP1
F18 E18
AH13 AH12
P41
J42
AH51 AH53
AF38
T45
PROJECT _ID1
P43
PROJECT _ID0
T42
N50
EC_LID_OU T#
PCH_SMB CLK
PCH_SMB DATA
PCH_GPIO6 0
PCH_GPIO7 4
PCH_SML 1CLK
PCH_SML 1DAT
CLK_PEG _VGA# CLK_PEG _VGA
PAD
PAD
T28
T28
PAD
PAD
T32
T32
XTAL25_ IN XTAL25_ OUT
XCLK_RC OMP
T23
T23
PAD
PAD
T24
PAD
PAD
EC_LID_OU T# (3 3)
R149 90.9_ 0402_1% R149 90.9_0402 _1%
@
@
Project Structure ID
@T24
@
2
PCH_SMB CLK
PCH_SMB DATA
+3VALW
12
R592
R592
10K_040 2_5%
10K_040 2_5%
CLK_CPU _DMI# (5) CLK_CPU _DMI (5)
CLK_BUF _CPU_DMI# (1 2) CLK_BUF _CPU_DMI (12 )
CLK_BUF _CPU_BCLK# (12) CLK_BUF _CPU_BCLK (1 2)
CLK_BUF _DREF_96M# (12 ) CLK_BUF _DREF_96M (12)
CLK_BUF _PCIE_SATA# (12) CLK_BUF _PCIE_SATA (12)
CLK_PCI_F B (1 7)
1 2
R106 10K_ 0402_5%R106 10K_040 2_5%
1 2
R107 10K_ 0402_5%
R107
1 2
@
@
R109 10K_ 0402_5%R109 10K_040 2_5%
1 2
R108 10K_ 0402_5%
R108 10K_ 0402_5%
1 2
@
@
3/22 add test point
ID3ID2ID1RAM ID0
GPIO65GPIO66 GPIO21 GPIO19
Samsung
H
Hynix
L
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
256MX8
128MX8
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
3
2 channel
1 channel
Compal Secret Data
Compal Secret Data
Compal Secret Data
Reserved*
Reserved
Deciphered Date
Deciphered Date
Deciphered Date
2
1
+3VS
R715
2
G
G
1 3
D
S
D
S
Q51 2 N7002KW_ 1N_SOT323-3
Q51 2 N7002KW_ 1N_SOT323-3
Move Q50.Q51.R714.R715 From P12 to here 1/13
+3VS
2
G
G
1 3
D
S
D
S
Q50 2 N7002KW_ 1N_SOT323-3
Q50 2 N7002KW_ 1N_SOT323-3
R715
4.7K_040 2_5%
4.7K_040 2_5%
1 2
R714
R714
4.7K_040 2_5%
4.7K_040 2_5%
1 2
+3VS
D_CK_SC LK (10,1 1,12,28,38)
+3VS
D_CK_SD ATA (10,11,1 2,28,38)
Del R593.Q41.R668.R667.R666 1/9
Add R843 1/11
R592 Change BOM Structure From VGA@ to POP 1/12
Add Netname PEG_CLKREQ#_R 1/11
Change Netname From PEG_CLKREQ#_R to VGA_PWROK# 1/13
Change Back From PEG_CLKREQ#_R to VGA_PWROK# 1/14
6/9 MOW23 Request add 25MHz crystal supporting Integrated Graphics
CLK_BUF _ICH_14M (12)
Del R148 C268 1/12
Y2 from 20 PF change to 12 PF 6/28
+1.05VS_ VTT
+3VS
10K_040 2_5%
RAM ID1
RAM ID0
PCH_SML 1CLK EC_SMB_CK 2
12
R521
R521
1M_0402 _5%
1M_0402 _5%
C554,C555 from 27p change to 12p 6/28
1 2
R909 0 _0402_5%R90 9 0_0402_5%
Del R505 1/12
C554
C554 12P_040 2_50V8J
12P_040 2_50V8J
1 2
12
Y2
Y2 25MHZ_1 2PF_X5H02500 0FC1H-H
25MHZ_1 2PF_X5H02500 0FC1H-H
1 2
C555
C555 12P_040 2_50V8J
12P_040 2_50V8J
EC_SMB_ CK2 (33)
Change to 5x3.2
Change From MOS to 0 1/13
PCH_SML 1DAT EC_ SMB_DA2
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
1 2
R910 0 _0402_5%R91 0 0_0402_5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
1
EC_SMB_ DA2 (33)
of
14 51Monday, November 22, 20 10
14 51Monday, November 22, 20 10
14 51Monday, November 22, 20 10
0.1
0.1
0.1
5
DMI_HTX_P RX_N[0..3](4)
DMI_HTX_P RX_P[0..3](4)
DMI_PTX_H RX_N[0..3](4)
DMI_PTX_H RX_P[0..3](4)
DMI_HTX_P RX_N[0..3]
DMI_HTX_P RX_P[0..3]
DMI_PTX_H RX_N[0..3]
DMI_PTX_H RX_P[0..3]
4
3
2
1
D D
+3VS
+3VALW
R599 10K_04 02_5%
R599 10K_04 02_5%
R584 8.2K_04 02_5%
R584 8.2K_04 02_5%
R178 10K_04 02_5%
C C
B B
Add R911 1/13 Add R1348 3/18
A A
R178 10K_04 02_5%
R188 10K_04 02_5%
R188 10K_04 02_5%
R198 10K_04 02_5%
R198 10K_04 02_5%
SYS_PW ROK
4/15 change pull down connect to PWROK_R
H_FDI_TXN [0..7](4)
H_FDI_TXP [0..7](4)
@
@
1 2
R604 8.2K_04 02_5%
R604 8.2K_04 02_5%
R791 1K_040 2_5%R791 1K_0402_5%
1 2
1 2
1 2
1 2
@
@
1 2
PWRO K
PM_CLKR UN#
XDP_DBR ESET#
12
SUS_PW R_DN_ACK
PCH_GPIO7 2
EC_SW I#
PCH_PCIE_ WAKE#
PM_SLP_ LAN#
+3VALW
EC_ACIN(33)
1 2
R1348 22 _0402_5%
R1348 22 _0402_5%
1 2
R911 22_04 02_5%
R911 22_04 02_5%
5
H_FDI_TXN [0..7]
H_FDI_TXP [0..7]
+1.05VS_ VTT
R163
R163
49.9_040 2_1%
49.9_040 2_1%
1 2
09/09/14 WW37 PCH WAKE# PU 10K
XDP_DBR ESET#(5)
3/22 add R1358
PM_DRAM _PWRGD(5)
SUS_PW R_DN_ACK(33)
@
@
1 2
R230 10K_04 02_5%
R230 10K_04 02_5%
R908 0_04 02_5%R908 0_04 02_5%
PWRO K_R
4
Y
PWRO K_R
EC_PW ROK
LAN_RST #
No used Integrated LAN, connecting LAN_RST# to GND
PBTN_OU T#(33)
12
+3VS
5
U40
U40
2
P
B
1
A
G
MC74VHC 1G08DFT2G_SC 70-5
MC74VHC 1G08DFT2G_SC 70-5
3
1 2
R181 1 0K_0402_5%
R181 1 0K_0402_5%
1 2
R676 1 0K_0402_5%
R676 1 0K_0402_5%
1 2
R184 1 0K_0402_5%
R184 1 0K_0402_5%
EC_SW I#(33)
R1358
R1358
1 2
0_0402_ 5%
0_0402_ 5%
EC_PW ROK
VGATE
DMI_HTX_P RX_N0 DMI_HTX_P RX_N1 DMI_HTX_P RX_N2 DMI_HTX_P RX_N3
DMI_HTX_P RX_P0 DMI_HTX_P RX_P1 DMI_HTX_P RX_P2 DMI_HTX_P RX_P3
DMI_PTX_H RX_N0 DMI_PTX_H RX_N1 DMI_PTX_H RX_N2 DMI_PTX_H RX_N3
DMI_PTX_H RX_P0 DMI_PTX_H RX_P1 DMI_PTX_H RX_P2 DMI_PTX_H RX_P3
DMI_COMP
XDP_DBR ESET#
SYS_PW ROK
PWRO K
MEPW ROK
LAN_RST #
PCH_RSM RST#
SUS_PW R_DN_ACK
PBTN_OU T#
PCH_ACIN
PCH_GPIO7 2
EC_SW I#
EC_PW ROK (33)
VGATE (47)
4
U30C
U30C
BC24
DMI0RXN
BJ22
DMI1RXN
AW20
DMI2RXN
BJ20
DMI3RXN
BD24
DMI0RXP
BG22
DMI1RXP
BA20
DMI2RXP
BG20
DMI3RXP
BE22
DMI0TXN
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_DN_ACK / GPIO30
P5
PWRBTN#
P7
ACPRESENT / GPIO31
A6
BATLOW# / GPIO72
F14
RI#
IBEXPEAK-M _FCBGA107
IBEXPEAK-M _FCBGA107
REV1.0
REV1.0
FDI_FSYNC0
DMI
FDI
DMI
FDI
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
System Power Management
SLP_LAN# / GPIO29
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7
FDI_INT
WAKE#
SLP_S4#
SLP_S3#
SLP_M#
TP23
PMSYNCH
BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12
BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12
BJ14
BF13
BH13
BJ12
BG14
PCH_PCIE_ WAKE#
J12
PM_CLKR UN#
Y1
PCH_GPIO6 1
P8
PCH_GPIO6 2
F3
E4
H7
P12
PM_SLP_ M#
K8
PM_SLP_ DSW#
N2
BJ10
PM_SLP_ LAN#
F6
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
3
H_FDI_TXN 0 H_FDI_TXN 1 H_FDI_TXN 2 H_FDI_TXN 3 H_FDI_TXN 4 H_FDI_TXN 5 H_FDI_TXN 6 H_FDI_TXN 7
H_FDI_TXP 0 H_FDI_TXP 1 H_FDI_TXP 2 H_FDI_TXP 3 H_FDI_TXP 4 H_FDI_TXP 5 H_FDI_TXP 6 H_FDI_TXP 7
PCH_PCIE_ WAKE# (28,29,31 )
@
@
PAD
PAD
T7
T7
@
@
PAD
PAD
T31
T31
PM_SLP_ S5# (33)
PM_SLP_ S4# (33)
PM_SLP_ S3# (33)
@
@
PAD
PAD
T8
T8
@
@
PAD
PAD
T29
T29
H_PM_SYNC (5)
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
H_FDI_INT (4)
H_FDI_FSYNC0 (4)
H_FDI_FSYNC1 (4)
H_FDI_LSYNC0 (4)
H_FDI_LSYNC1 (4)
12
R1371
R1371 1K_0402 _5%
1K_0402 _5%
Change From +3V to +3VALW 1/8Change D24 to 0 1/12
@
R645 0_04 02_5%
R645 0_04 02_5%
Q38
Q38 MMBT390 6_SOT23-3
PCH_RSM RST#
R656
R656 10K_040 2_5%
10K_040 2_5%
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
MMBT390 6_SOT23-3
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PCH (3/9) DMI, FDI, PM
PCH (3/9) DMI, FDI, PM
PCH (3/9) DMI, FDI, PM
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
@
12
123
C
C
E
E
B
B
1 2
R644 4.7K_04 02_5%
R644 4.7K_04 02_5%
D27A
D27A
1
2
BAV99DW -7_SOT363
BAV99DW -7_SOT363
D27B
D27B
4
5
BAV99DW -7_SOT363
BAV99DW -7_SOT363
6
3
1
EC_RSMR ST# (33)
+3VALW
12
R655
R655
2.2K_040 2_5%
2.2K_040 2_5%
15 51Monday, November 22, 20 10
15 51Monday, November 22, 20 10
15 51Monday, November 22, 20 10
0.1
0.1
0.1
5
IGPU_BKLT_EN Pul l down 100K at EC Side
D D
PCH_ENVDD Pull d own 100k at JLV DS1 Side
PCH_LCD_CLK and PCH_LCD_DATA Pu ll high 4.7K at JLVDS1 Side
+3VS
C C
Del R116 R119 1/13
R117 10K_ 0402_5% R117 10K_0 402_5%
1 2
R118 10K_ 0402_5% R118 10K_0 402_5%
1 2
R517 2.2K_ 0402_5% R517 2.2 K_0402_5%
1 2
R518 2.2K_ 0402_5% R518 2.2 K_0402_5%
1 2
R1048 4.7K_040 2_5%R 1048 4.7K_0 402_5%
1 2
R1049 4.7K_040 2_5%R 1049 4.7K_0 402_5%
1 2
LCTLA_C LK
LCTLB_D ATA
PCH_CRT _CLK
PCH_CRT _DATA
SDVOB_S CLK
SDVOB_S DATA
Change R1048.R1049 From 2.2K to 4.7K 1/18
1 2
R511 150_040 2_1%R511 150_040 2_1%
1 2
R512 150_040 2_1%R512 150_040 2_1%
1 2
R513 150_040 2_1%R513 150_040 2_1%
close to PCH
B B
A A
ENBKL(33)
R112 0_04 02_5%R112 0_04 02_5%
1 2
Del U11.C230.R115.R126 1/7
PCH_CRT _B
PCH_CRT _G
PCH_CRT _R
PCH_CRT _HSYNC(25) PCH_CRT _VSYNC(2 5)
IGPU_BKLT _ENENBKL
4
PCH_ENV DD(22)
DPST_PW M(22)
PCH_LCD _CLK(22)
PCH_LCD _DATA(22)
R145
R145
1 2
2.37K_04 02_1%
2.37K_04 02_1%
R141
R141
1 2
0_0402_ 5%
0_0402_ 5%
PCH_TXC LK-(22) PCH_TXC LK+(22)
PCH_TXO UT0-(22) PCH_TXO UT1-(22) PCH_TXO UT2-(22)
PCH_TXO UT0+(22 ) PCH_TXO UT1+(22 ) PCH_TXO UT2+(22 )
PCH_CRT _B(25)
PCH_CRT _G(25) PCH_CRT _R(2 5)
PCH_CRT _CLK(25) PCH_CRT _DATA(25)
R974 22_0 402_5%R974 2 2_0402_5%
1 2
R975 22_0 402_5%R975 2 2_0402_5%
1 2
Add R974.R975 1/14
IGPU_BKLT _EN
PCH_LCD _CLK PCH_LCD _DATA
LCTLA_C LK LCTLB_D ATA
LVDS_IBG
LVD_VRE F
PCH_TXC LK­PCH_TXC LK+
PCH_TXO UT0­PCH_TXO UT1­PCH_TXO UT2-
PCH_TXO UT0+ PCH_TXO UT1+ PCH_TXO UT2+
PCH_CRT _B PCH_CRT _G PCH_CRT _R
PCH_CRT _CLK PCH_CRT _DATA
PCH_CRT _HSYNC_R PCH_CRT _VSYNC_R
CRT_IREF
12
R135
R135 1K_0402 _0.5%
1K_0402 _0.5%
2/3 Change to 1K_0402_0.5% from Intel Suggestion. (EDS 1.0 is incorrect)
U30D
U30D
T48
L_BKLTEN
T47
L_VDD_EN
Y48
L_BKLTCTL
AB48
L_DDC_CLK
Y45
L_DDC_DATA
AB46
L_CTRL_CLK
V48
L_CTRL_DATA
AP39
LVD_IBG
AP41
LVD_VBG
AT43
LVD_VREFH
AT42
LVD_VREFL
AV53
LVDSA_CLK#
AV51
LVDSA_CLK
BB47
LVDSA_DATA#0
BA52
LVDSA_DATA#1
AY48
LVDSA_DATA#2
AV47
LVDSA_DATA#3
BB48
LVDSA_DATA0
BA50
LVDSA_DATA1
AY49
LVDSA_DATA2
AV48
LVDSA_DATA3
AP48
LVDSB_CLK#
AP47
LVDSB_CLK
AY53
LVDSB_DATA#0
AT49
LVDSB_DATA#1
AU52
LVDSB_DATA#2
AT53
LVDSB_DATA#3
AY51
LVDSB_DATA0
AT48
LVDSB_DATA1
AU50
LVDSB_DATA2
AT51
LVDSB_DATA3
AA52
CRT_BLUE
AB53
CRT_GREEN
AD53
CRT_RED
V51
CRT_DDC_CLK
V53
CRT_DDC_DATA
Y53
CRT_HSYNC
Y51
CRT_VSYNC
AD48
DAC_IREF
AB51
CRT_IRTN
IBEXPEAK-M _FCBGA107
IBEXPEAK-M _FCBGA107
3
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
BJ46 BG46
BJ48 BG48
BF45 BH45
T51 T53
BG44 BJ44 AU38
BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38
Y49 AB49
BE44 BD44 AV40
BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36
U50 U52
BC46 BD46 AT38
BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36
SDVO_TVCLKINN SDVO_TVCLKINP
SDVO_STALLN SDVO_STALLP
SDVO_INTN SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN DDPB_AUXP
DDPB_HPD
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN DDPC_AUXP
DDPC_HPD
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN DDPD_AUXP
DDPD_HPD
CRT
CRT
REV1.0
REV1.0
SDVOB_S CLK SDVOB_S DATA
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
DDPC_SC LK DDPC_SD ATA
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
PORT B
2
SDVOB_S TALL- (24) SDVOB_S TALL+ (2 4)
SDVOB_S CLK (24) SDVOB_S DATA (24)
4/13 add test point
@
C1004 .1 U_0402_16V7KC1004 .1 U_0402_16V7K
1 2
C1005 .1 U_0402_16V7KC1005 .1 U_0402_16V7K
1 2
C1006 .1 U_0402_16V7KC1006 .1 U_0402_16V7K
1 2
C1007 .1 U_0402_16V7KC1007 .1 U_0402_16V7K
1 2
C1008 .1 U_0402_16V7KC1008 .1 U_0402_16V7K
1 2
C1009 .1 U_0402_16V7KC1009 .1 U_0402_16V7K
1 2
C1010 .1 U_0402_16V7KC1010 .1 U_0402_16V7K
1 2
C1011 .1 U_0402_16V7KC1011 .1 U_0402_16V7K
1 2
C1078 .1U_0402 _16V7KC1078 .1U_0402 _16V7K
1 2
C1014 .1U_0402 _16V7KC1014 .1U_0402 _16V7K
1 2
C1028 .1U_0402 _16V7KC1028 .1U_0402 _16V7K
1 2
C1065 .1U_0402 _16V7KC1065 .1U_0402 _16V7K
1 2
C1068 .1U_0402 _16V7KC1068 .1U_0402 _16V7K
1 2
C1070 .1U_0402 _16V7KC1070 .1U_0402 _16V7K
1 2
C1071 .1U_0402 _16V7KC1071 .1U_0402 _16V7K
1 2
C1075 .1U_0402 _16V7KC1075 .1U_0402 _16V7K
1 2
T42 PAD@T42 PAD
DDPC_SC LK (26) DDPC_SD ATA (2 6)
Configuration Wise Pin Mapping for DDI Ports
DDI PCH Pin Names
DDPB_[0]P
DDPB_[0]N
DDPB_[1]P
DDPB_[1]N
DDPB_[2]P
DDPB_[2]N
DDPB_[3]P
DDPB_[3]N
DDPB_AUXP
DDPB_AUXN
DDPB_HPD
SDVO_CTRLCLK
SDVO_CTRLDATA
SDVO Mapping
SDVO_RED
SDVO_RED#
SDVO_GREEN
SDVO_GREEN#
SDVO_BLUE
SDVO_BLUE#
SDVO_CLK
SDVO_CLK#
NA
NA
NA
SDVO_CTRLCLK
SDVO_CTRLDATA
HDMI/DVI Mapping
TMDSB_DATA2
TMDSB_DATA2#
TMDSB_DATA1
TMDSB_DATA1#
TMDSB_DATA0
TMDSB_DATA0#
TMDSB_CLK
TMDSB_CLK#
NA
NA
HDMIB_HPD
HDMIB_CTRLCLK
HDMIB_CTRLDATA
1
SDVOB_R - (24) SDVOB_R + (24) SDVOB_G - (2 4) SDVOB_G + (24) SDVOB_B - (2 4) SDVOB_B + (24) SDVOB_C LK- (24) SDVOB_C LK+ (24)
PCH_DPC _HPD (26)
PCH_TMD S_D2# (2 6) PCH_TMD S_D2 (26 ) PCH_TMD S_D1# (2 6) PCH_TMD S_D1 (26 ) PCH_TMD S_D0# (2 6) PCH_TMD S_D0 (26 ) PCH_TMD S_CK# (2 6) PCH_TMD S_CK (26 )
DisplayPort Mapping
DDPB_[0]P
DDPB_[0]N
DDPB_[1]P
DDPB_[1]N
DDPB_[2]P
DDPB_[2]N
DDPB_[3]P
DDPB_[3]N
DDPB_AUXP
DDPB_AUXN
DDPB_HPD
NA
NA
Security Class ification
Security Class ification
Security Class ification
2009/11/ 23 2010/11/ 23
2009/11/ 23 2010/11/ 23
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/11/ 23 2010/11/ 23
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCH (4/9) LVDS, CRT, DPI
PCH (4/9) LVDS, CRT, DPI
PCH (4/9) LVDS, CRT, DPI
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
PAU30 M/B LA-6392P Schematic
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
16 51Monday, November 22, 20 10
16 51Monday, November 22, 20 10
16 51Monday, November 22, 20 10
1
0.1
0.1
0.1
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