YAMAH YGV619 Datasheet

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YGV619

AVDP6

Advanced Video Display Processor 6

Outline

YGV619 is a VDP (Video Display Processor) adopting OSD display control system which is best suited to the data broadcasting. The digital image interface of this device for connection with MPEG decoder has been improved. The use of this device allows screen composition that is suited to mobile information terminals, car navigation system, etc. Scan timing conforming to the display standard of digital TVs can be made.

Two built-in PLL circuits allows to realize superimposition of external image signal on original image signal, and to produce clock best suited to SDRAM that is adopted as external video memory.

Features

Display planes: External digital image is overlaid with OSD images composed of regions.

Up to four planes, which are individually composed of back drop plane (plane on which external images are inputted)

+region, are available.

OSD image format:

8bit/dot palette mode, and 16 bit RGB or YCbCr format can be selected. YCbCr conforms to the conversion method of ITU601.

Color palette (256 colors in 16777 k colors) can be specified by region.

Digital image input format:

· 18bitR6G6B6

(Max. dot clock frequency: 80 MHz)

· 16bitYCbCr422

(Max. dot clock frequency: 80 MHz)

· 8bitITU656

(Dot clock frequency 27 MHz)

Digital image output format:

·R6G6B6 + 2 bit AT

·18bitYCbCr444 + 2 bit AT

·16bitYCbCr422 + 2 bit AT

·8bitITU656 + 2 bit AT + 6 bit α blending coefficient

Max. OSD resolution: 960 dots × 1080 lines

(However, max. resolution of overlaid external image is 1920 ×1080 lines)

Applicable digital TV image format:

·525i

·525p

·1125i

Video capture function:

·Draws external image input on the frame memory in real time.

·Can convert resolution.

·Provided with progressive scanning conversion

YGV619 CATALOG

CATALOG No.: LSI-4GV619A1

2001.01

YGV619

Priority of display planes

Regular priority: Plane D > Plane C > Plane B > Plane A > Back drop plane The priority can be changed by region.

α blending function (64 intensity level) Blending weight can be set by dot.

Flicker cancel filter is built in.

Enabling / disabling flicker cancel function can be set by region.

8 bit DACs are built in for R, G and B individually. (Max. operating frequency: 80 MHz)

Two PLLs are built in. (1: Generates SDRAM clock and system clock 2: Generates dot clock)

Display monitor control

· Display resolution and scanning frequency can be set optionally.

This function is compatible with progressive scanning and interlaced scanning modes. NTSC subcarrier output

SDRAM can be added externally as VRAM (SDRAM generation clock frequency: Max. 80 MHz.)

·16 bit bus

 

:

 

512k words × 16 bits × 2 banks × 1 pc.

(capacity

2M bytes)

1M words × 16 bits × 4 banks × 1 pc.

(capacity

:

8M bytes)

2M words × 16 bits × 2 banks × 1 pc.

(capacity

:

8M bytes)

·32 bit bus

 

:

 

512k words × 16 bits × 2 banks × 2 pcs.

(capacity

4M bytes)

512k words × 32 bits × 4 banks × 1 pc.

(capacity

:

8M bytes)

1M words × 16 bits × 4 banks × 2 pcs.

(capacity

:

16M bytes)

2M words × 16 bits × 2 banks × 2 pcs.

(capacity

:

16M bytes)

CPU interface

Compatible with 16/32 bit CPU. Various built-in tables can be mapped on CPU space. Compatible with little endian and big endian

Package: 240SQFP (YGV619-S)

Operating temperature range: -45 to +85°C

Power supply: 3.3V, single power supply

Supplementary information:

For YGV619, Application Manual that details the specifications of the device and the evaluation board (MSY619DB01) are available in addition to this brochure.

The evaluation board is equipped with an SDRAM of 16 MB as a video memory. A high performance system can be realized when it is used with Hitachi’s CPU board, Super H Solution Engine.

The device driver provided by Yamaha and attached to the evaluation board consists of the main body of the driver and API related layers, allowing the user to build it into the system easily according to the environment.

For the details of these products, inquire of the sales agents or our business offices.

For CPU board, inquire of: Hitachi ULSI Systems Co., Ltd.

Tel:+81-42-351-6600

2

YAMAH YGV619 Datasheet

YGV619

Block Diagram

D31-0

 

 

A23-2

 

 

CSREG

 

 

CSMEM

 

 

DREQ

 

 

RD

DRAWING

 

 

 

A1/WR3

CPU

SDQ31-0

PROCESSOR

 

INTERFACE

 

WR2-0

UNIT

SA12-0

 

WAIT

SDRAM

SBA1-0

 

SCS

READY

INTERFACE

INT

 

RAS

RESET

 

CAS

 

 

WE

SYCKIN

 

DQM3-0

SYCKOUT

VIDEO

SDCLK

 

 

 

CAPTURE

 

FSC

CONTROLLER

 

CSYNC

 

 

HSYNC

 

 

HSIN

CRT

 

 

 

VSIN

CONTROLLER

 

DCKIN

 

AT1-0

 

 

DCKOUT

 

GCKOUT

PIXEL

 

GCKIN

DRO[5:0]

DATA

 

 

DGO[5:0]

DRI[5:0]

CONTROLLER

 

DBO[5:0]

 

 

DGI[5:0]

 

 

DBI[5:0]

DAC

R, G, B

 

AVDP6 performs parallel processing including operation of writing display data into video memory (SDRAM) connected on the local bus (drawing function) and operation of sequentially reading bit map image stored in the video memory in accordance with monitor scanning (display function).

Drawing function:

This function transfers bit map image data configured on the external memory of CPU to video memory. For the transfer of the data, a method that maps the video memory as external memory managed by CPU and performs the transfer as the transfer between external memories of CPU, or a method that uses internal drawing processor of AVDP6 to configure the display image on the video memory can be used.

Display function:

This function displays the bit map image stored in the video memory in accordance with the display parameters that are stored in the internal registers of AVDP6 and the video memory. Basically, AVDP6 automatically sends out display data and refreshes SDRAM once initial setting for internal registers are completed. When performing dynamic processing such as scroll, the processing that synchronizes with the scanning of AVDP6 can be performed easily by using internal flag polling of AVDP6 or interrupt function.

3

YGV619

Pin Assignment

VDD DCKIN DCKOUT VSS TCK80 TCKS VSIN HSIN GCKS GCKIN DBI0 VDD DBI1 DBI2 DBI3 VSS DBI4 DBI5 DGI0 DGI1 DGI2 DGI3 DGI4 DGI5 DRI0 VDD DRI1 VSS DRI2 DRI3 DRI4 DRI5 AVSS3 AVDD3 AVDD4 REXT AVSS4 R AVSS4 G AVSS4 B AVSS4 VSS DBO0 DBO1 DBO2 VDD DBO3 DBO4 VSS DBO5 DGO0 DGO1 DGO2 DGO3 VSS DGO4 DGO5 DRO0

A V S S 1 1 A V D D 1 2 A23 3 A22 4 A21 5 A20 6 A19 7 V S S 8 A18 9 V D D 10 A17 11 A16 12 A15 13 A14 14 A13 15 A12 16 A11 17 A10 18 A9 19 V S S 20 A8 21 A7 22 A6 23 A5 24 V D D 25 A4 26 A3 27 A2 28

A1/W R 3 29 W R 2 30 W R 1 31 V S S 32 W R 0 33

R D 34 R E S E T 35 V D D 36 C S R E G 37

C S M E M 38 L W D 39 L E N D 40

S Y C K S 41 D R E Q 42 V S S 43 R E A D Y 44 W A I T 45 INT 46 D31 47 V D D 48 D30 49 D29 50 D28 51 D27 52 D26 53 D25 54 D24 55 V S S 56 D23 57 D22 58 D21 59 V D D 60

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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121

61

62

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66

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68

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120

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D20

D19

D18

D17

D16

VSS

D15

D14

D13

D12

D11

VDD

D10

D9

D8

VSS

D7

D6

D5

D4

D3

D2

D1

D0

VSS

SYCKOUT

SYCKIN

VDD

 

TEST2

 

TEST1

 

TEST0

SDQ0

SDQ15

SDQ1

VSS

SDQ14

SDQ2

SDQ13

SDQ3

VDD

SDQ12

VSS

SDQ4

SDQ11

SDQ5

SDQ10

SDQ6

VSS

SDQ9

SDQ7

SDQ8

DQM0

VDD

 

WE

VSS

DQM1

 

CAS

SDCLK

AVSS2

AVDD2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V D D

D R O 1

D R O 2

V S S

D R O 3

D R O 4

D R O 5

G C K O U T

A T 0

V S S

A T 1 F S C

B L A N K

H S Y N C

C S Y N C

V D D

S D Q 2 4

V S S

S D Q 2 3

S D Q 2 5

S D Q 2 2

S D Q 2 6

S D Q 2 1

V S S

S D Q 2 7

S D Q 2 0

S D Q 2 8

S D Q 1 9

V D D

S D Q 2 9

V S S

S D Q 1 8

S D Q 3 0

S D Q 1 7

S D Q 3 1

S D Q 1 6

V S S

D Q M 3

D Q M 2

S A 4

S A 3

V D D

S A 5

S A 2

S A 7

V S S

S A 6

S A 1

S A 0

S A 8

SA10

S A 9

SA12

V D D

S B A 0

V S S

SA11 S B A 1

S C S

R A S

Top view

4

YGV619

Pin Functions

< CPU INTERFACE >

l D31-0 (I/O: Pull Up)

CPU data bus. D31-16 pins are not used for 16 bit CPU (LWD=0). These pins are provided with a pull-up resistor. Unused pins are to be open.

l A23-8 (I: Pull Up), A7-2 (I)

CPU address bus. When accessing CSREG space, signals inputted to A23-8 pins are ignored without regarding to the

bus width of CPU. Internal registers are selected depending on the state of signals inputted to A7-2 for 32 bit CPU or A7- 2 and A1 / WR3 pin for 16 bit CPU. Systems that control AVDP6 only with CSREG do not use this address bus.

However, A23-8 pins must be open because they are provided with pull-up resistor. All the addresses are valid when accessing CSMEM space.

l CSREG (I)

Chip select signal input to REG space. Internal registers of AVDP6 are accessed by a using write / read pulse that is inputted when the chip select signal is active.

When this signal is low, inputs to A23-8 pins are ignored.

l CSMEM (I)

CSMEM is made active when directly mapping the video memory connected to local bus of AVDP6 on the memory space of CPU. The video memory managed by AVDP6 is directly accessed using write / read pulse that is inputted with

this chip select signal is active. The video memory can be accessed from REG space without using this pin, however, high level signal must be inputted to CSMEM in this case.

l LWD (I: Pull Up)

Selects a CPU data bus width. When high level signal is inputted to this pin, AVDP6 operates as CPU 32 bit device, or when low level signal is inputted to this pin, AVDP6 operates as CPU 16 bit device.

l A1 / WR3 , WR2-0 (I)

Controls write access to AVDP6 when chip select input signal is active. A1 / WR3 control D31-24, WR2 controls D23-16, WR1 controls D15-8, and WR0 controls D7-0.

For 16 bit CPU, A1 / WR3 function as A1 of CPU address. WR2 is not used, and thus must be open because the pin is provided with a pull-up resistor.

l RD (I)

Controls read access to AVDP6 when chip select input signal is active. D31-0 pins are in output state while this signal and chip select signals are active. For 16 bit CPU, only D15-0 pins are in output state and D31-16 pins are in input states at all times.

l WAIT (O: Pull Up, 3-state output)

Data wait signal output to CPU. When CSREG pin or CSMEM pin (hereafter called “ CS pin”) is active, the WAIT signal is asserted once for RD or A1 / WR3 and WR2-0 signals, and then negated when AVDP6 becomes accessible.

This pin becomes high impedance state when CS pin is not active, and outputs high level signal when CS pin is active and RD or A1 / WR3 and WR2-0 pins are not active. Use this pin or READY depending on the type of CPU.

l READY (O: Pull Up, 3-state output)

Data ready signal output to CPU. When AVDP6 becomes accessible, this signal is asserted. This pin becomes high

impedance state when CS pin is not active, outputs high level signal when CS pin is active and RD or A1 / WR3, WR2-0 pins are not active. Use this pin or WAIT depending on the type of CPU.

l INT (O)

Interrupt request signal output to CPU. This pin becomes active when internal state of AVDP6 coincides with the setting conditions of the registers, and is reset when internal registers of AVDP6 are accessed.

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