YAMAH YAC520-E Datasheet

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YAC520

HGVC1

High Grade Volume Control

Outline

YAC520(HGVC1) is a high grade stereophonic digital volume for high end audio system.

It provides wide dynamic range and low distortion as well, and can control individual channels in 256 steps with 0.5 dB per step. The use of 16 bit serial data interface allows daisy chain connection of several devices for multi channel system.

Zero Crossing Detection function suppresses audible noise at quick change of the volume.

YAC520 operates on a single 5 volt power supply, and it is possible to input signal of up to 7.9Vrms by using three types of connection methods.

Development evaluation board, DMB-HGVC1, equipped with PC interface is available.

Features

● Wide volume range

A: +32.0 to - 95.0dB

IN1=IN2

(Input < 2.0Vrms @VDD=5V)

(can be used in three ways)

B: +29.5 to - 97.5dB

IN2=GND

(Input < 2.6Vrms @VDD=5V)

 

C: +20.0 to -107.0dB

IN1=GND

(Input < 7.9Vrms @VDD=5V)

● Adjustment step

adjustable in 256 steps, with 0.5dB per step

● Gain Error

± 0.1dB

 

 

● Low distortion factor

0.001% (input=150 mVrms, gain=+16dB)

● Low residual noise

1 μVrms(gain=- )

 

 

Others

Process

CMOS process

Package

20 SSOP (YAC520-E)

Power supply voltage

5 V

 

Operating temperature

0 to +70

ºC

Load current

20 mA

@VDD=5.0 V

 

 

 

 

 

 

 

 

 

YAC520 CATALOG

CATALOG No.: LSI-4AC520A0

2001.3

YAMAH YAC520-E Datasheet

YAC520

Block Diagram

LIN2

LIN1

DVSS

 

DVDD

L

 

Zero Cross

 

Detection

AVSS

R

AVDD

 

RIN1

RIN2

VREF

+

-

 

 

 

LOUT

 

 

Vref

 

 

 

Generator

 

256

 

&

VREF

 

Reset

 

 

 

 

pulse

 

 

 

Generator

 

Reset

 

 

ICN

 

 

 

TE

Control

 

 

ZCEN

Register

 

 

 

 

 

 

SDATAO

 

16

S/P

SDATAI

 

Register

 

 

 

CSN

 

 

 

256

 

 

SCLK

 

 

 

ROUT

-

+

VREF

2

YAC520

Pin Assignment

SCLK

 

1

20

 

SDATAI

 

 

 

 

2

 

 

CSN

SDATAO

 

19

 

 

 

3

18

 

 

DVDD

 

 

ZCEN

 

 

4

17

 

ICN

DVSS

 

 

AVSS

 

5

16

 

TE

 

 

 

 

6

 

 

RIN1

AVDD

 

15

 

 

 

7

14

 

RIN2

ROUT

 

 

VREF

 

8

13

 

AVSS

 

 

 

 

9

 

 

 

LOUT

 

12

 

LIN2

AVSS

 

10

11

 

LIN1

 

 

 

 

 

 

 

 

 

 

Top View

3

YAC520

Pin Functions

Power supply pins

AVDD

Analog power supply (+5.0 V)

AVSS

Analog ground

DVDD

Digital power supply (+5.0 V)

DVSS

Digital ground

Analog Pins

 

 

LIN1

Left Channel Analog input 1

Lch analog input pin 1

Gain setting ranges from +32 dB to - 95 dB when the signal inputted to LIN2 is inputted this pin, and gain setting ranges from +20.0 dB to - 107.0 dB when it is grounded through a capacitor.

LIN2

Left Channel Analog input 2

Lch analog input pin 2

Gain setting ranges from +32 dB to - 95 dB when the signal inputted to LIN1 is inputted this pin, and gain setting ranges from +29.5 dB to - 97.5 dB when it is grounded through a capacitor.

RIN1

Right Channel Analog input 1

Rch analog input pin 1

Gain setting ranges from +32 dB to - 95 dB when the signal inputted to RIN2 is inputted this pin, and gain setting ranges from +20.0 dB to - 107.0 dB when it is grounded through a capacitor.

RIN2

Right Channel Analog input 2

Rch analog input pin 2

Gain setting ranges from +32 dB to - 95 dB when the signal inputted to RIN1 is inputted this pin, and gain setting ranges from +29.5 dB to - 97.5 dB when it is grounded through a capacitor.

LOUT

Left Channel Analog output

Lch analog output pin

Note this is an inverted output.

ROUT

Right Channel Analog output

Rch analog output pin

Note this is an inverted output.

VREF

Analog Reference Voltage (output)

Analog reference voltage output pin

Outputs 1/2VDD. Ground through a capacitor of 10 μF or more to attain stabilization.

Digital Pins

 

 

SDATAI

Serial Data Input

Serial data input pin

SDATAO

Serial Data Output

Serial data putput pin

Outputs Serial data when CSN is “low”, or becomes high impedance state when it is “high”.

SCLK

Serial Clock (Input)

Serial clock input pin

CSN

Chip Select (Input)

Chip select input pin

ICN

DC Bias Initial Clear (Input)

DC bias initialization pin. DC bias is set to VREF (analog reference voltage) when this is “low”.

To stabilize the bias voltage at power on, determine the control time in accordance with the coupling capacitor that is connected to the inputs (LIN1, LIN2, RIN1 ,RIN2).

(Refer to “VREF stabilization time and DC bias initialization time” in the description of functions.)

ZCEN – Zero Crossing Enable (Input)

Zero crossing control pin. Making this pin “high” enables a mode where volume change is performed after detecting zero crossing.

The volume change immediately after writing data when this pin is “low”.

TE – Test Enable (Input)

Test mode control pin. Fix it to “low” or with NC when using.

4

YAC520

Description of analog functions

Maximum input voltage

As described in the following figure, the maximum amplitude of signal that can be inputted varies according the method of the use of L(R) IN1 and 2 pins. The method A makes the maximum amplitude of the input signal approximately 2 Vrms, the method B makes it approximately 2.6 Vrms, and the method C makes it approximately 7.9 Vrms. The use of the method B or C allows to input signal exceeding the power supply voltage.

Note that the gain setting range for the method B is reduced by 2.5 dB from the one for the method A, and 12 dB for the method C.

L(R) IN1

Ri(1)

Rf

L(R) IN1

Ri(1)

Rf

 

 

L(R)OUT

 

 

L(R)OUT

L(R) IN2

 

 

L(R) IN2

 

 

 

Ri(2)

• • • •

 

Ri(2)

• • • •

 

 

 

 

 

 

-

 

 

-

 

 

+

 

 

+

 

 

VREF

 

 

VREF

MethodA: IN1=IN2 Gain range (+32 dB to –95 dB) Maximum input voltage: 2 Vrms

MethodB: IN2=GND Gain range (+29.5 dB to –97.5 dB) Maximum input voltage: 2.6 Vrms

L(R) IN1

Ri(1)

Rf

 

 

L(R)OUT

L(R) IN2

 

 

 

Ri(2)

• • • •

 

 

 

 

-

 

 

+

 

 

VREF

MethodC: IN1=GND

Gain range (+20 dB to –107 dB)

Maximum input voltage: 7.9 Vrms

VREF (analog reference voltage) stabilization time and DC bias initialization time

The time required for stabilization of VREF pin voltage after power on moment varies according to the capacitance of the capacitor connected to VREF pin. Connecting a capacitor of 10 μF makes the time constant 30 ms (typ.). Note that the serial interface becomes invalid in this period, tPUP.

As shown in the following figure, making ICN terminal “low” sets the DC bias forcibly with SW in the LSI.

Since the time constant of L(R) IN1 and 2 pins becomes approximately 300 ms (typ.) when a capacitor of 100 μF is used as the coupling capacitors (Ci1, 2), control ICN according to the capacitor that is connected.

 

 

ICN

 

 

SW

Ci1

L(R) IN1 Ri1=0.98kΩ

Rsw= 80Ω (typ)

L(R)OUT

Audio

 

L(R) IN2

Rf=29.3kΩ

Source

 

Ci2

Ri2=2.94kΩ

 

 

 

-

 

 

+

VREF

Gain setting after power on = -

5

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