R
QPRO XQ4000E/EX
QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 |
Product Specification |
|
|
Product Features
•Certified to MIL-PRF-38535, appendix A QML (Qualified Manufacturers Listing)
•Also available under the following Standard Microcircuit Drawings (SMD)
- |
XC4005E |
5962-97522 |
- |
XC4010E |
5962-97523 |
- |
XC4013E |
5962-97524 |
- |
XC4025E |
5962-97525 |
- |
XC4028EX |
5962-98509 |
•For more information contact the Defense Supply Center Columbus (DSCC) http://www.dscc.dla.mis/v/va/smd/smdsrch.html
•System featured Field-Programmable Gate Arrays
-Select-RAMTM memory: on-chip ultra-fast RAM with
·Synchronous write option
·Dual-port RAM option
-Abundant flip-flops
-Flexible function generators
-Dedicated high-speed carry logic
-Wide edge decoders on each edge
-Hierarchy of interconnect lines
-Internal 3-state bus capability
-Eight global low-skew clock or signal distribution networks
•System Performance beyond 60 MHz
•Flexible Array Architecture
•Low Power Segmented Routing Architecture
•Systems-Oriented Features
-IEEE 1149.1-compatible boundary scan logic support
-Individually programmable output slew rate
-Programmable input pull-up or pull-down resistors
-12 mA sink current per XQ4000E/EX output
•Configured by Loading Binary File
-Unlimited reprogrammability
•Readback Capability
-Program verification
-Internal node observability
•Backward Compatible with XC4000 Devices
•Development System runs on most common computer platforms
-Interfaces to popular design environments
-Fully automatic mapping, placement and routing
-Interactive design editor for design optimization
•Available Speed Grades:
-XQ4000E -3 for plastic packages only
- |
-4 for ceramic packages only |
- |
XQ4028EX -4 for all packages |
More Information
For more information refer to Xilinx XC4000E and XC4000X series Field Programmable Gate Arrays product specification. This data sheet contains pinout tables for XQ4010E only. Refer to Xilinx web site for pinout tables for other devices. (Pinouts for XQ4000E/EX are identical to XC4000E/EX.)
(http://www.xilinx.com/partinfo/databook.htm)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS021 (v2.2) June 25, 2000 |
www.xilinx.com |
1 |
Product Specification |
1-800-255-7778 |
|
QPRO XQ4000E/EX QML High-Reliability FPGAs
Table 1: XQ4000E/EX Field Programmable Gate Arrays
R
|
Max. |
Max. |
Typical |
|
|
|
Max. |
|
|
|
Logic |
RAM Bits |
Gate Range |
|
|
Number |
Decode |
Max. |
|
|
Gates |
(No |
(Logic and |
CLB |
Total |
of |
Inputs |
User |
|
Device |
(No RAM) |
Logic) |
RAM)(1) |
Matrix |
CLBs |
Flip-Flops |
per Side |
I/O |
Packages |
XQ4005E |
5,000 |
6,272 |
3,000 - 9,000 |
14 x 14 |
196 |
616 |
42 |
112 |
PG156, |
|
|
|
|
|
|
|
|
|
CB164 |
|
|
|
|
|
|
|
|
|
|
XQ4010E |
10,000 |
12,800 |
7,000 - 20,000 |
20 x 20 |
400 |
1,120 |
60 |
160 |
PG191, |
|
|
|
|
|
|
|
|
|
CB196, |
|
|
|
|
|
|
|
|
|
HQ208 |
|
|
|
|
|
|
|
|
|
|
XQ4013E |
13,000 |
18,432 |
10,000 - 30,000 |
24 x 24 |
576 |
1,536 |
72 |
192 |
PG223, |
|
|
|
|
|
|
|
|
|
CB228, |
|
|
|
|
|
|
|
|
|
HQ240 |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
25,000 |
32,768 |
15,000 - 45,000 |
32 x 32 |
1,024 |
2,560 |
96 |
256 |
PG299, |
|
|
|
|
|
|
|
|
|
CB228 |
|
|
|
|
|
|
|
|
|
|
XQ4028EX |
28,000 |
32,768 |
18,000 - 50,000 |
32 x 32 |
1,024 |
2,560 |
96 |
256 |
PG299, |
|
|
|
|
|
|
|
|
|
CB228, |
|
|
|
|
|
|
|
|
|
HQ240, |
|
|
|
|
|
|
|
|
|
BG352 |
|
|
|
|
|
|
|
|
|
|
Notes: |
|
|
|
|
|
|
|
|
|
1.Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
XQ4000E Switching Characteristics
XQ4000E Absolute Maximum Ratings(1)
Symbol |
Description |
|
|
Units |
|
|
|
|
|
|
|
VCC |
Supply voltage relative to GND |
|
–0.5 to +7.0 |
V |
|
VIN |
Input voltage relative to GND(2) |
|
–0.5 to VCC + 0.5 |
V |
|
VTS |
Voltage applied to High-Z output(2) |
|
–0.5 to VCC + 0.5 |
V |
|
TSTG |
Storage temperature (ambient) |
|
–65 to +150 |
°C |
|
TSOL |
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) |
+260 |
°C |
||
TJ |
Junction temperature |
Ceramic package |
+150 |
°C |
|
|
|
|
Plastic package |
+125 |
°C |
|
|
|
|
|
|
Notes:
1.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2.Maximum DC excursion above VCC or below Ground must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0V or overshoot to VCC + 2.0V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
2 |
www.xilinx.com |
DS021 (v2.2) June 25, 2000 |
|
1-800-255-7778 |
Product Specification |
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Recommended Operating Conditions(1,2)
Symbol |
Description |
|
Min |
Max |
Units |
|
|
|
|
|
|
|
|
VCC |
Supply voltage relative to GND, TJ = –55°C to +125°C |
Plastic |
4.5 |
5.5 |
V |
|
|
Supply voltage relative to GND, TC = –55°C to +125°C |
Ceramic |
4.5 |
5.5 |
V |
|
VIH |
High-Level Input Voltage |
TTL inputs |
2.0 |
VCC |
V |
|
|
|
CMOS inputs |
70% |
100% |
VCC |
|
VIL |
Low-Level Input Voltage |
TTL inputs |
0 |
0.8 |
V |
|
|
|
CMOS inputs |
0 |
20% |
VCC |
|
TIN |
Input signal transition time |
|
- |
250 |
ns |
|
Notes: |
|
|
|
|
|
|
1.At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
2.Input and output measurement threshold are 1.5V for TTL and 2.5V for CMOS.
XQ4000E DC Characteristics Over Recommended Operating Conditions
Symbol |
|
|
Description |
|
|
|
|
Min |
Max |
Units |
|
|
|
|
|
|
|
||||
VOH |
High-level output voltage @ IOH = –4.0 mA, VCC min |
|
TTL outputs |
2.4 |
- |
V |
||||
|
High-level output voltage @ IOH = –1.0 mA, VCC min |
|
CMOS outputs |
VCC – 0.5 |
- |
V |
||||
V |
Low-level output voltage @ I |
OL |
= 12.0 mA, V |
CC |
min(1) |
|
TTL outputs |
- |
0.4 |
V |
OL |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
CMOS outputs |
- |
0.4 |
V |
|
|
|
|
|
|
|
|
|
||
ICCO |
Quiescent FPGA supply current(2) |
|
|
|
|
- |
50 |
mA |
||
IL |
Input or output leakage current |
|
|
|
|
|
–10 |
+10 |
A |
|
CIN |
Input capacitance (sample tested) |
|
|
|
|
- |
16 |
pF |
||
IRIN |
Pad pull-up (when selected) at VIN = 0V (sample tested)(3) |
–0.02 |
–0.25 |
mA |
||||||
I |
Horizontal longline pull-up (when selected) at logic Low(3) |
|
0.2 |
2.5 |
mA |
|||||
RLL |
|
|
|
|
|
|
|
|
|
|
Notes: |
|
|
|
|
|
|
|
|
|
|
1.With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2.With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA configured with the development system Tie option.
3.Characterized Only.
DS021 (v2.2) June 25, 2000 |
www.xilinx.com |
3 |
Product Specification |
1-800-255-7778 |
|
QPRO XQ4000E/EX QML High-Reliability FPGAs
R
XQ4000E Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature).
Note: -3 Speed Grade only applies to XQ4010E and XQ4013E Plastic Package options only. -4 Speed Grade applies to all XQ devices and is only available in Ceramic Packages only.
XQ4000E Global Buffer Switching Characteristics
|
|
|
|
-3(1) |
-4(2) |
|
Symbol |
Description |
Device |
Max |
Max |
Units |
|
|
|
|
|
|
|
|
TPG |
From pad through primary buffer, to any clock K |
XQ4005E |
- |
7.0 |
ns |
|
|
|
XQ4010E |
6.3 |
11.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4013E |
6.8 |
11.5 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
12.5 |
ns |
|
|
|
|
|
|
|
|
TSG |
From pad through secondary buffer, to any clock K |
XQ4005E |
- |
7.5 |
ns |
|
|
|
XQ4010E |
6.8 |
11.5 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4013E |
7.3 |
12.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
13.0 |
ns |
|
|
|
|
|
|
|
|
Notes:
1.For plastic package options only.
2.For ceramic package options only.
4 |
www.xilinx.com |
DS021 (v2.2) June 25, 2000 |
|
1-800-255-7778 |
Product Specification |
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
|
|
|
|
-3 |
-4 |
|
|
|
|
|
|
|
|
Symbol |
Description |
Device |
Max |
Max |
Units |
|
|
|
|
|
|
|
|
TBUF Driving a Horizontal Longline (LL): |
|
|
|
|
|
|
|
|
|
|
|
|
|
TIO1 |
I going High or Low to LL going High or Low, while T is Low. |
XQ4005E |
- |
5.0 |
ns |
|
|
Buffer is constantly active.(1) |
|
|
|
|
|
|
XQ4010E |
6.4 |
8.0 |
ns |
||
|
|
|||||
|
|
|
|
|
|
|
|
|
XQ4013E |
7.2 |
9.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
11.0 |
ns |
|
|
|
|
|
|
|
|
TIO2 |
I going Low to LL going from resistive pull-up High to active Low. |
XQ4005E |
- |
6.0 |
ns |
|
|
TBUF configured as open-drain.(1) |
|
|
|
|
|
|
XQ4010E |
6.9 |
10.5 |
ns |
||
|
|
|||||
|
|
|
|
|
|
|
|
|
XQ4013E |
7.7 |
11.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
12.0 |
ns |
|
|
|
|
|
|
|
|
TON |
T going Low to LL going from resistive pull-up or floating High to |
XQ4005E |
- |
7.0 |
ns |
|
|
active Low. TBUF configured as open-drain or active buffer with |
|
|
|
|
|
|
XQ4010E |
7.3 |
8.5 |
ns |
||
|
I = Low.(1) |
|||||
|
|
|
|
|
|
|
|
XQ4013E |
7.5 |
8.7 |
ns |
||
|
|
|||||
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
11.0 |
ns |
|
|
|
|
|
|
|
|
TOFF |
T going High to TBUF going inactive, not driving LL. |
XQ4005E |
- |
1.8 |
ns |
|
|
|
XQ4010E |
1.5 |
1.8 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4013E |
1.5 |
1.8 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
1.8 |
ns |
|
|
|
|
|
|
|
|
TPUS |
T going High to LL going from Low to High, pulled up by a single |
XQ4005E |
- |
23.0 |
ns |
|
|
resistor.(1) |
|
|
|
|
|
|
XQ4010E |
22.0 |
29.0 |
ns |
||
|
|
|||||
|
|
|
|
|
|
|
|
|
XQ4013E |
26.0 |
32.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
42.0 |
ns |
|
|
|
|
|
|
|
|
TPUF |
T going High to LL going from Low to High, pulled up by two |
XQ4005E |
- |
10.0 |
ns |
|
|
resistors.(1) |
|
|
|
|
|
|
XQ4010E |
11.0 |
13.5 |
ns |
||
|
|
|||||
|
|
|
|
|
|
|
|
|
XQ4013E |
13.0 |
15.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
18.0 |
ns |
|
|
|
|
|
|
|
|
Notes:
1.These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
DS021 (v2.2) June 25, 2000 |
www.xilinx.com |
5 |
Product Specification |
1-800-255-7778 |
|
QPRO XQ4000E/EX QML High-Reliability FPGAs
R
XQ4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
|
|
|
|
-3 |
-4 |
|
Symbol |
Description(1,2) |
|
|
|
|
|
Device |
Max |
Max |
Units |
|||
TWAF |
Full length, both pull-ups, inputs from IOB I-pins |
XQ4005E |
- |
9.5 |
ns |
|
|
|
XQ4010E |
9.0 |
15.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4013E |
11.0 |
16.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
18.0 |
ns |
|
|
|
|
|
|
|
|
TWAFL |
Full length, both pull-ups, inputs from internal logic |
XQ4005E |
- |
12.5 |
ns |
|
|
|
XQ4010E |
11.0 |
18.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4013E |
13.0 |
19.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
21.0 |
ns |
|
|
|
|
|
|
|
|
TWAO |
Half length, one pull-up, inputs from IOB I-pins |
XQ4005E |
- |
10.5 |
ns |
|
|
|
XQ4010E |
10.0 |
16.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4013E |
12.0 |
17.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
19.0 |
ns |
|
|
|
|
|
|
|
|
TWAOL |
Half length, one pull-up, inputs from internal logic |
XQ4005E |
- |
12.5 |
ns |
|
|
|
XQ4010E |
12.0 |
18.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4013E |
14.0 |
19.0 |
ns |
|
|
|
|
|
|
|
|
|
|
XQ4025E |
- |
21.0 |
ns |
|
|
|
|
|
|
|
|
Notes:
1.These delays are specified from the decoder input to the decoder output.
2.Fewer than the specified number of pull-up resistors can be used, if desired. Using fewer pull-ups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pull-ups are used.
6 |
www.xilinx.com |
DS021 (v2.2) June 25, 2000 |
|
1-800-255-7778 |
Product Specification |
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted.
|
|
|
|
-3 |
|
-4 |
|
||
|
|
|
|
|
|
|
|
|
|
Symbol |
Description |
Min |
|
Max |
Min |
|
Max |
Units |
|
|
|
|
|
|
|
|
|
|
|
Combinatorial Delays |
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
TILO |
F/G inputs to X/Y outputs |
- |
|
2.01 |
- |
|
2.7 |
ns |
|
TIHO |
F/G inputs via H to X/Y outputs |
- |
|
4.3 |
- |
|
4.7 |
ns |
|
THH0O |
C inputs via SR through H to X/Y outputs |
- |
|
3.3 |
- |
|
4.1 |
ns |
|
THH1O |
C inputs via H to X/Y outputs |
- |
|
3.6 |
- |
|
3.7 |
ns |
|
THH2O |
C inputs via DIN through H to X/Y outputs |
- |
|
3.6 |
- |
|
4.5 |
ns |
|
CLB Fast Carry Logic |
|
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TOPCY |
Operand inputs (F1, F2, G1, G4) to COUT |
- |
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2.6 |
- |
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3.2 |
ns |
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TASCY |
Add/Subtract input (F3) to COUT |
- |
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4.4 |
- |
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5.5 |
ns |
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TINCY |
Initialization inputs (F1, F3) to COUT |
- |
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1.7 |
- |
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1.7 |
ns |
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TSUM |
CIN through function generators to X/Y outputs |
- |
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3.3 |
- |
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3.8 |
ns |
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TBYP |
CIN to COUT, bypass function generators |
- |
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0.7 |
- |
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1.0 |
ns |
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Sequential Delays |
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TCKO |
Clock K to outputs Q |
- |
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2.8 |
- |
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3.7 |
ns |
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Setup Time before Clock K |
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TICK |
F/G inputs |
3.0 |
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- |
4.0 |
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- |
ns |
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TIHCK |
F/G inputs via H |
4.6 |
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- |
6.1 |
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- |
ns |
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THH0CK |
C inputs via H0 through H |
3.6 |
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- |
4.5 |
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- |
ns |
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THH1CK |
C inputs via H1 through H |
4.1 |
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- |
5.0 |
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- |
ns |
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THH2CK |
C inputs via H2 through H |
3.8 |
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- |
4.8 |
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- |
ns |
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TDICK |
C inputs via DIN |
2.4 |
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- |
3.0 |
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- |
ns |
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TECCK |
C inputs via EC |
3.0 |
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- |
4.0 |
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- |
ns |
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TRCK |
C inputs via S/R, going Low (inactive) |
4.0 |
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- |
4.2 |
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- |
ns |
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TCCK |
CIN input via F/G |
2.1 |
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- |
2.5 |
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- |
ns |
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TCHCK |
CIN input via F/G and H |
3.5 |
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- |
4.2 |
|
- |
ns |
DS021 (v2.2) June 25, 2000 |
www.xilinx.com |
7 |
Product Specification |
1-800-255-7778 |
|
QPRO XQ4000E/EX QML High-Reliability FPGAs
R
XQ4000E CLB Switching Characteristic Guidelines (continued)
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-3 |
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-4 |
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Symbol |
Description |
Min |
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Max |
Min |
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Max |
Units |
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Hold Time after Clock K |
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TCKI |
F/G inputs |
0 |
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- |
0 |
|
- |
ns |
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TCKIH |
F/G inputs via H |
0 |
|
- |
0 |
|
- |
ns |
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TCKHH0 |
C inputs via H0 through H |
0 |
|
- |
0 |
|
- |
ns |
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TCKHH1 |
C inputs via H1 through H |
0 |
|
- |
0 |
|
- |
ns |
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TCKHH2 |
C inputs via H2 through H |
0 |
|
- |
0 |
|
- |
ns |
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TCKDI |
C inputs via DIN/H2 |
0 |
|
- |
0 |
|
- |
ns |
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TCKEC |
C inputs via EC |
0 |
|
- |
0 |
|
- |
ns |
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TCKR |
C inputs via SR, going Low (inactive) |
0 |
|
- |
0 |
|
- |
ns |
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Clock |
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TCH |
Clock High time |
4.0 |
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- |
4.5 |
|
- |
ns |
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TCL |
Clock Low time |
4.0 |
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- |
4.5 |
|
- |
ns |
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Set/Reset Direct |
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TRPW |
Width (High) |
4.0 |
|
- |
5.5 |
|
- |
ns |
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TRIO |
Delay from C inputs via S/R, going High to Q |
- |
|
4.0 |
- |
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6.5 |
ns |
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Master Set/Reset(1) |
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TMRW |
Width (High or Low) |
11.5 |
|
- |
13.0 |
|
- |
ns |
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TMRQ |
Delay from Global Set/Reset net to Q |
- |
|
18.7 |
- |
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23.0 |
ns |
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TMRK |
Global Set/Reset inactive to first active clock K edge |
- |
|
18.7 |
- |
|
23.0 |
ns |
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FTOG |
Toggle Frequency(2) |
- |
|
125 |
- |
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111 |
MHz |
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Notes: |
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|
1.Timing is based on the XC4005E. For other devices see the static timing analyzer.
2.Export Control Max. flip-flop toggle rate.
8 |
www.xilinx.com |
DS021 (v2.2) June 25, 2000 |
|
1-800-255-7778 |
Product Specification |
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E/EX devices unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
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-3 |
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-4 |
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Symbol |
Write Operation Description |
Size |
Min |
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Max |
Min |
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Max |
Units |
|
TWCS |
Address write cycle time (clock K period) |
16x2 |
14.4 |
|
- |
15.0 |
|
- |
ns |
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TWCTS |
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|
32x1 |
14.4 |
|
- |
15.0 |
|
- |
ns |
TWPS |
Clock K pulse width (active edge) |
16x2 |
7.2 |
|
1 ms |
7.5 |
|
1 ms |
ns |
|
TWPTS |
|
|
32x1 |
7.2 |
|
1 ms |
7.5 |
|
1 ms |
ns |
TASS |
Address setup time before clock K |
16x2 |
2.4 |
|
- |
2.8 |
|
- |
ns |
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TASTS |
|
|
32x1 |
2.4 |
|
- |
2.8 |
|
- |
ns |
TAHS |
Address hold time after clock K |
16x2 |
0 |
|
- |
0 |
|
- |
ns |
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TAHTS |
|
|
32x1 |
0 |
|
- |
0 |
|
- |
ns |
TDSS |
DIN setup time before clock K |
16x2 |
3.2 |
|
- |
3.5 |
|
- |
ns |
|
TDSTS |
|
|
32x1 |
1.9 |
|
- |
2.5 |
|
- |
ns |
TDHS |
DIN hold time after clock K |
16x2 |
0 |
|
- |
0 |
|
- |
ns |
|
TDHTS |
|
|
32x1 |
0 |
|
- |
0 |
|
- |
ns |
TWSS |
WE setup time before clock K |
16x2 |
2.0 |
|
- |
2.2 |
|
- |
ns |
|
TWSTS |
|
|
32x1 |
2.0 |
|
- |
2.2 |
|
- |
ns |
TWHS |
WE hold time after clock K |
16x2 |
0 |
|
- |
0 |
|
- |
ns |
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TWHTS |
|
|
32x1 |
0 |
|
- |
0 |
|
- |
ns |
TWOS |
Data valid after clock K |
16x2 |
8.8 |
|
- |
- |
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10.3 |
ns |
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TWOTS |
|
|
32x1 |
10.3 |
|
- |
- |
|
11.6 |
ns |
Notes:
1.Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2.Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
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|
-3 |
|
-4 |
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||
Symbol |
Write Operation Description |
Size(1) |
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|
Units |
Min |
|
Max |
Min |
|
Max |
||||
TWCDS |
Address write cycle time (clock K period) |
16x1 |
14.4 |
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|
15.0 |
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|
ns |
TWPDS |
Clock K pulse width (active edge) |
16x1 |
7.2 |
|
1 ms |
7.5 |
|
1 ms |
ns |
TASDS |
Address setup time before clock K |
16x1 |
2.5 |
|
- |
2.8 |
|
- |
ns |
TAHDS |
Address hold time after clock K |
16x1 |
0 |
|
- |
0 |
|
- |
ns |
TDSDS |
DIN setup time before clock K |
16x1 |
2.5 |
|
- |
2.2 |
|
- |
ns |
TDHDS |
DIN hold time after clock K |
16x1 |
0 |
|
- |
0 |
|
- |
ns |
TWSDS |
WE setup time before clock K |
16x1 |
1.8 |
|
- |
2.2 |
|
- |
ns |
TWHDS |
WE hold time after clock K |
16x1 |
0 |
|
- |
0.3 |
|
- |
ns |
TWODS |
Data valid after clock K |
16x1 |
- |
|
7.8 |
- |
|
10.0 |
ns |
Notes:
1.Applicable Read timing specifications are identical to Level-Sensitive Read timing.
DS021 (v2.2) June 25, 2000 |
www.xilinx.com |
9 |
Product Specification |
1-800-255-7778 |
|
QPRO XQ4000E/EX QML High-Reliability FPGAs
R
XQ4000E CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform
WCLK (K)
WE
DATA IN
ADDRESS
DATA OUT
TWPS
TWSS TWHS
TDSS TDHS
TASS |
TAHS |
TILO |
TILO |
|
TWOS |
OLD NEW
DS021_01_060100
XQ4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform
|
|
|
TWPDS |
WCLK (K) |
|
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TWSS |
TWHS |
WE |
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TDSDS |
TDHDS |
DATA IN |
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TASDS |
TAHDS |
ADDRESS |
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TILO |
TWODS |
TILO |
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DATA OUT |
|
OLD |
NEW |
DS021_02_060100
10 |
www.xilinx.com |
DS021 (v2.2) June 25, 2000 |
|
1-800-255-7778 |
Product Specification |
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted.
|
|
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|
-3 |
|
-4 |
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||
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|
Symbol |
Single Port RAM |
Size |
Min |
|
Max |
Min |
|
Max |
Units |
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|
Write Operation |
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TWC |
Address write cycle time |
16x2 |
8.0 |
|
- |
8.0 |
|
- |
ns |
|
TWCT |
|
|
32x1 |
8.0 |
|
- |
8.0 |
|
- |
ns |
TWP |
Write Enable pulse width (High) |
16x2 |
4.0 |
|
- |
4.0 |
|
- |
ns |
|
TWPT |
|
|
32x1 |
4.0 |
|
- |
4.0 |
|
- |
ns |
TAS |
Address setup time before WE |
16x2 |
2.0 |
|
- |
2.0 |
|
- |
ns |
|
TAST |
|
|
32x1 |
2.0 |
|
- |
2.0 |
|
- |
ns |
TAH |
Address hold time after end of WE |
16x2 |
2.0 |
|
- |
2.5 |
|
- |
ns |
|
TAHT |
|
|
32x1 |
2.0 |
|
- |
2.0 |
|
- |
ns |
TDS |
DIN setup time before end of WE |
16x2 |
2.2 |
|
- |
4.0 |
|
- |
ns |
|
TDST |
|
|
32x1 |
2.2 |
|
- |
5.0 |
|
- |
ns |
TDH |
DIN hold time after end of WE |
16x2 |
2.0 |
|
- |
2.0 |
|
- |
ns |
|
TDHT |
|
|
32x1 |
2.0 |
|
- |
2.0 |
|
- |
ns |
Read Operation |
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||
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|
|
TRC |
Address read cycle time |
16x2 |
3.1 |
|
- |
4.5 |
|
- |
ns |
|
TRCT |
|
|
32x1 |
5.5 |
|
- |
6.5 |
|
- |
ns |
TILO |
Data valid after address change (no Write Enable) |
16x2 |
- |
|
1.8 |
- |
|
2.7 |
ns |
|
TIHO |
|
|
32x1 |
- |
|
3.2 |
- |
|
4.7 |
ns |
Read Operation, Clocking Data into Flip-Flop |
|
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||
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|
|
TICK |
Address setup time before clock K |
16x2 |
3.0 |
|
- |
4.0 |
|
- |
ns |
|
TIHCK |
|
|
32x1 |
4.6 |
|
- |
6.1 |
|
- |
ns |
Read During Write |
|
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||
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|
|
TWO |
Data valid after WE goes active (DIN stable before WE) |
16x2 |
- |
|
6.0 |
- |
|
10.0 |
ns |
|
TWOT |
|
|
32x1 |
- |
|
7.3 |
- |
|
12.0 |
ns |
TDO |
Data valid after DIN (DIN changes during WE) |
16x2 |
- |
|
6.6 |
- |
|
9.0 |
ns |
|
TDOT |
|
|
32x1 |
- |
|
7.6 |
- |
|
11.0 |
ns |
Read During Write, Clocking Data into Flip-Flop |
|
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||
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|
TWCK |
WE setup time before clock K |
16x2 |
6.0 |
|
- |
8.0 |
|
- |
ns |
|
TWCKT |
|
|
32x1 |
6.8 |
|
- |
9.6 |
|
- |
ns |
TDCK |
Data setup time before clock K |
16x2 |
5.2 |
|
- |
7.0 |
|
- |
ns |
|
TDOCK |
|
|
32x1 |
6.2 |
|
- |
8.0 |
|
- |
ns |
Notes: |
|
|
|
|
|
|
|
|
|
|
1.Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
DS021 (v2.2) June 25, 2000 |
www.xilinx.com |
11 |
Product Specification |
1-800-255-7778 |
|