R
XCR3512XL: 512 Macrocell CPLD
DS081 (v1.3) January 8, 2002
Features
•Lowest power 512 macrocell CPLD
•7.5 ns pin-to-pin logic delays
•System frequencies up to 127 MHz
•512 macrocells with 12,000 usable gates
•Available in small footprint packages
-208-pin PQFP (180 user I/O)
-256-ball FBGA (212 user I/O)
-324-ball FBGA (260 user I/O)
•Optimized for 3.3V systems
-Ultra low power operation
-5V tolerant I/O pins with 3.3V core supply
-Advanced 0.35 micron five layer metal EEPROM process
-Fast Zero Power™ (FZP) CMOS design technology
•Advanced system features
-In-system programming
-Input registers
-Predictable timing model
-Up to 23 clocks available per function block
-Excellent pin retention during design changes
-Full IEEE Standard 1149.1 boundary-scan (JTAG)
-Four global clocks
-Eight product term control terms per function block
•Fast ISP programming times
•Port Enable pin for additional I/O
•2.7V to 3.6V supply voltage at industrial grade voltage range
•Programmable slew rate control per output
•Security bit prevents unauthorized access
•Refer to XPLA3 family data sheet (DS012) for architecture description
Advance Product Specification
Description
The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 32 function blocks provide 12,000 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 127 MHz.
TotalCMOS Design Technique for Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3512XL TotalCMOS CPLD (data taken with 32 resetable up/down, 16-bit counters at 3.3V, 25°C).
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120 |
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(mA)ICC |
100 |
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80 |
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Typical |
60 |
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40 |
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20
0
0 |
20 |
40 |
60 |
80 |
100 |
120 |
140 |
160 |
Frequency (MHz)
DS024_01_112700
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Figure 1: XCR3512XL Typical ICC vs. Frequency at |
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VCC = 3.3V, 25° C |
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Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25° C |
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Frequency (MHz) |
0 |
1 |
10 |
20 |
40 |
60 |
80 |
100 |
120 |
140 |
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Typical ICC (mA) |
TBD |
TBD |
TBD |
TBD |
TBD |
TBD |
TBD |
TBD |
TBD |
TBD |
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© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS081 (v1.3) January 8, 2002 |
www.xilinx.com |
1 |
Advance Product Specification |
1-800-255-7778 |
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XCR3512XL: 512 Macrocell CPLD
R
DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol |
Parameter |
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Test Conditions |
Min. |
Max. |
Unit |
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VOH(2) |
Output High voltage |
VCC = 3.0V to 3.6V, IOH = –8 mA |
2.4 |
- |
V |
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V |
CC |
= 2.7V to 3.0V, I = –8 mA |
2.0(3) |
- |
V |
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OH |
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IOH = –500 A |
90% VCC |
- |
V |
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VOL |
Output Low voltage |
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IOL = 8 mA |
- |
0.4 |
V |
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IIL |
Input leakage current |
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VIN = GND or VCC |
–10 |
10 |
A |
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IIH |
I/O High-Z leakage current |
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VIN = GND or VCC |
–10 |
10 |
A |
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ICCSB |
Standby current |
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VCC = 3.6V |
- |
100 |
A |
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I |
Dynamic current(4,5) |
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f = 1 MHz |
- |
TBD |
mA |
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CC |
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f = 50 MHz |
- |
TBD |
mA |
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CIN |
Input pin capacitance(6) |
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f = 1 MHz |
- |
8 |
pF |
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CCLK |
Clock input capacitance(6) |
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f = 1 MHz |
5 |
12 |
pF |
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CI/O |
I/O pin capacitance(6) |
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f = 1 MHz |
- |
10 |
pF |
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Notes:
1.See XPLA3 family data sheet (DS012) for recommended operating conditions
2.See Figure 2 for output drive characteristics of the XPLA3 family.
3.This parameter guaranteed by design and characterization, not by testing.
4.See Table 1, Figure 1 for typical values.
5.This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
6.Typical values, not tested.
2 |
www.xilinx.com |
DS081 (v1.3) January 8, 2002 |
|
1-800-255-7778 |
Advance Product Specification |
R
XCR3512XL: 512 Macrocell CPLD
mA
100
90
OL (3.3V)
80
70
60
50
OH (3.3V)
40
30
OH (2.7V)
20
10
0
0 |
0.5 |
1 |
1.5 |
2 |
2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
Volts
DS012_10_041901
Figure 2: Typical I/V Curve for the XPLA3 Family
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
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-10 |
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-12 |
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Symbol |
Parameter |
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Unit |
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Min. |
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Max. |
Min. |
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Max. |
Min. |
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Max. |
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TPD1 |
Propagation delay time (single p-term) |
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- |
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9.0 |
- |
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10.8 |
ns |
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T |
PD2 |
Propagation delay time (OR array)(3) |
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- |
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10.0 |
- |
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12.0 |
ns |
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TCO |
Clock to output (global synchronous pin clock) |
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- |
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5.8 |
- |
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6.9 |
ns |
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TSUF |
Setup time (fast input register) |
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3.5 |
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- |
3.5 |
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- |
ns |
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TSU1(4) |
Setup time (single p-term) |
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5.5 |
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- |
6.7 |
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- |
ns |
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TSU2 |
Setup time (OR array) |
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6.5 |
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- |
7.9 |
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- |
ns |
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T |
(4) |
Hold time |
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0 |
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- |
0 |
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- |
ns |
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H |
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TWLH(4) |
Global Clock pulse width (High or Low) |
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4.0 |
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- |
5.0 |
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- |
ns |
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TtPLH(4) |
P-term clock pulse width |
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6.0 |
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- |
7.5 |
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- |
ns |
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T |
(4) |
Input rise time |
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- |
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20 |
- |
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20 |
ns |
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R |
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T |
(4) |
Input fall time |
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- |
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20 |
- |
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20 |
ns |
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L |
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fSYSTEM(4) |
Maximum system frequency |
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- |
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97 |
- |
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77 |
MHz |
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T |
(4) |
Configuration time(5) |
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- |
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120 |
- |
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120 |
s |
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CONFIG |
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TINIT(4) |
ISP initialization time |
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- |
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120 |
- |
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120 |
s |
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TPOE(4) |
P-term OE to output enabled |
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- |
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11.0 |
- |
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13.0 |
ns |
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T |
(4) |
P-term OE to output disabled(6) |
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- |
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11.0 |
- |
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13.0 |
ns |
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POD |
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TPCO(4) |
P-term clock to output |
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- |
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10.3 |
- |
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12.4 |
ns |
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TPAO(4) |
P-term set/reset to output valid |
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- |
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11.0 |
- |
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13.0 |
ns |
Notes:
1.Specifications measured with one output switching.
2.See XPLA3 family data sheet (DS012) for recommended operating conditions.
3.See Figure 4 for derating.
4.These parameters guaranteed by design and/or characterization, not testing.
5.Typical current draw during configuration is 12 mA at 3.6V.
6.Output CL = 5 pF.
DS081 (v1.3) January 8, 2002 |
www.xilinx.com |
3 |
Advance Product Specification |
1-800-255-7778 |
|
XCR3512XL: 512 Macrocell CPLD
R
Internal Timing Parameters(1,2)
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-7 |
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-10 |
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-12 |
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Symbol |
Parameter |
Min. |
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Max. |
Min. |
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Max. |
Min. |
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Max. |
Unit |
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Buffer Delays |
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TIN |
Input buffer delay |
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- |
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3.3 |
- |
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4.0 |
ns |
TFIN |
Fast input buffer delay |
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- |
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3.8 |
- |
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3.8 |
ns |
TGCK |
Global clock buffer delay |
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- |
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1.3 |
- |
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1.5 |
ns |
TOUT |
Output buffer delay |
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- |
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3.2 |
- |
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3.8 |
ns |
TEN |
Output buffer enable/disable delay |
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- |
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5.2 |
- |
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6.0 |
ns |
Internal Register and Combinatorial Delays |
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TLDI |
Latch transparent delay |
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- |
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1.6 |
- |
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2.0 |
ns |
TSUI |
Register setup time |
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1.0 |
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- |
1.2 |
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- |
ns |
THI |
Register hold time |
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0.5 |
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- |
0.7 |
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- |
ns |
TECSU |
Register clock enable setup time |
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2.5 |
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- |
3.0 |
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- |
ns |
TECHO |
Register clock enable hold time |
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4.5 |
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- |
5.5 |
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- |
ns |
TCOI |
Register clock to output delay |
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- |
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1.3 |
- |
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1.6 |
ns |
TAOI |
Register async. S/R to output delay |
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- |
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2.0 |
- |
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2.2 |
ns |
TRAI |
Register async. recovery |
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- |
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7.0 |
- |
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8.0 |
ns |
TLOGI1 |
Internal logic delay (single p-term) |
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- |
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2.5 |
- |
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3.0 |
ns |
TLOGI2 |
Internal logic delay (PLA OR term) |
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- |
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3.5 |
- |
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4.2 |
ns |
Feedback Delays |
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TF |
ZIA delay |
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- |
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4.5 |
- |
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6.0 |
ns |
Time Adders |
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TLOGI3 |
Fold-back NAND delay |
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- |
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2.5 |
- |
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3.0 |
ns |
TUDA |
Universal delay |
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- |
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2.8 |
- |
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3.5 |
ns |
TSLEW |
Slew rate limited delay |
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- |
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5.0 |
- |
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6.0 |
ns |
Notes:
1.These parameters guaranteed by design and/or characterization, not testing.
2.See XPLA3 family data sheet (DS012) for timing model.
4 |
www.xilinx.com |
DS081 (v1.3) January 8, 2002 |
|
1-800-255-7778 |
Advance Product Specification |
R
XCR3512XL: 512 Macrocell CPLD
Switching Characteristics
VCC
S1
R1
VIN
VOUT
R2 |
C1 |
S2
Component |
Values |
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R1 |
390Ω |
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R2 |
390Ω |
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C1 |
35 pF |
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Measurement |
S1 |
S2 |
TPOE (High) |
Open |
Closed |
TPOE (Low) |
Closed |
Open |
TP |
Closed |
Closed |
Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH – 300 mV.
DS023_03_102401
Figure 3: AC Load Circuit
(ns)
7.5
7.4
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
6.4
6.3
1 |
2 |
4 |
8 |
16 |
Number of Adjacent Outputs Switching
DS024_04_11800
Figure 4: Derating Curve for TPD2
+3.0V |
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90% |
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10% |
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0V |
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TR |
TL |
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1.5 ns |
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1.5 ns |
Measurements:
All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
DS017_05_042800
Figure 5: Voltage Waveform
DS081 (v1.3) January 8, 2002 |
www.xilinx.com |
5 |
Advance Product Specification |
1-800-255-7778 |
|