XILINX XCR3512XL-7PQ208C, XCR3512XL-7FT324C, XCR3512XL-7FT256C, XCR3512XL-12PQ208I, XCR3512XL-12PQ208C Datasheet

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XCR3512XL: 512 Macrocell CPLD

DS081 (v1.3) January 8, 2002

Features

Lowest power 512 macrocell CPLD

7.5 ns pin-to-pin logic delays

System frequencies up to 127 MHz

512 macrocells with 12,000 usable gates

Available in small footprint packages

-208-pin PQFP (180 user I/O)

-256-ball FBGA (212 user I/O)

-324-ball FBGA (260 user I/O)

Optimized for 3.3V systems

-Ultra low power operation

-5V tolerant I/O pins with 3.3V core supply

-Advanced 0.35 micron five layer metal EEPROM process

-Fast Zero Power™ (FZP) CMOS design technology

Advanced system features

-In-system programming

-Input registers

-Predictable timing model

-Up to 23 clocks available per function block

-Excellent pin retention during design changes

-Full IEEE Standard 1149.1 boundary-scan (JTAG)

-Four global clocks

-Eight product term control terms per function block

Fast ISP programming times

Port Enable pin for additional I/O

2.7V to 3.6V supply voltage at industrial grade voltage range

Programmable slew rate control per output

Security bit prevents unauthorized access

Refer to XPLA3 family data sheet (DS012) for architecture description

Advance Product Specification

Description

The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 32 function blocks provide 12,000 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 127 MHz.

TotalCMOS Design Technique for Fast Zero Power

Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3512XL TotalCMOS CPLD (data taken with 32 resetable up/down, 16-bit counters at 3.3V, 25°C).

 

140

 

120

(mA)ICC

100

80

 

Typical

60

40

 

20

0

0

20

40

60

80

100

120

140

160

Frequency (MHz)

DS024_01_112700

 

 

 

 

 

Figure 1: XCR3512XL Typical ICC vs. Frequency at

 

 

 

 

 

 

 

VCC = 3.3V, 25° C

 

 

Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25° C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Frequency (MHz)

0

1

10

20

40

60

80

100

120

140

 

 

 

 

 

 

 

 

 

 

 

 

 

Typical ICC (mA)

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

 

© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS081 (v1.3) January 8, 2002

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1

Advance Product Specification

1-800-255-7778

 

XCR3512XL: 512 Macrocell CPLD

R

DC Electrical Characteristics Over Recommended Operating Conditions(1)

Symbol

Parameter

 

 

Test Conditions

Min.

Max.

Unit

 

 

 

 

 

 

 

 

VOH(2)

Output High voltage

VCC = 3.0V to 3.6V, IOH = –8 mA

2.4

-

V

 

 

V

CC

= 2.7V to 3.0V, I = –8 mA

2.0(3)

-

V

 

 

 

OH

 

 

 

 

 

 

IOH = –500 A

90% VCC

-

V

VOL

Output Low voltage

 

 

 

IOL = 8 mA

-

0.4

V

IIL

Input leakage current

 

 

 

VIN = GND or VCC

–10

10

A

IIH

I/O High-Z leakage current

 

 

 

VIN = GND or VCC

–10

10

A

ICCSB

Standby current

 

 

 

VCC = 3.6V

-

100

A

I

Dynamic current(4,5)

 

 

 

f = 1 MHz

-

TBD

mA

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

f = 50 MHz

-

TBD

mA

 

 

 

 

 

 

 

 

 

 

CIN

Input pin capacitance(6)

 

 

 

f = 1 MHz

-

8

pF

CCLK

Clock input capacitance(6)

 

 

 

f = 1 MHz

5

12

pF

 

CI/O

I/O pin capacitance(6)

 

 

 

f = 1 MHz

-

10

pF

 

Notes:

1.See XPLA3 family data sheet (DS012) for recommended operating conditions

2.See Figure 2 for output drive characteristics of the XPLA3 family.

3.This parameter guaranteed by design and characterization, not by testing.

4.See Table 1, Figure 1 for typical values.

5.This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.

6.Typical values, not tested.

2

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DS081 (v1.3) January 8, 2002

 

1-800-255-7778

Advance Product Specification

R

XCR3512XL: 512 Macrocell CPLD

mA

100

90

OL (3.3V)

80

70

60

50

OH (3.3V)

40

30

OH (2.7V)

20

10

0

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Volts

DS012_10_041901

Figure 2: Typical I/V Curve for the XPLA3 Family

AC Electrical Characteristics Over Recommended Operating Conditions(1,2)

 

 

 

 

-7

-10

 

 

-12

 

Symbol

Parameter

 

 

 

 

 

 

 

 

 

Unit

Min.

 

Max.

Min.

 

Max.

Min.

 

Max.

TPD1

Propagation delay time (single p-term)

 

 

 

-

 

9.0

-

 

10.8

ns

T

PD2

Propagation delay time (OR array)(3)

 

 

 

-

 

10.0

-

 

12.0

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCO

Clock to output (global synchronous pin clock)

 

 

 

-

 

5.8

-

 

6.9

ns

TSUF

Setup time (fast input register)

 

 

 

3.5

 

-

3.5

 

-

ns

TSU1(4)

Setup time (single p-term)

 

 

 

5.5

 

-

6.7

 

-

ns

TSU2

Setup time (OR array)

 

 

 

6.5

 

-

7.9

 

-

ns

T

(4)

Hold time

 

 

 

0

 

-

0

 

-

ns

 

H

 

 

 

 

 

 

 

 

 

 

 

TWLH(4)

Global Clock pulse width (High or Low)

 

 

 

4.0

 

-

5.0

 

-

ns

TtPLH(4)

P-term clock pulse width

 

 

 

6.0

 

-

7.5

 

-

ns

T

(4)

Input rise time

 

 

 

-

 

20

-

 

20

ns

 

R

 

 

 

 

 

 

 

 

 

 

 

T

(4)

Input fall time

 

 

 

-

 

20

-

 

20

ns

 

L

 

 

 

 

 

 

 

 

 

 

 

fSYSTEM(4)

Maximum system frequency

 

 

 

-

 

97

-

 

77

MHz

T

(4)

Configuration time(5)

 

 

 

-

 

120

-

 

120

s

 

CONFIG

 

 

 

 

 

 

 

 

 

 

 

TINIT(4)

ISP initialization time

 

 

 

-

 

120

-

 

120

s

TPOE(4)

P-term OE to output enabled

 

 

 

-

 

11.0

-

 

13.0

ns

T

(4)

P-term OE to output disabled(6)

 

 

 

-

 

11.0

-

 

13.0

ns

 

POD

 

 

 

 

 

 

 

 

 

 

 

TPCO(4)

P-term clock to output

 

 

 

-

 

10.3

-

 

12.4

ns

TPAO(4)

P-term set/reset to output valid

 

 

 

-

 

11.0

-

 

13.0

ns

Notes:

1.Specifications measured with one output switching.

2.See XPLA3 family data sheet (DS012) for recommended operating conditions.

3.See Figure 4 for derating.

4.These parameters guaranteed by design and/or characterization, not testing.

5.Typical current draw during configuration is 12 mA at 3.6V.

6.Output CL = 5 pF.

DS081 (v1.3) January 8, 2002

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Advance Product Specification

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XCR3512XL: 512 Macrocell CPLD

R

Internal Timing Parameters(1,2)

 

 

 

-7

 

-10

 

-12

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

Min.

 

Max.

Min.

 

Max.

Min.

 

Max.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

Buffer Delays

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TIN

Input buffer delay

 

 

 

-

 

3.3

-

 

4.0

ns

TFIN

Fast input buffer delay

 

 

 

-

 

3.8

-

 

3.8

ns

TGCK

Global clock buffer delay

 

 

 

-

 

1.3

-

 

1.5

ns

TOUT

Output buffer delay

 

 

 

-

 

3.2

-

 

3.8

ns

TEN

Output buffer enable/disable delay

 

 

 

-

 

5.2

-

 

6.0

ns

Internal Register and Combinatorial Delays

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TLDI

Latch transparent delay

 

 

 

-

 

1.6

-

 

2.0

ns

TSUI

Register setup time

 

 

 

1.0

 

-

1.2

 

-

ns

THI

Register hold time

 

 

 

0.5

 

-

0.7

 

-

ns

TECSU

Register clock enable setup time

 

 

 

2.5

 

-

3.0

 

-

ns

TECHO

Register clock enable hold time

 

 

 

4.5

 

-

5.5

 

-

ns

TCOI

Register clock to output delay

 

 

 

-

 

1.3

-

 

1.6

ns

TAOI

Register async. S/R to output delay

 

 

 

-

 

2.0

-

 

2.2

ns

TRAI

Register async. recovery

 

 

 

-

 

7.0

-

 

8.0

ns

TLOGI1

Internal logic delay (single p-term)

 

 

 

-

 

2.5

-

 

3.0

ns

TLOGI2

Internal logic delay (PLA OR term)

 

 

 

-

 

3.5

-

 

4.2

ns

Feedback Delays

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TF

ZIA delay

 

 

 

-

 

4.5

-

 

6.0

ns

Time Adders

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TLOGI3

Fold-back NAND delay

 

 

 

-

 

2.5

-

 

3.0

ns

TUDA

Universal delay

 

 

 

-

 

2.8

-

 

3.5

ns

TSLEW

Slew rate limited delay

 

 

 

-

 

5.0

-

 

6.0

ns

Notes:

1.These parameters guaranteed by design and/or characterization, not testing.

2.See XPLA3 family data sheet (DS012) for timing model.

4

www.xilinx.com

DS081 (v1.3) January 8, 2002

 

1-800-255-7778

Advance Product Specification

XILINX XCR3512XL-7PQ208C, XCR3512XL-7FT324C, XCR3512XL-7FT256C, XCR3512XL-12PQ208I, XCR3512XL-12PQ208C Datasheet

R

XCR3512XL: 512 Macrocell CPLD

Switching Characteristics

VCC

S1

R1

VIN

VOUT

R2

C1

S2

Component

Values

 

 

 

R1

390Ω

R2

390Ω

 

C1

35 pF

 

 

 

Measurement

S1

S2

TPOE (High)

Open

Closed

TPOE (Low)

Closed

Open

TP

Closed

Closed

Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH – 300 mV.

DS023_03_102401

Figure 3: AC Load Circuit

(ns)

7.5

7.4

7.3

7.2

7.1

7.0

6.9

6.8

6.7

6.6

6.5

6.4

6.3

1

2

4

8

16

Number of Adjacent Outputs Switching

DS024_04_11800

Figure 4: Derating Curve for TPD2

+3.0V

 

 

 

 

 

 

 

 

 

 

90%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0V

 

 

 

 

 

 

 

 

TR

TL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.5 ns

 

 

 

1.5 ns

Measurements:

All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.

DS017_05_042800

Figure 5: Voltage Waveform

DS081 (v1.3) January 8, 2002

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Advance Product Specification

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