XILINX XCR3032XL-7VQ44I, XCR3032XL-7VQ44C, XCR3032XL-7PC44I, XCR3032XL-7PC44C, XCR3032XL-7CS48I Datasheet

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XILINX XCR3032XL-7VQ44I, XCR3032XL-7VQ44C, XCR3032XL-7PC44I, XCR3032XL-7PC44C, XCR3032XL-7CS48I Datasheet

R

XCR3032XL 32 Macrocell CPLD

DS023 (v1.5) January 8, 2002

Preliminary Product Specification

 

 

Features

Description

Lowest power 32 macrocell CPLD

5.0 ns pin-to-pin logic delays

System frequencies up to 200 MHz

32 macrocells with 750 usable gates

Available in small footprint packages

-48-ball CS BGA (36 user I/O pins)

-44-pin VQFP (36 user I/O)

-44-pin PLCC (36 user I/O)

Optimized for 3.3V systems

-Ultra-low power operation

-5V tolerant I/O pins with 3.3V core supply

-Advanced 0.35 micron five layer metal EEPROM process

-Fast Zero Power™ (FZP) CMOS design technology

Advanced system features

-In-system programming

-Input registers

-Predictable timing model

-Up to 23 available clocks per function block

-Excellent pin retention during design changes

-Full IEEE Standard 1149.1 boundary-scan (JTAG)

-Four global clocks

-Eight product term control terms per function block

Fast ISP programming times

Port Enable pin for dual function of JTAG ISP pins

2.7V to 3.6V supply voltage at industrial temperature range

Programmable slew rate control per macrocell

Security bit prevents unauthorized access

Refer to XPLA3 family data sheet (DS012) for architecture description

Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)

The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of two function blocks provide 750 usable gates. Pin-to-pin propagation delays are 5.0 ns with a maximum system frequency of 200 MHz.

TotalCMOS Design Technique for Fast Zero Power

Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3032XL TotalCMOS CPLD (data taken with two resetable up/down, 16-bit counters at 3.3V, 25° C).

 

20

(mA)

15

 

CC

 

I

10

Typical

 

 

5

 

0

0 20 40 60 80 100 120 140 160 180 200

Frequency (MHz)

DS023_01_080101

Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C

Frequency (MHz)

0

1

5

10

20

50

100

200

Typical ICC (mA)

0.02

0.13

0.54

1.06

2.09

5.2

10.26

20.3

© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS023 (v1.5) January 8, 2002

www.xilinx.com

1

Preliminary Product Specification

1-800-255-7778

 

XCR3032XL 32 Macrocell CPLD

R

DC Electrical Characteristics Over Recommended Operating Conditions(1)

Symbol

Parameter

 

 

Test Conditions

 

Min.

Max.

Unit

 

 

 

 

 

 

 

 

VOH(2)

Output High voltage

VCC = 3.0V to 3.6V, IOH = –8 mA

 

2.4

-

V

 

 

 

V

CC

= 2.7V to 3.0V, I = –8 mA

 

2.0(3)

-

V

 

 

 

 

OH

 

 

 

 

 

 

 

 

 

 

IOH = –500 A

 

 

 

90% VCC

-

V

VOL

Output Low voltage

 

 

 

IOL = 8 mA

 

-

0.4

V

I

(4)

Input leakage current

 

 

 

V

IN

= GND or V

CC

–10

10

A

IL

 

 

 

 

 

 

 

 

 

 

 

I

(4)

I/O High-Z leakage current

 

 

 

V

IN

= GND or V

CC

–10

10

A

IH

 

 

 

 

 

 

 

 

 

 

ICCSB

Standby current

 

 

 

VCC = 3.6V

 

-

100

A

I

 

Dynamic current(5,6)

 

 

 

f = 1 MHz

 

-

0.25

mA

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

f = 50 MHz

 

-

7.5

mA

 

 

 

 

 

 

 

 

 

 

 

CIN

Input pin capacitance(7)

 

 

 

f = 1 MHz

 

-

8

pF

CCLK

Clock input capacitance(7)

 

 

 

f = 1 MHz

 

-

12

pF

 

CI/O

I/O pin capacitance(7)

 

 

 

f = 1 MHz

 

-

10

pF

 

Notes:

1.See XPLA3 family data sheet (DS012) for recommended operating conditions

2.See Figure 2 for output drive characteristics of the XPLA3 family.

3.This parameter guaranteed by design and characterization, not by testing.

4.Typical leakage current is less than 1 A.

5.See Table 1, Figure 1 for typical values.

6.This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.

7.Typical values, not tested.

mA

100

90

IOL (3.3V)

80

70

60

50

IOH (3.3V)

40

30

IOH (2.7V)

20

10

0

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Volts

DS012_10_041901

Figure 2: Typical I/V Curve for the XPLA3 Family

2

www.xilinx.com

DS023 (v1.5) January 8, 2002

 

1-800-255-7778

Preliminary Product Specification

R

XCR3032XL 32 Macrocell CPLD

AC Electrical Characteristics Over Recommended Operating Conditions(1,2)

 

 

 

-5

 

-7

 

 

-10

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

Min.

 

Max.

Min.

 

Max.

Min.

 

Max.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

TPD1

Propagation delay time (single p-term)

 

 

4.5

-

 

7.0

-

 

9.1

ns

T

PD2

Propagation delay time (OR array)(3)

 

 

5.0

-

 

7.5

-

 

10.0

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCO

Clock to output (global synchronous pin clock)

 

 

3.5

 

 

5.0

-

 

6.5

ns

TSUF

Setup time (fast input register)

2.5

 

-

3.0

 

-

3.0

 

-

ns

TSU1(4)

Setup time (single p-term)

3.0

 

-

4.3

 

-

5.4

 

-

ns

TSU2

Setup time (OR array)

3.5

 

-

4.8

 

-

6.3

 

-

ns

T

(4)

Hold time

0

 

-

0

 

-

0

 

-

ns

 

H

 

 

 

 

 

 

 

 

 

 

 

TWLH(4)

Global Clock pulse width (High or Low)

2.5

 

-

3.0

 

-

4.0

 

-

ns

TPLH(4)

P-term clock pulse width

4.0

 

-

5.0

 

-

6.0

 

-

ns

T

(4)

Input rise time

-

 

20

-

 

20

-

 

20

ns

 

R

 

 

 

 

 

 

 

 

 

 

 

T

(4)

Input fall time

-

 

20

-

 

20

-

 

20

ns

 

L

 

 

 

 

 

 

 

 

 

 

 

fSYSTEM(4)

Maximum system frequency

-

 

200

-

 

119

-

 

95

MHz

T

(4)

Configuration time(5)

-

 

30

-

 

30

-

 

30

s

 

CONFIG

 

 

 

 

 

 

 

 

 

 

 

TINIT(4)

ISP initialization time

-

 

30

-

 

30

-

 

30

s

TPOE(4)

P-term OE to output enabled

-

 

7.2

-

 

9.3

-

 

11.2

ns

T

(4)

P-term OE to output disabled(6)

-

 

7.2

-

 

9.3

-

 

11.2

ns

 

POD

 

 

 

 

 

 

 

 

 

 

 

TPCO(4)

P-term clock to output

-

 

5.5

-

 

8.3

-

 

10.7

ns

TPAO(4)

P-term set/reset to output valid

-

 

6.5

-

 

9.3

-

 

11.2

ns

Notes:

1.Specifications measured with one output switching.

2.See XPLA3 family data sheet (DS012) for recommended operating conditions.

3.See Figure 4 for derating.

4.These parameters guaranteed by design and/or characterization, not testing.

5.Typical current draw during configuration is 3 mA at 3.6V.

6.Output CL = 5 pF.

DS023 (v1.5) January 8, 2002

www.xilinx.com

3

Preliminary Product Specification

1-800-255-7778

 

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