XILINX XC9572XV-5PC44C, XC9572XV-5CS48C, XC9572XV-4VQ44C, XC9572XV-4TQ100C, XC9572XV-4PC44C Datasheet

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XC9572XV High-performance

CPLD

DS052 (v2.2) August 27, 2001

Advance Product Specification

 

 

Features

72 macrocells with 1,600 usable gates

Available in small footprint packages

-44-pin PLCC (34 user I/O pins)

-44-pin VQFP (34 user I/O pins)

-48-pin CSP (38 user I/O pins)

-100-pin TQFP (72-user I/O pins)

Optimized for high-performance 2.5V systems

-Low power operation

-Multi-voltage operation

Advanced system features

-In-system programmable

-Two separate output banks

-Superior pin-locking and routability with FastCONNECT II™ switch matrix

-Extra wide 54-input Function Blocks

-Up to 90 product-terms per macrocell with individual product-term allocation

-Local clock inversion with three global and one product-term clocks

-Individual output enable per output pin

-Input hysteresis on all user and boundary-scan pin inputs

-Bus-hold ciruitry on all user pin inputs

-Full IEEE Standard 1149.1 boundary-scan (JTAG)

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

-Endurance exceeding 10,000 program/erase cycles

-20 year data retention

-ESD protection exceeding 2,000V

Description

The XC9572XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communications and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 4 ns.

Power Estimation

Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.

For a general estimate of ICC, the following equation may be used:

ICC (mA) =

MCHP(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f

Where:

MCHP = Macrocells in high-performance (default) mode

MCLP = Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation.

Figure 1 shows the above estimation in a graphical form.

 

90

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

70

 

 

 

 

 

 

 

 

 

 

(mA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50

 

 

Performance

 

 

 

 

 

 

CC

 

 

 

 

 

 

 

 

 

High

 

 

 

 

 

 

I

 

 

 

wPower

 

 

 

 

 

 

Typical

30

 

 

 

 

 

 

 

 

 

 

Lo

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

50

100

150

200

 

 

 

 

Clock Frequency (MHz)

 

 

DS052_01_012501

Figure 1: Typical ICC vs. Frequency for XC9572XV

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS052 (v2.2) August 27, 2001

www.xilinx.com

1

Advance Product Specification

1-800-255-7778

 

XILINX XC9572XV-5PC44C, XC9572XV-5CS48C, XC9572XV-4VQ44C, XC9572XV-4TQ100C, XC9572XV-4PC44C Datasheet

XC9572XV High-performance CPLD

R

 

 

3

 

JTAG Port

1

JTAG

In-System Programming Controller

Controller

 

 

 

 

 

 

54

 

 

18

Function

I/O

 

Block 1

I/O

 

 

Macrocells

 

 

1 to 18

 

 

 

I/O

Matrix

 

 

 

18

Block 2

I/O

 

 

54

 

 

Function

 

SwitchII

 

Blocks

 

Macrocells

 

 

 

I/O

FastCONNECT

 

1 to 18

I/O

 

1 to 18

 

 

 

54

I/O

 

18

Function

 

 

Block 3

I/O

 

 

Macrocells

I/O

 

 

 

3

 

 

 

I/O/GCK

 

 

54

1

 

18

Function

 

Block 4

I/O/GSR

 

2

 

 

Macrocells

I/O/GTS

 

 

1 to 18

DS052_02_041200

Figure 2: XC9572XV Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

2

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DS052 (v2.2) August 27, 2001

 

1-800-255-7778

Advance Product Specification

R

XC9572XV High-performance CPLD

Absolute Maximum Ratings

Symbol

Description

Value

Units

 

 

 

 

VCC

Supply voltage relative to GND

–0.5 to 2.7

V

VCCIO

Supply voltage for output drivers

–0.5 to 3.6

V

VIN

Input voltage relative to GND(1)

–0.5 to 3.6

V

VTS

Voltage applied to 3-state output(1)

–0.5 to 3.6

V

T

Storage temperature (ambient)

–65 to +150

oC

STG

 

 

 

T

Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)

+260

oC

SOL

 

 

 

T

Junction temperature

+150

oC

J

 

 

 

Notes:

1.Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0V or overshoot to +3.6V, provided this overor undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.

2.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol

Parameter

Min

Max

Units

 

 

 

 

 

 

 

V

CCINT

Supply voltage for internal logic

Commercial T = 0oC to +70oC

2.37

2.62

V

 

and input buffers

A

 

 

 

 

 

Industrial T = –40oC to +85oC

2.37

2.62

 

 

 

 

 

 

 

 

A

 

 

 

VCCIO

Supply voltage for output drivers for 3.3V operation

3.13

3.46

V

 

 

Supply voltage for output drivers for 2.5V operation

2.37

2.62

V

 

 

 

 

 

 

 

 

Supply voltage for output drivers for 1.8V operation

1.71

1.89

V

 

 

 

 

 

 

 

 

VIL

Low-level input voltage

 

0

0.8

V

 

VIH

High-level input voltage

 

1.7

3.6

V

 

VO

Output voltage

 

0

VCCIO

V

Quality and Reliability Characteristics

Symbol

Parameter

Min

Max

Units

 

 

 

 

 

TDR

Data retention

20

-

Years

NPE

Program/Erase cycles (endurance)

10,000

-

Cycles

VESD

Electrostatic Discharge (ESD)

2,000

-

Volts

DS052 (v2.2) August 27, 2001

www.xilinx.com

3

Advance Product Specification

1-800-255-7778

 

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